My Project
Loading...
Searching...
No Matches
stm32f3xx_hal.h
Go to the documentation of this file.
1
20/* Define to prevent recursive inclusion -------------------------------------*/
21#ifndef __STM32F3xx_HAL_H
22#define __STM32F3xx_HAL_H
23
24#ifdef __cplusplus
25 extern "C" {
26#endif
27
28/* Includes ------------------------------------------------------------------*/
29#include "stm32f3xx_hal_conf.h"
30
39/* Private macros ------------------------------------------------------------*/
43#define IS_SYSCFG_FASTMODEPLUS(__PIN__) ((((__PIN__) & SYSCFG_FASTMODEPLUS_PB6) == SYSCFG_FASTMODEPLUS_PB6) || \
44 (((__PIN__) & SYSCFG_FASTMODEPLUS_PB7) == SYSCFG_FASTMODEPLUS_PB7) || \
45 (((__PIN__) & SYSCFG_FASTMODEPLUS_PB8) == SYSCFG_FASTMODEPLUS_PB8) || \
46 (((__PIN__) & SYSCFG_FASTMODEPLUS_PB9) == SYSCFG_FASTMODEPLUS_PB9))
51/* Exported types ------------------------------------------------------------*/
52/* Exported constants --------------------------------------------------------*/
60typedef enum
61{
62 HAL_TICK_FREQ_10HZ = 100U,
63 HAL_TICK_FREQ_100HZ = 10U,
64 HAL_TICK_FREQ_1KHZ = 1U,
65 HAL_TICK_FREQ_DEFAULT = HAL_TICK_FREQ_1KHZ
66} HAL_TickFreqTypeDef;
81/* ------------ SYSCFG registers bit address in the alias region -------------*/
82#define SYSCFG_OFFSET (SYSCFG_BASE - PERIPH_BASE)
83/* --- CFGR2 Register ---*/
84/* Alias word address of BYP_ADDR_PAR bit */
85#define CFGR2_OFFSET (SYSCFG_OFFSET + 0x18U)
86#define BYPADDRPAR_BitNumber 0x04U
87#define CFGR2_BYPADDRPAR_BB (PERIPH_BB_BASE + (CFGR2_OFFSET * 32U) + (BYPADDRPAR_BitNumber * 4U))
92#if defined(SYSCFG_CFGR1_DMA_RMP)
101#define HAL_REMAPDMA_ADC24_DMA2_CH34 (0x00000100U)
103#define HAL_REMAPDMA_TIM16_DMA1_CH6 (0x00000800U)
105#define HAL_REMAPDMA_TIM17_DMA1_CH7 (0x00001000U)
107#define HAL_REMAPDMA_TIM6_DAC1_CH1_DMA1_CH3 (0x00002000U)
109#define HAL_REMAPDMA_TIM7_DAC1_CH2_DMA1_CH4 (0x00004000U)
111#define HAL_REMAPDMA_DAC2_CH1_DMA1_CH5 (0x00008000U)
113#define HAL_REMAPDMA_TIM18_DAC2_CH1_DMA1_CH5 (0x00008000U)
115#if defined(SYSCFG_CFGR3_DMA_RMP)
116#if !defined(HAL_REMAP_CFGR3_MASK)
117#define HAL_REMAP_CFGR3_MASK (0x01000000U)
118#endif
119
120#define HAL_REMAPDMA_SPI1_RX_DMA1_CH2 (0x01000003U)
122#define HAL_REMAPDMA_SPI1_RX_DMA1_CH4 (0x01000001U)
124#define HAL_REMAPDMA_SPI1_RX_DMA1_CH6 (0x01000002U)
126#define HAL_REMAPDMA_SPI1_TX_DMA1_CH3 (0x0100000CU)
128#define HAL_REMAPDMA_SPI1_TX_DMA1_CH5 (0x01000004U)
130#define HAL_REMAPDMA_SPI1_TX_DMA1_CH7 (0x01000008U)
132#define HAL_REMAPDMA_I2C1_RX_DMA1_CH7 (0x01000030U)
134#define HAL_REMAPDMA_I2C1_RX_DMA1_CH3 (0x01000010U)
136#define HAL_REMAPDMA_I2C1_RX_DMA1_CH5 (0x01000020U)
138#define HAL_REMAPDMA_I2C1_TX_DMA1_CH6 (0x010000C0U)
140#define HAL_REMAPDMA_I2C1_TX_DMA1_CH2 (0x01000040U)
142#define HAL_REMAPDMA_I2C1_TX_DMA1_CH4 (0x01000080U)
144#define HAL_REMAPDMA_ADC2_DMA1_CH2 (0x01000100U)
147#define HAL_REMAPDMA_ADC2_DMA1_CH4 (0x01000300U)
149#endif /* SYSCFG_CFGR3_DMA_RMP */
150
151#if defined(SYSCFG_CFGR3_DMA_RMP)
152#define IS_DMA_REMAP(RMP) ((((RMP) & HAL_REMAPDMA_ADC24_DMA2_CH34) == HAL_REMAPDMA_ADC24_DMA2_CH34) || \
153 (((RMP) & HAL_REMAPDMA_TIM16_DMA1_CH6) == HAL_REMAPDMA_TIM16_DMA1_CH6) || \
154 (((RMP) & HAL_REMAPDMA_TIM17_DMA1_CH7) == HAL_REMAPDMA_TIM17_DMA1_CH7) || \
155 (((RMP) & HAL_REMAPDMA_TIM6_DAC1_CH1_DMA1_CH3) == HAL_REMAPDMA_TIM6_DAC1_CH1_DMA1_CH3) || \
156 (((RMP) & HAL_REMAPDMA_TIM7_DAC1_CH2_DMA1_CH4) == HAL_REMAPDMA_TIM7_DAC1_CH2_DMA1_CH4) || \
157 (((RMP) & HAL_REMAPDMA_DAC2_CH1_DMA1_CH5) == HAL_REMAPDMA_DAC2_CH1_DMA1_CH5) || \
158 (((RMP) & HAL_REMAPDMA_TIM18_DAC2_CH1_DMA1_CH5) == HAL_REMAPDMA_TIM18_DAC2_CH1_DMA1_CH5) || \
159 (((RMP) & HAL_REMAPDMA_SPI1_RX_DMA1_CH2) == HAL_REMAPDMA_SPI1_RX_DMA1_CH2) || \
160 (((RMP) & HAL_REMAPDMA_SPI1_RX_DMA1_CH4) == HAL_REMAPDMA_SPI1_RX_DMA1_CH4) || \
161 (((RMP) & HAL_REMAPDMA_SPI1_RX_DMA1_CH6) == HAL_REMAPDMA_SPI1_RX_DMA1_CH6) || \
162 (((RMP) & HAL_REMAPDMA_SPI1_TX_DMA1_CH3) == HAL_REMAPDMA_SPI1_TX_DMA1_CH3) || \
163 (((RMP) & HAL_REMAPDMA_SPI1_TX_DMA1_CH5) == HAL_REMAPDMA_SPI1_TX_DMA1_CH5) || \
164 (((RMP) & HAL_REMAPDMA_SPI1_TX_DMA1_CH7) == HAL_REMAPDMA_SPI1_TX_DMA1_CH7) || \
165 (((RMP) & HAL_REMAPDMA_I2C1_RX_DMA1_CH7) == HAL_REMAPDMA_I2C1_RX_DMA1_CH7) || \
166 (((RMP) & HAL_REMAPDMA_I2C1_RX_DMA1_CH3) == HAL_REMAPDMA_I2C1_RX_DMA1_CH3) || \
167 (((RMP) & HAL_REMAPDMA_I2C1_RX_DMA1_CH5) == HAL_REMAPDMA_I2C1_RX_DMA1_CH5) || \
168 (((RMP) & HAL_REMAPDMA_I2C1_TX_DMA1_CH6) == HAL_REMAPDMA_I2C1_TX_DMA1_CH6) || \
169 (((RMP) & HAL_REMAPDMA_I2C1_TX_DMA1_CH2) == HAL_REMAPDMA_I2C1_TX_DMA1_CH2) || \
170 (((RMP) & HAL_REMAPDMA_I2C1_TX_DMA1_CH4) == HAL_REMAPDMA_I2C1_TX_DMA1_CH4) || \
171 (((RMP) & HAL_REMAPDMA_ADC2_DMA1_CH2) == HAL_REMAPDMA_ADC2_DMA1_CH2) || \
172 (((RMP) & HAL_REMAPDMA_ADC2_DMA1_CH4) == HAL_REMAPDMA_ADC2_DMA1_CH4))
173#else
174#define IS_DMA_REMAP(RMP) ((((RMP) & HAL_REMAPDMA_ADC24_DMA2_CH34) == HAL_REMAPDMA_ADC24_DMA2_CH34) || \
175 (((RMP) & HAL_REMAPDMA_TIM16_DMA1_CH6) == HAL_REMAPDMA_TIM16_DMA1_CH6) || \
176 (((RMP) & HAL_REMAPDMA_TIM17_DMA1_CH7) == HAL_REMAPDMA_TIM17_DMA1_CH7) || \
177 (((RMP) & HAL_REMAPDMA_TIM6_DAC1_CH1_DMA1_CH3) == HAL_REMAPDMA_TIM6_DAC1_CH1_DMA1_CH3) || \
178 (((RMP) & HAL_REMAPDMA_TIM7_DAC1_CH2_DMA1_CH4) == HAL_REMAPDMA_TIM7_DAC1_CH2_DMA1_CH4) || \
179 (((RMP) & HAL_REMAPDMA_DAC2_CH1_DMA1_CH5) == HAL_REMAPDMA_DAC2_CH1_DMA1_CH5) || \
180 (((RMP) & HAL_REMAPDMA_TIM18_DAC2_CH1_DMA1_CH5) == HAL_REMAPDMA_TIM18_DAC2_CH1_DMA1_CH5))
181#endif /* SYSCFG_CFGR3_DMA_RMP && SYSCFG_CFGR1_DMA_RMP*/
185#endif /* SYSCFG_CFGR1_DMA_RMP */
186
195#define HAL_REMAPTRIGGER_DAC1_TRIG (0x00000080U)
198#define HAL_REMAPTRIGGER_TIM1_ITR3 (0x00000040U)
201#if defined(SYSCFG_CFGR3_TRIGGER_RMP)
202#if !defined(HAL_REMAP_CFGR3_MASK)
203#define HAL_REMAP_CFGR3_MASK (0x01000000U)
204#endif
205#define HAL_REMAPTRIGGER_DAC1_TRIG3 (0x01010000U)
208#define HAL_REMAPTRIGGER_DAC1_TRIG5 (0x01020000U)
211#define IS_HAL_REMAPTRIGGER(RMP) ((((RMP) & HAL_REMAPTRIGGER_DAC1) == HAL_REMAPTRIGGER_DAC1) || \
212 (((RMP) & HAL_REMAPTRIGGER_TIM1_ITR3) == HAL_REMAPTRIGGER_TIM1_ITR3) || \
213 (((RMP) & HAL_REMAPTRIGGER_DAC1_TRIG3) == HAL_REMAPTRIGGER_DAC1_TRIG3) || \
214 (((RMP) & HAL_REMAPTRIGGER_DAC1_TRIG5) == HAL_REMAPTRIGGER_DAC1_TRIG5))
215#else
216#define IS_HAL_REMAPTRIGGER(RMP) ((((RMP) & HAL_REMAPTRIGGER_DAC1) == HAL_REMAPTRIGGER_DAC1) || \
217 (((RMP) & HAL_REMAPTRIGGER_TIM1_ITR3) == HAL_REMAPTRIGGER_TIM1_ITR3))
218#endif /* SYSCFG_CFGR3_TRIGGER_RMP */
223#if defined (STM32F302xE)
227#define HAL_REMAPADCTRIGGER_ADC12_EXT2 SYSCFG_CFGR4_ADC12_EXT2_RMP
230#define HAL_REMAPADCTRIGGER_ADC12_EXT3 SYSCFG_CFGR4_ADC12_EXT3_RMP
233#define HAL_REMAPADCTRIGGER_ADC12_EXT5 SYSCFG_CFGR4_ADC12_EXT5_RMP
236#define HAL_REMAPADCTRIGGER_ADC12_EXT13 SYSCFG_CFGR4_ADC12_EXT13_RMP
239#define HAL_REMAPADCTRIGGER_ADC12_EXT15 SYSCFG_CFGR4_ADC12_EXT15_RMP
242#define HAL_REMAPADCTRIGGER_ADC12_JEXT3 SYSCFG_CFGR4_ADC12_JEXT3_RMP
245#define HAL_REMAPADCTRIGGER_ADC12_JEXT6 SYSCFG_CFGR4_ADC12_JEXT6_RMP
248#define HAL_REMAPADCTRIGGER_ADC12_JEXT13 SYSCFG_CFGR4_ADC12_JEXT13_RMP
252#define IS_HAL_REMAPADCTRIGGER(RMP) ((((RMP) & HAL_REMAPADCTRIGGER_ADC12_EXT2) == HAL_REMAPADCTRIGGER_ADC12_EXT2) || \
253 (((RMP) & HAL_REMAPADCTRIGGER_ADC12_EXT3) == HAL_REMAPADCTRIGGER_ADC12_EXT3) || \
254 (((RMP) & HAL_REMAPADCTRIGGER_ADC12_EXT5) == HAL_REMAPADCTRIGGER_ADC12_EXT5) || \
255 (((RMP) & HAL_REMAPADCTRIGGER_ADC12_EXT13) == HAL_REMAPADCTRIGGER_ADC12_EXT13) || \
256 (((RMP) & HAL_REMAPADCTRIGGER_ADC12_EXT15) == HAL_REMAPADCTRIGGER_ADC12_EXT15) || \
257 (((RMP) & HAL_REMAPADCTRIGGER_ADC12_JEXT3) == HAL_REMAPADCTRIGGER_ADC12_JEXT3) || \
258 (((RMP) & HAL_REMAPADCTRIGGER_ADC12_JEXT6) == HAL_REMAPADCTRIGGER_ADC12_JEXT6) || \
259 (((RMP) & HAL_REMAPADCTRIGGER_ADC12_JEXT13) == HAL_REMAPADCTRIGGER_ADC12_JEXT13))
263#endif /* STM32F302xE */
264
265#if defined (STM32F303xE) || defined (STM32F398xx)
269#define HAL_REMAPADCTRIGGER_ADC12_EXT2 SYSCFG_CFGR4_ADC12_EXT2_RMP
272#define HAL_REMAPADCTRIGGER_ADC12_EXT3 SYSCFG_CFGR4_ADC12_EXT3_RMP
275#define HAL_REMAPADCTRIGGER_ADC12_EXT5 SYSCFG_CFGR4_ADC12_EXT5_RMP
278#define HAL_REMAPADCTRIGGER_ADC12_EXT13 SYSCFG_CFGR4_ADC12_EXT13_RMP
281#define HAL_REMAPADCTRIGGER_ADC12_EXT15 SYSCFG_CFGR4_ADC12_EXT15_RMP
284#define HAL_REMAPADCTRIGGER_ADC12_JEXT3 SYSCFG_CFGR4_ADC12_JEXT3_RMP
287#define HAL_REMAPADCTRIGGER_ADC12_JEXT6 SYSCFG_CFGR4_ADC12_JEXT6_RMP
290#define HAL_REMAPADCTRIGGER_ADC12_JEXT13 SYSCFG_CFGR4_ADC12_JEXT13_RMP
293#define HAL_REMAPADCTRIGGER_ADC34_EXT5 SYSCFG_CFGR4_ADC34_EXT5_RMP
296#define HAL_REMAPADCTRIGGER_ADC34_EXT6 SYSCFG_CFGR4_ADC34_EXT6_RMP
299#define HAL_REMAPADCTRIGGER_ADC34_EXT15 SYSCFG_CFGR4_ADC34_EXT15_RMP
302#define HAL_REMAPADCTRIGGER_ADC34_JEXT5 SYSCFG_CFGR4_ADC34_JEXT5_RMP
305#define HAL_REMAPADCTRIGGER_ADC34_JEXT11 SYSCFG_CFGR4_ADC34_JEXT11_RMP
308#define HAL_REMAPADCTRIGGER_ADC34_JEXT14 SYSCFG_CFGR4_ADC34_JEXT14_RMP
312#define IS_HAL_REMAPADCTRIGGER(RMP) ((((RMP) & HAL_REMAPADCTRIGGER_ADC12_EXT2) == HAL_REMAPADCTRIGGER_ADC12_EXT2) || \
313 (((RMP) & HAL_REMAPADCTRIGGER_ADC12_EXT3) == HAL_REMAPADCTRIGGER_ADC12_EXT3) || \
314 (((RMP) & HAL_REMAPADCTRIGGER_ADC12_EXT5) == HAL_REMAPADCTRIGGER_ADC12_EXT5) || \
315 (((RMP) & HAL_REMAPADCTRIGGER_ADC12_EXT13) == HAL_REMAPADCTRIGGER_ADC12_EXT13) || \
316 (((RMP) & HAL_REMAPADCTRIGGER_ADC12_EXT15) == HAL_REMAPADCTRIGGER_ADC12_EXT15) || \
317 (((RMP) & HAL_REMAPADCTRIGGER_ADC12_JEXT3) == HAL_REMAPADCTRIGGER_ADC12_JEXT3) || \
318 (((RMP) & HAL_REMAPADCTRIGGER_ADC12_JEXT6) == HAL_REMAPADCTRIGGER_ADC12_JEXT6) || \
319 (((RMP) & HAL_REMAPADCTRIGGER_ADC12_JEXT13) == HAL_REMAPADCTRIGGER_ADC12_JEXT13) || \
320 (((RMP) & HAL_REMAPADCTRIGGER_ADC34_EXT5) == HAL_REMAPADCTRIGGER_ADC34_EXT5) || \
321 (((RMP) & HAL_REMAPADCTRIGGER_ADC34_EXT6) == HAL_REMAPADCTRIGGER_ADC34_EXT6) || \
322 (((RMP) & HAL_REMAPADCTRIGGER_ADC34_EXT15) == HAL_REMAPADCTRIGGER_ADC34_EXT15) || \
323 (((RMP) & HAL_REMAPADCTRIGGER_ADC34_JEXT5) == HAL_REMAPADCTRIGGER_ADC34_JEXT5) || \
324 (((RMP) & HAL_REMAPADCTRIGGER_ADC34_JEXT11) == HAL_REMAPADCTRIGGER_ADC34_JEXT11) || \
325 (((RMP) & HAL_REMAPADCTRIGGER_ADC34_JEXT14) == HAL_REMAPADCTRIGGER_ADC34_JEXT14))
329#endif /* STM32F303xE || STM32F398xx */
330
337#if defined(SYSCFG_CFGR1_I2C_PB6_FMP)
338#define SYSCFG_FASTMODEPLUS_PB6 ((uint32_t)SYSCFG_CFGR1_I2C_PB6_FMP)
339#endif /* SYSCFG_CFGR1_I2C_PB6_FMP */
340
341#if defined(SYSCFG_CFGR1_I2C_PB7_FMP)
342#define SYSCFG_FASTMODEPLUS_PB7 ((uint32_t)SYSCFG_CFGR1_I2C_PB7_FMP)
343#endif /* SYSCFG_CFGR1_I2C_PB7_FMP */
344
345#if defined(SYSCFG_CFGR1_I2C_PB8_FMP)
346#define SYSCFG_FASTMODEPLUS_PB8 ((uint32_t)SYSCFG_CFGR1_I2C_PB8_FMP)
347#endif /* SYSCFG_CFGR1_I2C_PB8_FMP */
348
349#if defined(SYSCFG_CFGR1_I2C_PB9_FMP)
350#define SYSCFG_FASTMODEPLUS_PB9 ((uint32_t)SYSCFG_CFGR1_I2C_PB9_FMP)
351#endif /* SYSCFG_CFGR1_I2C_PB9_FMP */
356#if defined(SYSCFG_RCR_PAGE0)
357/* CCM-SRAM defined */
361#define HAL_SYSCFG_WP_PAGE0 (SYSCFG_RCR_PAGE0)
362#define HAL_SYSCFG_WP_PAGE1 (SYSCFG_RCR_PAGE1)
363#define HAL_SYSCFG_WP_PAGE2 (SYSCFG_RCR_PAGE2)
364#define HAL_SYSCFG_WP_PAGE3 (SYSCFG_RCR_PAGE3)
365#if defined(SYSCFG_RCR_PAGE4)
366/* More than 4KB CCM-SRAM defined */
367#define HAL_SYSCFG_WP_PAGE4 (SYSCFG_RCR_PAGE4)
368#define HAL_SYSCFG_WP_PAGE5 (SYSCFG_RCR_PAGE5)
369#define HAL_SYSCFG_WP_PAGE6 (SYSCFG_RCR_PAGE6)
370#define HAL_SYSCFG_WP_PAGE7 (SYSCFG_RCR_PAGE7)
371#endif /* SYSCFG_RCR_PAGE4 */
372#if defined(SYSCFG_RCR_PAGE8)
373#define HAL_SYSCFG_WP_PAGE8 (SYSCFG_RCR_PAGE8)
374#define HAL_SYSCFG_WP_PAGE9 (SYSCFG_RCR_PAGE9)
375#define HAL_SYSCFG_WP_PAGE10 (SYSCFG_RCR_PAGE10)
376#define HAL_SYSCFG_WP_PAGE11 (SYSCFG_RCR_PAGE11)
377#define HAL_SYSCFG_WP_PAGE12 (SYSCFG_RCR_PAGE12)
378#define HAL_SYSCFG_WP_PAGE13 (SYSCFG_RCR_PAGE13)
379#define HAL_SYSCFG_WP_PAGE14 (SYSCFG_RCR_PAGE14)
380#define HAL_SYSCFG_WP_PAGE15 (SYSCFG_RCR_PAGE15)
381#endif /* SYSCFG_RCR_PAGE8 */
382
383#if defined(SYSCFG_RCR_PAGE8)
384#define IS_HAL_SYSCFG_WP_PAGE(__PAGE__) (((__PAGE__) > 0U) && ((__PAGE__) <= 0xFFFFU))
385#elif defined(SYSCFG_RCR_PAGE4)
386#define IS_HAL_SYSCFG_WP_PAGE(__PAGE__) (((__PAGE__) > 0U) && ((__PAGE__) <= 0x00FFU))
387#else
388#define IS_HAL_SYSCFG_WP_PAGE(__PAGE__) (((__PAGE__) > 0U) && ((__PAGE__) <= 0x000FU))
389#endif /* SYSCFG_RCR_PAGE8 */
393#endif /* SYSCFG_RCR_PAGE0 */
394
398#define HAL_SYSCFG_IT_FPU_IOC (SYSCFG_CFGR1_FPU_IE_0)
399#define HAL_SYSCFG_IT_FPU_DZC (SYSCFG_CFGR1_FPU_IE_1)
400#define HAL_SYSCFG_IT_FPU_UFC (SYSCFG_CFGR1_FPU_IE_2)
401#define HAL_SYSCFG_IT_FPU_OFC (SYSCFG_CFGR1_FPU_IE_3)
402#define HAL_SYSCFG_IT_FPU_IDC (SYSCFG_CFGR1_FPU_IE_4)
403#define HAL_SYSCFG_IT_FPU_IXC (SYSCFG_CFGR1_FPU_IE_5)
405#define IS_HAL_SYSCFG_INTERRUPT(__INTERRUPT__) ((((__INTERRUPT__) & SYSCFG_CFGR1_FPU_IE_0) == SYSCFG_CFGR1_FPU_IE_0) || \
406 (((__INTERRUPT__) & SYSCFG_CFGR1_FPU_IE_1) == SYSCFG_CFGR1_FPU_IE_1) || \
407 (((__INTERRUPT__) & SYSCFG_CFGR1_FPU_IE_2) == SYSCFG_CFGR1_FPU_IE_2) || \
408 (((__INTERRUPT__) & SYSCFG_CFGR1_FPU_IE_3) == SYSCFG_CFGR1_FPU_IE_3) || \
409 (((__INTERRUPT__) & SYSCFG_CFGR1_FPU_IE_4) == SYSCFG_CFGR1_FPU_IE_4) || \
410 (((__INTERRUPT__) & SYSCFG_CFGR1_FPU_IE_5) == SYSCFG_CFGR1_FPU_IE_5))
411
420/* Exported macros -----------------------------------------------------------*/
428#if defined(DBGMCU_APB1_FZ_DBG_TIM2_STOP)
429#define __HAL_DBGMCU_FREEZE_TIM2() (DBGMCU->APB1FZ |= (DBGMCU_APB1_FZ_DBG_TIM2_STOP))
430#define __HAL_DBGMCU_UNFREEZE_TIM2() (DBGMCU->APB1FZ &= ~(DBGMCU_APB1_FZ_DBG_TIM2_STOP))
431#endif /* DBGMCU_APB1_FZ_DBG_TIM2_STOP */
432
433#if defined(DBGMCU_APB1_FZ_DBG_TIM3_STOP)
434#define __HAL_DBGMCU_FREEZE_TIM3() (DBGMCU->APB1FZ |= (DBGMCU_APB1_FZ_DBG_TIM3_STOP))
435#define __HAL_DBGMCU_UNFREEZE_TIM3() (DBGMCU->APB1FZ &= ~(DBGMCU_APB1_FZ_DBG_TIM3_STOP))
436#endif /* DBGMCU_APB1_FZ_DBG_TIM3_STOP */
437
438#if defined(DBGMCU_APB1_FZ_DBG_TIM4_STOP)
439#define __HAL_DBGMCU_FREEZE_TIM4() (DBGMCU->APB1FZ |= (DBGMCU_APB1_FZ_DBG_TIM4_STOP))
440#define __HAL_DBGMCU_UNFREEZE_TIM4() (DBGMCU->APB1FZ &= ~(DBGMCU_APB1_FZ_DBG_TIM4_STOP))
441#endif /* DBGMCU_APB1_FZ_DBG_TIM4_STOP */
442
443#if defined(DBGMCU_APB1_FZ_DBG_TIM5_STOP)
444#define __HAL_DBGMCU_FREEZE_TIM5() (DBGMCU->APB1FZ |= (DBGMCU_APB1_FZ_DBG_TIM5_STOP))
445#define __HAL_DBGMCU_UNFREEZE_TIM5() (DBGMCU->APB1FZ &= ~(DBGMCU_APB1_FZ_DBG_TIM5_STOP))
446#endif /* DBGMCU_APB1_FZ_DBG_TIM5_STOP */
447
448#if defined(DBGMCU_APB1_FZ_DBG_TIM6_STOP)
449#define __HAL_DBGMCU_FREEZE_TIM6() (DBGMCU->APB1FZ |= (DBGMCU_APB1_FZ_DBG_TIM6_STOP))
450#define __HAL_DBGMCU_UNFREEZE_TIM6() (DBGMCU->APB1FZ &= ~(DBGMCU_APB1_FZ_DBG_TIM6_STOP))
451#endif /* DBGMCU_APB1_FZ_DBG_TIM6_STOP */
452
453#if defined(DBGMCU_APB1_FZ_DBG_TIM7_STOP)
454#define __HAL_DBGMCU_FREEZE_TIM7() (DBGMCU->APB1FZ |= (DBGMCU_APB1_FZ_DBG_TIM7_STOP))
455#define __HAL_DBGMCU_UNFREEZE_TIM7() (DBGMCU->APB1FZ &= ~(DBGMCU_APB1_FZ_DBG_TIM7_STOP))
456#endif /* DBGMCU_APB1_FZ_DBG_TIM7_STOP */
457
458#if defined(DBGMCU_APB1_FZ_DBG_TIM12_STOP)
459#define __HAL_DBGMCU_FREEZE_TIM12() (DBGMCU->APB1FZ |= (DBGMCU_APB1_FZ_DBG_TIM12_STOP))
460#define __HAL_DBGMCU_UNFREEZE_TIM12() (DBGMCU->APB1FZ &= ~(DBGMCU_APB1_FZ_DBG_TIM12_STOP))
461#endif /* DBGMCU_APB1_FZ_DBG_TIM12_STOP */
462
463#if defined(DBGMCU_APB1_FZ_DBG_TIM13_STOP)
464#define __HAL_DBGMCU_FREEZE_TIM13() (DBGMCU->APB1FZ |= (DBGMCU_APB1_FZ_DBG_TIM13_STOP))
465#define __HAL_DBGMCU_UNFREEZE_TIM13() (DBGMCU->APB1FZ &= ~(DBGMCU_APB1_FZ_DBG_TIM13_STOP))
466#endif /* DBGMCU_APB1_FZ_DBG_TIM13_STOP */
467
468#if defined(DBGMCU_APB1_FZ_DBG_TIM14_STOP)
469#define __HAL_DBGMCU_FREEZE_TIM14() (DBGMCU->APB1FZ |= (DBGMCU_APB1_FZ_DBG_TIM14_STOP))
470#define __HAL_DBGMCU_UNFREEZE_TIM14() (DBGMCU->APB1FZ &= ~(DBGMCU_APB1_FZ_DBG_TIM14_STOP))
471#endif /* DBGMCU_APB1_FZ_DBG_TIM14_STOP */
472
473#if defined(DBGMCU_APB1_FZ_DBG_TIM18_STOP)
474#define __HAL_FREEZE_TIM18_DBGMCU() (DBGMCU->APB1FZ |= (DBGMCU_APB1_FZ_DBG_TIM18_STOP))
475#define __HAL_UNFREEZE_TIM18_DBGMCU() (DBGMCU->APB1FZ &= ~(DBGMCU_APB1_FZ_DBG_TIM18_STOP))
476#endif /* DBGMCU_APB1_FZ_DBG_TIM14_STOP */
477
478#if defined(DBGMCU_APB1_FZ_DBG_RTC_STOP)
479#define __HAL_DBGMCU_FREEZE_RTC() (DBGMCU->APB1FZ |= (DBGMCU_APB1_FZ_DBG_RTC_STOP))
480#define __HAL_DBGMCU_UNFREEZE_RTC() (DBGMCU->APB1FZ &= ~(DBGMCU_APB1_FZ_DBG_RTC_STOP))
481#endif /* DBGMCU_APB1_FZ_DBG_RTC_STOP */
482
483#if defined(DBGMCU_APB1_FZ_DBG_WWDG_STOP)
484#define __HAL_DBGMCU_FREEZE_WWDG() (DBGMCU->APB1FZ |= (DBGMCU_APB1_FZ_DBG_WWDG_STOP))
485#define __HAL_DBGMCU_UNFREEZE_WWDG() (DBGMCU->APB1FZ &= ~(DBGMCU_APB1_FZ_DBG_WWDG_STOP))
486#endif /* DBGMCU_APB1_FZ_DBG_WWDG_STOP */
487
488#if defined(DBGMCU_APB1_FZ_DBG_IWDG_STOP)
489#define __HAL_DBGMCU_FREEZE_IWDG() (DBGMCU->APB1FZ |= (DBGMCU_APB1_FZ_DBG_IWDG_STOP))
490#define __HAL_DBGMCU_UNFREEZE_IWDG() (DBGMCU->APB1FZ &= ~(DBGMCU_APB1_FZ_DBG_IWDG_STOP))
491#endif /* DBGMCU_APB1_FZ_DBG_IWDG_STOP */
492
493#if defined(DBGMCU_APB1_FZ_DBG_I2C1_SMBUS_TIMEOUT)
494#define __HAL_DBGMCU_FREEZE_I2C1_TIMEOUT() (DBGMCU->APB1FZ |= (DBGMCU_APB1_FZ_DBG_I2C1_SMBUS_TIMEOUT))
495#define __HAL_DBGMCU_UNFREEZE_I2C1_TIMEOUT() (DBGMCU->APB1FZ &= ~(DBGMCU_APB1_FZ_DBG_I2C1_SMBUS_TIMEOUT))
496#endif /* DBGMCU_APB1_FZ_DBG_I2C1_SMBUS_TIMEOUT */
497
498#if defined(DBGMCU_APB1_FZ_DBG_I2C2_SMBUS_TIMEOUT)
499#define __HAL_DBGMCU_FREEZE_I2C2_TIMEOUT() (DBGMCU->APB1FZ |= (DBGMCU_APB1_FZ_DBG_I2C2_SMBUS_TIMEOUT))
500#define __HAL_DBGMCU_UNFREEZE_I2C2_TIMEOUT() (DBGMCU->APB1FZ &= ~(DBGMCU_APB1_FZ_DBG_I2C2_SMBUS_TIMEOUT))
501#endif /* DBGMCU_APB1_FZ_DBG_I2C2_SMBUS_TIMEOUT */
502
503#if defined(DBGMCU_APB1_FZ_DBG_I2C3_SMBUS_TIMEOUT)
504#define __HAL_DBGMCU_FREEZE_I2C3_TIMEOUT() (DBGMCU->APB1FZ |= (DBGMCU_APB1_FZ_DBG_I2C3_SMBUS_TIMEOUT))
505#define __HAL_DBGMCU_UNFREEZE_I2C3_TIMEOUT() (DBGMCU->APB1FZ &= ~(DBGMCU_APB1_FZ_DBG_I2C3_SMBUS_TIMEOUT))
506#endif /* DBGMCU_APB1_FZ_DBG_I2C3_SMBUS_TIMEOUT */
507
508#if defined(DBGMCU_APB1_FZ_DBG_CAN_STOP)
509#define __HAL_FREEZE_CAN_DBGMCU() (DBGMCU->APB1FZ |= (DBGMCU_APB1_FZ_DBG_CAN_STOP))
510#define __HAL_UNFREEZE_CAN_DBGMCU() (DBGMCU->APB1FZ &= ~(DBGMCU_APB1_FZ_DBG_CAN_STOP))
511#endif /* DBGMCU_APB1_FZ_DBG_CAN_STOP */
519#if defined(DBGMCU_APB2_FZ_DBG_TIM1_STOP)
520#define __HAL_DBGMCU_FREEZE_TIM1() (DBGMCU->APB2FZ |= (DBGMCU_APB2_FZ_DBG_TIM1_STOP))
521#define __HAL_DBGMCU_UNFREEZE_TIM1() (DBGMCU->APB2FZ &= ~(DBGMCU_APB2_FZ_DBG_TIM1_STOP))
522#endif /* DBGMCU_APB2_FZ_DBG_TIM1_STOP */
523
524#if defined(DBGMCU_APB2_FZ_DBG_TIM8_STOP)
525#define __HAL_DBGMCU_FREEZE_TIM8() (DBGMCU->APB2FZ |= (DBGMCU_APB2_FZ_DBG_TIM8_STOP))
526#define __HAL_DBGMCU_UNFREEZE_TIM8() (DBGMCU->APB2FZ &= ~(DBGMCU_APB2_FZ_DBG_TIM8_STOP))
527#endif /* DBGMCU_APB2_FZ_DBG_TIM8_STOP */
528
529#if defined(DBGMCU_APB2_FZ_DBG_TIM15_STOP)
530#define __HAL_DBGMCU_FREEZE_TIM15() (DBGMCU->APB2FZ |= (DBGMCU_APB2_FZ_DBG_TIM15_STOP))
531#define __HAL_DBGMCU_UNFREEZE_TIM15() (DBGMCU->APB2FZ &= ~(DBGMCU_APB2_FZ_DBG_TIM15_STOP))
532#endif /* DBGMCU_APB2_FZ_DBG_TIM15_STOP */
533
534#if defined(DBGMCU_APB2_FZ_DBG_TIM16_STOP)
535#define __HAL_DBGMCU_FREEZE_TIM16() (DBGMCU->APB2FZ |= (DBGMCU_APB2_FZ_DBG_TIM16_STOP))
536#define __HAL_DBGMCU_UNFREEZE_TIM16() (DBGMCU->APB2FZ &= ~(DBGMCU_APB2_FZ_DBG_TIM16_STOP))
537#endif /* DBGMCU_APB2_FZ_DBG_TIM16_STOP */
538
539#if defined(DBGMCU_APB2_FZ_DBG_TIM17_STOP)
540#define __HAL_DBGMCU_FREEZE_TIM17() (DBGMCU->APB2FZ |= (DBGMCU_APB2_FZ_DBG_TIM17_STOP))
541#define __HAL_DBGMCU_UNFREEZE_TIM17() (DBGMCU->APB2FZ &= ~(DBGMCU_APB2_FZ_DBG_TIM17_STOP))
542#endif /* DBGMCU_APB2_FZ_DBG_TIM17_STOP */
543
544#if defined(DBGMCU_APB2_FZ_DBG_TIM19_STOP)
545#define __HAL_FREEZE_TIM19_DBGMCU() (DBGMCU->APB2FZ |= (DBGMCU_APB2_FZ_DBG_TIM19_STOP))
546#define __HAL_UNFREEZE_TIM19_DBGMCU() (DBGMCU->APB2FZ &= ~(DBGMCU_APB2_FZ_DBG_TIM19_STOP))
547#endif /* DBGMCU_APB2_FZ_DBG_TIM19_STOP */
548
549#if defined(DBGMCU_APB2_FZ_DBG_TIM20_STOP)
550#define __HAL_FREEZE_TIM20_DBGMCU() (DBGMCU->APB2FZ |= (DBGMCU_APB2_FZ_DBG_TIM20_STOP))
551#define __HAL_UNFREEZE_TIM20_DBGMCU() (DBGMCU->APB2FZ &= ~(DBGMCU_APB2_FZ_DBG_TIM20_STOP))
552#endif /* DBGMCU_APB2_FZ_DBG_TIM20_STOP */
553
554#if defined(DBGMCU_APB2_FZ_DBG_HRTIM1_STOP)
555#define __HAL_FREEZE_HRTIM1_DBGMCU() (DBGMCU->APB2FZ |= (DBGMCU_APB2_FZ_DBG_HRTIM1_STOP))
556#define __HAL_UNFREEZE_HRTIM1_DBGMCU() (DBGMCU->APB2FZ &= ~(DBGMCU_APB2_FZ_DBG_HRTIM1_STOP))
557#endif /* DBGMCU_APB2_FZ_DBG_HRTIM1_STOP */
565#if defined(SYSCFG_CFGR1_MEM_MODE)
568#define __HAL_SYSCFG_REMAPMEMORY_FLASH() (SYSCFG->CFGR1 &= ~(SYSCFG_CFGR1_MEM_MODE))
569#endif /* SYSCFG_CFGR1_MEM_MODE */
570
571#if defined(SYSCFG_CFGR1_MEM_MODE_0)
574#define __HAL_SYSCFG_REMAPMEMORY_SYSTEMFLASH() do {SYSCFG->CFGR1 &= ~(SYSCFG_CFGR1_MEM_MODE); \
575 SYSCFG->CFGR1 |= SYSCFG_CFGR1_MEM_MODE_0; \
576 }while(0U)
577#endif /* SYSCFG_CFGR1_MEM_MODE_0 */
578
579#if defined(SYSCFG_CFGR1_MEM_MODE_0) && defined(SYSCFG_CFGR1_MEM_MODE_1)
582#define __HAL_SYSCFG_REMAPMEMORY_SRAM() do {SYSCFG->CFGR1 &= ~(SYSCFG_CFGR1_MEM_MODE); \
583 SYSCFG->CFGR1 |= (SYSCFG_CFGR1_MEM_MODE_0 | SYSCFG_CFGR1_MEM_MODE_1); \
584 }while(0U)
585#endif /* SYSCFG_CFGR1_MEM_MODE_0 && SYSCFG_CFGR1_MEM_MODE_1 */
586
587#if defined(SYSCFG_CFGR1_MEM_MODE_2)
588#define __HAL_SYSCFG_FMC_BANK() do {SYSCFG->CFGR1 &= ~(SYSCFG_CFGR1_MEM_MODE); \
589 SYSCFG->CFGR1 |= (SYSCFG_CFGR1_MEM_MODE_2); \
590 }while(0U)
591#endif /* SYSCFG_CFGR1_MEM_MODE_2 */
599#if defined(SYSCFG_CFGR1_ENCODER_MODE)
602#define __HAL_REMAPENCODER_NONE() (SYSCFG->CFGR1 &= ~(SYSCFG_CFGR1_ENCODER_MODE))
603#endif /* SYSCFG_CFGR1_ENCODER_MODE */
604
605#if defined(SYSCFG_CFGR1_ENCODER_MODE_0)
608#define __HAL_REMAPENCODER_TIM2() do {SYSCFG->CFGR1 &= ~(SYSCFG_CFGR1_ENCODER_MODE); \
609 SYSCFG->CFGR1 |= SYSCFG_CFGR1_ENCODER_MODE_0; \
610 }while(0U)
611#endif /* SYSCFG_CFGR1_ENCODER_MODE_0 */
612
613#if defined(SYSCFG_CFGR1_ENCODER_MODE_1)
616#define __HAL_REMAPENCODER_TIM3() do {SYSCFG->CFGR1 &= ~(SYSCFG_CFGR1_ENCODER_MODE); \
617 SYSCFG->CFGR1 |= SYSCFG_CFGR1_ENCODER_MODE_1; \
618 }while(0U)
619#endif /* SYSCFG_CFGR1_ENCODER_MODE_1 */
620
621#if defined(SYSCFG_CFGR1_ENCODER_MODE_0) && defined(SYSCFG_CFGR1_ENCODER_MODE_1)
624#define __HAL_REMAPENCODER_TIM4() do {SYSCFG->CFGR1 &= ~(SYSCFG_CFGR1_ENCODER_MODE); \
625 SYSCFG->CFGR1 |= (SYSCFG_CFGR1_ENCODER_MODE_0 | SYSCFG_CFGR1_ENCODER_MODE_1); \
626 }while(0U)
627#endif /* SYSCFG_CFGR1_ENCODER_MODE_0 && SYSCFG_CFGR1_ENCODER_MODE_1 */
635#if defined(SYSCFG_CFGR3_DMA_RMP) && defined(SYSCFG_CFGR1_DMA_RMP)
639#define __HAL_DMA_REMAP_CHANNEL_ENABLE(__DMA_REMAP__) do {assert_param(IS_DMA_REMAP((__DMA_REMAP__))); \
640 (((__DMA_REMAP__) & HAL_REMAP_CFGR3_MASK) ? \
641 (SYSCFG->CFGR3 |= ((__DMA_REMAP__) & ~HAL_REMAP_CFGR3_MASK)) : \
642 (SYSCFG->CFGR1 |= (__DMA_REMAP__))); \
643 }while(0U)
644#define __HAL_DMA_REMAP_CHANNEL_DISABLE(__DMA_REMAP__) do {assert_param(IS_DMA_REMAP((__DMA_REMAP__))); \
645 (((__DMA_REMAP__) & HAL_REMAP_CFGR3_MASK) ? \
646 (SYSCFG->CFGR3 &= (~(__DMA_REMAP__) | HAL_REMAP_CFGR3_MASK)) : \
647 (SYSCFG->CFGR1 &= ~(__DMA_REMAP__))); \
648 }while(0U)
649#elif defined(SYSCFG_CFGR1_DMA_RMP)
653#define __HAL_DMA_REMAP_CHANNEL_ENABLE(__DMA_REMAP__) do {assert_param(IS_DMA_REMAP((__DMA_REMAP__))); \
654 SYSCFG->CFGR1 |= (__DMA_REMAP__); \
655 }while(0U)
656#define __HAL_DMA_REMAP_CHANNEL_DISABLE(__DMA_REMAP__) do {assert_param(IS_DMA_REMAP((__DMA_REMAP__))); \
657 SYSCFG->CFGR1 &= ~(__DMA_REMAP__); \
658 }while(0U)
659#endif /* SYSCFG_CFGR3_DMA_RMP || SYSCFG_CFGR1_DMA_RMP */
671#define __HAL_SYSCFG_FASTMODEPLUS_ENABLE(__FASTMODEPLUS__) do {assert_param(IS_SYSCFG_FASTMODEPLUS((__FASTMODEPLUS__)));\
672 SET_BIT(SYSCFG->CFGR1, (__FASTMODEPLUS__));\
673 }while(0U)
674
675#define __HAL_SYSCFG_FASTMODEPLUS_DISABLE(__FASTMODEPLUS__) do {assert_param(IS_SYSCFG_FASTMODEPLUS((__FASTMODEPLUS__)));\
676 CLEAR_BIT(SYSCFG->CFGR1, (__FASTMODEPLUS__));\
677 }while(0U)
688#define __HAL_SYSCFG_INTERRUPT_ENABLE(__INTERRUPT__) do {assert_param(IS_HAL_SYSCFG_INTERRUPT((__INTERRUPT__))); \
689 SYSCFG->CFGR1 |= (__INTERRUPT__); \
690 }while(0U)
691
692#define __HAL_SYSCFG_INTERRUPT_DISABLE(__INTERRUPT__) do {assert_param(IS_HAL_SYSCFG_INTERRUPT((__INTERRUPT__))); \
693 SYSCFG->CFGR1 &= ~(__INTERRUPT__); \
694 }while(0U)
699#if defined(SYSCFG_CFGR1_USB_IT_RMP)
705#define __HAL_REMAPINTERRUPT_USB_ENABLE() (SYSCFG->CFGR1 |= (SYSCFG_CFGR1_USB_IT_RMP))
706#define __HAL_REMAPINTERRUPT_USB_DISABLE() (SYSCFG->CFGR1 &= ~(SYSCFG_CFGR1_USB_IT_RMP))
710#endif /* SYSCFG_CFGR1_USB_IT_RMP */
711
712#if defined(SYSCFG_CFGR1_VBAT)
718#define __HAL_SYSCFG_VBAT_MONITORING_ENABLE() (SYSCFG->CFGR1 |= (SYSCFG_CFGR1_VBAT))
719#define __HAL_SYSCFG_VBAT_MONITORING_DISABLE() (SYSCFG->CFGR1 &= ~(SYSCFG_CFGR1_VBAT))
723#endif /* SYSCFG_CFGR1_VBAT */
724
725#if defined(SYSCFG_CFGR2_LOCKUP_LOCK)
733#define __HAL_SYSCFG_BREAK_LOCKUP_LOCK() do {SYSCFG->CFGR2 &= ~(SYSCFG_CFGR2_LOCKUP_LOCK); \
734 SYSCFG->CFGR2 |= SYSCFG_CFGR2_LOCKUP_LOCK; \
735 }while(0U)
739#endif /* SYSCFG_CFGR2_LOCKUP_LOCK */
740
741#if defined(SYSCFG_CFGR2_PVD_LOCK)
749#define __HAL_SYSCFG_BREAK_PVD_LOCK() do {SYSCFG->CFGR2 &= ~(SYSCFG_CFGR2_PVD_LOCK); \
750 SYSCFG->CFGR2 |= SYSCFG_CFGR2_PVD_LOCK; \
751 }while(0U)
755#endif /* SYSCFG_CFGR2_PVD_LOCK */
756
757#if defined(SYSCFG_CFGR2_SRAM_PARITY_LOCK)
765#define __HAL_SYSCFG_BREAK_SRAMPARITY_LOCK() do {SYSCFG->CFGR2 &= ~(SYSCFG_CFGR2_SRAM_PARITY_LOCK); \
766 SYSCFG->CFGR2 |= SYSCFG_CFGR2_SRAM_PARITY_LOCK; \
767 }while(0U)
771#endif /* SYSCFG_CFGR2_SRAM_PARITY_LOCK */
772
776#if defined(SYSCFG_CFGR3_TRIGGER_RMP)
780#define __HAL_REMAPTRIGGER_ENABLE(__TRIGGER_REMAP__) do {assert_param(IS_HAL_REMAPTRIGGER((__TRIGGER_REMAP__))); \
781 (((__TRIGGER_REMAP__) & HAL_REMAP_CFGR3_MASK) ? \
782 (SYSCFG->CFGR3 |= ((__TRIGGER_REMAP__) & ~HAL_REMAP_CFGR3_MASK)) : \
783 (SYSCFG->CFGR1 |= (__TRIGGER_REMAP__))); \
784 }while(0U)
785#define __HAL_REMAPTRIGGER_DISABLE(__TRIGGER_REMAP__) do {assert_param(IS_HAL_REMAPTRIGGER((__TRIGGER_REMAP__))); \
786 (((__TRIGGER_REMAP__) & HAL_REMAP_CFGR3_MASK) ? \
787 (SYSCFG->CFGR3 &= (~(__TRIGGER_REMAP__) | HAL_REMAP_CFGR3_MASK)) : \
788 (SYSCFG->CFGR1 &= ~(__TRIGGER_REMAP__))); \
789 }while(0U)
790#else
794#define __HAL_REMAPTRIGGER_ENABLE(__TRIGGER_REMAP__) do {assert_param(IS_HAL_REMAPTRIGGER((__TRIGGER_REMAP__))); \
795 (SYSCFG->CFGR1 |= (__TRIGGER_REMAP__)); \
796 }while(0U)
797#define __HAL_REMAPTRIGGER_DISABLE(__TRIGGER_REMAP__) do {assert_param(IS_HAL_REMAPTRIGGER((__TRIGGER_REMAP__))); \
798 (SYSCFG->CFGR1 &= ~(__TRIGGER_REMAP__)); \
799 }while(0U)
800#endif /* SYSCFG_CFGR3_TRIGGER_RMP */
805#if defined (STM32F302xE) || defined (STM32F303xE) || defined (STM32F398xx)
812#define __HAL_REMAPADCTRIGGER_ENABLE(__ADCTRIGGER_REMAP__) do {assert_param(IS_HAL_REMAPADCTRIGGER((__ADCTRIGGER_REMAP__))); \
813 (SYSCFG->CFGR4 |= (__ADCTRIGGER_REMAP__)); \
814 }while(0U)
815#define __HAL_REMAPADCTRIGGER_DISABLE(__ADCTRIGGER_REMAP__) do {assert_param(IS_HAL_REMAPADCTRIGGER((__ADCTRIGGER_REMAP__))); \
816 (SYSCFG->CFGR4 &= ~(__ADCTRIGGER_REMAP__)); \
817 }while(0U)
821#endif /* STM32F302xE || STM32F303xE || STM32F398xx */
822
823#if defined(SYSCFG_CFGR2_BYP_ADDR_PAR)
832#define __HAL_SYSCFG_RAM_PARITYCHECK_DISABLE() (*(__IO uint32_t *) CFGR2_BYPADDRPAR_BB = 0x00000001U)
836#endif /* SYSCFG_CFGR2_BYP_ADDR_PAR */
837
838#if defined(SYSCFG_RCR_PAGE0)
846#define __HAL_SYSCFG_SRAM_WRP_ENABLE(__PAGE_WP__) do {assert_param(IS_HAL_SYSCFG_WP_PAGE((__PAGE_WP__))); \
847 SYSCFG->RCR |= (__PAGE_WP__); \
848 }while(0U)
852#endif /* SYSCFG_RCR_PAGE0 */
853
857/* Private macro -------------------------------------------------------------*/
861#define IS_TICKFREQ(FREQ) (((FREQ) == HAL_TICK_FREQ_10HZ) || \
862 ((FREQ) == HAL_TICK_FREQ_100HZ) || \
863 ((FREQ) == HAL_TICK_FREQ_1KHZ))
867/* Exported functions --------------------------------------------------------*/
876/* Initialization and de-initialization functions ******************************/
877HAL_StatusTypeDef HAL_Init(void);
878HAL_StatusTypeDef HAL_DeInit(void);
879void HAL_MspInit(void);
880void HAL_MspDeInit(void);
881HAL_StatusTypeDef HAL_InitTick (uint32_t TickPriority);
886/* Exported variables ---------------------------------------------------------*/
890extern __IO uint32_t uwTick;
891extern uint32_t uwTickPrio;
892extern HAL_TickFreqTypeDef uwTickFreq;
901/* Peripheral Control functions ************************************************/
902void HAL_IncTick(void);
903void HAL_Delay(uint32_t Delay);
904void HAL_SuspendTick(void);
905void HAL_ResumeTick(void);
906uint32_t HAL_GetTick(void);
907uint32_t HAL_GetTickPrio(void);
908HAL_StatusTypeDef HAL_SetTickFreq(HAL_TickFreqTypeDef Freq);
909HAL_TickFreqTypeDef HAL_GetTickFreq(void);
910uint32_t HAL_GetHalVersion(void);
911uint32_t HAL_GetREVID(void);
912uint32_t HAL_GetDEVID(void);
913uint32_t HAL_GetUIDw0(void);
914uint32_t HAL_GetUIDw1(void);
915uint32_t HAL_GetUIDw2(void);
916void HAL_DBGMCU_EnableDBGSleepMode(void);
917void HAL_DBGMCU_DisableDBGSleepMode(void);
918void HAL_DBGMCU_EnableDBGStopMode(void);
919void HAL_DBGMCU_DisableDBGStopMode(void);
920void HAL_DBGMCU_EnableDBGStandbyMode(void);
921void HAL_DBGMCU_DisableDBGStandbyMode(void);
938#ifdef __cplusplus
939}
940#endif
941
942#endif /* __STM32F3xx_HAL_H */
943
944
__IO
#define __IO
Definition: core_armv8mbl.h:196
HAL_InitTick
HAL_StatusTypeDef HAL_InitTick(uint32_t TickPriority)
HAL_DeInit
HAL_StatusTypeDef HAL_DeInit(void)
HAL_MspDeInit
void HAL_MspDeInit(void)
HAL_MspInit
void HAL_MspInit(void)
Initializes the Global MSP.
Definition: stm32f3xx_hal_msp.c:63
HAL_Init
HAL_StatusTypeDef HAL_Init(void)
HAL_ResumeTick
void HAL_ResumeTick(void)
HAL_DBGMCU_EnableDBGStandbyMode
void HAL_DBGMCU_EnableDBGStandbyMode(void)
HAL_DBGMCU_DisableDBGStopMode
void HAL_DBGMCU_DisableDBGStopMode(void)
HAL_SetTickFreq
HAL_StatusTypeDef HAL_SetTickFreq(HAL_TickFreqTypeDef Freq)
HAL_GetUIDw1
uint32_t HAL_GetUIDw1(void)
HAL_GetUIDw2
uint32_t HAL_GetUIDw2(void)
HAL_DBGMCU_DisableDBGStandbyMode
void HAL_DBGMCU_DisableDBGStandbyMode(void)
HAL_GetTickFreq
HAL_TickFreqTypeDef HAL_GetTickFreq(void)
HAL_IncTick
void HAL_IncTick(void)
HAL_SuspendTick
void HAL_SuspendTick(void)
HAL_DBGMCU_DisableDBGSleepMode
void HAL_DBGMCU_DisableDBGSleepMode(void)
HAL_GetTickPrio
uint32_t HAL_GetTickPrio(void)
HAL_DBGMCU_EnableDBGStopMode
void HAL_DBGMCU_EnableDBGStopMode(void)
HAL_GetREVID
uint32_t HAL_GetREVID(void)
HAL_Delay
void HAL_Delay(uint32_t Delay)
HAL_DBGMCU_EnableDBGSleepMode
void HAL_DBGMCU_EnableDBGSleepMode(void)
HAL_GetTick
uint32_t HAL_GetTick(void)
HAL_GetUIDw0
uint32_t HAL_GetUIDw0(void)
HAL_GetHalVersion
uint32_t HAL_GetHalVersion(void)
HAL_GetDEVID
uint32_t HAL_GetDEVID(void)
uwTickPrio
uint32_t uwTickPrio
uwTickFreq
HAL_TickFreqTypeDef uwTickFreq
uwTick
__IO uint32_t uwTick
HAL_TickFreqTypeDef
HAL_TickFreqTypeDef
Definition: stm32f3xx_hal.h:61
HAL_TICK_FREQ_DEFAULT
@ HAL_TICK_FREQ_DEFAULT
Definition: stm32f3xx_hal.h:65
HAL_TICK_FREQ_1KHZ
@ HAL_TICK_FREQ_1KHZ
Definition: stm32f3xx_hal.h:64
HAL_TICK_FREQ_10HZ
@ HAL_TICK_FREQ_10HZ
Definition: stm32f3xx_hal.h:62
HAL_TICK_FREQ_100HZ
@ HAL_TICK_FREQ_100HZ
Definition: stm32f3xx_hal.h:63
stm32f3xx_hal_conf.h
HAL configuration file.
HAL_StatusTypeDef
HAL_StatusTypeDef
HAL Status structures definition
Definition: stm32f3xx_hal_def.h:39