20#ifndef __STM32F3xx_HAL_DMA_H
21#define __STM32F3xx_HAL_DMA_H
148#define HAL_DMA_ERROR_NONE (0x00000000U)
149#define HAL_DMA_ERROR_TE (0x00000001U)
150#define HAL_DMA_ERROR_NO_XFER (0x00000004U)
151#define HAL_DMA_ERROR_TIMEOUT (0x00000020U)
152#define HAL_DMA_ERROR_NOT_SUPPORTED (0x00000100U)
160#define DMA_PERIPH_TO_MEMORY (0x00000000U)
161#define DMA_MEMORY_TO_PERIPH ((uint32_t)DMA_CCR_DIR)
162#define DMA_MEMORY_TO_MEMORY ((uint32_t)DMA_CCR_MEM2MEM)
171#define DMA_PINC_ENABLE ((uint32_t)DMA_CCR_PINC)
172#define DMA_PINC_DISABLE (0x00000000U)
180#define DMA_MINC_ENABLE ((uint32_t)DMA_CCR_MINC)
181#define DMA_MINC_DISABLE (0x00000000U)
189#define DMA_PDATAALIGN_BYTE (0x00000000U)
190#define DMA_PDATAALIGN_HALFWORD ((uint32_t)DMA_CCR_PSIZE_0)
191#define DMA_PDATAALIGN_WORD ((uint32_t)DMA_CCR_PSIZE_1)
199#define DMA_MDATAALIGN_BYTE (0x00000000U)
200#define DMA_MDATAALIGN_HALFWORD ((uint32_t)DMA_CCR_MSIZE_0)
201#define DMA_MDATAALIGN_WORD ((uint32_t)DMA_CCR_MSIZE_1)
209#define DMA_NORMAL (0x00000000U)
210#define DMA_CIRCULAR ((uint32_t)DMA_CCR_CIRC)
218#define DMA_PRIORITY_LOW (0x00000000U)
219#define DMA_PRIORITY_MEDIUM ((uint32_t)DMA_CCR_PL_0)
220#define DMA_PRIORITY_HIGH ((uint32_t)DMA_CCR_PL_1)
221#define DMA_PRIORITY_VERY_HIGH ((uint32_t)DMA_CCR_PL)
230#define DMA_IT_TC ((uint32_t)DMA_CCR_TCIE)
231#define DMA_IT_HT ((uint32_t)DMA_CCR_HTIE)
232#define DMA_IT_TE ((uint32_t)DMA_CCR_TEIE)
240#define DMA_FLAG_GL1 (0x00000001U)
241#define DMA_FLAG_TC1 (0x00000002U)
242#define DMA_FLAG_HT1 (0x00000004U)
243#define DMA_FLAG_TE1 (0x00000008U)
244#define DMA_FLAG_GL2 (0x00000010U)
245#define DMA_FLAG_TC2 (0x00000020U)
246#define DMA_FLAG_HT2 (0x00000040U)
247#define DMA_FLAG_TE2 (0x00000080U)
248#define DMA_FLAG_GL3 (0x00000100U)
249#define DMA_FLAG_TC3 (0x00000200U)
250#define DMA_FLAG_HT3 (0x00000400U)
251#define DMA_FLAG_TE3 (0x00000800U)
252#define DMA_FLAG_GL4 (0x00001000U)
253#define DMA_FLAG_TC4 (0x00002000U)
254#define DMA_FLAG_HT4 (0x00004000U)
255#define DMA_FLAG_TE4 (0x00008000U)
256#define DMA_FLAG_GL5 (0x00010000U)
257#define DMA_FLAG_TC5 (0x00020000U)
258#define DMA_FLAG_HT5 (0x00040000U)
259#define DMA_FLAG_TE5 (0x00080000U)
260#define DMA_FLAG_GL6 (0x00100000U)
261#define DMA_FLAG_TC6 (0x00200000U)
262#define DMA_FLAG_HT6 (0x00400000U)
263#define DMA_FLAG_TE6 (0x00800000U)
264#define DMA_FLAG_GL7 (0x01000000U)
265#define DMA_FLAG_TC7 (0x02000000U)
266#define DMA_FLAG_HT7 (0x04000000U)
267#define DMA_FLAG_TE7 (0x08000000U)
286#define __HAL_DMA_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_DMA_STATE_RESET)
293#define __HAL_DMA_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->CCR |= DMA_CCR_EN)
300#define __HAL_DMA_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->CCR &= ~DMA_CCR_EN)
315#define __HAL_DMA_ENABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->CCR |= (__INTERRUPT__))
327#define __HAL_DMA_DISABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->CCR &= ~(__INTERRUPT__))
339#define __HAL_DMA_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) (((__HANDLE__)->Instance->CCR & (__INTERRUPT__)))
347#define __HAL_DMA_GET_COUNTER(__HANDLE__) ((__HANDLE__)->Instance->CNDTR)
406#define IS_DMA_BUFFER_SIZE(SIZE) (((SIZE) >= 0x1U) && ((SIZE) < 0x10000U))
408#define IS_DMA_DIRECTION(DIRECTION) (((DIRECTION) == DMA_PERIPH_TO_MEMORY ) || \
409 ((DIRECTION) == DMA_MEMORY_TO_PERIPH) || \
410 ((DIRECTION) == DMA_MEMORY_TO_MEMORY))
412#define IS_DMA_PERIPHERAL_INC_STATE(STATE) (((STATE) == DMA_PINC_ENABLE) || \
413 ((STATE) == DMA_PINC_DISABLE))
415#define IS_DMA_MEMORY_INC_STATE(STATE) (((STATE) == DMA_MINC_ENABLE) || \
416 ((STATE) == DMA_MINC_DISABLE))
418#define IS_DMA_PERIPHERAL_DATA_SIZE(SIZE) (((SIZE) == DMA_PDATAALIGN_BYTE) || \
419 ((SIZE) == DMA_PDATAALIGN_HALFWORD) || \
420 ((SIZE) == DMA_PDATAALIGN_WORD))
422#define IS_DMA_MEMORY_DATA_SIZE(SIZE) (((SIZE) == DMA_MDATAALIGN_BYTE) || \
423 ((SIZE) == DMA_MDATAALIGN_HALFWORD) || \
424 ((SIZE) == DMA_MDATAALIGN_WORD ))
426#define IS_DMA_MODE(MODE) (((MODE) == DMA_NORMAL ) || \
427 ((MODE) == DMA_CIRCULAR))
429#define IS_DMA_PRIORITY(PRIORITY) (((PRIORITY) == DMA_PRIORITY_LOW ) || \
430 ((PRIORITY) == DMA_PRIORITY_MEDIUM) || \
431 ((PRIORITY) == DMA_PRIORITY_HIGH) || \
432 ((PRIORITY) == DMA_PRIORITY_VERY_HIGH))
#define __IO
Definition: core_armv8mbl.h:196
HAL_StatusTypeDef HAL_DMA_Init(DMA_HandleTypeDef *hdma)
HAL_StatusTypeDef HAL_DMA_DeInit(DMA_HandleTypeDef *hdma)
HAL_StatusTypeDef HAL_DMA_Abort(DMA_HandleTypeDef *hdma)
HAL_StatusTypeDef HAL_DMA_Abort_IT(DMA_HandleTypeDef *hdma)
HAL_StatusTypeDef HAL_DMA_PollForTransfer(DMA_HandleTypeDef *hdma, uint32_t CompleteLevel, uint32_t Timeout)
HAL_StatusTypeDef HAL_DMA_Start_IT(DMA_HandleTypeDef *hdma, uint32_t SrcAddress, uint32_t DstAddress, uint32_t DataLength)
HAL_StatusTypeDef HAL_DMA_UnRegisterCallback(DMA_HandleTypeDef *hdma, HAL_DMA_CallbackIDTypeDef CallbackID)
void HAL_DMA_IRQHandler(DMA_HandleTypeDef *hdma)
HAL_StatusTypeDef HAL_DMA_Start(DMA_HandleTypeDef *hdma, uint32_t SrcAddress, uint32_t DstAddress, uint32_t DataLength)
HAL_StatusTypeDef HAL_DMA_RegisterCallback(DMA_HandleTypeDef *hdma, HAL_DMA_CallbackIDTypeDef CallbackID, void(*pCallback)(DMA_HandleTypeDef *_hdma))
uint32_t HAL_DMA_GetError(DMA_HandleTypeDef *hdma)
HAL_DMA_StateTypeDef HAL_DMA_GetState(DMA_HandleTypeDef *hdma)
struct __DMA_HandleTypeDef DMA_HandleTypeDef
DMA handle Structure definition
HAL_DMA_StateTypeDef
HAL DMA State structures definition
Definition: stm32f3xx_hal_dma.h:78
HAL_DMA_LevelCompleteTypeDef
HAL DMA Error Code structure definition
Definition: stm32f3xx_hal_dma.h:89
HAL_DMA_CallbackIDTypeDef
HAL DMA Callback ID structure definition.
Definition: stm32f3xx_hal_dma.h:98
@ HAL_DMA_STATE_RESET
Definition: stm32f3xx_hal_dma.h:79
@ HAL_DMA_STATE_TIMEOUT
Definition: stm32f3xx_hal_dma.h:82
@ HAL_DMA_STATE_READY
Definition: stm32f3xx_hal_dma.h:80
@ HAL_DMA_STATE_BUSY
Definition: stm32f3xx_hal_dma.h:81
@ HAL_DMA_FULL_TRANSFER
Definition: stm32f3xx_hal_dma.h:90
@ HAL_DMA_HALF_TRANSFER
Definition: stm32f3xx_hal_dma.h:91
@ HAL_DMA_XFER_ABORT_CB_ID
Definition: stm32f3xx_hal_dma.h:102
@ HAL_DMA_XFER_ERROR_CB_ID
Definition: stm32f3xx_hal_dma.h:101
@ HAL_DMA_XFER_HALFCPLT_CB_ID
Definition: stm32f3xx_hal_dma.h:100
@ HAL_DMA_XFER_CPLT_CB_ID
Definition: stm32f3xx_hal_dma.h:99
@ HAL_DMA_XFER_ALL_CB_ID
Definition: stm32f3xx_hal_dma.h:103
This file contains HAL common defines, enumeration, macros and structures definitions.
HAL_StatusTypeDef
HAL Status structures definition
Definition: stm32f3xx_hal_def.h:39
HAL_LockTypeDef
HAL Lock structures definition
Definition: stm32f3xx_hal_def.h:50
Header file of DMA HAL extension module.
DMA Controller.
Definition: stm32f303xe.h:349
DMA Configuration Structure definition
Definition: stm32f3xx_hal_dma.h:48
uint32_t Direction
Definition: stm32f3xx_hal_dma.h:49
uint32_t PeriphDataAlignment
Definition: stm32f3xx_hal_dma.h:59
uint32_t PeriphInc
Definition: stm32f3xx_hal_dma.h:53
uint32_t MemInc
Definition: stm32f3xx_hal_dma.h:56
uint32_t MemDataAlignment
Definition: stm32f3xx_hal_dma.h:62
uint32_t Mode
Definition: stm32f3xx_hal_dma.h:65
uint32_t Priority
Definition: stm32f3xx_hal_dma.h:70
Definition: stm32f303xe.h:357
DMA handle Structure definition
Definition: stm32f3xx_hal_dma.h:110
HAL_LockTypeDef Lock
Definition: stm32f3xx_hal_dma.h:115
HAL_DMA_StateTypeDef State
Definition: stm32f3xx_hal_dma.h:117
void(* XferAbortCallback)(struct __DMA_HandleTypeDef *hdma)
Definition: stm32f3xx_hal_dma.h:127
DMA_InitTypeDef Init
Definition: stm32f3xx_hal_dma.h:113
void(* XferCpltCallback)(struct __DMA_HandleTypeDef *hdma)
Definition: stm32f3xx_hal_dma.h:121
__IO uint32_t ErrorCode
Definition: stm32f3xx_hal_dma.h:129
uint32_t ChannelIndex
Definition: stm32f3xx_hal_dma.h:133
DMA_TypeDef * DmaBaseAddress
Definition: stm32f3xx_hal_dma.h:131
DMA_Channel_TypeDef * Instance
Definition: stm32f3xx_hal_dma.h:111
void(* XferErrorCallback)(struct __DMA_HandleTypeDef *hdma)
Definition: stm32f3xx_hal_dma.h:125
void(* XferHalfCpltCallback)(struct __DMA_HandleTypeDef *hdma)
Definition: stm32f3xx_hal_dma.h:123
void * Parent
Definition: stm32f3xx_hal_dma.h:119