25#if defined ( __ICCARM__ )
26 #pragma system_include
27#elif defined (__clang__)
28 #pragma clang system_header
31#ifndef __CORE_CM0PLUS_H_GENERIC
32#define __CORE_CM0PLUS_H_GENERIC
66#define __CM0PLUS_CMSIS_VERSION_MAIN (__CM_CMSIS_VERSION_MAIN)
67#define __CM0PLUS_CMSIS_VERSION_SUB (__CM_CMSIS_VERSION_SUB)
68#define __CM0PLUS_CMSIS_VERSION ((__CM0PLUS_CMSIS_VERSION_MAIN << 16U) | \
69 __CM0PLUS_CMSIS_VERSION_SUB )
71#define __CORTEX_M (0U)
78#if defined ( __CC_ARM )
79 #if defined __TARGET_FPU_VFP
80 #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
83#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
84 #if defined __ARM_PCS_VFP
85 #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
88#elif defined ( __GNUC__ )
89 #if defined (__VFP_FP__) && !defined(__SOFTFP__)
90 #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
93#elif defined ( __ICCARM__ )
94 #if defined __ARMVFP__
95 #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
98#elif defined ( __TI_ARM__ )
99 #if defined __TI_VFP_SUPPORT__
100 #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
103#elif defined ( __TASKING__ )
104 #if defined __FPU_VFP__
105 #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
108#elif defined ( __CSMC__ )
109 #if ( __CSMC__ & 0x400U)
110 #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
124#ifndef __CMSIS_GENERIC
126#ifndef __CORE_CM0PLUS_H_DEPENDANT
127#define __CORE_CM0PLUS_H_DEPENDANT
134#if defined __CHECK_DEVICE_DEFINES
135 #ifndef __CM0PLUS_REV
136 #define __CM0PLUS_REV 0x0000U
137 #warning "__CM0PLUS_REV not defined in device header file; using default!"
140 #ifndef __MPU_PRESENT
141 #define __MPU_PRESENT 0U
142 #warning "__MPU_PRESENT not defined in device header file; using default!"
145 #ifndef __VTOR_PRESENT
146 #define __VTOR_PRESENT 0U
147 #warning "__VTOR_PRESENT not defined in device header file; using default!"
150 #ifndef __NVIC_PRIO_BITS
151 #define __NVIC_PRIO_BITS 2U
152 #warning "__NVIC_PRIO_BITS not defined in device header file; using default!"
155 #ifndef __Vendor_SysTickConfig
156 #define __Vendor_SysTickConfig 0U
157 #warning "__Vendor_SysTickConfig not defined in device header file; using default!"
172 #define __I volatile const
178#define __IM volatile const
180#define __IOM volatile
224#define APSR_N_Pos 31U
225#define APSR_N_Msk (1UL << APSR_N_Pos)
227#define APSR_Z_Pos 30U
228#define APSR_Z_Msk (1UL << APSR_Z_Pos)
230#define APSR_C_Pos 29U
231#define APSR_C_Msk (1UL << APSR_C_Pos)
233#define APSR_V_Pos 28U
234#define APSR_V_Msk (1UL << APSR_V_Pos)
251#define IPSR_ISR_Pos 0U
252#define IPSR_ISR_Msk (0x1FFUL )
275#define xPSR_N_Pos 31U
276#define xPSR_N_Msk (1UL << xPSR_N_Pos)
278#define xPSR_Z_Pos 30U
279#define xPSR_Z_Msk (1UL << xPSR_Z_Pos)
281#define xPSR_C_Pos 29U
282#define xPSR_C_Msk (1UL << xPSR_C_Pos)
284#define xPSR_V_Pos 28U
285#define xPSR_V_Msk (1UL << xPSR_V_Pos)
287#define xPSR_T_Pos 24U
288#define xPSR_T_Msk (1UL << xPSR_T_Pos)
290#define xPSR_ISR_Pos 0U
291#define xPSR_ISR_Msk (0x1FFUL )
309#define CONTROL_SPSEL_Pos 1U
310#define CONTROL_SPSEL_Msk (1UL << CONTROL_SPSEL_Pos)
312#define CONTROL_nPRIV_Pos 0U
313#define CONTROL_nPRIV_Msk (1UL )
330 __IOM uint32_t ISER[1U];
331 uint32_t RESERVED0[31U];
332 __IOM uint32_t ICER[1U];
333 uint32_t RSERVED1[31U];
334 __IOM uint32_t ISPR[1U];
335 uint32_t RESERVED2[31U];
336 __IOM uint32_t ICPR[1U];
337 uint32_t RESERVED3[31U];
338 uint32_t RESERVED4[64U];
339 __IOM uint32_t IP[8U];
359#if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1U)
364 __IOM uint32_t AIRCR;
368 __IOM uint32_t SHP[2U];
369 __IOM uint32_t SHCSR;
373#define SCB_CPUID_IMPLEMENTER_Pos 24U
374#define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos)
376#define SCB_CPUID_VARIANT_Pos 20U
377#define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos)
379#define SCB_CPUID_ARCHITECTURE_Pos 16U
380#define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos)
382#define SCB_CPUID_PARTNO_Pos 4U
383#define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos)
385#define SCB_CPUID_REVISION_Pos 0U
386#define SCB_CPUID_REVISION_Msk (0xFUL )
389#define SCB_ICSR_NMIPENDSET_Pos 31U
390#define SCB_ICSR_NMIPENDSET_Msk (1UL << SCB_ICSR_NMIPENDSET_Pos)
392#define SCB_ICSR_PENDSVSET_Pos 28U
393#define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos)
395#define SCB_ICSR_PENDSVCLR_Pos 27U
396#define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos)
398#define SCB_ICSR_PENDSTSET_Pos 26U
399#define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos)
401#define SCB_ICSR_PENDSTCLR_Pos 25U
402#define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos)
404#define SCB_ICSR_ISRPREEMPT_Pos 23U
405#define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos)
407#define SCB_ICSR_ISRPENDING_Pos 22U
408#define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos)
410#define SCB_ICSR_VECTPENDING_Pos 12U
411#define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos)
413#define SCB_ICSR_VECTACTIVE_Pos 0U
414#define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL )
416#if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1U)
418#define SCB_VTOR_TBLOFF_Pos 8U
419#define SCB_VTOR_TBLOFF_Msk (0xFFFFFFUL << SCB_VTOR_TBLOFF_Pos)
423#define SCB_AIRCR_VECTKEY_Pos 16U
424#define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos)
426#define SCB_AIRCR_VECTKEYSTAT_Pos 16U
427#define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos)
429#define SCB_AIRCR_ENDIANESS_Pos 15U
430#define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos)
432#define SCB_AIRCR_SYSRESETREQ_Pos 2U
433#define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos)
435#define SCB_AIRCR_VECTCLRACTIVE_Pos 1U
436#define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos)
439#define SCB_SCR_SEVONPEND_Pos 4U
440#define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos)
442#define SCB_SCR_SLEEPDEEP_Pos 2U
443#define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos)
445#define SCB_SCR_SLEEPONEXIT_Pos 1U
446#define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos)
449#define SCB_CCR_STKALIGN_Pos 9U
450#define SCB_CCR_STKALIGN_Msk (1UL << SCB_CCR_STKALIGN_Pos)
452#define SCB_CCR_UNALIGN_TRP_Pos 3U
453#define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos)
456#define SCB_SHCSR_SVCALLPENDED_Pos 15U
457#define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos)
481#define SysTick_CTRL_COUNTFLAG_Pos 16U
482#define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos)
484#define SysTick_CTRL_CLKSOURCE_Pos 2U
485#define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos)
487#define SysTick_CTRL_TICKINT_Pos 1U
488#define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos)
490#define SysTick_CTRL_ENABLE_Pos 0U
491#define SysTick_CTRL_ENABLE_Msk (1UL )
494#define SysTick_LOAD_RELOAD_Pos 0U
495#define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL )
498#define SysTick_VAL_CURRENT_Pos 0U
499#define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL )
502#define SysTick_CALIB_NOREF_Pos 31U
503#define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos)
505#define SysTick_CALIB_SKEW_Pos 30U
506#define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos)
508#define SysTick_CALIB_TENMS_Pos 0U
509#define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL )
513#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U)
533#define MPU_TYPE_RALIASES 1U
536#define MPU_TYPE_IREGION_Pos 16U
537#define MPU_TYPE_IREGION_Msk (0xFFUL << MPU_TYPE_IREGION_Pos)
539#define MPU_TYPE_DREGION_Pos 8U
540#define MPU_TYPE_DREGION_Msk (0xFFUL << MPU_TYPE_DREGION_Pos)
542#define MPU_TYPE_SEPARATE_Pos 0U
543#define MPU_TYPE_SEPARATE_Msk (1UL )
546#define MPU_CTRL_PRIVDEFENA_Pos 2U
547#define MPU_CTRL_PRIVDEFENA_Msk (1UL << MPU_CTRL_PRIVDEFENA_Pos)
549#define MPU_CTRL_HFNMIENA_Pos 1U
550#define MPU_CTRL_HFNMIENA_Msk (1UL << MPU_CTRL_HFNMIENA_Pos)
552#define MPU_CTRL_ENABLE_Pos 0U
553#define MPU_CTRL_ENABLE_Msk (1UL )
556#define MPU_RNR_REGION_Pos 0U
557#define MPU_RNR_REGION_Msk (0xFFUL )
560#define MPU_RBAR_ADDR_Pos 8U
561#define MPU_RBAR_ADDR_Msk (0xFFFFFFUL << MPU_RBAR_ADDR_Pos)
563#define MPU_RBAR_VALID_Pos 4U
564#define MPU_RBAR_VALID_Msk (1UL << MPU_RBAR_VALID_Pos)
566#define MPU_RBAR_REGION_Pos 0U
567#define MPU_RBAR_REGION_Msk (0xFUL )
570#define MPU_RASR_ATTRS_Pos 16U
571#define MPU_RASR_ATTRS_Msk (0xFFFFUL << MPU_RASR_ATTRS_Pos)
573#define MPU_RASR_XN_Pos 28U
574#define MPU_RASR_XN_Msk (1UL << MPU_RASR_XN_Pos)
576#define MPU_RASR_AP_Pos 24U
577#define MPU_RASR_AP_Msk (0x7UL << MPU_RASR_AP_Pos)
579#define MPU_RASR_TEX_Pos 19U
580#define MPU_RASR_TEX_Msk (0x7UL << MPU_RASR_TEX_Pos)
582#define MPU_RASR_S_Pos 18U
583#define MPU_RASR_S_Msk (1UL << MPU_RASR_S_Pos)
585#define MPU_RASR_C_Pos 17U
586#define MPU_RASR_C_Msk (1UL << MPU_RASR_C_Pos)
588#define MPU_RASR_B_Pos 16U
589#define MPU_RASR_B_Msk (1UL << MPU_RASR_B_Pos)
591#define MPU_RASR_SRD_Pos 8U
592#define MPU_RASR_SRD_Msk (0xFFUL << MPU_RASR_SRD_Pos)
594#define MPU_RASR_SIZE_Pos 1U
595#define MPU_RASR_SIZE_Msk (0x1FUL << MPU_RASR_SIZE_Pos)
597#define MPU_RASR_ENABLE_Pos 0U
598#define MPU_RASR_ENABLE_Msk (1UL )
627#define _VAL2FLD(field, value) (((uint32_t)(value) << field ## _Pos) & field ## _Msk)
635#define _FLD2VAL(field, value) (((uint32_t)(value) & field ## _Msk) >> field ## _Pos)
648#define SCS_BASE (0xE000E000UL)
649#define SysTick_BASE (SCS_BASE + 0x0010UL)
650#define NVIC_BASE (SCS_BASE + 0x0100UL)
651#define SCB_BASE (SCS_BASE + 0x0D00UL)
653#define SCB ((SCB_Type *) SCB_BASE )
654#define SysTick ((SysTick_Type *) SysTick_BASE )
655#define NVIC ((NVIC_Type *) NVIC_BASE )
657#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U)
658 #define MPU_BASE (SCS_BASE + 0x0D90UL)
659 #define MPU ((MPU_Type *) MPU_BASE )
687#ifdef CMSIS_NVIC_VIRTUAL
688 #ifndef CMSIS_NVIC_VIRTUAL_HEADER_FILE
689 #define CMSIS_NVIC_VIRTUAL_HEADER_FILE "cmsis_nvic_virtual.h"
691 #include CMSIS_NVIC_VIRTUAL_HEADER_FILE
693 #define NVIC_SetPriorityGrouping __NVIC_SetPriorityGrouping
694 #define NVIC_GetPriorityGrouping __NVIC_GetPriorityGrouping
695 #define NVIC_EnableIRQ __NVIC_EnableIRQ
696 #define NVIC_GetEnableIRQ __NVIC_GetEnableIRQ
697 #define NVIC_DisableIRQ __NVIC_DisableIRQ
698 #define NVIC_GetPendingIRQ __NVIC_GetPendingIRQ
699 #define NVIC_SetPendingIRQ __NVIC_SetPendingIRQ
700 #define NVIC_ClearPendingIRQ __NVIC_ClearPendingIRQ
702 #define NVIC_SetPriority __NVIC_SetPriority
703 #define NVIC_GetPriority __NVIC_GetPriority
704 #define NVIC_SystemReset __NVIC_SystemReset
707#ifdef CMSIS_VECTAB_VIRTUAL
708 #ifndef CMSIS_VECTAB_VIRTUAL_HEADER_FILE
709 #define CMSIS_VECTAB_VIRTUAL_HEADER_FILE "cmsis_vectab_virtual.h"
711 #include CMSIS_VECTAB_VIRTUAL_HEADER_FILE
713 #define NVIC_SetVector __NVIC_SetVector
714 #define NVIC_GetVector __NVIC_GetVector
717#define NVIC_USER_IRQ_OFFSET 16
721#define EXC_RETURN_HANDLER (0xFFFFFFF1UL)
722#define EXC_RETURN_THREAD_MSP (0xFFFFFFF9UL)
723#define EXC_RETURN_THREAD_PSP (0xFFFFFFFDUL)
728#define _BIT_SHIFT(IRQn) ( ((((uint32_t)(int32_t)(IRQn)) ) & 0x03UL) * 8UL)
729#define _SHP_IDX(IRQn) ( (((((uint32_t)(int32_t)(IRQn)) & 0x0FUL)-8UL) >> 2UL) )
730#define _IP_IDX(IRQn) ( (((uint32_t)(int32_t)(IRQn)) >> 2UL) )
732#define __NVIC_SetPriorityGrouping(X) (void)(X)
733#define __NVIC_GetPriorityGrouping() (0U)
743 if ((int32_t)(IRQn) >= 0)
745 NVIC->ISER[0U] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
760 if ((int32_t)(IRQn) >= 0)
762 return((uint32_t)(((
NVIC->ISER[0U] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
779 if ((int32_t)(IRQn) >= 0)
781 NVIC->ICER[0U] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
798 if ((int32_t)(IRQn) >= 0)
800 return((uint32_t)(((
NVIC->ISPR[0U] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
817 if ((int32_t)(IRQn) >= 0)
819 NVIC->ISPR[0U] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
832 if ((int32_t)(IRQn) >= 0)
834 NVIC->ICPR[0U] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
850 if ((int32_t)(IRQn) >= 0)
875 if ((int32_t)(IRQn) >= 0)
899 uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL);
900 uint32_t PreemptPriorityBits;
901 uint32_t SubPriorityBits;
904 SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(
__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(
__NVIC_PRIO_BITS));
907 ((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits) |
908 ((SubPriority & (uint32_t)((1UL << (SubPriorityBits )) - 1UL)))
926 uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL);
927 uint32_t PreemptPriorityBits;
928 uint32_t SubPriorityBits;
931 SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(
__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(
__NVIC_PRIO_BITS));
933 *pPreemptPriority = (Priority >> SubPriorityBits) & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL);
934 *pSubPriority = (Priority ) & (uint32_t)((1UL << (SubPriorityBits )) - 1UL);
950#if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1U)
951 uint32_t *vectors = (uint32_t *)
SCB->VTOR;
953 uint32_t *vectors = (uint32_t *)0x0U;
969#if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1U)
970 uint32_t *vectors = (uint32_t *)
SCB->VTOR;
972 uint32_t *vectors = (uint32_t *)0x0U;
1001#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U)
1041#if defined (__Vendor_SysTickConfig) && (__Vendor_SysTickConfig == 0U)
1061 SysTick->LOAD = (uint32_t)(ticks - 1UL);
#define __NO_RETURN
Definition: cmsis_armcc.h:65
#define __STATIC_INLINE
Definition: cmsis_armcc.h:59
CMSIS compiler generic header file.
CMSIS Core(M) Version definitions.
#define __IM
Definition: core_cm0plus.h:178
#define __IOM
Definition: core_cm0plus.h:180
#define __DSB()
Data Synchronization Barrier.
Definition: cmsis_armcc.h:429
#define __ISB()
Instruction Synchronization Barrier.
Definition: cmsis_armcc.h:418
#define __NOP
No Operation.
Definition: cmsis_armcc.h:387
__NO_RETURN __STATIC_INLINE void __NVIC_SystemReset(void)
System Reset.
Definition: core_armv8mbl.h:1581
__STATIC_INLINE void __NVIC_SetVector(IRQn_Type IRQn, uint32_t vector)
Set Interrupt Vector.
Definition: core_armv8mbl.h:1547
__STATIC_INLINE void NVIC_DecodePriority(uint32_t Priority, uint32_t PriorityGroup, uint32_t *const pPreemptPriority, uint32_t *const pSubPriority)
Decode Priority.
Definition: core_armv8mbl.h:1523
#define _IP_IDX(IRQn)
Definition: core_cm0plus.h:730
__STATIC_INLINE uint32_t __NVIC_GetVector(IRQn_Type IRQn)
Get Interrupt Vector.
Definition: core_armv8mbl.h:1566
__STATIC_INLINE void __NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority)
Set Interrupt Priority.
Definition: core_armv8mbl.h:1447
#define _BIT_SHIFT(IRQn)
Definition: core_cm0plus.h:728
__STATIC_INLINE void __NVIC_ClearPendingIRQ(IRQn_Type IRQn)
Clear Pending Interrupt.
Definition: core_armv8mbl.h:1341
__STATIC_INLINE uint32_t __NVIC_GetPendingIRQ(IRQn_Type IRQn)
Get Pending Interrupt.
Definition: core_armv8mbl.h:1307
__STATIC_INLINE uint32_t SCB_GetFPUType(void)
get FPU type
Definition: core_armv8mbl.h:1791
__STATIC_INLINE void __NVIC_EnableIRQ(IRQn_Type IRQn)
Enable Interrupt.
Definition: core_armv8mbl.h:1252
#define NVIC_USER_IRQ_OFFSET
Definition: core_cm0plus.h:717
__STATIC_INLINE void __NVIC_SetPendingIRQ(IRQn_Type IRQn)
Set Pending Interrupt.
Definition: core_armv8mbl.h:1326
__STATIC_INLINE uint32_t __NVIC_GetEnableIRQ(IRQn_Type IRQn)
Get Interrupt Enable status.
Definition: core_armv8mbl.h:1269
__STATIC_INLINE uint32_t NVIC_EncodePriority(uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority)
Encode Priority.
Definition: core_armv8mbl.h:1496
__STATIC_INLINE void __NVIC_DisableIRQ(IRQn_Type IRQn)
Disable Interrupt.
Definition: core_armv8mbl.h:1288
#define NVIC_SetPriority
Definition: core_cm0plus.h:702
__STATIC_INLINE uint32_t __NVIC_GetPriority(IRQn_Type IRQn)
Get Interrupt Priority.
Definition: core_armv8mbl.h:1471
#define _SHP_IDX(IRQn)
Definition: core_cm0plus.h:729
uint32_t ISR
Definition: core_cm0plus.h:262
uint32_t T
Definition: core_cm0plus.h:264
uint32_t ISR
Definition: core_cm0plus.h:244
uint32_t SPSEL
Definition: core_cm0plus.h:302
uint32_t Z
Definition: core_cm0plus.h:217
uint32_t V
Definition: core_cm0plus.h:215
uint32_t nPRIV
Definition: core_cm0plus.h:301
uint32_t N
Definition: core_cm0plus.h:218
uint32_t _reserved0
Definition: core_cm0plus.h:245
uint32_t _reserved0
Definition: core_cm0plus.h:263
uint32_t _reserved1
Definition: core_cm0plus.h:265
uint32_t V
Definition: core_cm0plus.h:266
uint32_t C
Definition: core_cm0plus.h:267
uint32_t _reserved1
Definition: core_cm0plus.h:303
uint32_t Z
Definition: core_cm0plus.h:268
uint32_t C
Definition: core_cm0plus.h:216
uint32_t _reserved0
Definition: core_cm0plus.h:214
uint32_t N
Definition: core_cm0plus.h:269
#define SCB_AIRCR_VECTKEY_Pos
Definition: core_cm0plus.h:423
#define SCB_AIRCR_SYSRESETREQ_Msk
Definition: core_cm0plus.h:433
#define SysTick_CTRL_ENABLE_Msk
Definition: core_cm0plus.h:491
#define SysTick_LOAD_RELOAD_Msk
Definition: core_cm0plus.h:495
#define SysTick_CTRL_TICKINT_Msk
Definition: core_cm0plus.h:488
#define SysTick_CTRL_CLKSOURCE_Msk
Definition: core_cm0plus.h:485
#define SCB
Definition: core_cm0plus.h:653
#define NVIC
Definition: core_cm0plus.h:655
#define SysTick
Definition: core_cm0plus.h:654
#define __NVIC_PRIO_BITS
Definition: stm32f303xe.h:49
IRQn_Type
STM32F303xE devices Interrupt Number Definition, according to the selected device in Library_configur...
Definition: stm32f303xe.h:66
@ SysTick_IRQn
Definition: stm32f303xe.h:76
Structure type to access the Nested Vectored Interrupt Controller (NVIC).
Definition: core_armv8mbl.h:352
Structure type to access the System Control Block (SCB).
Definition: core_armv8mbl.h:382
Structure type to access the System Timer (SysTick).
Definition: core_armv8mbl.h:559
Union type to access the Application Program Status Register (APSR).
Definition: core_armv8mbl.h:234
Union type to access the Control Registers (CONTROL).
Definition: core_armv8mbl.h:321
Union type to access the Interrupt Program Status Register (IPSR).
Definition: core_armv8mbl.h:264
Union type to access the Special-Purpose Program Status Registers (xPSR).
Definition: core_armv8mbl.h:282