Core Register type definitions. More...

Modules
	Nested Vectored Interrupt Controller (NVIC)
	Type definitions for the NVIC Registers.

Classes
union	APSR_Type
	Union type to access the Application Program Status Register (APSR). More...

union	IPSR_Type
	Union type to access the Interrupt Program Status Register (IPSR). More...

union	xPSR_Type
	Union type to access the Special-Purpose Program Status Registers (xPSR). More...

union	CONTROL_Type
	Union type to access the Control Registers (CONTROL). More...

#define	APSR_N_Pos 31U

#define	APSR_N_Msk (1UL << APSR_N_Pos)

#define	APSR_Z_Pos 30U

#define	APSR_Z_Msk (1UL << APSR_Z_Pos)

#define	APSR_C_Pos 29U

#define	APSR_C_Msk (1UL << APSR_C_Pos)

#define	APSR_V_Pos 28U

#define	APSR_V_Msk (1UL << APSR_V_Pos)

#define	IPSR_ISR_Pos 0U

#define	IPSR_ISR_Msk (0x1FFUL /<< IPSR_ISR_Pos/)

#define	xPSR_N_Pos 31U

#define	xPSR_N_Msk (1UL << xPSR_N_Pos)

#define	xPSR_Z_Pos 30U

#define	xPSR_Z_Msk (1UL << xPSR_Z_Pos)

#define	xPSR_C_Pos 29U

#define	xPSR_C_Msk (1UL << xPSR_C_Pos)

#define	xPSR_V_Pos 28U

#define	xPSR_V_Msk (1UL << xPSR_V_Pos)

#define	xPSR_T_Pos 24U

#define	xPSR_T_Msk (1UL << xPSR_T_Pos)

#define	xPSR_ISR_Pos 0U

#define	xPSR_ISR_Msk (0x1FFUL /<< xPSR_ISR_Pos/)

#define	CONTROL_SPSEL_Pos 1U

#define	CONTROL_SPSEL_Msk (1UL << CONTROL_SPSEL_Pos)

#define	CONTROL_nPRIV_Pos 0U

#define	CONTROL_nPRIV_Msk (1UL /<< CONTROL_nPRIV_Pos/)

#define	APSR_N_Pos 31U

#define	APSR_N_Msk (1UL << APSR_N_Pos)

#define	APSR_Z_Pos 30U

#define	APSR_Z_Msk (1UL << APSR_Z_Pos)

#define	APSR_C_Pos 29U

#define	APSR_C_Msk (1UL << APSR_C_Pos)

#define	APSR_V_Pos 28U

#define	APSR_V_Msk (1UL << APSR_V_Pos)

#define	APSR_Q_Pos 27U

#define	APSR_Q_Msk (1UL << APSR_Q_Pos)

#define	APSR_GE_Pos 16U

#define	APSR_GE_Msk (0xFUL << APSR_GE_Pos)

#define	IPSR_ISR_Pos 0U

#define	IPSR_ISR_Msk (0x1FFUL /<< IPSR_ISR_Pos/)

#define	xPSR_N_Pos 31U

#define	xPSR_N_Msk (1UL << xPSR_N_Pos)

#define	xPSR_Z_Pos 30U

#define	xPSR_Z_Msk (1UL << xPSR_Z_Pos)

#define	xPSR_C_Pos 29U

#define	xPSR_C_Msk (1UL << xPSR_C_Pos)

#define	xPSR_V_Pos 28U

#define	xPSR_V_Msk (1UL << xPSR_V_Pos)

#define	xPSR_Q_Pos 27U

#define	xPSR_Q_Msk (1UL << xPSR_Q_Pos)

#define	xPSR_IT_Pos 25U

#define	xPSR_IT_Msk (3UL << xPSR_IT_Pos)

#define	xPSR_T_Pos 24U

#define	xPSR_T_Msk (1UL << xPSR_T_Pos)

#define	xPSR_GE_Pos 16U

#define	xPSR_GE_Msk (0xFUL << xPSR_GE_Pos)

#define	xPSR_ISR_Pos 0U

#define	xPSR_ISR_Msk (0x1FFUL /<< xPSR_ISR_Pos/)

#define	CONTROL_SFPA_Pos 3U

#define	CONTROL_SFPA_Msk (1UL << CONTROL_SFPA_Pos)

#define	CONTROL_FPCA_Pos 2U

#define	CONTROL_FPCA_Msk (1UL << CONTROL_FPCA_Pos)

#define	CONTROL_SPSEL_Pos 1U

#define	CONTROL_SPSEL_Msk (1UL << CONTROL_SPSEL_Pos)

#define	CONTROL_nPRIV_Pos 0U

#define	CONTROL_nPRIV_Msk (1UL /<< CONTROL_nPRIV_Pos/)

#define	APSR_N_Pos 31U

#define	APSR_N_Msk (1UL << APSR_N_Pos)

#define	APSR_Z_Pos 30U

#define	APSR_Z_Msk (1UL << APSR_Z_Pos)

#define	APSR_C_Pos 29U

#define	APSR_C_Msk (1UL << APSR_C_Pos)

#define	APSR_V_Pos 28U

#define	APSR_V_Msk (1UL << APSR_V_Pos)

#define	IPSR_ISR_Pos 0U

#define	IPSR_ISR_Msk (0x1FFUL /<< IPSR_ISR_Pos/)

#define	xPSR_N_Pos 31U

#define	xPSR_N_Msk (1UL << xPSR_N_Pos)

#define	xPSR_Z_Pos 30U

#define	xPSR_Z_Msk (1UL << xPSR_Z_Pos)

#define	xPSR_C_Pos 29U

#define	xPSR_C_Msk (1UL << xPSR_C_Pos)

#define	xPSR_V_Pos 28U

#define	xPSR_V_Msk (1UL << xPSR_V_Pos)

#define	xPSR_T_Pos 24U

#define	xPSR_T_Msk (1UL << xPSR_T_Pos)

#define	xPSR_ISR_Pos 0U

#define	xPSR_ISR_Msk (0x1FFUL /<< xPSR_ISR_Pos/)

#define	CONTROL_SPSEL_Pos 1U

#define	CONTROL_SPSEL_Msk (1UL << CONTROL_SPSEL_Pos)

#define	APSR_N_Pos 31U

#define	APSR_N_Msk (1UL << APSR_N_Pos)

#define	APSR_Z_Pos 30U

#define	APSR_Z_Msk (1UL << APSR_Z_Pos)

#define	APSR_C_Pos 29U

#define	APSR_C_Msk (1UL << APSR_C_Pos)

#define	APSR_V_Pos 28U

#define	APSR_V_Msk (1UL << APSR_V_Pos)

#define	IPSR_ISR_Pos 0U

#define	IPSR_ISR_Msk (0x1FFUL /<< IPSR_ISR_Pos/)

#define	xPSR_N_Pos 31U

#define	xPSR_N_Msk (1UL << xPSR_N_Pos)

#define	xPSR_Z_Pos 30U

#define	xPSR_Z_Msk (1UL << xPSR_Z_Pos)

#define	xPSR_C_Pos 29U

#define	xPSR_C_Msk (1UL << xPSR_C_Pos)

#define	xPSR_V_Pos 28U

#define	xPSR_V_Msk (1UL << xPSR_V_Pos)

#define	xPSR_T_Pos 24U

#define	xPSR_T_Msk (1UL << xPSR_T_Pos)

#define	xPSR_ISR_Pos 0U

#define	xPSR_ISR_Msk (0x1FFUL /<< xPSR_ISR_Pos/)

#define	CONTROL_SPSEL_Pos 1U

#define	CONTROL_SPSEL_Msk (1UL << CONTROL_SPSEL_Pos)

#define	CONTROL_nPRIV_Pos 0U

#define	CONTROL_nPRIV_Msk (1UL /<< CONTROL_nPRIV_Pos/)

#define	APSR_N_Pos 31U

#define	APSR_N_Msk (1UL << APSR_N_Pos)

#define	APSR_Z_Pos 30U

#define	APSR_Z_Msk (1UL << APSR_Z_Pos)

#define	APSR_C_Pos 29U

#define	APSR_C_Msk (1UL << APSR_C_Pos)

#define	APSR_V_Pos 28U

#define	APSR_V_Msk (1UL << APSR_V_Pos)

#define	IPSR_ISR_Pos 0U

#define	IPSR_ISR_Msk (0x1FFUL /<< IPSR_ISR_Pos/)

#define	xPSR_N_Pos 31U

#define	xPSR_N_Msk (1UL << xPSR_N_Pos)

#define	xPSR_Z_Pos 30U

#define	xPSR_Z_Msk (1UL << xPSR_Z_Pos)

#define	xPSR_C_Pos 29U

#define	xPSR_C_Msk (1UL << xPSR_C_Pos)

#define	xPSR_V_Pos 28U

#define	xPSR_V_Msk (1UL << xPSR_V_Pos)

#define	xPSR_T_Pos 24U

#define	xPSR_T_Msk (1UL << xPSR_T_Pos)

#define	xPSR_ISR_Pos 0U

#define	xPSR_ISR_Msk (0x1FFUL /<< xPSR_ISR_Pos/)

#define	CONTROL_SPSEL_Pos 1U

#define	CONTROL_SPSEL_Msk (1UL << CONTROL_SPSEL_Pos)

#define	APSR_N_Pos 31U

#define	APSR_N_Msk (1UL << APSR_N_Pos)

#define	APSR_Z_Pos 30U

#define	APSR_Z_Msk (1UL << APSR_Z_Pos)

#define	APSR_C_Pos 29U

#define	APSR_C_Msk (1UL << APSR_C_Pos)

#define	APSR_V_Pos 28U

#define	APSR_V_Msk (1UL << APSR_V_Pos)

#define	IPSR_ISR_Pos 0U

#define	IPSR_ISR_Msk (0x1FFUL /<< IPSR_ISR_Pos/)

#define	xPSR_N_Pos 31U

#define	xPSR_N_Msk (1UL << xPSR_N_Pos)

#define	xPSR_Z_Pos 30U

#define	xPSR_Z_Msk (1UL << xPSR_Z_Pos)

#define	xPSR_C_Pos 29U

#define	xPSR_C_Msk (1UL << xPSR_C_Pos)

#define	xPSR_V_Pos 28U

#define	xPSR_V_Msk (1UL << xPSR_V_Pos)

#define	xPSR_T_Pos 24U

#define	xPSR_T_Msk (1UL << xPSR_T_Pos)

#define	xPSR_ISR_Pos 0U

#define	xPSR_ISR_Msk (0x1FFUL /<< xPSR_ISR_Pos/)

#define	CONTROL_SPSEL_Pos 1U

#define	CONTROL_SPSEL_Msk (1UL << CONTROL_SPSEL_Pos)

#define	CONTROL_nPRIV_Pos 0U

#define	CONTROL_nPRIV_Msk (1UL /<< CONTROL_nPRIV_Pos/)

#define	APSR_N_Pos 31U

#define	APSR_N_Msk (1UL << APSR_N_Pos)

#define	APSR_Z_Pos 30U

#define	APSR_Z_Msk (1UL << APSR_Z_Pos)

#define	APSR_C_Pos 29U

#define	APSR_C_Msk (1UL << APSR_C_Pos)

#define	APSR_V_Pos 28U

#define	APSR_V_Msk (1UL << APSR_V_Pos)

#define	APSR_Q_Pos 27U

#define	APSR_Q_Msk (1UL << APSR_Q_Pos)

#define	IPSR_ISR_Pos 0U

#define	IPSR_ISR_Msk (0x1FFUL /<< IPSR_ISR_Pos/)

#define	xPSR_N_Pos 31U

#define	xPSR_N_Msk (1UL << xPSR_N_Pos)

#define	xPSR_Z_Pos 30U

#define	xPSR_Z_Msk (1UL << xPSR_Z_Pos)

#define	xPSR_C_Pos 29U

#define	xPSR_C_Msk (1UL << xPSR_C_Pos)

#define	xPSR_V_Pos 28U

#define	xPSR_V_Msk (1UL << xPSR_V_Pos)

#define	xPSR_Q_Pos 27U

#define	xPSR_Q_Msk (1UL << xPSR_Q_Pos)

#define	xPSR_ICI_IT_2_Pos 25U

#define	xPSR_ICI_IT_2_Msk (3UL << xPSR_ICI_IT_2_Pos)

#define	xPSR_T_Pos 24U

#define	xPSR_T_Msk (1UL << xPSR_T_Pos)

#define	xPSR_ICI_IT_1_Pos 10U

#define	xPSR_ICI_IT_1_Msk (0x3FUL << xPSR_ICI_IT_1_Pos)

#define	xPSR_ISR_Pos 0U

#define	xPSR_ISR_Msk (0x1FFUL /<< xPSR_ISR_Pos/)

#define	CONTROL_SPSEL_Pos 1U

#define	CONTROL_SPSEL_Msk (1UL << CONTROL_SPSEL_Pos)

#define	CONTROL_nPRIV_Pos 0U

#define	CONTROL_nPRIV_Msk (1UL /<< CONTROL_nPRIV_Pos/)

#define	APSR_N_Pos 31U

#define	APSR_N_Msk (1UL << APSR_N_Pos)

#define	APSR_Z_Pos 30U

#define	APSR_Z_Msk (1UL << APSR_Z_Pos)

#define	APSR_C_Pos 29U

#define	APSR_C_Msk (1UL << APSR_C_Pos)

#define	APSR_V_Pos 28U

#define	APSR_V_Msk (1UL << APSR_V_Pos)

#define	APSR_Q_Pos 27U

#define	APSR_Q_Msk (1UL << APSR_Q_Pos)

#define	APSR_GE_Pos 16U

#define	APSR_GE_Msk (0xFUL << APSR_GE_Pos)

#define	IPSR_ISR_Pos 0U

#define	IPSR_ISR_Msk (0x1FFUL /<< IPSR_ISR_Pos/)

#define	xPSR_N_Pos 31U

#define	xPSR_N_Msk (1UL << xPSR_N_Pos)

#define	xPSR_Z_Pos 30U

#define	xPSR_Z_Msk (1UL << xPSR_Z_Pos)

#define	xPSR_C_Pos 29U

#define	xPSR_C_Msk (1UL << xPSR_C_Pos)

#define	xPSR_V_Pos 28U

#define	xPSR_V_Msk (1UL << xPSR_V_Pos)

#define	xPSR_Q_Pos 27U

#define	xPSR_Q_Msk (1UL << xPSR_Q_Pos)

#define	xPSR_IT_Pos 25U

#define	xPSR_IT_Msk (3UL << xPSR_IT_Pos)

#define	xPSR_T_Pos 24U

#define	xPSR_T_Msk (1UL << xPSR_T_Pos)

#define	xPSR_GE_Pos 16U

#define	xPSR_GE_Msk (0xFUL << xPSR_GE_Pos)

#define	xPSR_ISR_Pos 0U

#define	xPSR_ISR_Msk (0x1FFUL /<< xPSR_ISR_Pos/)

#define	CONTROL_SFPA_Pos 3U

#define	CONTROL_SFPA_Msk (1UL << CONTROL_SFPA_Pos)

#define	CONTROL_FPCA_Pos 2U

#define	CONTROL_FPCA_Msk (1UL << CONTROL_FPCA_Pos)

#define	CONTROL_SPSEL_Pos 1U

#define	CONTROL_SPSEL_Msk (1UL << CONTROL_SPSEL_Pos)

#define	CONTROL_nPRIV_Pos 0U

#define	CONTROL_nPRIV_Msk (1UL /<< CONTROL_nPRIV_Pos/)

#define	APSR_N_Pos 31U

#define	APSR_N_Msk (1UL << APSR_N_Pos)

#define	APSR_Z_Pos 30U

#define	APSR_Z_Msk (1UL << APSR_Z_Pos)

#define	APSR_C_Pos 29U

#define	APSR_C_Msk (1UL << APSR_C_Pos)

#define	APSR_V_Pos 28U

#define	APSR_V_Msk (1UL << APSR_V_Pos)

#define	APSR_Q_Pos 27U

#define	APSR_Q_Msk (1UL << APSR_Q_Pos)

#define	APSR_GE_Pos 16U

#define	APSR_GE_Msk (0xFUL << APSR_GE_Pos)

#define	IPSR_ISR_Pos 0U

#define	IPSR_ISR_Msk (0x1FFUL /<< IPSR_ISR_Pos/)

#define	xPSR_N_Pos 31U

#define	xPSR_N_Msk (1UL << xPSR_N_Pos)

#define	xPSR_Z_Pos 30U

#define	xPSR_Z_Msk (1UL << xPSR_Z_Pos)

#define	xPSR_C_Pos 29U

#define	xPSR_C_Msk (1UL << xPSR_C_Pos)

#define	xPSR_V_Pos 28U

#define	xPSR_V_Msk (1UL << xPSR_V_Pos)

#define	xPSR_Q_Pos 27U

#define	xPSR_Q_Msk (1UL << xPSR_Q_Pos)

#define	xPSR_ICI_IT_2_Pos 25U

#define	xPSR_ICI_IT_2_Msk (3UL << xPSR_ICI_IT_2_Pos)

#define	xPSR_T_Pos 24U

#define	xPSR_T_Msk (1UL << xPSR_T_Pos)

#define	xPSR_GE_Pos 16U

#define	xPSR_GE_Msk (0xFUL << xPSR_GE_Pos)

#define	xPSR_ICI_IT_1_Pos 10U

#define	xPSR_ICI_IT_1_Msk (0x3FUL << xPSR_ICI_IT_1_Pos)

#define	xPSR_ISR_Pos 0U

#define	xPSR_ISR_Msk (0x1FFUL /<< xPSR_ISR_Pos/)

#define	CONTROL_FPCA_Pos 2U

#define	CONTROL_FPCA_Msk (1UL << CONTROL_FPCA_Pos)

#define	CONTROL_SPSEL_Pos 1U

#define	CONTROL_SPSEL_Msk (1UL << CONTROL_SPSEL_Pos)

#define	CONTROL_nPRIV_Pos 0U

#define	CONTROL_nPRIV_Msk (1UL /<< CONTROL_nPRIV_Pos/)

#define	APSR_N_Pos 31U

#define	APSR_N_Msk (1UL << APSR_N_Pos)

#define	APSR_Z_Pos 30U

#define	APSR_Z_Msk (1UL << APSR_Z_Pos)

#define	APSR_C_Pos 29U

#define	APSR_C_Msk (1UL << APSR_C_Pos)

#define	APSR_V_Pos 28U

#define	APSR_V_Msk (1UL << APSR_V_Pos)

#define	APSR_Q_Pos 27U

#define	APSR_Q_Msk (1UL << APSR_Q_Pos)

#define	APSR_GE_Pos 16U

#define	APSR_GE_Msk (0xFUL << APSR_GE_Pos)

#define	IPSR_ISR_Pos 0U

#define	IPSR_ISR_Msk (0x1FFUL /<< IPSR_ISR_Pos/)

#define	xPSR_N_Pos 31U

#define	xPSR_N_Msk (1UL << xPSR_N_Pos)

#define	xPSR_Z_Pos 30U

#define	xPSR_Z_Msk (1UL << xPSR_Z_Pos)

#define	xPSR_C_Pos 29U

#define	xPSR_C_Msk (1UL << xPSR_C_Pos)

#define	xPSR_V_Pos 28U

#define	xPSR_V_Msk (1UL << xPSR_V_Pos)

#define	xPSR_Q_Pos 27U

#define	xPSR_Q_Msk (1UL << xPSR_Q_Pos)

#define	xPSR_ICI_IT_2_Pos 25U

#define	xPSR_ICI_IT_2_Msk (3UL << xPSR_ICI_IT_2_Pos)

#define	xPSR_T_Pos 24U

#define	xPSR_T_Msk (1UL << xPSR_T_Pos)

#define	xPSR_GE_Pos 16U

#define	xPSR_GE_Msk (0xFUL << xPSR_GE_Pos)

#define	xPSR_ICI_IT_1_Pos 10U

#define	xPSR_ICI_IT_1_Msk (0x3FUL << xPSR_ICI_IT_1_Pos)

#define	xPSR_ISR_Pos 0U

#define	xPSR_ISR_Msk (0x1FFUL /<< xPSR_ISR_Pos/)

#define	CONTROL_FPCA_Pos 2U

#define	CONTROL_FPCA_Msk (1UL << CONTROL_FPCA_Pos)

#define	CONTROL_SPSEL_Pos 1U

#define	CONTROL_SPSEL_Msk (1UL << CONTROL_SPSEL_Pos)

#define	CONTROL_nPRIV_Pos 0U

#define	CONTROL_nPRIV_Msk (1UL /<< CONTROL_nPRIV_Pos/)

#define	APSR_N_Pos 31U

#define	APSR_N_Msk (1UL << APSR_N_Pos)

#define	APSR_Z_Pos 30U

#define	APSR_Z_Msk (1UL << APSR_Z_Pos)

#define	APSR_C_Pos 29U

#define	APSR_C_Msk (1UL << APSR_C_Pos)

#define	APSR_V_Pos 28U

#define	APSR_V_Msk (1UL << APSR_V_Pos)

#define	IPSR_ISR_Pos 0U

#define	IPSR_ISR_Msk (0x1FFUL /<< IPSR_ISR_Pos/)

#define	xPSR_N_Pos 31U

#define	xPSR_N_Msk (1UL << xPSR_N_Pos)

#define	xPSR_Z_Pos 30U

#define	xPSR_Z_Msk (1UL << xPSR_Z_Pos)

#define	xPSR_C_Pos 29U

#define	xPSR_C_Msk (1UL << xPSR_C_Pos)

#define	xPSR_V_Pos 28U

#define	xPSR_V_Msk (1UL << xPSR_V_Pos)

#define	xPSR_T_Pos 24U

#define	xPSR_T_Msk (1UL << xPSR_T_Pos)

#define	xPSR_ISR_Pos 0U

#define	xPSR_ISR_Msk (0x1FFUL /<< xPSR_ISR_Pos/)

#define	CONTROL_SPSEL_Pos 1U

#define	CONTROL_SPSEL_Msk (1UL << CONTROL_SPSEL_Pos)

#define	APSR_N_Pos 31U

#define	APSR_N_Msk (1UL << APSR_N_Pos)

#define	APSR_Z_Pos 30U

#define	APSR_Z_Msk (1UL << APSR_Z_Pos)

#define	APSR_C_Pos 29U

#define	APSR_C_Msk (1UL << APSR_C_Pos)

#define	APSR_V_Pos 28U

#define	APSR_V_Msk (1UL << APSR_V_Pos)

#define	APSR_Q_Pos 27U

#define	APSR_Q_Msk (1UL << APSR_Q_Pos)

#define	IPSR_ISR_Pos 0U

#define	IPSR_ISR_Msk (0x1FFUL /<< IPSR_ISR_Pos/)

#define	xPSR_N_Pos 31U

#define	xPSR_N_Msk (1UL << xPSR_N_Pos)

#define	xPSR_Z_Pos 30U

#define	xPSR_Z_Msk (1UL << xPSR_Z_Pos)

#define	xPSR_C_Pos 29U

#define	xPSR_C_Msk (1UL << xPSR_C_Pos)

#define	xPSR_V_Pos 28U

#define	xPSR_V_Msk (1UL << xPSR_V_Pos)

#define	xPSR_Q_Pos 27U

#define	xPSR_Q_Msk (1UL << xPSR_Q_Pos)

#define	xPSR_ICI_IT_2_Pos 25U

#define	xPSR_ICI_IT_2_Msk (3UL << xPSR_ICI_IT_2_Pos)

#define	xPSR_T_Pos 24U

#define	xPSR_T_Msk (1UL << xPSR_T_Pos)

#define	xPSR_ICI_IT_1_Pos 10U

#define	xPSR_ICI_IT_1_Msk (0x3FUL << xPSR_ICI_IT_1_Pos)

#define	xPSR_ISR_Pos 0U

#define	xPSR_ISR_Msk (0x1FFUL /<< xPSR_ISR_Pos/)

#define	CONTROL_SPSEL_Pos 1U

#define	CONTROL_SPSEL_Msk (1UL << CONTROL_SPSEL_Pos)

#define	CONTROL_nPRIV_Pos 0U

#define	CONTROL_nPRIV_Msk (1UL /<< CONTROL_nPRIV_Pos/)

Detailed Description

Core Register type definitions.

Macro Definition Documentation

◆ APSR_C_Msk [1/12]

#define APSR_C_Msk (1UL << APSR_C_Pos)

APSR: C Mask

◆ APSR_C_Msk [2/12]

#define APSR_C_Msk (1UL << APSR_C_Pos)

APSR: C Mask

◆ APSR_C_Msk [3/12]

#define APSR_C_Msk (1UL << APSR_C_Pos)

APSR: C Mask

◆ APSR_C_Msk [4/12]

#define APSR_C_Msk (1UL << APSR_C_Pos)

APSR: C Mask

◆ APSR_C_Msk [5/12]

#define APSR_C_Msk (1UL << APSR_C_Pos)

APSR: C Mask

◆ APSR_C_Msk [6/12]

#define APSR_C_Msk (1UL << APSR_C_Pos)

APSR: C Mask

◆ APSR_C_Msk [7/12]

#define APSR_C_Msk (1UL << APSR_C_Pos)

APSR: C Mask

◆ APSR_C_Msk [8/12]

#define APSR_C_Msk (1UL << APSR_C_Pos)

APSR: C Mask

◆ APSR_C_Msk [9/12]

#define APSR_C_Msk (1UL << APSR_C_Pos)

APSR: C Mask

◆ APSR_C_Msk [10/12]

#define APSR_C_Msk (1UL << APSR_C_Pos)

APSR: C Mask

◆ APSR_C_Msk [11/12]

#define APSR_C_Msk (1UL << APSR_C_Pos)

APSR: C Mask

◆ APSR_C_Msk [12/12]

#define APSR_C_Msk (1UL << APSR_C_Pos)

APSR: C Mask

◆ APSR_C_Pos [1/12]

#define APSR_C_Pos 29U

APSR: C Position

◆ APSR_C_Pos [2/12]

#define APSR_C_Pos 29U

APSR: C Position

◆ APSR_C_Pos [3/12]

#define APSR_C_Pos 29U

APSR: C Position

◆ APSR_C_Pos [4/12]

#define APSR_C_Pos 29U

APSR: C Position

◆ APSR_C_Pos [5/12]

#define APSR_C_Pos 29U

APSR: C Position

◆ APSR_C_Pos [6/12]

#define APSR_C_Pos 29U

APSR: C Position

◆ APSR_C_Pos [7/12]

#define APSR_C_Pos 29U

APSR: C Position

◆ APSR_C_Pos [8/12]

#define APSR_C_Pos 29U

APSR: C Position

◆ APSR_C_Pos [9/12]

#define APSR_C_Pos 29U

APSR: C Position

◆ APSR_C_Pos [10/12]

#define APSR_C_Pos 29U

APSR: C Position

◆ APSR_C_Pos [11/12]

#define APSR_C_Pos 29U

APSR: C Position

◆ APSR_C_Pos [12/12]

#define APSR_C_Pos 29U

APSR: C Position

◆ APSR_GE_Msk [1/4]

#define APSR_GE_Msk (0xFUL << APSR_GE_Pos)

APSR: GE Mask

◆ APSR_GE_Msk [2/4]

#define APSR_GE_Msk (0xFUL << APSR_GE_Pos)

APSR: GE Mask

◆ APSR_GE_Msk [3/4]

#define APSR_GE_Msk (0xFUL << APSR_GE_Pos)

APSR: GE Mask

◆ APSR_GE_Msk [4/4]

#define APSR_GE_Msk (0xFUL << APSR_GE_Pos)

APSR: GE Mask

◆ APSR_GE_Pos [1/4]

#define APSR_GE_Pos 16U

APSR: GE Position

◆ APSR_GE_Pos [2/4]

#define APSR_GE_Pos 16U

APSR: GE Position

◆ APSR_GE_Pos [3/4]

#define APSR_GE_Pos 16U

APSR: GE Position

◆ APSR_GE_Pos [4/4]

#define APSR_GE_Pos 16U

APSR: GE Position

◆ APSR_N_Msk [1/12]

#define APSR_N_Msk (1UL << APSR_N_Pos)

APSR: N Mask

◆ APSR_N_Msk [2/12]

#define APSR_N_Msk (1UL << APSR_N_Pos)

APSR: N Mask

◆ APSR_N_Msk [3/12]

#define APSR_N_Msk (1UL << APSR_N_Pos)

APSR: N Mask

◆ APSR_N_Msk [4/12]

#define APSR_N_Msk (1UL << APSR_N_Pos)

APSR: N Mask

◆ APSR_N_Msk [5/12]

#define APSR_N_Msk (1UL << APSR_N_Pos)

APSR: N Mask

◆ APSR_N_Msk [6/12]

#define APSR_N_Msk (1UL << APSR_N_Pos)

APSR: N Mask

◆ APSR_N_Msk [7/12]

#define APSR_N_Msk (1UL << APSR_N_Pos)

APSR: N Mask

◆ APSR_N_Msk [8/12]

#define APSR_N_Msk (1UL << APSR_N_Pos)

APSR: N Mask

◆ APSR_N_Msk [9/12]

#define APSR_N_Msk (1UL << APSR_N_Pos)

APSR: N Mask

◆ APSR_N_Msk [10/12]

#define APSR_N_Msk (1UL << APSR_N_Pos)

APSR: N Mask

◆ APSR_N_Msk [11/12]

#define APSR_N_Msk (1UL << APSR_N_Pos)

APSR: N Mask

◆ APSR_N_Msk [12/12]

#define APSR_N_Msk (1UL << APSR_N_Pos)

APSR: N Mask

◆ APSR_N_Pos [1/12]

#define APSR_N_Pos 31U

APSR: N Position

◆ APSR_N_Pos [2/12]

#define APSR_N_Pos 31U

APSR: N Position

◆ APSR_N_Pos [3/12]

#define APSR_N_Pos 31U

APSR: N Position

◆ APSR_N_Pos [4/12]

#define APSR_N_Pos 31U

APSR: N Position

◆ APSR_N_Pos [5/12]

#define APSR_N_Pos 31U

APSR: N Position

◆ APSR_N_Pos [6/12]

#define APSR_N_Pos 31U

APSR: N Position

◆ APSR_N_Pos [7/12]

#define APSR_N_Pos 31U

APSR: N Position

◆ APSR_N_Pos [8/12]

#define APSR_N_Pos 31U

APSR: N Position

◆ APSR_N_Pos [9/12]

#define APSR_N_Pos 31U

APSR: N Position

◆ APSR_N_Pos [10/12]

#define APSR_N_Pos 31U

APSR: N Position

◆ APSR_N_Pos [11/12]

#define APSR_N_Pos 31U

APSR: N Position

◆ APSR_N_Pos [12/12]

#define APSR_N_Pos 31U

APSR: N Position

◆ APSR_Q_Msk [1/6]

#define APSR_Q_Msk (1UL << APSR_Q_Pos)

APSR: Q Mask

◆ APSR_Q_Msk [2/6]

#define APSR_Q_Msk (1UL << APSR_Q_Pos)

APSR: Q Mask

◆ APSR_Q_Msk [3/6]

#define APSR_Q_Msk (1UL << APSR_Q_Pos)

APSR: Q Mask

◆ APSR_Q_Msk [4/6]

#define APSR_Q_Msk (1UL << APSR_Q_Pos)

APSR: Q Mask

◆ APSR_Q_Msk [5/6]

#define APSR_Q_Msk (1UL << APSR_Q_Pos)

APSR: Q Mask

◆ APSR_Q_Msk [6/6]

#define APSR_Q_Msk (1UL << APSR_Q_Pos)

APSR: Q Mask

◆ APSR_Q_Pos [1/6]

#define APSR_Q_Pos 27U

APSR: Q Position

◆ APSR_Q_Pos [2/6]

#define APSR_Q_Pos 27U

APSR: Q Position

◆ APSR_Q_Pos [3/6]

#define APSR_Q_Pos 27U

APSR: Q Position

◆ APSR_Q_Pos [4/6]

#define APSR_Q_Pos 27U

APSR: Q Position

◆ APSR_Q_Pos [5/6]

#define APSR_Q_Pos 27U

APSR: Q Position

◆ APSR_Q_Pos [6/6]

#define APSR_Q_Pos 27U

APSR: Q Position

◆ APSR_V_Msk [1/12]

#define APSR_V_Msk (1UL << APSR_V_Pos)

APSR: V Mask

◆ APSR_V_Msk [2/12]

#define APSR_V_Msk (1UL << APSR_V_Pos)

APSR: V Mask

◆ APSR_V_Msk [3/12]

#define APSR_V_Msk (1UL << APSR_V_Pos)

APSR: V Mask

◆ APSR_V_Msk [4/12]

#define APSR_V_Msk (1UL << APSR_V_Pos)

APSR: V Mask

◆ APSR_V_Msk [5/12]

#define APSR_V_Msk (1UL << APSR_V_Pos)

APSR: V Mask

◆ APSR_V_Msk [6/12]

#define APSR_V_Msk (1UL << APSR_V_Pos)

APSR: V Mask

◆ APSR_V_Msk [7/12]

#define APSR_V_Msk (1UL << APSR_V_Pos)

APSR: V Mask

◆ APSR_V_Msk [8/12]

#define APSR_V_Msk (1UL << APSR_V_Pos)

APSR: V Mask

◆ APSR_V_Msk [9/12]

#define APSR_V_Msk (1UL << APSR_V_Pos)

APSR: V Mask

◆ APSR_V_Msk [10/12]

#define APSR_V_Msk (1UL << APSR_V_Pos)

APSR: V Mask

◆ APSR_V_Msk [11/12]

#define APSR_V_Msk (1UL << APSR_V_Pos)

APSR: V Mask

◆ APSR_V_Msk [12/12]

#define APSR_V_Msk (1UL << APSR_V_Pos)

APSR: V Mask

◆ APSR_V_Pos [1/12]

#define APSR_V_Pos 28U

APSR: V Position

◆ APSR_V_Pos [2/12]

#define APSR_V_Pos 28U

APSR: V Position

◆ APSR_V_Pos [3/12]

#define APSR_V_Pos 28U

APSR: V Position

◆ APSR_V_Pos [4/12]

#define APSR_V_Pos 28U

APSR: V Position

◆ APSR_V_Pos [5/12]

#define APSR_V_Pos 28U

APSR: V Position

◆ APSR_V_Pos [6/12]

#define APSR_V_Pos 28U

APSR: V Position

◆ APSR_V_Pos [7/12]

#define APSR_V_Pos 28U

APSR: V Position

◆ APSR_V_Pos [8/12]

#define APSR_V_Pos 28U

APSR: V Position

◆ APSR_V_Pos [9/12]

#define APSR_V_Pos 28U

APSR: V Position

◆ APSR_V_Pos [10/12]

#define APSR_V_Pos 28U

APSR: V Position

◆ APSR_V_Pos [11/12]

#define APSR_V_Pos 28U

APSR: V Position