Nested Vectored Interrupt Controller (NVIC)

Type definitions for the NVIC Registers. More...

Modules
	System Control Block (SCB)
	Type definitions for the System Control Block Registers.

Classes
struct	NVIC_Type
	Structure type to access the Nested Vectored Interrupt Controller (NVIC). More...
#define	NVIC_STIR_INTID_Pos   0U
#define	NVIC_STIR_INTID_Msk   (0x1FFUL /*<< NVIC_STIR_INTID_Pos*/)
#define	NVIC_STIR_INTID_Pos   0U
#define	NVIC_STIR_INTID_Msk   (0x1FFUL /*<< NVIC_STIR_INTID_Pos*/)
#define	NVIC_STIR_INTID_Pos   0U
#define	NVIC_STIR_INTID_Msk   (0x1FFUL /*<< NVIC_STIR_INTID_Pos*/)
#define	NVIC_STIR_INTID_Pos   0U
#define	NVIC_STIR_INTID_Msk   (0x1FFUL /*<< NVIC_STIR_INTID_Pos*/)
#define	NVIC_STIR_INTID_Pos   0U
#define	NVIC_STIR_INTID_Msk   (0x1FFUL /*<< NVIC_STIR_INTID_Pos*/)
#define	NVIC_STIR_INTID_Pos   0U
#define	NVIC_STIR_INTID_Msk   (0x1FFUL /*<< NVIC_STIR_INTID_Pos*/)

Detailed Description

Type definitions for the NVIC Registers.

Macro Definition Documentation

NVIC_STIR_INTID_Msk [1/6]

#define NVIC_STIR_INTID_Msk   (0x1FFUL /*<< NVIC_STIR_INTID_Pos*/)

STIR: INTLINESNUM Mask

NVIC_STIR_INTID_Msk [2/6]

#define NVIC_STIR_INTID_Msk   (0x1FFUL /*<< NVIC_STIR_INTID_Pos*/)

STIR: INTLINESNUM Mask

NVIC_STIR_INTID_Msk [3/6]

#define NVIC_STIR_INTID_Msk   (0x1FFUL /*<< NVIC_STIR_INTID_Pos*/)

STIR: INTLINESNUM Mask

NVIC_STIR_INTID_Msk [4/6]

#define NVIC_STIR_INTID_Msk   (0x1FFUL /*<< NVIC_STIR_INTID_Pos*/)

STIR: INTLINESNUM Mask

NVIC_STIR_INTID_Msk [5/6]

#define NVIC_STIR_INTID_Msk   (0x1FFUL /*<< NVIC_STIR_INTID_Pos*/)

STIR: INTLINESNUM Mask

NVIC_STIR_INTID_Msk [6/6]

#define NVIC_STIR_INTID_Msk   (0x1FFUL /*<< NVIC_STIR_INTID_Pos*/)

STIR: INTLINESNUM Mask

NVIC_STIR_INTID_Pos [1/6]

#define NVIC_STIR_INTID_Pos   0U

STIR: INTLINESNUM Position

NVIC_STIR_INTID_Pos [2/6]

#define NVIC_STIR_INTID_Pos   0U

STIR: INTLINESNUM Position

NVIC_STIR_INTID_Pos [3/6]

#define NVIC_STIR_INTID_Pos   0U

STIR: INTLINESNUM Position

NVIC_STIR_INTID_Pos [4/6]

#define NVIC_STIR_INTID_Pos   0U

STIR: INTLINESNUM Position

NVIC_STIR_INTID_Pos [5/6]

#define NVIC_STIR_INTID_Pos   0U

STIR: INTLINESNUM Position

NVIC_STIR_INTID_Pos [6/6]

#define NVIC_STIR_INTID_Pos   0U

STIR: INTLINESNUM Position