My Project
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Macros | |
#define | VLAN_TAG ETH_VLAN_TAG |
#define | MIN_ETH_PAYLOAD ETH_MIN_ETH_PAYLOAD |
#define | MAX_ETH_PAYLOAD ETH_MAX_ETH_PAYLOAD |
#define | JUMBO_FRAME_PAYLOAD ETH_JUMBO_FRAME_PAYLOAD |
#define | MACMIIAR_CR_MASK ETH_MACMIIAR_CR_MASK |
#define | MACCR_CLEAR_MASK ETH_MACCR_CLEAR_MASK |
#define | MACFCR_CLEAR_MASK ETH_MACFCR_CLEAR_MASK |
#define | DMAOMR_CLEAR_MASK ETH_DMAOMR_CLEAR_MASK |
#define | ETH_MMCCR 0x00000100U |
#define | ETH_MMCRIR 0x00000104U |
#define | ETH_MMCTIR 0x00000108U |
#define | ETH_MMCRIMR 0x0000010CU |
#define | ETH_MMCTIMR 0x00000110U |
#define | ETH_MMCTGFSCCR 0x0000014CU |
#define | ETH_MMCTGFMSCCR 0x00000150U |
#define | ETH_MMCTGFCR 0x00000168U |
#define | ETH_MMCRFCECR 0x00000194U |
#define | ETH_MMCRFAECR 0x00000198U |
#define | ETH_MMCRGUFCR 0x000001C4U |
#define | ETH_MAC_TXFIFO_FULL 0x02000000U /* Tx FIFO full */ |
#define | ETH_MAC_TXFIFONOT_EMPTY 0x01000000U /* Tx FIFO not empty */ |
#define | ETH_MAC_TXFIFO_WRITE_ACTIVE 0x00400000U /* Tx FIFO write active */ |
#define | ETH_MAC_TXFIFO_IDLE 0x00000000U /* Tx FIFO read status: Idle */ |
#define | ETH_MAC_TXFIFO_READ |
#define | ETH_MAC_TXFIFO_WAITING |
#define | ETH_MAC_TXFIFO_WRITING |
#define | ETH_MAC_TRANSMISSION_PAUSE 0x00080000U /* MAC transmitter in pause */ |
#define | ETH_MAC_TRANSMITFRAMECONTROLLER_IDLE 0x00000000U /* MAC transmit frame controller: Idle */ |
#define | ETH_MAC_TRANSMITFRAMECONTROLLER_WAITING |
#define | ETH_MAC_TRANSMITFRAMECONTROLLER_GENRATING_PCF |
#define | ETH_MAC_TRANSMITFRAMECONTROLLER_TRANSFERRING |
#define | ETH_MAC_MII_TRANSMIT_ACTIVE 0x00010000U /* MAC MII transmit engine active */ |
#define | ETH_MAC_RXFIFO_EMPTY 0x00000000U /* Rx FIFO fill level: empty */ |
#define | ETH_MAC_RXFIFO_BELOW_THRESHOLD |
#define | ETH_MAC_RXFIFO_ABOVE_THRESHOLD |
#define | ETH_MAC_RXFIFO_FULL 0x00000300U /* Rx FIFO fill level: full */ |
#define | ETH_MAC_READCONTROLLER_IDLE 0x00000000U /* Rx FIFO read controller IDLE state */ |
#define | ETH_MAC_READCONTROLLER_READING_DATA 0x00000020U /* Rx FIFO read controller Reading frame data */ |
#define | ETH_MAC_READCONTROLLER_READING_STATUS |
#define | ETH_MAC_READCONTROLLER_FLUSHING |
#define | ETH_MAC_RXFIFO_WRITE_ACTIVE 0x00000010U /* Rx FIFO write controller active */ |
#define | ETH_MAC_SMALL_FIFO_NOTACTIVE 0x00000000U /* MAC small FIFO read / write controllers not active */ |
#define | ETH_MAC_SMALL_FIFO_READ_ACTIVE 0x00000002U /* MAC small FIFO read controller active */ |
#define | ETH_MAC_SMALL_FIFO_WRITE_ACTIVE 0x00000004U /* MAC small FIFO write controller active */ |
#define | ETH_MAC_SMALL_FIFO_RW_ACTIVE 0x00000006U /* MAC small FIFO read / write controllers active */ |
#define | ETH_MAC_MII_RECEIVE_PROTOCOL_ACTIVE 0x00000001U /* MAC MII receive protocol engine active */ |
#define DMAOMR_CLEAR_MASK ETH_DMAOMR_CLEAR_MASK |
#define ETH_MAC_MII_RECEIVE_PROTOCOL_ACTIVE 0x00000001U /* MAC MII receive protocol engine active */ |
#define ETH_MAC_MII_TRANSMIT_ACTIVE 0x00010000U /* MAC MII transmit engine active */ |
#define ETH_MAC_READCONTROLLER_FLUSHING |
#define ETH_MAC_READCONTROLLER_IDLE 0x00000000U /* Rx FIFO read controller IDLE state */ |
#define ETH_MAC_READCONTROLLER_READING_DATA 0x00000020U /* Rx FIFO read controller Reading frame data */ |
#define ETH_MAC_READCONTROLLER_READING_STATUS |
#define ETH_MAC_RXFIFO_ABOVE_THRESHOLD |
#define ETH_MAC_RXFIFO_BELOW_THRESHOLD |
#define ETH_MAC_RXFIFO_EMPTY 0x00000000U /* Rx FIFO fill level: empty */ |
#define ETH_MAC_RXFIFO_FULL 0x00000300U /* Rx FIFO fill level: full */ |
#define ETH_MAC_RXFIFO_WRITE_ACTIVE 0x00000010U /* Rx FIFO write controller active */ |
#define ETH_MAC_SMALL_FIFO_NOTACTIVE 0x00000000U /* MAC small FIFO read / write controllers not active */ |
#define ETH_MAC_SMALL_FIFO_READ_ACTIVE 0x00000002U /* MAC small FIFO read controller active */ |
#define ETH_MAC_SMALL_FIFO_RW_ACTIVE 0x00000006U /* MAC small FIFO read / write controllers active */ |
#define ETH_MAC_SMALL_FIFO_WRITE_ACTIVE 0x00000004U /* MAC small FIFO write controller active */ |
#define ETH_MAC_TRANSMISSION_PAUSE 0x00080000U /* MAC transmitter in pause */ |
#define ETH_MAC_TRANSMITFRAMECONTROLLER_GENRATING_PCF |
#define ETH_MAC_TRANSMITFRAMECONTROLLER_IDLE 0x00000000U /* MAC transmit frame controller: Idle */ |
#define ETH_MAC_TRANSMITFRAMECONTROLLER_TRANSFERRING |
#define ETH_MAC_TRANSMITFRAMECONTROLLER_WAITING |
#define ETH_MAC_TXFIFO_FULL 0x02000000U /* Tx FIFO full */ |
#define ETH_MAC_TXFIFO_IDLE 0x00000000U /* Tx FIFO read status: Idle */ |
#define ETH_MAC_TXFIFO_READ |
#define ETH_MAC_TXFIFO_WAITING |
#define ETH_MAC_TXFIFO_WRITE_ACTIVE 0x00400000U /* Tx FIFO write active */ |
#define ETH_MAC_TXFIFO_WRITING |
#define ETH_MAC_TXFIFONOT_EMPTY 0x01000000U /* Tx FIFO not empty */ |
#define ETH_MMCCR 0x00000100U |
#define ETH_MMCRFAECR 0x00000198U |
#define ETH_MMCRFCECR 0x00000194U |
#define ETH_MMCRGUFCR 0x000001C4U |
#define ETH_MMCRIMR 0x0000010CU |
#define ETH_MMCRIR 0x00000104U |
#define ETH_MMCTGFCR 0x00000168U |
#define ETH_MMCTGFMSCCR 0x00000150U |
#define ETH_MMCTGFSCCR 0x0000014CU |
#define ETH_MMCTIMR 0x00000110U |
#define ETH_MMCTIR 0x00000108U |
#define JUMBO_FRAME_PAYLOAD ETH_JUMBO_FRAME_PAYLOAD |
#define MACCR_CLEAR_MASK ETH_MACCR_CLEAR_MASK |
#define MACFCR_CLEAR_MASK ETH_MACFCR_CLEAR_MASK |
#define MACMIIAR_CR_MASK ETH_MACMIIAR_CR_MASK |
#define MAX_ETH_PAYLOAD ETH_MAX_ETH_PAYLOAD |
#define MIN_ETH_PAYLOAD ETH_MIN_ETH_PAYLOAD |
#define VLAN_TAG ETH_VLAN_TAG |