My Project
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Macros | |
#define | FLASH_BASE 0x08000000UL |
#define | CCMDATARAM_BASE 0x10000000UL |
#define | SRAM_BASE 0x20000000UL |
#define | PERIPH_BASE 0x40000000UL |
#define | FMC_BASE 0x60000000UL |
#define | FMC_R_BASE 0xA0000000UL |
#define | SRAM_BB_BASE 0x22000000UL |
#define | PERIPH_BB_BASE 0x42000000UL |
#define | APB1PERIPH_BASE PERIPH_BASE |
#define | APB2PERIPH_BASE (PERIPH_BASE + 0x00010000UL) |
#define | AHB1PERIPH_BASE (PERIPH_BASE + 0x00020000UL) |
#define | AHB2PERIPH_BASE (PERIPH_BASE + 0x08000000UL) |
#define | AHB3PERIPH_BASE (PERIPH_BASE + 0x10000000UL) |
#define | TIM2_BASE (APB1PERIPH_BASE + 0x00000000UL) |
#define | TIM3_BASE (APB1PERIPH_BASE + 0x00000400UL) |
#define | TIM4_BASE (APB1PERIPH_BASE + 0x00000800UL) |
#define | TIM6_BASE (APB1PERIPH_BASE + 0x00001000UL) |
#define | TIM7_BASE (APB1PERIPH_BASE + 0x00001400UL) |
#define | RTC_BASE (APB1PERIPH_BASE + 0x00002800UL) |
#define | WWDG_BASE (APB1PERIPH_BASE + 0x00002C00UL) |
#define | IWDG_BASE (APB1PERIPH_BASE + 0x00003000UL) |
#define | I2S2ext_BASE (APB1PERIPH_BASE + 0x00003400UL) |
#define | SPI2_BASE (APB1PERIPH_BASE + 0x00003800UL) |
#define | SPI3_BASE (APB1PERIPH_BASE + 0x00003C00UL) |
#define | I2S3ext_BASE (APB1PERIPH_BASE + 0x00004000UL) |
#define | USART2_BASE (APB1PERIPH_BASE + 0x00004400UL) |
#define | USART3_BASE (APB1PERIPH_BASE + 0x00004800UL) |
#define | UART4_BASE (APB1PERIPH_BASE + 0x00004C00UL) |
#define | UART5_BASE (APB1PERIPH_BASE + 0x00005000UL) |
#define | I2C1_BASE (APB1PERIPH_BASE + 0x00005400UL) |
#define | I2C2_BASE (APB1PERIPH_BASE + 0x00005800UL) |
#define | USB_BASE (APB1PERIPH_BASE + 0x00005C00UL) |
#define | USB_PMAADDR (APB1PERIPH_BASE + 0x00006000UL) |
#define | CAN_BASE (APB1PERIPH_BASE + 0x00006400UL) |
#define | PWR_BASE (APB1PERIPH_BASE + 0x00007000UL) |
#define | DAC1_BASE (APB1PERIPH_BASE + 0x00007400UL) |
#define | DAC_BASE DAC1_BASE |
#define | I2C3_BASE (APB1PERIPH_BASE + 0x00007800UL) |
#define | SYSCFG_BASE (APB2PERIPH_BASE + 0x00000000UL) |
#define | COMP1_BASE (APB2PERIPH_BASE + 0x0000001CUL) |
#define | COMP2_BASE (APB2PERIPH_BASE + 0x00000020UL) |
#define | COMP3_BASE (APB2PERIPH_BASE + 0x00000024UL) |
#define | COMP4_BASE (APB2PERIPH_BASE + 0x00000028UL) |
#define | COMP5_BASE (APB2PERIPH_BASE + 0x0000002CUL) |
#define | COMP6_BASE (APB2PERIPH_BASE + 0x00000030UL) |
#define | COMP7_BASE (APB2PERIPH_BASE + 0x00000034UL) |
#define | COMP_BASE COMP1_BASE |
#define | OPAMP1_BASE (APB2PERIPH_BASE + 0x00000038UL) |
#define | OPAMP2_BASE (APB2PERIPH_BASE + 0x0000003CUL) |
#define | OPAMP3_BASE (APB2PERIPH_BASE + 0x00000040UL) |
#define | OPAMP4_BASE (APB2PERIPH_BASE + 0x00000044UL) |
#define | OPAMP_BASE OPAMP1_BASE |
#define | EXTI_BASE (APB2PERIPH_BASE + 0x00000400UL) |
#define | TIM1_BASE (APB2PERIPH_BASE + 0x00002C00UL) |
#define | SPI1_BASE (APB2PERIPH_BASE + 0x00003000UL) |
#define | TIM8_BASE (APB2PERIPH_BASE + 0x00003400UL) |
#define | USART1_BASE (APB2PERIPH_BASE + 0x00003800UL) |
#define | SPI4_BASE (APB2PERIPH_BASE + 0x00003C00UL) |
#define | TIM15_BASE (APB2PERIPH_BASE + 0x00004000UL) |
#define | TIM16_BASE (APB2PERIPH_BASE + 0x00004400UL) |
#define | TIM17_BASE (APB2PERIPH_BASE + 0x00004800UL) |
#define | TIM20_BASE (APB2PERIPH_BASE + 0x00005000UL) |
#define | DMA1_BASE (AHB1PERIPH_BASE + 0x00000000UL) |
#define | DMA1_Channel1_BASE (AHB1PERIPH_BASE + 0x00000008UL) |
#define | DMA1_Channel2_BASE (AHB1PERIPH_BASE + 0x0000001CUL) |
#define | DMA1_Channel3_BASE (AHB1PERIPH_BASE + 0x00000030UL) |
#define | DMA1_Channel4_BASE (AHB1PERIPH_BASE + 0x00000044UL) |
#define | DMA1_Channel5_BASE (AHB1PERIPH_BASE + 0x00000058UL) |
#define | DMA1_Channel6_BASE (AHB1PERIPH_BASE + 0x0000006CUL) |
#define | DMA1_Channel7_BASE (AHB1PERIPH_BASE + 0x00000080UL) |
#define | DMA2_BASE (AHB1PERIPH_BASE + 0x00000400UL) |
#define | DMA2_Channel1_BASE (AHB1PERIPH_BASE + 0x00000408UL) |
#define | DMA2_Channel2_BASE (AHB1PERIPH_BASE + 0x0000041CUL) |
#define | DMA2_Channel3_BASE (AHB1PERIPH_BASE + 0x00000430UL) |
#define | DMA2_Channel4_BASE (AHB1PERIPH_BASE + 0x00000444UL) |
#define | DMA2_Channel5_BASE (AHB1PERIPH_BASE + 0x00000458UL) |
#define | RCC_BASE (AHB1PERIPH_BASE + 0x00001000UL) |
#define | FLASH_R_BASE (AHB1PERIPH_BASE + 0x00002000UL) |
#define | OB_BASE 0x1FFFF800UL |
#define | FLASHSIZE_BASE 0x1FFFF7CCUL |
#define | UID_BASE 0x1FFFF7ACUL |
#define | CRC_BASE (AHB1PERIPH_BASE + 0x00003000UL) |
#define | TSC_BASE (AHB1PERIPH_BASE + 0x00004000UL) |
#define | GPIOA_BASE (AHB2PERIPH_BASE + 0x00000000UL) |
#define | GPIOB_BASE (AHB2PERIPH_BASE + 0x00000400UL) |
#define | GPIOC_BASE (AHB2PERIPH_BASE + 0x00000800UL) |
#define | GPIOD_BASE (AHB2PERIPH_BASE + 0x00000C00UL) |
#define | GPIOE_BASE (AHB2PERIPH_BASE + 0x00001000UL) |
#define | GPIOF_BASE (AHB2PERIPH_BASE + 0x00001400UL) |
#define | GPIOG_BASE (AHB2PERIPH_BASE + 0x00001800UL) |
#define | GPIOH_BASE (AHB2PERIPH_BASE + 0x00001C00UL) |
#define | ADC1_BASE (AHB3PERIPH_BASE + 0x00000000UL) |
#define | ADC2_BASE (AHB3PERIPH_BASE + 0x00000100UL) |
#define | ADC1_2_COMMON_BASE (AHB3PERIPH_BASE + 0x00000300UL) |
#define | ADC3_BASE (AHB3PERIPH_BASE + 0x00000400UL) |
#define | ADC4_BASE (AHB3PERIPH_BASE + 0x00000500UL) |
#define | ADC3_4_COMMON_BASE (AHB3PERIPH_BASE + 0x00000700UL) |
#define | FMC_BANK1 (FMC_BASE) |
#define | FMC_BANK1_1 (FMC_BANK1) |
#define | FMC_BANK1_2 (FMC_BANK1 + 0x04000000UL) |
#define | FMC_BANK1_3 (FMC_BANK1 + 0x08000000UL) |
#define | FMC_BANK1_4 (FMC_BANK1 + 0x0C000000UL) |
#define | FMC_BANK2 (FMC_BASE + 0x10000000UL) |
#define | FMC_BANK3 (FMC_BASE + 0x20000000UL) |
#define | FMC_BANK4 (FMC_BASE + 0x30000000UL) |
#define | FMC_Bank1_R_BASE (FMC_R_BASE + 0x0000UL) |
#define | FMC_Bank1E_R_BASE (FMC_R_BASE + 0x0104UL) |
#define | FMC_Bank2_3_R_BASE (FMC_R_BASE + 0x0060UL) |
#define | FMC_Bank4_R_BASE (FMC_R_BASE + 0x00A0UL) |
#define | DBGMCU_BASE 0xE0042000UL |
#define ADC1_2_COMMON_BASE (AHB3PERIPH_BASE + 0x00000300UL) |
#define ADC1_BASE (AHB3PERIPH_BASE + 0x00000000UL) |
#define ADC2_BASE (AHB3PERIPH_BASE + 0x00000100UL) |
#define ADC3_4_COMMON_BASE (AHB3PERIPH_BASE + 0x00000700UL) |
FMC Bankx base address
#define ADC3_BASE (AHB3PERIPH_BASE + 0x00000400UL) |
#define ADC4_BASE (AHB3PERIPH_BASE + 0x00000500UL) |
#define AHB1PERIPH_BASE (PERIPH_BASE + 0x00020000UL) |
#define AHB2PERIPH_BASE (PERIPH_BASE + 0x08000000UL) |
#define AHB3PERIPH_BASE (PERIPH_BASE + 0x10000000UL) |
APB1 peripherals
#define APB1PERIPH_BASE PERIPH_BASE |
#define APB2PERIPH_BASE (PERIPH_BASE + 0x00010000UL) |
#define CAN_BASE (APB1PERIPH_BASE + 0x00006400UL) |
#define CCMDATARAM_BASE 0x10000000UL |
CCM(core coupled memory) data RAM base address in the alias region
#define COMP1_BASE (APB2PERIPH_BASE + 0x0000001CUL) |
#define COMP2_BASE (APB2PERIPH_BASE + 0x00000020UL) |
#define COMP3_BASE (APB2PERIPH_BASE + 0x00000024UL) |
#define COMP4_BASE (APB2PERIPH_BASE + 0x00000028UL) |
#define COMP5_BASE (APB2PERIPH_BASE + 0x0000002CUL) |
#define COMP6_BASE (APB2PERIPH_BASE + 0x00000030UL) |
#define COMP7_BASE (APB2PERIPH_BASE + 0x00000034UL) |
#define COMP_BASE COMP1_BASE |
#define CRC_BASE (AHB1PERIPH_BASE + 0x00003000UL) |
#define DAC1_BASE (APB1PERIPH_BASE + 0x00007400UL) |
#define DAC_BASE DAC1_BASE |
#define DBGMCU_BASE 0xE0042000UL |
Debug MCU registers base address
#define DMA1_BASE (AHB1PERIPH_BASE + 0x00000000UL) |
#define DMA1_Channel1_BASE (AHB1PERIPH_BASE + 0x00000008UL) |
#define DMA1_Channel2_BASE (AHB1PERIPH_BASE + 0x0000001CUL) |
#define DMA1_Channel3_BASE (AHB1PERIPH_BASE + 0x00000030UL) |
#define DMA1_Channel4_BASE (AHB1PERIPH_BASE + 0x00000044UL) |
#define DMA1_Channel5_BASE (AHB1PERIPH_BASE + 0x00000058UL) |
#define DMA1_Channel6_BASE (AHB1PERIPH_BASE + 0x0000006CUL) |
#define DMA1_Channel7_BASE (AHB1PERIPH_BASE + 0x00000080UL) |
#define DMA2_BASE (AHB1PERIPH_BASE + 0x00000400UL) |
#define DMA2_Channel1_BASE (AHB1PERIPH_BASE + 0x00000408UL) |
#define DMA2_Channel2_BASE (AHB1PERIPH_BASE + 0x0000041CUL) |
#define DMA2_Channel3_BASE (AHB1PERIPH_BASE + 0x00000430UL) |
#define DMA2_Channel4_BASE (AHB1PERIPH_BASE + 0x00000444UL) |
#define DMA2_Channel5_BASE (AHB1PERIPH_BASE + 0x00000458UL) |
#define EXTI_BASE (APB2PERIPH_BASE + 0x00000400UL) |
#define FLASH_BASE 0x08000000UL |
FLASH base address in the alias region
#define FLASH_R_BASE (AHB1PERIPH_BASE + 0x00002000UL) |
Flash registers base address
#define FLASHSIZE_BASE 0x1FFFF7CCUL |
FLASH Size register base address
#define FMC_BANK1 (FMC_BASE) |
FMC Bank1 base address
#define FMC_BANK1_1 (FMC_BANK1) |
FMC Bank1_1 base address
#define FMC_BANK1_2 (FMC_BANK1 + 0x04000000UL) |
FMC Bank1_2 base address
#define FMC_BANK1_3 (FMC_BANK1 + 0x08000000UL) |
FMC Bank1_3 base address
#define FMC_BANK1_4 (FMC_BANK1 + 0x0C000000UL) |
FMC Bank1_4 base address
#define FMC_Bank1_R_BASE (FMC_R_BASE + 0x0000UL) |
#define FMC_Bank1E_R_BASE (FMC_R_BASE + 0x0104UL) |
#define FMC_BANK2 (FMC_BASE + 0x10000000UL) |
FMC Bank2 base address
#define FMC_Bank2_3_R_BASE (FMC_R_BASE + 0x0060UL) |
#define FMC_BANK3 (FMC_BASE + 0x20000000UL) |
FMC Bank3 base address
#define FMC_BANK4 (FMC_BASE + 0x30000000UL) |
FMC Bank4 base address
FMC Bankx registers base address
#define FMC_Bank4_R_BASE (FMC_R_BASE + 0x00A0UL) |
#define FMC_BASE 0x60000000UL |
FMC base address
#define FMC_R_BASE 0xA0000000UL |
FMC registers base address
#define GPIOA_BASE (AHB2PERIPH_BASE + 0x00000000UL) |
#define GPIOB_BASE (AHB2PERIPH_BASE + 0x00000400UL) |
#define GPIOC_BASE (AHB2PERIPH_BASE + 0x00000800UL) |
#define GPIOD_BASE (AHB2PERIPH_BASE + 0x00000C00UL) |
#define GPIOE_BASE (AHB2PERIPH_BASE + 0x00001000UL) |
#define GPIOF_BASE (AHB2PERIPH_BASE + 0x00001400UL) |
#define GPIOG_BASE (AHB2PERIPH_BASE + 0x00001800UL) |
#define GPIOH_BASE (AHB2PERIPH_BASE + 0x00001C00UL) |
AHB3 peripherals
#define I2C1_BASE (APB1PERIPH_BASE + 0x00005400UL) |
#define I2C2_BASE (APB1PERIPH_BASE + 0x00005800UL) |
#define I2C3_BASE (APB1PERIPH_BASE + 0x00007800UL) |
APB2 peripherals
#define I2S2ext_BASE (APB1PERIPH_BASE + 0x00003400UL) |
#define I2S3ext_BASE (APB1PERIPH_BASE + 0x00004000UL) |
#define IWDG_BASE (APB1PERIPH_BASE + 0x00003000UL) |
#define OB_BASE 0x1FFFF800UL |
Flash Option Bytes base address
#define OPAMP1_BASE (APB2PERIPH_BASE + 0x00000038UL) |
#define OPAMP2_BASE (APB2PERIPH_BASE + 0x0000003CUL) |
#define OPAMP3_BASE (APB2PERIPH_BASE + 0x00000040UL) |
#define OPAMP4_BASE (APB2PERIPH_BASE + 0x00000044UL) |
#define OPAMP_BASE OPAMP1_BASE |
#define PERIPH_BASE 0x40000000UL |
Peripheral base address in the alias region
#define PERIPH_BB_BASE 0x42000000UL |
Peripheral base address in the bit-band region Peripheral memory map
#define PWR_BASE (APB1PERIPH_BASE + 0x00007000UL) |
#define RCC_BASE (AHB1PERIPH_BASE + 0x00001000UL) |
#define RTC_BASE (APB1PERIPH_BASE + 0x00002800UL) |
#define SPI1_BASE (APB2PERIPH_BASE + 0x00003000UL) |
#define SPI2_BASE (APB1PERIPH_BASE + 0x00003800UL) |
#define SPI3_BASE (APB1PERIPH_BASE + 0x00003C00UL) |
#define SPI4_BASE (APB2PERIPH_BASE + 0x00003C00UL) |
#define SRAM_BASE 0x20000000UL |
SRAM base address in the alias region
#define SRAM_BB_BASE 0x22000000UL |
SRAM base address in the bit-band region
#define SYSCFG_BASE (APB2PERIPH_BASE + 0x00000000UL) |
#define TIM15_BASE (APB2PERIPH_BASE + 0x00004000UL) |
#define TIM16_BASE (APB2PERIPH_BASE + 0x00004400UL) |
#define TIM17_BASE (APB2PERIPH_BASE + 0x00004800UL) |
#define TIM1_BASE (APB2PERIPH_BASE + 0x00002C00UL) |
#define TIM20_BASE (APB2PERIPH_BASE + 0x00005000UL) |
AHB1 peripherals
#define TIM2_BASE (APB1PERIPH_BASE + 0x00000000UL) |
#define TIM3_BASE (APB1PERIPH_BASE + 0x00000400UL) |
#define TIM4_BASE (APB1PERIPH_BASE + 0x00000800UL) |
#define TIM6_BASE (APB1PERIPH_BASE + 0x00001000UL) |
#define TIM7_BASE (APB1PERIPH_BASE + 0x00001400UL) |
#define TIM8_BASE (APB2PERIPH_BASE + 0x00003400UL) |
#define TSC_BASE (AHB1PERIPH_BASE + 0x00004000UL) |
AHB2 peripherals
#define UART4_BASE (APB1PERIPH_BASE + 0x00004C00UL) |
#define UART5_BASE (APB1PERIPH_BASE + 0x00005000UL) |
#define UID_BASE 0x1FFFF7ACUL |
Unique device ID register base address
#define USART1_BASE (APB2PERIPH_BASE + 0x00003800UL) |
#define USART2_BASE (APB1PERIPH_BASE + 0x00004400UL) |
#define USART3_BASE (APB1PERIPH_BASE + 0x00004800UL) |
#define USB_BASE (APB1PERIPH_BASE + 0x00005C00UL) |
USB_IP Peripheral Registers base address
#define USB_PMAADDR (APB1PERIPH_BASE + 0x00006000UL) |
USB_IP Packet Memory Area base address
#define WWDG_BASE (APB1PERIPH_BASE + 0x00002C00UL) |