Macros
#define	FLASH_BASE 0x08000000UL

#define	CCMDATARAM_BASE 0x10000000UL

#define	SRAM_BASE 0x20000000UL

#define	PERIPH_BASE 0x40000000UL

#define	FMC_BASE 0x60000000UL

#define	FMC_R_BASE 0xA0000000UL

#define	SRAM_BB_BASE 0x22000000UL

#define	PERIPH_BB_BASE 0x42000000UL

#define	APB1PERIPH_BASE PERIPH_BASE

#define	APB2PERIPH_BASE (PERIPH_BASE + 0x00010000UL)

#define	AHB1PERIPH_BASE (PERIPH_BASE + 0x00020000UL)

#define	AHB2PERIPH_BASE (PERIPH_BASE + 0x08000000UL)

#define	AHB3PERIPH_BASE (PERIPH_BASE + 0x10000000UL)

#define	TIM2_BASE (APB1PERIPH_BASE + 0x00000000UL)

#define	TIM3_BASE (APB1PERIPH_BASE + 0x00000400UL)

#define	TIM4_BASE (APB1PERIPH_BASE + 0x00000800UL)

#define	TIM6_BASE (APB1PERIPH_BASE + 0x00001000UL)

#define	TIM7_BASE (APB1PERIPH_BASE + 0x00001400UL)

#define	RTC_BASE (APB1PERIPH_BASE + 0x00002800UL)

#define	WWDG_BASE (APB1PERIPH_BASE + 0x00002C00UL)

#define	IWDG_BASE (APB1PERIPH_BASE + 0x00003000UL)

#define	I2S2ext_BASE (APB1PERIPH_BASE + 0x00003400UL)

#define	SPI2_BASE (APB1PERIPH_BASE + 0x00003800UL)

#define	SPI3_BASE (APB1PERIPH_BASE + 0x00003C00UL)

#define	I2S3ext_BASE (APB1PERIPH_BASE + 0x00004000UL)

#define	USART2_BASE (APB1PERIPH_BASE + 0x00004400UL)

#define	USART3_BASE (APB1PERIPH_BASE + 0x00004800UL)

#define	UART4_BASE (APB1PERIPH_BASE + 0x00004C00UL)

#define	UART5_BASE (APB1PERIPH_BASE + 0x00005000UL)

#define	I2C1_BASE (APB1PERIPH_BASE + 0x00005400UL)

#define	I2C2_BASE (APB1PERIPH_BASE + 0x00005800UL)

#define	USB_BASE (APB1PERIPH_BASE + 0x00005C00UL)

#define	USB_PMAADDR (APB1PERIPH_BASE + 0x00006000UL)

#define	CAN_BASE (APB1PERIPH_BASE + 0x00006400UL)

#define	PWR_BASE (APB1PERIPH_BASE + 0x00007000UL)

#define	DAC1_BASE (APB1PERIPH_BASE + 0x00007400UL)

#define	DAC_BASE DAC1_BASE

#define	I2C3_BASE (APB1PERIPH_BASE + 0x00007800UL)

#define	SYSCFG_BASE (APB2PERIPH_BASE + 0x00000000UL)

#define	COMP1_BASE (APB2PERIPH_BASE + 0x0000001CUL)

#define	COMP2_BASE (APB2PERIPH_BASE + 0x00000020UL)

#define	COMP3_BASE (APB2PERIPH_BASE + 0x00000024UL)

#define	COMP4_BASE (APB2PERIPH_BASE + 0x00000028UL)

#define	COMP5_BASE (APB2PERIPH_BASE + 0x0000002CUL)

#define	COMP6_BASE (APB2PERIPH_BASE + 0x00000030UL)

#define	COMP7_BASE (APB2PERIPH_BASE + 0x00000034UL)

#define	COMP_BASE COMP1_BASE

#define	OPAMP1_BASE (APB2PERIPH_BASE + 0x00000038UL)

#define	OPAMP2_BASE (APB2PERIPH_BASE + 0x0000003CUL)

#define	OPAMP3_BASE (APB2PERIPH_BASE + 0x00000040UL)

#define	OPAMP4_BASE (APB2PERIPH_BASE + 0x00000044UL)

#define	OPAMP_BASE OPAMP1_BASE

#define	EXTI_BASE (APB2PERIPH_BASE + 0x00000400UL)

#define	TIM1_BASE (APB2PERIPH_BASE + 0x00002C00UL)

#define	SPI1_BASE (APB2PERIPH_BASE + 0x00003000UL)

#define	TIM8_BASE (APB2PERIPH_BASE + 0x00003400UL)

#define	USART1_BASE (APB2PERIPH_BASE + 0x00003800UL)

#define	SPI4_BASE (APB2PERIPH_BASE + 0x00003C00UL)

#define	TIM15_BASE (APB2PERIPH_BASE + 0x00004000UL)

#define	TIM16_BASE (APB2PERIPH_BASE + 0x00004400UL)

#define	TIM17_BASE (APB2PERIPH_BASE + 0x00004800UL)

#define	TIM20_BASE (APB2PERIPH_BASE + 0x00005000UL)

#define	DMA1_BASE (AHB1PERIPH_BASE + 0x00000000UL)

#define	DMA1_Channel1_BASE (AHB1PERIPH_BASE + 0x00000008UL)

#define	DMA1_Channel2_BASE (AHB1PERIPH_BASE + 0x0000001CUL)

#define	DMA1_Channel3_BASE (AHB1PERIPH_BASE + 0x00000030UL)

#define	DMA1_Channel4_BASE (AHB1PERIPH_BASE + 0x00000044UL)

#define	DMA1_Channel5_BASE (AHB1PERIPH_BASE + 0x00000058UL)

#define	DMA1_Channel6_BASE (AHB1PERIPH_BASE + 0x0000006CUL)

#define	DMA1_Channel7_BASE (AHB1PERIPH_BASE + 0x00000080UL)

#define	DMA2_BASE (AHB1PERIPH_BASE + 0x00000400UL)

#define	DMA2_Channel1_BASE (AHB1PERIPH_BASE + 0x00000408UL)

#define	DMA2_Channel2_BASE (AHB1PERIPH_BASE + 0x0000041CUL)

#define	DMA2_Channel3_BASE (AHB1PERIPH_BASE + 0x00000430UL)

#define	DMA2_Channel4_BASE (AHB1PERIPH_BASE + 0x00000444UL)

#define	DMA2_Channel5_BASE (AHB1PERIPH_BASE + 0x00000458UL)

#define	RCC_BASE (AHB1PERIPH_BASE + 0x00001000UL)

#define	FLASH_R_BASE (AHB1PERIPH_BASE + 0x00002000UL)

#define	OB_BASE 0x1FFFF800UL

#define	FLASHSIZE_BASE 0x1FFFF7CCUL

#define	UID_BASE 0x1FFFF7ACUL

#define	CRC_BASE (AHB1PERIPH_BASE + 0x00003000UL)

#define	TSC_BASE (AHB1PERIPH_BASE + 0x00004000UL)

#define	GPIOA_BASE (AHB2PERIPH_BASE + 0x00000000UL)

#define	GPIOB_BASE (AHB2PERIPH_BASE + 0x00000400UL)

#define	GPIOC_BASE (AHB2PERIPH_BASE + 0x00000800UL)

#define	GPIOD_BASE (AHB2PERIPH_BASE + 0x00000C00UL)

#define	GPIOE_BASE (AHB2PERIPH_BASE + 0x00001000UL)

#define	GPIOF_BASE (AHB2PERIPH_BASE + 0x00001400UL)

#define	GPIOG_BASE (AHB2PERIPH_BASE + 0x00001800UL)

#define	GPIOH_BASE (AHB2PERIPH_BASE + 0x00001C00UL)

#define	ADC1_BASE (AHB3PERIPH_BASE + 0x00000000UL)

#define	ADC2_BASE (AHB3PERIPH_BASE + 0x00000100UL)

#define	ADC1_2_COMMON_BASE (AHB3PERIPH_BASE + 0x00000300UL)

#define	ADC3_BASE (AHB3PERIPH_BASE + 0x00000400UL)

#define	ADC4_BASE (AHB3PERIPH_BASE + 0x00000500UL)

#define	ADC3_4_COMMON_BASE (AHB3PERIPH_BASE + 0x00000700UL)

#define	FMC_BANK1 (FMC_BASE)

#define	FMC_BANK1_1 (FMC_BANK1)

#define	FMC_BANK1_2 (FMC_BANK1 + 0x04000000UL)

#define	FMC_BANK1_3 (FMC_BANK1 + 0x08000000UL)

#define	FMC_BANK1_4 (FMC_BANK1 + 0x0C000000UL)

#define	FMC_BANK2 (FMC_BASE + 0x10000000UL)

#define	FMC_BANK3 (FMC_BASE + 0x20000000UL)

#define	FMC_BANK4 (FMC_BASE + 0x30000000UL)

#define	FMC_Bank1_R_BASE (FMC_R_BASE + 0x0000UL)

#define	FMC_Bank1E_R_BASE (FMC_R_BASE + 0x0104UL)

#define	FMC_Bank2_3_R_BASE (FMC_R_BASE + 0x0060UL)

#define	FMC_Bank4_R_BASE (FMC_R_BASE + 0x00A0UL)

#define	DBGMCU_BASE 0xE0042000UL

Detailed Description

Macro Definition Documentation

◆ ADC1_2_COMMON_BASE

#define ADC1_2_COMMON_BASE (AHB3PERIPH_BASE + 0x00000300UL)

◆ ADC1_BASE

#define ADC1_BASE (AHB3PERIPH_BASE + 0x00000000UL)

◆ ADC2_BASE

#define ADC2_BASE (AHB3PERIPH_BASE + 0x00000100UL)

◆ ADC3_4_COMMON_BASE

#define ADC3_4_COMMON_BASE (AHB3PERIPH_BASE + 0x00000700UL)

FMC Bankx base address

◆ ADC3_BASE

#define ADC3_BASE (AHB3PERIPH_BASE + 0x00000400UL)

◆ ADC4_BASE

#define ADC4_BASE (AHB3PERIPH_BASE + 0x00000500UL)

◆ AHB1PERIPH_BASE

#define AHB1PERIPH_BASE (PERIPH_BASE + 0x00020000UL)

◆ AHB2PERIPH_BASE

#define AHB2PERIPH_BASE (PERIPH_BASE + 0x08000000UL)

◆ AHB3PERIPH_BASE

#define AHB3PERIPH_BASE (PERIPH_BASE + 0x10000000UL)

APB1 peripherals

◆ APB1PERIPH_BASE

#define APB1PERIPH_BASE PERIPH_BASE

◆ APB2PERIPH_BASE

#define APB2PERIPH_BASE (PERIPH_BASE + 0x00010000UL)

◆ CAN_BASE

#define CAN_BASE (APB1PERIPH_BASE + 0x00006400UL)

◆ CCMDATARAM_BASE

#define CCMDATARAM_BASE 0x10000000UL

CCM(core coupled memory) data RAM base address in the alias region

◆ COMP1_BASE

#define COMP1_BASE (APB2PERIPH_BASE + 0x0000001CUL)

◆ COMP2_BASE

#define COMP2_BASE (APB2PERIPH_BASE + 0x00000020UL)

◆ COMP3_BASE

#define COMP3_BASE (APB2PERIPH_BASE + 0x00000024UL)

◆ COMP4_BASE

#define COMP4_BASE (APB2PERIPH_BASE + 0x00000028UL)

◆ COMP5_BASE

#define COMP5_BASE (APB2PERIPH_BASE + 0x0000002CUL)

◆ COMP6_BASE

#define COMP6_BASE (APB2PERIPH_BASE + 0x00000030UL)

◆ COMP7_BASE

#define COMP7_BASE (APB2PERIPH_BASE + 0x00000034UL)

◆ COMP_BASE

#define COMP_BASE COMP1_BASE

◆ CRC_BASE

#define CRC_BASE (AHB1PERIPH_BASE + 0x00003000UL)

◆ DAC1_BASE

#define DAC1_BASE (APB1PERIPH_BASE + 0x00007400UL)

◆ DAC_BASE

#define DAC_BASE DAC1_BASE

◆ DBGMCU_BASE

#define DBGMCU_BASE 0xE0042000UL

Debug MCU registers base address

◆ DMA1_BASE

#define DMA1_BASE (AHB1PERIPH_BASE + 0x00000000UL)

◆ DMA1_Channel1_BASE

#define DMA1_Channel1_BASE (AHB1PERIPH_BASE + 0x00000008UL)

◆ DMA1_Channel2_BASE

#define DMA1_Channel2_BASE (AHB1PERIPH_BASE + 0x0000001CUL)

◆ DMA1_Channel3_BASE

#define DMA1_Channel3_BASE (AHB1PERIPH_BASE + 0x00000030UL)

◆ DMA1_Channel4_BASE

#define DMA1_Channel4_BASE (AHB1PERIPH_BASE + 0x00000044UL)

◆ DMA1_Channel5_BASE

#define DMA1_Channel5_BASE (AHB1PERIPH_BASE + 0x00000058UL)

◆ DMA1_Channel6_BASE

#define DMA1_Channel6_BASE (AHB1PERIPH_BASE + 0x0000006CUL)

◆ DMA1_Channel7_BASE

#define DMA1_Channel7_BASE (AHB1PERIPH_BASE + 0x00000080UL)

◆ DMA2_BASE

#define DMA2_BASE (AHB1PERIPH_BASE + 0x00000400UL)

◆ DMA2_Channel1_BASE

#define DMA2_Channel1_BASE (AHB1PERIPH_BASE + 0x00000408UL)

◆ DMA2_Channel2_BASE

#define DMA2_Channel2_BASE (AHB1PERIPH_BASE + 0x0000041CUL)

◆ DMA2_Channel3_BASE

#define DMA2_Channel3_BASE (AHB1PERIPH_BASE + 0x00000430UL)

◆ DMA2_Channel4_BASE

#define DMA2_Channel4_BASE (AHB1PERIPH_BASE + 0x00000444UL)

◆ DMA2_Channel5_BASE

#define DMA2_Channel5_BASE (AHB1PERIPH_BASE + 0x00000458UL)

◆ EXTI_BASE

#define EXTI_BASE (APB2PERIPH_BASE + 0x00000400UL)

◆ FLASH_BASE

#define FLASH_BASE 0x08000000UL

FLASH base address in the alias region

◆ FLASH_R_BASE

#define FLASH_R_BASE (AHB1PERIPH_BASE + 0x00002000UL)

Flash registers base address

◆ FLASHSIZE_BASE

#define FLASHSIZE_BASE 0x1FFFF7CCUL

FLASH Size register base address

◆ FMC_BANK1

#define FMC_BANK1 (FMC_BASE)

FMC Bank1 base address

◆ FMC_BANK1_1

#define FMC_BANK1_1 (FMC_BANK1)

FMC Bank1_1 base address

◆ FMC_BANK1_2

#define FMC_BANK1_2 (FMC_BANK1 + 0x04000000UL)

FMC Bank1_2 base address

◆ FMC_BANK1_3

#define FMC_BANK1_3 (FMC_BANK1 + 0x08000000UL)

FMC Bank1_3 base address

◆ FMC_BANK1_4

#define FMC_BANK1_4 (FMC_BANK1 + 0x0C000000UL)

FMC Bank1_4 base address

◆ FMC_Bank1_R_BASE

#define FMC_Bank1_R_BASE (FMC_R_BASE + 0x0000UL)

◆ FMC_Bank1E_R_BASE

#define FMC_Bank1E_R_BASE (FMC_R_BASE + 0x0104UL)

◆ FMC_BANK2

#define FMC_BANK2 (FMC_BASE + 0x10000000UL)

FMC Bank2 base address

◆ FMC_Bank2_3_R_BASE

#define FMC_Bank2_3_R_BASE (FMC_R_BASE + 0x0060UL)

◆ FMC_BANK3

#define FMC_BANK3 (FMC_BASE + 0x20000000UL)

FMC Bank3 base address

◆ FMC_BANK4

#define FMC_BANK4 (FMC_BASE + 0x30000000UL)

FMC Bank4 base address
FMC Bankx registers base address

◆ FMC_Bank4_R_BASE

#define FMC_Bank4_R_BASE (FMC_R_BASE + 0x00A0UL)

◆ FMC_BASE

#define FMC_BASE 0x60000000UL

FMC base address

◆ FMC_R_BASE

#define FMC_R_BASE 0xA0000000UL

FMC registers base address

◆ GPIOA_BASE

#define GPIOA_BASE (AHB2PERIPH_BASE + 0x00000000UL)

◆ GPIOB_BASE

#define GPIOB_BASE (AHB2PERIPH_BASE + 0x00000400UL)

◆ GPIOC_BASE

#define GPIOC_BASE (AHB2PERIPH_BASE + 0x00000800UL)

◆ GPIOD_BASE

#define GPIOD_BASE (AHB2PERIPH_BASE + 0x00000C00UL)

◆ GPIOE_BASE

#define GPIOE_BASE (AHB2PERIPH_BASE + 0x00001000UL)

◆ GPIOF_BASE

#define GPIOF_BASE (AHB2PERIPH_BASE + 0x00001400UL)

◆ GPIOG_BASE

#define GPIOG_BASE (AHB2PERIPH_BASE + 0x00001800UL)

◆ GPIOH_BASE

#define GPIOH_BASE (AHB2PERIPH_BASE + 0x00001C00UL)

AHB3 peripherals

◆ I2C1_BASE

#define I2C1_BASE (APB1PERIPH_BASE + 0x00005400UL)

◆ I2C2_BASE

#define I2C2_BASE (APB1PERIPH_BASE + 0x00005800UL)

◆ I2C3_BASE

#define I2C3_BASE (APB1PERIPH_BASE + 0x00007800UL)

APB2 peripherals

◆ I2S2ext_BASE

#define I2S2ext_BASE (APB1PERIPH_BASE + 0x00003400UL)

◆ I2S3ext_BASE

#define I2S3ext_BASE (APB1PERIPH_BASE + 0x00004000UL)

◆ IWDG_BASE

#define IWDG_BASE (APB1PERIPH_BASE + 0x00003000UL)

◆ OB_BASE

#define OB_BASE 0x1FFFF800UL

Flash Option Bytes base address

◆ OPAMP1_BASE

#define OPAMP1_BASE (APB2PERIPH_BASE + 0x00000038UL)

◆ OPAMP2_BASE

#define OPAMP2_BASE (APB2PERIPH_BASE + 0x0000003CUL)

◆ OPAMP3_BASE

#define OPAMP3_BASE (APB2PERIPH_BASE + 0x00000040UL)

◆ OPAMP4_BASE

#define OPAMP4_BASE (APB2PERIPH_BASE + 0x00000044UL)

◆ OPAMP_BASE

#define OPAMP_BASE OPAMP1_BASE

◆ PERIPH_BASE

#define PERIPH_BASE 0x40000000UL

Peripheral base address in the alias region

◆ PERIPH_BB_BASE

#define PERIPH_BB_BASE 0x42000000UL

Peripheral base address in the bit-band region Peripheral memory map

◆ PWR_BASE

#define PWR_BASE (APB1PERIPH_BASE + 0x00007000UL)

◆ RCC_BASE

#define RCC_BASE (AHB1PERIPH_BASE + 0x00001000UL)

◆ RTC_BASE

#define RTC_BASE (APB1PERIPH_BASE + 0x00002800UL)

◆ SPI1_BASE

#define SPI1_BASE (APB2PERIPH_BASE + 0x00003000UL)

◆ SPI2_BASE

#define SPI2_BASE (APB1PERIPH_BASE + 0x00003800UL)

◆ SPI3_BASE

#define SPI3_BASE (APB1PERIPH_BASE + 0x00003C00UL)

◆ SPI4_BASE

#define SPI4_BASE (APB2PERIPH_BASE + 0x00003C00UL)

◆ SRAM_BASE

#define SRAM_BASE 0x20000000UL

SRAM base address in the alias region

◆ SRAM_BB_BASE

#define SRAM_BB_BASE 0x22000000UL

SRAM base address in the bit-band region

◆ SYSCFG_BASE

#define SYSCFG_BASE (APB2PERIPH_BASE + 0x00000000UL)

◆ TIM15_BASE

#define TIM15_BASE (APB2PERIPH_BASE + 0x00004000UL)

◆ TIM16_BASE

#define TIM16_BASE (APB2PERIPH_BASE + 0x00004400UL)

◆ TIM17_BASE

#define TIM17_BASE (APB2PERIPH_BASE + 0x00004800UL)

◆ TIM1_BASE

#define TIM1_BASE (APB2PERIPH_BASE + 0x00002C00UL)

◆ TIM20_BASE

#define TIM20_BASE (APB2PERIPH_BASE + 0x00005000UL)

AHB1 peripherals

◆ TIM2_BASE

#define TIM2_BASE (APB1PERIPH_BASE + 0x00000000UL)

◆ TIM3_BASE

#define TIM3_BASE (APB1PERIPH_BASE + 0x00000400UL)

◆ TIM4_BASE

#define TIM4_BASE (APB1PERIPH_BASE + 0x00000800UL)

◆ TIM6_BASE

#define TIM6_BASE (APB1PERIPH_BASE + 0x00001000UL)

◆ TIM7_BASE

#define TIM7_BASE (APB1PERIPH_BASE + 0x00001400UL)

◆ TIM8_BASE

#define TIM8_BASE (APB2PERIPH_BASE + 0x00003400UL)

◆ TSC_BASE

#define TSC_BASE (AHB1PERIPH_BASE + 0x00004000UL)

AHB2 peripherals

◆ UART4_BASE

#define UART4_BASE (APB1PERIPH_BASE + 0x00004C00UL)

◆ UART5_BASE

#define UART5_BASE (APB1PERIPH_BASE + 0x00005000UL)

◆ UID_BASE

#define UID_BASE 0x1FFFF7ACUL

Unique device ID register base address

◆ USART1_BASE

#define USART1_BASE (APB2PERIPH_BASE + 0x00003800UL)

◆ USART2_BASE

#define USART2_BASE (APB1PERIPH_BASE + 0x00004400UL)

◆ USART3_BASE

#define USART3_BASE (APB1PERIPH_BASE + 0x00004800UL)

◆ USB_BASE

#define USB_BASE (APB1PERIPH_BASE + 0x00005C00UL)

USB_IP Peripheral Registers base address

◆ USB_PMAADDR

#define USB_PMAADDR (APB1PERIPH_BASE + 0x00006000UL)

USB_IP Packet Memory Area base address

◆ WWDG_BASE

#define WWDG_BASE (APB1PERIPH_BASE + 0x00002C00UL)

Macros