Macros
#define	TIM_DMABURSTLENGTH_1TRANSFER 0x00000000U

#define	TIM_DMABURSTLENGTH_2TRANSFERS 0x00000100U

#define	TIM_DMABURSTLENGTH_3TRANSFERS 0x00000200U

#define	TIM_DMABURSTLENGTH_4TRANSFERS 0x00000300U

#define	TIM_DMABURSTLENGTH_5TRANSFERS 0x00000400U

#define	TIM_DMABURSTLENGTH_6TRANSFERS 0x00000500U

#define	TIM_DMABURSTLENGTH_7TRANSFERS 0x00000600U

#define	TIM_DMABURSTLENGTH_8TRANSFERS 0x00000700U

#define	TIM_DMABURSTLENGTH_9TRANSFERS 0x00000800U

#define	TIM_DMABURSTLENGTH_10TRANSFERS 0x00000900U

#define	TIM_DMABURSTLENGTH_11TRANSFERS 0x00000A00U

#define	TIM_DMABURSTLENGTH_12TRANSFERS 0x00000B00U

#define	TIM_DMABURSTLENGTH_13TRANSFERS 0x00000C00U

#define	TIM_DMABURSTLENGTH_14TRANSFERS 0x00000D00U

#define	TIM_DMABURSTLENGTH_15TRANSFERS 0x00000E00U

#define	TIM_DMABURSTLENGTH_16TRANSFERS 0x00000F00U

#define	TIM_DMABURSTLENGTH_17TRANSFERS 0x00001000U

#define	TIM_DMABURSTLENGTH_18TRANSFERS 0x00001100U

Detailed Description

Macro Definition Documentation

◆ TIM_DMABURSTLENGTH_10TRANSFERS

#define TIM_DMABURSTLENGTH_10TRANSFERS 0x00000900U

The transfer is done to 10 registers starting from TIMx_CR1 + TIMx_DCR.DBA

◆ TIM_DMABURSTLENGTH_11TRANSFERS

#define TIM_DMABURSTLENGTH_11TRANSFERS 0x00000A00U

The transfer is done to 11 registers starting from TIMx_CR1 + TIMx_DCR.DBA

◆ TIM_DMABURSTLENGTH_12TRANSFERS

#define TIM_DMABURSTLENGTH_12TRANSFERS 0x00000B00U

The transfer is done to 12 registers starting from TIMx_CR1 + TIMx_DCR.DBA

◆ TIM_DMABURSTLENGTH_13TRANSFERS

#define TIM_DMABURSTLENGTH_13TRANSFERS 0x00000C00U

The transfer is done to 13 registers starting from TIMx_CR1 + TIMx_DCR.DBA

◆ TIM_DMABURSTLENGTH_14TRANSFERS

#define TIM_DMABURSTLENGTH_14TRANSFERS 0x00000D00U

The transfer is done to 14 registers starting from TIMx_CR1 + TIMx_DCR.DBA

◆ TIM_DMABURSTLENGTH_15TRANSFERS

#define TIM_DMABURSTLENGTH_15TRANSFERS 0x00000E00U

The transfer is done to 15 registers starting from TIMx_CR1 + TIMx_DCR.DBA

◆ TIM_DMABURSTLENGTH_16TRANSFERS

#define TIM_DMABURSTLENGTH_16TRANSFERS 0x00000F00U

The transfer is done to 16 registers starting from TIMx_CR1 + TIMx_DCR.DBA

◆ TIM_DMABURSTLENGTH_17TRANSFERS

#define TIM_DMABURSTLENGTH_17TRANSFERS 0x00001000U

The transfer is done to 17 registers starting from TIMx_CR1 + TIMx_DCR.DBA

◆ TIM_DMABURSTLENGTH_18TRANSFERS

#define TIM_DMABURSTLENGTH_18TRANSFERS 0x00001100U

The transfer is done to 18 registers starting from TIMx_CR1 + TIMx_DCR.DBA

◆ TIM_DMABURSTLENGTH_1TRANSFER

#define TIM_DMABURSTLENGTH_1TRANSFER 0x00000000U

The transfer is done to 1 register starting from TIMx_CR1 + TIMx_DCR.DBA

◆ TIM_DMABURSTLENGTH_2TRANSFERS

#define TIM_DMABURSTLENGTH_2TRANSFERS 0x00000100U

The transfer is done to 2 registers starting from TIMx_CR1 + TIMx_DCR.DBA

◆ TIM_DMABURSTLENGTH_3TRANSFERS

#define TIM_DMABURSTLENGTH_3TRANSFERS 0x00000200U

The transfer is done to 3 registers starting from TIMx_CR1 + TIMx_DCR.DBA

◆ TIM_DMABURSTLENGTH_4TRANSFERS

#define TIM_DMABURSTLENGTH_4TRANSFERS 0x00000300U

The transfer is done to 4 registers starting from TIMx_CR1 + TIMx_DCR.DBA

◆ TIM_DMABURSTLENGTH_5TRANSFERS

#define TIM_DMABURSTLENGTH_5TRANSFERS 0x00000400U

The transfer is done to 5 registers starting from TIMx_CR1 + TIMx_DCR.DBA

◆ TIM_DMABURSTLENGTH_6TRANSFERS

#define TIM_DMABURSTLENGTH_6TRANSFERS 0x00000500U

The transfer is done to 6 registers starting from TIMx_CR1 + TIMx_DCR.DBA

◆ TIM_DMABURSTLENGTH_7TRANSFERS

#define TIM_DMABURSTLENGTH_7TRANSFERS 0x00000600U

The transfer is done to 7 registers starting from TIMx_CR1 + TIMx_DCR.DBA

◆ TIM_DMABURSTLENGTH_8TRANSFERS

#define TIM_DMABURSTLENGTH_8TRANSFERS 0x00000700U

The transfer is done to 8 registers starting from TIMx_CR1 + TIMx_DCR.DBA

◆ TIM_DMABURSTLENGTH_9TRANSFERS

#define TIM_DMABURSTLENGTH_9TRANSFERS 0x00000800U

The transfer is done to 9 registers starting from TIMx_CR1 + TIMx_DCR.DBA

Macros