36#ifndef __STM32F3xx_LL_BUS_H
37#define __STM32F3xx_LL_BUS_H
72#define LL_AHB1_GRP1_PERIPH_ALL (uint32_t)0xFFFFFFFFU
73#define LL_AHB1_GRP1_PERIPH_DMA1 RCC_AHBENR_DMA1EN
75#define LL_AHB1_GRP1_PERIPH_DMA2 RCC_AHBENR_DMA2EN
77#define LL_AHB1_GRP1_PERIPH_SRAM RCC_AHBENR_SRAMEN
78#define LL_AHB1_GRP1_PERIPH_FLASH RCC_AHBENR_FLITFEN
80#define LL_AHB1_GRP1_PERIPH_FMC RCC_AHBENR_FMCEN
82#define LL_AHB1_GRP1_PERIPH_CRC RCC_AHBENR_CRCEN
84#define LL_AHB1_GRP1_PERIPH_GPIOH RCC_AHBENR_GPIOHEN
86#define LL_AHB1_GRP1_PERIPH_GPIOA RCC_AHBENR_GPIOAEN
87#define LL_AHB1_GRP1_PERIPH_GPIOB RCC_AHBENR_GPIOBEN
88#define LL_AHB1_GRP1_PERIPH_GPIOC RCC_AHBENR_GPIOCEN
89#define LL_AHB1_GRP1_PERIPH_GPIOD RCC_AHBENR_GPIODEN
91#define LL_AHB1_GRP1_PERIPH_GPIOE RCC_AHBENR_GPIOEEN
93#define LL_AHB1_GRP1_PERIPH_GPIOF RCC_AHBENR_GPIOFEN
95#define LL_AHB1_GRP1_PERIPH_GPIOG RCC_AHBENR_GPIOGEN
97#define LL_AHB1_GRP1_PERIPH_TSC RCC_AHBENR_TSCEN
98#if defined(RCC_AHBENR_ADC1EN)
99#define LL_AHB1_GRP1_PERIPH_ADC1 RCC_AHBENR_ADC1EN
101#if defined(ADC1_2_COMMON)
102#define LL_AHB1_GRP1_PERIPH_ADC12 RCC_AHBENR_ADC12EN
104#if defined(ADC3_4_COMMON)
105#define LL_AHB1_GRP1_PERIPH_ADC34 RCC_AHBENR_ADC34EN
114#define LL_APB1_GRP1_PERIPH_ALL (uint32_t)0xFFFFFFFFU
115#define LL_APB1_GRP1_PERIPH_TIM2 RCC_APB1ENR_TIM2EN
117#define LL_APB1_GRP1_PERIPH_TIM3 RCC_APB1ENR_TIM3EN
120#define LL_APB1_GRP1_PERIPH_TIM4 RCC_APB1ENR_TIM4EN
123#define LL_APB1_GRP1_PERIPH_TIM5 RCC_APB1ENR_TIM5EN
125#define LL_APB1_GRP1_PERIPH_TIM6 RCC_APB1ENR_TIM6EN
127#define LL_APB1_GRP1_PERIPH_TIM7 RCC_APB1ENR_TIM7EN
130#define LL_APB1_GRP1_PERIPH_TIM12 RCC_APB1ENR_TIM12EN
133#define LL_APB1_GRP1_PERIPH_TIM13 RCC_APB1ENR_TIM13EN
136#define LL_APB1_GRP1_PERIPH_TIM14 RCC_APB1ENR_TIM14EN
139#define LL_APB1_GRP1_PERIPH_TIM18 RCC_APB1ENR_TIM18EN
141#define LL_APB1_GRP1_PERIPH_WWDG RCC_APB1ENR_WWDGEN
143#define LL_APB1_GRP1_PERIPH_SPI2 RCC_APB1ENR_SPI2EN
146#define LL_APB1_GRP1_PERIPH_SPI3 RCC_APB1ENR_SPI3EN
148#define LL_APB1_GRP1_PERIPH_USART2 RCC_APB1ENR_USART2EN
149#define LL_APB1_GRP1_PERIPH_USART3 RCC_APB1ENR_USART3EN
151#define LL_APB1_GRP1_PERIPH_UART4 RCC_APB1ENR_UART4EN
154#define LL_APB1_GRP1_PERIPH_UART5 RCC_APB1ENR_UART5EN
156#define LL_APB1_GRP1_PERIPH_I2C1 RCC_APB1ENR_I2C1EN
158#define LL_APB1_GRP1_PERIPH_I2C2 RCC_APB1ENR_I2C2EN
161#define LL_APB1_GRP1_PERIPH_USB RCC_APB1ENR_USBEN
164#define LL_APB1_GRP1_PERIPH_CAN RCC_APB1ENR_CANEN
167#define LL_APB1_GRP1_PERIPH_DAC2 RCC_APB1ENR_DAC2EN
169#define LL_APB1_GRP1_PERIPH_PWR RCC_APB1ENR_PWREN
170#define LL_APB1_GRP1_PERIPH_DAC1 RCC_APB1ENR_DAC1EN
172#define LL_APB1_GRP1_PERIPH_CEC RCC_APB1ENR_CECEN
175#define LL_APB1_GRP1_PERIPH_I2C3 RCC_APB1ENR_I2C3EN
184#define LL_APB2_GRP1_PERIPH_ALL (uint32_t)0xFFFFFFFFU
185#define LL_APB2_GRP1_PERIPH_SYSCFG RCC_APB2ENR_SYSCFGEN
186#if defined(RCC_APB2ENR_ADC1EN)
187#define LL_APB2_GRP1_PERIPH_ADC1 RCC_APB2ENR_ADC1EN
190#define LL_APB2_GRP1_PERIPH_TIM1 RCC_APB2ENR_TIM1EN
193#define LL_APB2_GRP1_PERIPH_SPI1 RCC_APB2ENR_SPI1EN
196#define LL_APB2_GRP1_PERIPH_TIM8 RCC_APB2ENR_TIM8EN
198#define LL_APB2_GRP1_PERIPH_USART1 RCC_APB2ENR_USART1EN
200#define LL_APB2_GRP1_PERIPH_SPI4 RCC_APB2ENR_SPI4EN
202#define LL_APB2_GRP1_PERIPH_TIM15 RCC_APB2ENR_TIM15EN
203#define LL_APB2_GRP1_PERIPH_TIM16 RCC_APB2ENR_TIM16EN
204#define LL_APB2_GRP1_PERIPH_TIM17 RCC_APB2ENR_TIM17EN
206#define LL_APB2_GRP1_PERIPH_TIM19 RCC_APB2ENR_TIM19EN
209#define LL_APB2_GRP1_PERIPH_TIM20 RCC_APB2ENR_TIM20EN
212#define LL_APB2_GRP1_PERIPH_HRTIM1 RCC_APB2ENR_HRTIM1EN
215#define LL_APB2_GRP1_PERIPH_SDADC1 RCC_APB2ENR_SDADC1EN
218#define LL_APB2_GRP1_PERIPH_SDADC2 RCC_APB2ENR_SDADC2EN
221#define LL_APB2_GRP1_PERIPH_SDADC3 RCC_APB2ENR_SDADC3EN
287 __IO uint32_t tmpreg;
339 return (
READ_BIT(
RCC->AHBENR, Periphs) == Periphs);
537 __IO uint32_t tmpreg;
605 return (
READ_BIT(
RCC->APB1ENR, Periphs) == Periphs);
851 __IO uint32_t tmpreg;
899 return (
READ_BIT(
RCC->APB2ENR, Periphs) == Periphs);
#define __STATIC_INLINE
Definition: cmsis_armcc.h:59
#define __IO
Definition: core_armv8mbl.h:196
#define CLEAR_BIT(REG, BIT)
Definition: stm32f3xx.h:192
#define SET_BIT(REG, BIT)
Definition: stm32f3xx.h:190
#define READ_BIT(REG, BIT)
Definition: stm32f3xx.h:194
#define RCC
Definition: stm32f303xe.h:977
CMSIS STM32F3xx Device Peripheral Access Layer Header File.