36#ifndef __STM32F3xx_LL_CORTEX_H
37#define __STM32F3xx_LL_CORTEX_H
70#define LL_SYSTICK_CLKSOURCE_HCLK_DIV8 0x00000000U
71#define LL_SYSTICK_CLKSOURCE_HCLK SysTick_CTRL_CLKSOURCE_Msk
79#define LL_HANDLER_FAULT_USG SCB_SHCSR_USGFAULTENA_Msk
80#define LL_HANDLER_FAULT_BUS SCB_SHCSR_BUSFAULTENA_Msk
81#define LL_HANDLER_FAULT_MEM SCB_SHCSR_MEMFAULTENA_Msk
91#define LL_MPU_CTRL_HFNMI_PRIVDEF_NONE 0x00000000U
92#define LL_MPU_CTRL_HARDFAULT_NMI MPU_CTRL_HFNMIENA_Msk
93#define LL_MPU_CTRL_PRIVILEGED_DEFAULT MPU_CTRL_PRIVDEFENA_Msk
94#define LL_MPU_CTRL_HFNMI_PRIVDEF (MPU_CTRL_HFNMIENA_Msk | MPU_CTRL_PRIVDEFENA_Msk)
102#define LL_MPU_REGION_NUMBER0 0x00U
103#define LL_MPU_REGION_NUMBER1 0x01U
104#define LL_MPU_REGION_NUMBER2 0x02U
105#define LL_MPU_REGION_NUMBER3 0x03U
106#define LL_MPU_REGION_NUMBER4 0x04U
107#define LL_MPU_REGION_NUMBER5 0x05U
108#define LL_MPU_REGION_NUMBER6 0x06U
109#define LL_MPU_REGION_NUMBER7 0x07U
117#define LL_MPU_REGION_SIZE_32B (0x04U << MPU_RASR_SIZE_Pos)
118#define LL_MPU_REGION_SIZE_64B (0x05U << MPU_RASR_SIZE_Pos)
119#define LL_MPU_REGION_SIZE_128B (0x06U << MPU_RASR_SIZE_Pos)
120#define LL_MPU_REGION_SIZE_256B (0x07U << MPU_RASR_SIZE_Pos)
121#define LL_MPU_REGION_SIZE_512B (0x08U << MPU_RASR_SIZE_Pos)
122#define LL_MPU_REGION_SIZE_1KB (0x09U << MPU_RASR_SIZE_Pos)
123#define LL_MPU_REGION_SIZE_2KB (0x0AU << MPU_RASR_SIZE_Pos)
124#define LL_MPU_REGION_SIZE_4KB (0x0BU << MPU_RASR_SIZE_Pos)
125#define LL_MPU_REGION_SIZE_8KB (0x0CU << MPU_RASR_SIZE_Pos)
126#define LL_MPU_REGION_SIZE_16KB (0x0DU << MPU_RASR_SIZE_Pos)
127#define LL_MPU_REGION_SIZE_32KB (0x0EU << MPU_RASR_SIZE_Pos)
128#define LL_MPU_REGION_SIZE_64KB (0x0FU << MPU_RASR_SIZE_Pos)
129#define LL_MPU_REGION_SIZE_128KB (0x10U << MPU_RASR_SIZE_Pos)
130#define LL_MPU_REGION_SIZE_256KB (0x11U << MPU_RASR_SIZE_Pos)
131#define LL_MPU_REGION_SIZE_512KB (0x12U << MPU_RASR_SIZE_Pos)
132#define LL_MPU_REGION_SIZE_1MB (0x13U << MPU_RASR_SIZE_Pos)
133#define LL_MPU_REGION_SIZE_2MB (0x14U << MPU_RASR_SIZE_Pos)
134#define LL_MPU_REGION_SIZE_4MB (0x15U << MPU_RASR_SIZE_Pos)
135#define LL_MPU_REGION_SIZE_8MB (0x16U << MPU_RASR_SIZE_Pos)
136#define LL_MPU_REGION_SIZE_16MB (0x17U << MPU_RASR_SIZE_Pos)
137#define LL_MPU_REGION_SIZE_32MB (0x18U << MPU_RASR_SIZE_Pos)
138#define LL_MPU_REGION_SIZE_64MB (0x19U << MPU_RASR_SIZE_Pos)
139#define LL_MPU_REGION_SIZE_128MB (0x1AU << MPU_RASR_SIZE_Pos)
140#define LL_MPU_REGION_SIZE_256MB (0x1BU << MPU_RASR_SIZE_Pos)
141#define LL_MPU_REGION_SIZE_512MB (0x1CU << MPU_RASR_SIZE_Pos)
142#define LL_MPU_REGION_SIZE_1GB (0x1DU << MPU_RASR_SIZE_Pos)
143#define LL_MPU_REGION_SIZE_2GB (0x1EU << MPU_RASR_SIZE_Pos)
144#define LL_MPU_REGION_SIZE_4GB (0x1FU << MPU_RASR_SIZE_Pos)
152#define LL_MPU_REGION_NO_ACCESS (0x00U << MPU_RASR_AP_Pos)
153#define LL_MPU_REGION_PRIV_RW (0x01U << MPU_RASR_AP_Pos)
154#define LL_MPU_REGION_PRIV_RW_URO (0x02U << MPU_RASR_AP_Pos)
155#define LL_MPU_REGION_FULL_ACCESS (0x03U << MPU_RASR_AP_Pos)
156#define LL_MPU_REGION_PRIV_RO (0x05U << MPU_RASR_AP_Pos)
157#define LL_MPU_REGION_PRIV_RO_URO (0x06U << MPU_RASR_AP_Pos)
165#define LL_MPU_TEX_LEVEL0 (0x00U << MPU_RASR_TEX_Pos)
166#define LL_MPU_TEX_LEVEL1 (0x01U << MPU_RASR_TEX_Pos)
167#define LL_MPU_TEX_LEVEL2 (0x02U << MPU_RASR_TEX_Pos)
168#define LL_MPU_TEX_LEVEL4 (0x04U << MPU_RASR_TEX_Pos)
176#define LL_MPU_INSTRUCTION_ACCESS_ENABLE 0x00U
177#define LL_MPU_INSTRUCTION_ACCESS_DISABLE MPU_RASR_XN_Msk
185#define LL_MPU_ACCESS_SHAREABLE MPU_RASR_S_Msk
186#define LL_MPU_ACCESS_NOT_SHAREABLE 0x00U
194#define LL_MPU_ACCESS_CACHEABLE MPU_RASR_C_Msk
195#define LL_MPU_ACCESS_NOT_CACHEABLE 0x00U
203#define LL_MPU_ACCESS_BUFFERABLE MPU_RASR_B_Msk
204#define LL_MPU_ACCESS_NOT_BUFFERABLE 0x00U
493 WRITE_REG(MPU->CTRL, (MPU_CTRL_ENABLE_Msk | Options));
520 return (
READ_BIT(MPU->CTRL, MPU_CTRL_ENABLE_Msk) == (MPU_CTRL_ENABLE_Msk));
542 SET_BIT(MPU->RASR, MPU_RASR_ENABLE_Msk);
583__STATIC_INLINE void LL_MPU_ConfigRegion(uint32_t Region, uint32_t SubRegionDisable, uint32_t Address, uint32_t Attributes)
588 WRITE_REG(MPU->RBAR, (Address & 0xFFFFFFE0U));
590 WRITE_REG(MPU->RASR, (MPU_RASR_ENABLE_Msk | Attributes | SubRegionDisable << MPU_RASR_SRD_Pos));
613 CLEAR_BIT(MPU->RASR, MPU_RASR_ENABLE_Msk);
#define __STATIC_INLINE
Definition: cmsis_armcc.h:59
#define __DSB()
Data Synchronization Barrier.
Definition: cmsis_armcc.h:429
#define __DMB()
Data Memory Barrier.
Definition: cmsis_armcc.h:440
#define __ISB()
Instruction Synchronization Barrier.
Definition: cmsis_armcc.h:418
#define SCB_CPUID_IMPLEMENTER_Msk
Definition: core_armv8mbl.h:400
#define SCB_CPUID_VARIANT_Pos
Definition: core_armv8mbl.h:402
#define SCB_CPUID_REVISION_Msk
Definition: core_armv8mbl.h:412
#define SCB_CPUID_REVISION_Pos
Definition: core_armv8mbl.h:411
#define SCB_SCR_SLEEPONEXIT_Msk
Definition: core_armv8mbl.h:496
#define SCB_CPUID_IMPLEMENTER_Pos
Definition: core_armv8mbl.h:399
#define SCB_CPUID_PARTNO_Pos
Definition: core_armv8mbl.h:408
#define SCB_SCR_SLEEPDEEP_Msk
Definition: core_armv8mbl.h:493
#define SCB_CPUID_PARTNO_Msk
Definition: core_armv8mbl.h:409
#define SCB_CPUID_VARIANT_Msk
Definition: core_armv8mbl.h:403
#define SCB_CPUID_ARCHITECTURE_Pos
Definition: core_armv8mbl.h:405
#define SCB_CPUID_ARCHITECTURE_Msk
Definition: core_armv8mbl.h:406
#define SCB_SCR_SEVONPEND_Msk
Definition: core_armv8mbl.h:487
#define SysTick_CTRL_COUNTFLAG_Msk
Definition: core_armv8mbl.h:568
#define SysTick_CTRL_TICKINT_Msk
Definition: core_armv8mbl.h:574
#define SCB
Definition: core_armv8mbl.h:1122
#define SysTick
Definition: core_armv8mbl.h:1123
#define LL_SYSTICK_CLKSOURCE_HCLK
Definition: stm32f3xx_ll_cortex.h:71
__STATIC_INLINE void LL_HANDLER_DisableFault(uint32_t Fault)
Disable a fault in System handler control register (SHCSR) @rmtoll SCB_SHCSR MEMFAULTENA LL_HANDLER_D...
Definition: stm32f3xx_ll_cortex.h:407
__STATIC_INLINE void LL_HANDLER_EnableFault(uint32_t Fault)
Enable a fault in System handler control register (SHCSR) @rmtoll SCB_SHCSR MEMFAULTENA LL_HANDLER_En...
Definition: stm32f3xx_ll_cortex.h:392
__STATIC_INLINE void LL_LPM_EnableDeepSleep(void)
Processor uses deep sleep as its low power mode @rmtoll SCB_SCR SLEEPDEEP LL_LPM_EnableDeepSleep.
Definition: stm32f3xx_ll_cortex.h:321
__STATIC_INLINE void LL_LPM_DisableSleepOnExit(void)
Do not sleep when returning to Thread mode.
Definition: stm32f3xx_ll_cortex.h:345
__STATIC_INLINE void LL_LPM_EnableSleep(void)
Processor uses sleep as its low power mode @rmtoll SCB_SCR SLEEPDEEP LL_LPM_EnableSleep.
Definition: stm32f3xx_ll_cortex.h:310
__STATIC_INLINE void LL_LPM_EnableSleepOnExit(void)
Configures sleep-on-exit when returning from Handler mode to Thread mode.
Definition: stm32f3xx_ll_cortex.h:334
__STATIC_INLINE void LL_LPM_EnableEventOnPend(void)
Enabled events and all interrupts, including disabled interrupts, can wakeup the processor.
Definition: stm32f3xx_ll_cortex.h:357
__STATIC_INLINE void LL_LPM_DisableEventOnPend(void)
Only enabled interrupts or events can wakeup the processor, disabled interrupts are excluded @rmtoll ...
Definition: stm32f3xx_ll_cortex.h:369
__STATIC_INLINE uint32_t LL_CPUID_GetVariant(void)
Get Variant number (The r value in the rnpn product revision identifier) @rmtoll SCB_CPUID VARIANT LL...
Definition: stm32f3xx_ll_cortex.h:436
__STATIC_INLINE uint32_t LL_CPUID_GetImplementer(void)
Get Implementer code @rmtoll SCB_CPUID IMPLEMENTER LL_CPUID_GetImplementer.
Definition: stm32f3xx_ll_cortex.h:426
__STATIC_INLINE uint32_t LL_CPUID_GetRevision(void)
Get Revision number (The p value in the rnpn product revision identifier, indicates patch release) @r...
Definition: stm32f3xx_ll_cortex.h:466
__STATIC_INLINE uint32_t LL_CPUID_GetConstant(void)
Get Constant number @rmtoll SCB_CPUID ARCHITECTURE LL_CPUID_GetConstant.
Definition: stm32f3xx_ll_cortex.h:446
__STATIC_INLINE uint32_t LL_CPUID_GetParNo(void)
Get Part number @rmtoll SCB_CPUID PARTNO LL_CPUID_GetParNo.
Definition: stm32f3xx_ll_cortex.h:456
__STATIC_INLINE void LL_SYSTICK_DisableIT(void)
Disable SysTick exception request @rmtoll STK_CTRL TICKINT LL_SYSTICK_DisableIT.
Definition: stm32f3xx_ll_cortex.h:282
__STATIC_INLINE uint32_t LL_SYSTICK_GetClkSource(void)
Get the SysTick clock source @rmtoll STK_CTRL CLKSOURCE LL_SYSTICK_GetClkSource.
Definition: stm32f3xx_ll_cortex.h:262
__STATIC_INLINE void LL_SYSTICK_EnableIT(void)
Enable SysTick exception request @rmtoll STK_CTRL TICKINT LL_SYSTICK_EnableIT.
Definition: stm32f3xx_ll_cortex.h:272
__STATIC_INLINE void LL_SYSTICK_SetClkSource(uint32_t Source)
Configures the SysTick clock source @rmtoll STK_CTRL CLKSOURCE LL_SYSTICK_SetClkSource.
Definition: stm32f3xx_ll_cortex.h:243
__STATIC_INLINE uint32_t LL_SYSTICK_IsEnabledIT(void)
Checks if the SYSTICK interrupt is enabled or disabled.
Definition: stm32f3xx_ll_cortex.h:292
__STATIC_INLINE uint32_t LL_SYSTICK_IsActiveCounterFlag(void)
This function checks if the Systick counter flag is active or not.
Definition: stm32f3xx_ll_cortex.h:230
#define CLEAR_BIT(REG, BIT)
Definition: stm32f3xx.h:192
#define SET_BIT(REG, BIT)
Definition: stm32f3xx.h:190
#define WRITE_REG(REG, VAL)
Definition: stm32f3xx.h:198
#define READ_BIT(REG, BIT)
Definition: stm32f3xx.h:194
CMSIS STM32F3xx Device Peripheral Access Layer Header File.