33#ifndef __STM32F3xx_LL_UTILS_H
34#define __STM32F3xx_LL_UTILS_H
60#define LL_MAX_DELAY 0xFFFFFFFFU
65#define UID_BASE_ADDRESS UID_BASE
70#define FLASHSIZE_BASE_ADDRESS FLASHSIZE_BASE
75#define PACKAGE_BASE_ADDRESS PACKAGE_BASE
103#if defined(RCC_PLLSRC_PREDIV1_SUPPORT)
155#define LL_UTILS_HSEBYPASS_OFF 0x00000000U
156#define LL_UTILS_HSEBYPASS_ON 0x00000001U
234 SysTick->LOAD = (uint32_t)((HCLKFrequency / Ticks) - 1UL);
252#if defined(FLASH_ACR_LATENCY)
#define __STATIC_INLINE
Definition: cmsis_armcc.h:59
#define SysTick_CTRL_ENABLE_Msk
Definition: core_armv8mbl.h:577
#define SysTick_CTRL_CLKSOURCE_Msk
Definition: core_armv8mbl.h:571
#define SysTick
Definition: core_armv8mbl.h:1123
#define READ_REG(REG)
Definition: stm32f3xx.h:200
ErrorStatus
Definition: stm32f3xx.h:177
__STATIC_INLINE uint32_t LL_GetFlashSize(void)
Get Flash memory size.
Definition: stm32f3xx_ll_utils.h:209
__STATIC_INLINE uint32_t LL_GetUID_Word0(void)
Get Word0 of the unique device identifier (UID based on 96 bits)
Definition: stm32f3xx_ll_utils.h:180
__STATIC_INLINE uint32_t LL_GetUID_Word1(void)
Get Word1 of the unique device identifier (UID based on 96 bits)
Definition: stm32f3xx_ll_utils.h:189
__STATIC_INLINE uint32_t LL_GetUID_Word2(void)
Get Word2 of the unique device identifier (UID based on 96 bits)
Definition: stm32f3xx_ll_utils.h:198
void LL_SetSystemCoreClock(uint32_t HCLKFrequency)
ErrorStatus LL_PLL_ConfigSystemClock_HSI(LL_UTILS_PLLInitTypeDef *UTILS_PLLInitStruct, LL_UTILS_ClkInitTypeDef *UTILS_ClkInitStruct)
ErrorStatus LL_PLL_ConfigSystemClock_HSE(uint32_t HSEFrequency, uint32_t HSEBypass, LL_UTILS_PLLInitTypeDef *UTILS_PLLInitStruct, LL_UTILS_ClkInitTypeDef *UTILS_ClkInitStruct)
__STATIC_INLINE void LL_InitTick(uint32_t HCLKFrequency, uint32_t Ticks)
This function configures the Cortex-M SysTick source of the time base.
Definition: stm32f3xx_ll_utils.h:231
void LL_Init1msTick(uint32_t HCLKFrequency)
void LL_mDelay(uint32_t Delay)
#define UID_BASE_ADDRESS
Unique device ID register base address.
Definition: stm32f3xx_ll_utils.h:65
#define FLASHSIZE_BASE_ADDRESS
Flash size data register base address.
Definition: stm32f3xx_ll_utils.h:70
CMSIS STM32F3xx Device Peripheral Access Layer Header File.
UTILS System, AHB and APB buses clock configuration structure definition.
Definition: stm32f3xx_ll_utils.h:122
uint32_t APB1CLKDivider
Definition: stm32f3xx_ll_utils.h:129
uint32_t APB2CLKDivider
Definition: stm32f3xx_ll_utils.h:135
uint32_t AHBCLKDivider
Definition: stm32f3xx_ll_utils.h:123
UTILS PLL structure definition.
Definition: stm32f3xx_ll_utils.h:96
uint32_t PLLMul
Definition: stm32f3xx_ll_utils.h:97
uint32_t Prediv
Definition: stm32f3xx_ll_utils.h:110