25#if defined ( __ICCARM__ )
26 #pragma system_include
27#elif defined (__clang__)
28 #pragma clang system_header
31#ifndef __CORE_ARMV8MBL_H_GENERIC
32#define __CORE_ARMV8MBL_H_GENERIC
66#define __ARMv8MBL_CMSIS_VERSION_MAIN (__CM_CMSIS_VERSION_MAIN)
67#define __ARMv8MBL_CMSIS_VERSION_SUB (__CM_CMSIS_VERSION_SUB)
68#define __ARMv8MBL_CMSIS_VERSION ((__ARMv8MBL_CMSIS_VERSION_MAIN << 16U) | \
69 __ARMv8MBL_CMSIS_VERSION_SUB )
71#define __CORTEX_M ( 2U)
78#if defined ( __CC_ARM )
79 #if defined __TARGET_FPU_VFP
80 #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
83#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
84 #if defined __ARM_PCS_VFP
85 #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
88#elif defined ( __GNUC__ )
89 #if defined (__VFP_FP__) && !defined(__SOFTFP__)
90 #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
93#elif defined ( __ICCARM__ )
94 #if defined __ARMVFP__
95 #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
98#elif defined ( __TI_ARM__ )
99 #if defined __TI_VFP_SUPPORT__
100 #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
103#elif defined ( __TASKING__ )
104 #if defined __FPU_VFP__
105 #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
108#elif defined ( __CSMC__ )
109 #if ( __CSMC__ & 0x400U)
110 #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
124#ifndef __CMSIS_GENERIC
126#ifndef __CORE_ARMV8MBL_H_DEPENDANT
127#define __CORE_ARMV8MBL_H_DEPENDANT
134#if defined __CHECK_DEVICE_DEFINES
135 #ifndef __ARMv8MBL_REV
136 #define __ARMv8MBL_REV 0x0000U
137 #warning "__ARMv8MBL_REV not defined in device header file; using default!"
140 #ifndef __FPU_PRESENT
141 #define __FPU_PRESENT 0U
142 #warning "__FPU_PRESENT not defined in device header file; using default!"
145 #ifndef __MPU_PRESENT
146 #define __MPU_PRESENT 0U
147 #warning "__MPU_PRESENT not defined in device header file; using default!"
150 #ifndef __SAUREGION_PRESENT
151 #define __SAUREGION_PRESENT 0U
152 #warning "__SAUREGION_PRESENT not defined in device header file; using default!"
155 #ifndef __VTOR_PRESENT
156 #define __VTOR_PRESENT 0U
157 #warning "__VTOR_PRESENT not defined in device header file; using default!"
160 #ifndef __NVIC_PRIO_BITS
161 #define __NVIC_PRIO_BITS 2U
162 #warning "__NVIC_PRIO_BITS not defined in device header file; using default!"
165 #ifndef __Vendor_SysTickConfig
166 #define __Vendor_SysTickConfig 0U
167 #warning "__Vendor_SysTickConfig not defined in device header file; using default!"
170 #ifndef __ETM_PRESENT
171 #define __ETM_PRESENT 0U
172 #warning "__ETM_PRESENT not defined in device header file; using default!"
175 #ifndef __MTB_PRESENT
176 #define __MTB_PRESENT 0U
177 #warning "__MTB_PRESENT not defined in device header file; using default!"
193 #define __I volatile const
199#define __IM volatile const
201#define __IOM volatile
247#define APSR_N_Pos 31U
248#define APSR_N_Msk (1UL << APSR_N_Pos)
250#define APSR_Z_Pos 30U
251#define APSR_Z_Msk (1UL << APSR_Z_Pos)
253#define APSR_C_Pos 29U
254#define APSR_C_Msk (1UL << APSR_C_Pos)
256#define APSR_V_Pos 28U
257#define APSR_V_Msk (1UL << APSR_V_Pos)
274#define IPSR_ISR_Pos 0U
275#define IPSR_ISR_Msk (0x1FFUL )
298#define xPSR_N_Pos 31U
299#define xPSR_N_Msk (1UL << xPSR_N_Pos)
301#define xPSR_Z_Pos 30U
302#define xPSR_Z_Msk (1UL << xPSR_Z_Pos)
304#define xPSR_C_Pos 29U
305#define xPSR_C_Msk (1UL << xPSR_C_Pos)
307#define xPSR_V_Pos 28U
308#define xPSR_V_Msk (1UL << xPSR_V_Pos)
310#define xPSR_T_Pos 24U
311#define xPSR_T_Msk (1UL << xPSR_T_Pos)
313#define xPSR_ISR_Pos 0U
314#define xPSR_ISR_Msk (0x1FFUL )
332#define CONTROL_SPSEL_Pos 1U
333#define CONTROL_SPSEL_Msk (1UL << CONTROL_SPSEL_Pos)
335#define CONTROL_nPRIV_Pos 0U
336#define CONTROL_nPRIV_Msk (1UL )
354 uint32_t RESERVED0[16U];
356 uint32_t RSERVED1[16U];
358 uint32_t RESERVED2[16U];
360 uint32_t RESERVED3[16U];
362 uint32_t RESERVED4[16U];
364 uint32_t RESERVED5[16U];
385#if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1U)
399#define SCB_CPUID_IMPLEMENTER_Pos 24U
400#define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos)
402#define SCB_CPUID_VARIANT_Pos 20U
403#define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos)
405#define SCB_CPUID_ARCHITECTURE_Pos 16U
406#define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos)
408#define SCB_CPUID_PARTNO_Pos 4U
409#define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos)
411#define SCB_CPUID_REVISION_Pos 0U
412#define SCB_CPUID_REVISION_Msk (0xFUL )
415#define SCB_ICSR_PENDNMISET_Pos 31U
416#define SCB_ICSR_PENDNMISET_Msk (1UL << SCB_ICSR_PENDNMISET_Pos)
418#define SCB_ICSR_NMIPENDSET_Pos SCB_ICSR_PENDNMISET_Pos
419#define SCB_ICSR_NMIPENDSET_Msk SCB_ICSR_PENDNMISET_Msk
421#define SCB_ICSR_PENDNMICLR_Pos 30U
422#define SCB_ICSR_PENDNMICLR_Msk (1UL << SCB_ICSR_PENDNMICLR_Pos)
424#define SCB_ICSR_PENDSVSET_Pos 28U
425#define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos)
427#define SCB_ICSR_PENDSVCLR_Pos 27U
428#define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos)
430#define SCB_ICSR_PENDSTSET_Pos 26U
431#define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos)
433#define SCB_ICSR_PENDSTCLR_Pos 25U
434#define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos)
436#define SCB_ICSR_STTNS_Pos 24U
437#define SCB_ICSR_STTNS_Msk (1UL << SCB_ICSR_STTNS_Pos)
439#define SCB_ICSR_ISRPREEMPT_Pos 23U
440#define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos)
442#define SCB_ICSR_ISRPENDING_Pos 22U
443#define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos)
445#define SCB_ICSR_VECTPENDING_Pos 12U
446#define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos)
448#define SCB_ICSR_RETTOBASE_Pos 11U
449#define SCB_ICSR_RETTOBASE_Msk (1UL << SCB_ICSR_RETTOBASE_Pos)
451#define SCB_ICSR_VECTACTIVE_Pos 0U
452#define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL )
454#if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1U)
456#define SCB_VTOR_TBLOFF_Pos 7U
457#define SCB_VTOR_TBLOFF_Msk (0x1FFFFFFUL << SCB_VTOR_TBLOFF_Pos)
461#define SCB_AIRCR_VECTKEY_Pos 16U
462#define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos)
464#define SCB_AIRCR_VECTKEYSTAT_Pos 16U
465#define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos)
467#define SCB_AIRCR_ENDIANESS_Pos 15U
468#define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos)
470#define SCB_AIRCR_PRIS_Pos 14U
471#define SCB_AIRCR_PRIS_Msk (1UL << SCB_AIRCR_PRIS_Pos)
473#define SCB_AIRCR_BFHFNMINS_Pos 13U
474#define SCB_AIRCR_BFHFNMINS_Msk (1UL << SCB_AIRCR_BFHFNMINS_Pos)
476#define SCB_AIRCR_SYSRESETREQS_Pos 3U
477#define SCB_AIRCR_SYSRESETREQS_Msk (1UL << SCB_AIRCR_SYSRESETREQS_Pos)
479#define SCB_AIRCR_SYSRESETREQ_Pos 2U
480#define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos)
482#define SCB_AIRCR_VECTCLRACTIVE_Pos 1U
483#define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos)
486#define SCB_SCR_SEVONPEND_Pos 4U
487#define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos)
489#define SCB_SCR_SLEEPDEEPS_Pos 3U
490#define SCB_SCR_SLEEPDEEPS_Msk (1UL << SCB_SCR_SLEEPDEEPS_Pos)
492#define SCB_SCR_SLEEPDEEP_Pos 2U
493#define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos)
495#define SCB_SCR_SLEEPONEXIT_Pos 1U
496#define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos)
499#define SCB_CCR_BP_Pos 18U
500#define SCB_CCR_BP_Msk (1UL << SCB_CCR_BP_Pos)
502#define SCB_CCR_IC_Pos 17U
503#define SCB_CCR_IC_Msk (1UL << SCB_CCR_IC_Pos)
505#define SCB_CCR_DC_Pos 16U
506#define SCB_CCR_DC_Msk (1UL << SCB_CCR_DC_Pos)
508#define SCB_CCR_STKOFHFNMIGN_Pos 10U
509#define SCB_CCR_STKOFHFNMIGN_Msk (1UL << SCB_CCR_STKOFHFNMIGN_Pos)
511#define SCB_CCR_BFHFNMIGN_Pos 8U
512#define SCB_CCR_BFHFNMIGN_Msk (1UL << SCB_CCR_BFHFNMIGN_Pos)
514#define SCB_CCR_DIV_0_TRP_Pos 4U
515#define SCB_CCR_DIV_0_TRP_Msk (1UL << SCB_CCR_DIV_0_TRP_Pos)
517#define SCB_CCR_UNALIGN_TRP_Pos 3U
518#define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos)
520#define SCB_CCR_USERSETMPEND_Pos 1U
521#define SCB_CCR_USERSETMPEND_Msk (1UL << SCB_CCR_USERSETMPEND_Pos)
524#define SCB_SHCSR_HARDFAULTPENDED_Pos 21U
525#define SCB_SHCSR_HARDFAULTPENDED_Msk (1UL << SCB_SHCSR_HARDFAULTPENDED_Pos)
527#define SCB_SHCSR_SVCALLPENDED_Pos 15U
528#define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos)
530#define SCB_SHCSR_SYSTICKACT_Pos 11U
531#define SCB_SHCSR_SYSTICKACT_Msk (1UL << SCB_SHCSR_SYSTICKACT_Pos)
533#define SCB_SHCSR_PENDSVACT_Pos 10U
534#define SCB_SHCSR_PENDSVACT_Msk (1UL << SCB_SHCSR_PENDSVACT_Pos)
536#define SCB_SHCSR_SVCALLACT_Pos 7U
537#define SCB_SHCSR_SVCALLACT_Msk (1UL << SCB_SHCSR_SVCALLACT_Pos)
539#define SCB_SHCSR_NMIACT_Pos 5U
540#define SCB_SHCSR_NMIACT_Msk (1UL << SCB_SHCSR_NMIACT_Pos)
542#define SCB_SHCSR_HARDFAULTACT_Pos 2U
543#define SCB_SHCSR_HARDFAULTACT_Msk (1UL << SCB_SHCSR_HARDFAULTACT_Pos)
567#define SysTick_CTRL_COUNTFLAG_Pos 16U
568#define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos)
570#define SysTick_CTRL_CLKSOURCE_Pos 2U
571#define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos)
573#define SysTick_CTRL_TICKINT_Pos 1U
574#define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos)
576#define SysTick_CTRL_ENABLE_Pos 0U
577#define SysTick_CTRL_ENABLE_Msk (1UL )
580#define SysTick_LOAD_RELOAD_Pos 0U
581#define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL )
584#define SysTick_VAL_CURRENT_Pos 0U
585#define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL )
588#define SysTick_CALIB_NOREF_Pos 31U
589#define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos)
591#define SysTick_CALIB_SKEW_Pos 30U
592#define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos)
594#define SysTick_CALIB_TENMS_Pos 0U
595#define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL )
613 uint32_t RESERVED0[6U];
616 uint32_t RESERVED1[1U];
618 uint32_t RESERVED2[1U];
620 uint32_t RESERVED3[1U];
622 uint32_t RESERVED4[1U];
624 uint32_t RESERVED5[1U];
626 uint32_t RESERVED6[1U];
628 uint32_t RESERVED7[1U];
630 uint32_t RESERVED8[1U];
632 uint32_t RESERVED9[1U];
634 uint32_t RESERVED10[1U];
636 uint32_t RESERVED11[1U];
638 uint32_t RESERVED12[1U];
640 uint32_t RESERVED13[1U];
642 uint32_t RESERVED14[1U];
644 uint32_t RESERVED15[1U];
646 uint32_t RESERVED16[1U];
648 uint32_t RESERVED17[1U];
650 uint32_t RESERVED18[1U];
652 uint32_t RESERVED19[1U];
654 uint32_t RESERVED20[1U];
656 uint32_t RESERVED21[1U];
658 uint32_t RESERVED22[1U];
660 uint32_t RESERVED23[1U];
662 uint32_t RESERVED24[1U];
664 uint32_t RESERVED25[1U];
666 uint32_t RESERVED26[1U];
668 uint32_t RESERVED27[1U];
670 uint32_t RESERVED28[1U];
672 uint32_t RESERVED29[1U];
674 uint32_t RESERVED30[1U];
676 uint32_t RESERVED31[1U];
681#define DWT_CTRL_NUMCOMP_Pos 28U
682#define DWT_CTRL_NUMCOMP_Msk (0xFUL << DWT_CTRL_NUMCOMP_Pos)
684#define DWT_CTRL_NOTRCPKT_Pos 27U
685#define DWT_CTRL_NOTRCPKT_Msk (0x1UL << DWT_CTRL_NOTRCPKT_Pos)
687#define DWT_CTRL_NOEXTTRIG_Pos 26U
688#define DWT_CTRL_NOEXTTRIG_Msk (0x1UL << DWT_CTRL_NOEXTTRIG_Pos)
690#define DWT_CTRL_NOCYCCNT_Pos 25U
691#define DWT_CTRL_NOCYCCNT_Msk (0x1UL << DWT_CTRL_NOCYCCNT_Pos)
693#define DWT_CTRL_NOPRFCNT_Pos 24U
694#define DWT_CTRL_NOPRFCNT_Msk (0x1UL << DWT_CTRL_NOPRFCNT_Pos)
697#define DWT_FUNCTION_ID_Pos 27U
698#define DWT_FUNCTION_ID_Msk (0x1FUL << DWT_FUNCTION_ID_Pos)
700#define DWT_FUNCTION_MATCHED_Pos 24U
701#define DWT_FUNCTION_MATCHED_Msk (0x1UL << DWT_FUNCTION_MATCHED_Pos)
703#define DWT_FUNCTION_DATAVSIZE_Pos 10U
704#define DWT_FUNCTION_DATAVSIZE_Msk (0x3UL << DWT_FUNCTION_DATAVSIZE_Pos)
706#define DWT_FUNCTION_ACTION_Pos 4U
707#define DWT_FUNCTION_ACTION_Msk (0x3UL << DWT_FUNCTION_ACTION_Pos)
709#define DWT_FUNCTION_MATCH_Pos 0U
710#define DWT_FUNCTION_MATCH_Msk (0xFUL )
729 uint32_t RESERVED0[2U];
731 uint32_t RESERVED1[55U];
733 uint32_t RESERVED2[131U];
737 uint32_t RESERVED3[809U];
740 uint32_t RESERVED4[4U];
746#define TPI_ACPR_SWOSCALER_Pos 0U
747#define TPI_ACPR_SWOSCALER_Msk (0xFFFFUL )
750#define TPI_SPPR_TXMODE_Pos 0U
751#define TPI_SPPR_TXMODE_Msk (0x3UL )
754#define TPI_FFSR_FtNonStop_Pos 3U
755#define TPI_FFSR_FtNonStop_Msk (0x1UL << TPI_FFSR_FtNonStop_Pos)
757#define TPI_FFSR_TCPresent_Pos 2U
758#define TPI_FFSR_TCPresent_Msk (0x1UL << TPI_FFSR_TCPresent_Pos)
760#define TPI_FFSR_FtStopped_Pos 1U
761#define TPI_FFSR_FtStopped_Msk (0x1UL << TPI_FFSR_FtStopped_Pos)
763#define TPI_FFSR_FlInProg_Pos 0U
764#define TPI_FFSR_FlInProg_Msk (0x1UL )
767#define TPI_FFCR_TrigIn_Pos 8U
768#define TPI_FFCR_TrigIn_Msk (0x1UL << TPI_FFCR_TrigIn_Pos)
770#define TPI_FFCR_FOnMan_Pos 6U
771#define TPI_FFCR_FOnMan_Msk (0x1UL << TPI_FFCR_FOnMan_Pos)
773#define TPI_FFCR_EnFCont_Pos 1U
774#define TPI_FFCR_EnFCont_Msk (0x1UL << TPI_FFCR_EnFCont_Pos)
777#define TPI_PSCR_PSCount_Pos 0U
778#define TPI_PSCR_PSCount_Msk (0x1FUL )
781#define TPI_LSR_nTT_Pos 1U
782#define TPI_LSR_nTT_Msk (0x1UL << TPI_LSR_nTT_Pos)
784#define TPI_LSR_SLK_Pos 1U
785#define TPI_LSR_SLK_Msk (0x1UL << TPI_LSR_SLK_Pos)
787#define TPI_LSR_SLI_Pos 0U
788#define TPI_LSR_SLI_Msk (0x1UL )
791#define TPI_DEVID_NRZVALID_Pos 11U
792#define TPI_DEVID_NRZVALID_Msk (0x1UL << TPI_DEVID_NRZVALID_Pos)
794#define TPI_DEVID_MANCVALID_Pos 10U
795#define TPI_DEVID_MANCVALID_Msk (0x1UL << TPI_DEVID_MANCVALID_Pos)
797#define TPI_DEVID_PTINVALID_Pos 9U
798#define TPI_DEVID_PTINVALID_Msk (0x1UL << TPI_DEVID_PTINVALID_Pos)
800#define TPI_DEVID_FIFOSZ_Pos 6U
801#define TPI_DEVID_FIFOSZ_Msk (0x7UL << TPI_DEVID_FIFOSZ_Pos)
804#define TPI_DEVTYPE_SubType_Pos 4U
805#define TPI_DEVTYPE_SubType_Msk (0xFUL )
807#define TPI_DEVTYPE_MajorType_Pos 0U
808#define TPI_DEVTYPE_MajorType_Msk (0xFUL << TPI_DEVTYPE_MajorType_Pos)
813#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U)
831 uint32_t RESERVED0[7U];
833 __IOM uint32_t MAIR[2];
835 __IOM uint32_t MAIR0;
836 __IOM uint32_t MAIR1;
841#define MPU_TYPE_RALIASES 1U
844#define MPU_TYPE_IREGION_Pos 16U
845#define MPU_TYPE_IREGION_Msk (0xFFUL << MPU_TYPE_IREGION_Pos)
847#define MPU_TYPE_DREGION_Pos 8U
848#define MPU_TYPE_DREGION_Msk (0xFFUL << MPU_TYPE_DREGION_Pos)
850#define MPU_TYPE_SEPARATE_Pos 0U
851#define MPU_TYPE_SEPARATE_Msk (1UL )
854#define MPU_CTRL_PRIVDEFENA_Pos 2U
855#define MPU_CTRL_PRIVDEFENA_Msk (1UL << MPU_CTRL_PRIVDEFENA_Pos)
857#define MPU_CTRL_HFNMIENA_Pos 1U
858#define MPU_CTRL_HFNMIENA_Msk (1UL << MPU_CTRL_HFNMIENA_Pos)
860#define MPU_CTRL_ENABLE_Pos 0U
861#define MPU_CTRL_ENABLE_Msk (1UL )
864#define MPU_RNR_REGION_Pos 0U
865#define MPU_RNR_REGION_Msk (0xFFUL )
868#define MPU_RBAR_BASE_Pos 5U
869#define MPU_RBAR_BASE_Msk (0x7FFFFFFUL << MPU_RBAR_BASE_Pos)
871#define MPU_RBAR_SH_Pos 3U
872#define MPU_RBAR_SH_Msk (0x3UL << MPU_RBAR_SH_Pos)
874#define MPU_RBAR_AP_Pos 1U
875#define MPU_RBAR_AP_Msk (0x3UL << MPU_RBAR_AP_Pos)
877#define MPU_RBAR_XN_Pos 0U
878#define MPU_RBAR_XN_Msk (01UL )
881#define MPU_RLAR_LIMIT_Pos 5U
882#define MPU_RLAR_LIMIT_Msk (0x7FFFFFFUL << MPU_RLAR_LIMIT_Pos)
884#define MPU_RLAR_AttrIndx_Pos 1U
885#define MPU_RLAR_AttrIndx_Msk (0x7UL << MPU_RLAR_AttrIndx_Pos)
887#define MPU_RLAR_EN_Pos 0U
888#define MPU_RLAR_EN_Msk (1UL )
891#define MPU_MAIR0_Attr3_Pos 24U
892#define MPU_MAIR0_Attr3_Msk (0xFFUL << MPU_MAIR0_Attr3_Pos)
894#define MPU_MAIR0_Attr2_Pos 16U
895#define MPU_MAIR0_Attr2_Msk (0xFFUL << MPU_MAIR0_Attr2_Pos)
897#define MPU_MAIR0_Attr1_Pos 8U
898#define MPU_MAIR0_Attr1_Msk (0xFFUL << MPU_MAIR0_Attr1_Pos)
900#define MPU_MAIR0_Attr0_Pos 0U
901#define MPU_MAIR0_Attr0_Msk (0xFFUL )
904#define MPU_MAIR1_Attr7_Pos 24U
905#define MPU_MAIR1_Attr7_Msk (0xFFUL << MPU_MAIR1_Attr7_Pos)
907#define MPU_MAIR1_Attr6_Pos 16U
908#define MPU_MAIR1_Attr6_Msk (0xFFUL << MPU_MAIR1_Attr6_Pos)
910#define MPU_MAIR1_Attr5_Pos 8U
911#define MPU_MAIR1_Attr5_Msk (0xFFUL << MPU_MAIR1_Attr5_Pos)
913#define MPU_MAIR1_Attr4_Pos 0U
914#define MPU_MAIR1_Attr4_Msk (0xFFUL )
920#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
935#if defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U)
943#define SAU_CTRL_ALLNS_Pos 1U
944#define SAU_CTRL_ALLNS_Msk (1UL << SAU_CTRL_ALLNS_Pos)
946#define SAU_CTRL_ENABLE_Pos 0U
947#define SAU_CTRL_ENABLE_Msk (1UL )
950#define SAU_TYPE_SREGION_Pos 0U
951#define SAU_TYPE_SREGION_Msk (0xFFUL )
953#if defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U)
955#define SAU_RNR_REGION_Pos 0U
956#define SAU_RNR_REGION_Msk (0xFFUL )
959#define SAU_RBAR_BADDR_Pos 5U
960#define SAU_RBAR_BADDR_Msk (0x7FFFFFFUL << SAU_RBAR_BADDR_Pos)
963#define SAU_RLAR_LADDR_Pos 5U
964#define SAU_RLAR_LADDR_Msk (0x7FFFFFFUL << SAU_RLAR_LADDR_Pos)
966#define SAU_RLAR_NSC_Pos 1U
967#define SAU_RLAR_NSC_Msk (1UL << SAU_RLAR_NSC_Pos)
969#define SAU_RLAR_ENABLE_Pos 0U
970#define SAU_RLAR_ENABLE_Msk (1UL )
994 uint32_t RESERVED4[1U];
1000#define CoreDebug_DHCSR_DBGKEY_Pos 16U
1001#define CoreDebug_DHCSR_DBGKEY_Msk (0xFFFFUL << CoreDebug_DHCSR_DBGKEY_Pos)
1003#define CoreDebug_DHCSR_S_RESTART_ST_Pos 26U
1004#define CoreDebug_DHCSR_S_RESTART_ST_Msk (1UL << CoreDebug_DHCSR_S_RESTART_ST_Pos)
1006#define CoreDebug_DHCSR_S_RESET_ST_Pos 25U
1007#define CoreDebug_DHCSR_S_RESET_ST_Msk (1UL << CoreDebug_DHCSR_S_RESET_ST_Pos)
1009#define CoreDebug_DHCSR_S_RETIRE_ST_Pos 24U
1010#define CoreDebug_DHCSR_S_RETIRE_ST_Msk (1UL << CoreDebug_DHCSR_S_RETIRE_ST_Pos)
1012#define CoreDebug_DHCSR_S_LOCKUP_Pos 19U
1013#define CoreDebug_DHCSR_S_LOCKUP_Msk (1UL << CoreDebug_DHCSR_S_LOCKUP_Pos)
1015#define CoreDebug_DHCSR_S_SLEEP_Pos 18U
1016#define CoreDebug_DHCSR_S_SLEEP_Msk (1UL << CoreDebug_DHCSR_S_SLEEP_Pos)
1018#define CoreDebug_DHCSR_S_HALT_Pos 17U
1019#define CoreDebug_DHCSR_S_HALT_Msk (1UL << CoreDebug_DHCSR_S_HALT_Pos)
1021#define CoreDebug_DHCSR_S_REGRDY_Pos 16U
1022#define CoreDebug_DHCSR_S_REGRDY_Msk (1UL << CoreDebug_DHCSR_S_REGRDY_Pos)
1024#define CoreDebug_DHCSR_C_MASKINTS_Pos 3U
1025#define CoreDebug_DHCSR_C_MASKINTS_Msk (1UL << CoreDebug_DHCSR_C_MASKINTS_Pos)
1027#define CoreDebug_DHCSR_C_STEP_Pos 2U
1028#define CoreDebug_DHCSR_C_STEP_Msk (1UL << CoreDebug_DHCSR_C_STEP_Pos)
1030#define CoreDebug_DHCSR_C_HALT_Pos 1U
1031#define CoreDebug_DHCSR_C_HALT_Msk (1UL << CoreDebug_DHCSR_C_HALT_Pos)
1033#define CoreDebug_DHCSR_C_DEBUGEN_Pos 0U
1034#define CoreDebug_DHCSR_C_DEBUGEN_Msk (1UL )
1037#define CoreDebug_DCRSR_REGWnR_Pos 16U
1038#define CoreDebug_DCRSR_REGWnR_Msk (1UL << CoreDebug_DCRSR_REGWnR_Pos)
1040#define CoreDebug_DCRSR_REGSEL_Pos 0U
1041#define CoreDebug_DCRSR_REGSEL_Msk (0x1FUL )
1044#define CoreDebug_DEMCR_DWTENA_Pos 24U
1045#define CoreDebug_DEMCR_DWTENA_Msk (1UL << CoreDebug_DEMCR_DWTENA_Pos)
1047#define CoreDebug_DEMCR_VC_HARDERR_Pos 10U
1048#define CoreDebug_DEMCR_VC_HARDERR_Msk (1UL << CoreDebug_DEMCR_VC_HARDERR_Pos)
1050#define CoreDebug_DEMCR_VC_CORERESET_Pos 0U
1051#define CoreDebug_DEMCR_VC_CORERESET_Msk (1UL )
1054#define CoreDebug_DAUTHCTRL_INTSPNIDEN_Pos 3U
1055#define CoreDebug_DAUTHCTRL_INTSPNIDEN_Msk (1UL << CoreDebug_DAUTHCTRL_INTSPNIDEN_Pos)
1057#define CoreDebug_DAUTHCTRL_SPNIDENSEL_Pos 2U
1058#define CoreDebug_DAUTHCTRL_SPNIDENSEL_Msk (1UL << CoreDebug_DAUTHCTRL_SPNIDENSEL_Pos)
1060#define CoreDebug_DAUTHCTRL_INTSPIDEN_Pos 1U
1061#define CoreDebug_DAUTHCTRL_INTSPIDEN_Msk (1UL << CoreDebug_DAUTHCTRL_INTSPIDEN_Pos)
1063#define CoreDebug_DAUTHCTRL_SPIDENSEL_Pos 0U
1064#define CoreDebug_DAUTHCTRL_SPIDENSEL_Msk (1UL )
1067#define CoreDebug_DSCSR_CDS_Pos 16U
1068#define CoreDebug_DSCSR_CDS_Msk (1UL << CoreDebug_DSCSR_CDS_Pos)
1070#define CoreDebug_DSCSR_SBRSEL_Pos 1U
1071#define CoreDebug_DSCSR_SBRSEL_Msk (1UL << CoreDebug_DSCSR_SBRSEL_Pos)
1073#define CoreDebug_DSCSR_SBRSELEN_Pos 0U
1074#define CoreDebug_DSCSR_SBRSELEN_Msk (1UL )
1092#define _VAL2FLD(field, value) (((uint32_t)(value) << field ## _Pos) & field ## _Msk)
1100#define _FLD2VAL(field, value) (((uint32_t)(value) & field ## _Msk) >> field ## _Pos)
1113 #define SCS_BASE (0xE000E000UL)
1114 #define DWT_BASE (0xE0001000UL)
1115 #define TPI_BASE (0xE0040000UL)
1116 #define CoreDebug_BASE (0xE000EDF0UL)
1117 #define SysTick_BASE (SCS_BASE + 0x0010UL)
1118 #define NVIC_BASE (SCS_BASE + 0x0100UL)
1119 #define SCB_BASE (SCS_BASE + 0x0D00UL)
1122 #define SCB ((SCB_Type *) SCB_BASE )
1123 #define SysTick ((SysTick_Type *) SysTick_BASE )
1124 #define NVIC ((NVIC_Type *) NVIC_BASE )
1125 #define DWT ((DWT_Type *) DWT_BASE )
1126 #define TPI ((TPI_Type *) TPI_BASE )
1127 #define CoreDebug ((CoreDebug_Type *) CoreDebug_BASE )
1129 #if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U)
1130 #define MPU_BASE (SCS_BASE + 0x0D90UL)
1131 #define MPU ((MPU_Type *) MPU_BASE )
1134 #if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
1135 #define SAU_BASE (SCS_BASE + 0x0DD0UL)
1136 #define SAU ((SAU_Type *) SAU_BASE )
1139#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
1140 #define SCS_BASE_NS (0xE002E000UL)
1141 #define CoreDebug_BASE_NS (0xE002EDF0UL)
1142 #define SysTick_BASE_NS (SCS_BASE_NS + 0x0010UL)
1143 #define NVIC_BASE_NS (SCS_BASE_NS + 0x0100UL)
1144 #define SCB_BASE_NS (SCS_BASE_NS + 0x0D00UL)
1146 #define SCB_NS ((SCB_Type *) SCB_BASE_NS )
1147 #define SysTick_NS ((SysTick_Type *) SysTick_BASE_NS )
1148 #define NVIC_NS ((NVIC_Type *) NVIC_BASE_NS )
1149 #define CoreDebug_NS ((CoreDebug_Type *) CoreDebug_BASE_NS)
1151 #if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U)
1152 #define MPU_BASE_NS (SCS_BASE_NS + 0x0D90UL)
1153 #define MPU_NS ((MPU_Type *) MPU_BASE_NS )
1182#ifdef CMSIS_NVIC_VIRTUAL
1183 #ifndef CMSIS_NVIC_VIRTUAL_HEADER_FILE
1184 #define CMSIS_NVIC_VIRTUAL_HEADER_FILE "cmsis_nvic_virtual.h"
1186 #include CMSIS_NVIC_VIRTUAL_HEADER_FILE
1188 #define NVIC_SetPriorityGrouping __NVIC_SetPriorityGrouping
1189 #define NVIC_GetPriorityGrouping __NVIC_GetPriorityGrouping
1190 #define NVIC_EnableIRQ __NVIC_EnableIRQ
1191 #define NVIC_GetEnableIRQ __NVIC_GetEnableIRQ
1192 #define NVIC_DisableIRQ __NVIC_DisableIRQ
1193 #define NVIC_GetPendingIRQ __NVIC_GetPendingIRQ
1194 #define NVIC_SetPendingIRQ __NVIC_SetPendingIRQ
1195 #define NVIC_ClearPendingIRQ __NVIC_ClearPendingIRQ
1196 #define NVIC_GetActive __NVIC_GetActive
1197 #define NVIC_SetPriority __NVIC_SetPriority
1198 #define NVIC_GetPriority __NVIC_GetPriority
1199 #define NVIC_SystemReset __NVIC_SystemReset
1202#ifdef CMSIS_VECTAB_VIRTUAL
1203 #ifndef CMSIS_VECTAB_VIRTUAL_HEADER_FILE
1204 #define CMSIS_VECTAB_VIRTUAL_HEADER_FILE "cmsis_vectab_virtual.h"
1206 #include CMSIS_VECTAB_VIRTUAL_HEADER_FILE
1208 #define NVIC_SetVector __NVIC_SetVector
1209 #define NVIC_GetVector __NVIC_GetVector
1212#define NVIC_USER_IRQ_OFFSET 16
1218#define FNC_RETURN (0xFEFFFFFFUL)
1221#define EXC_RETURN_PREFIX (0xFF000000UL)
1222#define EXC_RETURN_S (0x00000040UL)
1223#define EXC_RETURN_DCRS (0x00000020UL)
1224#define EXC_RETURN_FTYPE (0x00000010UL)
1225#define EXC_RETURN_MODE (0x00000008UL)
1226#define EXC_RETURN_SPSEL (0x00000002UL)
1227#define EXC_RETURN_ES (0x00000001UL)
1230#if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)
1231#define EXC_INTEGRITY_SIGNATURE (0xFEFA125AUL)
1233#define EXC_INTEGRITY_SIGNATURE (0xFEFA125BUL)
1239#define _BIT_SHIFT(IRQn) ( ((((uint32_t)(int32_t)(IRQn)) ) & 0x03UL) * 8UL)
1240#define _SHP_IDX(IRQn) ( (((((uint32_t)(int32_t)(IRQn)) & 0x0FUL)-8UL) >> 2UL) )
1241#define _IP_IDX(IRQn) ( (((uint32_t)(int32_t)(IRQn)) >> 2UL) )
1243#define __NVIC_SetPriorityGrouping(X) (void)(X)
1244#define __NVIC_GetPriorityGrouping() (0U)
1254 if ((int32_t)(IRQn) >= 0)
1256 NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
1271 if ((int32_t)(IRQn) >= 0)
1273 return((uint32_t)(((
NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
1290 if ((int32_t)(IRQn) >= 0)
1292 NVIC->ICER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
1309 if ((int32_t)(IRQn) >= 0)
1311 return((uint32_t)(((
NVIC->ISPR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
1328 if ((int32_t)(IRQn) >= 0)
1330 NVIC->ISPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
1343 if ((int32_t)(IRQn) >= 0)
1345 NVIC->ICPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
1360 if ((int32_t)(IRQn) >= 0)
1362 return((uint32_t)(((
NVIC->IABR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
1371#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
1382 if ((int32_t)(IRQn) >= 0)
1384 return((uint32_t)(((
NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
1403 if ((int32_t)(IRQn) >= 0)
1405 NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] |= ((uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)));
1406 return((uint32_t)(((
NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
1425 if ((int32_t)(IRQn) >= 0)
1427 NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] &= ~((uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)));
1428 return((uint32_t)(((
NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
1449 if ((int32_t)(IRQn) >= 0)
1474 if ((int32_t)(IRQn) >= 0)
1498 uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL);
1499 uint32_t PreemptPriorityBits;
1500 uint32_t SubPriorityBits;
1503 SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(
__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(
__NVIC_PRIO_BITS));
1506 ((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits) |
1507 ((SubPriority & (uint32_t)((1UL << (SubPriorityBits )) - 1UL)))
1525 uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL);
1526 uint32_t PreemptPriorityBits;
1527 uint32_t SubPriorityBits;
1530 SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(
__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(
__NVIC_PRIO_BITS));
1532 *pPreemptPriority = (Priority >> SubPriorityBits) & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL);
1533 *pSubPriority = (Priority ) & (uint32_t)((1UL << (SubPriorityBits )) - 1UL);
1549#if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1U)
1550 uint32_t *vectors = (uint32_t *)
SCB->VTOR;
1552 uint32_t *vectors = (uint32_t *)0x0U;
1568#if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1U)
1569 uint32_t *vectors = (uint32_t *)
SCB->VTOR;
1571 uint32_t *vectors = (uint32_t *)0x0U;
1595#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
1604 if ((int32_t)(IRQn) >= 0)
1606 NVIC_NS->ISER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
1621 if ((int32_t)(IRQn) >= 0)
1623 return((uint32_t)(((NVIC_NS->ISER[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
1640 if ((int32_t)(IRQn) >= 0)
1642 NVIC_NS->ICER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
1657 if ((int32_t)(IRQn) >= 0)
1659 return((uint32_t)(((NVIC_NS->ISPR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
1676 if ((int32_t)(IRQn) >= 0)
1678 NVIC_NS->ISPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
1691 if ((int32_t)(IRQn) >= 0)
1693 NVIC_NS->ICPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
1708 if ((int32_t)(IRQn) >= 0)
1710 return((uint32_t)(((NVIC_NS->IABR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
1730 if ((int32_t)(IRQn) >= 0)
1754 if ((int32_t)(IRQn) >= 0)
1769#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U)
1809#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
1817 SAU->CTRL |= (SAU_CTRL_ENABLE_Msk);
1828 SAU->CTRL &= ~(SAU_CTRL_ENABLE_Msk);
1846#if defined (__Vendor_SysTickConfig) && (__Vendor_SysTickConfig == 0U)
1866 SysTick->LOAD = (uint32_t)(ticks - 1UL);
1875#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
1895 SysTick_NS->LOAD = (uint32_t)(ticks - 1UL);
1897 SysTick_NS->VAL = 0UL;
#define __NO_RETURN
Definition: cmsis_armcc.h:65
#define __STATIC_INLINE
Definition: cmsis_armcc.h:59
CMSIS compiler generic header file.
CMSIS Core(M) Version definitions.
#define __OM
Definition: core_armv8mbl.h:200
#define __IM
Definition: core_armv8mbl.h:199
#define __IOM
Definition: core_armv8mbl.h:201
#define __DSB()
Data Synchronization Barrier.
Definition: cmsis_armcc.h:429
#define __ISB()
Instruction Synchronization Barrier.
Definition: cmsis_armcc.h:418
#define __NOP
No Operation.
Definition: cmsis_armcc.h:387
__NO_RETURN __STATIC_INLINE void __NVIC_SystemReset(void)
System Reset.
Definition: core_armv8mbl.h:1581
__STATIC_INLINE void __NVIC_SetVector(IRQn_Type IRQn, uint32_t vector)
Set Interrupt Vector.
Definition: core_armv8mbl.h:1547
__STATIC_INLINE void NVIC_DecodePriority(uint32_t Priority, uint32_t PriorityGroup, uint32_t *const pPreemptPriority, uint32_t *const pSubPriority)
Decode Priority.
Definition: core_armv8mbl.h:1523
#define _IP_IDX(IRQn)
Definition: core_armv8mbl.h:1241
__STATIC_INLINE uint32_t __NVIC_GetVector(IRQn_Type IRQn)
Get Interrupt Vector.
Definition: core_armv8mbl.h:1566
__STATIC_INLINE void __NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority)
Set Interrupt Priority.
Definition: core_armv8mbl.h:1447
#define _BIT_SHIFT(IRQn)
Definition: core_armv8mbl.h:1239
__STATIC_INLINE void __NVIC_ClearPendingIRQ(IRQn_Type IRQn)
Clear Pending Interrupt.
Definition: core_armv8mbl.h:1341
__STATIC_INLINE uint32_t __NVIC_GetPendingIRQ(IRQn_Type IRQn)
Get Pending Interrupt.
Definition: core_armv8mbl.h:1307
__STATIC_INLINE uint32_t SCB_GetFPUType(void)
get FPU type
Definition: core_armv8mbl.h:1791
__STATIC_INLINE void __NVIC_EnableIRQ(IRQn_Type IRQn)
Enable Interrupt.
Definition: core_armv8mbl.h:1252
#define NVIC_USER_IRQ_OFFSET
Definition: core_armv8mbl.h:1212
__STATIC_INLINE uint32_t __NVIC_GetActive(IRQn_Type IRQn)
Get Active Interrupt.
Definition: core_armv8mbl.h:1358
__STATIC_INLINE void __NVIC_SetPendingIRQ(IRQn_Type IRQn)
Set Pending Interrupt.
Definition: core_armv8mbl.h:1326
__STATIC_INLINE uint32_t __NVIC_GetEnableIRQ(IRQn_Type IRQn)
Get Interrupt Enable status.
Definition: core_armv8mbl.h:1269
__STATIC_INLINE uint32_t NVIC_EncodePriority(uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority)
Encode Priority.
Definition: core_armv8mbl.h:1496
__STATIC_INLINE void __NVIC_DisableIRQ(IRQn_Type IRQn)
Disable Interrupt.
Definition: core_armv8mbl.h:1288
#define NVIC_SetPriority
Definition: core_armv8mbl.h:1197
__STATIC_INLINE uint32_t __NVIC_GetPriority(IRQn_Type IRQn)
Get Interrupt Priority.
Definition: core_armv8mbl.h:1471
#define _SHP_IDX(IRQn)
Definition: core_armv8mbl.h:1240
__IM uint32_t TYPE
Definition: core_armv8mbl.h:741
__IM uint32_t SSPSR
Definition: core_armv8mbl.h:727
__IOM uint32_t COMP5
Definition: core_armv8mbl.h:635
__IOM uint32_t ICSR
Definition: core_armv8mbl.h:384
uint32_t RESERVED0
Definition: core_armv8mbl.h:388
__IOM uint32_t COMP6
Definition: core_armv8mbl.h:639
__IOM uint32_t SPPR
Definition: core_armv8mbl.h:732
uint32_t w
Definition: core_armv8mbl.h:294
__IOM uint32_t DAUTHCTRL
Definition: core_armv8mbl.h:995
uint32_t Z
Definition: core_armv8mbl.h:291
__IOM uint32_t FUNCTION11
Definition: core_armv8mbl.h:661
__IM uint32_t CPUID
Definition: core_armv8mbl.h:383
__IOM uint32_t CCR
Definition: core_armv8mbl.h:392
uint32_t N
Definition: core_armv8mbl.h:292
__IOM uint32_t FUNCTION5
Definition: core_armv8mbl.h:637
__IOM uint32_t FUNCTION4
Definition: core_armv8mbl.h:633
uint32_t nPRIV
Definition: core_armv8mbl.h:324
__IOM uint32_t FUNCTION9
Definition: core_armv8mbl.h:653
__IOM uint32_t COMP1
Definition: core_armv8mbl.h:619
__IOM uint32_t SCR
Definition: core_armv8mbl.h:391
uint32_t Z
Definition: core_armv8mbl.h:240
uint32_t ISR
Definition: core_armv8mbl.h:285
__IOM uint32_t FFCR
Definition: core_armv8mbl.h:735
uint32_t C
Definition: core_armv8mbl.h:290
__IOM uint32_t COMP7
Definition: core_armv8mbl.h:643
__IOM uint32_t LOAD
Definition: core_armv8mbl.h:561
uint32_t w
Definition: core_armv8mbl.h:270
__IOM uint32_t FUNCTION12
Definition: core_armv8mbl.h:665
__IOM uint32_t FUNCTION3
Definition: core_armv8mbl.h:629
__IOM uint32_t FUNCTION0
Definition: core_armv8mbl.h:617
__IOM uint32_t COMP2
Definition: core_armv8mbl.h:623
__IOM uint32_t COMP0
Definition: core_armv8mbl.h:615
__IM uint32_t PCSR
Definition: core_armv8mbl.h:614
__IOM uint32_t FUNCTION10
Definition: core_armv8mbl.h:657
uint32_t w
Definition: core_armv8mbl.h:328
__IM uint32_t FFSR
Definition: core_armv8mbl.h:734
__IOM uint32_t FUNCTION15
Definition: core_armv8mbl.h:677
uint32_t _reserved1
Definition: core_armv8mbl.h:288
__IOM uint32_t SHCSR
Definition: core_armv8mbl.h:395
uint32_t N
Definition: core_armv8mbl.h:241
uint32_t T
Definition: core_armv8mbl.h:287
uint32_t V
Definition: core_armv8mbl.h:238
__IOM uint32_t FUNCTION14
Definition: core_armv8mbl.h:673
__IOM uint32_t COMP14
Definition: core_armv8mbl.h:671
__IOM uint32_t COMP3
Definition: core_armv8mbl.h:627
__IOM uint32_t COMP4
Definition: core_armv8mbl.h:631
uint32_t C
Definition: core_armv8mbl.h:239
__IOM uint32_t CTRL
Definition: core_armv8mbl.h:560
__IOM uint32_t CSPSR
Definition: core_armv8mbl.h:728
uint32_t SPSEL
Definition: core_armv8mbl.h:325
__IOM uint32_t FUNCTION1
Definition: core_armv8mbl.h:621
__IOM uint32_t COMP12
Definition: core_armv8mbl.h:663
__IOM uint32_t VAL
Definition: core_armv8mbl.h:562
__IOM uint32_t ACPR
Definition: core_armv8mbl.h:730
__IOM uint32_t COMP11
Definition: core_armv8mbl.h:659
__IOM uint32_t COMP15
Definition: core_armv8mbl.h:675
uint32_t _reserved1
Definition: core_armv8mbl.h:326
__IOM uint32_t FUNCTION6
Definition: core_armv8mbl.h:641
__IOM uint32_t DCRDR
Definition: core_armv8mbl.h:992
__IOM uint32_t FUNCTION2
Definition: core_armv8mbl.h:625
uint32_t ISR
Definition: core_armv8mbl.h:267
__IOM uint32_t FUNCTION7
Definition: core_armv8mbl.h:645
__IOM uint32_t COMP13
Definition: core_armv8mbl.h:667
__IOM uint32_t COMP9
Definition: core_armv8mbl.h:651
__IOM uint32_t FUNCTION8
Definition: core_armv8mbl.h:649
__IOM uint32_t COMP10
Definition: core_armv8mbl.h:655
__IOM uint32_t PSCR
Definition: core_armv8mbl.h:736
uint32_t _reserved0
Definition: core_armv8mbl.h:268
__IOM uint32_t AIRCR
Definition: core_armv8mbl.h:390
__IOM uint32_t DHCSR
Definition: core_armv8mbl.h:990
__IM uint32_t DEVTYPE
Definition: core_armv8mbl.h:742
__IOM uint32_t DSCSR
Definition: core_armv8mbl.h:996
__IOM uint32_t CTRL
Definition: core_armv8mbl.h:612
uint32_t RESERVED1
Definition: core_armv8mbl.h:393
__OM uint32_t LAR
Definition: core_armv8mbl.h:738
uint32_t w
Definition: core_armv8mbl.h:243
__IOM uint32_t DEMCR
Definition: core_armv8mbl.h:993
__IOM uint32_t COMP8
Definition: core_armv8mbl.h:647
uint32_t V
Definition: core_armv8mbl.h:289
uint32_t _reserved0
Definition: core_armv8mbl.h:286
__IM uint32_t LSR
Definition: core_armv8mbl.h:739
__OM uint32_t DCRSR
Definition: core_armv8mbl.h:991
__IOM uint32_t FUNCTION13
Definition: core_armv8mbl.h:669
uint32_t _reserved0
Definition: core_armv8mbl.h:237
__IM uint32_t CALIB
Definition: core_armv8mbl.h:563
#define SCB_AIRCR_VECTKEY_Pos
Definition: core_armv8mbl.h:461
#define SCB_AIRCR_SYSRESETREQ_Msk
Definition: core_armv8mbl.h:480
#define SysTick_CTRL_ENABLE_Msk
Definition: core_armv8mbl.h:577
#define SysTick_LOAD_RELOAD_Msk
Definition: core_armv8mbl.h:581
#define SysTick_CTRL_TICKINT_Msk
Definition: core_armv8mbl.h:574
#define SysTick_CTRL_CLKSOURCE_Msk
Definition: core_armv8mbl.h:571
#define SCB
Definition: core_armv8mbl.h:1122
#define NVIC
Definition: core_armv8mbl.h:1124
#define SysTick
Definition: core_armv8mbl.h:1123
#define __NVIC_PRIO_BITS
Definition: stm32f303xe.h:49
IRQn_Type
STM32F303xE devices Interrupt Number Definition, according to the selected device in Library_configur...
Definition: stm32f303xe.h:66
@ SysTick_IRQn
Definition: stm32f303xe.h:76
Structure type to access the Core Debug Register (CoreDebug).
Definition: core_armv8mbl.h:989
Structure type to access the Data Watchpoint and Trace Register (DWT).
Definition: core_armv8mbl.h:611
Structure type to access the Nested Vectored Interrupt Controller (NVIC).
Definition: core_armv8mbl.h:352
Structure type to access the System Control Block (SCB).
Definition: core_armv8mbl.h:382
Structure type to access the System Timer (SysTick).
Definition: core_armv8mbl.h:559
Structure type to access the Trace Port Interface Register (TPI).
Definition: core_armv8mbl.h:726
Union type to access the Application Program Status Register (APSR).
Definition: core_armv8mbl.h:234
Union type to access the Control Registers (CONTROL).
Definition: core_armv8mbl.h:321
Union type to access the Interrupt Program Status Register (IPSR).
Definition: core_armv8mbl.h:264
Union type to access the Special-Purpose Program Status Registers (xPSR).
Definition: core_armv8mbl.h:282