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Type definitions for the Trace Port Interface (TPI) More...
Modules | |
Core Debug Registers (CoreDebug) | |
Type definitions for the Core Debug Registers. | |
Floating Point Unit (FPU) | |
Type definitions for the Floating Point Unit (FPU) | |
Type definitions for the Trace Port Interface (TPI)
#define TPI_ACPR_PRESCALER_Msk (0x1FFFUL /*<< TPI_ACPR_PRESCALER_Pos*/) |
TPI ACPR: PRESCALER Mask
#define TPI_ACPR_PRESCALER_Msk (0x1FFFUL /*<< TPI_ACPR_PRESCALER_Pos*/) |
TPI ACPR: PRESCALER Mask
#define TPI_ACPR_PRESCALER_Msk (0x1FFFUL /*<< TPI_ACPR_PRESCALER_Pos*/) |
TPI ACPR: PRESCALER Mask
#define TPI_ACPR_PRESCALER_Msk (0x1FFFUL /*<< TPI_ACPR_PRESCALER_Pos*/) |
TPI ACPR: PRESCALER Mask
#define TPI_ACPR_PRESCALER_Msk (0x1FFFUL /*<< TPI_ACPR_PRESCALER_Pos*/) |
TPI ACPR: PRESCALER Mask
#define TPI_ACPR_PRESCALER_Msk (0x1FFFUL /*<< TPI_ACPR_PRESCALER_Pos*/) |
TPI ACPR: PRESCALER Mask
#define TPI_ACPR_PRESCALER_Pos 0U |
TPI ACPR: PRESCALER Position
#define TPI_ACPR_PRESCALER_Pos 0U |
TPI ACPR: PRESCALER Position
#define TPI_ACPR_PRESCALER_Pos 0U |
TPI ACPR: PRESCALER Position
#define TPI_ACPR_PRESCALER_Pos 0U |
TPI ACPR: PRESCALER Position
#define TPI_ACPR_PRESCALER_Pos 0U |
TPI ACPR: PRESCALER Position
#define TPI_ACPR_PRESCALER_Pos 0U |
TPI ACPR: PRESCALER Position
#define TPI_ACPR_SWOSCALER_Msk (0xFFFFUL /*<< TPI_ACPR_SWOSCALER_Pos*/) |
TPI ACPR: SWOSCALER Mask
#define TPI_ACPR_SWOSCALER_Msk (0xFFFFUL /*<< TPI_ACPR_SWOSCALER_Pos*/) |
TPI ACPR: SWOSCALER Mask
#define TPI_ACPR_SWOSCALER_Pos 0U |
TPI ACPR: SWOSCALER Position
#define TPI_ACPR_SWOSCALER_Pos 0U |
TPI ACPR: SWOSCALER Position
#define TPI_DEVID_AsynClkIn_Msk (0x1UL << TPI_DEVID_AsynClkIn_Pos) |
TPI DEVID: AsynClkIn Mask
#define TPI_DEVID_AsynClkIn_Msk (0x1UL << TPI_DEVID_AsynClkIn_Pos) |
TPI DEVID: AsynClkIn Mask
#define TPI_DEVID_AsynClkIn_Msk (0x1UL << TPI_DEVID_AsynClkIn_Pos) |
TPI DEVID: AsynClkIn Mask
#define TPI_DEVID_AsynClkIn_Msk (0x1UL << TPI_DEVID_AsynClkIn_Pos) |
TPI DEVID: AsynClkIn Mask
#define TPI_DEVID_AsynClkIn_Pos 5U |
TPI DEVID: AsynClkIn Position
#define TPI_DEVID_AsynClkIn_Pos 5U |
TPI DEVID: AsynClkIn Position
#define TPI_DEVID_AsynClkIn_Pos 5U |
TPI DEVID: AsynClkIn Position
#define TPI_DEVID_AsynClkIn_Pos 5U |
TPI DEVID: AsynClkIn Position
#define TPI_DEVID_FIFOSZ_Msk (0x7UL << TPI_DEVID_FIFOSZ_Pos) |
TPI DEVID: FIFO depth Mask
#define TPI_DEVID_FIFOSZ_Msk (0x7UL << TPI_DEVID_FIFOSZ_Pos) |
TPI DEVID: FIFO depth Mask
#define TPI_DEVID_FIFOSZ_Msk (0x7UL << TPI_DEVID_FIFOSZ_Pos) |
TPI DEVID: FIFOSZ Mask
#define TPI_DEVID_FIFOSZ_Msk (0x7UL << TPI_DEVID_FIFOSZ_Pos) |
TPI DEVID: FIFOSZ Mask
#define TPI_DEVID_FIFOSZ_Pos 6U |
TPI DEVID: FIFO depth Position
#define TPI_DEVID_FIFOSZ_Pos 6U |
TPI DEVID: FIFO depth Position
#define TPI_DEVID_FIFOSZ_Pos 6U |
TPI DEVID: FIFOSZ Position
#define TPI_DEVID_FIFOSZ_Pos 6U |
TPI DEVID: FIFOSZ Position
#define TPI_DEVID_MANCVALID_Msk (0x1UL << TPI_DEVID_MANCVALID_Pos) |
TPI DEVID: MANCVALID Mask
#define TPI_DEVID_MANCVALID_Msk (0x1UL << TPI_DEVID_MANCVALID_Pos) |
TPI DEVID: MANCVALID Mask
#define TPI_DEVID_MANCVALID_Msk (0x1UL << TPI_DEVID_MANCVALID_Pos) |
TPI DEVID: MANCVALID Mask
#define TPI_DEVID_MANCVALID_Msk (0x1UL << TPI_DEVID_MANCVALID_Pos) |
TPI DEVID: MANCVALID Mask
#define TPI_DEVID_MANCVALID_Msk (0x1UL << TPI_DEVID_MANCVALID_Pos) |
TPI DEVID: MANCVALID Mask
#define TPI_DEVID_MANCVALID_Msk (0x1UL << TPI_DEVID_MANCVALID_Pos) |
TPI DEVID: MANCVALID Mask
#define TPI_DEVID_MANCVALID_Msk (0x1UL << TPI_DEVID_MANCVALID_Pos) |
TPI DEVID: MANCVALID Mask
#define TPI_DEVID_MANCVALID_Msk (0x1UL << TPI_DEVID_MANCVALID_Pos) |
TPI DEVID: MANCVALID Mask
#define TPI_DEVID_MANCVALID_Pos 10U |
TPI DEVID: MANCVALID Position
#define TPI_DEVID_MANCVALID_Pos 10U |
TPI DEVID: MANCVALID Position
#define TPI_DEVID_MANCVALID_Pos 10U |
TPI DEVID: MANCVALID Position
#define TPI_DEVID_MANCVALID_Pos 10U |
TPI DEVID: MANCVALID Position
#define TPI_DEVID_MANCVALID_Pos 10U |
TPI DEVID: MANCVALID Position
#define TPI_DEVID_MANCVALID_Pos 10U |
TPI DEVID: MANCVALID Position
#define TPI_DEVID_MANCVALID_Pos 10U |
TPI DEVID: MANCVALID Position
#define TPI_DEVID_MANCVALID_Pos 10U |
TPI DEVID: MANCVALID Position
#define TPI_DEVID_MinBufSz_Msk (0x7UL << TPI_DEVID_MinBufSz_Pos) |
TPI DEVID: MinBufSz Mask
#define TPI_DEVID_MinBufSz_Msk (0x7UL << TPI_DEVID_MinBufSz_Pos) |
TPI DEVID: MinBufSz Mask
#define TPI_DEVID_MinBufSz_Msk (0x7UL << TPI_DEVID_MinBufSz_Pos) |
TPI DEVID: MinBufSz Mask
#define TPI_DEVID_MinBufSz_Msk (0x7UL << TPI_DEVID_MinBufSz_Pos) |
TPI DEVID: MinBufSz Mask
#define TPI_DEVID_MinBufSz_Pos 6U |
TPI DEVID: MinBufSz Position
#define TPI_DEVID_MinBufSz_Pos 6U |
TPI DEVID: MinBufSz Position
#define TPI_DEVID_MinBufSz_Pos 6U |
TPI DEVID: MinBufSz Position
#define TPI_DEVID_MinBufSz_Pos 6U |
TPI DEVID: MinBufSz Position
#define TPI_DEVID_NrTraceInput_Msk (0x3FUL /*<< TPI_DEVID_NrTraceInput_Pos*/) |
TPI DEVID: NrTraceInput Mask
#define TPI_DEVID_NrTraceInput_Msk (0x1FUL /*<< TPI_DEVID_NrTraceInput_Pos*/) |
TPI DEVID: NrTraceInput Mask
#define TPI_DEVID_NrTraceInput_Msk (0x3FUL /*<< TPI_DEVID_NrTraceInput_Pos*/) |
TPI DEVID: NrTraceInput Mask
#define TPI_DEVID_NrTraceInput_Msk (0x1FUL /*<< TPI_DEVID_NrTraceInput_Pos*/) |
TPI DEVID: NrTraceInput Mask
#define TPI_DEVID_NrTraceInput_Msk (0x1FUL /*<< TPI_DEVID_NrTraceInput_Pos*/) |
TPI DEVID: NrTraceInput Mask
#define TPI_DEVID_NrTraceInput_Msk (0x1FUL /*<< TPI_DEVID_NrTraceInput_Pos*/) |
TPI DEVID: NrTraceInput Mask
#define TPI_DEVID_NrTraceInput_Pos 0U |
TPI DEVID: NrTraceInput Position
#define TPI_DEVID_NrTraceInput_Pos 0U |
TPI DEVID: NrTraceInput Position
#define TPI_DEVID_NrTraceInput_Pos 0U |
TPI DEVID: NrTraceInput Position
#define TPI_DEVID_NrTraceInput_Pos 0U |
TPI DEVID: NrTraceInput Position
#define TPI_DEVID_NrTraceInput_Pos 0U |
TPI DEVID: NrTraceInput Position
#define TPI_DEVID_NrTraceInput_Pos 0U |
TPI DEVID: NrTraceInput Position
#define TPI_DEVID_NRZVALID_Msk (0x1UL << TPI_DEVID_NRZVALID_Pos) |
TPI DEVID: NRZVALID Mask
#define TPI_DEVID_NRZVALID_Msk (0x1UL << TPI_DEVID_NRZVALID_Pos) |
TPI DEVID: NRZVALID Mask
#define TPI_DEVID_NRZVALID_Msk (0x1UL << TPI_DEVID_NRZVALID_Pos) |
TPI DEVID: NRZVALID Mask
#define TPI_DEVID_NRZVALID_Msk (0x1UL << TPI_DEVID_NRZVALID_Pos) |
TPI DEVID: NRZVALID Mask
#define TPI_DEVID_NRZVALID_Msk (0x1UL << TPI_DEVID_NRZVALID_Pos) |
TPI DEVID: NRZVALID Mask
#define TPI_DEVID_NRZVALID_Msk (0x1UL << TPI_DEVID_NRZVALID_Pos) |
TPI DEVID: NRZVALID Mask
#define TPI_DEVID_NRZVALID_Msk (0x1UL << TPI_DEVID_NRZVALID_Pos) |
TPI DEVID: NRZVALID Mask
#define TPI_DEVID_NRZVALID_Msk (0x1UL << TPI_DEVID_NRZVALID_Pos) |
TPI DEVID: NRZVALID Mask
#define TPI_DEVID_NRZVALID_Pos 11U |
TPI DEVID: NRZVALID Position
#define TPI_DEVID_NRZVALID_Pos 11U |
TPI DEVID: NRZVALID Position
#define TPI_DEVID_NRZVALID_Pos 11U |
TPI DEVID: NRZVALID Position
#define TPI_DEVID_NRZVALID_Pos 11U |
TPI DEVID: NRZVALID Position
#define TPI_DEVID_NRZVALID_Pos 11U |
TPI DEVID: NRZVALID Position
#define TPI_DEVID_NRZVALID_Pos 11U |
TPI DEVID: NRZVALID Position
#define TPI_DEVID_NRZVALID_Pos 11U |
TPI DEVID: NRZVALID Position
#define TPI_DEVID_NRZVALID_Pos 11U |
TPI DEVID: NRZVALID Position
#define TPI_DEVID_PTINVALID_Msk (0x1UL << TPI_DEVID_PTINVALID_Pos) |
TPI DEVID: PTINVALID Mask
#define TPI_DEVID_PTINVALID_Msk (0x1UL << TPI_DEVID_PTINVALID_Pos) |
TPI DEVID: PTINVALID Mask
#define TPI_DEVID_PTINVALID_Msk (0x1UL << TPI_DEVID_PTINVALID_Pos) |
TPI DEVID: PTINVALID Mask
#define TPI_DEVID_PTINVALID_Msk (0x1UL << TPI_DEVID_PTINVALID_Pos) |
TPI DEVID: PTINVALID Mask
#define TPI_DEVID_PTINVALID_Msk (0x1UL << TPI_DEVID_PTINVALID_Pos) |
TPI DEVID: PTINVALID Mask
#define TPI_DEVID_PTINVALID_Msk (0x1UL << TPI_DEVID_PTINVALID_Pos) |
TPI DEVID: PTINVALID Mask
#define TPI_DEVID_PTINVALID_Msk (0x1UL << TPI_DEVID_PTINVALID_Pos) |
TPI DEVID: PTINVALID Mask
#define TPI_DEVID_PTINVALID_Msk (0x1UL << TPI_DEVID_PTINVALID_Pos) |
TPI DEVID: PTINVALID Mask
#define TPI_DEVID_PTINVALID_Pos 9U |
TPI DEVID: PTINVALID Position
#define TPI_DEVID_PTINVALID_Pos 9U |
TPI DEVID: PTINVALID Position
#define TPI_DEVID_PTINVALID_Pos 9U |
TPI DEVID: PTINVALID Position
#define TPI_DEVID_PTINVALID_Pos 9U |
TPI DEVID: PTINVALID Position
#define TPI_DEVID_PTINVALID_Pos 9U |
TPI DEVID: PTINVALID Position
#define TPI_DEVID_PTINVALID_Pos 9U |
TPI DEVID: PTINVALID Position
#define TPI_DEVID_PTINVALID_Pos 9U |
TPI DEVID: PTINVALID Position
#define TPI_DEVID_PTINVALID_Pos 9U |
TPI DEVID: PTINVALID Position
#define TPI_DEVTYPE_MajorType_Msk (0xFUL << TPI_DEVTYPE_MajorType_Pos) |
TPI DEVTYPE: MajorType Mask
#define TPI_DEVTYPE_MajorType_Msk (0xFUL << TPI_DEVTYPE_MajorType_Pos) |
TPI DEVTYPE: MajorType Mask
#define TPI_DEVTYPE_MajorType_Msk (0xFUL << TPI_DEVTYPE_MajorType_Pos) |
TPI DEVTYPE: MajorType Mask
#define TPI_DEVTYPE_MajorType_Msk (0xFUL << TPI_DEVTYPE_MajorType_Pos) |
TPI DEVTYPE: MajorType Mask
#define TPI_DEVTYPE_MajorType_Msk (0xFUL << TPI_DEVTYPE_MajorType_Pos) |
TPI DEVTYPE: MajorType Mask
#define TPI_DEVTYPE_MajorType_Msk (0xFUL << TPI_DEVTYPE_MajorType_Pos) |
TPI DEVTYPE: MajorType Mask
#define TPI_DEVTYPE_MajorType_Msk (0xFUL << TPI_DEVTYPE_MajorType_Pos) |
TPI DEVTYPE: MajorType Mask
#define TPI_DEVTYPE_MajorType_Msk (0xFUL << TPI_DEVTYPE_MajorType_Pos) |
TPI DEVTYPE: MajorType Mask
#define TPI_DEVTYPE_MajorType_Pos 0U |
TPI DEVTYPE: MajorType Position
#define TPI_DEVTYPE_MajorType_Pos 0U |
TPI DEVTYPE: MajorType Position
#define TPI_DEVTYPE_MajorType_Pos 0U |
TPI DEVTYPE: MajorType Position
#define TPI_DEVTYPE_MajorType_Pos 0U |
TPI DEVTYPE: MajorType Position
#define TPI_DEVTYPE_MajorType_Pos 0U |
TPI DEVTYPE: MajorType Position
#define TPI_DEVTYPE_MajorType_Pos 0U |
TPI DEVTYPE: MajorType Position
#define TPI_DEVTYPE_MajorType_Pos 0U |
TPI DEVTYPE: MajorType Position
#define TPI_DEVTYPE_MajorType_Pos 0U |
TPI DEVTYPE: MajorType Position
#define TPI_DEVTYPE_SubType_Msk (0xFUL /*<< TPI_DEVTYPE_SubType_Pos*/) |
TPI DEVTYPE: SubType Mask
#define TPI_DEVTYPE_SubType_Msk (0xFUL /*<< TPI_DEVTYPE_SubType_Pos*/) |
TPI DEVTYPE: SubType Mask
#define TPI_DEVTYPE_SubType_Msk (0xFUL /*<< TPI_DEVTYPE_SubType_Pos*/) |
TPI DEVTYPE: SubType Mask
#define TPI_DEVTYPE_SubType_Msk (0xFUL /*<< TPI_DEVTYPE_SubType_Pos*/) |
TPI DEVTYPE: SubType Mask
#define TPI_DEVTYPE_SubType_Msk (0xFUL /*<< TPI_DEVTYPE_SubType_Pos*/) |
TPI DEVTYPE: SubType Mask
#define TPI_DEVTYPE_SubType_Msk (0xFUL /*<< TPI_DEVTYPE_SubType_Pos*/) |
TPI DEVTYPE: SubType Mask
#define TPI_DEVTYPE_SubType_Msk (0xFUL /*<< TPI_DEVTYPE_SubType_Pos*/) |
TPI DEVTYPE: SubType Mask
#define TPI_DEVTYPE_SubType_Msk (0xFUL /*<< TPI_DEVTYPE_SubType_Pos*/) |
TPI DEVTYPE: SubType Mask
#define TPI_DEVTYPE_SubType_Pos 4U |
TPI DEVTYPE: SubType Position
#define TPI_DEVTYPE_SubType_Pos 4U |
TPI DEVTYPE: SubType Position
#define TPI_DEVTYPE_SubType_Pos 4U |
TPI DEVTYPE: SubType Position
#define TPI_DEVTYPE_SubType_Pos 4U |
TPI DEVTYPE: SubType Position
#define TPI_DEVTYPE_SubType_Pos 4U |
TPI DEVTYPE: SubType Position
#define TPI_DEVTYPE_SubType_Pos 4U |
TPI DEVTYPE: SubType Position
#define TPI_DEVTYPE_SubType_Pos 4U |
TPI DEVTYPE: SubType Position
#define TPI_DEVTYPE_SubType_Pos 4U |
TPI DEVTYPE: SubType Position
#define TPI_FFCR_EnFCont_Msk (0x1UL << TPI_FFCR_EnFCont_Pos) |
TPI FFCR: EnFCont Mask
#define TPI_FFCR_EnFCont_Msk (0x1UL << TPI_FFCR_EnFCont_Pos) |
TPI FFCR: EnFCont Mask
#define TPI_FFCR_EnFCont_Msk (0x1UL << TPI_FFCR_EnFCont_Pos) |
TPI FFCR: EnFCont Mask
#define TPI_FFCR_EnFCont_Msk (0x1UL << TPI_FFCR_EnFCont_Pos) |
TPI FFCR: EnFCont Mask
#define TPI_FFCR_EnFCont_Msk (0x1UL << TPI_FFCR_EnFCont_Pos) |
TPI FFCR: EnFCont Mask
#define TPI_FFCR_EnFCont_Msk (0x1UL << TPI_FFCR_EnFCont_Pos) |
TPI FFCR: EnFCont Mask
#define TPI_FFCR_EnFCont_Msk (0x1UL << TPI_FFCR_EnFCont_Pos) |
TPI FFCR: EnFCont Mask
#define TPI_FFCR_EnFCont_Msk (0x1UL << TPI_FFCR_EnFCont_Pos) |
TPI FFCR: EnFCont Mask
#define TPI_FFCR_EnFCont_Pos 1U |
TPI FFCR: EnFCont Position
#define TPI_FFCR_EnFCont_Pos 1U |
TPI FFCR: EnFCont Position
#define TPI_FFCR_EnFCont_Pos 1U |
TPI FFCR: EnFCont Position
#define TPI_FFCR_EnFCont_Pos 1U |
TPI FFCR: EnFCont Position
#define TPI_FFCR_EnFCont_Pos 1U |
TPI FFCR: EnFCont Position
#define TPI_FFCR_EnFCont_Pos 1U |
TPI FFCR: EnFCont Position
#define TPI_FFCR_EnFCont_Pos 1U |
TPI FFCR: EnFCont Position
#define TPI_FFCR_EnFCont_Pos 1U |
TPI FFCR: EnFCont Position
#define TPI_FFCR_FOnMan_Msk (0x1UL << TPI_FFCR_FOnMan_Pos) |
TPI FFCR: FOnMan Mask
#define TPI_FFCR_FOnMan_Msk (0x1UL << TPI_FFCR_FOnMan_Pos) |
TPI FFCR: FOnMan Mask
#define TPI_FFCR_FOnMan_Msk (0x1UL << TPI_FFCR_FOnMan_Pos) |
TPI FFCR: FOnMan Mask
#define TPI_FFCR_FOnMan_Msk (0x1UL << TPI_FFCR_FOnMan_Pos) |
TPI FFCR: FOnMan Mask
#define TPI_FFCR_FOnMan_Pos 6U |
TPI FFCR: FOnMan Position
#define TPI_FFCR_FOnMan_Pos 6U |
TPI FFCR: FOnMan Position
#define TPI_FFCR_FOnMan_Pos 6U |
TPI FFCR: FOnMan Position
#define TPI_FFCR_FOnMan_Pos 6U |
TPI FFCR: FOnMan Position
#define TPI_FFCR_TrigIn_Msk (0x1UL << TPI_FFCR_TrigIn_Pos) |
TPI FFCR: TrigIn Mask
#define TPI_FFCR_TrigIn_Msk (0x1UL << TPI_FFCR_TrigIn_Pos) |
TPI FFCR: TrigIn Mask
#define TPI_FFCR_TrigIn_Msk (0x1UL << TPI_FFCR_TrigIn_Pos) |
TPI FFCR: TrigIn Mask
#define TPI_FFCR_TrigIn_Msk (0x1UL << TPI_FFCR_TrigIn_Pos) |
TPI FFCR: TrigIn Mask
#define TPI_FFCR_TrigIn_Msk (0x1UL << TPI_FFCR_TrigIn_Pos) |
TPI FFCR: TrigIn Mask
#define TPI_FFCR_TrigIn_Msk (0x1UL << TPI_FFCR_TrigIn_Pos) |
TPI FFCR: TrigIn Mask
#define TPI_FFCR_TrigIn_Msk (0x1UL << TPI_FFCR_TrigIn_Pos) |
TPI FFCR: TrigIn Mask
#define TPI_FFCR_TrigIn_Msk (0x1UL << TPI_FFCR_TrigIn_Pos) |
TPI FFCR: TrigIn Mask
#define TPI_FFCR_TrigIn_Pos 8U |
TPI FFCR: TrigIn Position
#define TPI_FFCR_TrigIn_Pos 8U |
TPI FFCR: TrigIn Position
#define TPI_FFCR_TrigIn_Pos 8U |
TPI FFCR: TrigIn Position
#define TPI_FFCR_TrigIn_Pos 8U |
TPI FFCR: TrigIn Position
#define TPI_FFCR_TrigIn_Pos 8U |
TPI FFCR: TrigIn Position
#define TPI_FFCR_TrigIn_Pos 8U |
TPI FFCR: TrigIn Position
#define TPI_FFCR_TrigIn_Pos 8U |
TPI FFCR: TrigIn Position
#define TPI_FFCR_TrigIn_Pos 8U |
TPI FFCR: TrigIn Position
#define TPI_FFSR_FlInProg_Msk (0x1UL /*<< TPI_FFSR_FlInProg_Pos*/) |
TPI FFSR: FlInProg Mask
#define TPI_FFSR_FlInProg_Msk (0x1UL /*<< TPI_FFSR_FlInProg_Pos*/) |
TPI FFSR: FlInProg Mask
#define TPI_FFSR_FlInProg_Msk (0x1UL /*<< TPI_FFSR_FlInProg_Pos*/) |
TPI FFSR: FlInProg Mask
#define TPI_FFSR_FlInProg_Msk (0x1UL /*<< TPI_FFSR_FlInProg_Pos*/) |
TPI FFSR: FlInProg Mask
#define TPI_FFSR_FlInProg_Msk (0x1UL /*<< TPI_FFSR_FlInProg_Pos*/) |
TPI FFSR: FlInProg Mask
#define TPI_FFSR_FlInProg_Msk (0x1UL /*<< TPI_FFSR_FlInProg_Pos*/) |
TPI FFSR: FlInProg Mask
#define TPI_FFSR_FlInProg_Msk (0x1UL /*<< TPI_FFSR_FlInProg_Pos*/) |
TPI FFSR: FlInProg Mask
#define TPI_FFSR_FlInProg_Msk (0x1UL /*<< TPI_FFSR_FlInProg_Pos*/) |
TPI FFSR: FlInProg Mask
#define TPI_FFSR_FlInProg_Pos 0U |
TPI FFSR: FlInProg Position
#define TPI_FFSR_FlInProg_Pos 0U |
TPI FFSR: FlInProg Position
#define TPI_FFSR_FlInProg_Pos 0U |
TPI FFSR: FlInProg Position
#define TPI_FFSR_FlInProg_Pos 0U |
TPI FFSR: FlInProg Position
#define TPI_FFSR_FlInProg_Pos 0U |
TPI FFSR: FlInProg Position
#define TPI_FFSR_FlInProg_Pos 0U |
TPI FFSR: FlInProg Position
#define TPI_FFSR_FlInProg_Pos 0U |
TPI FFSR: FlInProg Position
#define TPI_FFSR_FlInProg_Pos 0U |
TPI FFSR: FlInProg Position
#define TPI_FFSR_FtNonStop_Msk (0x1UL << TPI_FFSR_FtNonStop_Pos) |
TPI FFSR: FtNonStop Mask
#define TPI_FFSR_FtNonStop_Msk (0x1UL << TPI_FFSR_FtNonStop_Pos) |
TPI FFSR: FtNonStop Mask
#define TPI_FFSR_FtNonStop_Msk (0x1UL << TPI_FFSR_FtNonStop_Pos) |
TPI FFSR: FtNonStop Mask
#define TPI_FFSR_FtNonStop_Msk (0x1UL << TPI_FFSR_FtNonStop_Pos) |
TPI FFSR: FtNonStop Mask
#define TPI_FFSR_FtNonStop_Msk (0x1UL << TPI_FFSR_FtNonStop_Pos) |
TPI FFSR: FtNonStop Mask
#define TPI_FFSR_FtNonStop_Msk (0x1UL << TPI_FFSR_FtNonStop_Pos) |
TPI FFSR: FtNonStop Mask
#define TPI_FFSR_FtNonStop_Msk (0x1UL << TPI_FFSR_FtNonStop_Pos) |
TPI FFSR: FtNonStop Mask
#define TPI_FFSR_FtNonStop_Msk (0x1UL << TPI_FFSR_FtNonStop_Pos) |
TPI FFSR: FtNonStop Mask
#define TPI_FFSR_FtNonStop_Pos 3U |
TPI FFSR: FtNonStop Position
#define TPI_FFSR_FtNonStop_Pos 3U |
TPI FFSR: FtNonStop Position
#define TPI_FFSR_FtNonStop_Pos 3U |
TPI FFSR: FtNonStop Position
#define TPI_FFSR_FtNonStop_Pos 3U |
TPI FFSR: FtNonStop Position
#define TPI_FFSR_FtNonStop_Pos 3U |
TPI FFSR: FtNonStop Position
#define TPI_FFSR_FtNonStop_Pos 3U |
TPI FFSR: FtNonStop Position
#define TPI_FFSR_FtNonStop_Pos 3U |
TPI FFSR: FtNonStop Position
#define TPI_FFSR_FtNonStop_Pos 3U |
TPI FFSR: FtNonStop Position
#define TPI_FFSR_FtStopped_Msk (0x1UL << TPI_FFSR_FtStopped_Pos) |
TPI FFSR: FtStopped Mask
#define TPI_FFSR_FtStopped_Msk (0x1UL << TPI_FFSR_FtStopped_Pos) |
TPI FFSR: FtStopped Mask
#define TPI_FFSR_FtStopped_Msk (0x1UL << TPI_FFSR_FtStopped_Pos) |
TPI FFSR: FtStopped Mask
#define TPI_FFSR_FtStopped_Msk (0x1UL << TPI_FFSR_FtStopped_Pos) |
TPI FFSR: FtStopped Mask
#define TPI_FFSR_FtStopped_Msk (0x1UL << TPI_FFSR_FtStopped_Pos) |
TPI FFSR: FtStopped Mask
#define TPI_FFSR_FtStopped_Msk (0x1UL << TPI_FFSR_FtStopped_Pos) |
TPI FFSR: FtStopped Mask
#define TPI_FFSR_FtStopped_Msk (0x1UL << TPI_FFSR_FtStopped_Pos) |
TPI FFSR: FtStopped Mask
#define TPI_FFSR_FtStopped_Msk (0x1UL << TPI_FFSR_FtStopped_Pos) |
TPI FFSR: FtStopped Mask
#define TPI_FFSR_FtStopped_Pos 1U |
TPI FFSR: FtStopped Position
#define TPI_FFSR_FtStopped_Pos 1U |
TPI FFSR: FtStopped Position
#define TPI_FFSR_FtStopped_Pos 1U |
TPI FFSR: FtStopped Position
#define TPI_FFSR_FtStopped_Pos 1U |
TPI FFSR: FtStopped Position
#define TPI_FFSR_FtStopped_Pos 1U |
TPI FFSR: FtStopped Position
#define TPI_FFSR_FtStopped_Pos 1U |
TPI FFSR: FtStopped Position
#define TPI_FFSR_FtStopped_Pos 1U |
TPI FFSR: FtStopped Position
#define TPI_FFSR_FtStopped_Pos 1U |
TPI FFSR: FtStopped Position
#define TPI_FFSR_TCPresent_Msk (0x1UL << TPI_FFSR_TCPresent_Pos) |
TPI FFSR: TCPresent Mask
#define TPI_FFSR_TCPresent_Msk (0x1UL << TPI_FFSR_TCPresent_Pos) |
TPI FFSR: TCPresent Mask
#define TPI_FFSR_TCPresent_Msk (0x1UL << TPI_FFSR_TCPresent_Pos) |
TPI FFSR: TCPresent Mask
#define TPI_FFSR_TCPresent_Msk (0x1UL << TPI_FFSR_TCPresent_Pos) |
TPI FFSR: TCPresent Mask
#define TPI_FFSR_TCPresent_Msk (0x1UL << TPI_FFSR_TCPresent_Pos) |
TPI FFSR: TCPresent Mask
#define TPI_FFSR_TCPresent_Msk (0x1UL << TPI_FFSR_TCPresent_Pos) |
TPI FFSR: TCPresent Mask
#define TPI_FFSR_TCPresent_Msk (0x1UL << TPI_FFSR_TCPresent_Pos) |
TPI FFSR: TCPresent Mask
#define TPI_FFSR_TCPresent_Msk (0x1UL << TPI_FFSR_TCPresent_Pos) |
TPI FFSR: TCPresent Mask
#define TPI_FFSR_TCPresent_Pos 2U |
TPI FFSR: TCPresent Position
#define TPI_FFSR_TCPresent_Pos 2U |
TPI FFSR: TCPresent Position
#define TPI_FFSR_TCPresent_Pos 2U |
TPI FFSR: TCPresent Position
#define TPI_FFSR_TCPresent_Pos 2U |
TPI FFSR: TCPresent Position
#define TPI_FFSR_TCPresent_Pos 2U |
TPI FFSR: TCPresent Position
#define TPI_FFSR_TCPresent_Pos 2U |
TPI FFSR: TCPresent Position
#define TPI_FFSR_TCPresent_Pos 2U |
TPI FFSR: TCPresent Position
#define TPI_FFSR_TCPresent_Pos 2U |
TPI FFSR: TCPresent Position
#define TPI_FIFO0_ETM0_Msk (0xFFUL /*<< TPI_FIFO0_ETM0_Pos*/) |
TPI FIFO0: ETM0 Mask
#define TPI_FIFO0_ETM0_Msk (0xFFUL /*<< TPI_FIFO0_ETM0_Pos*/) |
TPI FIFO0: ETM0 Mask
#define TPI_FIFO0_ETM0_Msk (0xFFUL /*<< TPI_FIFO0_ETM0_Pos*/) |
TPI FIFO0: ETM0 Mask
#define TPI_FIFO0_ETM0_Msk (0xFFUL /*<< TPI_FIFO0_ETM0_Pos*/) |
TPI FIFO0: ETM0 Mask
#define TPI_FIFO0_ETM0_Pos 0U |
TPI FIFO0: ETM0 Position
#define TPI_FIFO0_ETM0_Pos 0U |
TPI FIFO0: ETM0 Position
#define TPI_FIFO0_ETM0_Pos 0U |
TPI FIFO0: ETM0 Position
#define TPI_FIFO0_ETM0_Pos 0U |
TPI FIFO0: ETM0 Position
#define TPI_FIFO0_ETM1_Msk (0xFFUL << TPI_FIFO0_ETM1_Pos) |
TPI FIFO0: ETM1 Mask
#define TPI_FIFO0_ETM1_Msk (0xFFUL << TPI_FIFO0_ETM1_Pos) |
TPI FIFO0: ETM1 Mask
#define TPI_FIFO0_ETM1_Msk (0xFFUL << TPI_FIFO0_ETM1_Pos) |
TPI FIFO0: ETM1 Mask
#define TPI_FIFO0_ETM1_Msk (0xFFUL << TPI_FIFO0_ETM1_Pos) |
TPI FIFO0: ETM1 Mask
#define TPI_FIFO0_ETM1_Pos 8U |
TPI FIFO0: ETM1 Position
#define TPI_FIFO0_ETM1_Pos 8U |
TPI FIFO0: ETM1 Position
#define TPI_FIFO0_ETM1_Pos 8U |
TPI FIFO0: ETM1 Position
#define TPI_FIFO0_ETM1_Pos 8U |
TPI FIFO0: ETM1 Position
#define TPI_FIFO0_ETM2_Msk (0xFFUL << TPI_FIFO0_ETM2_Pos) |
TPI FIFO0: ETM2 Mask
#define TPI_FIFO0_ETM2_Msk (0xFFUL << TPI_FIFO0_ETM2_Pos) |
TPI FIFO0: ETM2 Mask
#define TPI_FIFO0_ETM2_Msk (0xFFUL << TPI_FIFO0_ETM2_Pos) |
TPI FIFO0: ETM2 Mask
#define TPI_FIFO0_ETM2_Msk (0xFFUL << TPI_FIFO0_ETM2_Pos) |
TPI FIFO0: ETM2 Mask
#define TPI_FIFO0_ETM2_Pos 16U |
TPI FIFO0: ETM2 Position
#define TPI_FIFO0_ETM2_Pos 16U |
TPI FIFO0: ETM2 Position
#define TPI_FIFO0_ETM2_Pos 16U |
TPI FIFO0: ETM2 Position
#define TPI_FIFO0_ETM2_Pos 16U |
TPI FIFO0: ETM2 Position
#define TPI_FIFO0_ETM_ATVALID_Msk (0x3UL << TPI_FIFO0_ETM_ATVALID_Pos) |
TPI FIFO0: ETM_ATVALID Mask
#define TPI_FIFO0_ETM_ATVALID_Msk (0x3UL << TPI_FIFO0_ETM_ATVALID_Pos) |
TPI FIFO0: ETM_ATVALID Mask
#define TPI_FIFO0_ETM_ATVALID_Msk (0x3UL << TPI_FIFO0_ETM_ATVALID_Pos) |
TPI FIFO0: ETM_ATVALID Mask
#define TPI_FIFO0_ETM_ATVALID_Msk (0x3UL << TPI_FIFO0_ETM_ATVALID_Pos) |
TPI FIFO0: ETM_ATVALID Mask
#define TPI_FIFO0_ETM_ATVALID_Pos 26U |
TPI FIFO0: ETM_ATVALID Position
#define TPI_FIFO0_ETM_ATVALID_Pos 26U |
TPI FIFO0: ETM_ATVALID Position
#define TPI_FIFO0_ETM_ATVALID_Pos 26U |
TPI FIFO0: ETM_ATVALID Position
#define TPI_FIFO0_ETM_ATVALID_Pos 26U |
TPI FIFO0: ETM_ATVALID Position
#define TPI_FIFO0_ETM_bytecount_Msk (0x3UL << TPI_FIFO0_ETM_bytecount_Pos) |
TPI FIFO0: ETM_bytecount Mask
#define TPI_FIFO0_ETM_bytecount_Msk (0x3UL << TPI_FIFO0_ETM_bytecount_Pos) |
TPI FIFO0: ETM_bytecount Mask
#define TPI_FIFO0_ETM_bytecount_Msk (0x3UL << TPI_FIFO0_ETM_bytecount_Pos) |
TPI FIFO0: ETM_bytecount Mask
#define TPI_FIFO0_ETM_bytecount_Msk (0x3UL << TPI_FIFO0_ETM_bytecount_Pos) |
TPI FIFO0: ETM_bytecount Mask
#define TPI_FIFO0_ETM_bytecount_Pos 24U |
TPI FIFO0: ETM_bytecount Position
#define TPI_FIFO0_ETM_bytecount_Pos 24U |
TPI FIFO0: ETM_bytecount Position
#define TPI_FIFO0_ETM_bytecount_Pos 24U |
TPI FIFO0: ETM_bytecount Position
#define TPI_FIFO0_ETM_bytecount_Pos 24U |
TPI FIFO0: ETM_bytecount Position
#define TPI_FIFO0_ITM_ATVALID_Msk (0x3UL << TPI_FIFO0_ITM_ATVALID_Pos) |
TPI FIFO0: ITM_ATVALID Mask
#define TPI_FIFO0_ITM_ATVALID_Msk (0x3UL << TPI_FIFO0_ITM_ATVALID_Pos) |
TPI FIFO0: ITM_ATVALID Mask
#define TPI_FIFO0_ITM_ATVALID_Msk (0x3UL << TPI_FIFO0_ITM_ATVALID_Pos) |
TPI FIFO0: ITM_ATVALID Mask
#define TPI_FIFO0_ITM_ATVALID_Msk (0x3UL << TPI_FIFO0_ITM_ATVALID_Pos) |
TPI FIFO0: ITM_ATVALID Mask
#define TPI_FIFO0_ITM_ATVALID_Pos 29U |
TPI FIFO0: ITM_ATVALID Position
#define TPI_FIFO0_ITM_ATVALID_Pos 29U |
TPI FIFO0: ITM_ATVALID Position
#define TPI_FIFO0_ITM_ATVALID_Pos 29U |
TPI FIFO0: ITM_ATVALID Position
#define TPI_FIFO0_ITM_ATVALID_Pos 29U |
TPI FIFO0: ITM_ATVALID Position
#define TPI_FIFO0_ITM_bytecount_Msk (0x3UL << TPI_FIFO0_ITM_bytecount_Pos) |
TPI FIFO0: ITM_bytecount Mask
#define TPI_FIFO0_ITM_bytecount_Msk (0x3UL << TPI_FIFO0_ITM_bytecount_Pos) |
TPI FIFO0: ITM_bytecount Mask
#define TPI_FIFO0_ITM_bytecount_Msk (0x3UL << TPI_FIFO0_ITM_bytecount_Pos) |
TPI FIFO0: ITM_bytecount Mask
#define TPI_FIFO0_ITM_bytecount_Msk (0x3UL << TPI_FIFO0_ITM_bytecount_Pos) |
TPI FIFO0: ITM_bytecount Mask
#define TPI_FIFO0_ITM_bytecount_Pos 27U |
TPI FIFO0: ITM_bytecount Position
#define TPI_FIFO0_ITM_bytecount_Pos 27U |
TPI FIFO0: ITM_bytecount Position
#define TPI_FIFO0_ITM_bytecount_Pos 27U |
TPI FIFO0: ITM_bytecount Position
#define TPI_FIFO0_ITM_bytecount_Pos 27U |
TPI FIFO0: ITM_bytecount Position
#define TPI_FIFO1_ETM_ATVALID_Msk (0x3UL << TPI_FIFO1_ETM_ATVALID_Pos) |
TPI FIFO1: ETM_ATVALID Mask
#define TPI_FIFO1_ETM_ATVALID_Msk (0x3UL << TPI_FIFO1_ETM_ATVALID_Pos) |
TPI FIFO1: ETM_ATVALID Mask
#define TPI_FIFO1_ETM_ATVALID_Msk (0x3UL << TPI_FIFO1_ETM_ATVALID_Pos) |
TPI FIFO1: ETM_ATVALID Mask
#define TPI_FIFO1_ETM_ATVALID_Msk (0x3UL << TPI_FIFO1_ETM_ATVALID_Pos) |
TPI FIFO1: ETM_ATVALID Mask
#define TPI_FIFO1_ETM_ATVALID_Pos 26U |
TPI FIFO1: ETM_ATVALID Position
#define TPI_FIFO1_ETM_ATVALID_Pos 26U |
TPI FIFO1: ETM_ATVALID Position
#define TPI_FIFO1_ETM_ATVALID_Pos 26U |
TPI FIFO1: ETM_ATVALID Position
#define TPI_FIFO1_ETM_ATVALID_Pos 26U |
TPI FIFO1: ETM_ATVALID Position
#define TPI_FIFO1_ETM_bytecount_Msk (0x3UL << TPI_FIFO1_ETM_bytecount_Pos) |
TPI FIFO1: ETM_bytecount Mask
#define TPI_FIFO1_ETM_bytecount_Msk (0x3UL << TPI_FIFO1_ETM_bytecount_Pos) |
TPI FIFO1: ETM_bytecount Mask
#define TPI_FIFO1_ETM_bytecount_Msk (0x3UL << TPI_FIFO1_ETM_bytecount_Pos) |
TPI FIFO1: ETM_bytecount Mask
#define TPI_FIFO1_ETM_bytecount_Msk (0x3UL << TPI_FIFO1_ETM_bytecount_Pos) |
TPI FIFO1: ETM_bytecount Mask
#define TPI_FIFO1_ETM_bytecount_Pos 24U |
TPI FIFO1: ETM_bytecount Position
#define TPI_FIFO1_ETM_bytecount_Pos 24U |
TPI FIFO1: ETM_bytecount Position
#define TPI_FIFO1_ETM_bytecount_Pos 24U |
TPI FIFO1: ETM_bytecount Position
#define TPI_FIFO1_ETM_bytecount_Pos 24U |
TPI FIFO1: ETM_bytecount Position
#define TPI_FIFO1_ITM0_Msk (0xFFUL /*<< TPI_FIFO1_ITM0_Pos*/) |
TPI FIFO1: ITM0 Mask
#define TPI_FIFO1_ITM0_Msk (0xFFUL /*<< TPI_FIFO1_ITM0_Pos*/) |
TPI FIFO1: ITM0 Mask
#define TPI_FIFO1_ITM0_Msk (0xFFUL /*<< TPI_FIFO1_ITM0_Pos*/) |
TPI FIFO1: ITM0 Mask
#define TPI_FIFO1_ITM0_Msk (0xFFUL /*<< TPI_FIFO1_ITM0_Pos*/) |
TPI FIFO1: ITM0 Mask
#define TPI_FIFO1_ITM0_Pos 0U |
TPI FIFO1: ITM0 Position
#define TPI_FIFO1_ITM0_Pos 0U |
TPI FIFO1: ITM0 Position
#define TPI_FIFO1_ITM0_Pos 0U |
TPI FIFO1: ITM0 Position
#define TPI_FIFO1_ITM0_Pos 0U |
TPI FIFO1: ITM0 Position
#define TPI_FIFO1_ITM1_Msk (0xFFUL << TPI_FIFO1_ITM1_Pos) |
TPI FIFO1: ITM1 Mask
#define TPI_FIFO1_ITM1_Msk (0xFFUL << TPI_FIFO1_ITM1_Pos) |
TPI FIFO1: ITM1 Mask
#define TPI_FIFO1_ITM1_Msk (0xFFUL << TPI_FIFO1_ITM1_Pos) |
TPI FIFO1: ITM1 Mask
#define TPI_FIFO1_ITM1_Msk (0xFFUL << TPI_FIFO1_ITM1_Pos) |
TPI FIFO1: ITM1 Mask
#define TPI_FIFO1_ITM1_Pos 8U |
TPI FIFO1: ITM1 Position
#define TPI_FIFO1_ITM1_Pos 8U |
TPI FIFO1: ITM1 Position
#define TPI_FIFO1_ITM1_Pos 8U |
TPI FIFO1: ITM1 Position
#define TPI_FIFO1_ITM1_Pos 8U |
TPI FIFO1: ITM1 Position
#define TPI_FIFO1_ITM2_Msk (0xFFUL << TPI_FIFO1_ITM2_Pos) |
TPI FIFO1: ITM2 Mask
#define TPI_FIFO1_ITM2_Msk (0xFFUL << TPI_FIFO1_ITM2_Pos) |
TPI FIFO1: ITM2 Mask
#define TPI_FIFO1_ITM2_Msk (0xFFUL << TPI_FIFO1_ITM2_Pos) |
TPI FIFO1: ITM2 Mask
#define TPI_FIFO1_ITM2_Msk (0xFFUL << TPI_FIFO1_ITM2_Pos) |
TPI FIFO1: ITM2 Mask
#define TPI_FIFO1_ITM2_Pos 16U |
TPI FIFO1: ITM2 Position
#define TPI_FIFO1_ITM2_Pos 16U |
TPI FIFO1: ITM2 Position
#define TPI_FIFO1_ITM2_Pos 16U |
TPI FIFO1: ITM2 Position
#define TPI_FIFO1_ITM2_Pos 16U |
TPI FIFO1: ITM2 Position
#define TPI_FIFO1_ITM_ATVALID_Msk (0x3UL << TPI_FIFO1_ITM_ATVALID_Pos) |
TPI FIFO1: ITM_ATVALID Mask
#define TPI_FIFO1_ITM_ATVALID_Msk (0x3UL << TPI_FIFO1_ITM_ATVALID_Pos) |
TPI FIFO1: ITM_ATVALID Mask
#define TPI_FIFO1_ITM_ATVALID_Msk (0x3UL << TPI_FIFO1_ITM_ATVALID_Pos) |
TPI FIFO1: ITM_ATVALID Mask
#define TPI_FIFO1_ITM_ATVALID_Msk (0x3UL << TPI_FIFO1_ITM_ATVALID_Pos) |
TPI FIFO1: ITM_ATVALID Mask
#define TPI_FIFO1_ITM_ATVALID_Pos 29U |
TPI FIFO1: ITM_ATVALID Position
#define TPI_FIFO1_ITM_ATVALID_Pos 29U |
TPI FIFO1: ITM_ATVALID Position
#define TPI_FIFO1_ITM_ATVALID_Pos 29U |
TPI FIFO1: ITM_ATVALID Position
#define TPI_FIFO1_ITM_ATVALID_Pos 29U |
TPI FIFO1: ITM_ATVALID Position
#define TPI_FIFO1_ITM_bytecount_Msk (0x3UL << TPI_FIFO1_ITM_bytecount_Pos) |
TPI FIFO1: ITM_bytecount Mask
#define TPI_FIFO1_ITM_bytecount_Msk (0x3UL << TPI_FIFO1_ITM_bytecount_Pos) |
TPI FIFO1: ITM_bytecount Mask
#define TPI_FIFO1_ITM_bytecount_Msk (0x3UL << TPI_FIFO1_ITM_bytecount_Pos) |
TPI FIFO1: ITM_bytecount Mask
#define TPI_FIFO1_ITM_bytecount_Msk (0x3UL << TPI_FIFO1_ITM_bytecount_Pos) |
TPI FIFO1: ITM_bytecount Mask
#define TPI_FIFO1_ITM_bytecount_Pos 27U |
TPI FIFO1: ITM_bytecount Position
#define TPI_FIFO1_ITM_bytecount_Pos 27U |
TPI FIFO1: ITM_bytecount Position
#define TPI_FIFO1_ITM_bytecount_Pos 27U |
TPI FIFO1: ITM_bytecount Position
#define TPI_FIFO1_ITM_bytecount_Pos 27U |
TPI FIFO1: ITM_bytecount Position
#define TPI_ITATBCTR0_AFVALID1S_Msk (0x1UL << TPI_ITATBCTR0_AFVALID1S_Pos) |
TPI ITATBCTR0: AFVALID1SS Mask
#define TPI_ITATBCTR0_AFVALID1S_Msk (0x1UL << TPI_ITATBCTR0_AFVALID1S_Pos) |
TPI ITATBCTR0: AFVALID1SS Mask
#define TPI_ITATBCTR0_AFVALID1S_Pos 1U |
TPI ITATBCTR0: AFVALID1S Position
#define TPI_ITATBCTR0_AFVALID1S_Pos 1U |
TPI ITATBCTR0: AFVALID1S Position
#define TPI_ITATBCTR0_AFVALID2S_Msk (0x1UL << TPI_ITATBCTR0_AFVALID2S_Pos) |
TPI ITATBCTR0: AFVALID2SS Mask
#define TPI_ITATBCTR0_AFVALID2S_Msk (0x1UL << TPI_ITATBCTR0_AFVALID2S_Pos) |
TPI ITATBCTR0: AFVALID2SS Mask
#define TPI_ITATBCTR0_AFVALID2S_Pos 1U |
TPI ITATBCTR0: AFVALID2S Position
#define TPI_ITATBCTR0_AFVALID2S_Pos 1U |
TPI ITATBCTR0: AFVALID2S Position
#define TPI_ITATBCTR0_ATREADY1_Msk (0x1UL /*<< TPI_ITATBCTR0_ATREADY1_Pos*/) |
TPI ITATBCTR0: ATREADY1 Mask
#define TPI_ITATBCTR0_ATREADY1_Msk (0x1UL /*<< TPI_ITATBCTR0_ATREADY1_Pos*/) |
TPI ITATBCTR0: ATREADY1 Mask
#define TPI_ITATBCTR0_ATREADY1_Msk (0x1UL /*<< TPI_ITATBCTR0_ATREADY1_Pos*/) |
TPI ITATBCTR0: ATREADY1 Mask
#define TPI_ITATBCTR0_ATREADY1_Msk (0x1UL /*<< TPI_ITATBCTR0_ATREADY1_Pos*/) |
TPI ITATBCTR0: ATREADY1 Mask
#define TPI_ITATBCTR0_ATREADY1_Pos 0U |
TPI ITATBCTR0: ATREADY1 Position
#define TPI_ITATBCTR0_ATREADY1_Pos 0U |
TPI ITATBCTR0: ATREADY1 Position
#define TPI_ITATBCTR0_ATREADY1_Pos 0U |
TPI ITATBCTR0: ATREADY1 Position
#define TPI_ITATBCTR0_ATREADY1_Pos 0U |
TPI ITATBCTR0: ATREADY1 Position
#define TPI_ITATBCTR0_ATREADY1S_Msk (0x1UL /*<< TPI_ITATBCTR0_ATREADY1S_Pos*/) |
TPI ITATBCTR0: ATREADY1S Mask
#define TPI_ITATBCTR0_ATREADY1S_Msk (0x1UL /*<< TPI_ITATBCTR0_ATREADY1S_Pos*/) |
TPI ITATBCTR0: ATREADY1S Mask
#define TPI_ITATBCTR0_ATREADY1S_Pos 0U |
TPI ITATBCTR0: ATREADY1S Position
#define TPI_ITATBCTR0_ATREADY1S_Pos 0U |
TPI ITATBCTR0: ATREADY1S Position
#define TPI_ITATBCTR0_ATREADY2_Msk (0x1UL /*<< TPI_ITATBCTR0_ATREADY2_Pos*/) |
TPI ITATBCTR0: ATREADY2 Mask
#define TPI_ITATBCTR0_ATREADY2_Msk (0x1UL /*<< TPI_ITATBCTR0_ATREADY2_Pos*/) |
TPI ITATBCTR0: ATREADY2 Mask
#define TPI_ITATBCTR0_ATREADY2_Msk (0x1UL /*<< TPI_ITATBCTR0_ATREADY2_Pos*/) |
TPI ITATBCTR0: ATREADY2 Mask
#define TPI_ITATBCTR0_ATREADY2_Msk (0x1UL /*<< TPI_ITATBCTR0_ATREADY2_Pos*/) |
TPI ITATBCTR0: ATREADY2 Mask
#define TPI_ITATBCTR0_ATREADY2_Pos 0U |
TPI ITATBCTR0: ATREADY2 Position
#define TPI_ITATBCTR0_ATREADY2_Pos 0U |
TPI ITATBCTR0: ATREADY2 Position
#define TPI_ITATBCTR0_ATREADY2_Pos 0U |
TPI ITATBCTR0: ATREADY2 Position
#define TPI_ITATBCTR0_ATREADY2_Pos 0U |
TPI ITATBCTR0: ATREADY2 Position
#define TPI_ITATBCTR0_ATREADY2S_Msk (0x1UL /*<< TPI_ITATBCTR0_ATREADY2S_Pos*/) |
TPI ITATBCTR0: ATREADY2S Mask
#define TPI_ITATBCTR0_ATREADY2S_Msk (0x1UL /*<< TPI_ITATBCTR0_ATREADY2S_Pos*/) |
TPI ITATBCTR0: ATREADY2S Mask
#define TPI_ITATBCTR0_ATREADY2S_Pos 0U |
TPI ITATBCTR0: ATREADY2S Position
#define TPI_ITATBCTR0_ATREADY2S_Pos 0U |
TPI ITATBCTR0: ATREADY2S Position
#define TPI_ITATBCTR2_AFVALID1S_Msk (0x1UL << TPI_ITATBCTR2_AFVALID1S_Pos) |
TPI ITATBCTR2: AFVALID1SS Mask
#define TPI_ITATBCTR2_AFVALID1S_Msk (0x1UL << TPI_ITATBCTR2_AFVALID1S_Pos) |
TPI ITATBCTR2: AFVALID1SS Mask
#define TPI_ITATBCTR2_AFVALID1S_Pos 1U |
TPI ITATBCTR2: AFVALID1S Position
#define TPI_ITATBCTR2_AFVALID1S_Pos 1U |
TPI ITATBCTR2: AFVALID1S Position
#define TPI_ITATBCTR2_AFVALID2S_Msk (0x1UL << TPI_ITATBCTR2_AFVALID2S_Pos) |
TPI ITATBCTR2: AFVALID2SS Mask
#define TPI_ITATBCTR2_AFVALID2S_Msk (0x1UL << TPI_ITATBCTR2_AFVALID2S_Pos) |
TPI ITATBCTR2: AFVALID2SS Mask
#define TPI_ITATBCTR2_AFVALID2S_Pos 1U |
TPI ITATBCTR2: AFVALID2S Position
#define TPI_ITATBCTR2_AFVALID2S_Pos 1U |
TPI ITATBCTR2: AFVALID2S Position
#define TPI_ITATBCTR2_ATREADY1_Msk (0x1UL /*<< TPI_ITATBCTR2_ATREADY1_Pos*/) |
TPI ITATBCTR2: ATREADY1 Mask
#define TPI_ITATBCTR2_ATREADY1_Msk (0x1UL /*<< TPI_ITATBCTR2_ATREADY1_Pos*/) |
TPI ITATBCTR2: ATREADY1 Mask
#define TPI_ITATBCTR2_ATREADY1_Msk (0x1UL /*<< TPI_ITATBCTR2_ATREADY1_Pos*/) |
TPI ITATBCTR2: ATREADY1 Mask
#define TPI_ITATBCTR2_ATREADY1_Msk (0x1UL /*<< TPI_ITATBCTR2_ATREADY1_Pos*/) |
TPI ITATBCTR2: ATREADY1 Mask
#define TPI_ITATBCTR2_ATREADY1_Pos 0U |
TPI ITATBCTR2: ATREADY1 Position
#define TPI_ITATBCTR2_ATREADY1_Pos 0U |
TPI ITATBCTR2: ATREADY1 Position
#define TPI_ITATBCTR2_ATREADY1_Pos 0U |
TPI ITATBCTR2: ATREADY1 Position
#define TPI_ITATBCTR2_ATREADY1_Pos 0U |
TPI ITATBCTR2: ATREADY1 Position
#define TPI_ITATBCTR2_ATREADY1S_Msk (0x1UL /*<< TPI_ITATBCTR2_ATREADY1S_Pos*/) |
TPI ITATBCTR2: ATREADY1S Mask
#define TPI_ITATBCTR2_ATREADY1S_Msk (0x1UL /*<< TPI_ITATBCTR2_ATREADY1S_Pos*/) |
TPI ITATBCTR2: ATREADY1S Mask
#define TPI_ITATBCTR2_ATREADY1S_Pos 0U |
TPI ITATBCTR2: ATREADY1S Position
#define TPI_ITATBCTR2_ATREADY1S_Pos 0U |
TPI ITATBCTR2: ATREADY1S Position
#define TPI_ITATBCTR2_ATREADY2_Msk (0x1UL /*<< TPI_ITATBCTR2_ATREADY2_Pos*/) |
TPI ITATBCTR2: ATREADY2 Mask
#define TPI_ITATBCTR2_ATREADY2_Msk (0x1UL /*<< TPI_ITATBCTR2_ATREADY2_Pos*/) |
TPI ITATBCTR2: ATREADY2 Mask
#define TPI_ITATBCTR2_ATREADY2_Msk (0x1UL /*<< TPI_ITATBCTR2_ATREADY2_Pos*/) |
TPI ITATBCTR2: ATREADY2 Mask
#define TPI_ITATBCTR2_ATREADY2_Msk (0x1UL /*<< TPI_ITATBCTR2_ATREADY2_Pos*/) |
TPI ITATBCTR2: ATREADY2 Mask
#define TPI_ITATBCTR2_ATREADY2_Pos 0U |
TPI ITATBCTR2: ATREADY2 Position
#define TPI_ITATBCTR2_ATREADY2_Pos 0U |
TPI ITATBCTR2: ATREADY2 Position
#define TPI_ITATBCTR2_ATREADY2_Pos 0U |
TPI ITATBCTR2: ATREADY2 Position
#define TPI_ITATBCTR2_ATREADY2_Pos 0U |
TPI ITATBCTR2: ATREADY2 Position
#define TPI_ITATBCTR2_ATREADY2S_Msk (0x1UL /*<< TPI_ITATBCTR2_ATREADY2S_Pos*/) |
TPI ITATBCTR2: ATREADY2S Mask
#define TPI_ITATBCTR2_ATREADY2S_Msk (0x1UL /*<< TPI_ITATBCTR2_ATREADY2S_Pos*/) |
TPI ITATBCTR2: ATREADY2S Mask
#define TPI_ITATBCTR2_ATREADY2S_Pos 0U |
TPI ITATBCTR2: ATREADY2S Position
#define TPI_ITATBCTR2_ATREADY2S_Pos 0U |
TPI ITATBCTR2: ATREADY2S Position
#define TPI_ITCTRL_Mode_Msk (0x3UL /*<< TPI_ITCTRL_Mode_Pos*/) |
TPI ITCTRL: Mode Mask
#define TPI_ITCTRL_Mode_Msk (0x3UL /*<< TPI_ITCTRL_Mode_Pos*/) |
TPI ITCTRL: Mode Mask
#define TPI_ITCTRL_Mode_Msk (0x3UL /*<< TPI_ITCTRL_Mode_Pos*/) |
TPI ITCTRL: Mode Mask
#define TPI_ITCTRL_Mode_Msk (0x3UL /*<< TPI_ITCTRL_Mode_Pos*/) |
TPI ITCTRL: Mode Mask
#define TPI_ITCTRL_Mode_Msk (0x3UL /*<< TPI_ITCTRL_Mode_Pos*/) |
TPI ITCTRL: Mode Mask
#define TPI_ITCTRL_Mode_Msk (0x3UL /*<< TPI_ITCTRL_Mode_Pos*/) |
TPI ITCTRL: Mode Mask
#define TPI_ITCTRL_Mode_Pos 0U |
TPI ITCTRL: Mode Position
#define TPI_ITCTRL_Mode_Pos 0U |
TPI ITCTRL: Mode Position
#define TPI_ITCTRL_Mode_Pos 0U |
TPI ITCTRL: Mode Position
#define TPI_ITCTRL_Mode_Pos 0U |
TPI ITCTRL: Mode Position
#define TPI_ITCTRL_Mode_Pos 0U |
TPI ITCTRL: Mode Position
#define TPI_ITCTRL_Mode_Pos 0U |
TPI ITCTRL: Mode Position
#define TPI_ITFTTD0_ATB_IF1_ATVALID_Msk (0x3UL << TPI_ITFTTD0_ATB_IF1_ATVALID_Pos) |
TPI ITFTTD0: ATB Interface 1 ATVALID Mask
#define TPI_ITFTTD0_ATB_IF1_ATVALID_Msk (0x3UL << TPI_ITFTTD0_ATB_IF1_ATVALID_Pos) |
TPI ITFTTD0: ATB Interface 1 ATVALID Mask
#define TPI_ITFTTD0_ATB_IF1_ATVALID_Pos 26U |
TPI ITFTTD0: ATB Interface 1 ATVALID Position
#define TPI_ITFTTD0_ATB_IF1_ATVALID_Pos 26U |
TPI ITFTTD0: ATB Interface 1 ATVALID Position
#define TPI_ITFTTD0_ATB_IF1_bytecount_Msk (0x3UL << TPI_ITFTTD0_ATB_IF1_bytecount_Pos) |
TPI ITFTTD0: ATB Interface 1 byte countt Mask
#define TPI_ITFTTD0_ATB_IF1_bytecount_Msk (0x3UL << TPI_ITFTTD0_ATB_IF1_bytecount_Pos) |
TPI ITFTTD0: ATB Interface 1 byte countt Mask
#define TPI_ITFTTD0_ATB_IF1_bytecount_Pos 24U |
TPI ITFTTD0: ATB Interface 1 byte count Position
#define TPI_ITFTTD0_ATB_IF1_bytecount_Pos 24U |
TPI ITFTTD0: ATB Interface 1 byte count Position
#define TPI_ITFTTD0_ATB_IF1_data0_Msk (0xFFUL /*<< TPI_ITFTTD0_ATB_IF1_data0_Pos*/) |
TPI ITFTTD0: ATB Interface 1 data0 Mask
#define TPI_ITFTTD0_ATB_IF1_data0_Msk (0xFFUL /*<< TPI_ITFTTD0_ATB_IF1_data0_Pos*/) |
TPI ITFTTD0: ATB Interface 1 data0 Mask
#define TPI_ITFTTD0_ATB_IF1_data0_Pos 0U |
TPI ITFTTD0: ATB Interface 1 data0 Position
#define TPI_ITFTTD0_ATB_IF1_data0_Pos 0U |
TPI ITFTTD0: ATB Interface 1 data0 Position
#define TPI_ITFTTD0_ATB_IF1_data1_Msk (0xFFUL << TPI_ITFTTD0_ATB_IF1_data1_Pos) |
TPI ITFTTD0: ATB Interface 1 data1 Mask
#define TPI_ITFTTD0_ATB_IF1_data1_Msk (0xFFUL << TPI_ITFTTD0_ATB_IF1_data1_Pos) |
TPI ITFTTD0: ATB Interface 1 data1 Mask
#define TPI_ITFTTD0_ATB_IF1_data1_Pos 8U |
TPI ITFTTD0: ATB Interface 1 data1 Position
#define TPI_ITFTTD0_ATB_IF1_data1_Pos 8U |
TPI ITFTTD0: ATB Interface 1 data1 Position
#define TPI_ITFTTD0_ATB_IF1_data2_Msk (0xFFUL << TPI_ITFTTD0_ATB_IF1_data1_Pos) |
TPI ITFTTD0: ATB Interface 1 data2 Mask
#define TPI_ITFTTD0_ATB_IF1_data2_Msk (0xFFUL << TPI_ITFTTD0_ATB_IF1_data1_Pos) |
TPI ITFTTD0: ATB Interface 1 data2 Mask
#define TPI_ITFTTD0_ATB_IF1_data2_Pos 16U |
TPI ITFTTD0: ATB Interface 1 data2 Position
#define TPI_ITFTTD0_ATB_IF1_data2_Pos 16U |
TPI ITFTTD0: ATB Interface 1 data2 Position
#define TPI_ITFTTD0_ATB_IF2_ATVALID_Msk (0x3UL << TPI_ITFTTD0_ATB_IF2_ATVALID_Pos) |
TPI ITFTTD0: ATB Interface 2 ATVALID Mask
#define TPI_ITFTTD0_ATB_IF2_ATVALID_Msk (0x3UL << TPI_ITFTTD0_ATB_IF2_ATVALID_Pos) |
TPI ITFTTD0: ATB Interface 2 ATVALID Mask
#define TPI_ITFTTD0_ATB_IF2_ATVALID_Pos 29U |
TPI ITFTTD0: ATB Interface 2 ATVALIDPosition
#define TPI_ITFTTD0_ATB_IF2_ATVALID_Pos 29U |
TPI ITFTTD0: ATB Interface 2 ATVALIDPosition
#define TPI_ITFTTD0_ATB_IF2_bytecount_Msk (0x3UL << TPI_ITFTTD0_ATB_IF2_bytecount_Pos) |
TPI ITFTTD0: ATB Interface 2 byte count Mask
#define TPI_ITFTTD0_ATB_IF2_bytecount_Msk (0x3UL << TPI_ITFTTD0_ATB_IF2_bytecount_Pos) |
TPI ITFTTD0: ATB Interface 2 byte count Mask
#define TPI_ITFTTD0_ATB_IF2_bytecount_Pos 27U |
TPI ITFTTD0: ATB Interface 2 byte count Position
#define TPI_ITFTTD0_ATB_IF2_bytecount_Pos 27U |
TPI ITFTTD0: ATB Interface 2 byte count Position
#define TPI_ITFTTD1_ATB_IF1_ATVALID_Msk (0x3UL << TPI_ITFTTD1_ATB_IF1_ATVALID_Pos) |
TPI ITFTTD1: ATB Interface 1 ATVALID Mask
#define TPI_ITFTTD1_ATB_IF1_ATVALID_Msk (0x3UL << TPI_ITFTTD1_ATB_IF1_ATVALID_Pos) |
TPI ITFTTD1: ATB Interface 1 ATVALID Mask
#define TPI_ITFTTD1_ATB_IF1_ATVALID_Pos 26U |
TPI ITFTTD1: ATB Interface 1 ATVALID Position
#define TPI_ITFTTD1_ATB_IF1_ATVALID_Pos 26U |
TPI ITFTTD1: ATB Interface 1 ATVALID Position
#define TPI_ITFTTD1_ATB_IF1_bytecount_Msk (0x3UL << TPI_ITFTTD1_ATB_IF1_bytecount_Pos) |
TPI ITFTTD1: ATB Interface 1 byte countt Mask
#define TPI_ITFTTD1_ATB_IF1_bytecount_Msk (0x3UL << TPI_ITFTTD1_ATB_IF1_bytecount_Pos) |
TPI ITFTTD1: ATB Interface 1 byte countt Mask
#define TPI_ITFTTD1_ATB_IF1_bytecount_Pos 24U |
TPI ITFTTD1: ATB Interface 1 byte count Position
#define TPI_ITFTTD1_ATB_IF1_bytecount_Pos 24U |
TPI ITFTTD1: ATB Interface 1 byte count Position
#define TPI_ITFTTD1_ATB_IF2_ATVALID_Msk (0x3UL << TPI_ITFTTD1_ATB_IF2_ATVALID_Pos) |
TPI ITFTTD1: ATB Interface 2 ATVALID Mask
#define TPI_ITFTTD1_ATB_IF2_ATVALID_Msk (0x3UL << TPI_ITFTTD1_ATB_IF2_ATVALID_Pos) |
TPI ITFTTD1: ATB Interface 2 ATVALID Mask
#define TPI_ITFTTD1_ATB_IF2_ATVALID_Pos 29U |
TPI ITFTTD1: ATB Interface 2 ATVALID Position
#define TPI_ITFTTD1_ATB_IF2_ATVALID_Pos 29U |
TPI ITFTTD1: ATB Interface 2 ATVALID Position
#define TPI_ITFTTD1_ATB_IF2_bytecount_Msk (0x3UL << TPI_ITFTTD1_ATB_IF2_bytecount_Pos) |
TPI ITFTTD1: ATB Interface 2 byte count Mask
#define TPI_ITFTTD1_ATB_IF2_bytecount_Msk (0x3UL << TPI_ITFTTD1_ATB_IF2_bytecount_Pos) |
TPI ITFTTD1: ATB Interface 2 byte count Mask
#define TPI_ITFTTD1_ATB_IF2_bytecount_Pos 27U |
TPI ITFTTD1: ATB Interface 2 byte count Position
#define TPI_ITFTTD1_ATB_IF2_bytecount_Pos 27U |
TPI ITFTTD1: ATB Interface 2 byte count Position
#define TPI_ITFTTD1_ATB_IF2_data0_Msk (0xFFUL /*<< TPI_ITFTTD1_ATB_IF2_data0_Pos*/) |
TPI ITFTTD1: ATB Interface 2 data0 Mask
#define TPI_ITFTTD1_ATB_IF2_data0_Msk (0xFFUL /*<< TPI_ITFTTD1_ATB_IF2_data0_Pos*/) |
TPI ITFTTD1: ATB Interface 2 data0 Mask
#define TPI_ITFTTD1_ATB_IF2_data0_Pos 0U |
TPI ITFTTD1: ATB Interface 2 data0 Position
#define TPI_ITFTTD1_ATB_IF2_data0_Pos 0U |
TPI ITFTTD1: ATB Interface 2 data0 Position
#define TPI_ITFTTD1_ATB_IF2_data1_Msk (0xFFUL << TPI_ITFTTD1_ATB_IF2_data1_Pos) |
TPI ITFTTD1: ATB Interface 2 data1 Mask
#define TPI_ITFTTD1_ATB_IF2_data1_Msk (0xFFUL << TPI_ITFTTD1_ATB_IF2_data1_Pos) |
TPI ITFTTD1: ATB Interface 2 data1 Mask
#define TPI_ITFTTD1_ATB_IF2_data1_Pos 8U |
TPI ITFTTD1: ATB Interface 2 data1 Position
#define TPI_ITFTTD1_ATB_IF2_data1_Pos 8U |
TPI ITFTTD1: ATB Interface 2 data1 Position
#define TPI_ITFTTD1_ATB_IF2_data2_Msk (0xFFUL << TPI_ITFTTD1_ATB_IF2_data1_Pos) |
TPI ITFTTD1: ATB Interface 2 data2 Mask
#define TPI_ITFTTD1_ATB_IF2_data2_Msk (0xFFUL << TPI_ITFTTD1_ATB_IF2_data1_Pos) |
TPI ITFTTD1: ATB Interface 2 data2 Mask
#define TPI_ITFTTD1_ATB_IF2_data2_Pos 16U |
TPI ITFTTD1: ATB Interface 2 data2 Position
#define TPI_ITFTTD1_ATB_IF2_data2_Pos 16U |
TPI ITFTTD1: ATB Interface 2 data2 Position
#define TPI_LSR_nTT_Msk (0x1UL << TPI_LSR_nTT_Pos) |
TPI LSR: Not thirty-two bit. Mask
#define TPI_LSR_nTT_Msk (0x1UL << TPI_LSR_nTT_Pos) |
TPI LSR: Not thirty-two bit. Mask
#define TPI_LSR_nTT_Pos 1U |
TPI LSR: Not thirty-two bit. Position
#define TPI_LSR_nTT_Pos 1U |
TPI LSR: Not thirty-two bit. Position
#define TPI_LSR_SLI_Msk (0x1UL /*<< TPI_LSR_SLI_Pos*/) |
TPI LSR: Software Lock implemented Mask
#define TPI_LSR_SLI_Msk (0x1UL /*<< TPI_LSR_SLI_Pos*/) |
TPI LSR: Software Lock implemented Mask
#define TPI_LSR_SLI_Pos 0U |
TPI LSR: Software Lock implemented Position
#define TPI_LSR_SLI_Pos 0U |
TPI LSR: Software Lock implemented Position
#define TPI_LSR_SLK_Msk (0x1UL << TPI_LSR_SLK_Pos) |
TPI LSR: Software Lock status Mask
#define TPI_LSR_SLK_Msk (0x1UL << TPI_LSR_SLK_Pos) |
TPI LSR: Software Lock status Mask
#define TPI_LSR_SLK_Pos 1U |
TPI LSR: Software Lock status Position
#define TPI_LSR_SLK_Pos 1U |
TPI LSR: Software Lock status Position
#define TPI_PSCR_PSCount_Msk (0x1FUL /*<< TPI_PSCR_PSCount_Pos*/) |
TPI PSCR: TPSCount Mask
#define TPI_PSCR_PSCount_Msk (0x1FUL /*<< TPI_PSCR_PSCount_Pos*/) |
TPI PSCR: TPSCount Mask
#define TPI_PSCR_PSCount_Pos 0U |
TPI PSCR: PSCount Position
#define TPI_PSCR_PSCount_Pos 0U |
TPI PSCR: PSCount Position
#define TPI_SPPR_TXMODE_Msk (0x3UL /*<< TPI_SPPR_TXMODE_Pos*/) |
TPI SPPR: TXMODE Mask
#define TPI_SPPR_TXMODE_Msk (0x3UL /*<< TPI_SPPR_TXMODE_Pos*/) |
TPI SPPR: TXMODE Mask
#define TPI_SPPR_TXMODE_Msk (0x3UL /*<< TPI_SPPR_TXMODE_Pos*/) |
TPI SPPR: TXMODE Mask
#define TPI_SPPR_TXMODE_Msk (0x3UL /*<< TPI_SPPR_TXMODE_Pos*/) |
TPI SPPR: TXMODE Mask
#define TPI_SPPR_TXMODE_Msk (0x3UL /*<< TPI_SPPR_TXMODE_Pos*/) |
TPI SPPR: TXMODE Mask
#define TPI_SPPR_TXMODE_Msk (0x3UL /*<< TPI_SPPR_TXMODE_Pos*/) |
TPI SPPR: TXMODE Mask
#define TPI_SPPR_TXMODE_Msk (0x3UL /*<< TPI_SPPR_TXMODE_Pos*/) |
TPI SPPR: TXMODE Mask
#define TPI_SPPR_TXMODE_Msk (0x3UL /*<< TPI_SPPR_TXMODE_Pos*/) |
TPI SPPR: TXMODE Mask
#define TPI_SPPR_TXMODE_Pos 0U |
TPI SPPR: TXMODE Position
#define TPI_SPPR_TXMODE_Pos 0U |
TPI SPPR: TXMODE Position
#define TPI_SPPR_TXMODE_Pos 0U |
TPI SPPR: TXMODE Position
#define TPI_SPPR_TXMODE_Pos 0U |
TPI SPPR: TXMODE Position
#define TPI_SPPR_TXMODE_Pos 0U |
TPI SPPR: TXMODE Position
#define TPI_SPPR_TXMODE_Pos 0U |
TPI SPPR: TXMODE Position
#define TPI_SPPR_TXMODE_Pos 0U |
TPI SPPR: TXMODE Position
#define TPI_SPPR_TXMODE_Pos 0U |
TPI SPPR: TXMODE Position
#define TPI_TRIGGER_TRIGGER_Msk (0x1UL /*<< TPI_TRIGGER_TRIGGER_Pos*/) |
TPI TRIGGER: TRIGGER Mask
#define TPI_TRIGGER_TRIGGER_Msk (0x1UL /*<< TPI_TRIGGER_TRIGGER_Pos*/) |
TPI TRIGGER: TRIGGER Mask
#define TPI_TRIGGER_TRIGGER_Msk (0x1UL /*<< TPI_TRIGGER_TRIGGER_Pos*/) |
TPI TRIGGER: TRIGGER Mask
#define TPI_TRIGGER_TRIGGER_Msk (0x1UL /*<< TPI_TRIGGER_TRIGGER_Pos*/) |
TPI TRIGGER: TRIGGER Mask
#define TPI_TRIGGER_TRIGGER_Msk (0x1UL /*<< TPI_TRIGGER_TRIGGER_Pos*/) |
TPI TRIGGER: TRIGGER Mask
#define TPI_TRIGGER_TRIGGER_Msk (0x1UL /*<< TPI_TRIGGER_TRIGGER_Pos*/) |
TPI TRIGGER: TRIGGER Mask
#define TPI_TRIGGER_TRIGGER_Pos 0U |
TPI TRIGGER: TRIGGER Position
#define TPI_TRIGGER_TRIGGER_Pos 0U |
TPI TRIGGER: TRIGGER Position
#define TPI_TRIGGER_TRIGGER_Pos 0U |
TPI TRIGGER: TRIGGER Position
#define TPI_TRIGGER_TRIGGER_Pos 0U |
TPI TRIGGER: TRIGGER Position
#define TPI_TRIGGER_TRIGGER_Pos 0U |
TPI TRIGGER: TRIGGER Position
#define TPI_TRIGGER_TRIGGER_Pos 0U |
TPI TRIGGER: TRIGGER Position