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Type definitions for the System Control and ID Register not in the SCB. More...
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System Tick Timer (SysTick) | |
Type definitions for the System Timer Registers. | |
Type definitions for the System Control and ID Register not in the SCB.
#define SCnSCB_ACTLR_DISDEFWBUF_Msk (1UL << SCnSCB_ACTLR_DISDEFWBUF_Pos) |
ACTLR: DISDEFWBUF Mask
#define SCnSCB_ACTLR_DISDEFWBUF_Msk (1UL << SCnSCB_ACTLR_DISDEFWBUF_Pos) |
ACTLR: DISDEFWBUF Mask
#define SCnSCB_ACTLR_DISDEFWBUF_Pos 1U |
ACTLR: DISDEFWBUF Position
#define SCnSCB_ACTLR_DISDEFWBUF_Pos 1U |
ACTLR: DISDEFWBUF Position
#define SCnSCB_ACTLR_DISFOLD_Msk (1UL << SCnSCB_ACTLR_DISFOLD_Pos) |
ACTLR: DISFOLD Mask
#define SCnSCB_ACTLR_DISFOLD_Msk (1UL << SCnSCB_ACTLR_DISFOLD_Pos) |
ACTLR: DISFOLD Mask
#define SCnSCB_ACTLR_DISFOLD_Msk (1UL << SCnSCB_ACTLR_DISFOLD_Pos) |
ACTLR: DISFOLD Mask
#define SCnSCB_ACTLR_DISFOLD_Pos 2U |
ACTLR: DISFOLD Position
#define SCnSCB_ACTLR_DISFOLD_Pos 2U |
ACTLR: DISFOLD Position
#define SCnSCB_ACTLR_DISFOLD_Pos 2U |
ACTLR: DISFOLD Position
#define SCnSCB_ACTLR_DISFPCA_Msk (1UL << SCnSCB_ACTLR_DISFPCA_Pos) |
ACTLR: DISFPCA Mask
#define SCnSCB_ACTLR_DISFPCA_Pos 8U |
ACTLR: DISFPCA Position
#define SCnSCB_ACTLR_DISITMATBFLUSH_Msk (1UL << SCnSCB_ACTLR_DISITMATBFLUSH_Pos) |
ACTLR: DISITMATBFLUSH Mask
#define SCnSCB_ACTLR_DISITMATBFLUSH_Pos 12U |
ACTLR: DISITMATBFLUSH Position
#define SCnSCB_ACTLR_DISMCYCINT_Msk (1UL /*<< SCnSCB_ACTLR_DISMCYCINT_Pos*/) |
ACTLR: DISMCYCINT Mask
#define SCnSCB_ACTLR_DISMCYCINT_Msk (1UL /*<< SCnSCB_ACTLR_DISMCYCINT_Pos*/) |
ACTLR: DISMCYCINT Mask
#define SCnSCB_ACTLR_DISMCYCINT_Msk (1UL /*<< SCnSCB_ACTLR_DISMCYCINT_Pos*/) |
ACTLR: DISMCYCINT Mask
#define SCnSCB_ACTLR_DISMCYCINT_Msk (1UL /*<< SCnSCB_ACTLR_DISMCYCINT_Pos*/) |
ACTLR: DISMCYCINT Mask
#define SCnSCB_ACTLR_DISMCYCINT_Pos 0U |
ACTLR: DISMCYCINT Position
#define SCnSCB_ACTLR_DISMCYCINT_Pos 0U |
ACTLR: DISMCYCINT Position
#define SCnSCB_ACTLR_DISMCYCINT_Pos 0U |
ACTLR: DISMCYCINT Position
#define SCnSCB_ACTLR_DISMCYCINT_Pos 0U |
ACTLR: DISMCYCINT Position
#define SCnSCB_ACTLR_DISOOFP_Msk (1UL << SCnSCB_ACTLR_DISOOFP_Pos) |
ACTLR: DISOOFP Mask
#define SCnSCB_ACTLR_DISOOFP_Pos 9U |
ACTLR: DISOOFP Position
#define SCnSCB_ACTLR_DISRAMODE_Msk (1UL << SCnSCB_ACTLR_DISRAMODE_Pos) |
ACTLR: DISRAMODE Mask
#define SCnSCB_ACTLR_DISRAMODE_Pos 11U |
ACTLR: DISRAMODE Position
#define SCnSCB_ACTLR_FPEXCODIS_Msk (1UL << SCnSCB_ACTLR_FPEXCODIS_Pos) |
ACTLR: FPEXCODIS Mask
#define SCnSCB_ACTLR_FPEXCODIS_Pos 10U |
ACTLR: FPEXCODIS Position
#define SCnSCB_ACTLR_ITCMLAEN_Msk (1UL << SCnSCB_ACTLR_ITCMLAEN_Pos) |
ACTLR: Instruction TCM Lower Alias Enable Mask
#define SCnSCB_ACTLR_ITCMLAEN_Pos 3U |
ACTLR: Instruction TCM Lower Alias Enable Position
#define SCnSCB_ACTLR_ITCMUAEN_Msk (1UL << SCnSCB_ACTLR_ITCMUAEN_Pos) |
ACTLR: Instruction TCM Upper Alias Enable Mask
#define SCnSCB_ACTLR_ITCMUAEN_Pos 4U |
ACTLR: Instruction TCM Upper Alias Enable Position
#define SCnSCB_ICTR_INTLINESNUM_Msk (0xFUL /*<< SCnSCB_ICTR_INTLINESNUM_Pos*/) |
ICTR: INTLINESNUM Mask
#define SCnSCB_ICTR_INTLINESNUM_Msk (0xFUL /*<< SCnSCB_ICTR_INTLINESNUM_Pos*/) |
ICTR: INTLINESNUM Mask
#define SCnSCB_ICTR_INTLINESNUM_Msk (0xFUL /*<< SCnSCB_ICTR_INTLINESNUM_Pos*/) |
ICTR: INTLINESNUM Mask
#define SCnSCB_ICTR_INTLINESNUM_Msk (0xFUL /*<< SCnSCB_ICTR_INTLINESNUM_Pos*/) |
ICTR: INTLINESNUM Mask
#define SCnSCB_ICTR_INTLINESNUM_Msk (0xFUL /*<< SCnSCB_ICTR_INTLINESNUM_Pos*/) |
ICTR: INTLINESNUM Mask
#define SCnSCB_ICTR_INTLINESNUM_Msk (0xFUL /*<< SCnSCB_ICTR_INTLINESNUM_Pos*/) |
ICTR: INTLINESNUM Mask
#define SCnSCB_ICTR_INTLINESNUM_Pos 0U |
ICTR: INTLINESNUM Position
#define SCnSCB_ICTR_INTLINESNUM_Pos 0U |
ICTR: INTLINESNUM Position
#define SCnSCB_ICTR_INTLINESNUM_Pos 0U |
ICTR: INTLINESNUM Position
#define SCnSCB_ICTR_INTLINESNUM_Pos 0U |
ICTR: INTLINESNUM Position
#define SCnSCB_ICTR_INTLINESNUM_Pos 0U |
ICTR: INTLINESNUM Position
#define SCnSCB_ICTR_INTLINESNUM_Pos 0U |
ICTR: INTLINESNUM Position