Type definitions for the System Control and ID Register not in the SCB. More...

Modules
	System Tick Timer (SysTick)
	Type definitions for the System Timer Registers.

Classes
struct	SCnSCB_Type
	Structure type to access the System Control and ID Register not in the SCB. More...

#define	SCnSCB_ICTR_INTLINESNUM_Pos 0U

#define	SCnSCB_ICTR_INTLINESNUM_Msk (0xFUL /<< SCnSCB_ICTR_INTLINESNUM_Pos/)

#define	SCnSCB_ACTLR_ITCMUAEN_Pos 4U

#define	SCnSCB_ACTLR_ITCMUAEN_Msk (1UL << SCnSCB_ACTLR_ITCMUAEN_Pos)

#define	SCnSCB_ACTLR_ITCMLAEN_Pos 3U

#define	SCnSCB_ACTLR_ITCMLAEN_Msk (1UL << SCnSCB_ACTLR_ITCMLAEN_Pos)

#define	SCnSCB_ICTR_INTLINESNUM_Pos 0U

#define	SCnSCB_ICTR_INTLINESNUM_Msk (0xFUL /<< SCnSCB_ICTR_INTLINESNUM_Pos/)

#define	SCnSCB_ACTLR_DISFOLD_Pos 2U

#define	SCnSCB_ACTLR_DISFOLD_Msk (1UL << SCnSCB_ACTLR_DISFOLD_Pos)

#define	SCnSCB_ACTLR_DISDEFWBUF_Pos 1U

#define	SCnSCB_ACTLR_DISDEFWBUF_Msk (1UL << SCnSCB_ACTLR_DISDEFWBUF_Pos)

#define	SCnSCB_ACTLR_DISMCYCINT_Pos 0U

#define	SCnSCB_ACTLR_DISMCYCINT_Msk (1UL /<< SCnSCB_ACTLR_DISMCYCINT_Pos/)

#define	SCnSCB_ICTR_INTLINESNUM_Pos 0U

#define	SCnSCB_ICTR_INTLINESNUM_Msk (0xFUL /<< SCnSCB_ICTR_INTLINESNUM_Pos/)

#define	SCnSCB_ICTR_INTLINESNUM_Pos 0U

#define	SCnSCB_ICTR_INTLINESNUM_Msk (0xFUL /<< SCnSCB_ICTR_INTLINESNUM_Pos/)

#define	SCnSCB_ACTLR_DISOOFP_Pos 9U

#define	SCnSCB_ACTLR_DISOOFP_Msk (1UL << SCnSCB_ACTLR_DISOOFP_Pos)

#define	SCnSCB_ACTLR_DISFPCA_Pos 8U

#define	SCnSCB_ACTLR_DISFPCA_Msk (1UL << SCnSCB_ACTLR_DISFPCA_Pos)

#define	SCnSCB_ACTLR_DISFOLD_Pos 2U

#define	SCnSCB_ACTLR_DISFOLD_Msk (1UL << SCnSCB_ACTLR_DISFOLD_Pos)

#define	SCnSCB_ACTLR_DISDEFWBUF_Pos 1U

#define	SCnSCB_ACTLR_DISDEFWBUF_Msk (1UL << SCnSCB_ACTLR_DISDEFWBUF_Pos)

#define	SCnSCB_ACTLR_DISMCYCINT_Pos 0U

#define	SCnSCB_ACTLR_DISMCYCINT_Msk (1UL /<< SCnSCB_ACTLR_DISMCYCINT_Pos/)

#define	SCnSCB_ICTR_INTLINESNUM_Pos 0U

#define	SCnSCB_ICTR_INTLINESNUM_Msk (0xFUL /<< SCnSCB_ICTR_INTLINESNUM_Pos/)

#define	SCnSCB_ACTLR_DISITMATBFLUSH_Pos 12U

#define	SCnSCB_ACTLR_DISITMATBFLUSH_Msk (1UL << SCnSCB_ACTLR_DISITMATBFLUSH_Pos)

#define	SCnSCB_ACTLR_DISRAMODE_Pos 11U

#define	SCnSCB_ACTLR_DISRAMODE_Msk (1UL << SCnSCB_ACTLR_DISRAMODE_Pos)

#define	SCnSCB_ACTLR_FPEXCODIS_Pos 10U

#define	SCnSCB_ACTLR_FPEXCODIS_Msk (1UL << SCnSCB_ACTLR_FPEXCODIS_Pos)

#define	SCnSCB_ACTLR_DISFOLD_Pos 2U

#define	SCnSCB_ACTLR_DISFOLD_Msk (1UL << SCnSCB_ACTLR_DISFOLD_Pos)

#define	SCnSCB_ACTLR_DISMCYCINT_Pos 0U

#define	SCnSCB_ACTLR_DISMCYCINT_Msk (1UL /<< SCnSCB_ACTLR_DISMCYCINT_Pos/)

#define	SCnSCB_ACTLR_DISMCYCINT_Pos 0U

#define	SCnSCB_ACTLR_DISMCYCINT_Msk (1UL /<< SCnSCB_ACTLR_DISMCYCINT_Pos/)

#define	SCnSCB_ICTR_INTLINESNUM_Pos 0U

#define	SCnSCB_ICTR_INTLINESNUM_Msk (0xFUL /<< SCnSCB_ICTR_INTLINESNUM_Pos/)

Detailed Description

Type definitions for the System Control and ID Register not in the SCB.

Macro Definition Documentation

◆ SCnSCB_ACTLR_DISDEFWBUF_Msk [1/2]

#define SCnSCB_ACTLR_DISDEFWBUF_Msk (1UL << SCnSCB_ACTLR_DISDEFWBUF_Pos)

ACTLR: DISDEFWBUF Mask

◆ SCnSCB_ACTLR_DISDEFWBUF_Msk [2/2]

#define SCnSCB_ACTLR_DISDEFWBUF_Msk (1UL << SCnSCB_ACTLR_DISDEFWBUF_Pos)

ACTLR: DISDEFWBUF Mask

◆ SCnSCB_ACTLR_DISDEFWBUF_Pos [1/2]

#define SCnSCB_ACTLR_DISDEFWBUF_Pos 1U

ACTLR: DISDEFWBUF Position

◆ SCnSCB_ACTLR_DISDEFWBUF_Pos [2/2]

#define SCnSCB_ACTLR_DISDEFWBUF_Pos 1U

ACTLR: DISDEFWBUF Position

◆ SCnSCB_ACTLR_DISFOLD_Msk [1/3]

#define SCnSCB_ACTLR_DISFOLD_Msk (1UL << SCnSCB_ACTLR_DISFOLD_Pos)

ACTLR: DISFOLD Mask

◆ SCnSCB_ACTLR_DISFOLD_Msk [2/3]

#define SCnSCB_ACTLR_DISFOLD_Msk (1UL << SCnSCB_ACTLR_DISFOLD_Pos)

ACTLR: DISFOLD Mask

◆ SCnSCB_ACTLR_DISFOLD_Msk [3/3]

#define SCnSCB_ACTLR_DISFOLD_Msk (1UL << SCnSCB_ACTLR_DISFOLD_Pos)

ACTLR: DISFOLD Mask

◆ SCnSCB_ACTLR_DISFOLD_Pos [1/3]

#define SCnSCB_ACTLR_DISFOLD_Pos 2U

ACTLR: DISFOLD Position

◆ SCnSCB_ACTLR_DISFOLD_Pos [2/3]

#define SCnSCB_ACTLR_DISFOLD_Pos 2U

ACTLR: DISFOLD Position

◆ SCnSCB_ACTLR_DISFOLD_Pos [3/3]

#define SCnSCB_ACTLR_DISFOLD_Pos 2U

ACTLR: DISFOLD Position

◆ SCnSCB_ACTLR_DISFPCA_Msk

#define SCnSCB_ACTLR_DISFPCA_Msk (1UL << SCnSCB_ACTLR_DISFPCA_Pos)

ACTLR: DISFPCA Mask

◆ SCnSCB_ACTLR_DISFPCA_Pos

#define SCnSCB_ACTLR_DISFPCA_Pos 8U

ACTLR: DISFPCA Position

◆ SCnSCB_ACTLR_DISITMATBFLUSH_Msk

#define SCnSCB_ACTLR_DISITMATBFLUSH_Msk (1UL << SCnSCB_ACTLR_DISITMATBFLUSH_Pos)

ACTLR: DISITMATBFLUSH Mask

◆ SCnSCB_ACTLR_DISITMATBFLUSH_Pos

#define SCnSCB_ACTLR_DISITMATBFLUSH_Pos 12U

ACTLR: DISITMATBFLUSH Position

◆ SCnSCB_ACTLR_DISMCYCINT_Msk [1/4]

#define SCnSCB_ACTLR_DISMCYCINT_Msk (1UL /*<< SCnSCB_ACTLR_DISMCYCINT_Pos*/)

ACTLR: DISMCYCINT Mask

◆ SCnSCB_ACTLR_DISMCYCINT_Msk [2/4]

#define SCnSCB_ACTLR_DISMCYCINT_Msk (1UL /*<< SCnSCB_ACTLR_DISMCYCINT_Pos*/)

ACTLR: DISMCYCINT Mask

◆ SCnSCB_ACTLR_DISMCYCINT_Msk [3/4]

#define SCnSCB_ACTLR_DISMCYCINT_Msk (1UL /*<< SCnSCB_ACTLR_DISMCYCINT_Pos*/)

ACTLR: DISMCYCINT Mask

◆ SCnSCB_ACTLR_DISMCYCINT_Msk [4/4]

#define SCnSCB_ACTLR_DISMCYCINT_Msk (1UL /*<< SCnSCB_ACTLR_DISMCYCINT_Pos*/)

ACTLR: DISMCYCINT Mask

◆ SCnSCB_ACTLR_DISMCYCINT_Pos [1/4]

#define SCnSCB_ACTLR_DISMCYCINT_Pos 0U

ACTLR: DISMCYCINT Position

◆ SCnSCB_ACTLR_DISMCYCINT_Pos [2/4]

#define SCnSCB_ACTLR_DISMCYCINT_Pos 0U

ACTLR: DISMCYCINT Position

◆ SCnSCB_ACTLR_DISMCYCINT_Pos [3/4]

#define SCnSCB_ACTLR_DISMCYCINT_Pos 0U

ACTLR: DISMCYCINT Position

◆ SCnSCB_ACTLR_DISMCYCINT_Pos [4/4]

#define SCnSCB_ACTLR_DISMCYCINT_Pos 0U

ACTLR: DISMCYCINT Position

◆ SCnSCB_ACTLR_DISOOFP_Msk

#define SCnSCB_ACTLR_DISOOFP_Msk (1UL << SCnSCB_ACTLR_DISOOFP_Pos)

ACTLR: DISOOFP Mask

◆ SCnSCB_ACTLR_DISOOFP_Pos

#define SCnSCB_ACTLR_DISOOFP_Pos 9U

ACTLR: DISOOFP Position

◆ SCnSCB_ACTLR_DISRAMODE_Msk

#define SCnSCB_ACTLR_DISRAMODE_Msk (1UL << SCnSCB_ACTLR_DISRAMODE_Pos)

ACTLR: DISRAMODE Mask

◆ SCnSCB_ACTLR_DISRAMODE_Pos

#define SCnSCB_ACTLR_DISRAMODE_Pos 11U

ACTLR: DISRAMODE Position

◆ SCnSCB_ACTLR_FPEXCODIS_Msk

#define SCnSCB_ACTLR_FPEXCODIS_Msk (1UL << SCnSCB_ACTLR_FPEXCODIS_Pos)

ACTLR: FPEXCODIS Mask

◆ SCnSCB_ACTLR_FPEXCODIS_Pos

#define SCnSCB_ACTLR_FPEXCODIS_Pos 10U

ACTLR: FPEXCODIS Position

◆ SCnSCB_ACTLR_ITCMLAEN_Msk

#define SCnSCB_ACTLR_ITCMLAEN_Msk (1UL << SCnSCB_ACTLR_ITCMLAEN_Pos)

ACTLR: Instruction TCM Lower Alias Enable Mask

◆ SCnSCB_ACTLR_ITCMLAEN_Pos

#define SCnSCB_ACTLR_ITCMLAEN_Pos 3U

ACTLR: Instruction TCM Lower Alias Enable Position

◆ SCnSCB_ACTLR_ITCMUAEN_Msk

#define SCnSCB_ACTLR_ITCMUAEN_Msk (1UL << SCnSCB_ACTLR_ITCMUAEN_Pos)

ACTLR: Instruction TCM Upper Alias Enable Mask

◆ SCnSCB_ACTLR_ITCMUAEN_Pos

#define SCnSCB_ACTLR_ITCMUAEN_Pos 4U

ACTLR: Instruction TCM Upper Alias Enable Position

◆ SCnSCB_ICTR_INTLINESNUM_Msk [1/6]

#define SCnSCB_ICTR_INTLINESNUM_Msk (0xFUL /*<< SCnSCB_ICTR_INTLINESNUM_Pos*/)

ICTR: INTLINESNUM Mask

◆ SCnSCB_ICTR_INTLINESNUM_Msk [2/6]

#define SCnSCB_ICTR_INTLINESNUM_Msk (0xFUL /*<< SCnSCB_ICTR_INTLINESNUM_Pos*/)

ICTR: INTLINESNUM Mask

◆ SCnSCB_ICTR_INTLINESNUM_Msk [3/6]

#define SCnSCB_ICTR_INTLINESNUM_Msk (0xFUL /*<< SCnSCB_ICTR_INTLINESNUM_Pos*/)

ICTR: INTLINESNUM Mask

◆ SCnSCB_ICTR_INTLINESNUM_Msk [4/6]

#define SCnSCB_ICTR_INTLINESNUM_Msk (0xFUL /*<< SCnSCB_ICTR_INTLINESNUM_Pos*/)

ICTR: INTLINESNUM Mask

◆ SCnSCB_ICTR_INTLINESNUM_Msk [5/6]

#define SCnSCB_ICTR_INTLINESNUM_Msk (0xFUL /*<< SCnSCB_ICTR_INTLINESNUM_Pos*/)

ICTR: INTLINESNUM Mask