Instrumentation Trace Macrocell (ITM)

Type definitions for the Instrumentation Trace Macrocell (ITM) More...

Modules
	Data Watchpoint and Trace (DWT)
	Type definitions for the Data Watchpoint and Trace (DWT)

Classes
struct	ITM_Type
	Structure type to access the Instrumentation Trace Macrocell Register (ITM). More...
#define	ITM_STIM_DISABLED_Pos   1U
#define	ITM_STIM_DISABLED_Msk   (0x1UL << ITM_STIM_DISABLED_Pos)
#define	ITM_STIM_FIFOREADY_Pos   0U
#define	ITM_STIM_FIFOREADY_Msk   (0x1UL /*<< ITM_STIM_FIFOREADY_Pos*/)
#define	ITM_TPR_PRIVMASK_Pos   0U
#define	ITM_TPR_PRIVMASK_Msk   (0xFUL /*<< ITM_TPR_PRIVMASK_Pos*/)
#define	ITM_TCR_BUSY_Pos   23U
#define	ITM_TCR_BUSY_Msk   (1UL << ITM_TCR_BUSY_Pos)
#define	ITM_TCR_TRACEBUSID_Pos   16U
#define	ITM_TCR_TRACEBUSID_Msk   (0x7FUL << ITM_TCR_TRACEBUSID_Pos)
#define	ITM_TCR_GTSFREQ_Pos   10U
#define	ITM_TCR_GTSFREQ_Msk   (3UL << ITM_TCR_GTSFREQ_Pos)
#define	ITM_TCR_TSPRESCALE_Pos   8U
#define	ITM_TCR_TSPRESCALE_Msk   (3UL << ITM_TCR_TSPRESCALE_Pos)
#define	ITM_TCR_STALLENA_Pos   5U
#define	ITM_TCR_STALLENA_Msk   (1UL << ITM_TCR_STALLENA_Pos)
#define	ITM_TCR_SWOENA_Pos   4U
#define	ITM_TCR_SWOENA_Msk   (1UL << ITM_TCR_SWOENA_Pos)
#define	ITM_TCR_DWTENA_Pos   3U
#define	ITM_TCR_DWTENA_Msk   (1UL << ITM_TCR_DWTENA_Pos)
#define	ITM_TCR_SYNCENA_Pos   2U
#define	ITM_TCR_SYNCENA_Msk   (1UL << ITM_TCR_SYNCENA_Pos)
#define	ITM_TCR_TSENA_Pos   1U
#define	ITM_TCR_TSENA_Msk   (1UL << ITM_TCR_TSENA_Pos)
#define	ITM_TCR_ITMENA_Pos   0U
#define	ITM_TCR_ITMENA_Msk   (1UL /*<< ITM_TCR_ITMENA_Pos*/)
#define	ITM_IWR_ATVALIDM_Pos   0U
#define	ITM_IWR_ATVALIDM_Msk   (1UL /*<< ITM_IWR_ATVALIDM_Pos*/)
#define	ITM_IRR_ATREADYM_Pos   0U
#define	ITM_IRR_ATREADYM_Msk   (1UL /*<< ITM_IRR_ATREADYM_Pos*/)
#define	ITM_IMCR_INTEGRATION_Pos   0U
#define	ITM_IMCR_INTEGRATION_Msk   (1UL /*<< ITM_IMCR_INTEGRATION_Pos*/)
#define	ITM_LSR_ByteAcc_Pos   2U
#define	ITM_LSR_ByteAcc_Msk   (1UL << ITM_LSR_ByteAcc_Pos)
#define	ITM_LSR_Access_Pos   1U
#define	ITM_LSR_Access_Msk   (1UL << ITM_LSR_Access_Pos)
#define	ITM_LSR_Present_Pos   0U
#define	ITM_LSR_Present_Msk   (1UL /*<< ITM_LSR_Present_Pos*/)
#define	ITM_TPR_PRIVMASK_Pos   0U
#define	ITM_TPR_PRIVMASK_Msk   (0xFFFFFFFFUL /*<< ITM_TPR_PRIVMASK_Pos*/)
#define	ITM_TCR_BUSY_Pos   23U
#define	ITM_TCR_BUSY_Msk   (1UL << ITM_TCR_BUSY_Pos)
#define	ITM_TCR_TraceBusID_Pos   16U
#define	ITM_TCR_TraceBusID_Msk   (0x7FUL << ITM_TCR_TraceBusID_Pos)
#define	ITM_TCR_GTSFREQ_Pos   10U
#define	ITM_TCR_GTSFREQ_Msk   (3UL << ITM_TCR_GTSFREQ_Pos)
#define	ITM_TCR_TSPrescale_Pos   8U
#define	ITM_TCR_TSPrescale_Msk   (3UL << ITM_TCR_TSPrescale_Pos)
#define	ITM_TCR_SWOENA_Pos   4U
#define	ITM_TCR_SWOENA_Msk   (1UL << ITM_TCR_SWOENA_Pos)
#define	ITM_TCR_DWTENA_Pos   3U
#define	ITM_TCR_DWTENA_Msk   (1UL << ITM_TCR_DWTENA_Pos)
#define	ITM_TCR_SYNCENA_Pos   2U
#define	ITM_TCR_SYNCENA_Msk   (1UL << ITM_TCR_SYNCENA_Pos)
#define	ITM_TCR_TSENA_Pos   1U
#define	ITM_TCR_TSENA_Msk   (1UL << ITM_TCR_TSENA_Pos)
#define	ITM_TCR_ITMENA_Pos   0U
#define	ITM_TCR_ITMENA_Msk   (1UL /*<< ITM_TCR_ITMENA_Pos*/)
#define	ITM_IWR_ATVALIDM_Pos   0U
#define	ITM_IWR_ATVALIDM_Msk   (1UL /*<< ITM_IWR_ATVALIDM_Pos*/)
#define	ITM_IRR_ATREADYM_Pos   0U
#define	ITM_IRR_ATREADYM_Msk   (1UL /*<< ITM_IRR_ATREADYM_Pos*/)
#define	ITM_IMCR_INTEGRATION_Pos   0U
#define	ITM_IMCR_INTEGRATION_Msk   (1UL /*<< ITM_IMCR_INTEGRATION_Pos*/)
#define	ITM_LSR_ByteAcc_Pos   2U
#define	ITM_LSR_ByteAcc_Msk   (1UL << ITM_LSR_ByteAcc_Pos)
#define	ITM_LSR_Access_Pos   1U
#define	ITM_LSR_Access_Msk   (1UL << ITM_LSR_Access_Pos)
#define	ITM_LSR_Present_Pos   0U
#define	ITM_LSR_Present_Msk   (1UL /*<< ITM_LSR_Present_Pos*/)
#define	ITM_STIM_DISABLED_Pos   1U
#define	ITM_STIM_DISABLED_Msk   (0x1UL << ITM_STIM_DISABLED_Pos)
#define	ITM_STIM_FIFOREADY_Pos   0U
#define	ITM_STIM_FIFOREADY_Msk   (0x1UL /*<< ITM_STIM_FIFOREADY_Pos*/)
#define	ITM_TPR_PRIVMASK_Pos   0U
#define	ITM_TPR_PRIVMASK_Msk   (0xFFFFFFFFUL /*<< ITM_TPR_PRIVMASK_Pos*/)
#define	ITM_TCR_BUSY_Pos   23U
#define	ITM_TCR_BUSY_Msk   (1UL << ITM_TCR_BUSY_Pos)
#define	ITM_TCR_TRACEBUSID_Pos   16U
#define	ITM_TCR_TRACEBUSID_Msk   (0x7FUL << ITM_TCR_TRACEBUSID_Pos)
#define	ITM_TCR_GTSFREQ_Pos   10U
#define	ITM_TCR_GTSFREQ_Msk   (3UL << ITM_TCR_GTSFREQ_Pos)
#define	ITM_TCR_TSPRESCALE_Pos   8U
#define	ITM_TCR_TSPRESCALE_Msk   (3UL << ITM_TCR_TSPRESCALE_Pos)
#define	ITM_TCR_STALLENA_Pos   5U
#define	ITM_TCR_STALLENA_Msk   (1UL << ITM_TCR_STALLENA_Pos)
#define	ITM_TCR_SWOENA_Pos   4U
#define	ITM_TCR_SWOENA_Msk   (1UL << ITM_TCR_SWOENA_Pos)
#define	ITM_TCR_DWTENA_Pos   3U
#define	ITM_TCR_DWTENA_Msk   (1UL << ITM_TCR_DWTENA_Pos)
#define	ITM_TCR_SYNCENA_Pos   2U
#define	ITM_TCR_SYNCENA_Msk   (1UL << ITM_TCR_SYNCENA_Pos)
#define	ITM_TCR_TSENA_Pos   1U
#define	ITM_TCR_TSENA_Msk   (1UL << ITM_TCR_TSENA_Pos)
#define	ITM_TCR_ITMENA_Pos   0U
#define	ITM_TCR_ITMENA_Msk   (1UL /*<< ITM_TCR_ITMENA_Pos*/)
#define	ITM_IWR_ATVALIDM_Pos   0U
#define	ITM_IWR_ATVALIDM_Msk   (1UL /*<< ITM_IWR_ATVALIDM_Pos*/)
#define	ITM_IRR_ATREADYM_Pos   0U
#define	ITM_IRR_ATREADYM_Msk   (1UL /*<< ITM_IRR_ATREADYM_Pos*/)
#define	ITM_IMCR_INTEGRATION_Pos   0U
#define	ITM_IMCR_INTEGRATION_Msk   (1UL /*<< ITM_IMCR_INTEGRATION_Pos*/)
#define	ITM_LSR_ByteAcc_Pos   2U
#define	ITM_LSR_ByteAcc_Msk   (1UL << ITM_LSR_ByteAcc_Pos)
#define	ITM_LSR_Access_Pos   1U
#define	ITM_LSR_Access_Msk   (1UL << ITM_LSR_Access_Pos)
#define	ITM_LSR_Present_Pos   0U
#define	ITM_LSR_Present_Msk   (1UL /*<< ITM_LSR_Present_Pos*/)
#define	ITM_TPR_PRIVMASK_Pos   0U
#define	ITM_TPR_PRIVMASK_Msk   (0xFFFFFFFFUL /*<< ITM_TPR_PRIVMASK_Pos*/)
#define	ITM_TCR_BUSY_Pos   23U
#define	ITM_TCR_BUSY_Msk   (1UL << ITM_TCR_BUSY_Pos)
#define	ITM_TCR_TraceBusID_Pos   16U
#define	ITM_TCR_TraceBusID_Msk   (0x7FUL << ITM_TCR_TraceBusID_Pos)
#define	ITM_TCR_GTSFREQ_Pos   10U
#define	ITM_TCR_GTSFREQ_Msk   (3UL << ITM_TCR_GTSFREQ_Pos)
#define	ITM_TCR_TSPrescale_Pos   8U
#define	ITM_TCR_TSPrescale_Msk   (3UL << ITM_TCR_TSPrescale_Pos)
#define	ITM_TCR_SWOENA_Pos   4U
#define	ITM_TCR_SWOENA_Msk   (1UL << ITM_TCR_SWOENA_Pos)
#define	ITM_TCR_DWTENA_Pos   3U
#define	ITM_TCR_DWTENA_Msk   (1UL << ITM_TCR_DWTENA_Pos)
#define	ITM_TCR_SYNCENA_Pos   2U
#define	ITM_TCR_SYNCENA_Msk   (1UL << ITM_TCR_SYNCENA_Pos)
#define	ITM_TCR_TSENA_Pos   1U
#define	ITM_TCR_TSENA_Msk   (1UL << ITM_TCR_TSENA_Pos)
#define	ITM_TCR_ITMENA_Pos   0U
#define	ITM_TCR_ITMENA_Msk   (1UL /*<< ITM_TCR_ITMENA_Pos*/)
#define	ITM_IWR_ATVALIDM_Pos   0U
#define	ITM_IWR_ATVALIDM_Msk   (1UL /*<< ITM_IWR_ATVALIDM_Pos*/)
#define	ITM_IRR_ATREADYM_Pos   0U
#define	ITM_IRR_ATREADYM_Msk   (1UL /*<< ITM_IRR_ATREADYM_Pos*/)
#define	ITM_IMCR_INTEGRATION_Pos   0U
#define	ITM_IMCR_INTEGRATION_Msk   (1UL /*<< ITM_IMCR_INTEGRATION_Pos*/)
#define	ITM_LSR_ByteAcc_Pos   2U
#define	ITM_LSR_ByteAcc_Msk   (1UL << ITM_LSR_ByteAcc_Pos)
#define	ITM_LSR_Access_Pos   1U
#define	ITM_LSR_Access_Msk   (1UL << ITM_LSR_Access_Pos)
#define	ITM_LSR_Present_Pos   0U
#define	ITM_LSR_Present_Msk   (1UL /*<< ITM_LSR_Present_Pos*/)
#define	ITM_TPR_PRIVMASK_Pos   0U
#define	ITM_TPR_PRIVMASK_Msk   (0xFFFFFFFFUL /*<< ITM_TPR_PRIVMASK_Pos*/)
#define	ITM_TCR_BUSY_Pos   23U
#define	ITM_TCR_BUSY_Msk   (1UL << ITM_TCR_BUSY_Pos)
#define	ITM_TCR_TraceBusID_Pos   16U
#define	ITM_TCR_TraceBusID_Msk   (0x7FUL << ITM_TCR_TraceBusID_Pos)
#define	ITM_TCR_GTSFREQ_Pos   10U
#define	ITM_TCR_GTSFREQ_Msk   (3UL << ITM_TCR_GTSFREQ_Pos)
#define	ITM_TCR_TSPrescale_Pos   8U
#define	ITM_TCR_TSPrescale_Msk   (3UL << ITM_TCR_TSPrescale_Pos)
#define	ITM_TCR_SWOENA_Pos   4U
#define	ITM_TCR_SWOENA_Msk   (1UL << ITM_TCR_SWOENA_Pos)
#define	ITM_TCR_DWTENA_Pos   3U
#define	ITM_TCR_DWTENA_Msk   (1UL << ITM_TCR_DWTENA_Pos)
#define	ITM_TCR_SYNCENA_Pos   2U
#define	ITM_TCR_SYNCENA_Msk   (1UL << ITM_TCR_SYNCENA_Pos)
#define	ITM_TCR_TSENA_Pos   1U
#define	ITM_TCR_TSENA_Msk   (1UL << ITM_TCR_TSENA_Pos)
#define	ITM_TCR_ITMENA_Pos   0U
#define	ITM_TCR_ITMENA_Msk   (1UL /*<< ITM_TCR_ITMENA_Pos*/)
#define	ITM_IWR_ATVALIDM_Pos   0U
#define	ITM_IWR_ATVALIDM_Msk   (1UL /*<< ITM_IWR_ATVALIDM_Pos*/)
#define	ITM_IRR_ATREADYM_Pos   0U
#define	ITM_IRR_ATREADYM_Msk   (1UL /*<< ITM_IRR_ATREADYM_Pos*/)
#define	ITM_IMCR_INTEGRATION_Pos   0U
#define	ITM_IMCR_INTEGRATION_Msk   (1UL /*<< ITM_IMCR_INTEGRATION_Pos*/)
#define	ITM_LSR_ByteAcc_Pos   2U
#define	ITM_LSR_ByteAcc_Msk   (1UL << ITM_LSR_ByteAcc_Pos)
#define	ITM_LSR_Access_Pos   1U
#define	ITM_LSR_Access_Msk   (1UL << ITM_LSR_Access_Pos)
#define	ITM_LSR_Present_Pos   0U
#define	ITM_LSR_Present_Msk   (1UL /*<< ITM_LSR_Present_Pos*/)
#define	ITM_TPR_PRIVMASK_Pos   0U
#define	ITM_TPR_PRIVMASK_Msk   (0xFUL /*<< ITM_TPR_PRIVMASK_Pos*/)
#define	ITM_TCR_BUSY_Pos   23U
#define	ITM_TCR_BUSY_Msk   (1UL << ITM_TCR_BUSY_Pos)
#define	ITM_TCR_TraceBusID_Pos   16U
#define	ITM_TCR_TraceBusID_Msk   (0x7FUL << ITM_TCR_TraceBusID_Pos)
#define	ITM_TCR_GTSFREQ_Pos   10U
#define	ITM_TCR_GTSFREQ_Msk   (3UL << ITM_TCR_GTSFREQ_Pos)
#define	ITM_TCR_TSPrescale_Pos   8U
#define	ITM_TCR_TSPrescale_Msk   (3UL << ITM_TCR_TSPrescale_Pos)
#define	ITM_TCR_SWOENA_Pos   4U
#define	ITM_TCR_SWOENA_Msk   (1UL << ITM_TCR_SWOENA_Pos)
#define	ITM_TCR_DWTENA_Pos   3U
#define	ITM_TCR_DWTENA_Msk   (1UL << ITM_TCR_DWTENA_Pos)
#define	ITM_TCR_SYNCENA_Pos   2U
#define	ITM_TCR_SYNCENA_Msk   (1UL << ITM_TCR_SYNCENA_Pos)
#define	ITM_TCR_TSENA_Pos   1U
#define	ITM_TCR_TSENA_Msk   (1UL << ITM_TCR_TSENA_Pos)
#define	ITM_TCR_ITMENA_Pos   0U
#define	ITM_TCR_ITMENA_Msk   (1UL /*<< ITM_TCR_ITMENA_Pos*/)
#define	ITM_IWR_ATVALIDM_Pos   0U
#define	ITM_IWR_ATVALIDM_Msk   (1UL /*<< ITM_IWR_ATVALIDM_Pos*/)
#define	ITM_IRR_ATREADYM_Pos   0U
#define	ITM_IRR_ATREADYM_Msk   (1UL /*<< ITM_IRR_ATREADYM_Pos*/)
#define	ITM_IMCR_INTEGRATION_Pos   0U
#define	ITM_IMCR_INTEGRATION_Msk   (1UL /*<< ITM_IMCR_INTEGRATION_Pos*/)
#define	ITM_LSR_ByteAcc_Pos   2U
#define	ITM_LSR_ByteAcc_Msk   (1UL << ITM_LSR_ByteAcc_Pos)
#define	ITM_LSR_Access_Pos   1U
#define	ITM_LSR_Access_Msk   (1UL << ITM_LSR_Access_Pos)
#define	ITM_LSR_Present_Pos   0U
#define	ITM_LSR_Present_Msk   (1UL /*<< ITM_LSR_Present_Pos*/)

Detailed Description

Type definitions for the Instrumentation Trace Macrocell (ITM)

Macro Definition Documentation

ITM_IMCR_INTEGRATION_Msk [1/6]

#define ITM_IMCR_INTEGRATION_Msk   (1UL /*<< ITM_IMCR_INTEGRATION_Pos*/)

ITM IMCR: INTEGRATION Mask

ITM_IMCR_INTEGRATION_Msk [2/6]

#define ITM_IMCR_INTEGRATION_Msk   (1UL /*<< ITM_IMCR_INTEGRATION_Pos*/)

ITM IMCR: INTEGRATION Mask

ITM_IMCR_INTEGRATION_Msk [3/6]

#define ITM_IMCR_INTEGRATION_Msk   (1UL /*<< ITM_IMCR_INTEGRATION_Pos*/)

ITM IMCR: INTEGRATION Mask

ITM_IMCR_INTEGRATION_Msk [4/6]

#define ITM_IMCR_INTEGRATION_Msk   (1UL /*<< ITM_IMCR_INTEGRATION_Pos*/)

ITM IMCR: INTEGRATION Mask

ITM_IMCR_INTEGRATION_Msk [5/6]

#define ITM_IMCR_INTEGRATION_Msk   (1UL /*<< ITM_IMCR_INTEGRATION_Pos*/)

ITM IMCR: INTEGRATION Mask

ITM_IMCR_INTEGRATION_Msk [6/6]

#define ITM_IMCR_INTEGRATION_Msk   (1UL /*<< ITM_IMCR_INTEGRATION_Pos*/)

ITM IMCR: INTEGRATION Mask

ITM_IMCR_INTEGRATION_Pos [1/6]

#define ITM_IMCR_INTEGRATION_Pos   0U

ITM IMCR: INTEGRATION Position

ITM_IMCR_INTEGRATION_Pos [2/6]

#define ITM_IMCR_INTEGRATION_Pos   0U

ITM IMCR: INTEGRATION Position

ITM_IMCR_INTEGRATION_Pos [3/6]

#define ITM_IMCR_INTEGRATION_Pos   0U

ITM IMCR: INTEGRATION Position

ITM_IMCR_INTEGRATION_Pos [4/6]

#define ITM_IMCR_INTEGRATION_Pos   0U

ITM IMCR: INTEGRATION Position

ITM_IMCR_INTEGRATION_Pos [5/6]

#define ITM_IMCR_INTEGRATION_Pos   0U

ITM IMCR: INTEGRATION Position

ITM_IMCR_INTEGRATION_Pos [6/6]

#define ITM_IMCR_INTEGRATION_Pos   0U

ITM IMCR: INTEGRATION Position

ITM_IRR_ATREADYM_Msk [1/6]

#define ITM_IRR_ATREADYM_Msk   (1UL /*<< ITM_IRR_ATREADYM_Pos*/)

ITM IRR: ATREADYM Mask

ITM_IRR_ATREADYM_Msk [2/6]

#define ITM_IRR_ATREADYM_Msk   (1UL /*<< ITM_IRR_ATREADYM_Pos*/)

ITM IRR: ATREADYM Mask

ITM_IRR_ATREADYM_Msk [3/6]

#define ITM_IRR_ATREADYM_Msk   (1UL /*<< ITM_IRR_ATREADYM_Pos*/)

ITM IRR: ATREADYM Mask

ITM_IRR_ATREADYM_Msk [4/6]

#define ITM_IRR_ATREADYM_Msk   (1UL /*<< ITM_IRR_ATREADYM_Pos*/)

ITM IRR: ATREADYM Mask

ITM_IRR_ATREADYM_Msk [5/6]

#define ITM_IRR_ATREADYM_Msk   (1UL /*<< ITM_IRR_ATREADYM_Pos*/)

ITM IRR: ATREADYM Mask

ITM_IRR_ATREADYM_Msk [6/6]

#define ITM_IRR_ATREADYM_Msk   (1UL /*<< ITM_IRR_ATREADYM_Pos*/)

ITM IRR: ATREADYM Mask

ITM_IRR_ATREADYM_Pos [1/6]

#define ITM_IRR_ATREADYM_Pos   0U

ITM IRR: ATREADYM Position

ITM_IRR_ATREADYM_Pos [2/6]

#define ITM_IRR_ATREADYM_Pos   0U

ITM IRR: ATREADYM Position

ITM_IRR_ATREADYM_Pos [3/6]

#define ITM_IRR_ATREADYM_Pos   0U

ITM IRR: ATREADYM Position

ITM_IRR_ATREADYM_Pos [4/6]

#define ITM_IRR_ATREADYM_Pos   0U

ITM IRR: ATREADYM Position

ITM_IRR_ATREADYM_Pos [5/6]

#define ITM_IRR_ATREADYM_Pos   0U

ITM IRR: ATREADYM Position

ITM_IRR_ATREADYM_Pos [6/6]

#define ITM_IRR_ATREADYM_Pos   0U

ITM IRR: ATREADYM Position

ITM_IWR_ATVALIDM_Msk [1/6]

#define ITM_IWR_ATVALIDM_Msk   (1UL /*<< ITM_IWR_ATVALIDM_Pos*/)

ITM IWR: ATVALIDM Mask

ITM_IWR_ATVALIDM_Msk [2/6]

#define ITM_IWR_ATVALIDM_Msk   (1UL /*<< ITM_IWR_ATVALIDM_Pos*/)

ITM IWR: ATVALIDM Mask

ITM_IWR_ATVALIDM_Msk [3/6]

#define ITM_IWR_ATVALIDM_Msk   (1UL /*<< ITM_IWR_ATVALIDM_Pos*/)

ITM IWR: ATVALIDM Mask

ITM_IWR_ATVALIDM_Msk [4/6]

#define ITM_IWR_ATVALIDM_Msk   (1UL /*<< ITM_IWR_ATVALIDM_Pos*/)

ITM IWR: ATVALIDM Mask

ITM_IWR_ATVALIDM_Msk [5/6]

#define ITM_IWR_ATVALIDM_Msk   (1UL /*<< ITM_IWR_ATVALIDM_Pos*/)

ITM IWR: ATVALIDM Mask

ITM_IWR_ATVALIDM_Msk [6/6]

#define ITM_IWR_ATVALIDM_Msk   (1UL /*<< ITM_IWR_ATVALIDM_Pos*/)

ITM IWR: ATVALIDM Mask

ITM_IWR_ATVALIDM_Pos [1/6]

#define ITM_IWR_ATVALIDM_Pos   0U

ITM IWR: ATVALIDM Position

ITM_IWR_ATVALIDM_Pos [2/6]

#define ITM_IWR_ATVALIDM_Pos   0U

ITM IWR: ATVALIDM Position

ITM_IWR_ATVALIDM_Pos [3/6]

#define ITM_IWR_ATVALIDM_Pos   0U

ITM IWR: ATVALIDM Position

ITM_IWR_ATVALIDM_Pos [4/6]

#define ITM_IWR_ATVALIDM_Pos   0U

ITM IWR: ATVALIDM Position

ITM_IWR_ATVALIDM_Pos [5/6]

#define ITM_IWR_ATVALIDM_Pos   0U

ITM IWR: ATVALIDM Position

ITM_IWR_ATVALIDM_Pos [6/6]

#define ITM_IWR_ATVALIDM_Pos   0U

ITM IWR: ATVALIDM Position

ITM_LSR_Access_Msk [1/6]

#define ITM_LSR_Access_Msk   (1UL << ITM_LSR_Access_Pos)

ITM LSR: Access Mask

ITM_LSR_Access_Msk [2/6]

#define ITM_LSR_Access_Msk   (1UL << ITM_LSR_Access_Pos)

ITM LSR: Access Mask

ITM_LSR_Access_Msk [3/6]

#define ITM_LSR_Access_Msk   (1UL << ITM_LSR_Access_Pos)

ITM LSR: Access Mask

ITM_LSR_Access_Msk [4/6]

#define ITM_LSR_Access_Msk   (1UL << ITM_LSR_Access_Pos)

ITM LSR: Access Mask

ITM_LSR_Access_Msk [5/6]

#define ITM_LSR_Access_Msk   (1UL << ITM_LSR_Access_Pos)

ITM LSR: Access Mask

ITM_LSR_Access_Msk [6/6]

#define ITM_LSR_Access_Msk   (1UL << ITM_LSR_Access_Pos)

ITM LSR: Access Mask

ITM_LSR_Access_Pos [1/6]

#define ITM_LSR_Access_Pos   1U

ITM LSR: Access Position

ITM_LSR_Access_Pos [2/6]

#define ITM_LSR_Access_Pos   1U

ITM LSR: Access Position

ITM_LSR_Access_Pos [3/6]

#define ITM_LSR_Access_Pos   1U

ITM LSR: Access Position

ITM_LSR_Access_Pos [4/6]

#define ITM_LSR_Access_Pos   1U

ITM LSR: Access Position

ITM_LSR_Access_Pos [5/6]

#define ITM_LSR_Access_Pos   1U

ITM LSR: Access Position

ITM_LSR_Access_Pos [6/6]

#define ITM_LSR_Access_Pos   1U

ITM LSR: Access Position

ITM_LSR_ByteAcc_Msk [1/6]

#define ITM_LSR_ByteAcc_Msk   (1UL << ITM_LSR_ByteAcc_Pos)

ITM LSR: ByteAcc Mask

ITM_LSR_ByteAcc_Msk [2/6]

#define ITM_LSR_ByteAcc_Msk   (1UL << ITM_LSR_ByteAcc_Pos)

ITM LSR: ByteAcc Mask

ITM_LSR_ByteAcc_Msk [3/6]

#define ITM_LSR_ByteAcc_Msk   (1UL << ITM_LSR_ByteAcc_Pos)

ITM LSR: ByteAcc Mask

ITM_LSR_ByteAcc_Msk [4/6]

#define ITM_LSR_ByteAcc_Msk   (1UL << ITM_LSR_ByteAcc_Pos)

ITM LSR: ByteAcc Mask

ITM_LSR_ByteAcc_Msk [5/6]

#define ITM_LSR_ByteAcc_Msk   (1UL << ITM_LSR_ByteAcc_Pos)

ITM LSR: ByteAcc Mask

ITM_LSR_ByteAcc_Msk [6/6]

#define ITM_LSR_ByteAcc_Msk   (1UL << ITM_LSR_ByteAcc_Pos)

ITM LSR: ByteAcc Mask

ITM_LSR_ByteAcc_Pos [1/6]

#define ITM_LSR_ByteAcc_Pos   2U

ITM LSR: ByteAcc Position

ITM_LSR_ByteAcc_Pos [2/6]

#define ITM_LSR_ByteAcc_Pos   2U

ITM LSR: ByteAcc Position

ITM_LSR_ByteAcc_Pos [3/6]

#define ITM_LSR_ByteAcc_Pos   2U

ITM LSR: ByteAcc Position

ITM_LSR_ByteAcc_Pos [4/6]

#define ITM_LSR_ByteAcc_Pos   2U

ITM LSR: ByteAcc Position

ITM_LSR_ByteAcc_Pos [5/6]

#define ITM_LSR_ByteAcc_Pos   2U

ITM LSR: ByteAcc Position

ITM_LSR_ByteAcc_Pos [6/6]

#define ITM_LSR_ByteAcc_Pos   2U

ITM LSR: ByteAcc Position

ITM_LSR_Present_Msk [1/6]

#define ITM_LSR_Present_Msk   (1UL /*<< ITM_LSR_Present_Pos*/)

ITM LSR: Present Mask

ITM_LSR_Present_Msk [2/6]

#define ITM_LSR_Present_Msk   (1UL /*<< ITM_LSR_Present_Pos*/)

ITM LSR: Present Mask

ITM_LSR_Present_Msk [3/6]

#define ITM_LSR_Present_Msk   (1UL /*<< ITM_LSR_Present_Pos*/)

ITM LSR: Present Mask

ITM_LSR_Present_Msk [4/6]

#define ITM_LSR_Present_Msk   (1UL /*<< ITM_LSR_Present_Pos*/)

ITM LSR: Present Mask

ITM_LSR_Present_Msk [5/6]

#define ITM_LSR_Present_Msk   (1UL /*<< ITM_LSR_Present_Pos*/)

ITM LSR: Present Mask

ITM_LSR_Present_Msk [6/6]

#define ITM_LSR_Present_Msk   (1UL /*<< ITM_LSR_Present_Pos*/)

ITM LSR: Present Mask

ITM_LSR_Present_Pos [1/6]

#define ITM_LSR_Present_Pos   0U

ITM LSR: Present Position

ITM_LSR_Present_Pos [2/6]

#define ITM_LSR_Present_Pos   0U

ITM LSR: Present Position

ITM_LSR_Present_Pos [3/6]

#define ITM_LSR_Present_Pos   0U

ITM LSR: Present Position

ITM_LSR_Present_Pos [4/6]

#define ITM_LSR_Present_Pos   0U

ITM LSR: Present Position

ITM_LSR_Present_Pos [5/6]

#define ITM_LSR_Present_Pos   0U

ITM LSR: Present Position

ITM_LSR_Present_Pos [6/6]

#define ITM_LSR_Present_Pos   0U

ITM LSR: Present Position

ITM_STIM_DISABLED_Msk [1/2]

#define ITM_STIM_DISABLED_Msk   (0x1UL << ITM_STIM_DISABLED_Pos)

ITM STIM: DISABLED Mask

ITM_STIM_DISABLED_Msk [2/2]

#define ITM_STIM_DISABLED_Msk   (0x1UL << ITM_STIM_DISABLED_Pos)

ITM STIM: DISABLED Mask

ITM_STIM_DISABLED_Pos [1/2]

#define ITM_STIM_DISABLED_Pos   1U

ITM STIM: DISABLED Position

ITM_STIM_DISABLED_Pos [2/2]

#define ITM_STIM_DISABLED_Pos   1U

ITM STIM: DISABLED Position

ITM_STIM_FIFOREADY_Msk [1/2]

#define ITM_STIM_FIFOREADY_Msk   (0x1UL /*<< ITM_STIM_FIFOREADY_Pos*/)

ITM STIM: FIFOREADY Mask

ITM_STIM_FIFOREADY_Msk [2/2]

#define ITM_STIM_FIFOREADY_Msk   (0x1UL /*<< ITM_STIM_FIFOREADY_Pos*/)

ITM STIM: FIFOREADY Mask

ITM_STIM_FIFOREADY_Pos [1/2]

#define ITM_STIM_FIFOREADY_Pos   0U

ITM STIM: FIFOREADY Position

ITM_STIM_FIFOREADY_Pos [2/2]

#define ITM_STIM_FIFOREADY_Pos   0U

ITM STIM: FIFOREADY Position

ITM_TCR_BUSY_Msk [1/6]

#define ITM_TCR_BUSY_Msk   (1UL << ITM_TCR_BUSY_Pos)

ITM TCR: BUSY Mask

ITM_TCR_BUSY_Msk [2/6]

#define ITM_TCR_BUSY_Msk   (1UL << ITM_TCR_BUSY_Pos)

ITM TCR: BUSY Mask

ITM_TCR_BUSY_Msk [3/6]

#define ITM_TCR_BUSY_Msk   (1UL << ITM_TCR_BUSY_Pos)

ITM TCR: BUSY Mask

ITM_TCR_BUSY_Msk [4/6]

#define ITM_TCR_BUSY_Msk   (1UL << ITM_TCR_BUSY_Pos)

ITM TCR: BUSY Mask

ITM_TCR_BUSY_Msk [5/6]

#define ITM_TCR_BUSY_Msk   (1UL << ITM_TCR_BUSY_Pos)

ITM TCR: BUSY Mask

ITM_TCR_BUSY_Msk [6/6]

#define ITM_TCR_BUSY_Msk   (1UL << ITM_TCR_BUSY_Pos)

ITM TCR: BUSY Mask

ITM_TCR_BUSY_Pos [1/6]

#define ITM_TCR_BUSY_Pos   23U

ITM TCR: BUSY Position

ITM_TCR_BUSY_Pos [2/6]

#define ITM_TCR_BUSY_Pos   23U

ITM TCR: BUSY Position

ITM_TCR_BUSY_Pos [3/6]

#define ITM_TCR_BUSY_Pos   23U

ITM TCR: BUSY Position

ITM_TCR_BUSY_Pos [4/6]

#define ITM_TCR_BUSY_Pos   23U

ITM TCR: BUSY Position

ITM_TCR_BUSY_Pos [5/6]

#define ITM_TCR_BUSY_Pos   23U

ITM TCR: BUSY Position

ITM_TCR_BUSY_Pos [6/6]

#define ITM_TCR_BUSY_Pos   23U

ITM TCR: BUSY Position

ITM_TCR_DWTENA_Msk [1/6]

#define ITM_TCR_DWTENA_Msk   (1UL << ITM_TCR_DWTENA_Pos)

ITM TCR: DWTENA Mask

ITM_TCR_DWTENA_Msk [2/6]

#define ITM_TCR_DWTENA_Msk   (1UL << ITM_TCR_DWTENA_Pos)

ITM TCR: DWTENA Mask

ITM_TCR_DWTENA_Msk [3/6]

#define ITM_TCR_DWTENA_Msk   (1UL << ITM_TCR_DWTENA_Pos)

ITM TCR: DWTENA Mask

ITM_TCR_DWTENA_Msk [4/6]

#define ITM_TCR_DWTENA_Msk   (1UL << ITM_TCR_DWTENA_Pos)

ITM TCR: DWTENA Mask

ITM_TCR_DWTENA_Msk [5/6]

#define ITM_TCR_DWTENA_Msk   (1UL << ITM_TCR_DWTENA_Pos)

ITM TCR: DWTENA Mask

ITM_TCR_DWTENA_Msk [6/6]

#define ITM_TCR_DWTENA_Msk   (1UL << ITM_TCR_DWTENA_Pos)

ITM TCR: DWTENA Mask

ITM_TCR_DWTENA_Pos [1/6]

#define ITM_TCR_DWTENA_Pos   3U

ITM TCR: DWTENA Position

ITM_TCR_DWTENA_Pos [2/6]

#define ITM_TCR_DWTENA_Pos   3U

ITM TCR: DWTENA Position

ITM_TCR_DWTENA_Pos [3/6]

#define ITM_TCR_DWTENA_Pos   3U

ITM TCR: DWTENA Position

ITM_TCR_DWTENA_Pos [4/6]

#define ITM_TCR_DWTENA_Pos   3U

ITM TCR: DWTENA Position

ITM_TCR_DWTENA_Pos [5/6]

#define ITM_TCR_DWTENA_Pos   3U

ITM TCR: DWTENA Position

ITM_TCR_DWTENA_Pos [6/6]

#define ITM_TCR_DWTENA_Pos   3U

ITM TCR: DWTENA Position

ITM_TCR_GTSFREQ_Msk [1/6]

#define ITM_TCR_GTSFREQ_Msk   (3UL << ITM_TCR_GTSFREQ_Pos)

ITM TCR: Global timestamp frequency Mask

ITM_TCR_GTSFREQ_Msk [2/6]

#define ITM_TCR_GTSFREQ_Msk   (3UL << ITM_TCR_GTSFREQ_Pos)

ITM TCR: Global timestamp frequency Mask

ITM_TCR_GTSFREQ_Msk [3/6]

#define ITM_TCR_GTSFREQ_Msk   (3UL << ITM_TCR_GTSFREQ_Pos)

ITM TCR: Global timestamp frequency Mask

ITM_TCR_GTSFREQ_Msk [4/6]

#define ITM_TCR_GTSFREQ_Msk   (3UL << ITM_TCR_GTSFREQ_Pos)

ITM TCR: Global timestamp frequency Mask

ITM_TCR_GTSFREQ_Msk [5/6]

#define ITM_TCR_GTSFREQ_Msk   (3UL << ITM_TCR_GTSFREQ_Pos)

ITM TCR: Global timestamp frequency Mask

ITM_TCR_GTSFREQ_Msk [6/6]

#define ITM_TCR_GTSFREQ_Msk   (3UL << ITM_TCR_GTSFREQ_Pos)

ITM TCR: Global timestamp frequency Mask

ITM_TCR_GTSFREQ_Pos [1/6]

#define ITM_TCR_GTSFREQ_Pos   10U

ITM TCR: Global timestamp frequency Position

ITM_TCR_GTSFREQ_Pos [2/6]

#define ITM_TCR_GTSFREQ_Pos   10U

ITM TCR: Global timestamp frequency Position

ITM_TCR_GTSFREQ_Pos [3/6]

#define ITM_TCR_GTSFREQ_Pos   10U

ITM TCR: Global timestamp frequency Position

ITM_TCR_GTSFREQ_Pos [4/6]

#define ITM_TCR_GTSFREQ_Pos   10U

ITM TCR: Global timestamp frequency Position

ITM_TCR_GTSFREQ_Pos [5/6]

#define ITM_TCR_GTSFREQ_Pos   10U

ITM TCR: Global timestamp frequency Position

ITM_TCR_GTSFREQ_Pos [6/6]

#define ITM_TCR_GTSFREQ_Pos   10U

ITM TCR: Global timestamp frequency Position

ITM_TCR_ITMENA_Msk [1/6]

#define ITM_TCR_ITMENA_Msk   (1UL /*<< ITM_TCR_ITMENA_Pos*/)

ITM TCR: ITM Enable bit Mask

ITM_TCR_ITMENA_Msk [2/6]

#define ITM_TCR_ITMENA_Msk   (1UL /*<< ITM_TCR_ITMENA_Pos*/)

ITM TCR: ITM Enable bit Mask

ITM_TCR_ITMENA_Msk [3/6]

#define ITM_TCR_ITMENA_Msk   (1UL /*<< ITM_TCR_ITMENA_Pos*/)

ITM TCR: ITM Enable bit Mask

ITM_TCR_ITMENA_Msk [4/6]

#define ITM_TCR_ITMENA_Msk   (1UL /*<< ITM_TCR_ITMENA_Pos*/)

ITM TCR: ITM Enable bit Mask

ITM_TCR_ITMENA_Msk [5/6]

#define ITM_TCR_ITMENA_Msk   (1UL /*<< ITM_TCR_ITMENA_Pos*/)

ITM TCR: ITM Enable bit Mask

ITM_TCR_ITMENA_Msk [6/6]

#define ITM_TCR_ITMENA_Msk   (1UL /*<< ITM_TCR_ITMENA_Pos*/)

ITM TCR: ITM Enable bit Mask

ITM_TCR_ITMENA_Pos [1/6]

#define ITM_TCR_ITMENA_Pos   0U

ITM TCR: ITM Enable bit Position

ITM_TCR_ITMENA_Pos [2/6]

#define ITM_TCR_ITMENA_Pos   0U

ITM TCR: ITM Enable bit Position

ITM_TCR_ITMENA_Pos [3/6]

#define ITM_TCR_ITMENA_Pos   0U

ITM TCR: ITM Enable bit Position

ITM_TCR_ITMENA_Pos [4/6]

#define ITM_TCR_ITMENA_Pos   0U

ITM TCR: ITM Enable bit Position

ITM_TCR_ITMENA_Pos [5/6]

#define ITM_TCR_ITMENA_Pos   0U

ITM TCR: ITM Enable bit Position

ITM_TCR_ITMENA_Pos [6/6]

#define ITM_TCR_ITMENA_Pos   0U

ITM TCR: ITM Enable bit Position

ITM_TCR_STALLENA_Msk [1/2]

#define ITM_TCR_STALLENA_Msk   (1UL << ITM_TCR_STALLENA_Pos)

ITM TCR: STALLENA Mask

ITM_TCR_STALLENA_Msk [2/2]

#define ITM_TCR_STALLENA_Msk   (1UL << ITM_TCR_STALLENA_Pos)

ITM TCR: STALLENA Mask

ITM_TCR_STALLENA_Pos [1/2]

#define ITM_TCR_STALLENA_Pos   5U

ITM TCR: STALLENA Position

ITM_TCR_STALLENA_Pos [2/2]

#define ITM_TCR_STALLENA_Pos   5U

ITM TCR: STALLENA Position

ITM_TCR_SWOENA_Msk [1/6]

#define ITM_TCR_SWOENA_Msk   (1UL << ITM_TCR_SWOENA_Pos)

ITM TCR: SWOENA Mask

ITM_TCR_SWOENA_Msk [2/6]

#define ITM_TCR_SWOENA_Msk   (1UL << ITM_TCR_SWOENA_Pos)

ITM TCR: SWOENA Mask

ITM_TCR_SWOENA_Msk [3/6]

#define ITM_TCR_SWOENA_Msk   (1UL << ITM_TCR_SWOENA_Pos)

ITM TCR: SWOENA Mask

ITM_TCR_SWOENA_Msk [4/6]

#define ITM_TCR_SWOENA_Msk   (1UL << ITM_TCR_SWOENA_Pos)

ITM TCR: SWOENA Mask

ITM_TCR_SWOENA_Msk [5/6]

#define ITM_TCR_SWOENA_Msk   (1UL << ITM_TCR_SWOENA_Pos)

ITM TCR: SWOENA Mask

ITM_TCR_SWOENA_Msk [6/6]

#define ITM_TCR_SWOENA_Msk   (1UL << ITM_TCR_SWOENA_Pos)

ITM TCR: SWOENA Mask

ITM_TCR_SWOENA_Pos [1/6]

#define ITM_TCR_SWOENA_Pos   4U

ITM TCR: SWOENA Position

ITM_TCR_SWOENA_Pos [2/6]

#define ITM_TCR_SWOENA_Pos   4U

ITM TCR: SWOENA Position

ITM_TCR_SWOENA_Pos [3/6]

#define ITM_TCR_SWOENA_Pos   4U

ITM TCR: SWOENA Position

ITM_TCR_SWOENA_Pos [4/6]

#define ITM_TCR_SWOENA_Pos   4U

ITM TCR: SWOENA Position

ITM_TCR_SWOENA_Pos [5/6]

#define ITM_TCR_SWOENA_Pos   4U

ITM TCR: SWOENA Position

ITM_TCR_SWOENA_Pos [6/6]

#define ITM_TCR_SWOENA_Pos   4U

ITM TCR: SWOENA Position

ITM_TCR_SYNCENA_Msk [1/6]

#define ITM_TCR_SYNCENA_Msk   (1UL << ITM_TCR_SYNCENA_Pos)

ITM TCR: SYNCENA Mask

ITM_TCR_SYNCENA_Msk [2/6]

#define ITM_TCR_SYNCENA_Msk   (1UL << ITM_TCR_SYNCENA_Pos)

ITM TCR: SYNCENA Mask

ITM_TCR_SYNCENA_Msk [3/6]

#define ITM_TCR_SYNCENA_Msk   (1UL << ITM_TCR_SYNCENA_Pos)

ITM TCR: SYNCENA Mask

ITM_TCR_SYNCENA_Msk [4/6]

#define ITM_TCR_SYNCENA_Msk   (1UL << ITM_TCR_SYNCENA_Pos)

ITM TCR: SYNCENA Mask

ITM_TCR_SYNCENA_Msk [5/6]

#define ITM_TCR_SYNCENA_Msk   (1UL << ITM_TCR_SYNCENA_Pos)

ITM TCR: SYNCENA Mask

ITM_TCR_SYNCENA_Msk [6/6]

#define ITM_TCR_SYNCENA_Msk   (1UL << ITM_TCR_SYNCENA_Pos)

ITM TCR: SYNCENA Mask

ITM_TCR_SYNCENA_Pos [1/6]

#define ITM_TCR_SYNCENA_Pos   2U

ITM TCR: SYNCENA Position

ITM_TCR_SYNCENA_Pos [2/6]

#define ITM_TCR_SYNCENA_Pos   2U

ITM TCR: SYNCENA Position

ITM_TCR_SYNCENA_Pos [3/6]

#define ITM_TCR_SYNCENA_Pos   2U

ITM TCR: SYNCENA Position

ITM_TCR_SYNCENA_Pos [4/6]

#define ITM_TCR_SYNCENA_Pos   2U

ITM TCR: SYNCENA Position

ITM_TCR_SYNCENA_Pos [5/6]

#define ITM_TCR_SYNCENA_Pos   2U

ITM TCR: SYNCENA Position

ITM_TCR_SYNCENA_Pos [6/6]

#define ITM_TCR_SYNCENA_Pos   2U

ITM TCR: SYNCENA Position

ITM_TCR_TRACEBUSID_Msk [1/2]

#define ITM_TCR_TRACEBUSID_Msk   (0x7FUL << ITM_TCR_TRACEBUSID_Pos)

ITM TCR: ATBID Mask

ITM_TCR_TraceBusID_Msk [1/4]

#define ITM_TCR_TraceBusID_Msk   (0x7FUL << ITM_TCR_TraceBusID_Pos)

ITM TCR: ATBID Mask

ITM_TCR_TRACEBUSID_Msk [2/2]

#define ITM_TCR_TRACEBUSID_Msk   (0x7FUL << ITM_TCR_TRACEBUSID_Pos)

ITM TCR: ATBID Mask

ITM_TCR_TraceBusID_Msk [2/4]

#define ITM_TCR_TraceBusID_Msk   (0x7FUL << ITM_TCR_TraceBusID_Pos)

ITM TCR: ATBID Mask

ITM_TCR_TraceBusID_Msk [3/4]

#define ITM_TCR_TraceBusID_Msk   (0x7FUL << ITM_TCR_TraceBusID_Pos)

ITM TCR: ATBID Mask

ITM_TCR_TraceBusID_Msk [4/4]

#define ITM_TCR_TraceBusID_Msk   (0x7FUL << ITM_TCR_TraceBusID_Pos)

ITM TCR: ATBID Mask

ITM_TCR_TRACEBUSID_Pos [1/2]

#define ITM_TCR_TRACEBUSID_Pos   16U

ITM TCR: ATBID Position

ITM_TCR_TraceBusID_Pos [1/4]

#define ITM_TCR_TraceBusID_Pos   16U

ITM TCR: ATBID Position

ITM_TCR_TRACEBUSID_Pos [2/2]

#define ITM_TCR_TRACEBUSID_Pos   16U

ITM TCR: ATBID Position

ITM_TCR_TraceBusID_Pos [2/4]

#define ITM_TCR_TraceBusID_Pos   16U

ITM TCR: ATBID Position

ITM_TCR_TraceBusID_Pos [3/4]

#define ITM_TCR_TraceBusID_Pos   16U

ITM TCR: ATBID Position

ITM_TCR_TraceBusID_Pos [4/4]

#define ITM_TCR_TraceBusID_Pos   16U

ITM TCR: ATBID Position

ITM_TCR_TSENA_Msk [1/6]

#define ITM_TCR_TSENA_Msk   (1UL << ITM_TCR_TSENA_Pos)

ITM TCR: TSENA Mask

ITM_TCR_TSENA_Msk [2/6]

#define ITM_TCR_TSENA_Msk   (1UL << ITM_TCR_TSENA_Pos)

ITM TCR: TSENA Mask

ITM_TCR_TSENA_Msk [3/6]

#define ITM_TCR_TSENA_Msk   (1UL << ITM_TCR_TSENA_Pos)

ITM TCR: TSENA Mask

ITM_TCR_TSENA_Msk [4/6]

#define ITM_TCR_TSENA_Msk   (1UL << ITM_TCR_TSENA_Pos)

ITM TCR: TSENA Mask

ITM_TCR_TSENA_Msk [5/6]

#define ITM_TCR_TSENA_Msk   (1UL << ITM_TCR_TSENA_Pos)

ITM TCR: TSENA Mask

ITM_TCR_TSENA_Msk [6/6]

#define ITM_TCR_TSENA_Msk   (1UL << ITM_TCR_TSENA_Pos)

ITM TCR: TSENA Mask

ITM_TCR_TSENA_Pos [1/6]

#define ITM_TCR_TSENA_Pos   1U

ITM TCR: TSENA Position

ITM_TCR_TSENA_Pos [2/6]

#define ITM_TCR_TSENA_Pos   1U

ITM TCR: TSENA Position

ITM_TCR_TSENA_Pos [3/6]

#define ITM_TCR_TSENA_Pos   1U

ITM TCR: TSENA Position

ITM_TCR_TSENA_Pos [4/6]

#define ITM_TCR_TSENA_Pos   1U

ITM TCR: TSENA Position

ITM_TCR_TSENA_Pos [5/6]

#define ITM_TCR_TSENA_Pos   1U

ITM TCR: TSENA Position

ITM_TCR_TSENA_Pos [6/6]

#define ITM_TCR_TSENA_Pos   1U

ITM TCR: TSENA Position

ITM_TCR_TSPRESCALE_Msk [1/2]

#define ITM_TCR_TSPRESCALE_Msk   (3UL << ITM_TCR_TSPRESCALE_Pos)

ITM TCR: TSPRESCALE Mask

ITM_TCR_TSPrescale_Msk [1/4]

#define ITM_TCR_TSPrescale_Msk   (3UL << ITM_TCR_TSPrescale_Pos)

ITM TCR: TSPrescale Mask

ITM_TCR_TSPRESCALE_Msk [2/2]

#define ITM_TCR_TSPRESCALE_Msk   (3UL << ITM_TCR_TSPRESCALE_Pos)

ITM TCR: TSPRESCALE Mask

ITM_TCR_TSPrescale_Msk [2/4]

#define ITM_TCR_TSPrescale_Msk   (3UL << ITM_TCR_TSPrescale_Pos)

ITM TCR: TSPrescale Mask

ITM_TCR_TSPrescale_Msk [3/4]

#define ITM_TCR_TSPrescale_Msk   (3UL << ITM_TCR_TSPrescale_Pos)

ITM TCR: TSPrescale Mask

ITM_TCR_TSPrescale_Msk [4/4]

#define ITM_TCR_TSPrescale_Msk   (3UL << ITM_TCR_TSPrescale_Pos)

ITM TCR: TSPrescale Mask

ITM_TCR_TSPRESCALE_Pos [1/2]

#define ITM_TCR_TSPRESCALE_Pos   8U

ITM TCR: TSPRESCALE Position

ITM_TCR_TSPrescale_Pos [1/4]

#define ITM_TCR_TSPrescale_Pos   8U

ITM TCR: TSPrescale Position

ITM_TCR_TSPRESCALE_Pos [2/2]

#define ITM_TCR_TSPRESCALE_Pos   8U

ITM TCR: TSPRESCALE Position

ITM_TCR_TSPrescale_Pos [2/4]

#define ITM_TCR_TSPrescale_Pos   8U

ITM TCR: TSPrescale Position

ITM_TCR_TSPrescale_Pos [3/4]

#define ITM_TCR_TSPrescale_Pos   8U

ITM TCR: TSPrescale Position

ITM_TCR_TSPrescale_Pos [4/4]

#define ITM_TCR_TSPrescale_Pos   8U

ITM TCR: TSPrescale Position

ITM_TPR_PRIVMASK_Msk [1/6]

#define ITM_TPR_PRIVMASK_Msk   (0xFUL /*<< ITM_TPR_PRIVMASK_Pos*/)

ITM TPR: PRIVMASK Mask

ITM_TPR_PRIVMASK_Msk [2/6]

#define ITM_TPR_PRIVMASK_Msk   (0xFFFFFFFFUL /*<< ITM_TPR_PRIVMASK_Pos*/)

ITM TPR: PRIVMASK Mask

ITM_TPR_PRIVMASK_Msk [3/6]

#define ITM_TPR_PRIVMASK_Msk   (0xFFFFFFFFUL /*<< ITM_TPR_PRIVMASK_Pos*/)

ITM TPR: PRIVMASK Mask

ITM_TPR_PRIVMASK_Msk [4/6]

#define ITM_TPR_PRIVMASK_Msk   (0xFFFFFFFFUL /*<< ITM_TPR_PRIVMASK_Pos*/)

ITM TPR: PRIVMASK Mask

ITM_TPR_PRIVMASK_Msk [5/6]

#define ITM_TPR_PRIVMASK_Msk   (0xFFFFFFFFUL /*<< ITM_TPR_PRIVMASK_Pos*/)

ITM TPR: PRIVMASK Mask

ITM_TPR_PRIVMASK_Msk [6/6]

#define ITM_TPR_PRIVMASK_Msk   (0xFUL /*<< ITM_TPR_PRIVMASK_Pos*/)

ITM TPR: PRIVMASK Mask

ITM_TPR_PRIVMASK_Pos [1/6]

#define ITM_TPR_PRIVMASK_Pos   0U

ITM TPR: PRIVMASK Position

ITM_TPR_PRIVMASK_Pos [2/6]

#define ITM_TPR_PRIVMASK_Pos   0U

ITM TPR: PRIVMASK Position

ITM_TPR_PRIVMASK_Pos [3/6]

#define ITM_TPR_PRIVMASK_Pos   0U

ITM TPR: PRIVMASK Position

ITM_TPR_PRIVMASK_Pos [4/6]

#define ITM_TPR_PRIVMASK_Pos   0U

ITM TPR: PRIVMASK Position

ITM_TPR_PRIVMASK_Pos [5/6]

#define ITM_TPR_PRIVMASK_Pos   0U

ITM TPR: PRIVMASK Position

ITM_TPR_PRIVMASK_Pos [6/6]

#define ITM_TPR_PRIVMASK_Pos   0U

ITM TPR: PRIVMASK Position