25#if defined ( __ICCARM__ )
26 #pragma system_include
27#elif defined (__clang__)
28 #pragma clang system_header
31#ifndef __CORE_CM1_H_GENERIC
32#define __CORE_CM1_H_GENERIC
66#define __CM1_CMSIS_VERSION_MAIN (__CM_CMSIS_VERSION_MAIN)
67#define __CM1_CMSIS_VERSION_SUB (__CM_CMSIS_VERSION_SUB)
68#define __CM1_CMSIS_VERSION ((__CM1_CMSIS_VERSION_MAIN << 16U) | \
69 __CM1_CMSIS_VERSION_SUB )
71#define __CORTEX_M (1U)
78#if defined ( __CC_ARM )
79 #if defined __TARGET_FPU_VFP
80 #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
83#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
84 #if defined __ARM_PCS_VFP
85 #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
88#elif defined ( __GNUC__ )
89 #if defined (__VFP_FP__) && !defined(__SOFTFP__)
90 #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
93#elif defined ( __ICCARM__ )
94 #if defined __ARMVFP__
95 #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
98#elif defined ( __TI_ARM__ )
99 #if defined __TI_VFP_SUPPORT__
100 #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
103#elif defined ( __TASKING__ )
104 #if defined __FPU_VFP__
105 #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
108#elif defined ( __CSMC__ )
109 #if ( __CSMC__ & 0x400U)
110 #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
124#ifndef __CMSIS_GENERIC
126#ifndef __CORE_CM1_H_DEPENDANT
127#define __CORE_CM1_H_DEPENDANT
134#if defined __CHECK_DEVICE_DEFINES
136 #define __CM1_REV 0x0100U
137 #warning "__CM1_REV not defined in device header file; using default!"
140 #ifndef __NVIC_PRIO_BITS
141 #define __NVIC_PRIO_BITS 2U
142 #warning "__NVIC_PRIO_BITS not defined in device header file; using default!"
145 #ifndef __Vendor_SysTickConfig
146 #define __Vendor_SysTickConfig 0U
147 #warning "__Vendor_SysTickConfig not defined in device header file; using default!"
162 #define __I volatile const
168#define __IM volatile const
170#define __IOM volatile
213#define APSR_N_Pos 31U
214#define APSR_N_Msk (1UL << APSR_N_Pos)
216#define APSR_Z_Pos 30U
217#define APSR_Z_Msk (1UL << APSR_Z_Pos)
219#define APSR_C_Pos 29U
220#define APSR_C_Msk (1UL << APSR_C_Pos)
222#define APSR_V_Pos 28U
223#define APSR_V_Msk (1UL << APSR_V_Pos)
240#define IPSR_ISR_Pos 0U
241#define IPSR_ISR_Msk (0x1FFUL )
264#define xPSR_N_Pos 31U
265#define xPSR_N_Msk (1UL << xPSR_N_Pos)
267#define xPSR_Z_Pos 30U
268#define xPSR_Z_Msk (1UL << xPSR_Z_Pos)
270#define xPSR_C_Pos 29U
271#define xPSR_C_Msk (1UL << xPSR_C_Pos)
273#define xPSR_V_Pos 28U
274#define xPSR_V_Msk (1UL << xPSR_V_Pos)
276#define xPSR_T_Pos 24U
277#define xPSR_T_Msk (1UL << xPSR_T_Pos)
279#define xPSR_ISR_Pos 0U
280#define xPSR_ISR_Msk (0x1FFUL )
298#define CONTROL_SPSEL_Pos 1U
299#define CONTROL_SPSEL_Msk (1UL << CONTROL_SPSEL_Pos)
316 __IOM uint32_t ISER[1U];
317 uint32_t RESERVED0[31U];
318 __IOM uint32_t ICER[1U];
319 uint32_t RSERVED1[31U];
320 __IOM uint32_t ISPR[1U];
321 uint32_t RESERVED2[31U];
322 __IOM uint32_t ICPR[1U];
323 uint32_t RESERVED3[31U];
324 uint32_t RESERVED4[64U];
325 __IOM uint32_t IP[8U];
346 __IOM uint32_t AIRCR;
350 __IOM uint32_t SHP[2U];
351 __IOM uint32_t SHCSR;
355#define SCB_CPUID_IMPLEMENTER_Pos 24U
356#define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos)
358#define SCB_CPUID_VARIANT_Pos 20U
359#define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos)
361#define SCB_CPUID_ARCHITECTURE_Pos 16U
362#define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos)
364#define SCB_CPUID_PARTNO_Pos 4U
365#define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos)
367#define SCB_CPUID_REVISION_Pos 0U
368#define SCB_CPUID_REVISION_Msk (0xFUL )
371#define SCB_ICSR_NMIPENDSET_Pos 31U
372#define SCB_ICSR_NMIPENDSET_Msk (1UL << SCB_ICSR_NMIPENDSET_Pos)
374#define SCB_ICSR_PENDSVSET_Pos 28U
375#define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos)
377#define SCB_ICSR_PENDSVCLR_Pos 27U
378#define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos)
380#define SCB_ICSR_PENDSTSET_Pos 26U
381#define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos)
383#define SCB_ICSR_PENDSTCLR_Pos 25U
384#define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos)
386#define SCB_ICSR_ISRPREEMPT_Pos 23U
387#define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos)
389#define SCB_ICSR_ISRPENDING_Pos 22U
390#define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos)
392#define SCB_ICSR_VECTPENDING_Pos 12U
393#define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos)
395#define SCB_ICSR_VECTACTIVE_Pos 0U
396#define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL )
399#define SCB_AIRCR_VECTKEY_Pos 16U
400#define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos)
402#define SCB_AIRCR_VECTKEYSTAT_Pos 16U
403#define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos)
405#define SCB_AIRCR_ENDIANESS_Pos 15U
406#define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos)
408#define SCB_AIRCR_SYSRESETREQ_Pos 2U
409#define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos)
411#define SCB_AIRCR_VECTCLRACTIVE_Pos 1U
412#define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos)
415#define SCB_SCR_SEVONPEND_Pos 4U
416#define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos)
418#define SCB_SCR_SLEEPDEEP_Pos 2U
419#define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos)
421#define SCB_SCR_SLEEPONEXIT_Pos 1U
422#define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos)
425#define SCB_CCR_STKALIGN_Pos 9U
426#define SCB_CCR_STKALIGN_Msk (1UL << SCB_CCR_STKALIGN_Pos)
428#define SCB_CCR_UNALIGN_TRP_Pos 3U
429#define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos)
432#define SCB_SHCSR_SVCALLPENDED_Pos 15U
433#define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos)
450 uint32_t RESERVED0[2U];
451 __IOM uint32_t ACTLR;
455#define SCnSCB_ACTLR_ITCMUAEN_Pos 4U
456#define SCnSCB_ACTLR_ITCMUAEN_Msk (1UL << SCnSCB_ACTLR_ITCMUAEN_Pos)
458#define SCnSCB_ACTLR_ITCMLAEN_Pos 3U
459#define SCnSCB_ACTLR_ITCMLAEN_Msk (1UL << SCnSCB_ACTLR_ITCMLAEN_Pos)
483#define SysTick_CTRL_COUNTFLAG_Pos 16U
484#define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos)
486#define SysTick_CTRL_CLKSOURCE_Pos 2U
487#define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos)
489#define SysTick_CTRL_TICKINT_Pos 1U
490#define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos)
492#define SysTick_CTRL_ENABLE_Pos 0U
493#define SysTick_CTRL_ENABLE_Msk (1UL )
496#define SysTick_LOAD_RELOAD_Pos 0U
497#define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL )
500#define SysTick_VAL_CURRENT_Pos 0U
501#define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL )
504#define SysTick_CALIB_NOREF_Pos 31U
505#define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos)
507#define SysTick_CALIB_SKEW_Pos 30U
508#define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos)
510#define SysTick_CALIB_TENMS_Pos 0U
511#define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL )
539#define _VAL2FLD(field, value) (((uint32_t)(value) << field ## _Pos) & field ## _Msk)
547#define _FLD2VAL(field, value) (((uint32_t)(value) & field ## _Msk) >> field ## _Pos)
560#define SCS_BASE (0xE000E000UL)
561#define SysTick_BASE (SCS_BASE + 0x0010UL)
562#define NVIC_BASE (SCS_BASE + 0x0100UL)
563#define SCB_BASE (SCS_BASE + 0x0D00UL)
565#define SCnSCB ((SCnSCB_Type *) SCS_BASE )
566#define SCB ((SCB_Type *) SCB_BASE )
567#define SysTick ((SysTick_Type *) SysTick_BASE )
568#define NVIC ((NVIC_Type *) NVIC_BASE )
596#ifdef CMSIS_NVIC_VIRTUAL
597 #ifndef CMSIS_NVIC_VIRTUAL_HEADER_FILE
598 #define CMSIS_NVIC_VIRTUAL_HEADER_FILE "cmsis_nvic_virtual.h"
600 #include CMSIS_NVIC_VIRTUAL_HEADER_FILE
602 #define NVIC_SetPriorityGrouping __NVIC_SetPriorityGrouping
603 #define NVIC_GetPriorityGrouping __NVIC_GetPriorityGrouping
604 #define NVIC_EnableIRQ __NVIC_EnableIRQ
605 #define NVIC_GetEnableIRQ __NVIC_GetEnableIRQ
606 #define NVIC_DisableIRQ __NVIC_DisableIRQ
607 #define NVIC_GetPendingIRQ __NVIC_GetPendingIRQ
608 #define NVIC_SetPendingIRQ __NVIC_SetPendingIRQ
609 #define NVIC_ClearPendingIRQ __NVIC_ClearPendingIRQ
611 #define NVIC_SetPriority __NVIC_SetPriority
612 #define NVIC_GetPriority __NVIC_GetPriority
613 #define NVIC_SystemReset __NVIC_SystemReset
616#ifdef CMSIS_VECTAB_VIRTUAL
617 #ifndef CMSIS_VECTAB_VIRTUAL_HEADER_FILE
618 #define CMSIS_VECTAB_VIRTUAL_HEADER_FILE "cmsis_vectab_virtual.h"
620 #include CMSIS_VECTAB_VIRTUAL_HEADER_FILE
622 #define NVIC_SetVector __NVIC_SetVector
623 #define NVIC_GetVector __NVIC_GetVector
626#define NVIC_USER_IRQ_OFFSET 16
630#define EXC_RETURN_HANDLER (0xFFFFFFF1UL)
631#define EXC_RETURN_THREAD_MSP (0xFFFFFFF9UL)
632#define EXC_RETURN_THREAD_PSP (0xFFFFFFFDUL)
637#define _BIT_SHIFT(IRQn) ( ((((uint32_t)(int32_t)(IRQn)) ) & 0x03UL) * 8UL)
638#define _SHP_IDX(IRQn) ( (((((uint32_t)(int32_t)(IRQn)) & 0x0FUL)-8UL) >> 2UL) )
639#define _IP_IDX(IRQn) ( (((uint32_t)(int32_t)(IRQn)) >> 2UL) )
641#define __NVIC_SetPriorityGrouping(X) (void)(X)
642#define __NVIC_GetPriorityGrouping() (0U)
652 if ((int32_t)(IRQn) >= 0)
654 NVIC->ISER[0U] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
669 if ((int32_t)(IRQn) >= 0)
671 return((uint32_t)(((
NVIC->ISER[0U] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
688 if ((int32_t)(IRQn) >= 0)
690 NVIC->ICER[0U] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
707 if ((int32_t)(IRQn) >= 0)
709 return((uint32_t)(((
NVIC->ISPR[0U] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
726 if ((int32_t)(IRQn) >= 0)
728 NVIC->ISPR[0U] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
741 if ((int32_t)(IRQn) >= 0)
743 NVIC->ICPR[0U] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
759 if ((int32_t)(IRQn) >= 0)
784 if ((int32_t)(IRQn) >= 0)
808 uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL);
809 uint32_t PreemptPriorityBits;
810 uint32_t SubPriorityBits;
813 SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(
__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(
__NVIC_PRIO_BITS));
816 ((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits) |
817 ((SubPriority & (uint32_t)((1UL << (SubPriorityBits )) - 1UL)))
835 uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL);
836 uint32_t PreemptPriorityBits;
837 uint32_t SubPriorityBits;
840 SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(
__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(
__NVIC_PRIO_BITS));
842 *pPreemptPriority = (Priority >> SubPriorityBits) & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL);
843 *pSubPriority = (Priority ) & (uint32_t)((1UL << (SubPriorityBits )) - 1UL);
859 uint32_t *vectors = (uint32_t *)0x0U;
874 uint32_t *vectors = (uint32_t *)0x0U;
934#if defined (__Vendor_SysTickConfig) && (__Vendor_SysTickConfig == 0U)
954 SysTick->LOAD = (uint32_t)(ticks - 1UL);
#define __NO_RETURN
Definition: cmsis_armcc.h:65
#define __STATIC_INLINE
Definition: cmsis_armcc.h:59
CMSIS compiler generic header file.
CMSIS Core(M) Version definitions.
#define __IM
Definition: core_cm1.h:168
#define __IOM
Definition: core_cm1.h:170
#define __DSB()
Data Synchronization Barrier.
Definition: cmsis_armcc.h:429
#define __ISB()
Instruction Synchronization Barrier.
Definition: cmsis_armcc.h:418
#define __NOP
No Operation.
Definition: cmsis_armcc.h:387
__NO_RETURN __STATIC_INLINE void __NVIC_SystemReset(void)
System Reset.
Definition: core_armv8mbl.h:1581
__STATIC_INLINE void __NVIC_SetVector(IRQn_Type IRQn, uint32_t vector)
Set Interrupt Vector.
Definition: core_armv8mbl.h:1547
__STATIC_INLINE void NVIC_DecodePriority(uint32_t Priority, uint32_t PriorityGroup, uint32_t *const pPreemptPriority, uint32_t *const pSubPriority)
Decode Priority.
Definition: core_armv8mbl.h:1523
#define _IP_IDX(IRQn)
Definition: core_cm1.h:639
__STATIC_INLINE uint32_t __NVIC_GetVector(IRQn_Type IRQn)
Get Interrupt Vector.
Definition: core_armv8mbl.h:1566
__STATIC_INLINE void __NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority)
Set Interrupt Priority.
Definition: core_armv8mbl.h:1447
#define _BIT_SHIFT(IRQn)
Definition: core_cm1.h:637
__STATIC_INLINE void __NVIC_ClearPendingIRQ(IRQn_Type IRQn)
Clear Pending Interrupt.
Definition: core_armv8mbl.h:1341
__STATIC_INLINE uint32_t __NVIC_GetPendingIRQ(IRQn_Type IRQn)
Get Pending Interrupt.
Definition: core_armv8mbl.h:1307
__STATIC_INLINE uint32_t SCB_GetFPUType(void)
get FPU type
Definition: core_armv8mbl.h:1791
__STATIC_INLINE void __NVIC_EnableIRQ(IRQn_Type IRQn)
Enable Interrupt.
Definition: core_armv8mbl.h:1252
#define NVIC_USER_IRQ_OFFSET
Definition: core_cm1.h:626
__STATIC_INLINE void __NVIC_SetPendingIRQ(IRQn_Type IRQn)
Set Pending Interrupt.
Definition: core_armv8mbl.h:1326
__STATIC_INLINE uint32_t __NVIC_GetEnableIRQ(IRQn_Type IRQn)
Get Interrupt Enable status.
Definition: core_armv8mbl.h:1269
__STATIC_INLINE uint32_t NVIC_EncodePriority(uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority)
Encode Priority.
Definition: core_armv8mbl.h:1496
__STATIC_INLINE void __NVIC_DisableIRQ(IRQn_Type IRQn)
Disable Interrupt.
Definition: core_armv8mbl.h:1288
#define NVIC_SetPriority
Definition: core_cm1.h:611
__STATIC_INLINE uint32_t __NVIC_GetPriority(IRQn_Type IRQn)
Get Interrupt Priority.
Definition: core_armv8mbl.h:1471
#define _SHP_IDX(IRQn)
Definition: core_cm1.h:638
uint32_t C
Definition: core_cm1.h:256
uint32_t V
Definition: core_cm1.h:255
uint32_t T
Definition: core_cm1.h:253
uint32_t SPSEL
Definition: core_cm1.h:291
uint32_t _reserved1
Definition: core_cm1.h:254
uint32_t _reserved1
Definition: core_cm1.h:292
uint32_t N
Definition: core_cm1.h:207
uint32_t _reserved0
Definition: core_cm1.h:203
uint32_t _reserved0
Definition: core_cm1.h:234
uint32_t Z
Definition: core_cm1.h:257
uint32_t ISR
Definition: core_cm1.h:233
uint32_t C
Definition: core_cm1.h:205
uint32_t V
Definition: core_cm1.h:204
uint32_t N
Definition: core_cm1.h:258
uint32_t Z
Definition: core_cm1.h:206
uint32_t _reserved0
Definition: core_cm1.h:290
uint32_t ISR
Definition: core_cm1.h:251
uint32_t _reserved0
Definition: core_cm1.h:252
#define SCB_AIRCR_VECTKEY_Pos
Definition: core_cm1.h:399
#define SCB_AIRCR_SYSRESETREQ_Msk
Definition: core_cm1.h:409
#define SysTick_CTRL_ENABLE_Msk
Definition: core_cm1.h:493
#define SysTick_LOAD_RELOAD_Msk
Definition: core_cm1.h:497
#define SysTick_CTRL_TICKINT_Msk
Definition: core_cm1.h:490
#define SysTick_CTRL_CLKSOURCE_Msk
Definition: core_cm1.h:487
#define SCB
Definition: core_cm1.h:566
#define NVIC
Definition: core_cm1.h:568
#define SysTick
Definition: core_cm1.h:567
#define __NVIC_PRIO_BITS
Definition: stm32f303xe.h:49
IRQn_Type
STM32F303xE devices Interrupt Number Definition, according to the selected device in Library_configur...
Definition: stm32f303xe.h:66
@ SysTick_IRQn
Definition: stm32f303xe.h:76
Structure type to access the Nested Vectored Interrupt Controller (NVIC).
Definition: core_armv8mbl.h:352
Structure type to access the System Control Block (SCB).
Definition: core_armv8mbl.h:382
Structure type to access the System Control and ID Register not in the SCB.
Definition: core_armv8mml.h:1010
Structure type to access the System Timer (SysTick).
Definition: core_armv8mbl.h:559
Union type to access the Application Program Status Register (APSR).
Definition: core_armv8mbl.h:234
Union type to access the Control Registers (CONTROL).
Definition: core_armv8mbl.h:321
Union type to access the Interrupt Program Status Register (IPSR).
Definition: core_armv8mbl.h:264
Union type to access the Special-Purpose Program Status Registers (xPSR).
Definition: core_armv8mbl.h:282