25#if defined ( __ICCARM__ )
26 #pragma system_include
27#elif defined (__clang__)
28 #pragma clang system_header
31#ifndef __CORE_SC000_H_GENERIC
32#define __CORE_SC000_H_GENERIC
66#define __SC000_CMSIS_VERSION_MAIN (__CM_CMSIS_VERSION_MAIN)
67#define __SC000_CMSIS_VERSION_SUB (__CM_CMSIS_VERSION_SUB)
68#define __SC000_CMSIS_VERSION ((__SC000_CMSIS_VERSION_MAIN << 16U) | \
69 __SC000_CMSIS_VERSION_SUB )
71#define __CORTEX_SC (000U)
78#if defined ( __CC_ARM )
79 #if defined __TARGET_FPU_VFP
80 #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
83#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
84 #if defined __ARM_PCS_VFP
85 #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
88#elif defined ( __GNUC__ )
89 #if defined (__VFP_FP__) && !defined(__SOFTFP__)
90 #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
93#elif defined ( __ICCARM__ )
94 #if defined __ARMVFP__
95 #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
98#elif defined ( __TI_ARM__ )
99 #if defined __TI_VFP_SUPPORT__
100 #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
103#elif defined ( __TASKING__ )
104 #if defined __FPU_VFP__
105 #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
108#elif defined ( __CSMC__ )
109 #if ( __CSMC__ & 0x400U)
110 #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
124#ifndef __CMSIS_GENERIC
126#ifndef __CORE_SC000_H_DEPENDANT
127#define __CORE_SC000_H_DEPENDANT
134#if defined __CHECK_DEVICE_DEFINES
136 #define __SC000_REV 0x0000U
137 #warning "__SC000_REV not defined in device header file; using default!"
140 #ifndef __MPU_PRESENT
141 #define __MPU_PRESENT 0U
142 #warning "__MPU_PRESENT not defined in device header file; using default!"
145 #ifndef __NVIC_PRIO_BITS
146 #define __NVIC_PRIO_BITS 2U
147 #warning "__NVIC_PRIO_BITS not defined in device header file; using default!"
150 #ifndef __Vendor_SysTickConfig
151 #define __Vendor_SysTickConfig 0U
152 #warning "__Vendor_SysTickConfig not defined in device header file; using default!"
167 #define __I volatile const
173#define __IM volatile const
175#define __IOM volatile
219#define APSR_N_Pos 31U
220#define APSR_N_Msk (1UL << APSR_N_Pos)
222#define APSR_Z_Pos 30U
223#define APSR_Z_Msk (1UL << APSR_Z_Pos)
225#define APSR_C_Pos 29U
226#define APSR_C_Msk (1UL << APSR_C_Pos)
228#define APSR_V_Pos 28U
229#define APSR_V_Msk (1UL << APSR_V_Pos)
246#define IPSR_ISR_Pos 0U
247#define IPSR_ISR_Msk (0x1FFUL )
270#define xPSR_N_Pos 31U
271#define xPSR_N_Msk (1UL << xPSR_N_Pos)
273#define xPSR_Z_Pos 30U
274#define xPSR_Z_Msk (1UL << xPSR_Z_Pos)
276#define xPSR_C_Pos 29U
277#define xPSR_C_Msk (1UL << xPSR_C_Pos)
279#define xPSR_V_Pos 28U
280#define xPSR_V_Msk (1UL << xPSR_V_Pos)
282#define xPSR_T_Pos 24U
283#define xPSR_T_Msk (1UL << xPSR_T_Pos)
285#define xPSR_ISR_Pos 0U
286#define xPSR_ISR_Msk (0x1FFUL )
304#define CONTROL_SPSEL_Pos 1U
305#define CONTROL_SPSEL_Msk (1UL << CONTROL_SPSEL_Pos)
322 __IOM uint32_t ISER[1U];
323 uint32_t RESERVED0[31U];
324 __IOM uint32_t ICER[1U];
325 uint32_t RSERVED1[31U];
326 __IOM uint32_t ISPR[1U];
327 uint32_t RESERVED2[31U];
328 __IOM uint32_t ICPR[1U];
329 uint32_t RESERVED3[31U];
330 uint32_t RESERVED4[64U];
331 __IOM uint32_t IP[8U];
352 __IOM uint32_t AIRCR;
355 uint32_t RESERVED0[1U];
356 __IOM uint32_t SHP[2U];
357 __IOM uint32_t SHCSR;
358 uint32_t RESERVED1[154U];
363#define SCB_CPUID_IMPLEMENTER_Pos 24U
364#define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos)
366#define SCB_CPUID_VARIANT_Pos 20U
367#define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos)
369#define SCB_CPUID_ARCHITECTURE_Pos 16U
370#define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos)
372#define SCB_CPUID_PARTNO_Pos 4U
373#define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos)
375#define SCB_CPUID_REVISION_Pos 0U
376#define SCB_CPUID_REVISION_Msk (0xFUL )
379#define SCB_ICSR_NMIPENDSET_Pos 31U
380#define SCB_ICSR_NMIPENDSET_Msk (1UL << SCB_ICSR_NMIPENDSET_Pos)
382#define SCB_ICSR_PENDSVSET_Pos 28U
383#define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos)
385#define SCB_ICSR_PENDSVCLR_Pos 27U
386#define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos)
388#define SCB_ICSR_PENDSTSET_Pos 26U
389#define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos)
391#define SCB_ICSR_PENDSTCLR_Pos 25U
392#define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos)
394#define SCB_ICSR_ISRPREEMPT_Pos 23U
395#define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos)
397#define SCB_ICSR_ISRPENDING_Pos 22U
398#define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos)
400#define SCB_ICSR_VECTPENDING_Pos 12U
401#define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos)
403#define SCB_ICSR_VECTACTIVE_Pos 0U
404#define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL )
407#define SCB_VTOR_TBLOFF_Pos 7U
408#define SCB_VTOR_TBLOFF_Msk (0x1FFFFFFUL << SCB_VTOR_TBLOFF_Pos)
411#define SCB_AIRCR_VECTKEY_Pos 16U
412#define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos)
414#define SCB_AIRCR_VECTKEYSTAT_Pos 16U
415#define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos)
417#define SCB_AIRCR_ENDIANESS_Pos 15U
418#define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos)
420#define SCB_AIRCR_SYSRESETREQ_Pos 2U
421#define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos)
423#define SCB_AIRCR_VECTCLRACTIVE_Pos 1U
424#define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos)
427#define SCB_SCR_SEVONPEND_Pos 4U
428#define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos)
430#define SCB_SCR_SLEEPDEEP_Pos 2U
431#define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos)
433#define SCB_SCR_SLEEPONEXIT_Pos 1U
434#define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos)
437#define SCB_CCR_STKALIGN_Pos 9U
438#define SCB_CCR_STKALIGN_Msk (1UL << SCB_CCR_STKALIGN_Pos)
440#define SCB_CCR_UNALIGN_TRP_Pos 3U
441#define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos)
444#define SCB_SHCSR_SVCALLPENDED_Pos 15U
445#define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos)
462 uint32_t RESERVED0[2U];
463 __IOM uint32_t ACTLR;
467#define SCnSCB_ACTLR_DISMCYCINT_Pos 0U
468#define SCnSCB_ACTLR_DISMCYCINT_Msk (1UL )
492#define SysTick_CTRL_COUNTFLAG_Pos 16U
493#define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos)
495#define SysTick_CTRL_CLKSOURCE_Pos 2U
496#define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos)
498#define SysTick_CTRL_TICKINT_Pos 1U
499#define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos)
501#define SysTick_CTRL_ENABLE_Pos 0U
502#define SysTick_CTRL_ENABLE_Msk (1UL )
505#define SysTick_LOAD_RELOAD_Pos 0U
506#define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL )
509#define SysTick_VAL_CURRENT_Pos 0U
510#define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL )
513#define SysTick_CALIB_NOREF_Pos 31U
514#define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos)
516#define SysTick_CALIB_SKEW_Pos 30U
517#define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos)
519#define SysTick_CALIB_TENMS_Pos 0U
520#define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL )
524#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U)
545#define MPU_TYPE_IREGION_Pos 16U
546#define MPU_TYPE_IREGION_Msk (0xFFUL << MPU_TYPE_IREGION_Pos)
548#define MPU_TYPE_DREGION_Pos 8U
549#define MPU_TYPE_DREGION_Msk (0xFFUL << MPU_TYPE_DREGION_Pos)
551#define MPU_TYPE_SEPARATE_Pos 0U
552#define MPU_TYPE_SEPARATE_Msk (1UL )
555#define MPU_CTRL_PRIVDEFENA_Pos 2U
556#define MPU_CTRL_PRIVDEFENA_Msk (1UL << MPU_CTRL_PRIVDEFENA_Pos)
558#define MPU_CTRL_HFNMIENA_Pos 1U
559#define MPU_CTRL_HFNMIENA_Msk (1UL << MPU_CTRL_HFNMIENA_Pos)
561#define MPU_CTRL_ENABLE_Pos 0U
562#define MPU_CTRL_ENABLE_Msk (1UL )
565#define MPU_RNR_REGION_Pos 0U
566#define MPU_RNR_REGION_Msk (0xFFUL )
569#define MPU_RBAR_ADDR_Pos 8U
570#define MPU_RBAR_ADDR_Msk (0xFFFFFFUL << MPU_RBAR_ADDR_Pos)
572#define MPU_RBAR_VALID_Pos 4U
573#define MPU_RBAR_VALID_Msk (1UL << MPU_RBAR_VALID_Pos)
575#define MPU_RBAR_REGION_Pos 0U
576#define MPU_RBAR_REGION_Msk (0xFUL )
579#define MPU_RASR_ATTRS_Pos 16U
580#define MPU_RASR_ATTRS_Msk (0xFFFFUL << MPU_RASR_ATTRS_Pos)
582#define MPU_RASR_XN_Pos 28U
583#define MPU_RASR_XN_Msk (1UL << MPU_RASR_XN_Pos)
585#define MPU_RASR_AP_Pos 24U
586#define MPU_RASR_AP_Msk (0x7UL << MPU_RASR_AP_Pos)
588#define MPU_RASR_TEX_Pos 19U
589#define MPU_RASR_TEX_Msk (0x7UL << MPU_RASR_TEX_Pos)
591#define MPU_RASR_S_Pos 18U
592#define MPU_RASR_S_Msk (1UL << MPU_RASR_S_Pos)
594#define MPU_RASR_C_Pos 17U
595#define MPU_RASR_C_Msk (1UL << MPU_RASR_C_Pos)
597#define MPU_RASR_B_Pos 16U
598#define MPU_RASR_B_Msk (1UL << MPU_RASR_B_Pos)
600#define MPU_RASR_SRD_Pos 8U
601#define MPU_RASR_SRD_Msk (0xFFUL << MPU_RASR_SRD_Pos)
603#define MPU_RASR_SIZE_Pos 1U
604#define MPU_RASR_SIZE_Msk (0x1FUL << MPU_RASR_SIZE_Pos)
606#define MPU_RASR_ENABLE_Pos 0U
607#define MPU_RASR_ENABLE_Msk (1UL )
636#define _VAL2FLD(field, value) (((uint32_t)(value) << field ## _Pos) & field ## _Msk)
644#define _FLD2VAL(field, value) (((uint32_t)(value) & field ## _Msk) >> field ## _Pos)
657#define SCS_BASE (0xE000E000UL)
658#define SysTick_BASE (SCS_BASE + 0x0010UL)
659#define NVIC_BASE (SCS_BASE + 0x0100UL)
660#define SCB_BASE (SCS_BASE + 0x0D00UL)
662#define SCnSCB ((SCnSCB_Type *) SCS_BASE )
663#define SCB ((SCB_Type *) SCB_BASE )
664#define SysTick ((SysTick_Type *) SysTick_BASE )
665#define NVIC ((NVIC_Type *) NVIC_BASE )
667#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U)
668 #define MPU_BASE (SCS_BASE + 0x0D90UL)
669 #define MPU ((MPU_Type *) MPU_BASE )
697#ifdef CMSIS_NVIC_VIRTUAL
698 #ifndef CMSIS_NVIC_VIRTUAL_HEADER_FILE
699 #define CMSIS_NVIC_VIRTUAL_HEADER_FILE "cmsis_nvic_virtual.h"
701 #include CMSIS_NVIC_VIRTUAL_HEADER_FILE
705 #define NVIC_EnableIRQ __NVIC_EnableIRQ
706 #define NVIC_GetEnableIRQ __NVIC_GetEnableIRQ
707 #define NVIC_DisableIRQ __NVIC_DisableIRQ
708 #define NVIC_GetPendingIRQ __NVIC_GetPendingIRQ
709 #define NVIC_SetPendingIRQ __NVIC_SetPendingIRQ
710 #define NVIC_ClearPendingIRQ __NVIC_ClearPendingIRQ
712 #define NVIC_SetPriority __NVIC_SetPriority
713 #define NVIC_GetPriority __NVIC_GetPriority
714 #define NVIC_SystemReset __NVIC_SystemReset
717#ifdef CMSIS_VECTAB_VIRTUAL
718 #ifndef CMSIS_VECTAB_VIRTUAL_HEADER_FILE
719 #define CMSIS_VECTAB_VIRTUAL_HEADER_FILE "cmsis_vectab_virtual.h"
721 #include CMSIS_VECTAB_VIRTUAL_HEADER_FILE
723 #define NVIC_SetVector __NVIC_SetVector
724 #define NVIC_GetVector __NVIC_GetVector
727#define NVIC_USER_IRQ_OFFSET 16
731#define EXC_RETURN_HANDLER (0xFFFFFFF1UL)
732#define EXC_RETURN_THREAD_MSP (0xFFFFFFF9UL)
733#define EXC_RETURN_THREAD_PSP (0xFFFFFFFDUL)
738#define _BIT_SHIFT(IRQn) ( ((((uint32_t)(int32_t)(IRQn)) ) & 0x03UL) * 8UL)
739#define _SHP_IDX(IRQn) ( (((((uint32_t)(int32_t)(IRQn)) & 0x0FUL)-8UL) >> 2UL) )
740#define _IP_IDX(IRQn) ( (((uint32_t)(int32_t)(IRQn)) >> 2UL) )
751 if ((int32_t)(IRQn) >= 0)
753 NVIC->ISER[0U] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
768 if ((int32_t)(IRQn) >= 0)
770 return((uint32_t)(((
NVIC->ISER[0U] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
787 if ((int32_t)(IRQn) >= 0)
789 NVIC->ICER[0U] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
806 if ((int32_t)(IRQn) >= 0)
808 return((uint32_t)(((
NVIC->ISPR[0U] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
825 if ((int32_t)(IRQn) >= 0)
827 NVIC->ISPR[0U] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
840 if ((int32_t)(IRQn) >= 0)
842 NVIC->ICPR[0U] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
858 if ((int32_t)(IRQn) >= 0)
883 if ((int32_t)(IRQn) >= 0)
905 uint32_t *vectors = (uint32_t *)
SCB->VTOR;
920 uint32_t *vectors = (uint32_t *)
SCB->VTOR;
980#if defined (__Vendor_SysTickConfig) && (__Vendor_SysTickConfig == 0U)
1000 SysTick->LOAD = (uint32_t)(ticks - 1UL);
#define __NO_RETURN
Definition: cmsis_armcc.h:65
#define __STATIC_INLINE
Definition: cmsis_armcc.h:59
CMSIS compiler generic header file.
CMSIS Core(M) Version definitions.
#define __IM
Definition: core_sc000.h:173
#define __IOM
Definition: core_sc000.h:175
#define __DSB()
Data Synchronization Barrier.
Definition: cmsis_armcc.h:429
#define __ISB()
Instruction Synchronization Barrier.
Definition: cmsis_armcc.h:418
#define __NOP
No Operation.
Definition: cmsis_armcc.h:387
__NO_RETURN __STATIC_INLINE void __NVIC_SystemReset(void)
System Reset.
Definition: core_armv8mbl.h:1581
__STATIC_INLINE void __NVIC_SetVector(IRQn_Type IRQn, uint32_t vector)
Set Interrupt Vector.
Definition: core_armv8mbl.h:1547
#define _IP_IDX(IRQn)
Definition: core_sc000.h:740
__STATIC_INLINE uint32_t __NVIC_GetVector(IRQn_Type IRQn)
Get Interrupt Vector.
Definition: core_armv8mbl.h:1566
__STATIC_INLINE void __NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority)
Set Interrupt Priority.
Definition: core_armv8mbl.h:1447
#define _BIT_SHIFT(IRQn)
Definition: core_sc000.h:738
__STATIC_INLINE void __NVIC_ClearPendingIRQ(IRQn_Type IRQn)
Clear Pending Interrupt.
Definition: core_armv8mbl.h:1341
__STATIC_INLINE uint32_t __NVIC_GetPendingIRQ(IRQn_Type IRQn)
Get Pending Interrupt.
Definition: core_armv8mbl.h:1307
__STATIC_INLINE uint32_t SCB_GetFPUType(void)
get FPU type
Definition: core_armv8mbl.h:1791
__STATIC_INLINE void __NVIC_EnableIRQ(IRQn_Type IRQn)
Enable Interrupt.
Definition: core_armv8mbl.h:1252
#define NVIC_USER_IRQ_OFFSET
Definition: core_sc000.h:727
__STATIC_INLINE void __NVIC_SetPendingIRQ(IRQn_Type IRQn)
Set Pending Interrupt.
Definition: core_armv8mbl.h:1326
__STATIC_INLINE uint32_t __NVIC_GetEnableIRQ(IRQn_Type IRQn)
Get Interrupt Enable status.
Definition: core_armv8mbl.h:1269
__STATIC_INLINE void __NVIC_DisableIRQ(IRQn_Type IRQn)
Disable Interrupt.
Definition: core_armv8mbl.h:1288
#define NVIC_SetPriority
Definition: core_sc000.h:712
__STATIC_INLINE uint32_t __NVIC_GetPriority(IRQn_Type IRQn)
Get Interrupt Priority.
Definition: core_armv8mbl.h:1471
#define _SHP_IDX(IRQn)
Definition: core_sc000.h:739
uint32_t Z
Definition: core_sc000.h:212
uint32_t _reserved1
Definition: core_sc000.h:260
uint32_t N
Definition: core_sc000.h:213
uint32_t ISR
Definition: core_sc000.h:239
uint32_t _reserved0
Definition: core_sc000.h:296
uint32_t ISR
Definition: core_sc000.h:257
uint32_t T
Definition: core_sc000.h:259
uint32_t Z
Definition: core_sc000.h:263
uint32_t _reserved0
Definition: core_sc000.h:209
__IOM uint32_t SFCR
Definition: core_sc000.h:359
uint32_t _reserved1
Definition: core_sc000.h:298
uint32_t V
Definition: core_sc000.h:210
uint32_t C
Definition: core_sc000.h:211
uint32_t C
Definition: core_sc000.h:262
uint32_t N
Definition: core_sc000.h:264
uint32_t _reserved0
Definition: core_sc000.h:258
uint32_t SPSEL
Definition: core_sc000.h:297
uint32_t _reserved0
Definition: core_sc000.h:240
uint32_t V
Definition: core_sc000.h:261
#define SCB_AIRCR_VECTKEY_Pos
Definition: core_sc000.h:411
#define SCB_AIRCR_SYSRESETREQ_Msk
Definition: core_sc000.h:421
#define SysTick_CTRL_ENABLE_Msk
Definition: core_sc000.h:502
#define SysTick_LOAD_RELOAD_Msk
Definition: core_sc000.h:506
#define SysTick_CTRL_TICKINT_Msk
Definition: core_sc000.h:499
#define SysTick_CTRL_CLKSOURCE_Msk
Definition: core_sc000.h:496
#define SCB
Definition: core_sc000.h:663
#define NVIC
Definition: core_sc000.h:665
#define SysTick
Definition: core_sc000.h:664
#define __NVIC_PRIO_BITS
Definition: stm32f303xe.h:49
IRQn_Type
STM32F303xE devices Interrupt Number Definition, according to the selected device in Library_configur...
Definition: stm32f303xe.h:66
@ SysTick_IRQn
Definition: stm32f303xe.h:76
Structure type to access the Nested Vectored Interrupt Controller (NVIC).
Definition: core_armv8mbl.h:352
Structure type to access the System Control Block (SCB).
Definition: core_armv8mbl.h:382
Structure type to access the System Control and ID Register not in the SCB.
Definition: core_armv8mml.h:1010
Structure type to access the System Timer (SysTick).
Definition: core_armv8mbl.h:559
Union type to access the Application Program Status Register (APSR).
Definition: core_armv8mbl.h:234
Union type to access the Control Registers (CONTROL).
Definition: core_armv8mbl.h:321
Union type to access the Interrupt Program Status Register (IPSR).
Definition: core_armv8mbl.h:264
Union type to access the Special-Purpose Program Status Registers (xPSR).
Definition: core_armv8mbl.h:282