Macros
#define	ADC5_V1_1

#define	ADC_MULTIMODE_SUPPORT

#define	ADC_ISR_ADRDY_Pos (0U)

#define	ADC_ISR_ADRDY_Msk (0x1UL << ADC_ISR_ADRDY_Pos)

#define	ADC_ISR_ADRDY ADC_ISR_ADRDY_Msk

#define	ADC_ISR_EOSMP_Pos (1U)

#define	ADC_ISR_EOSMP_Msk (0x1UL << ADC_ISR_EOSMP_Pos)

#define	ADC_ISR_EOSMP ADC_ISR_EOSMP_Msk

#define	ADC_ISR_EOC_Pos (2U)

#define	ADC_ISR_EOC_Msk (0x1UL << ADC_ISR_EOC_Pos)

#define	ADC_ISR_EOC ADC_ISR_EOC_Msk

#define	ADC_ISR_EOS_Pos (3U)

#define	ADC_ISR_EOS_Msk (0x1UL << ADC_ISR_EOS_Pos)

#define	ADC_ISR_EOS ADC_ISR_EOS_Msk

#define	ADC_ISR_OVR_Pos (4U)

#define	ADC_ISR_OVR_Msk (0x1UL << ADC_ISR_OVR_Pos)

#define	ADC_ISR_OVR ADC_ISR_OVR_Msk

#define	ADC_ISR_JEOC_Pos (5U)

#define	ADC_ISR_JEOC_Msk (0x1UL << ADC_ISR_JEOC_Pos)

#define	ADC_ISR_JEOC ADC_ISR_JEOC_Msk

#define	ADC_ISR_JEOS_Pos (6U)

#define	ADC_ISR_JEOS_Msk (0x1UL << ADC_ISR_JEOS_Pos)

#define	ADC_ISR_JEOS ADC_ISR_JEOS_Msk

#define	ADC_ISR_AWD1_Pos (7U)

#define	ADC_ISR_AWD1_Msk (0x1UL << ADC_ISR_AWD1_Pos)

#define	ADC_ISR_AWD1 ADC_ISR_AWD1_Msk

#define	ADC_ISR_AWD2_Pos (8U)

#define	ADC_ISR_AWD2_Msk (0x1UL << ADC_ISR_AWD2_Pos)

#define	ADC_ISR_AWD2 ADC_ISR_AWD2_Msk

#define	ADC_ISR_AWD3_Pos (9U)

#define	ADC_ISR_AWD3_Msk (0x1UL << ADC_ISR_AWD3_Pos)

#define	ADC_ISR_AWD3 ADC_ISR_AWD3_Msk

#define	ADC_ISR_JQOVF_Pos (10U)

#define	ADC_ISR_JQOVF_Msk (0x1UL << ADC_ISR_JQOVF_Pos)

#define	ADC_ISR_JQOVF ADC_ISR_JQOVF_Msk

#define	ADC_ISR_ADRD (ADC_ISR_ADRDY)

#define	ADC_IER_ADRDYIE_Pos (0U)

#define	ADC_IER_ADRDYIE_Msk (0x1UL << ADC_IER_ADRDYIE_Pos)

#define	ADC_IER_ADRDYIE ADC_IER_ADRDYIE_Msk

#define	ADC_IER_EOSMPIE_Pos (1U)

#define	ADC_IER_EOSMPIE_Msk (0x1UL << ADC_IER_EOSMPIE_Pos)

#define	ADC_IER_EOSMPIE ADC_IER_EOSMPIE_Msk

#define	ADC_IER_EOCIE_Pos (2U)

#define	ADC_IER_EOCIE_Msk (0x1UL << ADC_IER_EOCIE_Pos)

#define	ADC_IER_EOCIE ADC_IER_EOCIE_Msk

#define	ADC_IER_EOSIE_Pos (3U)

#define	ADC_IER_EOSIE_Msk (0x1UL << ADC_IER_EOSIE_Pos)

#define	ADC_IER_EOSIE ADC_IER_EOSIE_Msk

#define	ADC_IER_OVRIE_Pos (4U)

#define	ADC_IER_OVRIE_Msk (0x1UL << ADC_IER_OVRIE_Pos)

#define	ADC_IER_OVRIE ADC_IER_OVRIE_Msk

#define	ADC_IER_JEOCIE_Pos (5U)

#define	ADC_IER_JEOCIE_Msk (0x1UL << ADC_IER_JEOCIE_Pos)

#define	ADC_IER_JEOCIE ADC_IER_JEOCIE_Msk

#define	ADC_IER_JEOSIE_Pos (6U)

#define	ADC_IER_JEOSIE_Msk (0x1UL << ADC_IER_JEOSIE_Pos)

#define	ADC_IER_JEOSIE ADC_IER_JEOSIE_Msk

#define	ADC_IER_AWD1IE_Pos (7U)

#define	ADC_IER_AWD1IE_Msk (0x1UL << ADC_IER_AWD1IE_Pos)

#define	ADC_IER_AWD1IE ADC_IER_AWD1IE_Msk

#define	ADC_IER_AWD2IE_Pos (8U)

#define	ADC_IER_AWD2IE_Msk (0x1UL << ADC_IER_AWD2IE_Pos)

#define	ADC_IER_AWD2IE ADC_IER_AWD2IE_Msk

#define	ADC_IER_AWD3IE_Pos (9U)

#define	ADC_IER_AWD3IE_Msk (0x1UL << ADC_IER_AWD3IE_Pos)

#define	ADC_IER_AWD3IE ADC_IER_AWD3IE_Msk

#define	ADC_IER_JQOVFIE_Pos (10U)

#define	ADC_IER_JQOVFIE_Msk (0x1UL << ADC_IER_JQOVFIE_Pos)

#define	ADC_IER_JQOVFIE ADC_IER_JQOVFIE_Msk

#define	ADC_IER_RDY (ADC_IER_ADRDYIE)

#define	ADC_IER_EOSMP (ADC_IER_EOSMPIE)

#define	ADC_IER_EOC (ADC_IER_EOCIE)

#define	ADC_IER_EOS (ADC_IER_EOSIE)

#define	ADC_IER_OVR (ADC_IER_OVRIE)

#define	ADC_IER_JEOC (ADC_IER_JEOCIE)

#define	ADC_IER_JEOS (ADC_IER_JEOSIE)

#define	ADC_IER_AWD1 (ADC_IER_AWD1IE)

#define	ADC_IER_AWD2 (ADC_IER_AWD2IE)

#define	ADC_IER_AWD3 (ADC_IER_AWD3IE)

#define	ADC_IER_JQOVF (ADC_IER_JQOVFIE)

#define	ADC_CR_ADEN_Pos (0U)

#define	ADC_CR_ADEN_Msk (0x1UL << ADC_CR_ADEN_Pos)

#define	ADC_CR_ADEN ADC_CR_ADEN_Msk

#define	ADC_CR_ADDIS_Pos (1U)

#define	ADC_CR_ADDIS_Msk (0x1UL << ADC_CR_ADDIS_Pos)

#define	ADC_CR_ADDIS ADC_CR_ADDIS_Msk

#define	ADC_CR_ADSTART_Pos (2U)

#define	ADC_CR_ADSTART_Msk (0x1UL << ADC_CR_ADSTART_Pos)

#define	ADC_CR_ADSTART ADC_CR_ADSTART_Msk

#define	ADC_CR_JADSTART_Pos (3U)

#define	ADC_CR_JADSTART_Msk (0x1UL << ADC_CR_JADSTART_Pos)

#define	ADC_CR_JADSTART ADC_CR_JADSTART_Msk

#define	ADC_CR_ADSTP_Pos (4U)

#define	ADC_CR_ADSTP_Msk (0x1UL << ADC_CR_ADSTP_Pos)

#define	ADC_CR_ADSTP ADC_CR_ADSTP_Msk

#define	ADC_CR_JADSTP_Pos (5U)

#define	ADC_CR_JADSTP_Msk (0x1UL << ADC_CR_JADSTP_Pos)

#define	ADC_CR_JADSTP ADC_CR_JADSTP_Msk

#define	ADC_CR_ADVREGEN_Pos (28U)

#define	ADC_CR_ADVREGEN_Msk (0x3UL << ADC_CR_ADVREGEN_Pos)

#define	ADC_CR_ADVREGEN ADC_CR_ADVREGEN_Msk

#define	ADC_CR_ADVREGEN_0 (0x1UL << ADC_CR_ADVREGEN_Pos)

#define	ADC_CR_ADVREGEN_1 (0x2UL << ADC_CR_ADVREGEN_Pos)

#define	ADC_CR_ADCALDIF_Pos (30U)

#define	ADC_CR_ADCALDIF_Msk (0x1UL << ADC_CR_ADCALDIF_Pos)

#define	ADC_CR_ADCALDIF ADC_CR_ADCALDIF_Msk

#define	ADC_CR_ADCAL_Pos (31U)

#define	ADC_CR_ADCAL_Msk (0x1UL << ADC_CR_ADCAL_Pos)

#define	ADC_CR_ADCAL ADC_CR_ADCAL_Msk

#define	ADC_CFGR_DMAEN_Pos (0U)

#define	ADC_CFGR_DMAEN_Msk (0x1UL << ADC_CFGR_DMAEN_Pos)

#define	ADC_CFGR_DMAEN ADC_CFGR_DMAEN_Msk

#define	ADC_CFGR_DMACFG_Pos (1U)

#define	ADC_CFGR_DMACFG_Msk (0x1UL << ADC_CFGR_DMACFG_Pos)

#define	ADC_CFGR_DMACFG ADC_CFGR_DMACFG_Msk

#define	ADC_CFGR_RES_Pos (3U)

#define	ADC_CFGR_RES_Msk (0x3UL << ADC_CFGR_RES_Pos)

#define	ADC_CFGR_RES ADC_CFGR_RES_Msk

#define	ADC_CFGR_RES_0 (0x1UL << ADC_CFGR_RES_Pos)

#define	ADC_CFGR_RES_1 (0x2UL << ADC_CFGR_RES_Pos)

#define	ADC_CFGR_ALIGN_Pos (5U)

#define	ADC_CFGR_ALIGN_Msk (0x1UL << ADC_CFGR_ALIGN_Pos)

#define	ADC_CFGR_ALIGN ADC_CFGR_ALIGN_Msk

#define	ADC_CFGR_EXTSEL_Pos (6U)

#define	ADC_CFGR_EXTSEL_Msk (0xFUL << ADC_CFGR_EXTSEL_Pos)

#define	ADC_CFGR_EXTSEL ADC_CFGR_EXTSEL_Msk

#define	ADC_CFGR_EXTSEL_0 (0x1UL << ADC_CFGR_EXTSEL_Pos)

#define	ADC_CFGR_EXTSEL_1 (0x2UL << ADC_CFGR_EXTSEL_Pos)

#define	ADC_CFGR_EXTSEL_2 (0x4UL << ADC_CFGR_EXTSEL_Pos)

#define	ADC_CFGR_EXTSEL_3 (0x8UL << ADC_CFGR_EXTSEL_Pos)

#define	ADC_CFGR_EXTEN_Pos (10U)

#define	ADC_CFGR_EXTEN_Msk (0x3UL << ADC_CFGR_EXTEN_Pos)

#define	ADC_CFGR_EXTEN ADC_CFGR_EXTEN_Msk

#define	ADC_CFGR_EXTEN_0 (0x1UL << ADC_CFGR_EXTEN_Pos)

#define	ADC_CFGR_EXTEN_1 (0x2UL << ADC_CFGR_EXTEN_Pos)

#define	ADC_CFGR_OVRMOD_Pos (12U)

#define	ADC_CFGR_OVRMOD_Msk (0x1UL << ADC_CFGR_OVRMOD_Pos)

#define	ADC_CFGR_OVRMOD ADC_CFGR_OVRMOD_Msk

#define	ADC_CFGR_CONT_Pos (13U)

#define	ADC_CFGR_CONT_Msk (0x1UL << ADC_CFGR_CONT_Pos)

#define	ADC_CFGR_CONT ADC_CFGR_CONT_Msk

#define	ADC_CFGR_AUTDLY_Pos (14U)

#define	ADC_CFGR_AUTDLY_Msk (0x1UL << ADC_CFGR_AUTDLY_Pos)

#define	ADC_CFGR_AUTDLY ADC_CFGR_AUTDLY_Msk

#define	ADC_CFGR_DISCEN_Pos (16U)

#define	ADC_CFGR_DISCEN_Msk (0x1UL << ADC_CFGR_DISCEN_Pos)

#define	ADC_CFGR_DISCEN ADC_CFGR_DISCEN_Msk

#define	ADC_CFGR_DISCNUM_Pos (17U)

#define	ADC_CFGR_DISCNUM_Msk (0x7UL << ADC_CFGR_DISCNUM_Pos)

#define	ADC_CFGR_DISCNUM ADC_CFGR_DISCNUM_Msk

#define	ADC_CFGR_DISCNUM_0 (0x1UL << ADC_CFGR_DISCNUM_Pos)

#define	ADC_CFGR_DISCNUM_1 (0x2UL << ADC_CFGR_DISCNUM_Pos)

#define	ADC_CFGR_DISCNUM_2 (0x4UL << ADC_CFGR_DISCNUM_Pos)

#define	ADC_CFGR_JDISCEN_Pos (20U)

#define	ADC_CFGR_JDISCEN_Msk (0x1UL << ADC_CFGR_JDISCEN_Pos)

#define	ADC_CFGR_JDISCEN ADC_CFGR_JDISCEN_Msk

#define	ADC_CFGR_JQM_Pos (21U)

#define	ADC_CFGR_JQM_Msk (0x1UL << ADC_CFGR_JQM_Pos)

#define	ADC_CFGR_JQM ADC_CFGR_JQM_Msk

#define	ADC_CFGR_AWD1SGL_Pos (22U)

#define	ADC_CFGR_AWD1SGL_Msk (0x1UL << ADC_CFGR_AWD1SGL_Pos)

#define	ADC_CFGR_AWD1SGL ADC_CFGR_AWD1SGL_Msk

#define	ADC_CFGR_AWD1EN_Pos (23U)

#define	ADC_CFGR_AWD1EN_Msk (0x1UL << ADC_CFGR_AWD1EN_Pos)

#define	ADC_CFGR_AWD1EN ADC_CFGR_AWD1EN_Msk

#define	ADC_CFGR_JAWD1EN_Pos (24U)

#define	ADC_CFGR_JAWD1EN_Msk (0x1UL << ADC_CFGR_JAWD1EN_Pos)

#define	ADC_CFGR_JAWD1EN ADC_CFGR_JAWD1EN_Msk

#define	ADC_CFGR_JAUTO_Pos (25U)

#define	ADC_CFGR_JAUTO_Msk (0x1UL << ADC_CFGR_JAUTO_Pos)

#define	ADC_CFGR_JAUTO ADC_CFGR_JAUTO_Msk

#define	ADC_CFGR_AWD1CH_Pos (26U)

#define	ADC_CFGR_AWD1CH_Msk (0x1FUL << ADC_CFGR_AWD1CH_Pos)

#define	ADC_CFGR_AWD1CH ADC_CFGR_AWD1CH_Msk

#define	ADC_CFGR_AWD1CH_0 (0x01UL << ADC_CFGR_AWD1CH_Pos)

#define	ADC_CFGR_AWD1CH_1 (0x02UL << ADC_CFGR_AWD1CH_Pos)

#define	ADC_CFGR_AWD1CH_2 (0x04UL << ADC_CFGR_AWD1CH_Pos)

#define	ADC_CFGR_AWD1CH_3 (0x08UL << ADC_CFGR_AWD1CH_Pos)

#define	ADC_CFGR_AWD1CH_4 (0x10UL << ADC_CFGR_AWD1CH_Pos)

#define	ADC_CFGR_AUTOFF_Pos (15U)

#define	ADC_CFGR_AUTOFF_Msk (0x1UL << ADC_CFGR_AUTOFF_Pos)

#define	ADC_CFGR_AUTOFF ADC_CFGR_AUTOFF_Msk

#define	ADC_SMPR1_SMP0_Pos (0U)

#define	ADC_SMPR1_SMP0_Msk (0x7UL << ADC_SMPR1_SMP0_Pos)

#define	ADC_SMPR1_SMP0 ADC_SMPR1_SMP0_Msk

#define	ADC_SMPR1_SMP0_0 (0x1UL << ADC_SMPR1_SMP0_Pos)

#define	ADC_SMPR1_SMP0_1 (0x2UL << ADC_SMPR1_SMP0_Pos)

#define	ADC_SMPR1_SMP0_2 (0x4UL << ADC_SMPR1_SMP0_Pos)

#define	ADC_SMPR1_SMP1_Pos (3U)

#define	ADC_SMPR1_SMP1_Msk (0x7UL << ADC_SMPR1_SMP1_Pos)

#define	ADC_SMPR1_SMP1 ADC_SMPR1_SMP1_Msk

#define	ADC_SMPR1_SMP1_0 (0x1UL << ADC_SMPR1_SMP1_Pos)

#define	ADC_SMPR1_SMP1_1 (0x2UL << ADC_SMPR1_SMP1_Pos)

#define	ADC_SMPR1_SMP1_2 (0x4UL << ADC_SMPR1_SMP1_Pos)

#define	ADC_SMPR1_SMP2_Pos (6U)

#define	ADC_SMPR1_SMP2_Msk (0x7UL << ADC_SMPR1_SMP2_Pos)

#define	ADC_SMPR1_SMP2 ADC_SMPR1_SMP2_Msk

#define	ADC_SMPR1_SMP2_0 (0x1UL << ADC_SMPR1_SMP2_Pos)

#define	ADC_SMPR1_SMP2_1 (0x2UL << ADC_SMPR1_SMP2_Pos)

#define	ADC_SMPR1_SMP2_2 (0x4UL << ADC_SMPR1_SMP2_Pos)

#define	ADC_SMPR1_SMP3_Pos (9U)

#define	ADC_SMPR1_SMP3_Msk (0x7UL << ADC_SMPR1_SMP3_Pos)

#define	ADC_SMPR1_SMP3 ADC_SMPR1_SMP3_Msk

#define	ADC_SMPR1_SMP3_0 (0x1UL << ADC_SMPR1_SMP3_Pos)

#define	ADC_SMPR1_SMP3_1 (0x2UL << ADC_SMPR1_SMP3_Pos)

#define	ADC_SMPR1_SMP3_2 (0x4UL << ADC_SMPR1_SMP3_Pos)

#define	ADC_SMPR1_SMP4_Pos (12U)

#define	ADC_SMPR1_SMP4_Msk (0x7UL << ADC_SMPR1_SMP4_Pos)

#define	ADC_SMPR1_SMP4 ADC_SMPR1_SMP4_Msk

#define	ADC_SMPR1_SMP4_0 (0x1UL << ADC_SMPR1_SMP4_Pos)

#define	ADC_SMPR1_SMP4_1 (0x2UL << ADC_SMPR1_SMP4_Pos)

#define	ADC_SMPR1_SMP4_2 (0x4UL << ADC_SMPR1_SMP4_Pos)

#define	ADC_SMPR1_SMP5_Pos (15U)

#define	ADC_SMPR1_SMP5_Msk (0x7UL << ADC_SMPR1_SMP5_Pos)

#define	ADC_SMPR1_SMP5 ADC_SMPR1_SMP5_Msk

#define	ADC_SMPR1_SMP5_0 (0x1UL << ADC_SMPR1_SMP5_Pos)

#define	ADC_SMPR1_SMP5_1 (0x2UL << ADC_SMPR1_SMP5_Pos)

#define	ADC_SMPR1_SMP5_2 (0x4UL << ADC_SMPR1_SMP5_Pos)

#define	ADC_SMPR1_SMP6_Pos (18U)

#define	ADC_SMPR1_SMP6_Msk (0x7UL << ADC_SMPR1_SMP6_Pos)

#define	ADC_SMPR1_SMP6 ADC_SMPR1_SMP6_Msk

#define	ADC_SMPR1_SMP6_0 (0x1UL << ADC_SMPR1_SMP6_Pos)

#define	ADC_SMPR1_SMP6_1 (0x2UL << ADC_SMPR1_SMP6_Pos)

#define	ADC_SMPR1_SMP6_2 (0x4UL << ADC_SMPR1_SMP6_Pos)

#define	ADC_SMPR1_SMP7_Pos (21U)

#define	ADC_SMPR1_SMP7_Msk (0x7UL << ADC_SMPR1_SMP7_Pos)

#define	ADC_SMPR1_SMP7 ADC_SMPR1_SMP7_Msk

#define	ADC_SMPR1_SMP7_0 (0x1UL << ADC_SMPR1_SMP7_Pos)

#define	ADC_SMPR1_SMP7_1 (0x2UL << ADC_SMPR1_SMP7_Pos)

#define	ADC_SMPR1_SMP7_2 (0x4UL << ADC_SMPR1_SMP7_Pos)

#define	ADC_SMPR1_SMP8_Pos (24U)

#define	ADC_SMPR1_SMP8_Msk (0x7UL << ADC_SMPR1_SMP8_Pos)

#define	ADC_SMPR1_SMP8 ADC_SMPR1_SMP8_Msk

#define	ADC_SMPR1_SMP8_0 (0x1UL << ADC_SMPR1_SMP8_Pos)

#define	ADC_SMPR1_SMP8_1 (0x2UL << ADC_SMPR1_SMP8_Pos)

#define	ADC_SMPR1_SMP8_2 (0x4UL << ADC_SMPR1_SMP8_Pos)

#define	ADC_SMPR1_SMP9_Pos (27U)

#define	ADC_SMPR1_SMP9_Msk (0x7UL << ADC_SMPR1_SMP9_Pos)

#define	ADC_SMPR1_SMP9 ADC_SMPR1_SMP9_Msk

#define	ADC_SMPR1_SMP9_0 (0x1UL << ADC_SMPR1_SMP9_Pos)

#define	ADC_SMPR1_SMP9_1 (0x2UL << ADC_SMPR1_SMP9_Pos)

#define	ADC_SMPR1_SMP9_2 (0x4UL << ADC_SMPR1_SMP9_Pos)

#define	ADC_SMPR2_SMP10_Pos (0U)

#define	ADC_SMPR2_SMP10_Msk (0x7UL << ADC_SMPR2_SMP10_Pos)

#define	ADC_SMPR2_SMP10 ADC_SMPR2_SMP10_Msk

#define	ADC_SMPR2_SMP10_0 (0x1UL << ADC_SMPR2_SMP10_Pos)

#define	ADC_SMPR2_SMP10_1 (0x2UL << ADC_SMPR2_SMP10_Pos)

#define	ADC_SMPR2_SMP10_2 (0x4UL << ADC_SMPR2_SMP10_Pos)

#define	ADC_SMPR2_SMP11_Pos (3U)

#define	ADC_SMPR2_SMP11_Msk (0x7UL << ADC_SMPR2_SMP11_Pos)

#define	ADC_SMPR2_SMP11 ADC_SMPR2_SMP11_Msk

#define	ADC_SMPR2_SMP11_0 (0x1UL << ADC_SMPR2_SMP11_Pos)

#define	ADC_SMPR2_SMP11_1 (0x2UL << ADC_SMPR2_SMP11_Pos)

#define	ADC_SMPR2_SMP11_2 (0x4UL << ADC_SMPR2_SMP11_Pos)

#define	ADC_SMPR2_SMP12_Pos (6U)

#define	ADC_SMPR2_SMP12_Msk (0x7UL << ADC_SMPR2_SMP12_Pos)

#define	ADC_SMPR2_SMP12 ADC_SMPR2_SMP12_Msk

#define	ADC_SMPR2_SMP12_0 (0x1UL << ADC_SMPR2_SMP12_Pos)

#define	ADC_SMPR2_SMP12_1 (0x2UL << ADC_SMPR2_SMP12_Pos)

#define	ADC_SMPR2_SMP12_2 (0x4UL << ADC_SMPR2_SMP12_Pos)

#define	ADC_SMPR2_SMP13_Pos (9U)

#define	ADC_SMPR2_SMP13_Msk (0x7UL << ADC_SMPR2_SMP13_Pos)

#define	ADC_SMPR2_SMP13 ADC_SMPR2_SMP13_Msk

#define	ADC_SMPR2_SMP13_0 (0x1UL << ADC_SMPR2_SMP13_Pos)

#define	ADC_SMPR2_SMP13_1 (0x2UL << ADC_SMPR2_SMP13_Pos)

#define	ADC_SMPR2_SMP13_2 (0x4UL << ADC_SMPR2_SMP13_Pos)

#define	ADC_SMPR2_SMP14_Pos (12U)

#define	ADC_SMPR2_SMP14_Msk (0x7UL << ADC_SMPR2_SMP14_Pos)

#define	ADC_SMPR2_SMP14 ADC_SMPR2_SMP14_Msk

#define	ADC_SMPR2_SMP14_0 (0x1UL << ADC_SMPR2_SMP14_Pos)

#define	ADC_SMPR2_SMP14_1 (0x2UL << ADC_SMPR2_SMP14_Pos)

#define	ADC_SMPR2_SMP14_2 (0x4UL << ADC_SMPR2_SMP14_Pos)

#define	ADC_SMPR2_SMP15_Pos (15U)

#define	ADC_SMPR2_SMP15_Msk (0x7UL << ADC_SMPR2_SMP15_Pos)

#define	ADC_SMPR2_SMP15 ADC_SMPR2_SMP15_Msk

#define	ADC_SMPR2_SMP15_0 (0x1UL << ADC_SMPR2_SMP15_Pos)

#define	ADC_SMPR2_SMP15_1 (0x2UL << ADC_SMPR2_SMP15_Pos)

#define	ADC_SMPR2_SMP15_2 (0x4UL << ADC_SMPR2_SMP15_Pos)

#define	ADC_SMPR2_SMP16_Pos (18U)

#define	ADC_SMPR2_SMP16_Msk (0x7UL << ADC_SMPR2_SMP16_Pos)

#define	ADC_SMPR2_SMP16 ADC_SMPR2_SMP16_Msk

#define	ADC_SMPR2_SMP16_0 (0x1UL << ADC_SMPR2_SMP16_Pos)

#define	ADC_SMPR2_SMP16_1 (0x2UL << ADC_SMPR2_SMP16_Pos)

#define	ADC_SMPR2_SMP16_2 (0x4UL << ADC_SMPR2_SMP16_Pos)

#define	ADC_SMPR2_SMP17_Pos (21U)

#define	ADC_SMPR2_SMP17_Msk (0x7UL << ADC_SMPR2_SMP17_Pos)

#define	ADC_SMPR2_SMP17 ADC_SMPR2_SMP17_Msk

#define	ADC_SMPR2_SMP17_0 (0x1UL << ADC_SMPR2_SMP17_Pos)

#define	ADC_SMPR2_SMP17_1 (0x2UL << ADC_SMPR2_SMP17_Pos)

#define	ADC_SMPR2_SMP17_2 (0x4UL << ADC_SMPR2_SMP17_Pos)

#define	ADC_SMPR2_SMP18_Pos (24U)

#define	ADC_SMPR2_SMP18_Msk (0x7UL << ADC_SMPR2_SMP18_Pos)

#define	ADC_SMPR2_SMP18 ADC_SMPR2_SMP18_Msk

#define	ADC_SMPR2_SMP18_0 (0x1UL << ADC_SMPR2_SMP18_Pos)

#define	ADC_SMPR2_SMP18_1 (0x2UL << ADC_SMPR2_SMP18_Pos)

#define	ADC_SMPR2_SMP18_2 (0x4UL << ADC_SMPR2_SMP18_Pos)

#define	ADC_TR1_LT1_Pos (0U)

#define	ADC_TR1_LT1_Msk (0xFFFUL << ADC_TR1_LT1_Pos)

#define	ADC_TR1_LT1 ADC_TR1_LT1_Msk

#define	ADC_TR1_LT1_0 (0x001UL << ADC_TR1_LT1_Pos)

#define	ADC_TR1_LT1_1 (0x002UL << ADC_TR1_LT1_Pos)

#define	ADC_TR1_LT1_2 (0x004UL << ADC_TR1_LT1_Pos)

#define	ADC_TR1_LT1_3 (0x008UL << ADC_TR1_LT1_Pos)

#define	ADC_TR1_LT1_4 (0x010UL << ADC_TR1_LT1_Pos)

#define	ADC_TR1_LT1_5 (0x020UL << ADC_TR1_LT1_Pos)

#define	ADC_TR1_LT1_6 (0x040UL << ADC_TR1_LT1_Pos)

#define	ADC_TR1_LT1_7 (0x080UL << ADC_TR1_LT1_Pos)

#define	ADC_TR1_LT1_8 (0x100UL << ADC_TR1_LT1_Pos)

#define	ADC_TR1_LT1_9 (0x200UL << ADC_TR1_LT1_Pos)

#define	ADC_TR1_LT1_10 (0x400UL << ADC_TR1_LT1_Pos)

#define	ADC_TR1_LT1_11 (0x800UL << ADC_TR1_LT1_Pos)

#define	ADC_TR1_HT1_Pos (16U)

#define	ADC_TR1_HT1_Msk (0xFFFUL << ADC_TR1_HT1_Pos)

#define	ADC_TR1_HT1 ADC_TR1_HT1_Msk

#define	ADC_TR1_HT1_0 (0x001UL << ADC_TR1_HT1_Pos)

#define	ADC_TR1_HT1_1 (0x002UL << ADC_TR1_HT1_Pos)

#define	ADC_TR1_HT1_2 (0x004UL << ADC_TR1_HT1_Pos)

#define	ADC_TR1_HT1_3 (0x008UL << ADC_TR1_HT1_Pos)

#define	ADC_TR1_HT1_4 (0x010UL << ADC_TR1_HT1_Pos)

#define	ADC_TR1_HT1_5 (0x020UL << ADC_TR1_HT1_Pos)

#define	ADC_TR1_HT1_6 (0x040UL << ADC_TR1_HT1_Pos)

#define	ADC_TR1_HT1_7 (0x080UL << ADC_TR1_HT1_Pos)

#define	ADC_TR1_HT1_8 (0x100UL << ADC_TR1_HT1_Pos)

#define	ADC_TR1_HT1_9 (0x200UL << ADC_TR1_HT1_Pos)

#define	ADC_TR1_HT1_10 (0x400UL << ADC_TR1_HT1_Pos)

#define	ADC_TR1_HT1_11 (0x800UL << ADC_TR1_HT1_Pos)

#define	ADC_TR2_LT2_Pos (0U)

#define	ADC_TR2_LT2_Msk (0xFFUL << ADC_TR2_LT2_Pos)

#define	ADC_TR2_LT2 ADC_TR2_LT2_Msk

#define	ADC_TR2_LT2_0 (0x01UL << ADC_TR2_LT2_Pos)

#define	ADC_TR2_LT2_1 (0x02UL << ADC_TR2_LT2_Pos)

#define	ADC_TR2_LT2_2 (0x04UL << ADC_TR2_LT2_Pos)

#define	ADC_TR2_LT2_3 (0x08UL << ADC_TR2_LT2_Pos)

#define	ADC_TR2_LT2_4 (0x10UL << ADC_TR2_LT2_Pos)

#define	ADC_TR2_LT2_5 (0x20UL << ADC_TR2_LT2_Pos)

#define	ADC_TR2_LT2_6 (0x40UL << ADC_TR2_LT2_Pos)

#define	ADC_TR2_LT2_7 (0x80UL << ADC_TR2_LT2_Pos)

#define	ADC_TR2_HT2_Pos (16U)

#define	ADC_TR2_HT2_Msk (0xFFUL << ADC_TR2_HT2_Pos)

#define	ADC_TR2_HT2 ADC_TR2_HT2_Msk

#define	ADC_TR2_HT2_0 (0x01UL << ADC_TR2_HT2_Pos)

#define	ADC_TR2_HT2_1 (0x02UL << ADC_TR2_HT2_Pos)

#define	ADC_TR2_HT2_2 (0x04UL << ADC_TR2_HT2_Pos)

#define	ADC_TR2_HT2_3 (0x08UL << ADC_TR2_HT2_Pos)

#define	ADC_TR2_HT2_4 (0x10UL << ADC_TR2_HT2_Pos)

#define	ADC_TR2_HT2_5 (0x20UL << ADC_TR2_HT2_Pos)

#define	ADC_TR2_HT2_6 (0x40UL << ADC_TR2_HT2_Pos)

#define	ADC_TR2_HT2_7 (0x80UL << ADC_TR2_HT2_Pos)

#define	ADC_TR3_LT3_Pos (0U)

#define	ADC_TR3_LT3_Msk (0xFFUL << ADC_TR3_LT3_Pos)

#define	ADC_TR3_LT3 ADC_TR3_LT3_Msk

#define	ADC_TR3_LT3_0 (0x01UL << ADC_TR3_LT3_Pos)

#define	ADC_TR3_LT3_1 (0x02UL << ADC_TR3_LT3_Pos)

#define	ADC_TR3_LT3_2 (0x04UL << ADC_TR3_LT3_Pos)

#define	ADC_TR3_LT3_3 (0x08UL << ADC_TR3_LT3_Pos)

#define	ADC_TR3_LT3_4 (0x10UL << ADC_TR3_LT3_Pos)

#define	ADC_TR3_LT3_5 (0x20UL << ADC_TR3_LT3_Pos)

#define	ADC_TR3_LT3_6 (0x40UL << ADC_TR3_LT3_Pos)

#define	ADC_TR3_LT3_7 (0x80UL << ADC_TR3_LT3_Pos)

#define	ADC_TR3_HT3_Pos (16U)

#define	ADC_TR3_HT3_Msk (0xFFUL << ADC_TR3_HT3_Pos)

#define	ADC_TR3_HT3 ADC_TR3_HT3_Msk

#define	ADC_TR3_HT3_0 (0x01UL << ADC_TR3_HT3_Pos)

#define	ADC_TR3_HT3_1 (0x02UL << ADC_TR3_HT3_Pos)

#define	ADC_TR3_HT3_2 (0x04UL << ADC_TR3_HT3_Pos)

#define	ADC_TR3_HT3_3 (0x08UL << ADC_TR3_HT3_Pos)

#define	ADC_TR3_HT3_4 (0x10UL << ADC_TR3_HT3_Pos)

#define	ADC_TR3_HT3_5 (0x20UL << ADC_TR3_HT3_Pos)

#define	ADC_TR3_HT3_6 (0x40UL << ADC_TR3_HT3_Pos)

#define	ADC_TR3_HT3_7 (0x80UL << ADC_TR3_HT3_Pos)

#define	ADC_SQR1_L_Pos (0U)

#define	ADC_SQR1_L_Msk (0xFUL << ADC_SQR1_L_Pos)

#define	ADC_SQR1_L ADC_SQR1_L_Msk

#define	ADC_SQR1_L_0 (0x1UL << ADC_SQR1_L_Pos)

#define	ADC_SQR1_L_1 (0x2UL << ADC_SQR1_L_Pos)

#define	ADC_SQR1_L_2 (0x4UL << ADC_SQR1_L_Pos)

#define	ADC_SQR1_L_3 (0x8UL << ADC_SQR1_L_Pos)

#define	ADC_SQR1_SQ1_Pos (6U)

#define	ADC_SQR1_SQ1_Msk (0x1FUL << ADC_SQR1_SQ1_Pos)

#define	ADC_SQR1_SQ1 ADC_SQR1_SQ1_Msk

#define	ADC_SQR1_SQ1_0 (0x01UL << ADC_SQR1_SQ1_Pos)

#define	ADC_SQR1_SQ1_1 (0x02UL << ADC_SQR1_SQ1_Pos)

#define	ADC_SQR1_SQ1_2 (0x04UL << ADC_SQR1_SQ1_Pos)

#define	ADC_SQR1_SQ1_3 (0x08UL << ADC_SQR1_SQ1_Pos)

#define	ADC_SQR1_SQ1_4 (0x10UL << ADC_SQR1_SQ1_Pos)

#define	ADC_SQR1_SQ2_Pos (12U)

#define	ADC_SQR1_SQ2_Msk (0x1FUL << ADC_SQR1_SQ2_Pos)

#define	ADC_SQR1_SQ2 ADC_SQR1_SQ2_Msk

#define	ADC_SQR1_SQ2_0 (0x01UL << ADC_SQR1_SQ2_Pos)

#define	ADC_SQR1_SQ2_1 (0x02UL << ADC_SQR1_SQ2_Pos)

#define	ADC_SQR1_SQ2_2 (0x04UL << ADC_SQR1_SQ2_Pos)

#define	ADC_SQR1_SQ2_3 (0x08UL << ADC_SQR1_SQ2_Pos)

#define	ADC_SQR1_SQ2_4 (0x10UL << ADC_SQR1_SQ2_Pos)

#define	ADC_SQR1_SQ3_Pos (18U)

#define	ADC_SQR1_SQ3_Msk (0x1FUL << ADC_SQR1_SQ3_Pos)

#define	ADC_SQR1_SQ3 ADC_SQR1_SQ3_Msk

#define	ADC_SQR1_SQ3_0 (0x01UL << ADC_SQR1_SQ3_Pos)

#define	ADC_SQR1_SQ3_1 (0x02UL << ADC_SQR1_SQ3_Pos)

#define	ADC_SQR1_SQ3_2 (0x04UL << ADC_SQR1_SQ3_Pos)

#define	ADC_SQR1_SQ3_3 (0x08UL << ADC_SQR1_SQ3_Pos)

#define	ADC_SQR1_SQ3_4 (0x10UL << ADC_SQR1_SQ3_Pos)

#define	ADC_SQR1_SQ4_Pos (24U)

#define	ADC_SQR1_SQ4_Msk (0x1FUL << ADC_SQR1_SQ4_Pos)

#define	ADC_SQR1_SQ4 ADC_SQR1_SQ4_Msk

#define	ADC_SQR1_SQ4_0 (0x01UL << ADC_SQR1_SQ4_Pos)

#define	ADC_SQR1_SQ4_1 (0x02UL << ADC_SQR1_SQ4_Pos)

#define	ADC_SQR1_SQ4_2 (0x04UL << ADC_SQR1_SQ4_Pos)

#define	ADC_SQR1_SQ4_3 (0x08UL << ADC_SQR1_SQ4_Pos)

#define	ADC_SQR1_SQ4_4 (0x10UL << ADC_SQR1_SQ4_Pos)

#define	ADC_SQR2_SQ5_Pos (0U)

#define	ADC_SQR2_SQ5_Msk (0x1FUL << ADC_SQR2_SQ5_Pos)

#define	ADC_SQR2_SQ5 ADC_SQR2_SQ5_Msk

#define	ADC_SQR2_SQ5_0 (0x01UL << ADC_SQR2_SQ5_Pos)

#define	ADC_SQR2_SQ5_1 (0x02UL << ADC_SQR2_SQ5_Pos)

#define	ADC_SQR2_SQ5_2 (0x04UL << ADC_SQR2_SQ5_Pos)

#define	ADC_SQR2_SQ5_3 (0x08UL << ADC_SQR2_SQ5_Pos)

#define	ADC_SQR2_SQ5_4 (0x10UL << ADC_SQR2_SQ5_Pos)

#define	ADC_SQR2_SQ6_Pos (6U)

#define	ADC_SQR2_SQ6_Msk (0x1FUL << ADC_SQR2_SQ6_Pos)

#define	ADC_SQR2_SQ6 ADC_SQR2_SQ6_Msk

#define	ADC_SQR2_SQ6_0 (0x01UL << ADC_SQR2_SQ6_Pos)

#define	ADC_SQR2_SQ6_1 (0x02UL << ADC_SQR2_SQ6_Pos)

#define	ADC_SQR2_SQ6_2 (0x04UL << ADC_SQR2_SQ6_Pos)

#define	ADC_SQR2_SQ6_3 (0x08UL << ADC_SQR2_SQ6_Pos)

#define	ADC_SQR2_SQ6_4 (0x10UL << ADC_SQR2_SQ6_Pos)

#define	ADC_SQR2_SQ7_Pos (12U)

#define	ADC_SQR2_SQ7_Msk (0x1FUL << ADC_SQR2_SQ7_Pos)

#define	ADC_SQR2_SQ7 ADC_SQR2_SQ7_Msk

#define	ADC_SQR2_SQ7_0 (0x01UL << ADC_SQR2_SQ7_Pos)

#define	ADC_SQR2_SQ7_1 (0x02UL << ADC_SQR2_SQ7_Pos)

#define	ADC_SQR2_SQ7_2 (0x04UL << ADC_SQR2_SQ7_Pos)

#define	ADC_SQR2_SQ7_3 (0x08UL << ADC_SQR2_SQ7_Pos)

#define	ADC_SQR2_SQ7_4 (0x10UL << ADC_SQR2_SQ7_Pos)

#define	ADC_SQR2_SQ8_Pos (18U)

#define	ADC_SQR2_SQ8_Msk (0x1FUL << ADC_SQR2_SQ8_Pos)

#define	ADC_SQR2_SQ8 ADC_SQR2_SQ8_Msk

#define	ADC_SQR2_SQ8_0 (0x01UL << ADC_SQR2_SQ8_Pos)

#define	ADC_SQR2_SQ8_1 (0x02UL << ADC_SQR2_SQ8_Pos)

#define	ADC_SQR2_SQ8_2 (0x04UL << ADC_SQR2_SQ8_Pos)

#define	ADC_SQR2_SQ8_3 (0x08UL << ADC_SQR2_SQ8_Pos)

#define	ADC_SQR2_SQ8_4 (0x10UL << ADC_SQR2_SQ8_Pos)

#define	ADC_SQR2_SQ9_Pos (24U)

#define	ADC_SQR2_SQ9_Msk (0x1FUL << ADC_SQR2_SQ9_Pos)

#define	ADC_SQR2_SQ9 ADC_SQR2_SQ9_Msk

#define	ADC_SQR2_SQ9_0 (0x01UL << ADC_SQR2_SQ9_Pos)

#define	ADC_SQR2_SQ9_1 (0x02UL << ADC_SQR2_SQ9_Pos)

#define	ADC_SQR2_SQ9_2 (0x04UL << ADC_SQR2_SQ9_Pos)

#define	ADC_SQR2_SQ9_3 (0x08UL << ADC_SQR2_SQ9_Pos)

#define	ADC_SQR2_SQ9_4 (0x10UL << ADC_SQR2_SQ9_Pos)

#define	ADC_SQR3_SQ10_Pos (0U)

#define	ADC_SQR3_SQ10_Msk (0x1FUL << ADC_SQR3_SQ10_Pos)

#define	ADC_SQR3_SQ10 ADC_SQR3_SQ10_Msk

#define	ADC_SQR3_SQ10_0 (0x01UL << ADC_SQR3_SQ10_Pos)

#define	ADC_SQR3_SQ10_1 (0x02UL << ADC_SQR3_SQ10_Pos)

#define	ADC_SQR3_SQ10_2 (0x04UL << ADC_SQR3_SQ10_Pos)

#define	ADC_SQR3_SQ10_3 (0x08UL << ADC_SQR3_SQ10_Pos)

#define	ADC_SQR3_SQ10_4 (0x10UL << ADC_SQR3_SQ10_Pos)

#define	ADC_SQR3_SQ11_Pos (6U)

#define	ADC_SQR3_SQ11_Msk (0x1FUL << ADC_SQR3_SQ11_Pos)

#define	ADC_SQR3_SQ11 ADC_SQR3_SQ11_Msk

#define	ADC_SQR3_SQ11_0 (0x01UL << ADC_SQR3_SQ11_Pos)

#define	ADC_SQR3_SQ11_1 (0x02UL << ADC_SQR3_SQ11_Pos)

#define	ADC_SQR3_SQ11_2 (0x04UL << ADC_SQR3_SQ11_Pos)

#define	ADC_SQR3_SQ11_3 (0x08UL << ADC_SQR3_SQ11_Pos)

#define	ADC_SQR3_SQ11_4 (0x10UL << ADC_SQR3_SQ11_Pos)

#define	ADC_SQR3_SQ12_Pos (12U)

#define	ADC_SQR3_SQ12_Msk (0x1FUL << ADC_SQR3_SQ12_Pos)

#define	ADC_SQR3_SQ12 ADC_SQR3_SQ12_Msk

#define	ADC_SQR3_SQ12_0 (0x01UL << ADC_SQR3_SQ12_Pos)

#define	ADC_SQR3_SQ12_1 (0x02UL << ADC_SQR3_SQ12_Pos)

#define	ADC_SQR3_SQ12_2 (0x04UL << ADC_SQR3_SQ12_Pos)

#define	ADC_SQR3_SQ12_3 (0x08UL << ADC_SQR3_SQ12_Pos)

#define	ADC_SQR3_SQ12_4 (0x10UL << ADC_SQR3_SQ12_Pos)

#define	ADC_SQR3_SQ13_Pos (18U)

#define	ADC_SQR3_SQ13_Msk (0x1FUL << ADC_SQR3_SQ13_Pos)

#define	ADC_SQR3_SQ13 ADC_SQR3_SQ13_Msk

#define	ADC_SQR3_SQ13_0 (0x01UL << ADC_SQR3_SQ13_Pos)

#define	ADC_SQR3_SQ13_1 (0x02UL << ADC_SQR3_SQ13_Pos)

#define	ADC_SQR3_SQ13_2 (0x04UL << ADC_SQR3_SQ13_Pos)

#define	ADC_SQR3_SQ13_3 (0x08UL << ADC_SQR3_SQ13_Pos)

#define	ADC_SQR3_SQ13_4 (0x10UL << ADC_SQR3_SQ13_Pos)

#define	ADC_SQR3_SQ14_Pos (24U)

#define	ADC_SQR3_SQ14_Msk (0x1FUL << ADC_SQR3_SQ14_Pos)

#define	ADC_SQR3_SQ14 ADC_SQR3_SQ14_Msk

#define	ADC_SQR3_SQ14_0 (0x01UL << ADC_SQR3_SQ14_Pos)

#define	ADC_SQR3_SQ14_1 (0x02UL << ADC_SQR3_SQ14_Pos)

#define	ADC_SQR3_SQ14_2 (0x04UL << ADC_SQR3_SQ14_Pos)

#define	ADC_SQR3_SQ14_3 (0x08UL << ADC_SQR3_SQ14_Pos)

#define	ADC_SQR3_SQ14_4 (0x10UL << ADC_SQR3_SQ14_Pos)

#define	ADC_SQR4_SQ15_Pos (0U)

#define	ADC_SQR4_SQ15_Msk (0x1FUL << ADC_SQR4_SQ15_Pos)

#define	ADC_SQR4_SQ15 ADC_SQR4_SQ15_Msk

#define	ADC_SQR4_SQ15_0 (0x01UL << ADC_SQR4_SQ15_Pos)

#define	ADC_SQR4_SQ15_1 (0x02UL << ADC_SQR4_SQ15_Pos)

#define	ADC_SQR4_SQ15_2 (0x04UL << ADC_SQR4_SQ15_Pos)

#define	ADC_SQR4_SQ15_3 (0x08UL << ADC_SQR4_SQ15_Pos)

#define	ADC_SQR4_SQ15_4 (0x10UL << ADC_SQR4_SQ15_Pos)

#define	ADC_SQR4_SQ16_Pos (6U)

#define	ADC_SQR4_SQ16_Msk (0x1FUL << ADC_SQR4_SQ16_Pos)

#define	ADC_SQR4_SQ16 ADC_SQR4_SQ16_Msk

#define	ADC_SQR4_SQ16_0 (0x01UL << ADC_SQR4_SQ16_Pos)

#define	ADC_SQR4_SQ16_1 (0x02UL << ADC_SQR4_SQ16_Pos)

#define	ADC_SQR4_SQ16_2 (0x04UL << ADC_SQR4_SQ16_Pos)

#define	ADC_SQR4_SQ16_3 (0x08UL << ADC_SQR4_SQ16_Pos)

#define	ADC_SQR4_SQ16_4 (0x10UL << ADC_SQR4_SQ16_Pos)

#define	ADC_DR_RDATA_Pos (0U)

#define	ADC_DR_RDATA_Msk (0xFFFFUL << ADC_DR_RDATA_Pos)

#define	ADC_DR_RDATA ADC_DR_RDATA_Msk

#define	ADC_DR_RDATA_0 (0x0001UL << ADC_DR_RDATA_Pos)

#define	ADC_DR_RDATA_1 (0x0002UL << ADC_DR_RDATA_Pos)

#define	ADC_DR_RDATA_2 (0x0004UL << ADC_DR_RDATA_Pos)

#define	ADC_DR_RDATA_3 (0x0008UL << ADC_DR_RDATA_Pos)

#define	ADC_DR_RDATA_4 (0x0010UL << ADC_DR_RDATA_Pos)

#define	ADC_DR_RDATA_5 (0x0020UL << ADC_DR_RDATA_Pos)

#define	ADC_DR_RDATA_6 (0x0040UL << ADC_DR_RDATA_Pos)

#define	ADC_DR_RDATA_7 (0x0080UL << ADC_DR_RDATA_Pos)

#define	ADC_DR_RDATA_8 (0x0100UL << ADC_DR_RDATA_Pos)

#define	ADC_DR_RDATA_9 (0x0200UL << ADC_DR_RDATA_Pos)

#define	ADC_DR_RDATA_10 (0x0400UL << ADC_DR_RDATA_Pos)

#define	ADC_DR_RDATA_11 (0x0800UL << ADC_DR_RDATA_Pos)

#define	ADC_DR_RDATA_12 (0x1000UL << ADC_DR_RDATA_Pos)

#define	ADC_DR_RDATA_13 (0x2000UL << ADC_DR_RDATA_Pos)

#define	ADC_DR_RDATA_14 (0x4000UL << ADC_DR_RDATA_Pos)

#define	ADC_DR_RDATA_15 (0x8000UL << ADC_DR_RDATA_Pos)

#define	ADC_JSQR_JL_Pos (0U)

#define	ADC_JSQR_JL_Msk (0x3UL << ADC_JSQR_JL_Pos)

#define	ADC_JSQR_JL ADC_JSQR_JL_Msk

#define	ADC_JSQR_JL_0 (0x1UL << ADC_JSQR_JL_Pos)

#define	ADC_JSQR_JL_1 (0x2UL << ADC_JSQR_JL_Pos)

#define	ADC_JSQR_JEXTSEL_Pos (2U)

#define	ADC_JSQR_JEXTSEL_Msk (0xFUL << ADC_JSQR_JEXTSEL_Pos)

#define	ADC_JSQR_JEXTSEL ADC_JSQR_JEXTSEL_Msk

#define	ADC_JSQR_JEXTSEL_0 (0x1UL << ADC_JSQR_JEXTSEL_Pos)

#define	ADC_JSQR_JEXTSEL_1 (0x2UL << ADC_JSQR_JEXTSEL_Pos)

#define	ADC_JSQR_JEXTSEL_2 (0x4UL << ADC_JSQR_JEXTSEL_Pos)

#define	ADC_JSQR_JEXTSEL_3 (0x8UL << ADC_JSQR_JEXTSEL_Pos)

#define	ADC_JSQR_JEXTEN_Pos (6U)

#define	ADC_JSQR_JEXTEN_Msk (0x3UL << ADC_JSQR_JEXTEN_Pos)

#define	ADC_JSQR_JEXTEN ADC_JSQR_JEXTEN_Msk

#define	ADC_JSQR_JEXTEN_0 (0x1UL << ADC_JSQR_JEXTEN_Pos)

#define	ADC_JSQR_JEXTEN_1 (0x2UL << ADC_JSQR_JEXTEN_Pos)

#define	ADC_JSQR_JSQ1_Pos (8U)

#define	ADC_JSQR_JSQ1_Msk (0x1FUL << ADC_JSQR_JSQ1_Pos)

#define	ADC_JSQR_JSQ1 ADC_JSQR_JSQ1_Msk

#define	ADC_JSQR_JSQ1_0 (0x01UL << ADC_JSQR_JSQ1_Pos)

#define	ADC_JSQR_JSQ1_1 (0x02UL << ADC_JSQR_JSQ1_Pos)

#define	ADC_JSQR_JSQ1_2 (0x04UL << ADC_JSQR_JSQ1_Pos)

#define	ADC_JSQR_JSQ1_3 (0x08UL << ADC_JSQR_JSQ1_Pos)

#define	ADC_JSQR_JSQ1_4 (0x10UL << ADC_JSQR_JSQ1_Pos)

#define	ADC_JSQR_JSQ2_Pos (14U)

#define	ADC_JSQR_JSQ2_Msk (0x1FUL << ADC_JSQR_JSQ2_Pos)

#define	ADC_JSQR_JSQ2 ADC_JSQR_JSQ2_Msk

#define	ADC_JSQR_JSQ2_0 (0x01UL << ADC_JSQR_JSQ2_Pos)

#define	ADC_JSQR_JSQ2_1 (0x02UL << ADC_JSQR_JSQ2_Pos)

#define	ADC_JSQR_JSQ2_2 (0x04UL << ADC_JSQR_JSQ2_Pos)

#define	ADC_JSQR_JSQ2_3 (0x08UL << ADC_JSQR_JSQ2_Pos)

#define	ADC_JSQR_JSQ2_4 (0x10UL << ADC_JSQR_JSQ2_Pos)

#define	ADC_JSQR_JSQ3_Pos (20U)

#define	ADC_JSQR_JSQ3_Msk (0x1FUL << ADC_JSQR_JSQ3_Pos)

#define	ADC_JSQR_JSQ3 ADC_JSQR_JSQ3_Msk

#define	ADC_JSQR_JSQ3_0 (0x01UL << ADC_JSQR_JSQ3_Pos)

#define	ADC_JSQR_JSQ3_1 (0x02UL << ADC_JSQR_JSQ3_Pos)

#define	ADC_JSQR_JSQ3_2 (0x04UL << ADC_JSQR_JSQ3_Pos)

#define	ADC_JSQR_JSQ3_3 (0x08UL << ADC_JSQR_JSQ3_Pos)

#define	ADC_JSQR_JSQ3_4 (0x10UL << ADC_JSQR_JSQ3_Pos)

#define	ADC_JSQR_JSQ4_Pos (26U)

#define	ADC_JSQR_JSQ4_Msk (0x1FUL << ADC_JSQR_JSQ4_Pos)

#define	ADC_JSQR_JSQ4 ADC_JSQR_JSQ4_Msk

#define	ADC_JSQR_JSQ4_0 (0x01UL << ADC_JSQR_JSQ4_Pos)

#define	ADC_JSQR_JSQ4_1 (0x02UL << ADC_JSQR_JSQ4_Pos)

#define	ADC_JSQR_JSQ4_2 (0x04UL << ADC_JSQR_JSQ4_Pos)

#define	ADC_JSQR_JSQ4_3 (0x08UL << ADC_JSQR_JSQ4_Pos)

#define	ADC_JSQR_JSQ4_4 (0x10UL << ADC_JSQR_JSQ4_Pos)

#define	ADC_OFR1_OFFSET1_Pos (0U)

#define	ADC_OFR1_OFFSET1_Msk (0xFFFUL << ADC_OFR1_OFFSET1_Pos)

#define	ADC_OFR1_OFFSET1 ADC_OFR1_OFFSET1_Msk

#define	ADC_OFR1_OFFSET1_0 (0x001UL << ADC_OFR1_OFFSET1_Pos)

#define	ADC_OFR1_OFFSET1_1 (0x002UL << ADC_OFR1_OFFSET1_Pos)

#define	ADC_OFR1_OFFSET1_2 (0x004UL << ADC_OFR1_OFFSET1_Pos)

#define	ADC_OFR1_OFFSET1_3 (0x008UL << ADC_OFR1_OFFSET1_Pos)

#define	ADC_OFR1_OFFSET1_4 (0x010UL << ADC_OFR1_OFFSET1_Pos)

#define	ADC_OFR1_OFFSET1_5 (0x020UL << ADC_OFR1_OFFSET1_Pos)

#define	ADC_OFR1_OFFSET1_6 (0x040UL << ADC_OFR1_OFFSET1_Pos)

#define	ADC_OFR1_OFFSET1_7 (0x080UL << ADC_OFR1_OFFSET1_Pos)

#define	ADC_OFR1_OFFSET1_8 (0x100UL << ADC_OFR1_OFFSET1_Pos)

#define	ADC_OFR1_OFFSET1_9 (0x200UL << ADC_OFR1_OFFSET1_Pos)

#define	ADC_OFR1_OFFSET1_10 (0x400UL << ADC_OFR1_OFFSET1_Pos)

#define	ADC_OFR1_OFFSET1_11 (0x800UL << ADC_OFR1_OFFSET1_Pos)

#define	ADC_OFR1_OFFSET1_CH_Pos (26U)

#define	ADC_OFR1_OFFSET1_CH_Msk (0x1FUL << ADC_OFR1_OFFSET1_CH_Pos)

#define	ADC_OFR1_OFFSET1_CH ADC_OFR1_OFFSET1_CH_Msk

#define	ADC_OFR1_OFFSET1_CH_0 (0x01UL << ADC_OFR1_OFFSET1_CH_Pos)

#define	ADC_OFR1_OFFSET1_CH_1 (0x02UL << ADC_OFR1_OFFSET1_CH_Pos)

#define	ADC_OFR1_OFFSET1_CH_2 (0x04UL << ADC_OFR1_OFFSET1_CH_Pos)

#define	ADC_OFR1_OFFSET1_CH_3 (0x08UL << ADC_OFR1_OFFSET1_CH_Pos)

#define	ADC_OFR1_OFFSET1_CH_4 (0x10UL << ADC_OFR1_OFFSET1_CH_Pos)

#define	ADC_OFR1_OFFSET1_EN_Pos (31U)

#define	ADC_OFR1_OFFSET1_EN_Msk (0x1UL << ADC_OFR1_OFFSET1_EN_Pos)

#define	ADC_OFR1_OFFSET1_EN ADC_OFR1_OFFSET1_EN_Msk

#define	ADC_OFR2_OFFSET2_Pos (0U)

#define	ADC_OFR2_OFFSET2_Msk (0xFFFUL << ADC_OFR2_OFFSET2_Pos)

#define	ADC_OFR2_OFFSET2 ADC_OFR2_OFFSET2_Msk

#define	ADC_OFR2_OFFSET2_0 (0x001UL << ADC_OFR2_OFFSET2_Pos)

#define	ADC_OFR2_OFFSET2_1 (0x002UL << ADC_OFR2_OFFSET2_Pos)

#define	ADC_OFR2_OFFSET2_2 (0x004UL << ADC_OFR2_OFFSET2_Pos)

#define	ADC_OFR2_OFFSET2_3 (0x008UL << ADC_OFR2_OFFSET2_Pos)

#define	ADC_OFR2_OFFSET2_4 (0x010UL << ADC_OFR2_OFFSET2_Pos)

#define	ADC_OFR2_OFFSET2_5 (0x020UL << ADC_OFR2_OFFSET2_Pos)

#define	ADC_OFR2_OFFSET2_6 (0x040UL << ADC_OFR2_OFFSET2_Pos)

#define	ADC_OFR2_OFFSET2_7 (0x080UL << ADC_OFR2_OFFSET2_Pos)

#define	ADC_OFR2_OFFSET2_8 (0x100UL << ADC_OFR2_OFFSET2_Pos)

#define	ADC_OFR2_OFFSET2_9 (0x200UL << ADC_OFR2_OFFSET2_Pos)

#define	ADC_OFR2_OFFSET2_10 (0x400UL << ADC_OFR2_OFFSET2_Pos)

#define	ADC_OFR2_OFFSET2_11 (0x800UL << ADC_OFR2_OFFSET2_Pos)

#define	ADC_OFR2_OFFSET2_CH_Pos (26U)

#define	ADC_OFR2_OFFSET2_CH_Msk (0x1FUL << ADC_OFR2_OFFSET2_CH_Pos)

#define	ADC_OFR2_OFFSET2_CH ADC_OFR2_OFFSET2_CH_Msk

#define	ADC_OFR2_OFFSET2_CH_0 (0x01UL << ADC_OFR2_OFFSET2_CH_Pos)

#define	ADC_OFR2_OFFSET2_CH_1 (0x02UL << ADC_OFR2_OFFSET2_CH_Pos)

#define	ADC_OFR2_OFFSET2_CH_2 (0x04UL << ADC_OFR2_OFFSET2_CH_Pos)

#define	ADC_OFR2_OFFSET2_CH_3 (0x08UL << ADC_OFR2_OFFSET2_CH_Pos)

#define	ADC_OFR2_OFFSET2_CH_4 (0x10UL << ADC_OFR2_OFFSET2_CH_Pos)

#define	ADC_OFR2_OFFSET2_EN_Pos (31U)

#define	ADC_OFR2_OFFSET2_EN_Msk (0x1UL << ADC_OFR2_OFFSET2_EN_Pos)

#define	ADC_OFR2_OFFSET2_EN ADC_OFR2_OFFSET2_EN_Msk

#define	ADC_OFR3_OFFSET3_Pos (0U)

#define	ADC_OFR3_OFFSET3_Msk (0xFFFUL << ADC_OFR3_OFFSET3_Pos)

#define	ADC_OFR3_OFFSET3 ADC_OFR3_OFFSET3_Msk

#define	ADC_OFR3_OFFSET3_0 (0x001UL << ADC_OFR3_OFFSET3_Pos)

#define	ADC_OFR3_OFFSET3_1 (0x002UL << ADC_OFR3_OFFSET3_Pos)

#define	ADC_OFR3_OFFSET3_2 (0x004UL << ADC_OFR3_OFFSET3_Pos)

#define	ADC_OFR3_OFFSET3_3 (0x008UL << ADC_OFR3_OFFSET3_Pos)

#define	ADC_OFR3_OFFSET3_4 (0x010UL << ADC_OFR3_OFFSET3_Pos)

#define	ADC_OFR3_OFFSET3_5 (0x020UL << ADC_OFR3_OFFSET3_Pos)

#define	ADC_OFR3_OFFSET3_6 (0x040UL << ADC_OFR3_OFFSET3_Pos)

#define	ADC_OFR3_OFFSET3_7 (0x080UL << ADC_OFR3_OFFSET3_Pos)

#define	ADC_OFR3_OFFSET3_8 (0x100UL << ADC_OFR3_OFFSET3_Pos)

#define	ADC_OFR3_OFFSET3_9 (0x200UL << ADC_OFR3_OFFSET3_Pos)

#define	ADC_OFR3_OFFSET3_10 (0x400UL << ADC_OFR3_OFFSET3_Pos)

#define	ADC_OFR3_OFFSET3_11 (0x800UL << ADC_OFR3_OFFSET3_Pos)

#define	ADC_OFR3_OFFSET3_CH_Pos (26U)

#define	ADC_OFR3_OFFSET3_CH_Msk (0x1FUL << ADC_OFR3_OFFSET3_CH_Pos)

#define	ADC_OFR3_OFFSET3_CH ADC_OFR3_OFFSET3_CH_Msk

#define	ADC_OFR3_OFFSET3_CH_0 (0x01UL << ADC_OFR3_OFFSET3_CH_Pos)

#define	ADC_OFR3_OFFSET3_CH_1 (0x02UL << ADC_OFR3_OFFSET3_CH_Pos)

#define	ADC_OFR3_OFFSET3_CH_2 (0x04UL << ADC_OFR3_OFFSET3_CH_Pos)

#define	ADC_OFR3_OFFSET3_CH_3 (0x08UL << ADC_OFR3_OFFSET3_CH_Pos)

#define	ADC_OFR3_OFFSET3_CH_4 (0x10UL << ADC_OFR3_OFFSET3_CH_Pos)

#define	ADC_OFR3_OFFSET3_EN_Pos (31U)

#define	ADC_OFR3_OFFSET3_EN_Msk (0x1UL << ADC_OFR3_OFFSET3_EN_Pos)

#define	ADC_OFR3_OFFSET3_EN ADC_OFR3_OFFSET3_EN_Msk

#define	ADC_OFR4_OFFSET4_Pos (0U)

#define	ADC_OFR4_OFFSET4_Msk (0xFFFUL << ADC_OFR4_OFFSET4_Pos)

#define	ADC_OFR4_OFFSET4 ADC_OFR4_OFFSET4_Msk

#define	ADC_OFR4_OFFSET4_0 (0x001UL << ADC_OFR4_OFFSET4_Pos)

#define	ADC_OFR4_OFFSET4_1 (0x002UL << ADC_OFR4_OFFSET4_Pos)

#define	ADC_OFR4_OFFSET4_2 (0x004UL << ADC_OFR4_OFFSET4_Pos)

#define	ADC_OFR4_OFFSET4_3 (0x008UL << ADC_OFR4_OFFSET4_Pos)

#define	ADC_OFR4_OFFSET4_4 (0x010UL << ADC_OFR4_OFFSET4_Pos)

#define	ADC_OFR4_OFFSET4_5 (0x020UL << ADC_OFR4_OFFSET4_Pos)

#define	ADC_OFR4_OFFSET4_6 (0x040UL << ADC_OFR4_OFFSET4_Pos)

#define	ADC_OFR4_OFFSET4_7 (0x080UL << ADC_OFR4_OFFSET4_Pos)

#define	ADC_OFR4_OFFSET4_8 (0x100UL << ADC_OFR4_OFFSET4_Pos)

#define	ADC_OFR4_OFFSET4_9 (0x200UL << ADC_OFR4_OFFSET4_Pos)

#define	ADC_OFR4_OFFSET4_10 (0x400UL << ADC_OFR4_OFFSET4_Pos)

#define	ADC_OFR4_OFFSET4_11 (0x800UL << ADC_OFR4_OFFSET4_Pos)

#define	ADC_OFR4_OFFSET4_CH_Pos (26U)

#define	ADC_OFR4_OFFSET4_CH_Msk (0x1FUL << ADC_OFR4_OFFSET4_CH_Pos)

#define	ADC_OFR4_OFFSET4_CH ADC_OFR4_OFFSET4_CH_Msk

#define	ADC_OFR4_OFFSET4_CH_0 (0x01UL << ADC_OFR4_OFFSET4_CH_Pos)

#define	ADC_OFR4_OFFSET4_CH_1 (0x02UL << ADC_OFR4_OFFSET4_CH_Pos)

#define	ADC_OFR4_OFFSET4_CH_2 (0x04UL << ADC_OFR4_OFFSET4_CH_Pos)

#define	ADC_OFR4_OFFSET4_CH_3 (0x08UL << ADC_OFR4_OFFSET4_CH_Pos)

#define	ADC_OFR4_OFFSET4_CH_4 (0x10UL << ADC_OFR4_OFFSET4_CH_Pos)

#define	ADC_OFR4_OFFSET4_EN_Pos (31U)

#define	ADC_OFR4_OFFSET4_EN_Msk (0x1UL << ADC_OFR4_OFFSET4_EN_Pos)

#define	ADC_OFR4_OFFSET4_EN ADC_OFR4_OFFSET4_EN_Msk

#define	ADC_JDR1_JDATA_Pos (0U)

#define	ADC_JDR1_JDATA_Msk (0xFFFFUL << ADC_JDR1_JDATA_Pos)

#define	ADC_JDR1_JDATA ADC_JDR1_JDATA_Msk

#define	ADC_JDR1_JDATA_0 (0x0001UL << ADC_JDR1_JDATA_Pos)

#define	ADC_JDR1_JDATA_1 (0x0002UL << ADC_JDR1_JDATA_Pos)

#define	ADC_JDR1_JDATA_2 (0x0004UL << ADC_JDR1_JDATA_Pos)

#define	ADC_JDR1_JDATA_3 (0x0008UL << ADC_JDR1_JDATA_Pos)

#define	ADC_JDR1_JDATA_4 (0x0010UL << ADC_JDR1_JDATA_Pos)

#define	ADC_JDR1_JDATA_5 (0x0020UL << ADC_JDR1_JDATA_Pos)

#define	ADC_JDR1_JDATA_6 (0x0040UL << ADC_JDR1_JDATA_Pos)

#define	ADC_JDR1_JDATA_7 (0x0080UL << ADC_JDR1_JDATA_Pos)

#define	ADC_JDR1_JDATA_8 (0x0100UL << ADC_JDR1_JDATA_Pos)

#define	ADC_JDR1_JDATA_9 (0x0200UL << ADC_JDR1_JDATA_Pos)

#define	ADC_JDR1_JDATA_10 (0x0400UL << ADC_JDR1_JDATA_Pos)

#define	ADC_JDR1_JDATA_11 (0x0800UL << ADC_JDR1_JDATA_Pos)

#define	ADC_JDR1_JDATA_12 (0x1000UL << ADC_JDR1_JDATA_Pos)

#define	ADC_JDR1_JDATA_13 (0x2000UL << ADC_JDR1_JDATA_Pos)

#define	ADC_JDR1_JDATA_14 (0x4000UL << ADC_JDR1_JDATA_Pos)

#define	ADC_JDR1_JDATA_15 (0x8000UL << ADC_JDR1_JDATA_Pos)

#define	ADC_JDR2_JDATA_Pos (0U)

#define	ADC_JDR2_JDATA_Msk (0xFFFFUL << ADC_JDR2_JDATA_Pos)

#define	ADC_JDR2_JDATA ADC_JDR2_JDATA_Msk

#define	ADC_JDR2_JDATA_0 (0x0001UL << ADC_JDR2_JDATA_Pos)

#define	ADC_JDR2_JDATA_1 (0x0002UL << ADC_JDR2_JDATA_Pos)

#define	ADC_JDR2_JDATA_2 (0x0004UL << ADC_JDR2_JDATA_Pos)

#define	ADC_JDR2_JDATA_3 (0x0008UL << ADC_JDR2_JDATA_Pos)

#define	ADC_JDR2_JDATA_4 (0x0010UL << ADC_JDR2_JDATA_Pos)

#define	ADC_JDR2_JDATA_5 (0x0020UL << ADC_JDR2_JDATA_Pos)

#define	ADC_JDR2_JDATA_6 (0x0040UL << ADC_JDR2_JDATA_Pos)

#define	ADC_JDR2_JDATA_7 (0x0080UL << ADC_JDR2_JDATA_Pos)

#define	ADC_JDR2_JDATA_8 (0x0100UL << ADC_JDR2_JDATA_Pos)

#define	ADC_JDR2_JDATA_9 (0x0200UL << ADC_JDR2_JDATA_Pos)

#define	ADC_JDR2_JDATA_10 (0x0400UL << ADC_JDR2_JDATA_Pos)

#define	ADC_JDR2_JDATA_11 (0x0800UL << ADC_JDR2_JDATA_Pos)

#define	ADC_JDR2_JDATA_12 (0x1000UL << ADC_JDR2_JDATA_Pos)

#define	ADC_JDR2_JDATA_13 (0x2000UL << ADC_JDR2_JDATA_Pos)

#define	ADC_JDR2_JDATA_14 (0x4000UL << ADC_JDR2_JDATA_Pos)

#define	ADC_JDR2_JDATA_15 (0x8000UL << ADC_JDR2_JDATA_Pos)

#define	ADC_JDR3_JDATA_Pos (0U)

#define	ADC_JDR3_JDATA_Msk (0xFFFFUL << ADC_JDR3_JDATA_Pos)

#define	ADC_JDR3_JDATA ADC_JDR3_JDATA_Msk

#define	ADC_JDR3_JDATA_0 (0x0001UL << ADC_JDR3_JDATA_Pos)

#define	ADC_JDR3_JDATA_1 (0x0002UL << ADC_JDR3_JDATA_Pos)

#define	ADC_JDR3_JDATA_2 (0x0004UL << ADC_JDR3_JDATA_Pos)

#define	ADC_JDR3_JDATA_3 (0x0008UL << ADC_JDR3_JDATA_Pos)

#define	ADC_JDR3_JDATA_4 (0x0010UL << ADC_JDR3_JDATA_Pos)

#define	ADC_JDR3_JDATA_5 (0x0020UL << ADC_JDR3_JDATA_Pos)

#define	ADC_JDR3_JDATA_6 (0x0040UL << ADC_JDR3_JDATA_Pos)

#define	ADC_JDR3_JDATA_7 (0x0080UL << ADC_JDR3_JDATA_Pos)

#define	ADC_JDR3_JDATA_8 (0x0100UL << ADC_JDR3_JDATA_Pos)

#define	ADC_JDR3_JDATA_9 (0x0200UL << ADC_JDR3_JDATA_Pos)

#define	ADC_JDR3_JDATA_10 (0x0400UL << ADC_JDR3_JDATA_Pos)

#define	ADC_JDR3_JDATA_11 (0x0800UL << ADC_JDR3_JDATA_Pos)

#define	ADC_JDR3_JDATA_12 (0x1000UL << ADC_JDR3_JDATA_Pos)

#define	ADC_JDR3_JDATA_13 (0x2000UL << ADC_JDR3_JDATA_Pos)

#define	ADC_JDR3_JDATA_14 (0x4000UL << ADC_JDR3_JDATA_Pos)

#define	ADC_JDR3_JDATA_15 (0x8000UL << ADC_JDR3_JDATA_Pos)

#define	ADC_JDR4_JDATA_Pos (0U)

#define	ADC_JDR4_JDATA_Msk (0xFFFFUL << ADC_JDR4_JDATA_Pos)

#define	ADC_JDR4_JDATA ADC_JDR4_JDATA_Msk

#define	ADC_JDR4_JDATA_0 (0x0001UL << ADC_JDR4_JDATA_Pos)

#define	ADC_JDR4_JDATA_1 (0x0002UL << ADC_JDR4_JDATA_Pos)

#define	ADC_JDR4_JDATA_2 (0x0004UL << ADC_JDR4_JDATA_Pos)

#define	ADC_JDR4_JDATA_3 (0x0008UL << ADC_JDR4_JDATA_Pos)

#define	ADC_JDR4_JDATA_4 (0x0010UL << ADC_JDR4_JDATA_Pos)

#define	ADC_JDR4_JDATA_5 (0x0020UL << ADC_JDR4_JDATA_Pos)

#define	ADC_JDR4_JDATA_6 (0x0040UL << ADC_JDR4_JDATA_Pos)

#define	ADC_JDR4_JDATA_7 (0x0080UL << ADC_JDR4_JDATA_Pos)

#define	ADC_JDR4_JDATA_8 (0x0100UL << ADC_JDR4_JDATA_Pos)

#define	ADC_JDR4_JDATA_9 (0x0200UL << ADC_JDR4_JDATA_Pos)

#define	ADC_JDR4_JDATA_10 (0x0400UL << ADC_JDR4_JDATA_Pos)

#define	ADC_JDR4_JDATA_11 (0x0800UL << ADC_JDR4_JDATA_Pos)

#define	ADC_JDR4_JDATA_12 (0x1000UL << ADC_JDR4_JDATA_Pos)

#define	ADC_JDR4_JDATA_13 (0x2000UL << ADC_JDR4_JDATA_Pos)

#define	ADC_JDR4_JDATA_14 (0x4000UL << ADC_JDR4_JDATA_Pos)

#define	ADC_JDR4_JDATA_15 (0x8000UL << ADC_JDR4_JDATA_Pos)

#define	ADC_AWD2CR_AWD2CH_Pos (1U)

#define	ADC_AWD2CR_AWD2CH_Msk (0x3FFFFUL << ADC_AWD2CR_AWD2CH_Pos)

#define	ADC_AWD2CR_AWD2CH ADC_AWD2CR_AWD2CH_Msk

#define	ADC_AWD2CR_AWD2CH_0 (0x00001UL << ADC_AWD2CR_AWD2CH_Pos)

#define	ADC_AWD2CR_AWD2CH_1 (0x00002UL << ADC_AWD2CR_AWD2CH_Pos)

#define	ADC_AWD2CR_AWD2CH_2 (0x00004UL << ADC_AWD2CR_AWD2CH_Pos)

#define	ADC_AWD2CR_AWD2CH_3 (0x00008UL << ADC_AWD2CR_AWD2CH_Pos)

#define	ADC_AWD2CR_AWD2CH_4 (0x00010UL << ADC_AWD2CR_AWD2CH_Pos)

#define	ADC_AWD2CR_AWD2CH_5 (0x00020UL << ADC_AWD2CR_AWD2CH_Pos)

#define	ADC_AWD2CR_AWD2CH_6 (0x00040UL << ADC_AWD2CR_AWD2CH_Pos)

#define	ADC_AWD2CR_AWD2CH_7 (0x00080UL << ADC_AWD2CR_AWD2CH_Pos)

#define	ADC_AWD2CR_AWD2CH_8 (0x00100UL << ADC_AWD2CR_AWD2CH_Pos)

#define	ADC_AWD2CR_AWD2CH_9 (0x00200UL << ADC_AWD2CR_AWD2CH_Pos)

#define	ADC_AWD2CR_AWD2CH_10 (0x00400UL << ADC_AWD2CR_AWD2CH_Pos)

#define	ADC_AWD2CR_AWD2CH_11 (0x00800UL << ADC_AWD2CR_AWD2CH_Pos)

#define	ADC_AWD2CR_AWD2CH_12 (0x01000UL << ADC_AWD2CR_AWD2CH_Pos)

#define	ADC_AWD2CR_AWD2CH_13 (0x02000UL << ADC_AWD2CR_AWD2CH_Pos)

#define	ADC_AWD2CR_AWD2CH_14 (0x04000UL << ADC_AWD2CR_AWD2CH_Pos)

#define	ADC_AWD2CR_AWD2CH_15 (0x08000UL << ADC_AWD2CR_AWD2CH_Pos)

#define	ADC_AWD2CR_AWD2CH_16 (0x10000UL << ADC_AWD2CR_AWD2CH_Pos)

#define	ADC_AWD2CR_AWD2CH_17 (0x20000UL << ADC_AWD2CR_AWD2CH_Pos)

#define	ADC_AWD3CR_AWD3CH_Pos (1U)

#define	ADC_AWD3CR_AWD3CH_Msk (0x3FFFFUL << ADC_AWD3CR_AWD3CH_Pos)

#define	ADC_AWD3CR_AWD3CH ADC_AWD3CR_AWD3CH_Msk

#define	ADC_AWD3CR_AWD3CH_0 (0x00001UL << ADC_AWD3CR_AWD3CH_Pos)

#define	ADC_AWD3CR_AWD3CH_1 (0x00002UL << ADC_AWD3CR_AWD3CH_Pos)

#define	ADC_AWD3CR_AWD3CH_2 (0x00004UL << ADC_AWD3CR_AWD3CH_Pos)

#define	ADC_AWD3CR_AWD3CH_3 (0x00008UL << ADC_AWD3CR_AWD3CH_Pos)

#define	ADC_AWD3CR_AWD3CH_4 (0x00010UL << ADC_AWD3CR_AWD3CH_Pos)

#define	ADC_AWD3CR_AWD3CH_5 (0x00020UL << ADC_AWD3CR_AWD3CH_Pos)

#define	ADC_AWD3CR_AWD3CH_6 (0x00040UL << ADC_AWD3CR_AWD3CH_Pos)

#define	ADC_AWD3CR_AWD3CH_7 (0x00080UL << ADC_AWD3CR_AWD3CH_Pos)

#define	ADC_AWD3CR_AWD3CH_8 (0x00100UL << ADC_AWD3CR_AWD3CH_Pos)

#define	ADC_AWD3CR_AWD3CH_9 (0x00200UL << ADC_AWD3CR_AWD3CH_Pos)

#define	ADC_AWD3CR_AWD3CH_10 (0x00400UL << ADC_AWD3CR_AWD3CH_Pos)

#define	ADC_AWD3CR_AWD3CH_11 (0x00800UL << ADC_AWD3CR_AWD3CH_Pos)

#define	ADC_AWD3CR_AWD3CH_12 (0x01000UL << ADC_AWD3CR_AWD3CH_Pos)

#define	ADC_AWD3CR_AWD3CH_13 (0x02000UL << ADC_AWD3CR_AWD3CH_Pos)

#define	ADC_AWD3CR_AWD3CH_14 (0x04000UL << ADC_AWD3CR_AWD3CH_Pos)

#define	ADC_AWD3CR_AWD3CH_15 (0x08000UL << ADC_AWD3CR_AWD3CH_Pos)

#define	ADC_AWD3CR_AWD3CH_16 (0x10000UL << ADC_AWD3CR_AWD3CH_Pos)

#define	ADC_AWD3CR_AWD3CH_17 (0x20000UL << ADC_AWD3CR_AWD3CH_Pos)

#define	ADC_DIFSEL_DIFSEL_Pos (1U)

#define	ADC_DIFSEL_DIFSEL_Msk (0x3FFFFUL << ADC_DIFSEL_DIFSEL_Pos)

#define	ADC_DIFSEL_DIFSEL ADC_DIFSEL_DIFSEL_Msk

#define	ADC_DIFSEL_DIFSEL_0 (0x00001UL << ADC_DIFSEL_DIFSEL_Pos)

#define	ADC_DIFSEL_DIFSEL_1 (0x00002UL << ADC_DIFSEL_DIFSEL_Pos)

#define	ADC_DIFSEL_DIFSEL_2 (0x00004UL << ADC_DIFSEL_DIFSEL_Pos)

#define	ADC_DIFSEL_DIFSEL_3 (0x00008UL << ADC_DIFSEL_DIFSEL_Pos)

#define	ADC_DIFSEL_DIFSEL_4 (0x00010UL << ADC_DIFSEL_DIFSEL_Pos)

#define	ADC_DIFSEL_DIFSEL_5 (0x00020UL << ADC_DIFSEL_DIFSEL_Pos)

#define	ADC_DIFSEL_DIFSEL_6 (0x00040UL << ADC_DIFSEL_DIFSEL_Pos)

#define	ADC_DIFSEL_DIFSEL_7 (0x00080UL << ADC_DIFSEL_DIFSEL_Pos)

#define	ADC_DIFSEL_DIFSEL_8 (0x00100UL << ADC_DIFSEL_DIFSEL_Pos)

#define	ADC_DIFSEL_DIFSEL_9 (0x00200UL << ADC_DIFSEL_DIFSEL_Pos)

#define	ADC_DIFSEL_DIFSEL_10 (0x00400UL << ADC_DIFSEL_DIFSEL_Pos)

#define	ADC_DIFSEL_DIFSEL_11 (0x00800UL << ADC_DIFSEL_DIFSEL_Pos)

#define	ADC_DIFSEL_DIFSEL_12 (0x01000UL << ADC_DIFSEL_DIFSEL_Pos)

#define	ADC_DIFSEL_DIFSEL_13 (0x02000UL << ADC_DIFSEL_DIFSEL_Pos)

#define	ADC_DIFSEL_DIFSEL_14 (0x04000UL << ADC_DIFSEL_DIFSEL_Pos)

#define	ADC_DIFSEL_DIFSEL_15 (0x08000UL << ADC_DIFSEL_DIFSEL_Pos)

#define	ADC_DIFSEL_DIFSEL_16 (0x10000UL << ADC_DIFSEL_DIFSEL_Pos)

#define	ADC_DIFSEL_DIFSEL_17 (0x20000UL << ADC_DIFSEL_DIFSEL_Pos)

#define	ADC_CALFACT_CALFACT_S_Pos (0U)

#define	ADC_CALFACT_CALFACT_S_Msk (0x7FUL << ADC_CALFACT_CALFACT_S_Pos)

#define	ADC_CALFACT_CALFACT_S ADC_CALFACT_CALFACT_S_Msk

#define	ADC_CALFACT_CALFACT_S_0 (0x01UL << ADC_CALFACT_CALFACT_S_Pos)

#define	ADC_CALFACT_CALFACT_S_1 (0x02UL << ADC_CALFACT_CALFACT_S_Pos)

#define	ADC_CALFACT_CALFACT_S_2 (0x04UL << ADC_CALFACT_CALFACT_S_Pos)

#define	ADC_CALFACT_CALFACT_S_3 (0x08UL << ADC_CALFACT_CALFACT_S_Pos)

#define	ADC_CALFACT_CALFACT_S_4 (0x10UL << ADC_CALFACT_CALFACT_S_Pos)

#define	ADC_CALFACT_CALFACT_S_5 (0x20UL << ADC_CALFACT_CALFACT_S_Pos)

#define	ADC_CALFACT_CALFACT_S_6 (0x40UL << ADC_CALFACT_CALFACT_S_Pos)

#define	ADC_CALFACT_CALFACT_D_Pos (16U)

#define	ADC_CALFACT_CALFACT_D_Msk (0x7FUL << ADC_CALFACT_CALFACT_D_Pos)

#define	ADC_CALFACT_CALFACT_D ADC_CALFACT_CALFACT_D_Msk

#define	ADC_CALFACT_CALFACT_D_0 (0x01UL << ADC_CALFACT_CALFACT_D_Pos)

#define	ADC_CALFACT_CALFACT_D_1 (0x02UL << ADC_CALFACT_CALFACT_D_Pos)

#define	ADC_CALFACT_CALFACT_D_2 (0x04UL << ADC_CALFACT_CALFACT_D_Pos)

#define	ADC_CALFACT_CALFACT_D_3 (0x08UL << ADC_CALFACT_CALFACT_D_Pos)

#define	ADC_CALFACT_CALFACT_D_4 (0x10UL << ADC_CALFACT_CALFACT_D_Pos)

#define	ADC_CALFACT_CALFACT_D_5 (0x20UL << ADC_CALFACT_CALFACT_D_Pos)

#define	ADC_CALFACT_CALFACT_D_6 (0x40UL << ADC_CALFACT_CALFACT_D_Pos)

#define	ADC12_CSR_ADRDY_MST_Pos (0U)

#define	ADC12_CSR_ADRDY_MST_Msk (0x1UL << ADC12_CSR_ADRDY_MST_Pos)

#define	ADC12_CSR_ADRDY_MST ADC12_CSR_ADRDY_MST_Msk

#define	ADC12_CSR_ADRDY_EOSMP_MST_Pos (1U)

#define	ADC12_CSR_ADRDY_EOSMP_MST_Msk (0x1UL << ADC12_CSR_ADRDY_EOSMP_MST_Pos)

#define	ADC12_CSR_ADRDY_EOSMP_MST ADC12_CSR_ADRDY_EOSMP_MST_Msk

#define	ADC12_CSR_ADRDY_EOC_MST_Pos (2U)

#define	ADC12_CSR_ADRDY_EOC_MST_Msk (0x1UL << ADC12_CSR_ADRDY_EOC_MST_Pos)

#define	ADC12_CSR_ADRDY_EOC_MST ADC12_CSR_ADRDY_EOC_MST_Msk

#define	ADC12_CSR_ADRDY_EOS_MST_Pos (3U)

#define	ADC12_CSR_ADRDY_EOS_MST_Msk (0x1UL << ADC12_CSR_ADRDY_EOS_MST_Pos)

#define	ADC12_CSR_ADRDY_EOS_MST ADC12_CSR_ADRDY_EOS_MST_Msk

#define	ADC12_CSR_ADRDY_OVR_MST_Pos (4U)

#define	ADC12_CSR_ADRDY_OVR_MST_Msk (0x1UL << ADC12_CSR_ADRDY_OVR_MST_Pos)

#define	ADC12_CSR_ADRDY_OVR_MST ADC12_CSR_ADRDY_OVR_MST_Msk

#define	ADC12_CSR_ADRDY_JEOC_MST_Pos (5U)

#define	ADC12_CSR_ADRDY_JEOC_MST_Msk (0x1UL << ADC12_CSR_ADRDY_JEOC_MST_Pos)

#define	ADC12_CSR_ADRDY_JEOC_MST ADC12_CSR_ADRDY_JEOC_MST_Msk

#define	ADC12_CSR_ADRDY_JEOS_MST_Pos (6U)

#define	ADC12_CSR_ADRDY_JEOS_MST_Msk (0x1UL << ADC12_CSR_ADRDY_JEOS_MST_Pos)

#define	ADC12_CSR_ADRDY_JEOS_MST ADC12_CSR_ADRDY_JEOS_MST_Msk

#define	ADC12_CSR_AWD1_MST_Pos (7U)

#define	ADC12_CSR_AWD1_MST_Msk (0x1UL << ADC12_CSR_AWD1_MST_Pos)

#define	ADC12_CSR_AWD1_MST ADC12_CSR_AWD1_MST_Msk

#define	ADC12_CSR_AWD2_MST_Pos (8U)

#define	ADC12_CSR_AWD2_MST_Msk (0x1UL << ADC12_CSR_AWD2_MST_Pos)

#define	ADC12_CSR_AWD2_MST ADC12_CSR_AWD2_MST_Msk

#define	ADC12_CSR_AWD3_MST_Pos (9U)

#define	ADC12_CSR_AWD3_MST_Msk (0x1UL << ADC12_CSR_AWD3_MST_Pos)

#define	ADC12_CSR_AWD3_MST ADC12_CSR_AWD3_MST_Msk

#define	ADC12_CSR_JQOVF_MST_Pos (10U)

#define	ADC12_CSR_JQOVF_MST_Msk (0x1UL << ADC12_CSR_JQOVF_MST_Pos)

#define	ADC12_CSR_JQOVF_MST ADC12_CSR_JQOVF_MST_Msk

#define	ADC12_CSR_ADRDY_SLV_Pos (16U)

#define	ADC12_CSR_ADRDY_SLV_Msk (0x1UL << ADC12_CSR_ADRDY_SLV_Pos)

#define	ADC12_CSR_ADRDY_SLV ADC12_CSR_ADRDY_SLV_Msk

#define	ADC12_CSR_ADRDY_EOSMP_SLV_Pos (17U)

#define	ADC12_CSR_ADRDY_EOSMP_SLV_Msk (0x1UL << ADC12_CSR_ADRDY_EOSMP_SLV_Pos)

#define	ADC12_CSR_ADRDY_EOSMP_SLV ADC12_CSR_ADRDY_EOSMP_SLV_Msk

#define	ADC12_CSR_ADRDY_EOC_SLV_Pos (18U)

#define	ADC12_CSR_ADRDY_EOC_SLV_Msk (0x1UL << ADC12_CSR_ADRDY_EOC_SLV_Pos)

#define	ADC12_CSR_ADRDY_EOC_SLV ADC12_CSR_ADRDY_EOC_SLV_Msk

#define	ADC12_CSR_ADRDY_EOS_SLV_Pos (19U)

#define	ADC12_CSR_ADRDY_EOS_SLV_Msk (0x1UL << ADC12_CSR_ADRDY_EOS_SLV_Pos)

#define	ADC12_CSR_ADRDY_EOS_SLV ADC12_CSR_ADRDY_EOS_SLV_Msk

#define	ADC12_CSR_ADRDY_OVR_SLV_Pos (20U)

#define	ADC12_CSR_ADRDY_OVR_SLV_Pos (20U)

#define	ADC12_CSR_ADRDY_OVR_SLV_Msk (0x1UL << ADC12_CSR_ADRDY_OVR_SLV_Pos)

#define	ADC12_CSR_ADRDY_OVR_SLV_Msk (0x1UL << ADC12_CSR_ADRDY_OVR_SLV_Pos)

#define	ADC12_CSR_ADRDY_OVR_SLV ADC12_CSR_ADRDY_OVR_SLV_Msk

#define	ADC12_CSR_ADRDY_OVR_SLV ADC12_CSR_ADRDY_OVR_SLV_Msk

#define	ADC12_CSR_ADRDY_JEOC_SLV_Pos (21U)

#define	ADC12_CSR_ADRDY_JEOC_SLV_Msk (0x1UL << ADC12_CSR_ADRDY_JEOC_SLV_Pos)

#define	ADC12_CSR_ADRDY_JEOC_SLV ADC12_CSR_ADRDY_JEOC_SLV_Msk

#define	ADC12_CSR_ADRDY_JEOS_SLV_Pos (22U)

#define	ADC12_CSR_ADRDY_JEOS_SLV_Msk (0x1UL << ADC12_CSR_ADRDY_JEOS_SLV_Pos)

#define	ADC12_CSR_ADRDY_JEOS_SLV ADC12_CSR_ADRDY_JEOS_SLV_Msk

#define	ADC12_CSR_AWD1_SLV_Pos (23U)

#define	ADC12_CSR_AWD1_SLV_Msk (0x1UL << ADC12_CSR_AWD1_SLV_Pos)

#define	ADC12_CSR_AWD1_SLV ADC12_CSR_AWD1_SLV_Msk

#define	ADC12_CSR_AWD2_SLV_Pos (24U)

#define	ADC12_CSR_AWD2_SLV_Msk (0x1UL << ADC12_CSR_AWD2_SLV_Pos)

#define	ADC12_CSR_AWD2_SLV ADC12_CSR_AWD2_SLV_Msk

#define	ADC12_CSR_AWD3_SLV_Pos (25U)

#define	ADC12_CSR_AWD3_SLV_Msk (0x1UL << ADC12_CSR_AWD3_SLV_Pos)

#define	ADC12_CSR_AWD3_SLV ADC12_CSR_AWD3_SLV_Msk

#define	ADC12_CSR_JQOVF_SLV_Pos (26U)

#define	ADC12_CSR_JQOVF_SLV_Msk (0x1UL << ADC12_CSR_JQOVF_SLV_Pos)

#define	ADC12_CSR_JQOVF_SLV ADC12_CSR_JQOVF_SLV_Msk

#define	ADC34_CSR_ADRDY_MST_Pos (0U)

#define	ADC34_CSR_ADRDY_MST_Msk (0x1UL << ADC34_CSR_ADRDY_MST_Pos)

#define	ADC34_CSR_ADRDY_MST ADC34_CSR_ADRDY_MST_Msk

#define	ADC34_CSR_ADRDY_EOSMP_MST_Pos (1U)

#define	ADC34_CSR_ADRDY_EOSMP_MST_Msk (0x1UL << ADC34_CSR_ADRDY_EOSMP_MST_Pos)

#define	ADC34_CSR_ADRDY_EOSMP_MST ADC34_CSR_ADRDY_EOSMP_MST_Msk

#define	ADC34_CSR_ADRDY_EOC_MST_Pos (2U)

#define	ADC34_CSR_ADRDY_EOC_MST_Msk (0x1UL << ADC34_CSR_ADRDY_EOC_MST_Pos)

#define	ADC34_CSR_ADRDY_EOC_MST ADC34_CSR_ADRDY_EOC_MST_Msk

#define	ADC34_CSR_ADRDY_EOS_MST_Pos (3U)

#define	ADC34_CSR_ADRDY_EOS_MST_Msk (0x1UL << ADC34_CSR_ADRDY_EOS_MST_Pos)

#define	ADC34_CSR_ADRDY_EOS_MST ADC34_CSR_ADRDY_EOS_MST_Msk

#define	ADC34_CSR_ADRDY_OVR_MST_Pos (4U)

#define	ADC34_CSR_ADRDY_OVR_MST_Msk (0x1UL << ADC34_CSR_ADRDY_OVR_MST_Pos)

#define	ADC34_CSR_ADRDY_OVR_MST ADC34_CSR_ADRDY_OVR_MST_Msk

#define	ADC34_CSR_ADRDY_JEOC_MST_Pos (5U)

#define	ADC34_CSR_ADRDY_JEOC_MST_Msk (0x1UL << ADC34_CSR_ADRDY_JEOC_MST_Pos)

#define	ADC34_CSR_ADRDY_JEOC_MST ADC34_CSR_ADRDY_JEOC_MST_Msk

#define	ADC34_CSR_ADRDY_JEOS_MST_Pos (6U)

#define	ADC34_CSR_ADRDY_JEOS_MST_Msk (0x1UL << ADC34_CSR_ADRDY_JEOS_MST_Pos)

#define	ADC34_CSR_ADRDY_JEOS_MST ADC34_CSR_ADRDY_JEOS_MST_Msk

#define	ADC34_CSR_AWD1_MST_Pos (7U)

#define	ADC34_CSR_AWD1_MST_Msk (0x1UL << ADC34_CSR_AWD1_MST_Pos)

#define	ADC34_CSR_AWD1_MST ADC34_CSR_AWD1_MST_Msk

#define	ADC34_CSR_AWD2_MST_Pos (8U)

#define	ADC34_CSR_AWD2_MST_Msk (0x1UL << ADC34_CSR_AWD2_MST_Pos)

#define	ADC34_CSR_AWD2_MST ADC34_CSR_AWD2_MST_Msk

#define	ADC34_CSR_AWD3_MST_Pos (9U)

#define	ADC34_CSR_AWD3_MST_Msk (0x1UL << ADC34_CSR_AWD3_MST_Pos)

#define	ADC34_CSR_AWD3_MST ADC34_CSR_AWD3_MST_Msk

#define	ADC34_CSR_JQOVF_MST_Pos (10U)

#define	ADC34_CSR_JQOVF_MST_Msk (0x1UL << ADC34_CSR_JQOVF_MST_Pos)

#define	ADC34_CSR_JQOVF_MST ADC34_CSR_JQOVF_MST_Msk

#define	ADC34_CSR_ADRDY_SLV_Pos (16U)

#define	ADC34_CSR_ADRDY_SLV_Msk (0x1UL << ADC34_CSR_ADRDY_SLV_Pos)

#define	ADC34_CSR_ADRDY_SLV ADC34_CSR_ADRDY_SLV_Msk

#define	ADC34_CSR_ADRDY_EOSMP_SLV_Pos (17U)

#define	ADC34_CSR_ADRDY_EOSMP_SLV_Msk (0x1UL << ADC34_CSR_ADRDY_EOSMP_SLV_Pos)

#define	ADC34_CSR_ADRDY_EOSMP_SLV ADC34_CSR_ADRDY_EOSMP_SLV_Msk

#define	ADC34_CSR_ADRDY_EOC_SLV_Pos (18U)

#define	ADC34_CSR_ADRDY_EOC_SLV_Msk (0x1UL << ADC34_CSR_ADRDY_EOC_SLV_Pos)

#define	ADC34_CSR_ADRDY_EOC_SLV ADC34_CSR_ADRDY_EOC_SLV_Msk

#define	ADC34_CSR_ADRDY_EOS_SLV_Pos (19U)

#define	ADC34_CSR_ADRDY_EOS_SLV_Msk (0x1UL << ADC34_CSR_ADRDY_EOS_SLV_Pos)

#define	ADC34_CSR_ADRDY_EOS_SLV ADC34_CSR_ADRDY_EOS_SLV_Msk

#define	ADC34_CSR_ADRDY_JEOC_SLV_Pos (21U)

#define	ADC34_CSR_ADRDY_JEOC_SLV_Msk (0x1UL << ADC34_CSR_ADRDY_JEOC_SLV_Pos)

#define	ADC34_CSR_ADRDY_JEOC_SLV ADC34_CSR_ADRDY_JEOC_SLV_Msk

#define	ADC34_CSR_ADRDY_JEOS_SLV_Pos (22U)

#define	ADC34_CSR_ADRDY_JEOS_SLV_Msk (0x1UL << ADC34_CSR_ADRDY_JEOS_SLV_Pos)

#define	ADC34_CSR_ADRDY_JEOS_SLV ADC34_CSR_ADRDY_JEOS_SLV_Msk

#define	ADC34_CSR_AWD1_SLV_Pos (23U)

#define	ADC34_CSR_AWD1_SLV_Msk (0x1UL << ADC34_CSR_AWD1_SLV_Pos)

#define	ADC34_CSR_AWD1_SLV ADC34_CSR_AWD1_SLV_Msk

#define	ADC34_CSR_AWD2_SLV_Pos (24U)

#define	ADC34_CSR_AWD2_SLV_Msk (0x1UL << ADC34_CSR_AWD2_SLV_Pos)

#define	ADC34_CSR_AWD2_SLV ADC34_CSR_AWD2_SLV_Msk

#define	ADC34_CSR_AWD3_SLV_Pos (25U)

#define	ADC34_CSR_AWD3_SLV_Msk (0x1UL << ADC34_CSR_AWD3_SLV_Pos)

#define	ADC34_CSR_AWD3_SLV ADC34_CSR_AWD3_SLV_Msk

#define	ADC34_CSR_JQOVF_SLV_Pos (26U)

#define	ADC34_CSR_JQOVF_SLV_Msk (0x1UL << ADC34_CSR_JQOVF_SLV_Pos)

#define	ADC34_CSR_JQOVF_SLV ADC34_CSR_JQOVF_SLV_Msk

#define	ADC12_CCR_MULTI_Pos (0U)

#define	ADC12_CCR_MULTI_Msk (0x1FUL << ADC12_CCR_MULTI_Pos)

#define	ADC12_CCR_MULTI ADC12_CCR_MULTI_Msk

#define	ADC12_CCR_MULTI_0 (0x01UL << ADC12_CCR_MULTI_Pos)

#define	ADC12_CCR_MULTI_1 (0x02UL << ADC12_CCR_MULTI_Pos)

#define	ADC12_CCR_MULTI_2 (0x04UL << ADC12_CCR_MULTI_Pos)

#define	ADC12_CCR_MULTI_3 (0x08UL << ADC12_CCR_MULTI_Pos)

#define	ADC12_CCR_MULTI_4 (0x10UL << ADC12_CCR_MULTI_Pos)

#define	ADC12_CCR_DELAY_Pos (8U)

#define	ADC12_CCR_DELAY_Msk (0xFUL << ADC12_CCR_DELAY_Pos)

#define	ADC12_CCR_DELAY ADC12_CCR_DELAY_Msk

#define	ADC12_CCR_DELAY_0 (0x1UL << ADC12_CCR_DELAY_Pos)

#define	ADC12_CCR_DELAY_1 (0x2UL << ADC12_CCR_DELAY_Pos)

#define	ADC12_CCR_DELAY_2 (0x4UL << ADC12_CCR_DELAY_Pos)

#define	ADC12_CCR_DELAY_3 (0x8UL << ADC12_CCR_DELAY_Pos)

#define	ADC12_CCR_DMACFG_Pos (13U)

#define	ADC12_CCR_DMACFG_Msk (0x1UL << ADC12_CCR_DMACFG_Pos)

#define	ADC12_CCR_DMACFG ADC12_CCR_DMACFG_Msk

#define	ADC12_CCR_MDMA_Pos (14U)

#define	ADC12_CCR_MDMA_Msk (0x3UL << ADC12_CCR_MDMA_Pos)

#define	ADC12_CCR_MDMA ADC12_CCR_MDMA_Msk

#define	ADC12_CCR_MDMA_0 (0x1UL << ADC12_CCR_MDMA_Pos)

#define	ADC12_CCR_MDMA_1 (0x2UL << ADC12_CCR_MDMA_Pos)

#define	ADC12_CCR_CKMODE_Pos (16U)

#define	ADC12_CCR_CKMODE_Msk (0x3UL << ADC12_CCR_CKMODE_Pos)

#define	ADC12_CCR_CKMODE ADC12_CCR_CKMODE_Msk

#define	ADC12_CCR_CKMODE_0 (0x1UL << ADC12_CCR_CKMODE_Pos)

#define	ADC12_CCR_CKMODE_1 (0x2UL << ADC12_CCR_CKMODE_Pos)

#define	ADC12_CCR_VREFEN_Pos (22U)

#define	ADC12_CCR_VREFEN_Msk (0x1UL << ADC12_CCR_VREFEN_Pos)

#define	ADC12_CCR_VREFEN ADC12_CCR_VREFEN_Msk

#define	ADC12_CCR_TSEN_Pos (23U)

#define	ADC12_CCR_TSEN_Msk (0x1UL << ADC12_CCR_TSEN_Pos)

#define	ADC12_CCR_TSEN ADC12_CCR_TSEN_Msk

#define	ADC12_CCR_VBATEN_Pos (24U)

#define	ADC12_CCR_VBATEN_Msk (0x1UL << ADC12_CCR_VBATEN_Pos)

#define	ADC12_CCR_VBATEN ADC12_CCR_VBATEN_Msk

#define	ADC34_CCR_MULTI_Pos (0U)

#define	ADC34_CCR_MULTI_Msk (0x1FUL << ADC34_CCR_MULTI_Pos)

#define	ADC34_CCR_MULTI ADC34_CCR_MULTI_Msk

#define	ADC34_CCR_MULTI_0 (0x01UL << ADC34_CCR_MULTI_Pos)

#define	ADC34_CCR_MULTI_1 (0x02UL << ADC34_CCR_MULTI_Pos)

#define	ADC34_CCR_MULTI_2 (0x04UL << ADC34_CCR_MULTI_Pos)

#define	ADC34_CCR_MULTI_3 (0x08UL << ADC34_CCR_MULTI_Pos)

#define	ADC34_CCR_MULTI_4 (0x10UL << ADC34_CCR_MULTI_Pos)

#define	ADC34_CCR_DELAY_Pos (8U)

#define	ADC34_CCR_DELAY_Msk (0xFUL << ADC34_CCR_DELAY_Pos)

#define	ADC34_CCR_DELAY ADC34_CCR_DELAY_Msk

#define	ADC34_CCR_DELAY_0 (0x1UL << ADC34_CCR_DELAY_Pos)

#define	ADC34_CCR_DELAY_1 (0x2UL << ADC34_CCR_DELAY_Pos)

#define	ADC34_CCR_DELAY_2 (0x4UL << ADC34_CCR_DELAY_Pos)

#define	ADC34_CCR_DELAY_3 (0x8UL << ADC34_CCR_DELAY_Pos)

#define	ADC34_CCR_DMACFG_Pos (13U)

#define	ADC34_CCR_DMACFG_Msk (0x1UL << ADC34_CCR_DMACFG_Pos)

#define	ADC34_CCR_DMACFG ADC34_CCR_DMACFG_Msk

#define	ADC34_CCR_MDMA_Pos (14U)

#define	ADC34_CCR_MDMA_Msk (0x3UL << ADC34_CCR_MDMA_Pos)

#define	ADC34_CCR_MDMA ADC34_CCR_MDMA_Msk

#define	ADC34_CCR_MDMA_0 (0x1UL << ADC34_CCR_MDMA_Pos)

#define	ADC34_CCR_MDMA_1 (0x2UL << ADC34_CCR_MDMA_Pos)

#define	ADC34_CCR_CKMODE_Pos (16U)

#define	ADC34_CCR_CKMODE_Msk (0x3UL << ADC34_CCR_CKMODE_Pos)

#define	ADC34_CCR_CKMODE ADC34_CCR_CKMODE_Msk

#define	ADC34_CCR_CKMODE_0 (0x1UL << ADC34_CCR_CKMODE_Pos)

#define	ADC34_CCR_CKMODE_1 (0x2UL << ADC34_CCR_CKMODE_Pos)

#define	ADC34_CCR_VREFEN_Pos (22U)

#define	ADC34_CCR_VREFEN_Msk (0x1UL << ADC34_CCR_VREFEN_Pos)

#define	ADC34_CCR_VREFEN ADC34_CCR_VREFEN_Msk

#define	ADC34_CCR_TSEN_Pos (23U)

#define	ADC34_CCR_TSEN_Msk (0x1UL << ADC34_CCR_TSEN_Pos)

#define	ADC34_CCR_TSEN ADC34_CCR_TSEN_Msk

#define	ADC34_CCR_VBATEN_Pos (24U)

#define	ADC34_CCR_VBATEN_Msk (0x1UL << ADC34_CCR_VBATEN_Pos)

#define	ADC34_CCR_VBATEN ADC34_CCR_VBATEN_Msk

#define	ADC12_CDR_RDATA_MST_Pos (0U)

#define	ADC12_CDR_RDATA_MST_Msk (0xFFFFUL << ADC12_CDR_RDATA_MST_Pos)

#define	ADC12_CDR_RDATA_MST ADC12_CDR_RDATA_MST_Msk

#define	ADC12_CDR_RDATA_MST_0 (0x0001UL << ADC12_CDR_RDATA_MST_Pos)

#define	ADC12_CDR_RDATA_MST_1 (0x0002UL << ADC12_CDR_RDATA_MST_Pos)

#define	ADC12_CDR_RDATA_MST_2 (0x0004UL << ADC12_CDR_RDATA_MST_Pos)

#define	ADC12_CDR_RDATA_MST_3 (0x0008UL << ADC12_CDR_RDATA_MST_Pos)

#define	ADC12_CDR_RDATA_MST_4 (0x0010UL << ADC12_CDR_RDATA_MST_Pos)

#define	ADC12_CDR_RDATA_MST_5 (0x0020UL << ADC12_CDR_RDATA_MST_Pos)

#define	ADC12_CDR_RDATA_MST_6 (0x0040UL << ADC12_CDR_RDATA_MST_Pos)

#define	ADC12_CDR_RDATA_MST_7 (0x0080UL << ADC12_CDR_RDATA_MST_Pos)

#define	ADC12_CDR_RDATA_MST_8 (0x0100UL << ADC12_CDR_RDATA_MST_Pos)

#define	ADC12_CDR_RDATA_MST_9 (0x0200UL << ADC12_CDR_RDATA_MST_Pos)

#define	ADC12_CDR_RDATA_MST_10 (0x0400UL << ADC12_CDR_RDATA_MST_Pos)

#define	ADC12_CDR_RDATA_MST_11 (0x0800UL << ADC12_CDR_RDATA_MST_Pos)

#define	ADC12_CDR_RDATA_MST_12 (0x1000UL << ADC12_CDR_RDATA_MST_Pos)

#define	ADC12_CDR_RDATA_MST_13 (0x2000UL << ADC12_CDR_RDATA_MST_Pos)

#define	ADC12_CDR_RDATA_MST_14 (0x4000UL << ADC12_CDR_RDATA_MST_Pos)

#define	ADC12_CDR_RDATA_MST_15 (0x8000UL << ADC12_CDR_RDATA_MST_Pos)

#define	ADC12_CDR_RDATA_SLV_Pos (16U)

#define	ADC12_CDR_RDATA_SLV_Msk (0xFFFFUL << ADC12_CDR_RDATA_SLV_Pos)

#define	ADC12_CDR_RDATA_SLV ADC12_CDR_RDATA_SLV_Msk

#define	ADC12_CDR_RDATA_SLV_0 (0x0001UL << ADC12_CDR_RDATA_SLV_Pos)

#define	ADC12_CDR_RDATA_SLV_1 (0x0002UL << ADC12_CDR_RDATA_SLV_Pos)

#define	ADC12_CDR_RDATA_SLV_2 (0x0004UL << ADC12_CDR_RDATA_SLV_Pos)

#define	ADC12_CDR_RDATA_SLV_3 (0x0008UL << ADC12_CDR_RDATA_SLV_Pos)

#define	ADC12_CDR_RDATA_SLV_4 (0x0010UL << ADC12_CDR_RDATA_SLV_Pos)

#define	ADC12_CDR_RDATA_SLV_5 (0x0020UL << ADC12_CDR_RDATA_SLV_Pos)

#define	ADC12_CDR_RDATA_SLV_6 (0x0040UL << ADC12_CDR_RDATA_SLV_Pos)

#define	ADC12_CDR_RDATA_SLV_7 (0x0080UL << ADC12_CDR_RDATA_SLV_Pos)

#define	ADC12_CDR_RDATA_SLV_8 (0x0100UL << ADC12_CDR_RDATA_SLV_Pos)

#define	ADC12_CDR_RDATA_SLV_9 (0x0200UL << ADC12_CDR_RDATA_SLV_Pos)

#define	ADC12_CDR_RDATA_SLV_10 (0x0400UL << ADC12_CDR_RDATA_SLV_Pos)

#define	ADC12_CDR_RDATA_SLV_11 (0x0800UL << ADC12_CDR_RDATA_SLV_Pos)

#define	ADC12_CDR_RDATA_SLV_12 (0x1000UL << ADC12_CDR_RDATA_SLV_Pos)

#define	ADC12_CDR_RDATA_SLV_13 (0x2000UL << ADC12_CDR_RDATA_SLV_Pos)

#define	ADC12_CDR_RDATA_SLV_14 (0x4000UL << ADC12_CDR_RDATA_SLV_Pos)

#define	ADC12_CDR_RDATA_SLV_15 (0x8000UL << ADC12_CDR_RDATA_SLV_Pos)

#define	ADC34_CDR_RDATA_MST_Pos (0U)

#define	ADC34_CDR_RDATA_MST_Msk (0xFFFFUL << ADC34_CDR_RDATA_MST_Pos)

#define	ADC34_CDR_RDATA_MST ADC34_CDR_RDATA_MST_Msk

#define	ADC34_CDR_RDATA_MST_0 (0x0001UL << ADC34_CDR_RDATA_MST_Pos)

#define	ADC34_CDR_RDATA_MST_1 (0x0002UL << ADC34_CDR_RDATA_MST_Pos)

#define	ADC34_CDR_RDATA_MST_2 (0x0004UL << ADC34_CDR_RDATA_MST_Pos)

#define	ADC34_CDR_RDATA_MST_3 (0x0008UL << ADC34_CDR_RDATA_MST_Pos)

#define	ADC34_CDR_RDATA_MST_4 (0x0010UL << ADC34_CDR_RDATA_MST_Pos)

#define	ADC34_CDR_RDATA_MST_5 (0x0020UL << ADC34_CDR_RDATA_MST_Pos)

#define	ADC34_CDR_RDATA_MST_6 (0x0040UL << ADC34_CDR_RDATA_MST_Pos)

#define	ADC34_CDR_RDATA_MST_7 (0x0080UL << ADC34_CDR_RDATA_MST_Pos)

#define	ADC34_CDR_RDATA_MST_8 (0x0100UL << ADC34_CDR_RDATA_MST_Pos)

#define	ADC34_CDR_RDATA_MST_9 (0x0200UL << ADC34_CDR_RDATA_MST_Pos)

#define	ADC34_CDR_RDATA_MST_10 (0x0400UL << ADC34_CDR_RDATA_MST_Pos)

#define	ADC34_CDR_RDATA_MST_11 (0x0800UL << ADC34_CDR_RDATA_MST_Pos)

#define	ADC34_CDR_RDATA_MST_12 (0x1000UL << ADC34_CDR_RDATA_MST_Pos)

#define	ADC34_CDR_RDATA_MST_13 (0x2000UL << ADC34_CDR_RDATA_MST_Pos)

#define	ADC34_CDR_RDATA_MST_14 (0x4000UL << ADC34_CDR_RDATA_MST_Pos)

#define	ADC34_CDR_RDATA_MST_15 (0x8000UL << ADC34_CDR_RDATA_MST_Pos)

#define	ADC34_CDR_RDATA_SLV_Pos (16U)

#define	ADC34_CDR_RDATA_SLV_Msk (0xFFFFUL << ADC34_CDR_RDATA_SLV_Pos)

#define	ADC34_CDR_RDATA_SLV ADC34_CDR_RDATA_SLV_Msk

#define	ADC34_CDR_RDATA_SLV_0 (0x0001UL << ADC34_CDR_RDATA_SLV_Pos)

#define	ADC34_CDR_RDATA_SLV_1 (0x0002UL << ADC34_CDR_RDATA_SLV_Pos)

#define	ADC34_CDR_RDATA_SLV_2 (0x0004UL << ADC34_CDR_RDATA_SLV_Pos)

#define	ADC34_CDR_RDATA_SLV_3 (0x0008UL << ADC34_CDR_RDATA_SLV_Pos)

#define	ADC34_CDR_RDATA_SLV_4 (0x0010UL << ADC34_CDR_RDATA_SLV_Pos)

#define	ADC34_CDR_RDATA_SLV_5 (0x0020UL << ADC34_CDR_RDATA_SLV_Pos)

#define	ADC34_CDR_RDATA_SLV_6 (0x0040UL << ADC34_CDR_RDATA_SLV_Pos)

#define	ADC34_CDR_RDATA_SLV_7 (0x0080UL << ADC34_CDR_RDATA_SLV_Pos)

#define	ADC34_CDR_RDATA_SLV_8 (0x0100UL << ADC34_CDR_RDATA_SLV_Pos)

#define	ADC34_CDR_RDATA_SLV_9 (0x0200UL << ADC34_CDR_RDATA_SLV_Pos)

#define	ADC34_CDR_RDATA_SLV_10 (0x0400UL << ADC34_CDR_RDATA_SLV_Pos)

#define	ADC34_CDR_RDATA_SLV_11 (0x0800UL << ADC34_CDR_RDATA_SLV_Pos)

#define	ADC34_CDR_RDATA_SLV_12 (0x1000UL << ADC34_CDR_RDATA_SLV_Pos)

#define	ADC34_CDR_RDATA_SLV_13 (0x2000UL << ADC34_CDR_RDATA_SLV_Pos)

#define	ADC34_CDR_RDATA_SLV_14 (0x4000UL << ADC34_CDR_RDATA_SLV_Pos)

#define	ADC34_CDR_RDATA_SLV_15 (0x8000UL << ADC34_CDR_RDATA_SLV_Pos)

#define	ADC_CSR_ADRDY_MST_Pos (0U)

#define	ADC_CSR_ADRDY_MST_Msk (0x1UL << ADC_CSR_ADRDY_MST_Pos)

#define	ADC_CSR_ADRDY_MST ADC_CSR_ADRDY_MST_Msk

#define	ADC_CSR_EOSMP_MST_Pos (1U)

#define	ADC_CSR_EOSMP_MST_Msk (0x1UL << ADC_CSR_EOSMP_MST_Pos)

#define	ADC_CSR_EOSMP_MST ADC_CSR_EOSMP_MST_Msk

#define	ADC_CSR_EOC_MST_Pos (2U)

#define	ADC_CSR_EOC_MST_Msk (0x1UL << ADC_CSR_EOC_MST_Pos)

#define	ADC_CSR_EOC_MST ADC_CSR_EOC_MST_Msk

#define	ADC_CSR_EOS_MST_Pos (3U)

#define	ADC_CSR_EOS_MST_Msk (0x1UL << ADC_CSR_EOS_MST_Pos)

#define	ADC_CSR_EOS_MST ADC_CSR_EOS_MST_Msk

#define	ADC_CSR_OVR_MST_Pos (4U)

#define	ADC_CSR_OVR_MST_Msk (0x1UL << ADC_CSR_OVR_MST_Pos)

#define	ADC_CSR_OVR_MST ADC_CSR_OVR_MST_Msk

#define	ADC_CSR_JEOC_MST_Pos (5U)

#define	ADC_CSR_JEOC_MST_Msk (0x1UL << ADC_CSR_JEOC_MST_Pos)

#define	ADC_CSR_JEOC_MST ADC_CSR_JEOC_MST_Msk

#define	ADC_CSR_JEOS_MST_Pos (6U)

#define	ADC_CSR_JEOS_MST_Msk (0x1UL << ADC_CSR_JEOS_MST_Pos)

#define	ADC_CSR_JEOS_MST ADC_CSR_JEOS_MST_Msk

#define	ADC_CSR_AWD1_MST_Pos (7U)

#define	ADC_CSR_AWD1_MST_Msk (0x1UL << ADC_CSR_AWD1_MST_Pos)

#define	ADC_CSR_AWD1_MST ADC_CSR_AWD1_MST_Msk

#define	ADC_CSR_AWD2_MST_Pos (8U)

#define	ADC_CSR_AWD2_MST_Msk (0x1UL << ADC_CSR_AWD2_MST_Pos)

#define	ADC_CSR_AWD2_MST ADC_CSR_AWD2_MST_Msk

#define	ADC_CSR_AWD3_MST_Pos (9U)

#define	ADC_CSR_AWD3_MST_Msk (0x1UL << ADC_CSR_AWD3_MST_Pos)

#define	ADC_CSR_AWD3_MST ADC_CSR_AWD3_MST_Msk

#define	ADC_CSR_JQOVF_MST_Pos (10U)

#define	ADC_CSR_JQOVF_MST_Msk (0x1UL << ADC_CSR_JQOVF_MST_Pos)

#define	ADC_CSR_JQOVF_MST ADC_CSR_JQOVF_MST_Msk

#define	ADC_CSR_ADRDY_SLV_Pos (16U)

#define	ADC_CSR_ADRDY_SLV_Msk (0x1UL << ADC_CSR_ADRDY_SLV_Pos)

#define	ADC_CSR_ADRDY_SLV ADC_CSR_ADRDY_SLV_Msk

#define	ADC_CSR_EOSMP_SLV_Pos (17U)

#define	ADC_CSR_EOSMP_SLV_Msk (0x1UL << ADC_CSR_EOSMP_SLV_Pos)

#define	ADC_CSR_EOSMP_SLV ADC_CSR_EOSMP_SLV_Msk

#define	ADC_CSR_EOC_SLV_Pos (18U)

#define	ADC_CSR_EOC_SLV_Msk (0x1UL << ADC_CSR_EOC_SLV_Pos)

#define	ADC_CSR_EOC_SLV ADC_CSR_EOC_SLV_Msk

#define	ADC_CSR_EOS_SLV_Pos (19U)

#define	ADC_CSR_EOS_SLV_Msk (0x1UL << ADC_CSR_EOS_SLV_Pos)

#define	ADC_CSR_EOS_SLV ADC_CSR_EOS_SLV_Msk

#define	ADC_CSR_OVR_SLV_Pos (20U)

#define	ADC_CSR_OVR_SLV_Msk (0x1UL << ADC_CSR_OVR_SLV_Pos)

#define	ADC_CSR_OVR_SLV ADC_CSR_OVR_SLV_Msk

#define	ADC_CSR_JEOC_SLV_Pos (21U)

#define	ADC_CSR_JEOC_SLV_Msk (0x1UL << ADC_CSR_JEOC_SLV_Pos)

#define	ADC_CSR_JEOC_SLV ADC_CSR_JEOC_SLV_Msk

#define	ADC_CSR_JEOS_SLV_Pos (22U)

#define	ADC_CSR_JEOS_SLV_Msk (0x1UL << ADC_CSR_JEOS_SLV_Pos)

#define	ADC_CSR_JEOS_SLV ADC_CSR_JEOS_SLV_Msk

#define	ADC_CSR_AWD1_SLV_Pos (23U)

#define	ADC_CSR_AWD1_SLV_Msk (0x1UL << ADC_CSR_AWD1_SLV_Pos)

#define	ADC_CSR_AWD1_SLV ADC_CSR_AWD1_SLV_Msk

#define	ADC_CSR_AWD2_SLV_Pos (24U)

#define	ADC_CSR_AWD2_SLV_Msk (0x1UL << ADC_CSR_AWD2_SLV_Pos)

#define	ADC_CSR_AWD2_SLV ADC_CSR_AWD2_SLV_Msk

#define	ADC_CSR_AWD3_SLV_Pos (25U)

#define	ADC_CSR_AWD3_SLV_Msk (0x1UL << ADC_CSR_AWD3_SLV_Pos)

#define	ADC_CSR_AWD3_SLV ADC_CSR_AWD3_SLV_Msk

#define	ADC_CSR_JQOVF_SLV_Pos (26U)

#define	ADC_CSR_JQOVF_SLV_Msk (0x1UL << ADC_CSR_JQOVF_SLV_Pos)

#define	ADC_CSR_JQOVF_SLV ADC_CSR_JQOVF_SLV_Msk

#define	ADC_CSR_ADRDY_EOSMP_MST ADC_CSR_EOSMP_MST

#define	ADC_CSR_ADRDY_EOC_MST ADC_CSR_EOC_MST

#define	ADC_CSR_ADRDY_EOS_MST ADC_CSR_EOS_MST

#define	ADC_CSR_ADRDY_OVR_MST ADC_CSR_OVR_MST

#define	ADC_CSR_ADRDY_JEOC_MST ADC_CSR_JEOC_MST

#define	ADC_CSR_ADRDY_JEOS_MST ADC_CSR_JEOS_MST

#define	ADC_CSR_ADRDY_EOSMP_SLV ADC_CSR_EOSMP_SLV

#define	ADC_CSR_ADRDY_EOC_SLV ADC_CSR_EOC_SLV

#define	ADC_CSR_ADRDY_EOS_SLV ADC_CSR_EOS_SLV

#define	ADC_CSR_ADRDY_OVR_SLV ADC_CSR_OVR_SLV

#define	ADC_CSR_ADRDY_JEOC_SLV ADC_CSR_JEOC_SLV

#define	ADC_CSR_ADRDY_JEOS_SLV ADC_CSR_JEOS_SLV

#define	ADC_CCR_DUAL_Pos (0U)

#define	ADC_CCR_DUAL_Msk (0x1FUL << ADC_CCR_DUAL_Pos)

#define	ADC_CCR_DUAL ADC_CCR_DUAL_Msk

#define	ADC_CCR_DUAL_0 (0x01UL << ADC_CCR_DUAL_Pos)

#define	ADC_CCR_DUAL_1 (0x02UL << ADC_CCR_DUAL_Pos)

#define	ADC_CCR_DUAL_2 (0x04UL << ADC_CCR_DUAL_Pos)

#define	ADC_CCR_DUAL_3 (0x08UL << ADC_CCR_DUAL_Pos)

#define	ADC_CCR_DUAL_4 (0x10UL << ADC_CCR_DUAL_Pos)

#define	ADC_CCR_DELAY_Pos (8U)

#define	ADC_CCR_DELAY_Msk (0xFUL << ADC_CCR_DELAY_Pos)

#define	ADC_CCR_DELAY ADC_CCR_DELAY_Msk

#define	ADC_CCR_DELAY_0 (0x1UL << ADC_CCR_DELAY_Pos)

#define	ADC_CCR_DELAY_1 (0x2UL << ADC_CCR_DELAY_Pos)

#define	ADC_CCR_DELAY_2 (0x4UL << ADC_CCR_DELAY_Pos)

#define	ADC_CCR_DELAY_3 (0x8UL << ADC_CCR_DELAY_Pos)

#define	ADC_CCR_DMACFG_Pos (13U)

#define	ADC_CCR_DMACFG_Msk (0x1UL << ADC_CCR_DMACFG_Pos)

#define	ADC_CCR_DMACFG ADC_CCR_DMACFG_Msk

#define	ADC_CCR_MDMA_Pos (14U)

#define	ADC_CCR_MDMA_Msk (0x3UL << ADC_CCR_MDMA_Pos)

#define	ADC_CCR_MDMA ADC_CCR_MDMA_Msk

#define	ADC_CCR_MDMA_0 (0x1UL << ADC_CCR_MDMA_Pos)

#define	ADC_CCR_MDMA_1 (0x2UL << ADC_CCR_MDMA_Pos)

#define	ADC_CCR_CKMODE_Pos (16U)

#define	ADC_CCR_CKMODE_Msk (0x3UL << ADC_CCR_CKMODE_Pos)

#define	ADC_CCR_CKMODE ADC_CCR_CKMODE_Msk

#define	ADC_CCR_CKMODE_0 (0x1UL << ADC_CCR_CKMODE_Pos)

#define	ADC_CCR_CKMODE_1 (0x2UL << ADC_CCR_CKMODE_Pos)

#define	ADC_CCR_VREFEN_Pos (22U)

#define	ADC_CCR_VREFEN_Msk (0x1UL << ADC_CCR_VREFEN_Pos)

#define	ADC_CCR_VREFEN ADC_CCR_VREFEN_Msk

#define	ADC_CCR_TSEN_Pos (23U)

#define	ADC_CCR_TSEN_Msk (0x1UL << ADC_CCR_TSEN_Pos)

#define	ADC_CCR_TSEN ADC_CCR_TSEN_Msk

#define	ADC_CCR_VBATEN_Pos (24U)

#define	ADC_CCR_VBATEN_Msk (0x1UL << ADC_CCR_VBATEN_Pos)

#define	ADC_CCR_VBATEN ADC_CCR_VBATEN_Msk

#define	ADC_CCR_MULTI (ADC_CCR_DUAL)

#define	ADC_CCR_MULTI_0 (ADC_CCR_DUAL_0)

#define	ADC_CCR_MULTI_1 (ADC_CCR_DUAL_1)

#define	ADC_CCR_MULTI_2 (ADC_CCR_DUAL_2)

#define	ADC_CCR_MULTI_3 (ADC_CCR_DUAL_3)

#define	ADC_CCR_MULTI_4 (ADC_CCR_DUAL_4)

#define	ADC_CDR_RDATA_MST_Pos (0U)

#define	ADC_CDR_RDATA_MST_Msk (0xFFFFUL << ADC_CDR_RDATA_MST_Pos)

#define	ADC_CDR_RDATA_MST ADC_CDR_RDATA_MST_Msk

#define	ADC_CDR_RDATA_MST_0 (0x0001UL << ADC_CDR_RDATA_MST_Pos)

#define	ADC_CDR_RDATA_MST_1 (0x0002UL << ADC_CDR_RDATA_MST_Pos)

#define	ADC_CDR_RDATA_MST_2 (0x0004UL << ADC_CDR_RDATA_MST_Pos)

#define	ADC_CDR_RDATA_MST_3 (0x0008UL << ADC_CDR_RDATA_MST_Pos)

#define	ADC_CDR_RDATA_MST_4 (0x0010UL << ADC_CDR_RDATA_MST_Pos)

#define	ADC_CDR_RDATA_MST_5 (0x0020UL << ADC_CDR_RDATA_MST_Pos)

#define	ADC_CDR_RDATA_MST_6 (0x0040UL << ADC_CDR_RDATA_MST_Pos)

#define	ADC_CDR_RDATA_MST_7 (0x0080UL << ADC_CDR_RDATA_MST_Pos)

#define	ADC_CDR_RDATA_MST_8 (0x0100UL << ADC_CDR_RDATA_MST_Pos)

#define	ADC_CDR_RDATA_MST_9 (0x0200UL << ADC_CDR_RDATA_MST_Pos)

#define	ADC_CDR_RDATA_MST_10 (0x0400UL << ADC_CDR_RDATA_MST_Pos)

#define	ADC_CDR_RDATA_MST_11 (0x0800UL << ADC_CDR_RDATA_MST_Pos)

#define	ADC_CDR_RDATA_MST_12 (0x1000UL << ADC_CDR_RDATA_MST_Pos)

#define	ADC_CDR_RDATA_MST_13 (0x2000UL << ADC_CDR_RDATA_MST_Pos)

#define	ADC_CDR_RDATA_MST_14 (0x4000UL << ADC_CDR_RDATA_MST_Pos)

#define	ADC_CDR_RDATA_MST_15 (0x8000UL << ADC_CDR_RDATA_MST_Pos)

#define	ADC_CDR_RDATA_SLV_Pos (16U)

#define	ADC_CDR_RDATA_SLV_Msk (0xFFFFUL << ADC_CDR_RDATA_SLV_Pos)

#define	ADC_CDR_RDATA_SLV ADC_CDR_RDATA_SLV_Msk

#define	ADC_CDR_RDATA_SLV_0 (0x0001UL << ADC_CDR_RDATA_SLV_Pos)

#define	ADC_CDR_RDATA_SLV_1 (0x0002UL << ADC_CDR_RDATA_SLV_Pos)

#define	ADC_CDR_RDATA_SLV_2 (0x0004UL << ADC_CDR_RDATA_SLV_Pos)

#define	ADC_CDR_RDATA_SLV_3 (0x0008UL << ADC_CDR_RDATA_SLV_Pos)

#define	ADC_CDR_RDATA_SLV_4 (0x0010UL << ADC_CDR_RDATA_SLV_Pos)

#define	ADC_CDR_RDATA_SLV_5 (0x0020UL << ADC_CDR_RDATA_SLV_Pos)

#define	ADC_CDR_RDATA_SLV_6 (0x0040UL << ADC_CDR_RDATA_SLV_Pos)

#define	ADC_CDR_RDATA_SLV_7 (0x0080UL << ADC_CDR_RDATA_SLV_Pos)

#define	ADC_CDR_RDATA_SLV_8 (0x0100UL << ADC_CDR_RDATA_SLV_Pos)

#define	ADC_CDR_RDATA_SLV_9 (0x0200UL << ADC_CDR_RDATA_SLV_Pos)

#define	ADC_CDR_RDATA_SLV_10 (0x0400UL << ADC_CDR_RDATA_SLV_Pos)

#define	ADC_CDR_RDATA_SLV_11 (0x0800UL << ADC_CDR_RDATA_SLV_Pos)

#define	ADC_CDR_RDATA_SLV_12 (0x1000UL << ADC_CDR_RDATA_SLV_Pos)

#define	ADC_CDR_RDATA_SLV_13 (0x2000UL << ADC_CDR_RDATA_SLV_Pos)

#define	ADC_CDR_RDATA_SLV_14 (0x4000UL << ADC_CDR_RDATA_SLV_Pos)

#define	ADC_CDR_RDATA_SLV_15 (0x8000UL << ADC_CDR_RDATA_SLV_Pos)

#define	COMP_V1_3_0_0

#define	COMP1_CSR_COMP1EN_Pos (0U)

#define	COMP1_CSR_COMP1EN_Msk (0x1UL << COMP1_CSR_COMP1EN_Pos)

#define	COMP1_CSR_COMP1EN COMP1_CSR_COMP1EN_Msk

#define	COMP1_CSR_COMP1SW1_Pos (1U)

#define	COMP1_CSR_COMP1SW1_Msk (0x1UL << COMP1_CSR_COMP1SW1_Pos)

#define	COMP1_CSR_COMP1SW1 COMP1_CSR_COMP1SW1_Msk

#define	COMP_CSR_COMP1SW1 COMP1_CSR_COMP1SW1

#define	COMP1_CSR_COMP1INSEL_Pos (4U)

#define	COMP1_CSR_COMP1INSEL_Msk (0x7UL << COMP1_CSR_COMP1INSEL_Pos)

#define	COMP1_CSR_COMP1INSEL COMP1_CSR_COMP1INSEL_Msk

#define	COMP1_CSR_COMP1INSEL_0 (0x1UL << COMP1_CSR_COMP1INSEL_Pos)

#define	COMP1_CSR_COMP1INSEL_1 (0x2UL << COMP1_CSR_COMP1INSEL_Pos)

#define	COMP1_CSR_COMP1INSEL_2 (0x4UL << COMP1_CSR_COMP1INSEL_Pos)

#define	COMP1_CSR_COMP1OUTSEL_Pos (10U)

#define	COMP1_CSR_COMP1OUTSEL_Msk (0xFUL << COMP1_CSR_COMP1OUTSEL_Pos)

#define	COMP1_CSR_COMP1OUTSEL COMP1_CSR_COMP1OUTSEL_Msk

#define	COMP1_CSR_COMP1OUTSEL_0 (0x1UL << COMP1_CSR_COMP1OUTSEL_Pos)

#define	COMP1_CSR_COMP1OUTSEL_1 (0x2UL << COMP1_CSR_COMP1OUTSEL_Pos)

#define	COMP1_CSR_COMP1OUTSEL_2 (0x4UL << COMP1_CSR_COMP1OUTSEL_Pos)

#define	COMP1_CSR_COMP1OUTSEL_3 (0x8UL << COMP1_CSR_COMP1OUTSEL_Pos)

#define	COMP1_CSR_COMP1POL_Pos (15U)

#define	COMP1_CSR_COMP1POL_Msk (0x1UL << COMP1_CSR_COMP1POL_Pos)

#define	COMP1_CSR_COMP1POL COMP1_CSR_COMP1POL_Msk

#define	COMP1_CSR_COMP1BLANKING_Pos (18U)

#define	COMP1_CSR_COMP1BLANKING_Msk (0x3UL << COMP1_CSR_COMP1BLANKING_Pos)

#define	COMP1_CSR_COMP1BLANKING COMP1_CSR_COMP1BLANKING_Msk

#define	COMP1_CSR_COMP1BLANKING_0 (0x1UL << COMP1_CSR_COMP1BLANKING_Pos)

#define	COMP1_CSR_COMP1BLANKING_1 (0x2UL << COMP1_CSR_COMP1BLANKING_Pos)

#define	COMP1_CSR_COMP1BLANKING_2 (0x4UL << COMP1_CSR_COMP1BLANKING_Pos)

#define	COMP1_CSR_COMP1OUT_Pos (30U)

#define	COMP1_CSR_COMP1OUT_Msk (0x1UL << COMP1_CSR_COMP1OUT_Pos)

#define	COMP1_CSR_COMP1OUT COMP1_CSR_COMP1OUT_Msk

#define	COMP1_CSR_COMP1LOCK_Pos (31U)

#define	COMP1_CSR_COMP1LOCK_Msk (0x1UL << COMP1_CSR_COMP1LOCK_Pos)

#define	COMP1_CSR_COMP1LOCK COMP1_CSR_COMP1LOCK_Msk

#define	COMP2_CSR_COMP2EN_Pos (0U)

#define	COMP2_CSR_COMP2EN_Msk (0x1UL << COMP2_CSR_COMP2EN_Pos)

#define	COMP2_CSR_COMP2EN COMP2_CSR_COMP2EN_Msk

#define	COMP2_CSR_COMP2INSEL_Pos (4U)

#define	COMP2_CSR_COMP2INSEL_Msk (0x7UL << COMP2_CSR_COMP2INSEL_Pos)

#define	COMP2_CSR_COMP2INSEL COMP2_CSR_COMP2INSEL_Msk

#define	COMP2_CSR_COMP2INSEL_0 (0x00000010U)

#define	COMP2_CSR_COMP2INSEL_1 (0x00000020U)

#define	COMP2_CSR_COMP2INSEL_2 (0x00000040U)

#define	COMP2_CSR_COMP2OUTSEL_Pos (10U)

#define	COMP2_CSR_COMP2OUTSEL_Msk (0xFUL << COMP2_CSR_COMP2OUTSEL_Pos)

#define	COMP2_CSR_COMP2OUTSEL COMP2_CSR_COMP2OUTSEL_Msk

#define	COMP2_CSR_COMP2OUTSEL_0 (0x1UL << COMP2_CSR_COMP2OUTSEL_Pos)

#define	COMP2_CSR_COMP2OUTSEL_1 (0x2UL << COMP2_CSR_COMP2OUTSEL_Pos)

#define	COMP2_CSR_COMP2OUTSEL_2 (0x4UL << COMP2_CSR_COMP2OUTSEL_Pos)

#define	COMP2_CSR_COMP2OUTSEL_3 (0x8UL << COMP2_CSR_COMP2OUTSEL_Pos)

#define	COMP2_CSR_COMP2POL_Pos (15U)

#define	COMP2_CSR_COMP2POL_Msk (0x1UL << COMP2_CSR_COMP2POL_Pos)

#define	COMP2_CSR_COMP2POL COMP2_CSR_COMP2POL_Msk

#define	COMP2_CSR_COMP2BLANKING_Pos (18U)

#define	COMP2_CSR_COMP2BLANKING_Msk (0x3UL << COMP2_CSR_COMP2BLANKING_Pos)

#define	COMP2_CSR_COMP2BLANKING COMP2_CSR_COMP2BLANKING_Msk

#define	COMP2_CSR_COMP2BLANKING_0 (0x1UL << COMP2_CSR_COMP2BLANKING_Pos)

#define	COMP2_CSR_COMP2BLANKING_1 (0x2UL << COMP2_CSR_COMP2BLANKING_Pos)

#define	COMP2_CSR_COMP2BLANKING_2 (0x4UL << COMP2_CSR_COMP2BLANKING_Pos)

#define	COMP2_CSR_COMP2OUT_Pos (30U)

#define	COMP2_CSR_COMP2OUT_Msk (0x1UL << COMP2_CSR_COMP2OUT_Pos)

#define	COMP2_CSR_COMP2OUT COMP2_CSR_COMP2OUT_Msk

#define	COMP2_CSR_COMP2LOCK_Pos (31U)

#define	COMP2_CSR_COMP2LOCK_Msk (0x1UL << COMP2_CSR_COMP2LOCK_Pos)

#define	COMP2_CSR_COMP2LOCK COMP2_CSR_COMP2LOCK_Msk

#define	COMP3_CSR_COMP3EN_Pos (0U)

#define	COMP3_CSR_COMP3EN_Msk (0x1UL << COMP3_CSR_COMP3EN_Pos)

#define	COMP3_CSR_COMP3EN COMP3_CSR_COMP3EN_Msk

#define	COMP3_CSR_COMP3INSEL_Pos (4U)

#define	COMP3_CSR_COMP3INSEL_Msk (0x7UL << COMP3_CSR_COMP3INSEL_Pos)

#define	COMP3_CSR_COMP3INSEL COMP3_CSR_COMP3INSEL_Msk

#define	COMP3_CSR_COMP3INSEL_0 (0x1UL << COMP3_CSR_COMP3INSEL_Pos)

#define	COMP3_CSR_COMP3INSEL_1 (0x2UL << COMP3_CSR_COMP3INSEL_Pos)

#define	COMP3_CSR_COMP3INSEL_2 (0x4UL << COMP3_CSR_COMP3INSEL_Pos)

#define	COMP3_CSR_COMP3OUTSEL_Pos (10U)

#define	COMP3_CSR_COMP3OUTSEL_Msk (0xFUL << COMP3_CSR_COMP3OUTSEL_Pos)

#define	COMP3_CSR_COMP3OUTSEL COMP3_CSR_COMP3OUTSEL_Msk

#define	COMP3_CSR_COMP3OUTSEL_0 (0x1UL << COMP3_CSR_COMP3OUTSEL_Pos)

#define	COMP3_CSR_COMP3OUTSEL_1 (0x2UL << COMP3_CSR_COMP3OUTSEL_Pos)

#define	COMP3_CSR_COMP3OUTSEL_2 (0x4UL << COMP3_CSR_COMP3OUTSEL_Pos)

#define	COMP3_CSR_COMP3OUTSEL_3 (0x8UL << COMP3_CSR_COMP3OUTSEL_Pos)

#define	COMP3_CSR_COMP3POL_Pos (15U)

#define	COMP3_CSR_COMP3POL_Msk (0x1UL << COMP3_CSR_COMP3POL_Pos)

#define	COMP3_CSR_COMP3POL COMP3_CSR_COMP3POL_Msk

#define	COMP3_CSR_COMP3BLANKING_Pos (18U)

#define	COMP3_CSR_COMP3BLANKING_Msk (0x3UL << COMP3_CSR_COMP3BLANKING_Pos)

#define	COMP3_CSR_COMP3BLANKING COMP3_CSR_COMP3BLANKING_Msk

#define	COMP3_CSR_COMP3BLANKING_0 (0x1UL << COMP3_CSR_COMP3BLANKING_Pos)

#define	COMP3_CSR_COMP3BLANKING_1 (0x2UL << COMP3_CSR_COMP3BLANKING_Pos)

#define	COMP3_CSR_COMP3BLANKING_2 (0x4UL << COMP3_CSR_COMP3BLANKING_Pos)

#define	COMP3_CSR_COMP3OUT_Pos (30U)

#define	COMP3_CSR_COMP3OUT_Msk (0x1UL << COMP3_CSR_COMP3OUT_Pos)

#define	COMP3_CSR_COMP3OUT COMP3_CSR_COMP3OUT_Msk

#define	COMP3_CSR_COMP3LOCK_Pos (31U)

#define	COMP3_CSR_COMP3LOCK_Msk (0x1UL << COMP3_CSR_COMP3LOCK_Pos)

#define	COMP3_CSR_COMP3LOCK COMP3_CSR_COMP3LOCK_Msk

#define	COMP4_CSR_COMP4EN_Pos (0U)

#define	COMP4_CSR_COMP4EN_Msk (0x1UL << COMP4_CSR_COMP4EN_Pos)

#define	COMP4_CSR_COMP4EN COMP4_CSR_COMP4EN_Msk

#define	COMP4_CSR_COMP4INSEL_Pos (4U)

#define	COMP4_CSR_COMP4INSEL_Msk (0x7UL << COMP4_CSR_COMP4INSEL_Pos)

#define	COMP4_CSR_COMP4INSEL COMP4_CSR_COMP4INSEL_Msk

#define	COMP4_CSR_COMP4INSEL_0 (0x00000010U)

#define	COMP4_CSR_COMP4INSEL_1 (0x00000020U)

#define	COMP4_CSR_COMP4INSEL_2 (0x00000040U)

#define	COMP4_CSR_COMP4OUTSEL_Pos (10U)

#define	COMP4_CSR_COMP4OUTSEL_Msk (0xFUL << COMP4_CSR_COMP4OUTSEL_Pos)

#define	COMP4_CSR_COMP4OUTSEL COMP4_CSR_COMP4OUTSEL_Msk

#define	COMP4_CSR_COMP4OUTSEL_0 (0x1UL << COMP4_CSR_COMP4OUTSEL_Pos)

#define	COMP4_CSR_COMP4OUTSEL_1 (0x2UL << COMP4_CSR_COMP4OUTSEL_Pos)

#define	COMP4_CSR_COMP4OUTSEL_2 (0x4UL << COMP4_CSR_COMP4OUTSEL_Pos)

#define	COMP4_CSR_COMP4OUTSEL_3 (0x8UL << COMP4_CSR_COMP4OUTSEL_Pos)

#define	COMP4_CSR_COMP4POL_Pos (15U)

#define	COMP4_CSR_COMP4POL_Msk (0x1UL << COMP4_CSR_COMP4POL_Pos)

#define	COMP4_CSR_COMP4POL COMP4_CSR_COMP4POL_Msk

#define	COMP4_CSR_COMP4BLANKING_Pos (18U)

#define	COMP4_CSR_COMP4BLANKING_Msk (0x3UL << COMP4_CSR_COMP4BLANKING_Pos)

#define	COMP4_CSR_COMP4BLANKING COMP4_CSR_COMP4BLANKING_Msk

#define	COMP4_CSR_COMP4BLANKING_0 (0x1UL << COMP4_CSR_COMP4BLANKING_Pos)

#define	COMP4_CSR_COMP4BLANKING_1 (0x2UL << COMP4_CSR_COMP4BLANKING_Pos)

#define	COMP4_CSR_COMP4BLANKING_2 (0x4UL << COMP4_CSR_COMP4BLANKING_Pos)

#define	COMP4_CSR_COMP4OUT_Pos (30U)

#define	COMP4_CSR_COMP4OUT_Msk (0x1UL << COMP4_CSR_COMP4OUT_Pos)

#define	COMP4_CSR_COMP4OUT COMP4_CSR_COMP4OUT_Msk

#define	COMP4_CSR_COMP4LOCK_Pos (31U)

#define	COMP4_CSR_COMP4LOCK_Msk (0x1UL << COMP4_CSR_COMP4LOCK_Pos)

#define	COMP4_CSR_COMP4LOCK COMP4_CSR_COMP4LOCK_Msk

#define	COMP5_CSR_COMP5EN_Pos (0U)

#define	COMP5_CSR_COMP5EN_Msk (0x1UL << COMP5_CSR_COMP5EN_Pos)

#define	COMP5_CSR_COMP5EN COMP5_CSR_COMP5EN_Msk

#define	COMP5_CSR_COMP5INSEL_Pos (4U)

#define	COMP5_CSR_COMP5INSEL_Msk (0x7UL << COMP5_CSR_COMP5INSEL_Pos)

#define	COMP5_CSR_COMP5INSEL COMP5_CSR_COMP5INSEL_Msk

#define	COMP5_CSR_COMP5INSEL_0 (0x1UL << COMP5_CSR_COMP5INSEL_Pos)

#define	COMP5_CSR_COMP5INSEL_1 (0x2UL << COMP5_CSR_COMP5INSEL_Pos)

#define	COMP5_CSR_COMP5INSEL_2 (0x4UL << COMP5_CSR_COMP5INSEL_Pos)

#define	COMP5_CSR_COMP5OUTSEL_Pos (10U)

#define	COMP5_CSR_COMP5OUTSEL_Msk (0xFUL << COMP5_CSR_COMP5OUTSEL_Pos)

#define	COMP5_CSR_COMP5OUTSEL COMP5_CSR_COMP5OUTSEL_Msk

#define	COMP5_CSR_COMP5OUTSEL_0 (0x1UL << COMP5_CSR_COMP5OUTSEL_Pos)

#define	COMP5_CSR_COMP5OUTSEL_1 (0x2UL << COMP5_CSR_COMP5OUTSEL_Pos)

#define	COMP5_CSR_COMP5OUTSEL_2 (0x4UL << COMP5_CSR_COMP5OUTSEL_Pos)

#define	COMP5_CSR_COMP5OUTSEL_3 (0x8UL << COMP5_CSR_COMP5OUTSEL_Pos)

#define	COMP5_CSR_COMP5POL_Pos (15U)

#define	COMP5_CSR_COMP5POL_Msk (0x1UL << COMP5_CSR_COMP5POL_Pos)

#define	COMP5_CSR_COMP5POL COMP5_CSR_COMP5POL_Msk

#define	COMP5_CSR_COMP5BLANKING_Pos (18U)

#define	COMP5_CSR_COMP5BLANKING_Msk (0x3UL << COMP5_CSR_COMP5BLANKING_Pos)

#define	COMP5_CSR_COMP5BLANKING COMP5_CSR_COMP5BLANKING_Msk

#define	COMP5_CSR_COMP5BLANKING_0 (0x1UL << COMP5_CSR_COMP5BLANKING_Pos)

#define	COMP5_CSR_COMP5BLANKING_1 (0x2UL << COMP5_CSR_COMP5BLANKING_Pos)

#define	COMP5_CSR_COMP5BLANKING_2 (0x4UL << COMP5_CSR_COMP5BLANKING_Pos)

#define	COMP5_CSR_COMP5OUT_Pos (30U)

#define	COMP5_CSR_COMP5OUT_Msk (0x1UL << COMP5_CSR_COMP5OUT_Pos)

#define	COMP5_CSR_COMP5OUT COMP5_CSR_COMP5OUT_Msk

#define	COMP5_CSR_COMP5LOCK_Pos (31U)

#define	COMP5_CSR_COMP5LOCK_Msk (0x1UL << COMP5_CSR_COMP5LOCK_Pos)

#define	COMP5_CSR_COMP5LOCK COMP5_CSR_COMP5LOCK_Msk

#define	COMP6_CSR_COMP6EN_Pos (0U)

#define	COMP6_CSR_COMP6EN_Msk (0x1UL << COMP6_CSR_COMP6EN_Pos)

#define	COMP6_CSR_COMP6EN COMP6_CSR_COMP6EN_Msk

#define	COMP6_CSR_COMP6INSEL_Pos (4U)

#define	COMP6_CSR_COMP6INSEL_Msk (0x7UL << COMP6_CSR_COMP6INSEL_Pos)

#define	COMP6_CSR_COMP6INSEL COMP6_CSR_COMP6INSEL_Msk

#define	COMP6_CSR_COMP6INSEL_0 (0x00000010U)

#define	COMP6_CSR_COMP6INSEL_1 (0x00000020U)

#define	COMP6_CSR_COMP6INSEL_2 (0x00000040U)

#define	COMP6_CSR_COMP6OUTSEL_Pos (10U)

#define	COMP6_CSR_COMP6OUTSEL_Msk (0xFUL << COMP6_CSR_COMP6OUTSEL_Pos)

#define	COMP6_CSR_COMP6OUTSEL COMP6_CSR_COMP6OUTSEL_Msk

#define	COMP6_CSR_COMP6OUTSEL_0 (0x1UL << COMP6_CSR_COMP6OUTSEL_Pos)

#define	COMP6_CSR_COMP6OUTSEL_1 (0x2UL << COMP6_CSR_COMP6OUTSEL_Pos)

#define	COMP6_CSR_COMP6OUTSEL_2 (0x4UL << COMP6_CSR_COMP6OUTSEL_Pos)

#define	COMP6_CSR_COMP6OUTSEL_3 (0x8UL << COMP6_CSR_COMP6OUTSEL_Pos)

#define	COMP6_CSR_COMP6POL_Pos (15U)

#define	COMP6_CSR_COMP6POL_Msk (0x1UL << COMP6_CSR_COMP6POL_Pos)

#define	COMP6_CSR_COMP6POL COMP6_CSR_COMP6POL_Msk

#define	COMP6_CSR_COMP6BLANKING_Pos (18U)

#define	COMP6_CSR_COMP6BLANKING_Msk (0x3UL << COMP6_CSR_COMP6BLANKING_Pos)

#define	COMP6_CSR_COMP6BLANKING COMP6_CSR_COMP6BLANKING_Msk

#define	COMP6_CSR_COMP6BLANKING_0 (0x1UL << COMP6_CSR_COMP6BLANKING_Pos)

#define	COMP6_CSR_COMP6BLANKING_1 (0x2UL << COMP6_CSR_COMP6BLANKING_Pos)

#define	COMP6_CSR_COMP6BLANKING_2 (0x4UL << COMP6_CSR_COMP6BLANKING_Pos)

#define	COMP6_CSR_COMP6OUT_Pos (30U)

#define	COMP6_CSR_COMP6OUT_Msk (0x1UL << COMP6_CSR_COMP6OUT_Pos)

#define	COMP6_CSR_COMP6OUT COMP6_CSR_COMP6OUT_Msk

#define	COMP6_CSR_COMP6LOCK_Pos (31U)

#define	COMP6_CSR_COMP6LOCK_Msk (0x1UL << COMP6_CSR_COMP6LOCK_Pos)

#define	COMP6_CSR_COMP6LOCK COMP6_CSR_COMP6LOCK_Msk

#define	COMP7_CSR_COMP7EN_Pos (0U)

#define	COMP7_CSR_COMP7EN_Msk (0x1UL << COMP7_CSR_COMP7EN_Pos)

#define	COMP7_CSR_COMP7EN COMP7_CSR_COMP7EN_Msk

#define	COMP7_CSR_COMP7INSEL_Pos (4U)

#define	COMP7_CSR_COMP7INSEL_Msk (0x7UL << COMP7_CSR_COMP7INSEL_Pos)

#define	COMP7_CSR_COMP7INSEL COMP7_CSR_COMP7INSEL_Msk

#define	COMP7_CSR_COMP7INSEL_0 (0x1UL << COMP7_CSR_COMP7INSEL_Pos)

#define	COMP7_CSR_COMP7INSEL_1 (0x2UL << COMP7_CSR_COMP7INSEL_Pos)

#define	COMP7_CSR_COMP7INSEL_2 (0x4UL << COMP7_CSR_COMP7INSEL_Pos)

#define	COMP7_CSR_COMP7OUTSEL_Pos (10U)

#define	COMP7_CSR_COMP7OUTSEL_Msk (0xFUL << COMP7_CSR_COMP7OUTSEL_Pos)

#define	COMP7_CSR_COMP7OUTSEL COMP7_CSR_COMP7OUTSEL_Msk

#define	COMP7_CSR_COMP7OUTSEL_0 (0x1UL << COMP7_CSR_COMP7OUTSEL_Pos)

#define	COMP7_CSR_COMP7OUTSEL_1 (0x2UL << COMP7_CSR_COMP7OUTSEL_Pos)

#define	COMP7_CSR_COMP7OUTSEL_2 (0x4UL << COMP7_CSR_COMP7OUTSEL_Pos)

#define	COMP7_CSR_COMP7OUTSEL_3 (0x8UL << COMP7_CSR_COMP7OUTSEL_Pos)

#define	COMP7_CSR_COMP7POL_Pos (15U)

#define	COMP7_CSR_COMP7POL_Msk (0x1UL << COMP7_CSR_COMP7POL_Pos)

#define	COMP7_CSR_COMP7POL COMP7_CSR_COMP7POL_Msk

#define	COMP7_CSR_COMP7BLANKING_Pos (18U)

#define	COMP7_CSR_COMP7BLANKING_Msk (0x3UL << COMP7_CSR_COMP7BLANKING_Pos)

#define	COMP7_CSR_COMP7BLANKING COMP7_CSR_COMP7BLANKING_Msk

#define	COMP7_CSR_COMP7BLANKING_0 (0x1UL << COMP7_CSR_COMP7BLANKING_Pos)

#define	COMP7_CSR_COMP7BLANKING_1 (0x2UL << COMP7_CSR_COMP7BLANKING_Pos)

#define	COMP7_CSR_COMP7BLANKING_2 (0x4UL << COMP7_CSR_COMP7BLANKING_Pos)

#define	COMP7_CSR_COMP7OUT_Pos (30U)

#define	COMP7_CSR_COMP7OUT_Msk (0x1UL << COMP7_CSR_COMP7OUT_Pos)

#define	COMP7_CSR_COMP7OUT COMP7_CSR_COMP7OUT_Msk

#define	COMP7_CSR_COMP7LOCK_Pos (31U)

#define	COMP7_CSR_COMP7LOCK_Msk (0x1UL << COMP7_CSR_COMP7LOCK_Pos)

#define	COMP7_CSR_COMP7LOCK COMP7_CSR_COMP7LOCK_Msk

#define	COMP_CSR_COMPxEN_Pos (0U)

#define	COMP_CSR_COMPxEN_Msk (0x1UL << COMP_CSR_COMPxEN_Pos)

#define	COMP_CSR_COMPxEN COMP_CSR_COMPxEN_Msk

#define	COMP_CSR_COMPxSW1_Pos (1U)

#define	COMP_CSR_COMPxSW1_Msk (0x1UL << COMP_CSR_COMPxSW1_Pos)

#define	COMP_CSR_COMPxSW1 COMP_CSR_COMPxSW1_Msk

#define	COMP_CSR_COMPxINSEL_Pos (4U)

#define	COMP_CSR_COMPxINSEL_Msk (0x7UL << COMP_CSR_COMPxINSEL_Pos)

#define	COMP_CSR_COMPxINSEL COMP_CSR_COMPxINSEL_Msk

#define	COMP_CSR_COMPxINSEL_0 (0x00000010U)

#define	COMP_CSR_COMPxINSEL_1 (0x00000020U)

#define	COMP_CSR_COMPxINSEL_2 (0x00000040U)

#define	COMP_CSR_COMPxOUTSEL_Pos (10U)

#define	COMP_CSR_COMPxOUTSEL_Msk (0xFUL << COMP_CSR_COMPxOUTSEL_Pos)

#define	COMP_CSR_COMPxOUTSEL COMP_CSR_COMPxOUTSEL_Msk

#define	COMP_CSR_COMPxOUTSEL_0 (0x1UL << COMP_CSR_COMPxOUTSEL_Pos)

#define	COMP_CSR_COMPxOUTSEL_1 (0x2UL << COMP_CSR_COMPxOUTSEL_Pos)

#define	COMP_CSR_COMPxOUTSEL_2 (0x4UL << COMP_CSR_COMPxOUTSEL_Pos)

#define	COMP_CSR_COMPxOUTSEL_3 (0x8UL << COMP_CSR_COMPxOUTSEL_Pos)

#define	COMP_CSR_COMPxPOL_Pos (15U)

#define	COMP_CSR_COMPxPOL_Msk (0x1UL << COMP_CSR_COMPxPOL_Pos)

#define	COMP_CSR_COMPxPOL COMP_CSR_COMPxPOL_Msk

#define	COMP_CSR_COMPxBLANKING_Pos (18U)

#define	COMP_CSR_COMPxBLANKING_Msk (0x3UL << COMP_CSR_COMPxBLANKING_Pos)

#define	COMP_CSR_COMPxBLANKING COMP_CSR_COMPxBLANKING_Msk

#define	COMP_CSR_COMPxBLANKING_0 (0x1UL << COMP_CSR_COMPxBLANKING_Pos)

#define	COMP_CSR_COMPxBLANKING_1 (0x2UL << COMP_CSR_COMPxBLANKING_Pos)

#define	COMP_CSR_COMPxBLANKING_2 (0x4UL << COMP_CSR_COMPxBLANKING_Pos)

#define	COMP_CSR_COMPxOUT_Pos (30U)

#define	COMP_CSR_COMPxOUT_Msk (0x1UL << COMP_CSR_COMPxOUT_Pos)

#define	COMP_CSR_COMPxOUT COMP_CSR_COMPxOUT_Msk

#define	COMP_CSR_COMPxLOCK_Pos (31U)

#define	COMP_CSR_COMPxLOCK_Msk (0x1UL << COMP_CSR_COMPxLOCK_Pos)

#define	COMP_CSR_COMPxLOCK COMP_CSR_COMPxLOCK_Msk

#define	OPAMP1_CSR_OPAMP1EN_Pos (0U)

#define	OPAMP1_CSR_OPAMP1EN_Msk (0x1UL << OPAMP1_CSR_OPAMP1EN_Pos)

#define	OPAMP1_CSR_OPAMP1EN OPAMP1_CSR_OPAMP1EN_Msk

#define	OPAMP1_CSR_FORCEVP_Pos (1U)

#define	OPAMP1_CSR_FORCEVP_Msk (0x1UL << OPAMP1_CSR_FORCEVP_Pos)

#define	OPAMP1_CSR_FORCEVP OPAMP1_CSR_FORCEVP_Msk

#define	OPAMP1_CSR_VPSEL_Pos (2U)

#define	OPAMP1_CSR_VPSEL_Msk (0x3UL << OPAMP1_CSR_VPSEL_Pos)

#define	OPAMP1_CSR_VPSEL OPAMP1_CSR_VPSEL_Msk

#define	OPAMP1_CSR_VPSEL_0 (0x1UL << OPAMP1_CSR_VPSEL_Pos)

#define	OPAMP1_CSR_VPSEL_1 (0x2UL << OPAMP1_CSR_VPSEL_Pos)

#define	OPAMP1_CSR_VMSEL_Pos (5U)

#define	OPAMP1_CSR_VMSEL_Msk (0x3UL << OPAMP1_CSR_VMSEL_Pos)

#define	OPAMP1_CSR_VMSEL OPAMP1_CSR_VMSEL_Msk

#define	OPAMP1_CSR_VMSEL_0 (0x1UL << OPAMP1_CSR_VMSEL_Pos)

#define	OPAMP1_CSR_VMSEL_1 (0x2UL << OPAMP1_CSR_VMSEL_Pos)

#define	OPAMP1_CSR_TCMEN_Pos (7U)

#define	OPAMP1_CSR_TCMEN_Msk (0x1UL << OPAMP1_CSR_TCMEN_Pos)

#define	OPAMP1_CSR_TCMEN OPAMP1_CSR_TCMEN_Msk

#define	OPAMP1_CSR_VMSSEL_Pos (8U)

#define	OPAMP1_CSR_VMSSEL_Msk (0x1UL << OPAMP1_CSR_VMSSEL_Pos)

#define	OPAMP1_CSR_VMSSEL OPAMP1_CSR_VMSSEL_Msk

#define	OPAMP1_CSR_VPSSEL_Pos (9U)

#define	OPAMP1_CSR_VPSSEL_Msk (0x3UL << OPAMP1_CSR_VPSSEL_Pos)

#define	OPAMP1_CSR_VPSSEL OPAMP1_CSR_VPSSEL_Msk

#define	OPAMP1_CSR_VPSSEL_0 (0x1UL << OPAMP1_CSR_VPSSEL_Pos)

#define	OPAMP1_CSR_VPSSEL_1 (0x2UL << OPAMP1_CSR_VPSSEL_Pos)

#define	OPAMP1_CSR_CALON_Pos (11U)

#define	OPAMP1_CSR_CALON_Msk (0x1UL << OPAMP1_CSR_CALON_Pos)

#define	OPAMP1_CSR_CALON OPAMP1_CSR_CALON_Msk

#define	OPAMP1_CSR_CALSEL_Pos (12U)

#define	OPAMP1_CSR_CALSEL_Msk (0x3UL << OPAMP1_CSR_CALSEL_Pos)

#define	OPAMP1_CSR_CALSEL OPAMP1_CSR_CALSEL_Msk

#define	OPAMP1_CSR_CALSEL_0 (0x1UL << OPAMP1_CSR_CALSEL_Pos)

#define	OPAMP1_CSR_CALSEL_1 (0x2UL << OPAMP1_CSR_CALSEL_Pos)

#define	OPAMP1_CSR_PGGAIN_Pos (14U)

#define	OPAMP1_CSR_PGGAIN_Msk (0xFUL << OPAMP1_CSR_PGGAIN_Pos)

#define	OPAMP1_CSR_PGGAIN OPAMP1_CSR_PGGAIN_Msk

#define	OPAMP1_CSR_PGGAIN_0 (0x1UL << OPAMP1_CSR_PGGAIN_Pos)

#define	OPAMP1_CSR_PGGAIN_1 (0x2UL << OPAMP1_CSR_PGGAIN_Pos)

#define	OPAMP1_CSR_PGGAIN_2 (0x4UL << OPAMP1_CSR_PGGAIN_Pos)

#define	OPAMP1_CSR_PGGAIN_3 (0x8UL << OPAMP1_CSR_PGGAIN_Pos)

#define	OPAMP1_CSR_USERTRIM_Pos (18U)

#define	OPAMP1_CSR_USERTRIM_Msk (0x1UL << OPAMP1_CSR_USERTRIM_Pos)

#define	OPAMP1_CSR_USERTRIM OPAMP1_CSR_USERTRIM_Msk

#define	OPAMP1_CSR_TRIMOFFSETP_Pos (19U)

#define	OPAMP1_CSR_TRIMOFFSETP_Msk (0x1FUL << OPAMP1_CSR_TRIMOFFSETP_Pos)

#define	OPAMP1_CSR_TRIMOFFSETP OPAMP1_CSR_TRIMOFFSETP_Msk

#define	OPAMP1_CSR_TRIMOFFSETN_Pos (24U)

#define	OPAMP1_CSR_TRIMOFFSETN_Msk (0x1FUL << OPAMP1_CSR_TRIMOFFSETN_Pos)

#define	OPAMP1_CSR_TRIMOFFSETN OPAMP1_CSR_TRIMOFFSETN_Msk

#define	OPAMP1_CSR_TSTREF_Pos (29U)

#define	OPAMP1_CSR_TSTREF_Msk (0x1UL << OPAMP1_CSR_TSTREF_Pos)

#define	OPAMP1_CSR_TSTREF OPAMP1_CSR_TSTREF_Msk

#define	OPAMP1_CSR_OUTCAL_Pos (30U)

#define	OPAMP1_CSR_OUTCAL_Msk (0x1UL << OPAMP1_CSR_OUTCAL_Pos)

#define	OPAMP1_CSR_OUTCAL OPAMP1_CSR_OUTCAL_Msk

#define	OPAMP1_CSR_LOCK_Pos (31U)

#define	OPAMP1_CSR_LOCK_Msk (0x1UL << OPAMP1_CSR_LOCK_Pos)

#define	OPAMP1_CSR_LOCK OPAMP1_CSR_LOCK_Msk

#define	OPAMP2_CSR_OPAMP2EN_Pos (0U)

#define	OPAMP2_CSR_OPAMP2EN_Msk (0x1UL << OPAMP2_CSR_OPAMP2EN_Pos)

#define	OPAMP2_CSR_OPAMP2EN OPAMP2_CSR_OPAMP2EN_Msk

#define	OPAMP2_CSR_FORCEVP_Pos (1U)

#define	OPAMP2_CSR_FORCEVP_Msk (0x1UL << OPAMP2_CSR_FORCEVP_Pos)

#define	OPAMP2_CSR_FORCEVP OPAMP2_CSR_FORCEVP_Msk

#define	OPAMP2_CSR_VPSEL_Pos (2U)

#define	OPAMP2_CSR_VPSEL_Msk (0x3UL << OPAMP2_CSR_VPSEL_Pos)

#define	OPAMP2_CSR_VPSEL OPAMP2_CSR_VPSEL_Msk

#define	OPAMP2_CSR_VPSEL_0 (0x1UL << OPAMP2_CSR_VPSEL_Pos)

#define	OPAMP2_CSR_VPSEL_1 (0x2UL << OPAMP2_CSR_VPSEL_Pos)

#define	OPAMP2_CSR_VMSEL_Pos (5U)

#define	OPAMP2_CSR_VMSEL_Msk (0x3UL << OPAMP2_CSR_VMSEL_Pos)

#define	OPAMP2_CSR_VMSEL OPAMP2_CSR_VMSEL_Msk

#define	OPAMP2_CSR_VMSEL_0 (0x1UL << OPAMP2_CSR_VMSEL_Pos)

#define	OPAMP2_CSR_VMSEL_1 (0x2UL << OPAMP2_CSR_VMSEL_Pos)

#define	OPAMP2_CSR_TCMEN_Pos (7U)

#define	OPAMP2_CSR_TCMEN_Msk (0x1UL << OPAMP2_CSR_TCMEN_Pos)

#define	OPAMP2_CSR_TCMEN OPAMP2_CSR_TCMEN_Msk

#define	OPAMP2_CSR_VMSSEL_Pos (8U)

#define	OPAMP2_CSR_VMSSEL_Msk (0x1UL << OPAMP2_CSR_VMSSEL_Pos)

#define	OPAMP2_CSR_VMSSEL OPAMP2_CSR_VMSSEL_Msk

#define	OPAMP2_CSR_VPSSEL_Pos (9U)

#define	OPAMP2_CSR_VPSSEL_Msk (0x3UL << OPAMP2_CSR_VPSSEL_Pos)

#define	OPAMP2_CSR_VPSSEL OPAMP2_CSR_VPSSEL_Msk

#define	OPAMP2_CSR_VPSSEL_0 (0x1UL << OPAMP2_CSR_VPSSEL_Pos)

#define	OPAMP2_CSR_VPSSEL_1 (0x2UL << OPAMP2_CSR_VPSSEL_Pos)

#define	OPAMP2_CSR_CALON_Pos (11U)

#define	OPAMP2_CSR_CALON_Msk (0x1UL << OPAMP2_CSR_CALON_Pos)

#define	OPAMP2_CSR_CALON OPAMP2_CSR_CALON_Msk

#define	OPAMP2_CSR_CALSEL_Pos (12U)

#define	OPAMP2_CSR_CALSEL_Msk (0x3UL << OPAMP2_CSR_CALSEL_Pos)

#define	OPAMP2_CSR_CALSEL OPAMP2_CSR_CALSEL_Msk

#define	OPAMP2_CSR_CALSEL_0 (0x1UL << OPAMP2_CSR_CALSEL_Pos)

#define	OPAMP2_CSR_CALSEL_1 (0x2UL << OPAMP2_CSR_CALSEL_Pos)

#define	OPAMP2_CSR_PGGAIN_Pos (14U)

#define	OPAMP2_CSR_PGGAIN_Msk (0xFUL << OPAMP2_CSR_PGGAIN_Pos)

#define	OPAMP2_CSR_PGGAIN OPAMP2_CSR_PGGAIN_Msk

#define	OPAMP2_CSR_PGGAIN_0 (0x1UL << OPAMP2_CSR_PGGAIN_Pos)

#define	OPAMP2_CSR_PGGAIN_1 (0x2UL << OPAMP2_CSR_PGGAIN_Pos)

#define	OPAMP2_CSR_PGGAIN_2 (0x4UL << OPAMP2_CSR_PGGAIN_Pos)

#define	OPAMP2_CSR_PGGAIN_3 (0x8UL << OPAMP2_CSR_PGGAIN_Pos)

#define	OPAMP2_CSR_USERTRIM_Pos (18U)

#define	OPAMP2_CSR_USERTRIM_Msk (0x1UL << OPAMP2_CSR_USERTRIM_Pos)

#define	OPAMP2_CSR_USERTRIM OPAMP2_CSR_USERTRIM_Msk

#define	OPAMP2_CSR_TRIMOFFSETP_Pos (19U)

#define	OPAMP2_CSR_TRIMOFFSETP_Msk (0x1FUL << OPAMP2_CSR_TRIMOFFSETP_Pos)

#define	OPAMP2_CSR_TRIMOFFSETP OPAMP2_CSR_TRIMOFFSETP_Msk

#define	OPAMP2_CSR_TRIMOFFSETN_Pos (24U)

#define	OPAMP2_CSR_TRIMOFFSETN_Msk (0x1FUL << OPAMP2_CSR_TRIMOFFSETN_Pos)

#define	OPAMP2_CSR_TRIMOFFSETN OPAMP2_CSR_TRIMOFFSETN_Msk

#define	OPAMP2_CSR_TSTREF_Pos (29U)

#define	OPAMP2_CSR_TSTREF_Msk (0x1UL << OPAMP2_CSR_TSTREF_Pos)

#define	OPAMP2_CSR_TSTREF OPAMP2_CSR_TSTREF_Msk

#define	OPAMP2_CSR_OUTCAL_Pos (30U)

#define	OPAMP2_CSR_OUTCAL_Msk (0x1UL << OPAMP2_CSR_OUTCAL_Pos)

#define	OPAMP2_CSR_OUTCAL OPAMP2_CSR_OUTCAL_Msk

#define	OPAMP2_CSR_LOCK_Pos (31U)

#define	OPAMP2_CSR_LOCK_Msk (0x1UL << OPAMP2_CSR_LOCK_Pos)

#define	OPAMP2_CSR_LOCK OPAMP2_CSR_LOCK_Msk

#define	OPAMP3_CSR_OPAMP3EN_Pos (0U)

#define	OPAMP3_CSR_OPAMP3EN_Msk (0x1UL << OPAMP3_CSR_OPAMP3EN_Pos)

#define	OPAMP3_CSR_OPAMP3EN OPAMP3_CSR_OPAMP3EN_Msk

#define	OPAMP3_CSR_FORCEVP_Pos (1U)

#define	OPAMP3_CSR_FORCEVP_Msk (0x1UL << OPAMP3_CSR_FORCEVP_Pos)

#define	OPAMP3_CSR_FORCEVP OPAMP3_CSR_FORCEVP_Msk

#define	OPAMP3_CSR_VPSEL_Pos (2U)

#define	OPAMP3_CSR_VPSEL_Msk (0x3UL << OPAMP3_CSR_VPSEL_Pos)

#define	OPAMP3_CSR_VPSEL OPAMP3_CSR_VPSEL_Msk

#define	OPAMP3_CSR_VPSEL_0 (0x1UL << OPAMP3_CSR_VPSEL_Pos)

#define	OPAMP3_CSR_VPSEL_1 (0x2UL << OPAMP3_CSR_VPSEL_Pos)

#define	OPAMP3_CSR_VMSEL_Pos (5U)

#define	OPAMP3_CSR_VMSEL_Msk (0x3UL << OPAMP3_CSR_VMSEL_Pos)

#define	OPAMP3_CSR_VMSEL OPAMP3_CSR_VMSEL_Msk

#define	OPAMP3_CSR_VMSEL_0 (0x1UL << OPAMP3_CSR_VMSEL_Pos)

#define	OPAMP3_CSR_VMSEL_1 (0x2UL << OPAMP3_CSR_VMSEL_Pos)

#define	OPAMP3_CSR_TCMEN_Pos (7U)

#define	OPAMP3_CSR_TCMEN_Msk (0x1UL << OPAMP3_CSR_TCMEN_Pos)

#define	OPAMP3_CSR_TCMEN OPAMP3_CSR_TCMEN_Msk

#define	OPAMP3_CSR_VMSSEL_Pos (8U)

#define	OPAMP3_CSR_VMSSEL_Msk (0x1UL << OPAMP3_CSR_VMSSEL_Pos)

#define	OPAMP3_CSR_VMSSEL OPAMP3_CSR_VMSSEL_Msk

#define	OPAMP3_CSR_VPSSEL_Pos (9U)

#define	OPAMP3_CSR_VPSSEL_Msk (0x3UL << OPAMP3_CSR_VPSSEL_Pos)

#define	OPAMP3_CSR_VPSSEL OPAMP3_CSR_VPSSEL_Msk

#define	OPAMP3_CSR_VPSSEL_0 (0x1UL << OPAMP3_CSR_VPSSEL_Pos)

#define	OPAMP3_CSR_VPSSEL_1 (0x2UL << OPAMP3_CSR_VPSSEL_Pos)

#define	OPAMP3_CSR_CALON_Pos (11U)

#define	OPAMP3_CSR_CALON_Msk (0x1UL << OPAMP3_CSR_CALON_Pos)

#define	OPAMP3_CSR_CALON OPAMP3_CSR_CALON_Msk

#define	OPAMP3_CSR_CALSEL_Pos (12U)

#define	OPAMP3_CSR_CALSEL_Msk (0x3UL << OPAMP3_CSR_CALSEL_Pos)

#define	OPAMP3_CSR_CALSEL OPAMP3_CSR_CALSEL_Msk

#define	OPAMP3_CSR_CALSEL_0 (0x1UL << OPAMP3_CSR_CALSEL_Pos)

#define	OPAMP3_CSR_CALSEL_1 (0x2UL << OPAMP3_CSR_CALSEL_Pos)

#define	OPAMP3_CSR_PGGAIN_Pos (14U)

#define	OPAMP3_CSR_PGGAIN_Msk (0xFUL << OPAMP3_CSR_PGGAIN_Pos)

#define	OPAMP3_CSR_PGGAIN OPAMP3_CSR_PGGAIN_Msk

#define	OPAMP3_CSR_PGGAIN_0 (0x1UL << OPAMP3_CSR_PGGAIN_Pos)

#define	OPAMP3_CSR_PGGAIN_1 (0x2UL << OPAMP3_CSR_PGGAIN_Pos)

#define	OPAMP3_CSR_PGGAIN_2 (0x4UL << OPAMP3_CSR_PGGAIN_Pos)

#define	OPAMP3_CSR_PGGAIN_3 (0x8UL << OPAMP3_CSR_PGGAIN_Pos)

#define	OPAMP3_CSR_USERTRIM_Pos (18U)

#define	OPAMP3_CSR_USERTRIM_Msk (0x1UL << OPAMP3_CSR_USERTRIM_Pos)

#define	OPAMP3_CSR_USERTRIM OPAMP3_CSR_USERTRIM_Msk

#define	OPAMP3_CSR_TRIMOFFSETP_Pos (19U)

#define	OPAMP3_CSR_TRIMOFFSETP_Msk (0x1FUL << OPAMP3_CSR_TRIMOFFSETP_Pos)

#define	OPAMP3_CSR_TRIMOFFSETP OPAMP3_CSR_TRIMOFFSETP_Msk

#define	OPAMP3_CSR_TRIMOFFSETN_Pos (24U)

#define	OPAMP3_CSR_TRIMOFFSETN_Msk (0x1FUL << OPAMP3_CSR_TRIMOFFSETN_Pos)

#define	OPAMP3_CSR_TRIMOFFSETN OPAMP3_CSR_TRIMOFFSETN_Msk

#define	OPAMP3_CSR_TSTREF_Pos (29U)

#define	OPAMP3_CSR_TSTREF_Msk (0x1UL << OPAMP3_CSR_TSTREF_Pos)

#define	OPAMP3_CSR_TSTREF OPAMP3_CSR_TSTREF_Msk

#define	OPAMP3_CSR_OUTCAL_Pos (30U)

#define	OPAMP3_CSR_OUTCAL_Msk (0x1UL << OPAMP3_CSR_OUTCAL_Pos)

#define	OPAMP3_CSR_OUTCAL OPAMP3_CSR_OUTCAL_Msk

#define	OPAMP3_CSR_LOCK_Pos (31U)

#define	OPAMP3_CSR_LOCK_Msk (0x1UL << OPAMP3_CSR_LOCK_Pos)

#define	OPAMP3_CSR_LOCK OPAMP3_CSR_LOCK_Msk

#define	OPAMP4_CSR_OPAMP4EN_Pos (0U)

#define	OPAMP4_CSR_OPAMP4EN_Msk (0x1UL << OPAMP4_CSR_OPAMP4EN_Pos)

#define	OPAMP4_CSR_OPAMP4EN OPAMP4_CSR_OPAMP4EN_Msk

#define	OPAMP4_CSR_FORCEVP_Pos (1U)

#define	OPAMP4_CSR_FORCEVP_Msk (0x1UL << OPAMP4_CSR_FORCEVP_Pos)

#define	OPAMP4_CSR_FORCEVP OPAMP4_CSR_FORCEVP_Msk

#define	OPAMP4_CSR_VPSEL_Pos (2U)

#define	OPAMP4_CSR_VPSEL_Msk (0x3UL << OPAMP4_CSR_VPSEL_Pos)

#define	OPAMP4_CSR_VPSEL OPAMP4_CSR_VPSEL_Msk

#define	OPAMP4_CSR_VPSEL_0 (0x1UL << OPAMP4_CSR_VPSEL_Pos)

#define	OPAMP4_CSR_VPSEL_1 (0x2UL << OPAMP4_CSR_VPSEL_Pos)

#define	OPAMP4_CSR_VMSEL_Pos (5U)

#define	OPAMP4_CSR_VMSEL_Msk (0x3UL << OPAMP4_CSR_VMSEL_Pos)

#define	OPAMP4_CSR_VMSEL OPAMP4_CSR_VMSEL_Msk

#define	OPAMP4_CSR_VMSEL_0 (0x1UL << OPAMP4_CSR_VMSEL_Pos)

#define	OPAMP4_CSR_VMSEL_1 (0x2UL << OPAMP4_CSR_VMSEL_Pos)

#define	OPAMP4_CSR_TCMEN_Pos (7U)

#define	OPAMP4_CSR_TCMEN_Msk (0x1UL << OPAMP4_CSR_TCMEN_Pos)

#define	OPAMP4_CSR_TCMEN OPAMP4_CSR_TCMEN_Msk

#define	OPAMP4_CSR_VMSSEL_Pos (8U)

#define	OPAMP4_CSR_VMSSEL_Msk (0x1UL << OPAMP4_CSR_VMSSEL_Pos)

#define	OPAMP4_CSR_VMSSEL OPAMP4_CSR_VMSSEL_Msk

#define	OPAMP4_CSR_VPSSEL_Pos (9U)

#define	OPAMP4_CSR_VPSSEL_Msk (0x3UL << OPAMP4_CSR_VPSSEL_Pos)

#define	OPAMP4_CSR_VPSSEL OPAMP4_CSR_VPSSEL_Msk

#define	OPAMP4_CSR_VPSSEL_0 (0x1UL << OPAMP4_CSR_VPSSEL_Pos)

#define	OPAMP4_CSR_VPSSEL_1 (0x2UL << OPAMP4_CSR_VPSSEL_Pos)

#define	OPAMP4_CSR_CALON_Pos (11U)

#define	OPAMP4_CSR_CALON_Msk (0x1UL << OPAMP4_CSR_CALON_Pos)

#define	OPAMP4_CSR_CALON OPAMP4_CSR_CALON_Msk

#define	OPAMP4_CSR_CALSEL_Pos (12U)

#define	OPAMP4_CSR_CALSEL_Msk (0x3UL << OPAMP4_CSR_CALSEL_Pos)

#define	OPAMP4_CSR_CALSEL OPAMP4_CSR_CALSEL_Msk

#define	OPAMP4_CSR_CALSEL_0 (0x1UL << OPAMP4_CSR_CALSEL_Pos)

#define	OPAMP4_CSR_CALSEL_1 (0x2UL << OPAMP4_CSR_CALSEL_Pos)

#define	OPAMP4_CSR_PGGAIN_Pos (14U)

#define	OPAMP4_CSR_PGGAIN_Msk (0xFUL << OPAMP4_CSR_PGGAIN_Pos)

#define	OPAMP4_CSR_PGGAIN OPAMP4_CSR_PGGAIN_Msk

#define	OPAMP4_CSR_PGGAIN_0 (0x1UL << OPAMP4_CSR_PGGAIN_Pos)

#define	OPAMP4_CSR_PGGAIN_1 (0x2UL << OPAMP4_CSR_PGGAIN_Pos)

#define	OPAMP4_CSR_PGGAIN_2 (0x4UL << OPAMP4_CSR_PGGAIN_Pos)

#define	OPAMP4_CSR_PGGAIN_3 (0x8UL << OPAMP4_CSR_PGGAIN_Pos)

#define	OPAMP4_CSR_USERTRIM_Pos (18U)

#define	OPAMP4_CSR_USERTRIM_Msk (0x1UL << OPAMP4_CSR_USERTRIM_Pos)

#define	OPAMP4_CSR_USERTRIM OPAMP4_CSR_USERTRIM_Msk

#define	OPAMP4_CSR_TRIMOFFSETP_Pos (19U)

#define	OPAMP4_CSR_TRIMOFFSETP_Msk (0x1FUL << OPAMP4_CSR_TRIMOFFSETP_Pos)

#define	OPAMP4_CSR_TRIMOFFSETP OPAMP4_CSR_TRIMOFFSETP_Msk

#define	OPAMP4_CSR_TRIMOFFSETN_Pos (24U)

#define	OPAMP4_CSR_TRIMOFFSETN_Msk (0x1FUL << OPAMP4_CSR_TRIMOFFSETN_Pos)

#define	OPAMP4_CSR_TRIMOFFSETN OPAMP4_CSR_TRIMOFFSETN_Msk

#define	OPAMP4_CSR_TSTREF_Pos (29U)

#define	OPAMP4_CSR_TSTREF_Msk (0x1UL << OPAMP4_CSR_TSTREF_Pos)

#define	OPAMP4_CSR_TSTREF OPAMP4_CSR_TSTREF_Msk

#define	OPAMP4_CSR_OUTCAL_Pos (30U)

#define	OPAMP4_CSR_OUTCAL_Msk (0x1UL << OPAMP4_CSR_OUTCAL_Pos)

#define	OPAMP4_CSR_OUTCAL OPAMP4_CSR_OUTCAL_Msk

#define	OPAMP4_CSR_LOCK_Pos (31U)

#define	OPAMP4_CSR_LOCK_Msk (0x1UL << OPAMP4_CSR_LOCK_Pos)

#define	OPAMP4_CSR_LOCK OPAMP4_CSR_LOCK_Msk

#define	OPAMP_CSR_OPAMPxEN_Pos (0U)

#define	OPAMP_CSR_OPAMPxEN_Msk (0x1UL << OPAMP_CSR_OPAMPxEN_Pos)

#define	OPAMP_CSR_OPAMPxEN OPAMP_CSR_OPAMPxEN_Msk

#define	OPAMP_CSR_FORCEVP_Pos (1U)

#define	OPAMP_CSR_FORCEVP_Msk (0x1UL << OPAMP_CSR_FORCEVP_Pos)

#define	OPAMP_CSR_FORCEVP OPAMP_CSR_FORCEVP_Msk

#define	OPAMP_CSR_VPSEL_Pos (2U)

#define	OPAMP_CSR_VPSEL_Msk (0x3UL << OPAMP_CSR_VPSEL_Pos)

#define	OPAMP_CSR_VPSEL OPAMP_CSR_VPSEL_Msk

#define	OPAMP_CSR_VPSEL_0 (0x1UL << OPAMP_CSR_VPSEL_Pos)

#define	OPAMP_CSR_VPSEL_1 (0x2UL << OPAMP_CSR_VPSEL_Pos)

#define	OPAMP_CSR_VMSEL_Pos (5U)

#define	OPAMP_CSR_VMSEL_Msk (0x3UL << OPAMP_CSR_VMSEL_Pos)

#define	OPAMP_CSR_VMSEL OPAMP_CSR_VMSEL_Msk

#define	OPAMP_CSR_VMSEL_0 (0x1UL << OPAMP_CSR_VMSEL_Pos)

#define	OPAMP_CSR_VMSEL_1 (0x2UL << OPAMP_CSR_VMSEL_Pos)

#define	OPAMP_CSR_TCMEN_Pos (7U)

#define	OPAMP_CSR_TCMEN_Msk (0x1UL << OPAMP_CSR_TCMEN_Pos)

#define	OPAMP_CSR_TCMEN OPAMP_CSR_TCMEN_Msk

#define	OPAMP_CSR_VMSSEL_Pos (8U)

#define	OPAMP_CSR_VMSSEL_Msk (0x1UL << OPAMP_CSR_VMSSEL_Pos)

#define	OPAMP_CSR_VMSSEL OPAMP_CSR_VMSSEL_Msk

#define	OPAMP_CSR_VPSSEL_Pos (9U)

#define	OPAMP_CSR_VPSSEL_Msk (0x3UL << OPAMP_CSR_VPSSEL_Pos)

#define	OPAMP_CSR_VPSSEL OPAMP_CSR_VPSSEL_Msk

#define	OPAMP_CSR_VPSSEL_0 (0x1UL << OPAMP_CSR_VPSSEL_Pos)

#define	OPAMP_CSR_VPSSEL_1 (0x2UL << OPAMP_CSR_VPSSEL_Pos)

#define	OPAMP_CSR_CALON_Pos (11U)

#define	OPAMP_CSR_CALON_Msk (0x1UL << OPAMP_CSR_CALON_Pos)

#define	OPAMP_CSR_CALON OPAMP_CSR_CALON_Msk

#define	OPAMP_CSR_CALSEL_Pos (12U)

#define	OPAMP_CSR_CALSEL_Msk (0x3UL << OPAMP_CSR_CALSEL_Pos)

#define	OPAMP_CSR_CALSEL OPAMP_CSR_CALSEL_Msk

#define	OPAMP_CSR_CALSEL_0 (0x1UL << OPAMP_CSR_CALSEL_Pos)

#define	OPAMP_CSR_CALSEL_1 (0x2UL << OPAMP_CSR_CALSEL_Pos)

#define	OPAMP_CSR_PGGAIN_Pos (14U)

#define	OPAMP_CSR_PGGAIN_Msk (0xFUL << OPAMP_CSR_PGGAIN_Pos)

#define	OPAMP_CSR_PGGAIN OPAMP_CSR_PGGAIN_Msk

#define	OPAMP_CSR_PGGAIN_0 (0x1UL << OPAMP_CSR_PGGAIN_Pos)

#define	OPAMP_CSR_PGGAIN_1 (0x2UL << OPAMP_CSR_PGGAIN_Pos)

#define	OPAMP_CSR_PGGAIN_2 (0x4UL << OPAMP_CSR_PGGAIN_Pos)

#define	OPAMP_CSR_PGGAIN_3 (0x8UL << OPAMP_CSR_PGGAIN_Pos)

#define	OPAMP_CSR_USERTRIM_Pos (18U)

#define	OPAMP_CSR_USERTRIM_Msk (0x1UL << OPAMP_CSR_USERTRIM_Pos)

#define	OPAMP_CSR_USERTRIM OPAMP_CSR_USERTRIM_Msk

#define	OPAMP_CSR_TRIMOFFSETP_Pos (19U)

#define	OPAMP_CSR_TRIMOFFSETP_Msk (0x1FUL << OPAMP_CSR_TRIMOFFSETP_Pos)

#define	OPAMP_CSR_TRIMOFFSETP OPAMP_CSR_TRIMOFFSETP_Msk

#define	OPAMP_CSR_TRIMOFFSETN_Pos (24U)

#define	OPAMP_CSR_TRIMOFFSETN_Msk (0x1FUL << OPAMP_CSR_TRIMOFFSETN_Pos)

#define	OPAMP_CSR_TRIMOFFSETN OPAMP_CSR_TRIMOFFSETN_Msk

#define	OPAMP_CSR_TSTREF_Pos (29U)

#define	OPAMP_CSR_TSTREF_Msk (0x1UL << OPAMP_CSR_TSTREF_Pos)

#define	OPAMP_CSR_TSTREF OPAMP_CSR_TSTREF_Msk

#define	OPAMP_CSR_OUTCAL_Pos (30U)

#define	OPAMP_CSR_OUTCAL_Msk (0x1UL << OPAMP_CSR_OUTCAL_Pos)

#define	OPAMP_CSR_OUTCAL OPAMP_CSR_OUTCAL_Msk

#define	OPAMP_CSR_LOCK_Pos (31U)

#define	OPAMP_CSR_LOCK_Msk (0x1UL << OPAMP_CSR_LOCK_Pos)

#define	OPAMP_CSR_LOCK OPAMP_CSR_LOCK_Msk

#define	CAN_MCR_INRQ_Pos (0U)

#define	CAN_MCR_INRQ_Msk (0x1UL << CAN_MCR_INRQ_Pos)

#define	CAN_MCR_INRQ CAN_MCR_INRQ_Msk

#define	CAN_MCR_SLEEP_Pos (1U)

#define	CAN_MCR_SLEEP_Msk (0x1UL << CAN_MCR_SLEEP_Pos)

#define	CAN_MCR_SLEEP CAN_MCR_SLEEP_Msk

#define	CAN_MCR_TXFP_Pos (2U)

#define	CAN_MCR_TXFP_Msk (0x1UL << CAN_MCR_TXFP_Pos)

#define	CAN_MCR_TXFP CAN_MCR_TXFP_Msk

#define	CAN_MCR_RFLM_Pos (3U)

#define	CAN_MCR_RFLM_Msk (0x1UL << CAN_MCR_RFLM_Pos)

#define	CAN_MCR_RFLM CAN_MCR_RFLM_Msk

#define	CAN_MCR_NART_Pos (4U)

#define	CAN_MCR_NART_Msk (0x1UL << CAN_MCR_NART_Pos)

#define	CAN_MCR_NART CAN_MCR_NART_Msk

#define	CAN_MCR_AWUM_Pos (5U)

#define	CAN_MCR_AWUM_Msk (0x1UL << CAN_MCR_AWUM_Pos)

#define	CAN_MCR_AWUM CAN_MCR_AWUM_Msk

#define	CAN_MCR_ABOM_Pos (6U)

#define	CAN_MCR_ABOM_Msk (0x1UL << CAN_MCR_ABOM_Pos)

#define	CAN_MCR_ABOM CAN_MCR_ABOM_Msk

#define	CAN_MCR_TTCM_Pos (7U)

#define	CAN_MCR_TTCM_Msk (0x1UL << CAN_MCR_TTCM_Pos)

#define	CAN_MCR_TTCM CAN_MCR_TTCM_Msk

#define	CAN_MCR_RESET_Pos (15U)

#define	CAN_MCR_RESET_Msk (0x1UL << CAN_MCR_RESET_Pos)

#define	CAN_MCR_RESET CAN_MCR_RESET_Msk

#define	CAN_MSR_INAK_Pos (0U)

#define	CAN_MSR_INAK_Msk (0x1UL << CAN_MSR_INAK_Pos)

#define	CAN_MSR_INAK CAN_MSR_INAK_Msk

#define	CAN_MSR_SLAK_Pos (1U)

#define	CAN_MSR_SLAK_Msk (0x1UL << CAN_MSR_SLAK_Pos)

#define	CAN_MSR_SLAK CAN_MSR_SLAK_Msk

#define	CAN_MSR_ERRI_Pos (2U)

#define	CAN_MSR_ERRI_Msk (0x1UL << CAN_MSR_ERRI_Pos)

#define	CAN_MSR_ERRI CAN_MSR_ERRI_Msk

#define	CAN_MSR_WKUI_Pos (3U)

#define	CAN_MSR_WKUI_Msk (0x1UL << CAN_MSR_WKUI_Pos)

#define	CAN_MSR_WKUI CAN_MSR_WKUI_Msk

#define	CAN_MSR_SLAKI_Pos (4U)

#define	CAN_MSR_SLAKI_Msk (0x1UL << CAN_MSR_SLAKI_Pos)

#define	CAN_MSR_SLAKI CAN_MSR_SLAKI_Msk

#define	CAN_MSR_TXM_Pos (8U)

#define	CAN_MSR_TXM_Msk (0x1UL << CAN_MSR_TXM_Pos)

#define	CAN_MSR_TXM CAN_MSR_TXM_Msk

#define	CAN_MSR_RXM_Pos (9U)

#define	CAN_MSR_RXM_Msk (0x1UL << CAN_MSR_RXM_Pos)

#define	CAN_MSR_RXM CAN_MSR_RXM_Msk

#define	CAN_MSR_SAMP_Pos (10U)

#define	CAN_MSR_SAMP_Msk (0x1UL << CAN_MSR_SAMP_Pos)

#define	CAN_MSR_SAMP CAN_MSR_SAMP_Msk

#define	CAN_MSR_RX_Pos (11U)

#define	CAN_MSR_RX_Msk (0x1UL << CAN_MSR_RX_Pos)

#define	CAN_MSR_RX CAN_MSR_RX_Msk

#define	CAN_TSR_RQCP0_Pos (0U)

#define	CAN_TSR_RQCP0_Msk (0x1UL << CAN_TSR_RQCP0_Pos)

#define	CAN_TSR_RQCP0 CAN_TSR_RQCP0_Msk

#define	CAN_TSR_TXOK0_Pos (1U)

#define	CAN_TSR_TXOK0_Msk (0x1UL << CAN_TSR_TXOK0_Pos)

#define	CAN_TSR_TXOK0 CAN_TSR_TXOK0_Msk

#define	CAN_TSR_ALST0_Pos (2U)

#define	CAN_TSR_ALST0_Msk (0x1UL << CAN_TSR_ALST0_Pos)

#define	CAN_TSR_ALST0 CAN_TSR_ALST0_Msk

#define	CAN_TSR_TERR0_Pos (3U)

#define	CAN_TSR_TERR0_Msk (0x1UL << CAN_TSR_TERR0_Pos)

#define	CAN_TSR_TERR0 CAN_TSR_TERR0_Msk

#define	CAN_TSR_ABRQ0_Pos (7U)

#define	CAN_TSR_ABRQ0_Msk (0x1UL << CAN_TSR_ABRQ0_Pos)

#define	CAN_TSR_ABRQ0 CAN_TSR_ABRQ0_Msk

#define	CAN_TSR_RQCP1_Pos (8U)

#define	CAN_TSR_RQCP1_Msk (0x1UL << CAN_TSR_RQCP1_Pos)

#define	CAN_TSR_RQCP1 CAN_TSR_RQCP1_Msk

#define	CAN_TSR_TXOK1_Pos (9U)

#define	CAN_TSR_TXOK1_Msk (0x1UL << CAN_TSR_TXOK1_Pos)

#define	CAN_TSR_TXOK1 CAN_TSR_TXOK1_Msk

#define	CAN_TSR_ALST1_Pos (10U)

#define	CAN_TSR_ALST1_Msk (0x1UL << CAN_TSR_ALST1_Pos)

#define	CAN_TSR_ALST1 CAN_TSR_ALST1_Msk

#define	CAN_TSR_TERR1_Pos (11U)

#define	CAN_TSR_TERR1_Msk (0x1UL << CAN_TSR_TERR1_Pos)

#define	CAN_TSR_TERR1 CAN_TSR_TERR1_Msk

#define	CAN_TSR_ABRQ1_Pos (15U)

#define	CAN_TSR_ABRQ1_Msk (0x1UL << CAN_TSR_ABRQ1_Pos)

#define	CAN_TSR_ABRQ1 CAN_TSR_ABRQ1_Msk

#define	CAN_TSR_RQCP2_Pos (16U)

#define	CAN_TSR_RQCP2_Msk (0x1UL << CAN_TSR_RQCP2_Pos)

#define	CAN_TSR_RQCP2 CAN_TSR_RQCP2_Msk

#define	CAN_TSR_TXOK2_Pos (17U)

#define	CAN_TSR_TXOK2_Msk (0x1UL << CAN_TSR_TXOK2_Pos)

#define	CAN_TSR_TXOK2 CAN_TSR_TXOK2_Msk

#define	CAN_TSR_ALST2_Pos (18U)

#define	CAN_TSR_ALST2_Msk (0x1UL << CAN_TSR_ALST2_Pos)

#define	CAN_TSR_ALST2 CAN_TSR_ALST2_Msk

#define	CAN_TSR_TERR2_Pos (19U)

#define	CAN_TSR_TERR2_Msk (0x1UL << CAN_TSR_TERR2_Pos)

#define	CAN_TSR_TERR2 CAN_TSR_TERR2_Msk

#define	CAN_TSR_ABRQ2_Pos (23U)

#define	CAN_TSR_ABRQ2_Msk (0x1UL << CAN_TSR_ABRQ2_Pos)

#define	CAN_TSR_ABRQ2 CAN_TSR_ABRQ2_Msk

#define	CAN_TSR_CODE_Pos (24U)

#define	CAN_TSR_CODE_Msk (0x3UL << CAN_TSR_CODE_Pos)

#define	CAN_TSR_CODE CAN_TSR_CODE_Msk

#define	CAN_TSR_TME_Pos (26U)

#define	CAN_TSR_TME_Msk (0x7UL << CAN_TSR_TME_Pos)

#define	CAN_TSR_TME CAN_TSR_TME_Msk

#define	CAN_TSR_TME0_Pos (26U)

#define	CAN_TSR_TME0_Msk (0x1UL << CAN_TSR_TME0_Pos)

#define	CAN_TSR_TME0 CAN_TSR_TME0_Msk

#define	CAN_TSR_TME1_Pos (27U)

#define	CAN_TSR_TME1_Msk (0x1UL << CAN_TSR_TME1_Pos)

#define	CAN_TSR_TME1 CAN_TSR_TME1_Msk

#define	CAN_TSR_TME2_Pos (28U)

#define	CAN_TSR_TME2_Msk (0x1UL << CAN_TSR_TME2_Pos)

#define	CAN_TSR_TME2 CAN_TSR_TME2_Msk

#define	CAN_TSR_LOW_Pos (29U)

#define	CAN_TSR_LOW_Msk (0x7UL << CAN_TSR_LOW_Pos)

#define	CAN_TSR_LOW CAN_TSR_LOW_Msk

#define	CAN_TSR_LOW0_Pos (29U)

#define	CAN_TSR_LOW0_Msk (0x1UL << CAN_TSR_LOW0_Pos)

#define	CAN_TSR_LOW0 CAN_TSR_LOW0_Msk

#define	CAN_TSR_LOW1_Pos (30U)

#define	CAN_TSR_LOW1_Msk (0x1UL << CAN_TSR_LOW1_Pos)

#define	CAN_TSR_LOW1 CAN_TSR_LOW1_Msk

#define	CAN_TSR_LOW2_Pos (31U)

#define	CAN_TSR_LOW2_Msk (0x1UL << CAN_TSR_LOW2_Pos)

#define	CAN_TSR_LOW2 CAN_TSR_LOW2_Msk

#define	CAN_RF0R_FMP0_Pos (0U)

#define	CAN_RF0R_FMP0_Msk (0x3UL << CAN_RF0R_FMP0_Pos)

#define	CAN_RF0R_FMP0 CAN_RF0R_FMP0_Msk

#define	CAN_RF0R_FULL0_Pos (3U)

#define	CAN_RF0R_FULL0_Msk (0x1UL << CAN_RF0R_FULL0_Pos)

#define	CAN_RF0R_FULL0 CAN_RF0R_FULL0_Msk

#define	CAN_RF0R_FOVR0_Pos (4U)

#define	CAN_RF0R_FOVR0_Msk (0x1UL << CAN_RF0R_FOVR0_Pos)

#define	CAN_RF0R_FOVR0 CAN_RF0R_FOVR0_Msk

#define	CAN_RF0R_RFOM0_Pos (5U)

#define	CAN_RF0R_RFOM0_Msk (0x1UL << CAN_RF0R_RFOM0_Pos)

#define	CAN_RF0R_RFOM0 CAN_RF0R_RFOM0_Msk

#define	CAN_RF1R_FMP1_Pos (0U)

#define	CAN_RF1R_FMP1_Msk (0x3UL << CAN_RF1R_FMP1_Pos)

#define	CAN_RF1R_FMP1 CAN_RF1R_FMP1_Msk

#define	CAN_RF1R_FULL1_Pos (3U)

#define	CAN_RF1R_FULL1_Msk (0x1UL << CAN_RF1R_FULL1_Pos)

#define	CAN_RF1R_FULL1 CAN_RF1R_FULL1_Msk

#define	CAN_RF1R_FOVR1_Pos (4U)

#define	CAN_RF1R_FOVR1_Msk (0x1UL << CAN_RF1R_FOVR1_Pos)

#define	CAN_RF1R_FOVR1 CAN_RF1R_FOVR1_Msk

#define	CAN_RF1R_RFOM1_Pos (5U)

#define	CAN_RF1R_RFOM1_Msk (0x1UL << CAN_RF1R_RFOM1_Pos)

#define	CAN_RF1R_RFOM1 CAN_RF1R_RFOM1_Msk

#define	CAN_IER_TMEIE_Pos (0U)

#define	CAN_IER_TMEIE_Msk (0x1UL << CAN_IER_TMEIE_Pos)

#define	CAN_IER_TMEIE CAN_IER_TMEIE_Msk

#define	CAN_IER_FMPIE0_Pos (1U)

#define	CAN_IER_FMPIE0_Msk (0x1UL << CAN_IER_FMPIE0_Pos)

#define	CAN_IER_FMPIE0 CAN_IER_FMPIE0_Msk

#define	CAN_IER_FFIE0_Pos (2U)

#define	CAN_IER_FFIE0_Msk (0x1UL << CAN_IER_FFIE0_Pos)

#define	CAN_IER_FFIE0 CAN_IER_FFIE0_Msk

#define	CAN_IER_FOVIE0_Pos (3U)

#define	CAN_IER_FOVIE0_Msk (0x1UL << CAN_IER_FOVIE0_Pos)

#define	CAN_IER_FOVIE0 CAN_IER_FOVIE0_Msk

#define	CAN_IER_FMPIE1_Pos (4U)

#define	CAN_IER_FMPIE1_Msk (0x1UL << CAN_IER_FMPIE1_Pos)

#define	CAN_IER_FMPIE1 CAN_IER_FMPIE1_Msk

#define	CAN_IER_FFIE1_Pos (5U)

#define	CAN_IER_FFIE1_Msk (0x1UL << CAN_IER_FFIE1_Pos)

#define	CAN_IER_FFIE1 CAN_IER_FFIE1_Msk

#define	CAN_IER_FOVIE1_Pos (6U)

#define	CAN_IER_FOVIE1_Msk (0x1UL << CAN_IER_FOVIE1_Pos)

#define	CAN_IER_FOVIE1 CAN_IER_FOVIE1_Msk

#define	CAN_IER_EWGIE_Pos (8U)

#define	CAN_IER_EWGIE_Msk (0x1UL << CAN_IER_EWGIE_Pos)

#define	CAN_IER_EWGIE CAN_IER_EWGIE_Msk

#define	CAN_IER_EPVIE_Pos (9U)

#define	CAN_IER_EPVIE_Msk (0x1UL << CAN_IER_EPVIE_Pos)

#define	CAN_IER_EPVIE CAN_IER_EPVIE_Msk

#define	CAN_IER_BOFIE_Pos (10U)

#define	CAN_IER_BOFIE_Msk (0x1UL << CAN_IER_BOFIE_Pos)

#define	CAN_IER_BOFIE CAN_IER_BOFIE_Msk

#define	CAN_IER_LECIE_Pos (11U)

#define	CAN_IER_LECIE_Msk (0x1UL << CAN_IER_LECIE_Pos)

#define	CAN_IER_LECIE CAN_IER_LECIE_Msk

#define	CAN_IER_ERRIE_Pos (15U)

#define	CAN_IER_ERRIE_Msk (0x1UL << CAN_IER_ERRIE_Pos)

#define	CAN_IER_ERRIE CAN_IER_ERRIE_Msk

#define	CAN_IER_WKUIE_Pos (16U)

#define	CAN_IER_WKUIE_Msk (0x1UL << CAN_IER_WKUIE_Pos)

#define	CAN_IER_WKUIE CAN_IER_WKUIE_Msk

#define	CAN_IER_SLKIE_Pos (17U)

#define	CAN_IER_SLKIE_Msk (0x1UL << CAN_IER_SLKIE_Pos)

#define	CAN_IER_SLKIE CAN_IER_SLKIE_Msk

#define	CAN_ESR_EWGF_Pos (0U)

#define	CAN_ESR_EWGF_Msk (0x1UL << CAN_ESR_EWGF_Pos)

#define	CAN_ESR_EWGF CAN_ESR_EWGF_Msk

#define	CAN_ESR_EPVF_Pos (1U)

#define	CAN_ESR_EPVF_Msk (0x1UL << CAN_ESR_EPVF_Pos)

#define	CAN_ESR_EPVF CAN_ESR_EPVF_Msk

#define	CAN_ESR_BOFF_Pos (2U)

#define	CAN_ESR_BOFF_Msk (0x1UL << CAN_ESR_BOFF_Pos)

#define	CAN_ESR_BOFF CAN_ESR_BOFF_Msk

#define	CAN_ESR_LEC_Pos (4U)

#define	CAN_ESR_LEC_Msk (0x7UL << CAN_ESR_LEC_Pos)

#define	CAN_ESR_LEC CAN_ESR_LEC_Msk

#define	CAN_ESR_LEC_0 (0x1UL << CAN_ESR_LEC_Pos)

#define	CAN_ESR_LEC_1 (0x2UL << CAN_ESR_LEC_Pos)

#define	CAN_ESR_LEC_2 (0x4UL << CAN_ESR_LEC_Pos)

#define	CAN_ESR_TEC_Pos (16U)

#define	CAN_ESR_TEC_Msk (0xFFUL << CAN_ESR_TEC_Pos)

#define	CAN_ESR_TEC CAN_ESR_TEC_Msk

#define	CAN_ESR_REC_Pos (24U)

#define	CAN_ESR_REC_Msk (0xFFUL << CAN_ESR_REC_Pos)

#define	CAN_ESR_REC CAN_ESR_REC_Msk

#define	CAN_BTR_BRP_Pos (0U)

#define	CAN_BTR_BRP_Msk (0x3FFUL << CAN_BTR_BRP_Pos)

#define	CAN_BTR_BRP CAN_BTR_BRP_Msk

#define	CAN_BTR_TS1_Pos (16U)

#define	CAN_BTR_TS1_Msk (0xFUL << CAN_BTR_TS1_Pos)

#define	CAN_BTR_TS1 CAN_BTR_TS1_Msk

#define	CAN_BTR_TS1_0 (0x1UL << CAN_BTR_TS1_Pos)

#define	CAN_BTR_TS1_1 (0x2UL << CAN_BTR_TS1_Pos)

#define	CAN_BTR_TS1_2 (0x4UL << CAN_BTR_TS1_Pos)

#define	CAN_BTR_TS1_3 (0x8UL << CAN_BTR_TS1_Pos)

#define	CAN_BTR_TS2_Pos (20U)

#define	CAN_BTR_TS2_Msk (0x7UL << CAN_BTR_TS2_Pos)

#define	CAN_BTR_TS2 CAN_BTR_TS2_Msk

#define	CAN_BTR_TS2_0 (0x1UL << CAN_BTR_TS2_Pos)

#define	CAN_BTR_TS2_1 (0x2UL << CAN_BTR_TS2_Pos)

#define	CAN_BTR_TS2_2 (0x4UL << CAN_BTR_TS2_Pos)

#define	CAN_BTR_SJW_Pos (24U)

#define	CAN_BTR_SJW_Msk (0x3UL << CAN_BTR_SJW_Pos)

#define	CAN_BTR_SJW CAN_BTR_SJW_Msk

#define	CAN_BTR_SJW_0 (0x1UL << CAN_BTR_SJW_Pos)

#define	CAN_BTR_SJW_1 (0x2UL << CAN_BTR_SJW_Pos)

#define	CAN_BTR_LBKM_Pos (30U)

#define	CAN_BTR_LBKM_Msk (0x1UL << CAN_BTR_LBKM_Pos)

#define	CAN_BTR_LBKM CAN_BTR_LBKM_Msk

#define	CAN_BTR_SILM_Pos (31U)

#define	CAN_BTR_SILM_Msk (0x1UL << CAN_BTR_SILM_Pos)

#define	CAN_BTR_SILM CAN_BTR_SILM_Msk

#define	CAN_TI0R_TXRQ_Pos (0U)

#define	CAN_TI0R_TXRQ_Msk (0x1UL << CAN_TI0R_TXRQ_Pos)

#define	CAN_TI0R_TXRQ CAN_TI0R_TXRQ_Msk

#define	CAN_TI0R_RTR_Pos (1U)

#define	CAN_TI0R_RTR_Msk (0x1UL << CAN_TI0R_RTR_Pos)

#define	CAN_TI0R_RTR CAN_TI0R_RTR_Msk

#define	CAN_TI0R_IDE_Pos (2U)

#define	CAN_TI0R_IDE_Msk (0x1UL << CAN_TI0R_IDE_Pos)

#define	CAN_TI0R_IDE CAN_TI0R_IDE_Msk

#define	CAN_TI0R_EXID_Pos (3U)

#define	CAN_TI0R_EXID_Msk (0x3FFFFUL << CAN_TI0R_EXID_Pos)

#define	CAN_TI0R_EXID CAN_TI0R_EXID_Msk

#define	CAN_TI0R_STID_Pos (21U)

#define	CAN_TI0R_STID_Msk (0x7FFUL << CAN_TI0R_STID_Pos)

#define	CAN_TI0R_STID CAN_TI0R_STID_Msk

#define	CAN_TDT0R_DLC_Pos (0U)

#define	CAN_TDT0R_DLC_Msk (0xFUL << CAN_TDT0R_DLC_Pos)

#define	CAN_TDT0R_DLC CAN_TDT0R_DLC_Msk

#define	CAN_TDT0R_TGT_Pos (8U)

#define	CAN_TDT0R_TGT_Msk (0x1UL << CAN_TDT0R_TGT_Pos)

#define	CAN_TDT0R_TGT CAN_TDT0R_TGT_Msk

#define	CAN_TDT0R_TIME_Pos (16U)

#define	CAN_TDT0R_TIME_Msk (0xFFFFUL << CAN_TDT0R_TIME_Pos)

#define	CAN_TDT0R_TIME CAN_TDT0R_TIME_Msk

#define	CAN_TDL0R_DATA0_Pos (0U)

#define	CAN_TDL0R_DATA0_Msk (0xFFUL << CAN_TDL0R_DATA0_Pos)

#define	CAN_TDL0R_DATA0 CAN_TDL0R_DATA0_Msk

#define	CAN_TDL0R_DATA1_Pos (8U)

#define	CAN_TDL0R_DATA1_Msk (0xFFUL << CAN_TDL0R_DATA1_Pos)

#define	CAN_TDL0R_DATA1 CAN_TDL0R_DATA1_Msk

#define	CAN_TDL0R_DATA2_Pos (16U)

#define	CAN_TDL0R_DATA2_Msk (0xFFUL << CAN_TDL0R_DATA2_Pos)

#define	CAN_TDL0R_DATA2 CAN_TDL0R_DATA2_Msk

#define	CAN_TDL0R_DATA3_Pos (24U)

#define	CAN_TDL0R_DATA3_Msk (0xFFUL << CAN_TDL0R_DATA3_Pos)

#define	CAN_TDL0R_DATA3 CAN_TDL0R_DATA3_Msk

#define	CAN_TDH0R_DATA4_Pos (0U)

#define	CAN_TDH0R_DATA4_Msk (0xFFUL << CAN_TDH0R_DATA4_Pos)

#define	CAN_TDH0R_DATA4 CAN_TDH0R_DATA4_Msk

#define	CAN_TDH0R_DATA5_Pos (8U)

#define	CAN_TDH0R_DATA5_Msk (0xFFUL << CAN_TDH0R_DATA5_Pos)

#define	CAN_TDH0R_DATA5 CAN_TDH0R_DATA5_Msk

#define	CAN_TDH0R_DATA6_Pos (16U)

#define	CAN_TDH0R_DATA6_Msk (0xFFUL << CAN_TDH0R_DATA6_Pos)

#define	CAN_TDH0R_DATA6 CAN_TDH0R_DATA6_Msk

#define	CAN_TDH0R_DATA7_Pos (24U)

#define	CAN_TDH0R_DATA7_Msk (0xFFUL << CAN_TDH0R_DATA7_Pos)

#define	CAN_TDH0R_DATA7 CAN_TDH0R_DATA7_Msk

#define	CAN_TI1R_TXRQ_Pos (0U)

#define	CAN_TI1R_TXRQ_Msk (0x1UL << CAN_TI1R_TXRQ_Pos)

#define	CAN_TI1R_TXRQ CAN_TI1R_TXRQ_Msk

#define	CAN_TI1R_RTR_Pos (1U)

#define	CAN_TI1R_RTR_Msk (0x1UL << CAN_TI1R_RTR_Pos)

#define	CAN_TI1R_RTR CAN_TI1R_RTR_Msk

#define	CAN_TI1R_IDE_Pos (2U)

#define	CAN_TI1R_IDE_Msk (0x1UL << CAN_TI1R_IDE_Pos)

#define	CAN_TI1R_IDE CAN_TI1R_IDE_Msk

#define	CAN_TI1R_EXID_Pos (3U)

#define	CAN_TI1R_EXID_Msk (0x3FFFFUL << CAN_TI1R_EXID_Pos)

#define	CAN_TI1R_EXID CAN_TI1R_EXID_Msk

#define	CAN_TI1R_STID_Pos (21U)

#define	CAN_TI1R_STID_Msk (0x7FFUL << CAN_TI1R_STID_Pos)

#define	CAN_TI1R_STID CAN_TI1R_STID_Msk

#define	CAN_TDT1R_DLC_Pos (0U)

#define	CAN_TDT1R_DLC_Msk (0xFUL << CAN_TDT1R_DLC_Pos)

#define	CAN_TDT1R_DLC CAN_TDT1R_DLC_Msk

#define	CAN_TDT1R_TGT_Pos (8U)

#define	CAN_TDT1R_TGT_Msk (0x1UL << CAN_TDT1R_TGT_Pos)

#define	CAN_TDT1R_TGT CAN_TDT1R_TGT_Msk

#define	CAN_TDT1R_TIME_Pos (16U)

#define	CAN_TDT1R_TIME_Msk (0xFFFFUL << CAN_TDT1R_TIME_Pos)

#define	CAN_TDT1R_TIME CAN_TDT1R_TIME_Msk

#define	CAN_TDL1R_DATA0_Pos (0U)

#define	CAN_TDL1R_DATA0_Msk (0xFFUL << CAN_TDL1R_DATA0_Pos)

#define	CAN_TDL1R_DATA0 CAN_TDL1R_DATA0_Msk

#define	CAN_TDL1R_DATA1_Pos (8U)

#define	CAN_TDL1R_DATA1_Msk (0xFFUL << CAN_TDL1R_DATA1_Pos)

#define	CAN_TDL1R_DATA1 CAN_TDL1R_DATA1_Msk

#define	CAN_TDL1R_DATA2_Pos (16U)

#define	CAN_TDL1R_DATA2_Msk (0xFFUL << CAN_TDL1R_DATA2_Pos)

#define	CAN_TDL1R_DATA2 CAN_TDL1R_DATA2_Msk

#define	CAN_TDL1R_DATA3_Pos (24U)

#define	CAN_TDL1R_DATA3_Msk (0xFFUL << CAN_TDL1R_DATA3_Pos)

#define	CAN_TDL1R_DATA3 CAN_TDL1R_DATA3_Msk

#define	CAN_TDH1R_DATA4_Pos (0U)

#define	CAN_TDH1R_DATA4_Msk (0xFFUL << CAN_TDH1R_DATA4_Pos)

#define	CAN_TDH1R_DATA4 CAN_TDH1R_DATA4_Msk

#define	CAN_TDH1R_DATA5_Pos (8U)

#define	CAN_TDH1R_DATA5_Msk (0xFFUL << CAN_TDH1R_DATA5_Pos)

#define	CAN_TDH1R_DATA5 CAN_TDH1R_DATA5_Msk

#define	CAN_TDH1R_DATA6_Pos (16U)

#define	CAN_TDH1R_DATA6_Msk (0xFFUL << CAN_TDH1R_DATA6_Pos)

#define	CAN_TDH1R_DATA6 CAN_TDH1R_DATA6_Msk

#define	CAN_TDH1R_DATA7_Pos (24U)

#define	CAN_TDH1R_DATA7_Msk (0xFFUL << CAN_TDH1R_DATA7_Pos)

#define	CAN_TDH1R_DATA7 CAN_TDH1R_DATA7_Msk

#define	CAN_TI2R_TXRQ_Pos (0U)

#define	CAN_TI2R_TXRQ_Msk (0x1UL << CAN_TI2R_TXRQ_Pos)

#define	CAN_TI2R_TXRQ CAN_TI2R_TXRQ_Msk

#define	CAN_TI2R_RTR_Pos (1U)

#define	CAN_TI2R_RTR_Msk (0x1UL << CAN_TI2R_RTR_Pos)

#define	CAN_TI2R_RTR CAN_TI2R_RTR_Msk

#define	CAN_TI2R_IDE_Pos (2U)

#define	CAN_TI2R_IDE_Msk (0x1UL << CAN_TI2R_IDE_Pos)

#define	CAN_TI2R_IDE CAN_TI2R_IDE_Msk

#define	CAN_TI2R_EXID_Pos (3U)

#define	CAN_TI2R_EXID_Msk (0x3FFFFUL << CAN_TI2R_EXID_Pos)

#define	CAN_TI2R_EXID CAN_TI2R_EXID_Msk

#define	CAN_TI2R_STID_Pos (21U)

#define	CAN_TI2R_STID_Msk (0x7FFUL << CAN_TI2R_STID_Pos)

#define	CAN_TI2R_STID CAN_TI2R_STID_Msk

#define	CAN_TDT2R_DLC_Pos (0U)

#define	CAN_TDT2R_DLC_Msk (0xFUL << CAN_TDT2R_DLC_Pos)

#define	CAN_TDT2R_DLC CAN_TDT2R_DLC_Msk

#define	CAN_TDT2R_TGT_Pos (8U)

#define	CAN_TDT2R_TGT_Msk (0x1UL << CAN_TDT2R_TGT_Pos)

#define	CAN_TDT2R_TGT CAN_TDT2R_TGT_Msk

#define	CAN_TDT2R_TIME_Pos (16U)

#define	CAN_TDT2R_TIME_Msk (0xFFFFUL << CAN_TDT2R_TIME_Pos)

#define	CAN_TDT2R_TIME CAN_TDT2R_TIME_Msk

#define	CAN_TDL2R_DATA0_Pos (0U)

#define	CAN_TDL2R_DATA0_Msk (0xFFUL << CAN_TDL2R_DATA0_Pos)

#define	CAN_TDL2R_DATA0 CAN_TDL2R_DATA0_Msk

#define	CAN_TDL2R_DATA1_Pos (8U)

#define	CAN_TDL2R_DATA1_Msk (0xFFUL << CAN_TDL2R_DATA1_Pos)

#define	CAN_TDL2R_DATA1 CAN_TDL2R_DATA1_Msk

#define	CAN_TDL2R_DATA2_Pos (16U)

#define	CAN_TDL2R_DATA2_Msk (0xFFUL << CAN_TDL2R_DATA2_Pos)

#define	CAN_TDL2R_DATA2 CAN_TDL2R_DATA2_Msk

#define	CAN_TDL2R_DATA3_Pos (24U)

#define	CAN_TDL2R_DATA3_Msk (0xFFUL << CAN_TDL2R_DATA3_Pos)

#define	CAN_TDL2R_DATA3 CAN_TDL2R_DATA3_Msk

#define	CAN_TDH2R_DATA4_Pos (0U)

#define	CAN_TDH2R_DATA4_Msk (0xFFUL << CAN_TDH2R_DATA4_Pos)

#define	CAN_TDH2R_DATA4 CAN_TDH2R_DATA4_Msk

#define	CAN_TDH2R_DATA5_Pos (8U)

#define	CAN_TDH2R_DATA5_Msk (0xFFUL << CAN_TDH2R_DATA5_Pos)

#define	CAN_TDH2R_DATA5 CAN_TDH2R_DATA5_Msk

#define	CAN_TDH2R_DATA6_Pos (16U)

#define	CAN_TDH2R_DATA6_Msk (0xFFUL << CAN_TDH2R_DATA6_Pos)

#define	CAN_TDH2R_DATA6 CAN_TDH2R_DATA6_Msk

#define	CAN_TDH2R_DATA7_Pos (24U)

#define	CAN_TDH2R_DATA7_Msk (0xFFUL << CAN_TDH2R_DATA7_Pos)

#define	CAN_TDH2R_DATA7 CAN_TDH2R_DATA7_Msk

#define	CAN_RI0R_RTR_Pos (1U)

#define	CAN_RI0R_RTR_Msk (0x1UL << CAN_RI0R_RTR_Pos)

#define	CAN_RI0R_RTR CAN_RI0R_RTR_Msk

#define	CAN_RI0R_IDE_Pos (2U)

#define	CAN_RI0R_IDE_Msk (0x1UL << CAN_RI0R_IDE_Pos)

#define	CAN_RI0R_IDE CAN_RI0R_IDE_Msk

#define	CAN_RI0R_EXID_Pos (3U)

#define	CAN_RI0R_EXID_Msk (0x3FFFFUL << CAN_RI0R_EXID_Pos)

#define	CAN_RI0R_EXID CAN_RI0R_EXID_Msk

#define	CAN_RI0R_STID_Pos (21U)

#define	CAN_RI0R_STID_Msk (0x7FFUL << CAN_RI0R_STID_Pos)

#define	CAN_RI0R_STID CAN_RI0R_STID_Msk

#define	CAN_RDT0R_DLC_Pos (0U)

#define	CAN_RDT0R_DLC_Msk (0xFUL << CAN_RDT0R_DLC_Pos)

#define	CAN_RDT0R_DLC CAN_RDT0R_DLC_Msk

#define	CAN_RDT0R_FMI_Pos (8U)

#define	CAN_RDT0R_FMI_Msk (0xFFUL << CAN_RDT0R_FMI_Pos)

#define	CAN_RDT0R_FMI CAN_RDT0R_FMI_Msk

#define	CAN_RDT0R_TIME_Pos (16U)

#define	CAN_RDT0R_TIME_Msk (0xFFFFUL << CAN_RDT0R_TIME_Pos)

#define	CAN_RDT0R_TIME CAN_RDT0R_TIME_Msk

#define	CAN_RDL0R_DATA0_Pos (0U)

#define	CAN_RDL0R_DATA0_Msk (0xFFUL << CAN_RDL0R_DATA0_Pos)

#define	CAN_RDL0R_DATA0 CAN_RDL0R_DATA0_Msk

#define	CAN_RDL0R_DATA1_Pos (8U)

#define	CAN_RDL0R_DATA1_Msk (0xFFUL << CAN_RDL0R_DATA1_Pos)

#define	CAN_RDL0R_DATA1 CAN_RDL0R_DATA1_Msk

#define	CAN_RDL0R_DATA2_Pos (16U)

#define	CAN_RDL0R_DATA2_Msk (0xFFUL << CAN_RDL0R_DATA2_Pos)

#define	CAN_RDL0R_DATA2 CAN_RDL0R_DATA2_Msk

#define	CAN_RDL0R_DATA3_Pos (24U)

#define	CAN_RDL0R_DATA3_Msk (0xFFUL << CAN_RDL0R_DATA3_Pos)

#define	CAN_RDL0R_DATA3 CAN_RDL0R_DATA3_Msk

#define	CAN_RDH0R_DATA4_Pos (0U)

#define	CAN_RDH0R_DATA4_Msk (0xFFUL << CAN_RDH0R_DATA4_Pos)

#define	CAN_RDH0R_DATA4 CAN_RDH0R_DATA4_Msk

#define	CAN_RDH0R_DATA5_Pos (8U)

#define	CAN_RDH0R_DATA5_Msk (0xFFUL << CAN_RDH0R_DATA5_Pos)

#define	CAN_RDH0R_DATA5 CAN_RDH0R_DATA5_Msk

#define	CAN_RDH0R_DATA6_Pos (16U)

#define	CAN_RDH0R_DATA6_Msk (0xFFUL << CAN_RDH0R_DATA6_Pos)

#define	CAN_RDH0R_DATA6 CAN_RDH0R_DATA6_Msk

#define	CAN_RDH0R_DATA7_Pos (24U)

#define	CAN_RDH0R_DATA7_Msk (0xFFUL << CAN_RDH0R_DATA7_Pos)

#define	CAN_RDH0R_DATA7 CAN_RDH0R_DATA7_Msk

#define	CAN_RI1R_RTR_Pos (1U)

#define	CAN_RI1R_RTR_Msk (0x1UL << CAN_RI1R_RTR_Pos)

#define	CAN_RI1R_RTR CAN_RI1R_RTR_Msk

#define	CAN_RI1R_IDE_Pos (2U)

#define	CAN_RI1R_IDE_Msk (0x1UL << CAN_RI1R_IDE_Pos)

#define	CAN_RI1R_IDE CAN_RI1R_IDE_Msk

#define	CAN_RI1R_EXID_Pos (3U)

#define	CAN_RI1R_EXID_Msk (0x3FFFFUL << CAN_RI1R_EXID_Pos)

#define	CAN_RI1R_EXID CAN_RI1R_EXID_Msk

#define	CAN_RI1R_STID_Pos (21U)

#define	CAN_RI1R_STID_Msk (0x7FFUL << CAN_RI1R_STID_Pos)

#define	CAN_RI1R_STID CAN_RI1R_STID_Msk

#define	CAN_RDT1R_DLC_Pos (0U)

#define	CAN_RDT1R_DLC_Msk (0xFUL << CAN_RDT1R_DLC_Pos)

#define	CAN_RDT1R_DLC CAN_RDT1R_DLC_Msk

#define	CAN_RDT1R_FMI_Pos (8U)

#define	CAN_RDT1R_FMI_Msk (0xFFUL << CAN_RDT1R_FMI_Pos)

#define	CAN_RDT1R_FMI CAN_RDT1R_FMI_Msk

#define	CAN_RDT1R_TIME_Pos (16U)

#define	CAN_RDT1R_TIME_Msk (0xFFFFUL << CAN_RDT1R_TIME_Pos)

#define	CAN_RDT1R_TIME CAN_RDT1R_TIME_Msk

#define	CAN_RDL1R_DATA0_Pos (0U)

#define	CAN_RDL1R_DATA0_Msk (0xFFUL << CAN_RDL1R_DATA0_Pos)

#define	CAN_RDL1R_DATA0 CAN_RDL1R_DATA0_Msk

#define	CAN_RDL1R_DATA1_Pos (8U)

#define	CAN_RDL1R_DATA1_Msk (0xFFUL << CAN_RDL1R_DATA1_Pos)

#define	CAN_RDL1R_DATA1 CAN_RDL1R_DATA1_Msk

#define	CAN_RDL1R_DATA2_Pos (16U)

#define	CAN_RDL1R_DATA2_Msk (0xFFUL << CAN_RDL1R_DATA2_Pos)

#define	CAN_RDL1R_DATA2 CAN_RDL1R_DATA2_Msk

#define	CAN_RDL1R_DATA3_Pos (24U)

#define	CAN_RDL1R_DATA3_Msk (0xFFUL << CAN_RDL1R_DATA3_Pos)

#define	CAN_RDL1R_DATA3 CAN_RDL1R_DATA3_Msk

#define	CAN_RDH1R_DATA4_Pos (0U)

#define	CAN_RDH1R_DATA4_Msk (0xFFUL << CAN_RDH1R_DATA4_Pos)

#define	CAN_RDH1R_DATA4 CAN_RDH1R_DATA4_Msk

#define	CAN_RDH1R_DATA5_Pos (8U)

#define	CAN_RDH1R_DATA5_Msk (0xFFUL << CAN_RDH1R_DATA5_Pos)

#define	CAN_RDH1R_DATA5 CAN_RDH1R_DATA5_Msk

#define	CAN_RDH1R_DATA6_Pos (16U)

#define	CAN_RDH1R_DATA6_Msk (0xFFUL << CAN_RDH1R_DATA6_Pos)

#define	CAN_RDH1R_DATA6 CAN_RDH1R_DATA6_Msk

#define	CAN_RDH1R_DATA7_Pos (24U)

#define	CAN_RDH1R_DATA7_Msk (0xFFUL << CAN_RDH1R_DATA7_Pos)

#define	CAN_RDH1R_DATA7 CAN_RDH1R_DATA7_Msk

#define	CAN_FMR_FINIT_Pos (0U)

#define	CAN_FMR_FINIT_Msk (0x1UL << CAN_FMR_FINIT_Pos)

#define	CAN_FMR_FINIT CAN_FMR_FINIT_Msk

#define	CAN_FM1R_FBM_Pos (0U)

#define	CAN_FM1R_FBM_Msk (0x3FFFUL << CAN_FM1R_FBM_Pos)

#define	CAN_FM1R_FBM CAN_FM1R_FBM_Msk

#define	CAN_FM1R_FBM0_Pos (0U)

#define	CAN_FM1R_FBM0_Msk (0x1UL << CAN_FM1R_FBM0_Pos)

#define	CAN_FM1R_FBM0 CAN_FM1R_FBM0_Msk

#define	CAN_FM1R_FBM1_Pos (1U)

#define	CAN_FM1R_FBM1_Msk (0x1UL << CAN_FM1R_FBM1_Pos)

#define	CAN_FM1R_FBM1 CAN_FM1R_FBM1_Msk

#define	CAN_FM1R_FBM2_Pos (2U)

#define	CAN_FM1R_FBM2_Msk (0x1UL << CAN_FM1R_FBM2_Pos)

#define	CAN_FM1R_FBM2 CAN_FM1R_FBM2_Msk

#define	CAN_FM1R_FBM3_Pos (3U)

#define	CAN_FM1R_FBM3_Msk (0x1UL << CAN_FM1R_FBM3_Pos)

#define	CAN_FM1R_FBM3 CAN_FM1R_FBM3_Msk

#define	CAN_FM1R_FBM4_Pos (4U)

#define	CAN_FM1R_FBM4_Msk (0x1UL << CAN_FM1R_FBM4_Pos)

#define	CAN_FM1R_FBM4 CAN_FM1R_FBM4_Msk

#define	CAN_FM1R_FBM5_Pos (5U)

#define	CAN_FM1R_FBM5_Msk (0x1UL << CAN_FM1R_FBM5_Pos)

#define	CAN_FM1R_FBM5 CAN_FM1R_FBM5_Msk

#define	CAN_FM1R_FBM6_Pos (6U)

#define	CAN_FM1R_FBM6_Msk (0x1UL << CAN_FM1R_FBM6_Pos)

#define	CAN_FM1R_FBM6 CAN_FM1R_FBM6_Msk

#define	CAN_FM1R_FBM7_Pos (7U)

#define	CAN_FM1R_FBM7_Msk (0x1UL << CAN_FM1R_FBM7_Pos)

#define	CAN_FM1R_FBM7 CAN_FM1R_FBM7_Msk

#define	CAN_FM1R_FBM8_Pos (8U)

#define	CAN_FM1R_FBM8_Msk (0x1UL << CAN_FM1R_FBM8_Pos)

#define	CAN_FM1R_FBM8 CAN_FM1R_FBM8_Msk

#define	CAN_FM1R_FBM9_Pos (9U)

#define	CAN_FM1R_FBM9_Msk (0x1UL << CAN_FM1R_FBM9_Pos)

#define	CAN_FM1R_FBM9 CAN_FM1R_FBM9_Msk

#define	CAN_FM1R_FBM10_Pos (10U)

#define	CAN_FM1R_FBM10_Msk (0x1UL << CAN_FM1R_FBM10_Pos)

#define	CAN_FM1R_FBM10 CAN_FM1R_FBM10_Msk

#define	CAN_FM1R_FBM11_Pos (11U)

#define	CAN_FM1R_FBM11_Msk (0x1UL << CAN_FM1R_FBM11_Pos)

#define	CAN_FM1R_FBM11 CAN_FM1R_FBM11_Msk

#define	CAN_FM1R_FBM12_Pos (12U)

#define	CAN_FM1R_FBM12_Msk (0x1UL << CAN_FM1R_FBM12_Pos)

#define	CAN_FM1R_FBM12 CAN_FM1R_FBM12_Msk

#define	CAN_FM1R_FBM13_Pos (13U)

#define	CAN_FM1R_FBM13_Msk (0x1UL << CAN_FM1R_FBM13_Pos)

#define	CAN_FM1R_FBM13 CAN_FM1R_FBM13_Msk

#define	CAN_FS1R_FSC_Pos (0U)

#define	CAN_FS1R_FSC_Msk (0x3FFFUL << CAN_FS1R_FSC_Pos)

#define	CAN_FS1R_FSC CAN_FS1R_FSC_Msk

#define	CAN_FS1R_FSC0_Pos (0U)

#define	CAN_FS1R_FSC0_Msk (0x1UL << CAN_FS1R_FSC0_Pos)

#define	CAN_FS1R_FSC0 CAN_FS1R_FSC0_Msk

#define	CAN_FS1R_FSC1_Pos (1U)

#define	CAN_FS1R_FSC1_Msk (0x1UL << CAN_FS1R_FSC1_Pos)

#define	CAN_FS1R_FSC1 CAN_FS1R_FSC1_Msk

#define	CAN_FS1R_FSC2_Pos (2U)

#define	CAN_FS1R_FSC2_Msk (0x1UL << CAN_FS1R_FSC2_Pos)

#define	CAN_FS1R_FSC2 CAN_FS1R_FSC2_Msk

#define	CAN_FS1R_FSC3_Pos (3U)

#define	CAN_FS1R_FSC3_Msk (0x1UL << CAN_FS1R_FSC3_Pos)

#define	CAN_FS1R_FSC3 CAN_FS1R_FSC3_Msk

#define	CAN_FS1R_FSC4_Pos (4U)

#define	CAN_FS1R_FSC4_Msk (0x1UL << CAN_FS1R_FSC4_Pos)

#define	CAN_FS1R_FSC4 CAN_FS1R_FSC4_Msk

#define	CAN_FS1R_FSC5_Pos (5U)

#define	CAN_FS1R_FSC5_Msk (0x1UL << CAN_FS1R_FSC5_Pos)

#define	CAN_FS1R_FSC5 CAN_FS1R_FSC5_Msk

#define	CAN_FS1R_FSC6_Pos (6U)

#define	CAN_FS1R_FSC6_Msk (0x1UL << CAN_FS1R_FSC6_Pos)

#define	CAN_FS1R_FSC6 CAN_FS1R_FSC6_Msk

#define	CAN_FS1R_FSC7_Pos (7U)

#define	CAN_FS1R_FSC7_Msk (0x1UL << CAN_FS1R_FSC7_Pos)

#define	CAN_FS1R_FSC7 CAN_FS1R_FSC7_Msk

#define	CAN_FS1R_FSC8_Pos (8U)

#define	CAN_FS1R_FSC8_Msk (0x1UL << CAN_FS1R_FSC8_Pos)

#define	CAN_FS1R_FSC8 CAN_FS1R_FSC8_Msk

#define	CAN_FS1R_FSC9_Pos (9U)

#define	CAN_FS1R_FSC9_Msk (0x1UL << CAN_FS1R_FSC9_Pos)

#define	CAN_FS1R_FSC9 CAN_FS1R_FSC9_Msk

#define	CAN_FS1R_FSC10_Pos (10U)

#define	CAN_FS1R_FSC10_Msk (0x1UL << CAN_FS1R_FSC10_Pos)

#define	CAN_FS1R_FSC10 CAN_FS1R_FSC10_Msk

#define	CAN_FS1R_FSC11_Pos (11U)

#define	CAN_FS1R_FSC11_Msk (0x1UL << CAN_FS1R_FSC11_Pos)

#define	CAN_FS1R_FSC11 CAN_FS1R_FSC11_Msk

#define	CAN_FS1R_FSC12_Pos (12U)

#define	CAN_FS1R_FSC12_Msk (0x1UL << CAN_FS1R_FSC12_Pos)

#define	CAN_FS1R_FSC12 CAN_FS1R_FSC12_Msk

#define	CAN_FS1R_FSC13_Pos (13U)

#define	CAN_FS1R_FSC13_Msk (0x1UL << CAN_FS1R_FSC13_Pos)

#define	CAN_FS1R_FSC13 CAN_FS1R_FSC13_Msk

#define	CAN_FFA1R_FFA_Pos (0U)

#define	CAN_FFA1R_FFA_Msk (0x3FFFUL << CAN_FFA1R_FFA_Pos)

#define	CAN_FFA1R_FFA CAN_FFA1R_FFA_Msk

#define	CAN_FFA1R_FFA0_Pos (0U)

#define	CAN_FFA1R_FFA0_Msk (0x1UL << CAN_FFA1R_FFA0_Pos)

#define	CAN_FFA1R_FFA0 CAN_FFA1R_FFA0_Msk

#define	CAN_FFA1R_FFA1_Pos (1U)

#define	CAN_FFA1R_FFA1_Msk (0x1UL << CAN_FFA1R_FFA1_Pos)

#define	CAN_FFA1R_FFA1 CAN_FFA1R_FFA1_Msk

#define	CAN_FFA1R_FFA2_Pos (2U)

#define	CAN_FFA1R_FFA2_Msk (0x1UL << CAN_FFA1R_FFA2_Pos)

#define	CAN_FFA1R_FFA2 CAN_FFA1R_FFA2_Msk

#define	CAN_FFA1R_FFA3_Pos (3U)

#define	CAN_FFA1R_FFA3_Msk (0x1UL << CAN_FFA1R_FFA3_Pos)

#define	CAN_FFA1R_FFA3 CAN_FFA1R_FFA3_Msk

#define	CAN_FFA1R_FFA4_Pos (4U)

#define	CAN_FFA1R_FFA4_Msk (0x1UL << CAN_FFA1R_FFA4_Pos)

#define	CAN_FFA1R_FFA4 CAN_FFA1R_FFA4_Msk

#define	CAN_FFA1R_FFA5_Pos (5U)

#define	CAN_FFA1R_FFA5_Msk (0x1UL << CAN_FFA1R_FFA5_Pos)

#define	CAN_FFA1R_FFA5 CAN_FFA1R_FFA5_Msk

#define	CAN_FFA1R_FFA6_Pos (6U)

#define	CAN_FFA1R_FFA6_Msk (0x1UL << CAN_FFA1R_FFA6_Pos)

#define	CAN_FFA1R_FFA6 CAN_FFA1R_FFA6_Msk

#define	CAN_FFA1R_FFA7_Pos (7U)

#define	CAN_FFA1R_FFA7_Msk (0x1UL << CAN_FFA1R_FFA7_Pos)

#define	CAN_FFA1R_FFA7 CAN_FFA1R_FFA7_Msk

#define	CAN_FFA1R_FFA8_Pos (8U)

#define	CAN_FFA1R_FFA8_Msk (0x1UL << CAN_FFA1R_FFA8_Pos)

#define	CAN_FFA1R_FFA8 CAN_FFA1R_FFA8_Msk

#define	CAN_FFA1R_FFA9_Pos (9U)

#define	CAN_FFA1R_FFA9_Msk (0x1UL << CAN_FFA1R_FFA9_Pos)

#define	CAN_FFA1R_FFA9 CAN_FFA1R_FFA9_Msk

#define	CAN_FFA1R_FFA10_Pos (10U)

#define	CAN_FFA1R_FFA10_Msk (0x1UL << CAN_FFA1R_FFA10_Pos)

#define	CAN_FFA1R_FFA10 CAN_FFA1R_FFA10_Msk

#define	CAN_FFA1R_FFA11_Pos (11U)

#define	CAN_FFA1R_FFA11_Msk (0x1UL << CAN_FFA1R_FFA11_Pos)

#define	CAN_FFA1R_FFA11 CAN_FFA1R_FFA11_Msk

#define	CAN_FFA1R_FFA12_Pos (12U)

#define	CAN_FFA1R_FFA12_Msk (0x1UL << CAN_FFA1R_FFA12_Pos)

#define	CAN_FFA1R_FFA12 CAN_FFA1R_FFA12_Msk

#define	CAN_FFA1R_FFA13_Pos (13U)

#define	CAN_FFA1R_FFA13_Msk (0x1UL << CAN_FFA1R_FFA13_Pos)

#define	CAN_FFA1R_FFA13 CAN_FFA1R_FFA13_Msk

#define	CAN_FA1R_FACT_Pos (0U)

#define	CAN_FA1R_FACT_Msk (0x3FFFUL << CAN_FA1R_FACT_Pos)

#define	CAN_FA1R_FACT CAN_FA1R_FACT_Msk

#define	CAN_FA1R_FACT0_Pos (0U)

#define	CAN_FA1R_FACT0_Msk (0x1UL << CAN_FA1R_FACT0_Pos)

#define	CAN_FA1R_FACT0 CAN_FA1R_FACT0_Msk

#define	CAN_FA1R_FACT1_Pos (1U)

#define	CAN_FA1R_FACT1_Msk (0x1UL << CAN_FA1R_FACT1_Pos)

#define	CAN_FA1R_FACT1 CAN_FA1R_FACT1_Msk

#define	CAN_FA1R_FACT2_Pos (2U)

#define	CAN_FA1R_FACT2_Msk (0x1UL << CAN_FA1R_FACT2_Pos)

#define	CAN_FA1R_FACT2 CAN_FA1R_FACT2_Msk

#define	CAN_FA1R_FACT3_Pos (3U)

#define	CAN_FA1R_FACT3_Msk (0x1UL << CAN_FA1R_FACT3_Pos)

#define	CAN_FA1R_FACT3 CAN_FA1R_FACT3_Msk

#define	CAN_FA1R_FACT4_Pos (4U)

#define	CAN_FA1R_FACT4_Msk (0x1UL << CAN_FA1R_FACT4_Pos)

#define	CAN_FA1R_FACT4 CAN_FA1R_FACT4_Msk

#define	CAN_FA1R_FACT5_Pos (5U)

#define	CAN_FA1R_FACT5_Msk (0x1UL << CAN_FA1R_FACT5_Pos)

#define	CAN_FA1R_FACT5 CAN_FA1R_FACT5_Msk

#define	CAN_FA1R_FACT6_Pos (6U)

#define	CAN_FA1R_FACT6_Msk (0x1UL << CAN_FA1R_FACT6_Pos)

#define	CAN_FA1R_FACT6 CAN_FA1R_FACT6_Msk

#define	CAN_FA1R_FACT7_Pos (7U)

#define	CAN_FA1R_FACT7_Msk (0x1UL << CAN_FA1R_FACT7_Pos)

#define	CAN_FA1R_FACT7 CAN_FA1R_FACT7_Msk

#define	CAN_FA1R_FACT8_Pos (8U)

#define	CAN_FA1R_FACT8_Msk (0x1UL << CAN_FA1R_FACT8_Pos)

#define	CAN_FA1R_FACT8 CAN_FA1R_FACT8_Msk

#define	CAN_FA1R_FACT9_Pos (9U)

#define	CAN_FA1R_FACT9_Msk (0x1UL << CAN_FA1R_FACT9_Pos)

#define	CAN_FA1R_FACT9 CAN_FA1R_FACT9_Msk

#define	CAN_FA1R_FACT10_Pos (10U)

#define	CAN_FA1R_FACT10_Msk (0x1UL << CAN_FA1R_FACT10_Pos)

#define	CAN_FA1R_FACT10 CAN_FA1R_FACT10_Msk

#define	CAN_FA1R_FACT11_Pos (11U)

#define	CAN_FA1R_FACT11_Msk (0x1UL << CAN_FA1R_FACT11_Pos)

#define	CAN_FA1R_FACT11 CAN_FA1R_FACT11_Msk

#define	CAN_FA1R_FACT12_Pos (12U)

#define	CAN_FA1R_FACT12_Msk (0x1UL << CAN_FA1R_FACT12_Pos)

#define	CAN_FA1R_FACT12 CAN_FA1R_FACT12_Msk

#define	CAN_FA1R_FACT13_Pos (13U)

#define	CAN_FA1R_FACT13_Msk (0x1UL << CAN_FA1R_FACT13_Pos)

#define	CAN_FA1R_FACT13 CAN_FA1R_FACT13_Msk

#define	CAN_F0R1_FB0_Pos (0U)

#define	CAN_F0R1_FB0_Msk (0x1UL << CAN_F0R1_FB0_Pos)

#define	CAN_F0R1_FB0 CAN_F0R1_FB0_Msk

#define	CAN_F0R1_FB1_Pos (1U)

#define	CAN_F0R1_FB1_Msk (0x1UL << CAN_F0R1_FB1_Pos)

#define	CAN_F0R1_FB1 CAN_F0R1_FB1_Msk

#define	CAN_F0R1_FB2_Pos (2U)

#define	CAN_F0R1_FB2_Msk (0x1UL << CAN_F0R1_FB2_Pos)

#define	CAN_F0R1_FB2 CAN_F0R1_FB2_Msk

#define	CAN_F0R1_FB3_Pos (3U)

#define	CAN_F0R1_FB3_Msk (0x1UL << CAN_F0R1_FB3_Pos)

#define	CAN_F0R1_FB3 CAN_F0R1_FB3_Msk

#define	CAN_F0R1_FB4_Pos (4U)

#define	CAN_F0R1_FB4_Msk (0x1UL << CAN_F0R1_FB4_Pos)

#define	CAN_F0R1_FB4 CAN_F0R1_FB4_Msk

#define	CAN_F0R1_FB5_Pos (5U)

#define	CAN_F0R1_FB5_Msk (0x1UL << CAN_F0R1_FB5_Pos)

#define	CAN_F0R1_FB5 CAN_F0R1_FB5_Msk

#define	CAN_F0R1_FB6_Pos (6U)

#define	CAN_F0R1_FB6_Msk (0x1UL << CAN_F0R1_FB6_Pos)

#define	CAN_F0R1_FB6 CAN_F0R1_FB6_Msk

#define	CAN_F0R1_FB7_Pos (7U)

#define	CAN_F0R1_FB7_Msk (0x1UL << CAN_F0R1_FB7_Pos)

#define	CAN_F0R1_FB7 CAN_F0R1_FB7_Msk

#define	CAN_F0R1_FB8_Pos (8U)

#define	CAN_F0R1_FB8_Msk (0x1UL << CAN_F0R1_FB8_Pos)

#define	CAN_F0R1_FB8 CAN_F0R1_FB8_Msk

#define	CAN_F0R1_FB9_Pos (9U)

#define	CAN_F0R1_FB9_Msk (0x1UL << CAN_F0R1_FB9_Pos)

#define	CAN_F0R1_FB9 CAN_F0R1_FB9_Msk

#define	CAN_F0R1_FB10_Pos (10U)

#define	CAN_F0R1_FB10_Msk (0x1UL << CAN_F0R1_FB10_Pos)

#define	CAN_F0R1_FB10 CAN_F0R1_FB10_Msk

#define	CAN_F0R1_FB11_Pos (11U)

#define	CAN_F0R1_FB11_Msk (0x1UL << CAN_F0R1_FB11_Pos)

#define	CAN_F0R1_FB11 CAN_F0R1_FB11_Msk

#define	CAN_F0R1_FB12_Pos (12U)

#define	CAN_F0R1_FB12_Msk (0x1UL << CAN_F0R1_FB12_Pos)

#define	CAN_F0R1_FB12 CAN_F0R1_FB12_Msk

#define	CAN_F0R1_FB13_Pos (13U)

#define	CAN_F0R1_FB13_Msk (0x1UL << CAN_F0R1_FB13_Pos)

#define	CAN_F0R1_FB13 CAN_F0R1_FB13_Msk

#define	CAN_F0R1_FB14_Pos (14U)

#define	CAN_F0R1_FB14_Msk (0x1UL << CAN_F0R1_FB14_Pos)

#define	CAN_F0R1_FB14 CAN_F0R1_FB14_Msk

#define	CAN_F0R1_FB15_Pos (15U)

#define	CAN_F0R1_FB15_Msk (0x1UL << CAN_F0R1_FB15_Pos)

#define	CAN_F0R1_FB15 CAN_F0R1_FB15_Msk

#define	CAN_F0R1_FB16_Pos (16U)

#define	CAN_F0R1_FB16_Msk (0x1UL << CAN_F0R1_FB16_Pos)

#define	CAN_F0R1_FB16 CAN_F0R1_FB16_Msk

#define	CAN_F0R1_FB17_Pos (17U)

#define	CAN_F0R1_FB17_Msk (0x1UL << CAN_F0R1_FB17_Pos)

#define	CAN_F0R1_FB17 CAN_F0R1_FB17_Msk

#define	CAN_F0R1_FB18_Pos (18U)

#define	CAN_F0R1_FB18_Msk (0x1UL << CAN_F0R1_FB18_Pos)

#define	CAN_F0R1_FB18 CAN_F0R1_FB18_Msk

#define	CAN_F0R1_FB19_Pos (19U)

#define	CAN_F0R1_FB19_Msk (0x1UL << CAN_F0R1_FB19_Pos)

#define	CAN_F0R1_FB19 CAN_F0R1_FB19_Msk

#define	CAN_F0R1_FB20_Pos (20U)

#define	CAN_F0R1_FB20_Msk (0x1UL << CAN_F0R1_FB20_Pos)

#define	CAN_F0R1_FB20 CAN_F0R1_FB20_Msk

#define	CAN_F0R1_FB21_Pos (21U)

#define	CAN_F0R1_FB21_Msk (0x1UL << CAN_F0R1_FB21_Pos)

#define	CAN_F0R1_FB21 CAN_F0R1_FB21_Msk

#define	CAN_F0R1_FB22_Pos (22U)

#define	CAN_F0R1_FB22_Msk (0x1UL << CAN_F0R1_FB22_Pos)

#define	CAN_F0R1_FB22 CAN_F0R1_FB22_Msk

#define	CAN_F0R1_FB23_Pos (23U)

#define	CAN_F0R1_FB23_Msk (0x1UL << CAN_F0R1_FB23_Pos)

#define	CAN_F0R1_FB23 CAN_F0R1_FB23_Msk

#define	CAN_F0R1_FB24_Pos (24U)

#define	CAN_F0R1_FB24_Msk (0x1UL << CAN_F0R1_FB24_Pos)

#define	CAN_F0R1_FB24 CAN_F0R1_FB24_Msk

#define	CAN_F0R1_FB25_Pos (25U)

#define	CAN_F0R1_FB25_Msk (0x1UL << CAN_F0R1_FB25_Pos)

#define	CAN_F0R1_FB25 CAN_F0R1_FB25_Msk

#define	CAN_F0R1_FB26_Pos (26U)

#define	CAN_F0R1_FB26_Msk (0x1UL << CAN_F0R1_FB26_Pos)

#define	CAN_F0R1_FB26 CAN_F0R1_FB26_Msk

#define	CAN_F0R1_FB27_Pos (27U)

#define	CAN_F0R1_FB27_Msk (0x1UL << CAN_F0R1_FB27_Pos)

#define	CAN_F0R1_FB27 CAN_F0R1_FB27_Msk

#define	CAN_F0R1_FB28_Pos (28U)

#define	CAN_F0R1_FB28_Msk (0x1UL << CAN_F0R1_FB28_Pos)

#define	CAN_F0R1_FB28 CAN_F0R1_FB28_Msk

#define	CAN_F0R1_FB29_Pos (29U)

#define	CAN_F0R1_FB29_Msk (0x1UL << CAN_F0R1_FB29_Pos)

#define	CAN_F0R1_FB29 CAN_F0R1_FB29_Msk

#define	CAN_F0R1_FB30_Pos (30U)

#define	CAN_F0R1_FB30_Msk (0x1UL << CAN_F0R1_FB30_Pos)

#define	CAN_F0R1_FB30 CAN_F0R1_FB30_Msk

#define	CAN_F0R1_FB31_Pos (31U)

#define	CAN_F0R1_FB31_Msk (0x1UL << CAN_F0R1_FB31_Pos)

#define	CAN_F0R1_FB31 CAN_F0R1_FB31_Msk

#define	CAN_F1R1_FB0_Pos (0U)

#define	CAN_F1R1_FB0_Msk (0x1UL << CAN_F1R1_FB0_Pos)

#define	CAN_F1R1_FB0 CAN_F1R1_FB0_Msk

#define	CAN_F1R1_FB1_Pos (1U)

#define	CAN_F1R1_FB1_Msk (0x1UL << CAN_F1R1_FB1_Pos)

#define	CAN_F1R1_FB1 CAN_F1R1_FB1_Msk

#define	CAN_F1R1_FB2_Pos (2U)

#define	CAN_F1R1_FB2_Msk (0x1UL << CAN_F1R1_FB2_Pos)

#define	CAN_F1R1_FB2 CAN_F1R1_FB2_Msk

#define	CAN_F1R1_FB3_Pos (3U)

#define	CAN_F1R1_FB3_Msk (0x1UL << CAN_F1R1_FB3_Pos)

#define	CAN_F1R1_FB3 CAN_F1R1_FB3_Msk

#define	CAN_F1R1_FB4_Pos (4U)

#define	CAN_F1R1_FB4_Msk (0x1UL << CAN_F1R1_FB4_Pos)

#define	CAN_F1R1_FB4 CAN_F1R1_FB4_Msk

#define	CAN_F1R1_FB5_Pos (5U)

#define	CAN_F1R1_FB5_Msk (0x1UL << CAN_F1R1_FB5_Pos)

#define	CAN_F1R1_FB5 CAN_F1R1_FB5_Msk

#define	CAN_F1R1_FB6_Pos (6U)

#define	CAN_F1R1_FB6_Msk (0x1UL << CAN_F1R1_FB6_Pos)

#define	CAN_F1R1_FB6 CAN_F1R1_FB6_Msk

#define	CAN_F1R1_FB7_Pos (7U)

#define	CAN_F1R1_FB7_Msk (0x1UL << CAN_F1R1_FB7_Pos)

#define	CAN_F1R1_FB7 CAN_F1R1_FB7_Msk

#define	CAN_F1R1_FB8_Pos (8U)

#define	CAN_F1R1_FB8_Msk (0x1UL << CAN_F1R1_FB8_Pos)

#define	CAN_F1R1_FB8 CAN_F1R1_FB8_Msk

#define	CAN_F1R1_FB9_Pos (9U)

#define	CAN_F1R1_FB9_Msk (0x1UL << CAN_F1R1_FB9_Pos)

#define	CAN_F1R1_FB9 CAN_F1R1_FB9_Msk

#define	CAN_F1R1_FB10_Pos (10U)

#define	CAN_F1R1_FB10_Msk (0x1UL << CAN_F1R1_FB10_Pos)

#define	CAN_F1R1_FB10 CAN_F1R1_FB10_Msk

#define	CAN_F1R1_FB11_Pos (11U)

#define	CAN_F1R1_FB11_Msk (0x1UL << CAN_F1R1_FB11_Pos)

#define	CAN_F1R1_FB11 CAN_F1R1_FB11_Msk

#define	CAN_F1R1_FB12_Pos (12U)

#define	CAN_F1R1_FB12_Msk (0x1UL << CAN_F1R1_FB12_Pos)

#define	CAN_F1R1_FB12 CAN_F1R1_FB12_Msk

#define	CAN_F1R1_FB13_Pos (13U)

#define	CAN_F1R1_FB13_Msk (0x1UL << CAN_F1R1_FB13_Pos)

#define	CAN_F1R1_FB13 CAN_F1R1_FB13_Msk

#define	CAN_F1R1_FB14_Pos (14U)

#define	CAN_F1R1_FB14_Msk (0x1UL << CAN_F1R1_FB14_Pos)

#define	CAN_F1R1_FB14 CAN_F1R1_FB14_Msk

#define	CAN_F1R1_FB15_Pos (15U)

#define	CAN_F1R1_FB15_Msk (0x1UL << CAN_F1R1_FB15_Pos)

#define	CAN_F1R1_FB15 CAN_F1R1_FB15_Msk

#define	CAN_F1R1_FB16_Pos (16U)

#define	CAN_F1R1_FB16_Msk (0x1UL << CAN_F1R1_FB16_Pos)

#define	CAN_F1R1_FB16 CAN_F1R1_FB16_Msk

#define	CAN_F1R1_FB17_Pos (17U)

#define	CAN_F1R1_FB17_Msk (0x1UL << CAN_F1R1_FB17_Pos)

#define	CAN_F1R1_FB17 CAN_F1R1_FB17_Msk

#define	CAN_F1R1_FB18_Pos (18U)

#define	CAN_F1R1_FB18_Msk (0x1UL << CAN_F1R1_FB18_Pos)

#define	CAN_F1R1_FB18 CAN_F1R1_FB18_Msk

#define	CAN_F1R1_FB19_Pos (19U)

#define	CAN_F1R1_FB19_Msk (0x1UL << CAN_F1R1_FB19_Pos)

#define	CAN_F1R1_FB19 CAN_F1R1_FB19_Msk

#define	CAN_F1R1_FB20_Pos (20U)

#define	CAN_F1R1_FB20_Msk (0x1UL << CAN_F1R1_FB20_Pos)

#define	CAN_F1R1_FB20 CAN_F1R1_FB20_Msk

#define	CAN_F1R1_FB21_Pos (21U)

#define	CAN_F1R1_FB21_Msk (0x1UL << CAN_F1R1_FB21_Pos)

#define	CAN_F1R1_FB21 CAN_F1R1_FB21_Msk

#define	CAN_F1R1_FB22_Pos (22U)

#define	CAN_F1R1_FB22_Msk (0x1UL << CAN_F1R1_FB22_Pos)

#define	CAN_F1R1_FB22 CAN_F1R1_FB22_Msk

#define	CAN_F1R1_FB23_Pos (23U)

#define	CAN_F1R1_FB23_Msk (0x1UL << CAN_F1R1_FB23_Pos)

#define	CAN_F1R1_FB23 CAN_F1R1_FB23_Msk

#define	CAN_F1R1_FB24_Pos (24U)

#define	CAN_F1R1_FB24_Msk (0x1UL << CAN_F1R1_FB24_Pos)

#define	CAN_F1R1_FB24 CAN_F1R1_FB24_Msk

#define	CAN_F1R1_FB25_Pos (25U)

#define	CAN_F1R1_FB25_Msk (0x1UL << CAN_F1R1_FB25_Pos)

#define	CAN_F1R1_FB25 CAN_F1R1_FB25_Msk

#define	CAN_F1R1_FB26_Pos (26U)

#define	CAN_F1R1_FB26_Msk (0x1UL << CAN_F1R1_FB26_Pos)

#define	CAN_F1R1_FB26 CAN_F1R1_FB26_Msk

#define	CAN_F1R1_FB27_Pos (27U)

#define	CAN_F1R1_FB27_Msk (0x1UL << CAN_F1R1_FB27_Pos)

#define	CAN_F1R1_FB27 CAN_F1R1_FB27_Msk

#define	CAN_F1R1_FB28_Pos (28U)

#define	CAN_F1R1_FB28_Msk (0x1UL << CAN_F1R1_FB28_Pos)

#define	CAN_F1R1_FB28 CAN_F1R1_FB28_Msk

#define	CAN_F1R1_FB29_Pos (29U)

#define	CAN_F1R1_FB29_Msk (0x1UL << CAN_F1R1_FB29_Pos)

#define	CAN_F1R1_FB29 CAN_F1R1_FB29_Msk

#define	CAN_F1R1_FB30_Pos (30U)

#define	CAN_F1R1_FB30_Msk (0x1UL << CAN_F1R1_FB30_Pos)

#define	CAN_F1R1_FB30 CAN_F1R1_FB30_Msk

#define	CAN_F1R1_FB31_Pos (31U)

#define	CAN_F1R1_FB31_Msk (0x1UL << CAN_F1R1_FB31_Pos)

#define	CAN_F1R1_FB31 CAN_F1R1_FB31_Msk

#define	CAN_F2R1_FB0_Pos (0U)

#define	CAN_F2R1_FB0_Msk (0x1UL << CAN_F2R1_FB0_Pos)

#define	CAN_F2R1_FB0 CAN_F2R1_FB0_Msk

#define	CAN_F2R1_FB1_Pos (1U)

#define	CAN_F2R1_FB1_Msk (0x1UL << CAN_F2R1_FB1_Pos)

#define	CAN_F2R1_FB1 CAN_F2R1_FB1_Msk

#define	CAN_F2R1_FB2_Pos (2U)

#define	CAN_F2R1_FB2_Msk (0x1UL << CAN_F2R1_FB2_Pos)

#define	CAN_F2R1_FB2 CAN_F2R1_FB2_Msk

#define	CAN_F2R1_FB3_Pos (3U)

#define	CAN_F2R1_FB3_Msk (0x1UL << CAN_F2R1_FB3_Pos)

#define	CAN_F2R1_FB3 CAN_F2R1_FB3_Msk

#define	CAN_F2R1_FB4_Pos (4U)

#define	CAN_F2R1_FB4_Msk (0x1UL << CAN_F2R1_FB4_Pos)

#define	CAN_F2R1_FB4 CAN_F2R1_FB4_Msk

#define	CAN_F2R1_FB5_Pos (5U)

#define	CAN_F2R1_FB5_Msk (0x1UL << CAN_F2R1_FB5_Pos)

#define	CAN_F2R1_FB5 CAN_F2R1_FB5_Msk

#define	CAN_F2R1_FB6_Pos (6U)

#define	CAN_F2R1_FB6_Msk (0x1UL << CAN_F2R1_FB6_Pos)

#define	CAN_F2R1_FB6 CAN_F2R1_FB6_Msk

#define	CAN_F2R1_FB7_Pos (7U)

#define	CAN_F2R1_FB7_Msk (0x1UL << CAN_F2R1_FB7_Pos)

#define	CAN_F2R1_FB7 CAN_F2R1_FB7_Msk

#define	CAN_F2R1_FB8_Pos (8U)

#define	CAN_F2R1_FB8_Msk (0x1UL << CAN_F2R1_FB8_Pos)

#define	CAN_F2R1_FB8 CAN_F2R1_FB8_Msk

#define	CAN_F2R1_FB9_Pos (9U)

#define	CAN_F2R1_FB9_Msk (0x1UL << CAN_F2R1_FB9_Pos)

#define	CAN_F2R1_FB9 CAN_F2R1_FB9_Msk

#define	CAN_F2R1_FB10_Pos (10U)

#define	CAN_F2R1_FB10_Msk (0x1UL << CAN_F2R1_FB10_Pos)

#define	CAN_F2R1_FB10 CAN_F2R1_FB10_Msk

#define	CAN_F2R1_FB11_Pos (11U)

#define	CAN_F2R1_FB11_Msk (0x1UL << CAN_F2R1_FB11_Pos)

#define	CAN_F2R1_FB11 CAN_F2R1_FB11_Msk

#define	CAN_F2R1_FB12_Pos (12U)

#define	CAN_F2R1_FB12_Msk (0x1UL << CAN_F2R1_FB12_Pos)

#define	CAN_F2R1_FB12 CAN_F2R1_FB12_Msk

#define	CAN_F2R1_FB13_Pos (13U)

#define	CAN_F2R1_FB13_Msk (0x1UL << CAN_F2R1_FB13_Pos)

#define	CAN_F2R1_FB13 CAN_F2R1_FB13_Msk

#define	CAN_F2R1_FB14_Pos (14U)

#define	CAN_F2R1_FB14_Msk (0x1UL << CAN_F2R1_FB14_Pos)

#define	CAN_F2R1_FB14 CAN_F2R1_FB14_Msk

#define	CAN_F2R1_FB15_Pos (15U)

#define	CAN_F2R1_FB15_Msk (0x1UL << CAN_F2R1_FB15_Pos)

#define	CAN_F2R1_FB15 CAN_F2R1_FB15_Msk

#define	CAN_F2R1_FB16_Pos (16U)

#define	CAN_F2R1_FB16_Msk (0x1UL << CAN_F2R1_FB16_Pos)

#define	CAN_F2R1_FB16 CAN_F2R1_FB16_Msk

#define	CAN_F2R1_FB17_Pos (17U)

#define	CAN_F2R1_FB17_Msk (0x1UL << CAN_F2R1_FB17_Pos)

#define	CAN_F2R1_FB17 CAN_F2R1_FB17_Msk

#define	CAN_F2R1_FB18_Pos (18U)

#define	CAN_F2R1_FB18_Msk (0x1UL << CAN_F2R1_FB18_Pos)

#define	CAN_F2R1_FB18 CAN_F2R1_FB18_Msk

#define	CAN_F2R1_FB19_Pos (19U)

#define	CAN_F2R1_FB19_Msk (0x1UL << CAN_F2R1_FB19_Pos)

#define	CAN_F2R1_FB19 CAN_F2R1_FB19_Msk

#define	CAN_F2R1_FB20_Pos (20U)

#define	CAN_F2R1_FB20_Msk (0x1UL << CAN_F2R1_FB20_Pos)

#define	CAN_F2R1_FB20 CAN_F2R1_FB20_Msk

#define	CAN_F2R1_FB21_Pos (21U)

#define	CAN_F2R1_FB21_Msk (0x1UL << CAN_F2R1_FB21_Pos)

#define	CAN_F2R1_FB21 CAN_F2R1_FB21_Msk

#define	CAN_F2R1_FB22_Pos (22U)

#define	CAN_F2R1_FB22_Msk (0x1UL << CAN_F2R1_FB22_Pos)

#define	CAN_F2R1_FB22 CAN_F2R1_FB22_Msk

#define	CAN_F2R1_FB23_Pos (23U)

#define	CAN_F2R1_FB23_Msk (0x1UL << CAN_F2R1_FB23_Pos)

#define	CAN_F2R1_FB23 CAN_F2R1_FB23_Msk

#define	CAN_F2R1_FB24_Pos (24U)

#define	CAN_F2R1_FB24_Msk (0x1UL << CAN_F2R1_FB24_Pos)

#define	CAN_F2R1_FB24 CAN_F2R1_FB24_Msk

#define	CAN_F2R1_FB25_Pos (25U)

#define	CAN_F2R1_FB25_Msk (0x1UL << CAN_F2R1_FB25_Pos)

#define	CAN_F2R1_FB25 CAN_F2R1_FB25_Msk

#define	CAN_F2R1_FB26_Pos (26U)

#define	CAN_F2R1_FB26_Msk (0x1UL << CAN_F2R1_FB26_Pos)

#define	CAN_F2R1_FB26 CAN_F2R1_FB26_Msk

#define	CAN_F2R1_FB27_Pos (27U)

#define	CAN_F2R1_FB27_Msk (0x1UL << CAN_F2R1_FB27_Pos)

#define	CAN_F2R1_FB27 CAN_F2R1_FB27_Msk

#define	CAN_F2R1_FB28_Pos (28U)

#define	CAN_F2R1_FB28_Msk (0x1UL << CAN_F2R1_FB28_Pos)

#define	CAN_F2R1_FB28 CAN_F2R1_FB28_Msk

#define	CAN_F2R1_FB29_Pos (29U)

#define	CAN_F2R1_FB29_Msk (0x1UL << CAN_F2R1_FB29_Pos)

#define	CAN_F2R1_FB29 CAN_F2R1_FB29_Msk

#define	CAN_F2R1_FB30_Pos (30U)

#define	CAN_F2R1_FB30_Msk (0x1UL << CAN_F2R1_FB30_Pos)

#define	CAN_F2R1_FB30 CAN_F2R1_FB30_Msk

#define	CAN_F2R1_FB31_Pos (31U)

#define	CAN_F2R1_FB31_Msk (0x1UL << CAN_F2R1_FB31_Pos)

#define	CAN_F2R1_FB31 CAN_F2R1_FB31_Msk

#define	CAN_F3R1_FB0_Pos (0U)

#define	CAN_F3R1_FB0_Msk (0x1UL << CAN_F3R1_FB0_Pos)

#define	CAN_F3R1_FB0 CAN_F3R1_FB0_Msk

#define	CAN_F3R1_FB1_Pos (1U)

#define	CAN_F3R1_FB1_Msk (0x1UL << CAN_F3R1_FB1_Pos)

#define	CAN_F3R1_FB1 CAN_F3R1_FB1_Msk

#define	CAN_F3R1_FB2_Pos (2U)

#define	CAN_F3R1_FB2_Msk (0x1UL << CAN_F3R1_FB2_Pos)

#define	CAN_F3R1_FB2 CAN_F3R1_FB2_Msk

#define	CAN_F3R1_FB3_Pos (3U)

#define	CAN_F3R1_FB3_Msk (0x1UL << CAN_F3R1_FB3_Pos)

#define	CAN_F3R1_FB3 CAN_F3R1_FB3_Msk

#define	CAN_F3R1_FB4_Pos (4U)

#define	CAN_F3R1_FB4_Msk (0x1UL << CAN_F3R1_FB4_Pos)

#define	CAN_F3R1_FB4 CAN_F3R1_FB4_Msk

#define	CAN_F3R1_FB5_Pos (5U)

#define	CAN_F3R1_FB5_Msk (0x1UL << CAN_F3R1_FB5_Pos)

#define	CAN_F3R1_FB5 CAN_F3R1_FB5_Msk

#define	CAN_F3R1_FB6_Pos (6U)

#define	CAN_F3R1_FB6_Msk (0x1UL << CAN_F3R1_FB6_Pos)

#define	CAN_F3R1_FB6 CAN_F3R1_FB6_Msk

#define	CAN_F3R1_FB7_Pos (7U)

#define	CAN_F3R1_FB7_Msk (0x1UL << CAN_F3R1_FB7_Pos)

#define	CAN_F3R1_FB7 CAN_F3R1_FB7_Msk

#define	CAN_F3R1_FB8_Pos (8U)

#define	CAN_F3R1_FB8_Msk (0x1UL << CAN_F3R1_FB8_Pos)

#define	CAN_F3R1_FB8 CAN_F3R1_FB8_Msk

#define	CAN_F3R1_FB9_Pos (9U)

#define	CAN_F3R1_FB9_Msk (0x1UL << CAN_F3R1_FB9_Pos)

#define	CAN_F3R1_FB9 CAN_F3R1_FB9_Msk

#define	CAN_F3R1_FB10_Pos (10U)

#define	CAN_F3R1_FB10_Msk (0x1UL << CAN_F3R1_FB10_Pos)

#define	CAN_F3R1_FB10 CAN_F3R1_FB10_Msk

#define	CAN_F3R1_FB11_Pos (11U)

#define	CAN_F3R1_FB11_Msk (0x1UL << CAN_F3R1_FB11_Pos)

#define	CAN_F3R1_FB11 CAN_F3R1_FB11_Msk

#define	CAN_F3R1_FB12_Pos (12U)

#define	CAN_F3R1_FB12_Msk (0x1UL << CAN_F3R1_FB12_Pos)

#define	CAN_F3R1_FB12 CAN_F3R1_FB12_Msk

#define	CAN_F3R1_FB13_Pos (13U)

#define	CAN_F3R1_FB13_Msk (0x1UL << CAN_F3R1_FB13_Pos)

#define	CAN_F3R1_FB13 CAN_F3R1_FB13_Msk

#define	CAN_F3R1_FB14_Pos (14U)

#define	CAN_F3R1_FB14_Msk (0x1UL << CAN_F3R1_FB14_Pos)

#define	CAN_F3R1_FB14 CAN_F3R1_FB14_Msk

#define	CAN_F3R1_FB15_Pos (15U)

#define	CAN_F3R1_FB15_Msk (0x1UL << CAN_F3R1_FB15_Pos)

#define	CAN_F3R1_FB15 CAN_F3R1_FB15_Msk

#define	CAN_F3R1_FB16_Pos (16U)

#define	CAN_F3R1_FB16_Msk (0x1UL << CAN_F3R1_FB16_Pos)

#define	CAN_F3R1_FB16 CAN_F3R1_FB16_Msk

#define	CAN_F3R1_FB17_Pos (17U)

#define	CAN_F3R1_FB17_Msk (0x1UL << CAN_F3R1_FB17_Pos)

#define	CAN_F3R1_FB17 CAN_F3R1_FB17_Msk

#define	CAN_F3R1_FB18_Pos (18U)

#define	CAN_F3R1_FB18_Msk (0x1UL << CAN_F3R1_FB18_Pos)

#define	CAN_F3R1_FB18 CAN_F3R1_FB18_Msk

#define	CAN_F3R1_FB19_Pos (19U)

#define	CAN_F3R1_FB19_Msk (0x1UL << CAN_F3R1_FB19_Pos)

#define	CAN_F3R1_FB19 CAN_F3R1_FB19_Msk

#define	CAN_F3R1_FB20_Pos (20U)

#define	CAN_F3R1_FB20_Msk (0x1UL << CAN_F3R1_FB20_Pos)

#define	CAN_F3R1_FB20 CAN_F3R1_FB20_Msk

#define	CAN_F3R1_FB21_Pos (21U)

#define	CAN_F3R1_FB21_Msk (0x1UL << CAN_F3R1_FB21_Pos)

#define	CAN_F3R1_FB21 CAN_F3R1_FB21_Msk

#define	CAN_F3R1_FB22_Pos (22U)

#define	CAN_F3R1_FB22_Msk (0x1UL << CAN_F3R1_FB22_Pos)

#define	CAN_F3R1_FB22 CAN_F3R1_FB22_Msk

#define	CAN_F3R1_FB23_Pos (23U)

#define	CAN_F3R1_FB23_Msk (0x1UL << CAN_F3R1_FB23_Pos)

#define	CAN_F3R1_FB23 CAN_F3R1_FB23_Msk

#define	CAN_F3R1_FB24_Pos (24U)

#define	CAN_F3R1_FB24_Msk (0x1UL << CAN_F3R1_FB24_Pos)

#define	CAN_F3R1_FB24 CAN_F3R1_FB24_Msk

#define	CAN_F3R1_FB25_Pos (25U)

#define	CAN_F3R1_FB25_Msk (0x1UL << CAN_F3R1_FB25_Pos)

#define	CAN_F3R1_FB25 CAN_F3R1_FB25_Msk

#define	CAN_F3R1_FB26_Pos (26U)

#define	CAN_F3R1_FB26_Msk (0x1UL << CAN_F3R1_FB26_Pos)

#define	CAN_F3R1_FB26 CAN_F3R1_FB26_Msk

#define	CAN_F3R1_FB27_Pos (27U)

#define	CAN_F3R1_FB27_Msk (0x1UL << CAN_F3R1_FB27_Pos)

#define	CAN_F3R1_FB27 CAN_F3R1_FB27_Msk

#define	CAN_F3R1_FB28_Pos (28U)

#define	CAN_F3R1_FB28_Msk (0x1UL << CAN_F3R1_FB28_Pos)

#define	CAN_F3R1_FB28 CAN_F3R1_FB28_Msk

#define	CAN_F3R1_FB29_Pos (29U)

#define	CAN_F3R1_FB29_Msk (0x1UL << CAN_F3R1_FB29_Pos)

#define	CAN_F3R1_FB29 CAN_F3R1_FB29_Msk

#define	CAN_F3R1_FB30_Pos (30U)

#define	CAN_F3R1_FB30_Msk (0x1UL << CAN_F3R1_FB30_Pos)

#define	CAN_F3R1_FB30 CAN_F3R1_FB30_Msk

#define	CAN_F3R1_FB31_Pos (31U)

#define	CAN_F3R1_FB31_Msk (0x1UL << CAN_F3R1_FB31_Pos)

#define	CAN_F3R1_FB31 CAN_F3R1_FB31_Msk

#define	CAN_F4R1_FB0_Pos (0U)

#define	CAN_F4R1_FB0_Msk (0x1UL << CAN_F4R1_FB0_Pos)

#define	CAN_F4R1_FB0 CAN_F4R1_FB0_Msk

#define	CAN_F4R1_FB1_Pos (1U)

#define	CAN_F4R1_FB1_Msk (0x1UL << CAN_F4R1_FB1_Pos)

#define	CAN_F4R1_FB1 CAN_F4R1_FB1_Msk

#define	CAN_F4R1_FB2_Pos (2U)

#define	CAN_F4R1_FB2_Msk (0x1UL << CAN_F4R1_FB2_Pos)

#define	CAN_F4R1_FB2 CAN_F4R1_FB2_Msk

#define	CAN_F4R1_FB3_Pos (3U)

#define	CAN_F4R1_FB3_Msk (0x1UL << CAN_F4R1_FB3_Pos)

#define	CAN_F4R1_FB3 CAN_F4R1_FB3_Msk

#define	CAN_F4R1_FB4_Pos (4U)

#define	CAN_F4R1_FB4_Msk (0x1UL << CAN_F4R1_FB4_Pos)

#define	CAN_F4R1_FB4 CAN_F4R1_FB4_Msk

#define	CAN_F4R1_FB5_Pos (5U)

#define	CAN_F4R1_FB5_Msk (0x1UL << CAN_F4R1_FB5_Pos)

#define	CAN_F4R1_FB5 CAN_F4R1_FB5_Msk

#define	CAN_F4R1_FB6_Pos (6U)

#define	CAN_F4R1_FB6_Msk (0x1UL << CAN_F4R1_FB6_Pos)

#define	CAN_F4R1_FB6 CAN_F4R1_FB6_Msk

#define	CAN_F4R1_FB7_Pos (7U)

#define	CAN_F4R1_FB7_Msk (0x1UL << CAN_F4R1_FB7_Pos)

#define	CAN_F4R1_FB7 CAN_F4R1_FB7_Msk

#define	CAN_F4R1_FB8_Pos (8U)

#define	CAN_F4R1_FB8_Msk (0x1UL << CAN_F4R1_FB8_Pos)

#define	CAN_F4R1_FB8 CAN_F4R1_FB8_Msk

#define	CAN_F4R1_FB9_Pos (9U)

#define	CAN_F4R1_FB9_Msk (0x1UL << CAN_F4R1_FB9_Pos)

#define	CAN_F4R1_FB9 CAN_F4R1_FB9_Msk

#define	CAN_F4R1_FB10_Pos (10U)

#define	CAN_F4R1_FB10_Msk (0x1UL << CAN_F4R1_FB10_Pos)

#define	CAN_F4R1_FB10 CAN_F4R1_FB10_Msk

#define	CAN_F4R1_FB11_Pos (11U)

#define	CAN_F4R1_FB11_Msk (0x1UL << CAN_F4R1_FB11_Pos)

#define	CAN_F4R1_FB11 CAN_F4R1_FB11_Msk

#define	CAN_F4R1_FB12_Pos (12U)

#define	CAN_F4R1_FB12_Msk (0x1UL << CAN_F4R1_FB12_Pos)

#define	CAN_F4R1_FB12 CAN_F4R1_FB12_Msk

#define	CAN_F4R1_FB13_Pos (13U)

#define	CAN_F4R1_FB13_Msk (0x1UL << CAN_F4R1_FB13_Pos)

#define	CAN_F4R1_FB13 CAN_F4R1_FB13_Msk

#define	CAN_F4R1_FB14_Pos (14U)

#define	CAN_F4R1_FB14_Msk (0x1UL << CAN_F4R1_FB14_Pos)

#define	CAN_F4R1_FB14 CAN_F4R1_FB14_Msk

#define	CAN_F4R1_FB15_Pos (15U)

#define	CAN_F4R1_FB15_Msk (0x1UL << CAN_F4R1_FB15_Pos)

#define	CAN_F4R1_FB15 CAN_F4R1_FB15_Msk

#define	CAN_F4R1_FB16_Pos (16U)

#define	CAN_F4R1_FB16_Msk (0x1UL << CAN_F4R1_FB16_Pos)

#define	CAN_F4R1_FB16 CAN_F4R1_FB16_Msk

#define	CAN_F4R1_FB17_Pos (17U)

#define	CAN_F4R1_FB17_Msk (0x1UL << CAN_F4R1_FB17_Pos)

#define	CAN_F4R1_FB17 CAN_F4R1_FB17_Msk

#define	CAN_F4R1_FB18_Pos (18U)

#define	CAN_F4R1_FB18_Msk (0x1UL << CAN_F4R1_FB18_Pos)

#define	CAN_F4R1_FB18 CAN_F4R1_FB18_Msk

#define	CAN_F4R1_FB19_Pos (19U)

#define	CAN_F4R1_FB19_Msk (0x1UL << CAN_F4R1_FB19_Pos)

#define	CAN_F4R1_FB19 CAN_F4R1_FB19_Msk

#define	CAN_F4R1_FB20_Pos (20U)

#define	CAN_F4R1_FB20_Msk (0x1UL << CAN_F4R1_FB20_Pos)

#define	CAN_F4R1_FB20 CAN_F4R1_FB20_Msk

#define	CAN_F4R1_FB21_Pos (21U)

#define	CAN_F4R1_FB21_Msk (0x1UL << CAN_F4R1_FB21_Pos)

#define	CAN_F4R1_FB21 CAN_F4R1_FB21_Msk

#define	CAN_F4R1_FB22_Pos (22U)

#define	CAN_F4R1_FB22_Msk (0x1UL << CAN_F4R1_FB22_Pos)

#define	CAN_F4R1_FB22 CAN_F4R1_FB22_Msk

#define	CAN_F4R1_FB23_Pos (23U)

#define	CAN_F4R1_FB23_Msk (0x1UL << CAN_F4R1_FB23_Pos)

#define	CAN_F4R1_FB23 CAN_F4R1_FB23_Msk

#define	CAN_F4R1_FB24_Pos (24U)

#define	CAN_F4R1_FB24_Msk (0x1UL << CAN_F4R1_FB24_Pos)

#define	CAN_F4R1_FB24 CAN_F4R1_FB24_Msk

#define	CAN_F4R1_FB25_Pos (25U)

#define	CAN_F4R1_FB25_Msk (0x1UL << CAN_F4R1_FB25_Pos)

#define	CAN_F4R1_FB25 CAN_F4R1_FB25_Msk

#define	CAN_F4R1_FB26_Pos (26U)

#define	CAN_F4R1_FB26_Msk (0x1UL << CAN_F4R1_FB26_Pos)

#define	CAN_F4R1_FB26 CAN_F4R1_FB26_Msk

#define	CAN_F4R1_FB27_Pos (27U)

#define	CAN_F4R1_FB27_Msk (0x1UL << CAN_F4R1_FB27_Pos)

#define	CAN_F4R1_FB27 CAN_F4R1_FB27_Msk

#define	CAN_F4R1_FB28_Pos (28U)

#define	CAN_F4R1_FB28_Msk (0x1UL << CAN_F4R1_FB28_Pos)

#define	CAN_F4R1_FB28 CAN_F4R1_FB28_Msk

#define	CAN_F4R1_FB29_Pos (29U)

#define	CAN_F4R1_FB29_Msk (0x1UL << CAN_F4R1_FB29_Pos)

#define	CAN_F4R1_FB29 CAN_F4R1_FB29_Msk

#define	CAN_F4R1_FB30_Pos (30U)

#define	CAN_F4R1_FB30_Msk (0x1UL << CAN_F4R1_FB30_Pos)

#define	CAN_F4R1_FB30 CAN_F4R1_FB30_Msk

#define	CAN_F4R1_FB31_Pos (31U)

#define	CAN_F4R1_FB31_Msk (0x1UL << CAN_F4R1_FB31_Pos)

#define	CAN_F4R1_FB31 CAN_F4R1_FB31_Msk

#define	CAN_F5R1_FB0_Pos (0U)

#define	CAN_F5R1_FB0_Msk (0x1UL << CAN_F5R1_FB0_Pos)

#define	CAN_F5R1_FB0 CAN_F5R1_FB0_Msk

#define	CAN_F5R1_FB1_Pos (1U)

#define	CAN_F5R1_FB1_Msk (0x1UL << CAN_F5R1_FB1_Pos)

#define	CAN_F5R1_FB1 CAN_F5R1_FB1_Msk

#define	CAN_F5R1_FB2_Pos (2U)

#define	CAN_F5R1_FB2_Msk (0x1UL << CAN_F5R1_FB2_Pos)

#define	CAN_F5R1_FB2 CAN_F5R1_FB2_Msk

#define	CAN_F5R1_FB3_Pos (3U)

#define	CAN_F5R1_FB3_Msk (0x1UL << CAN_F5R1_FB3_Pos)

#define	CAN_F5R1_FB3 CAN_F5R1_FB3_Msk

#define	CAN_F5R1_FB4_Pos (4U)

#define	CAN_F5R1_FB4_Msk (0x1UL << CAN_F5R1_FB4_Pos)

#define	CAN_F5R1_FB4 CAN_F5R1_FB4_Msk

#define	CAN_F5R1_FB5_Pos (5U)

#define	CAN_F5R1_FB5_Msk (0x1UL << CAN_F5R1_FB5_Pos)

#define	CAN_F5R1_FB5 CAN_F5R1_FB5_Msk

#define	CAN_F5R1_FB6_Pos (6U)

#define	CAN_F5R1_FB6_Msk (0x1UL << CAN_F5R1_FB6_Pos)

#define	CAN_F5R1_FB6 CAN_F5R1_FB6_Msk

#define	CAN_F5R1_FB7_Pos (7U)

#define	CAN_F5R1_FB7_Msk (0x1UL << CAN_F5R1_FB7_Pos)

#define	CAN_F5R1_FB7 CAN_F5R1_FB7_Msk

#define	CAN_F5R1_FB8_Pos (8U)

#define	CAN_F5R1_FB8_Msk (0x1UL << CAN_F5R1_FB8_Pos)

#define	CAN_F5R1_FB8 CAN_F5R1_FB8_Msk

#define	CAN_F5R1_FB9_Pos (9U)

#define	CAN_F5R1_FB9_Msk (0x1UL << CAN_F5R1_FB9_Pos)

#define	CAN_F5R1_FB9 CAN_F5R1_FB9_Msk

#define	CAN_F5R1_FB10_Pos (10U)

#define	CAN_F5R1_FB10_Msk (0x1UL << CAN_F5R1_FB10_Pos)

#define	CAN_F5R1_FB10 CAN_F5R1_FB10_Msk

#define	CAN_F5R1_FB11_Pos (11U)

#define	CAN_F5R1_FB11_Msk (0x1UL << CAN_F5R1_FB11_Pos)

#define	CAN_F5R1_FB11 CAN_F5R1_FB11_Msk

#define	CAN_F5R1_FB12_Pos (12U)

#define	CAN_F5R1_FB12_Msk (0x1UL << CAN_F5R1_FB12_Pos)

#define	CAN_F5R1_FB12 CAN_F5R1_FB12_Msk

#define	CAN_F5R1_FB13_Pos (13U)

#define	CAN_F5R1_FB13_Msk (0x1UL << CAN_F5R1_FB13_Pos)

#define	CAN_F5R1_FB13 CAN_F5R1_FB13_Msk

#define	CAN_F5R1_FB14_Pos (14U)

#define	CAN_F5R1_FB14_Msk (0x1UL << CAN_F5R1_FB14_Pos)

#define	CAN_F5R1_FB14 CAN_F5R1_FB14_Msk

#define	CAN_F5R1_FB15_Pos (15U)

#define	CAN_F5R1_FB15_Msk (0x1UL << CAN_F5R1_FB15_Pos)

#define	CAN_F5R1_FB15 CAN_F5R1_FB15_Msk

#define	CAN_F5R1_FB16_Pos (16U)

#define	CAN_F5R1_FB16_Msk (0x1UL << CAN_F5R1_FB16_Pos)

#define	CAN_F5R1_FB16 CAN_F5R1_FB16_Msk

#define	CAN_F5R1_FB17_Pos (17U)

#define	CAN_F5R1_FB17_Msk (0x1UL << CAN_F5R1_FB17_Pos)

#define	CAN_F5R1_FB17 CAN_F5R1_FB17_Msk

#define	CAN_F5R1_FB18_Pos (18U)

#define	CAN_F5R1_FB18_Msk (0x1UL << CAN_F5R1_FB18_Pos)

#define	CAN_F5R1_FB18 CAN_F5R1_FB18_Msk

#define	CAN_F5R1_FB19_Pos (19U)

#define	CAN_F5R1_FB19_Msk (0x1UL << CAN_F5R1_FB19_Pos)

#define	CAN_F5R1_FB19 CAN_F5R1_FB19_Msk

#define	CAN_F5R1_FB20_Pos (20U)

#define	CAN_F5R1_FB20_Msk (0x1UL << CAN_F5R1_FB20_Pos)

#define	CAN_F5R1_FB20 CAN_F5R1_FB20_Msk

#define	CAN_F5R1_FB21_Pos (21U)

#define	CAN_F5R1_FB21_Msk (0x1UL << CAN_F5R1_FB21_Pos)

#define	CAN_F5R1_FB21 CAN_F5R1_FB21_Msk

#define	CAN_F5R1_FB22_Pos (22U)

#define	CAN_F5R1_FB22_Msk (0x1UL << CAN_F5R1_FB22_Pos)

#define	CAN_F5R1_FB22 CAN_F5R1_FB22_Msk

#define	CAN_F5R1_FB23_Pos (23U)

#define	CAN_F5R1_FB23_Msk (0x1UL << CAN_F5R1_FB23_Pos)

#define	CAN_F5R1_FB23 CAN_F5R1_FB23_Msk

#define	CAN_F5R1_FB24_Pos (24U)

#define	CAN_F5R1_FB24_Msk (0x1UL << CAN_F5R1_FB24_Pos)

#define	CAN_F5R1_FB24 CAN_F5R1_FB24_Msk

#define	CAN_F5R1_FB25_Pos (25U)

#define	CAN_F5R1_FB25_Msk (0x1UL << CAN_F5R1_FB25_Pos)

#define	CAN_F5R1_FB25 CAN_F5R1_FB25_Msk

#define	CAN_F5R1_FB26_Pos (26U)

#define	CAN_F5R1_FB26_Msk (0x1UL << CAN_F5R1_FB26_Pos)

#define	CAN_F5R1_FB26 CAN_F5R1_FB26_Msk

#define	CAN_F5R1_FB27_Pos (27U)

#define	CAN_F5R1_FB27_Msk (0x1UL << CAN_F5R1_FB27_Pos)

#define	CAN_F5R1_FB27 CAN_F5R1_FB27_Msk

#define	CAN_F5R1_FB28_Pos (28U)

#define	CAN_F5R1_FB28_Msk (0x1UL << CAN_F5R1_FB28_Pos)

#define	CAN_F5R1_FB28 CAN_F5R1_FB28_Msk

#define	CAN_F5R1_FB29_Pos (29U)

#define	CAN_F5R1_FB29_Msk (0x1UL << CAN_F5R1_FB29_Pos)

#define	CAN_F5R1_FB29 CAN_F5R1_FB29_Msk

#define	CAN_F5R1_FB30_Pos (30U)

#define	CAN_F5R1_FB30_Msk (0x1UL << CAN_F5R1_FB30_Pos)

#define	CAN_F5R1_FB30 CAN_F5R1_FB30_Msk

#define	CAN_F5R1_FB31_Pos (31U)

#define	CAN_F5R1_FB31_Msk (0x1UL << CAN_F5R1_FB31_Pos)

#define	CAN_F5R1_FB31 CAN_F5R1_FB31_Msk

#define	CAN_F6R1_FB0_Pos (0U)

#define	CAN_F6R1_FB0_Msk (0x1UL << CAN_F6R1_FB0_Pos)

#define	CAN_F6R1_FB0 CAN_F6R1_FB0_Msk

#define	CAN_F6R1_FB1_Pos (1U)

#define	CAN_F6R1_FB1_Msk (0x1UL << CAN_F6R1_FB1_Pos)

#define	CAN_F6R1_FB1 CAN_F6R1_FB1_Msk

#define	CAN_F6R1_FB2_Pos (2U)

#define	CAN_F6R1_FB2_Msk (0x1UL << CAN_F6R1_FB2_Pos)

#define	CAN_F6R1_FB2 CAN_F6R1_FB2_Msk

#define	CAN_F6R1_FB3_Pos (3U)

#define	CAN_F6R1_FB3_Msk (0x1UL << CAN_F6R1_FB3_Pos)

#define	CAN_F6R1_FB3 CAN_F6R1_FB3_Msk

#define	CAN_F6R1_FB4_Pos (4U)

#define	CAN_F6R1_FB4_Msk (0x1UL << CAN_F6R1_FB4_Pos)

#define	CAN_F6R1_FB4 CAN_F6R1_FB4_Msk

#define	CAN_F6R1_FB5_Pos (5U)

#define	CAN_F6R1_FB5_Msk (0x1UL << CAN_F6R1_FB5_Pos)

#define	CAN_F6R1_FB5 CAN_F6R1_FB5_Msk

#define	CAN_F6R1_FB6_Pos (6U)

#define	CAN_F6R1_FB6_Msk (0x1UL << CAN_F6R1_FB6_Pos)

#define	CAN_F6R1_FB6 CAN_F6R1_FB6_Msk

#define	CAN_F6R1_FB7_Pos (7U)

#define	CAN_F6R1_FB7_Msk (0x1UL << CAN_F6R1_FB7_Pos)

#define	CAN_F6R1_FB7 CAN_F6R1_FB7_Msk

#define	CAN_F6R1_FB8_Pos (8U)

#define	CAN_F6R1_FB8_Msk (0x1UL << CAN_F6R1_FB8_Pos)

#define	CAN_F6R1_FB8 CAN_F6R1_FB8_Msk

#define	CAN_F6R1_FB9_Pos (9U)

#define	CAN_F6R1_FB9_Msk (0x1UL << CAN_F6R1_FB9_Pos)

#define	CAN_F6R1_FB9 CAN_F6R1_FB9_Msk

#define	CAN_F6R1_FB10_Pos (10U)

#define	CAN_F6R1_FB10_Msk (0x1UL << CAN_F6R1_FB10_Pos)

#define	CAN_F6R1_FB10 CAN_F6R1_FB10_Msk

#define	CAN_F6R1_FB11_Pos (11U)

#define	CAN_F6R1_FB11_Msk (0x1UL << CAN_F6R1_FB11_Pos)

#define	CAN_F6R1_FB11 CAN_F6R1_FB11_Msk

#define	CAN_F6R1_FB12_Pos (12U)

#define	CAN_F6R1_FB12_Msk (0x1UL << CAN_F6R1_FB12_Pos)

#define	CAN_F6R1_FB12 CAN_F6R1_FB12_Msk

#define	CAN_F6R1_FB13_Pos (13U)

#define	CAN_F6R1_FB13_Msk (0x1UL << CAN_F6R1_FB13_Pos)

#define	CAN_F6R1_FB13 CAN_F6R1_FB13_Msk

#define	CAN_F6R1_FB14_Pos (14U)

#define	CAN_F6R1_FB14_Msk (0x1UL << CAN_F6R1_FB14_Pos)

#define	CAN_F6R1_FB14 CAN_F6R1_FB14_Msk

#define	CAN_F6R1_FB15_Pos (15U)

#define	CAN_F6R1_FB15_Msk (0x1UL << CAN_F6R1_FB15_Pos)

#define	CAN_F6R1_FB15 CAN_F6R1_FB15_Msk

#define	CAN_F6R1_FB16_Pos (16U)

#define	CAN_F6R1_FB16_Msk (0x1UL << CAN_F6R1_FB16_Pos)

#define	CAN_F6R1_FB16 CAN_F6R1_FB16_Msk

#define	CAN_F6R1_FB17_Pos (17U)

#define	CAN_F6R1_FB17_Msk (0x1UL << CAN_F6R1_FB17_Pos)

#define	CAN_F6R1_FB17 CAN_F6R1_FB17_Msk

#define	CAN_F6R1_FB18_Pos (18U)

#define	CAN_F6R1_FB18_Msk (0x1UL << CAN_F6R1_FB18_Pos)

#define	CAN_F6R1_FB18 CAN_F6R1_FB18_Msk

#define	CAN_F6R1_FB19_Pos (19U)

#define	CAN_F6R1_FB19_Msk (0x1UL << CAN_F6R1_FB19_Pos)

#define	CAN_F6R1_FB19 CAN_F6R1_FB19_Msk

#define	CAN_F6R1_FB20_Pos (20U)

#define	CAN_F6R1_FB20_Msk (0x1UL << CAN_F6R1_FB20_Pos)

#define	CAN_F6R1_FB20 CAN_F6R1_FB20_Msk

#define	CAN_F6R1_FB21_Pos (21U)

#define	CAN_F6R1_FB21_Msk (0x1UL << CAN_F6R1_FB21_Pos)

#define	CAN_F6R1_FB21 CAN_F6R1_FB21_Msk

#define	CAN_F6R1_FB22_Pos (22U)

#define	CAN_F6R1_FB22_Msk (0x1UL << CAN_F6R1_FB22_Pos)

#define	CAN_F6R1_FB22 CAN_F6R1_FB22_Msk

#define	CAN_F6R1_FB23_Pos (23U)

#define	CAN_F6R1_FB23_Msk (0x1UL << CAN_F6R1_FB23_Pos)

#define	CAN_F6R1_FB23 CAN_F6R1_FB23_Msk

#define	CAN_F6R1_FB24_Pos (24U)

#define	CAN_F6R1_FB24_Msk (0x1UL << CAN_F6R1_FB24_Pos)

#define	CAN_F6R1_FB24 CAN_F6R1_FB24_Msk

#define	CAN_F6R1_FB25_Pos (25U)

#define	CAN_F6R1_FB25_Msk (0x1UL << CAN_F6R1_FB25_Pos)

#define	CAN_F6R1_FB25 CAN_F6R1_FB25_Msk

#define	CAN_F6R1_FB26_Pos (26U)

#define	CAN_F6R1_FB26_Msk (0x1UL << CAN_F6R1_FB26_Pos)

#define	CAN_F6R1_FB26 CAN_F6R1_FB26_Msk

#define	CAN_F6R1_FB27_Pos (27U)

#define	CAN_F6R1_FB27_Msk (0x1UL << CAN_F6R1_FB27_Pos)

#define	CAN_F6R1_FB27 CAN_F6R1_FB27_Msk

#define	CAN_F6R1_FB28_Pos (28U)

#define	CAN_F6R1_FB28_Msk (0x1UL << CAN_F6R1_FB28_Pos)

#define	CAN_F6R1_FB28 CAN_F6R1_FB28_Msk

#define	CAN_F6R1_FB29_Pos (29U)

#define	CAN_F6R1_FB29_Msk (0x1UL << CAN_F6R1_FB29_Pos)

#define	CAN_F6R1_FB29 CAN_F6R1_FB29_Msk

#define	CAN_F6R1_FB30_Pos (30U)

#define	CAN_F6R1_FB30_Msk (0x1UL << CAN_F6R1_FB30_Pos)

#define	CAN_F6R1_FB30 CAN_F6R1_FB30_Msk

#define	CAN_F6R1_FB31_Pos (31U)

#define	CAN_F6R1_FB31_Msk (0x1UL << CAN_F6R1_FB31_Pos)

#define	CAN_F6R1_FB31 CAN_F6R1_FB31_Msk

#define	CAN_F7R1_FB0_Pos (0U)

#define	CAN_F7R1_FB0_Msk (0x1UL << CAN_F7R1_FB0_Pos)

#define	CAN_F7R1_FB0 CAN_F7R1_FB0_Msk

#define	CAN_F7R1_FB1_Pos (1U)

#define	CAN_F7R1_FB1_Msk (0x1UL << CAN_F7R1_FB1_Pos)

#define	CAN_F7R1_FB1 CAN_F7R1_FB1_Msk

#define	CAN_F7R1_FB2_Pos (2U)

#define	CAN_F7R1_FB2_Msk (0x1UL << CAN_F7R1_FB2_Pos)

#define	CAN_F7R1_FB2 CAN_F7R1_FB2_Msk

#define	CAN_F7R1_FB3_Pos (3U)

#define	CAN_F7R1_FB3_Msk (0x1UL << CAN_F7R1_FB3_Pos)

#define	CAN_F7R1_FB3 CAN_F7R1_FB3_Msk

#define	CAN_F7R1_FB4_Pos (4U)

#define	CAN_F7R1_FB4_Msk (0x1UL << CAN_F7R1_FB4_Pos)

#define	CAN_F7R1_FB4 CAN_F7R1_FB4_Msk

#define	CAN_F7R1_FB5_Pos (5U)

#define	CAN_F7R1_FB5_Msk (0x1UL << CAN_F7R1_FB5_Pos)

#define	CAN_F7R1_FB5 CAN_F7R1_FB5_Msk

#define	CAN_F7R1_FB6_Pos (6U)

#define	CAN_F7R1_FB6_Msk (0x1UL << CAN_F7R1_FB6_Pos)

#define	CAN_F7R1_FB6 CAN_F7R1_FB6_Msk

#define	CAN_F7R1_FB7_Pos (7U)

#define	CAN_F7R1_FB7_Msk (0x1UL << CAN_F7R1_FB7_Pos)

#define	CAN_F7R1_FB7 CAN_F7R1_FB7_Msk

#define	CAN_F7R1_FB8_Pos (8U)

#define	CAN_F7R1_FB8_Msk (0x1UL << CAN_F7R1_FB8_Pos)

#define	CAN_F7R1_FB8 CAN_F7R1_FB8_Msk

#define	CAN_F7R1_FB9_Pos (9U)

#define	CAN_F7R1_FB9_Msk (0x1UL << CAN_F7R1_FB9_Pos)

#define	CAN_F7R1_FB9 CAN_F7R1_FB9_Msk

#define	CAN_F7R1_FB10_Pos (10U)

#define	CAN_F7R1_FB10_Msk (0x1UL << CAN_F7R1_FB10_Pos)

#define	CAN_F7R1_FB10 CAN_F7R1_FB10_Msk

#define	CAN_F7R1_FB11_Pos (11U)

#define	CAN_F7R1_FB11_Msk (0x1UL << CAN_F7R1_FB11_Pos)

#define	CAN_F7R1_FB11 CAN_F7R1_FB11_Msk

#define	CAN_F7R1_FB12_Pos (12U)

#define	CAN_F7R1_FB12_Msk (0x1UL << CAN_F7R1_FB12_Pos)

#define	CAN_F7R1_FB12 CAN_F7R1_FB12_Msk

#define	CAN_F7R1_FB13_Pos (13U)

#define	CAN_F7R1_FB13_Msk (0x1UL << CAN_F7R1_FB13_Pos)

#define	CAN_F7R1_FB13 CAN_F7R1_FB13_Msk

#define	CAN_F7R1_FB14_Pos (14U)

#define	CAN_F7R1_FB14_Msk (0x1UL << CAN_F7R1_FB14_Pos)

#define	CAN_F7R1_FB14 CAN_F7R1_FB14_Msk

#define	CAN_F7R1_FB15_Pos (15U)

#define	CAN_F7R1_FB15_Msk (0x1UL << CAN_F7R1_FB15_Pos)

#define	CAN_F7R1_FB15 CAN_F7R1_FB15_Msk

#define	CAN_F7R1_FB16_Pos (16U)

#define	CAN_F7R1_FB16_Msk (0x1UL << CAN_F7R1_FB16_Pos)

#define	CAN_F7R1_FB16 CAN_F7R1_FB16_Msk

#define	CAN_F7R1_FB17_Pos (17U)

#define	CAN_F7R1_FB17_Msk (0x1UL << CAN_F7R1_FB17_Pos)

#define	CAN_F7R1_FB17 CAN_F7R1_FB17_Msk

#define	CAN_F7R1_FB18_Pos (18U)

#define	CAN_F7R1_FB18_Msk (0x1UL << CAN_F7R1_FB18_Pos)

#define	CAN_F7R1_FB18 CAN_F7R1_FB18_Msk

#define	CAN_F7R1_FB19_Pos (19U)

#define	CAN_F7R1_FB19_Msk (0x1UL << CAN_F7R1_FB19_Pos)

#define	CAN_F7R1_FB19 CAN_F7R1_FB19_Msk

#define	CAN_F7R1_FB20_Pos (20U)

#define	CAN_F7R1_FB20_Msk (0x1UL << CAN_F7R1_FB20_Pos)

#define	CAN_F7R1_FB20 CAN_F7R1_FB20_Msk

#define	CAN_F7R1_FB21_Pos (21U)

#define	CAN_F7R1_FB21_Msk (0x1UL << CAN_F7R1_FB21_Pos)

#define	CAN_F7R1_FB21 CAN_F7R1_FB21_Msk

#define	CAN_F7R1_FB22_Pos (22U)

#define	CAN_F7R1_FB22_Msk (0x1UL << CAN_F7R1_FB22_Pos)

#define	CAN_F7R1_FB22 CAN_F7R1_FB22_Msk

#define	CAN_F7R1_FB23_Pos (23U)

#define	CAN_F7R1_FB23_Msk (0x1UL << CAN_F7R1_FB23_Pos)

#define	CAN_F7R1_FB23 CAN_F7R1_FB23_Msk

#define	CAN_F7R1_FB24_Pos (24U)

#define	CAN_F7R1_FB24_Msk (0x1UL << CAN_F7R1_FB24_Pos)

#define	CAN_F7R1_FB24 CAN_F7R1_FB24_Msk

#define	CAN_F7R1_FB25_Pos (25U)

#define	CAN_F7R1_FB25_Msk (0x1UL << CAN_F7R1_FB25_Pos)

#define	CAN_F7R1_FB25 CAN_F7R1_FB25_Msk

#define	CAN_F7R1_FB26_Pos (26U)

#define	CAN_F7R1_FB26_Msk (0x1UL << CAN_F7R1_FB26_Pos)

#define	CAN_F7R1_FB26 CAN_F7R1_FB26_Msk

#define	CAN_F7R1_FB27_Pos (27U)

#define	CAN_F7R1_FB27_Msk (0x1UL << CAN_F7R1_FB27_Pos)

#define	CAN_F7R1_FB27 CAN_F7R1_FB27_Msk

#define	CAN_F7R1_FB28_Pos (28U)

#define	CAN_F7R1_FB28_Msk (0x1UL << CAN_F7R1_FB28_Pos)

#define	CAN_F7R1_FB28 CAN_F7R1_FB28_Msk

#define	CAN_F7R1_FB29_Pos (29U)

#define	CAN_F7R1_FB29_Msk (0x1UL << CAN_F7R1_FB29_Pos)

#define	CAN_F7R1_FB29 CAN_F7R1_FB29_Msk

#define	CAN_F7R1_FB30_Pos (30U)

#define	CAN_F7R1_FB30_Msk (0x1UL << CAN_F7R1_FB30_Pos)

#define	CAN_F7R1_FB30 CAN_F7R1_FB30_Msk

#define	CAN_F7R1_FB31_Pos (31U)

#define	CAN_F7R1_FB31_Msk (0x1UL << CAN_F7R1_FB31_Pos)

#define	CAN_F7R1_FB31 CAN_F7R1_FB31_Msk

#define	CAN_F8R1_FB0_Pos (0U)

#define	CAN_F8R1_FB0_Msk (0x1UL << CAN_F8R1_FB0_Pos)

#define	CAN_F8R1_FB0 CAN_F8R1_FB0_Msk

#define	CAN_F8R1_FB1_Pos (1U)

#define	CAN_F8R1_FB1_Msk (0x1UL << CAN_F8R1_FB1_Pos)

#define	CAN_F8R1_FB1 CAN_F8R1_FB1_Msk

#define	CAN_F8R1_FB2_Pos (2U)

#define	CAN_F8R1_FB2_Msk (0x1UL << CAN_F8R1_FB2_Pos)

#define	CAN_F8R1_FB2 CAN_F8R1_FB2_Msk

#define	CAN_F8R1_FB3_Pos (3U)

#define	CAN_F8R1_FB3_Msk (0x1UL << CAN_F8R1_FB3_Pos)

#define	CAN_F8R1_FB3 CAN_F8R1_FB3_Msk

#define	CAN_F8R1_FB4_Pos (4U)

#define	CAN_F8R1_FB4_Msk (0x1UL << CAN_F8R1_FB4_Pos)

#define	CAN_F8R1_FB4 CAN_F8R1_FB4_Msk

#define	CAN_F8R1_FB5_Pos (5U)

#define	CAN_F8R1_FB5_Msk (0x1UL << CAN_F8R1_FB5_Pos)

#define	CAN_F8R1_FB5 CAN_F8R1_FB5_Msk

#define	CAN_F8R1_FB6_Pos (6U)

#define	CAN_F8R1_FB6_Msk (0x1UL << CAN_F8R1_FB6_Pos)

#define	CAN_F8R1_FB6 CAN_F8R1_FB6_Msk

#define	CAN_F8R1_FB7_Pos (7U)

#define	CAN_F8R1_FB7_Msk (0x1UL << CAN_F8R1_FB7_Pos)

#define	CAN_F8R1_FB7 CAN_F8R1_FB7_Msk

#define	CAN_F8R1_FB8_Pos (8U)

#define	CAN_F8R1_FB8_Msk (0x1UL << CAN_F8R1_FB8_Pos)

#define	CAN_F8R1_FB8 CAN_F8R1_FB8_Msk

#define	CAN_F8R1_FB9_Pos (9U)

#define	CAN_F8R1_FB9_Msk (0x1UL << CAN_F8R1_FB9_Pos)

#define	CAN_F8R1_FB9 CAN_F8R1_FB9_Msk

#define	CAN_F8R1_FB10_Pos (10U)

#define	CAN_F8R1_FB10_Msk (0x1UL << CAN_F8R1_FB10_Pos)

#define	CAN_F8R1_FB10 CAN_F8R1_FB10_Msk

#define	CAN_F8R1_FB11_Pos (11U)

#define	CAN_F8R1_FB11_Msk (0x1UL << CAN_F8R1_FB11_Pos)

#define	CAN_F8R1_FB11 CAN_F8R1_FB11_Msk

#define	CAN_F8R1_FB12_Pos (12U)

#define	CAN_F8R1_FB12_Msk (0x1UL << CAN_F8R1_FB12_Pos)

#define	CAN_F8R1_FB12 CAN_F8R1_FB12_Msk

#define	CAN_F8R1_FB13_Pos (13U)

#define	CAN_F8R1_FB13_Msk (0x1UL << CAN_F8R1_FB13_Pos)

#define	CAN_F8R1_FB13 CAN_F8R1_FB13_Msk

#define	CAN_F8R1_FB14_Pos (14U)

#define	CAN_F8R1_FB14_Msk (0x1UL << CAN_F8R1_FB14_Pos)

#define	CAN_F8R1_FB14 CAN_F8R1_FB14_Msk

#define	CAN_F8R1_FB15_Pos (15U)

#define	CAN_F8R1_FB15_Msk (0x1UL << CAN_F8R1_FB15_Pos)

#define	CAN_F8R1_FB15 CAN_F8R1_FB15_Msk

#define	CAN_F8R1_FB16_Pos (16U)

#define	CAN_F8R1_FB16_Msk (0x1UL << CAN_F8R1_FB16_Pos)

#define	CAN_F8R1_FB16 CAN_F8R1_FB16_Msk

#define	CAN_F8R1_FB17_Pos (17U)

#define	CAN_F8R1_FB17_Msk (0x1UL << CAN_F8R1_FB17_Pos)

#define	CAN_F8R1_FB17 CAN_F8R1_FB17_Msk

#define	CAN_F8R1_FB18_Pos (18U)

#define	CAN_F8R1_FB18_Msk (0x1UL << CAN_F8R1_FB18_Pos)

#define	CAN_F8R1_FB18 CAN_F8R1_FB18_Msk

#define	CAN_F8R1_FB19_Pos (19U)

#define	CAN_F8R1_FB19_Msk (0x1UL << CAN_F8R1_FB19_Pos)

#define	CAN_F8R1_FB19 CAN_F8R1_FB19_Msk

#define	CAN_F8R1_FB20_Pos (20U)

#define	CAN_F8R1_FB20_Msk (0x1UL << CAN_F8R1_FB20_Pos)

#define	CAN_F8R1_FB20 CAN_F8R1_FB20_Msk

#define	CAN_F8R1_FB21_Pos (21U)

#define	CAN_F8R1_FB21_Msk (0x1UL << CAN_F8R1_FB21_Pos)

#define	CAN_F8R1_FB21 CAN_F8R1_FB21_Msk

#define	CAN_F8R1_FB22_Pos (22U)

#define	CAN_F8R1_FB22_Msk (0x1UL << CAN_F8R1_FB22_Pos)

#define	CAN_F8R1_FB22 CAN_F8R1_FB22_Msk

#define	CAN_F8R1_FB23_Pos (23U)

#define	CAN_F8R1_FB23_Msk (0x1UL << CAN_F8R1_FB23_Pos)

#define	CAN_F8R1_FB23 CAN_F8R1_FB23_Msk

#define	CAN_F8R1_FB24_Pos (24U)

#define	CAN_F8R1_FB24_Msk (0x1UL << CAN_F8R1_FB24_Pos)

#define	CAN_F8R1_FB24 CAN_F8R1_FB24_Msk

#define	CAN_F8R1_FB25_Pos (25U)

#define	CAN_F8R1_FB25_Msk (0x1UL << CAN_F8R1_FB25_Pos)

#define	CAN_F8R1_FB25 CAN_F8R1_FB25_Msk

#define	CAN_F8R1_FB26_Pos (26U)

#define	CAN_F8R1_FB26_Msk (0x1UL << CAN_F8R1_FB26_Pos)

#define	CAN_F8R1_FB26 CAN_F8R1_FB26_Msk

#define	CAN_F8R1_FB27_Pos (27U)

#define	CAN_F8R1_FB27_Msk (0x1UL << CAN_F8R1_FB27_Pos)

#define	CAN_F8R1_FB27 CAN_F8R1_FB27_Msk

#define	CAN_F8R1_FB28_Pos (28U)

#define	CAN_F8R1_FB28_Msk (0x1UL << CAN_F8R1_FB28_Pos)

#define	CAN_F8R1_FB28 CAN_F8R1_FB28_Msk

#define	CAN_F8R1_FB29_Pos (29U)

#define	CAN_F8R1_FB29_Msk (0x1UL << CAN_F8R1_FB29_Pos)

#define	CAN_F8R1_FB29 CAN_F8R1_FB29_Msk

#define	CAN_F8R1_FB30_Pos (30U)

#define	CAN_F8R1_FB30_Msk (0x1UL << CAN_F8R1_FB30_Pos)

#define	CAN_F8R1_FB30 CAN_F8R1_FB30_Msk

#define	CAN_F8R1_FB31_Pos (31U)

#define	CAN_F8R1_FB31_Msk (0x1UL << CAN_F8R1_FB31_Pos)

#define	CAN_F8R1_FB31 CAN_F8R1_FB31_Msk

#define	CAN_F9R1_FB0_Pos (0U)

#define	CAN_F9R1_FB0_Msk (0x1UL << CAN_F9R1_FB0_Pos)

#define	CAN_F9R1_FB0 CAN_F9R1_FB0_Msk

#define	CAN_F9R1_FB1_Pos (1U)

#define	CAN_F9R1_FB1_Msk (0x1UL << CAN_F9R1_FB1_Pos)

#define	CAN_F9R1_FB1 CAN_F9R1_FB1_Msk

#define	CAN_F9R1_FB2_Pos (2U)

#define	CAN_F9R1_FB2_Msk (0x1UL << CAN_F9R1_FB2_Pos)

#define	CAN_F9R1_FB2 CAN_F9R1_FB2_Msk

#define	CAN_F9R1_FB3_Pos (3U)

#define	CAN_F9R1_FB3_Msk (0x1UL << CAN_F9R1_FB3_Pos)

#define	CAN_F9R1_FB3 CAN_F9R1_FB3_Msk

#define	CAN_F9R1_FB4_Pos (4U)

#define	CAN_F9R1_FB4_Msk (0x1UL << CAN_F9R1_FB4_Pos)

#define	CAN_F9R1_FB4 CAN_F9R1_FB4_Msk

#define	CAN_F9R1_FB5_Pos (5U)

#define	CAN_F9R1_FB5_Msk (0x1UL << CAN_F9R1_FB5_Pos)

#define	CAN_F9R1_FB5 CAN_F9R1_FB5_Msk

#define	CAN_F9R1_FB6_Pos (6U)

#define	CAN_F9R1_FB6_Msk (0x1UL << CAN_F9R1_FB6_Pos)

#define	CAN_F9R1_FB6 CAN_F9R1_FB6_Msk

#define	CAN_F9R1_FB7_Pos (7U)

#define	CAN_F9R1_FB7_Msk (0x1UL << CAN_F9R1_FB7_Pos)

#define	CAN_F9R1_FB7 CAN_F9R1_FB7_Msk

#define	CAN_F9R1_FB8_Pos (8U)

#define	CAN_F9R1_FB8_Msk (0x1UL << CAN_F9R1_FB8_Pos)

#define	CAN_F9R1_FB8 CAN_F9R1_FB8_Msk

#define	CAN_F9R1_FB9_Pos (9U)

#define	CAN_F9R1_FB9_Msk (0x1UL << CAN_F9R1_FB9_Pos)

#define	CAN_F9R1_FB9 CAN_F9R1_FB9_Msk

#define	CAN_F9R1_FB10_Pos (10U)

#define	CAN_F9R1_FB10_Msk (0x1UL << CAN_F9R1_FB10_Pos)

#define	CAN_F9R1_FB10 CAN_F9R1_FB10_Msk

#define	CAN_F9R1_FB11_Pos (11U)

#define	CAN_F9R1_FB11_Msk (0x1UL << CAN_F9R1_FB11_Pos)

#define	CAN_F9R1_FB11 CAN_F9R1_FB11_Msk

#define	CAN_F9R1_FB12_Pos (12U)

#define	CAN_F9R1_FB12_Msk (0x1UL << CAN_F9R1_FB12_Pos)

#define	CAN_F9R1_FB12 CAN_F9R1_FB12_Msk

#define	CAN_F9R1_FB13_Pos (13U)

#define	CAN_F9R1_FB13_Msk (0x1UL << CAN_F9R1_FB13_Pos)

#define	CAN_F9R1_FB13 CAN_F9R1_FB13_Msk

#define	CAN_F9R1_FB14_Pos (14U)

#define	CAN_F9R1_FB14_Msk (0x1UL << CAN_F9R1_FB14_Pos)

#define	CAN_F9R1_FB14 CAN_F9R1_FB14_Msk

#define	CAN_F9R1_FB15_Pos (15U)

#define	CAN_F9R1_FB15_Msk (0x1UL << CAN_F9R1_FB15_Pos)

#define	CAN_F9R1_FB15 CAN_F9R1_FB15_Msk

#define	CAN_F9R1_FB16_Pos (16U)

#define	CAN_F9R1_FB16_Msk (0x1UL << CAN_F9R1_FB16_Pos)

#define	CAN_F9R1_FB16 CAN_F9R1_FB16_Msk

#define	CAN_F9R1_FB17_Pos (17U)

#define	CAN_F9R1_FB17_Msk (0x1UL << CAN_F9R1_FB17_Pos)

#define	CAN_F9R1_FB17 CAN_F9R1_FB17_Msk

#define	CAN_F9R1_FB18_Pos (18U)

#define	CAN_F9R1_FB18_Msk (0x1UL << CAN_F9R1_FB18_Pos)

#define	CAN_F9R1_FB18 CAN_F9R1_FB18_Msk

#define	CAN_F9R1_FB19_Pos (19U)

#define	CAN_F9R1_FB19_Msk (0x1UL << CAN_F9R1_FB19_Pos)

#define	CAN_F9R1_FB19 CAN_F9R1_FB19_Msk

#define	CAN_F9R1_FB20_Pos (20U)

#define	CAN_F9R1_FB20_Msk (0x1UL << CAN_F9R1_FB20_Pos)

#define	CAN_F9R1_FB20 CAN_F9R1_FB20_Msk

#define	CAN_F9R1_FB21_Pos (21U)

#define	CAN_F9R1_FB21_Msk (0x1UL << CAN_F9R1_FB21_Pos)

#define	CAN_F9R1_FB21 CAN_F9R1_FB21_Msk

#define	CAN_F9R1_FB22_Pos (22U)

#define	CAN_F9R1_FB22_Msk (0x1UL << CAN_F9R1_FB22_Pos)

#define	CAN_F9R1_FB22 CAN_F9R1_FB22_Msk

#define	CAN_F9R1_FB23_Pos (23U)

#define	CAN_F9R1_FB23_Msk (0x1UL << CAN_F9R1_FB23_Pos)

#define	CAN_F9R1_FB23 CAN_F9R1_FB23_Msk

#define	CAN_F9R1_FB24_Pos (24U)

#define	CAN_F9R1_FB24_Msk (0x1UL << CAN_F9R1_FB24_Pos)

#define	CAN_F9R1_FB24 CAN_F9R1_FB24_Msk

#define	CAN_F9R1_FB25_Pos (25U)

#define	CAN_F9R1_FB25_Msk (0x1UL << CAN_F9R1_FB25_Pos)

#define	CAN_F9R1_FB25 CAN_F9R1_FB25_Msk

#define	CAN_F9R1_FB26_Pos (26U)

#define	CAN_F9R1_FB26_Msk (0x1UL << CAN_F9R1_FB26_Pos)

#define	CAN_F9R1_FB26 CAN_F9R1_FB26_Msk

#define	CAN_F9R1_FB27_Pos (27U)

#define	CAN_F9R1_FB27_Msk (0x1UL << CAN_F9R1_FB27_Pos)

#define	CAN_F9R1_FB27 CAN_F9R1_FB27_Msk

#define	CAN_F9R1_FB28_Pos (28U)

#define	CAN_F9R1_FB28_Msk (0x1UL << CAN_F9R1_FB28_Pos)

#define	CAN_F9R1_FB28 CAN_F9R1_FB28_Msk

#define	CAN_F9R1_FB29_Pos (29U)

#define	CAN_F9R1_FB29_Msk (0x1UL << CAN_F9R1_FB29_Pos)

#define	CAN_F9R1_FB29 CAN_F9R1_FB29_Msk

#define	CAN_F9R1_FB30_Pos (30U)

#define	CAN_F9R1_FB30_Msk (0x1UL << CAN_F9R1_FB30_Pos)

#define	CAN_F9R1_FB30 CAN_F9R1_FB30_Msk

#define	CAN_F9R1_FB31_Pos (31U)

#define	CAN_F9R1_FB31_Msk (0x1UL << CAN_F9R1_FB31_Pos)

#define	CAN_F9R1_FB31 CAN_F9R1_FB31_Msk

#define	CAN_F10R1_FB0_Pos (0U)

#define	CAN_F10R1_FB0_Msk (0x1UL << CAN_F10R1_FB0_Pos)

#define	CAN_F10R1_FB0 CAN_F10R1_FB0_Msk

#define	CAN_F10R1_FB1_Pos (1U)

#define	CAN_F10R1_FB1_Msk (0x1UL << CAN_F10R1_FB1_Pos)

#define	CAN_F10R1_FB1 CAN_F10R1_FB1_Msk

#define	CAN_F10R1_FB2_Pos (2U)

#define	CAN_F10R1_FB2_Msk (0x1UL << CAN_F10R1_FB2_Pos)

#define	CAN_F10R1_FB2 CAN_F10R1_FB2_Msk

#define	CAN_F10R1_FB3_Pos (3U)

#define	CAN_F10R1_FB3_Msk (0x1UL << CAN_F10R1_FB3_Pos)

#define	CAN_F10R1_FB3 CAN_F10R1_FB3_Msk

#define	CAN_F10R1_FB4_Pos (4U)

#define	CAN_F10R1_FB4_Msk (0x1UL << CAN_F10R1_FB4_Pos)

#define	CAN_F10R1_FB4 CAN_F10R1_FB4_Msk

#define	CAN_F10R1_FB5_Pos (5U)

#define	CAN_F10R1_FB5_Msk (0x1UL << CAN_F10R1_FB5_Pos)

#define	CAN_F10R1_FB5 CAN_F10R1_FB5_Msk

#define	CAN_F10R1_FB6_Pos (6U)

#define	CAN_F10R1_FB6_Msk (0x1UL << CAN_F10R1_FB6_Pos)

#define	CAN_F10R1_FB6 CAN_F10R1_FB6_Msk

#define	CAN_F10R1_FB7_Pos (7U)

#define	CAN_F10R1_FB7_Msk (0x1UL << CAN_F10R1_FB7_Pos)

#define	CAN_F10R1_FB7 CAN_F10R1_FB7_Msk

#define	CAN_F10R1_FB8_Pos (8U)

#define	CAN_F10R1_FB8_Msk (0x1UL << CAN_F10R1_FB8_Pos)

#define	CAN_F10R1_FB8 CAN_F10R1_FB8_Msk

#define	CAN_F10R1_FB9_Pos (9U)

#define	CAN_F10R1_FB9_Msk (0x1UL << CAN_F10R1_FB9_Pos)

#define	CAN_F10R1_FB9 CAN_F10R1_FB9_Msk

#define	CAN_F10R1_FB10_Pos (10U)

#define	CAN_F10R1_FB10_Msk (0x1UL << CAN_F10R1_FB10_Pos)

#define	CAN_F10R1_FB10 CAN_F10R1_FB10_Msk

#define	CAN_F10R1_FB11_Pos (11U)

#define	CAN_F10R1_FB11_Msk (0x1UL << CAN_F10R1_FB11_Pos)

#define	CAN_F10R1_FB11 CAN_F10R1_FB11_Msk

#define	CAN_F10R1_FB12_Pos (12U)

#define	CAN_F10R1_FB12_Msk (0x1UL << CAN_F10R1_FB12_Pos)

#define	CAN_F10R1_FB12 CAN_F10R1_FB12_Msk

#define	CAN_F10R1_FB13_Pos (13U)

#define	CAN_F10R1_FB13_Msk (0x1UL << CAN_F10R1_FB13_Pos)

#define	CAN_F10R1_FB13 CAN_F10R1_FB13_Msk

#define	CAN_F10R1_FB14_Pos (14U)

#define	CAN_F10R1_FB14_Msk (0x1UL << CAN_F10R1_FB14_Pos)

#define	CAN_F10R1_FB14 CAN_F10R1_FB14_Msk

#define	CAN_F10R1_FB15_Pos (15U)

#define	CAN_F10R1_FB15_Msk (0x1UL << CAN_F10R1_FB15_Pos)

#define	CAN_F10R1_FB15 CAN_F10R1_FB15_Msk

#define	CAN_F10R1_FB16_Pos (16U)

#define	CAN_F10R1_FB16_Msk (0x1UL << CAN_F10R1_FB16_Pos)

#define	CAN_F10R1_FB16 CAN_F10R1_FB16_Msk

#define	CAN_F10R1_FB17_Pos (17U)

#define	CAN_F10R1_FB17_Msk (0x1UL << CAN_F10R1_FB17_Pos)

#define	CAN_F10R1_FB17 CAN_F10R1_FB17_Msk

#define	CAN_F10R1_FB18_Pos (18U)

#define	CAN_F10R1_FB18_Msk (0x1UL << CAN_F10R1_FB18_Pos)

#define	CAN_F10R1_FB18 CAN_F10R1_FB18_Msk

#define	CAN_F10R1_FB19_Pos (19U)

#define	CAN_F10R1_FB19_Msk (0x1UL << CAN_F10R1_FB19_Pos)

#define	CAN_F10R1_FB19 CAN_F10R1_FB19_Msk

#define	CAN_F10R1_FB20_Pos (20U)

#define	CAN_F10R1_FB20_Msk (0x1UL << CAN_F10R1_FB20_Pos)

#define	CAN_F10R1_FB20 CAN_F10R1_FB20_Msk

#define	CAN_F10R1_FB21_Pos (21U)

#define	CAN_F10R1_FB21_Msk (0x1UL << CAN_F10R1_FB21_Pos)

#define	CAN_F10R1_FB21 CAN_F10R1_FB21_Msk

#define	CAN_F10R1_FB22_Pos (22U)

#define	CAN_F10R1_FB22_Msk (0x1UL << CAN_F10R1_FB22_Pos)

#define	CAN_F10R1_FB22 CAN_F10R1_FB22_Msk

#define	CAN_F10R1_FB23_Pos (23U)

#define	CAN_F10R1_FB23_Msk (0x1UL << CAN_F10R1_FB23_Pos)

#define	CAN_F10R1_FB23 CAN_F10R1_FB23_Msk

#define	CAN_F10R1_FB24_Pos (24U)

#define	CAN_F10R1_FB24_Msk (0x1UL << CAN_F10R1_FB24_Pos)

#define	CAN_F10R1_FB24 CAN_F10R1_FB24_Msk

#define	CAN_F10R1_FB25_Pos (25U)

#define	CAN_F10R1_FB25_Msk (0x1UL << CAN_F10R1_FB25_Pos)

#define	CAN_F10R1_FB25 CAN_F10R1_FB25_Msk

#define	CAN_F10R1_FB26_Pos (26U)

#define	CAN_F10R1_FB26_Msk (0x1UL << CAN_F10R1_FB26_Pos)

#define	CAN_F10R1_FB26 CAN_F10R1_FB26_Msk

#define	CAN_F10R1_FB27_Pos (27U)

#define	CAN_F10R1_FB27_Msk (0x1UL << CAN_F10R1_FB27_Pos)

#define	CAN_F10R1_FB27 CAN_F10R1_FB27_Msk

#define	CAN_F10R1_FB28_Pos (28U)

#define	CAN_F10R1_FB28_Msk (0x1UL << CAN_F10R1_FB28_Pos)

#define	CAN_F10R1_FB28 CAN_F10R1_FB28_Msk

#define	CAN_F10R1_FB29_Pos (29U)

#define	CAN_F10R1_FB29_Msk (0x1UL << CAN_F10R1_FB29_Pos)

#define	CAN_F10R1_FB29 CAN_F10R1_FB29_Msk

#define	CAN_F10R1_FB30_Pos (30U)

#define	CAN_F10R1_FB30_Msk (0x1UL << CAN_F10R1_FB30_Pos)

#define	CAN_F10R1_FB30 CAN_F10R1_FB30_Msk

#define	CAN_F10R1_FB31_Pos (31U)

#define	CAN_F10R1_FB31_Msk (0x1UL << CAN_F10R1_FB31_Pos)

#define	CAN_F10R1_FB31 CAN_F10R1_FB31_Msk

#define	CAN_F11R1_FB0_Pos (0U)

#define	CAN_F11R1_FB0_Msk (0x1UL << CAN_F11R1_FB0_Pos)

#define	CAN_F11R1_FB0 CAN_F11R1_FB0_Msk

#define	CAN_F11R1_FB1_Pos (1U)

#define	CAN_F11R1_FB1_Msk (0x1UL << CAN_F11R1_FB1_Pos)

#define	CAN_F11R1_FB1 CAN_F11R1_FB1_Msk

#define	CAN_F11R1_FB2_Pos (2U)

#define	CAN_F11R1_FB2_Msk (0x1UL << CAN_F11R1_FB2_Pos)

#define	CAN_F11R1_FB2 CAN_F11R1_FB2_Msk

#define	CAN_F11R1_FB3_Pos (3U)

#define	CAN_F11R1_FB3_Msk (0x1UL << CAN_F11R1_FB3_Pos)

#define	CAN_F11R1_FB3 CAN_F11R1_FB3_Msk

#define	CAN_F11R1_FB4_Pos (4U)

#define	CAN_F11R1_FB4_Msk (0x1UL << CAN_F11R1_FB4_Pos)

#define	CAN_F11R1_FB4 CAN_F11R1_FB4_Msk

#define	CAN_F11R1_FB5_Pos (5U)

#define	CAN_F11R1_FB5_Msk (0x1UL << CAN_F11R1_FB5_Pos)

#define	CAN_F11R1_FB5 CAN_F11R1_FB5_Msk

#define	CAN_F11R1_FB6_Pos (6U)

#define	CAN_F11R1_FB6_Msk (0x1UL << CAN_F11R1_FB6_Pos)

#define	CAN_F11R1_FB6 CAN_F11R1_FB6_Msk

#define	CAN_F11R1_FB7_Pos (7U)

#define	CAN_F11R1_FB7_Msk (0x1UL << CAN_F11R1_FB7_Pos)

#define	CAN_F11R1_FB7 CAN_F11R1_FB7_Msk

#define	CAN_F11R1_FB8_Pos (8U)

#define	CAN_F11R1_FB8_Msk (0x1UL << CAN_F11R1_FB8_Pos)

#define	CAN_F11R1_FB8 CAN_F11R1_FB8_Msk

#define	CAN_F11R1_FB9_Pos (9U)

#define	CAN_F11R1_FB9_Msk (0x1UL << CAN_F11R1_FB9_Pos)

#define	CAN_F11R1_FB9 CAN_F11R1_FB9_Msk

#define	CAN_F11R1_FB10_Pos (10U)

#define	CAN_F11R1_FB10_Msk (0x1UL << CAN_F11R1_FB10_Pos)

#define	CAN_F11R1_FB10 CAN_F11R1_FB10_Msk

#define	CAN_F11R1_FB11_Pos (11U)

#define	CAN_F11R1_FB11_Msk (0x1UL << CAN_F11R1_FB11_Pos)

#define	CAN_F11R1_FB11 CAN_F11R1_FB11_Msk

#define	CAN_F11R1_FB12_Pos (12U)

#define	CAN_F11R1_FB12_Msk (0x1UL << CAN_F11R1_FB12_Pos)

#define	CAN_F11R1_FB12 CAN_F11R1_FB12_Msk

#define	CAN_F11R1_FB13_Pos (13U)

#define	CAN_F11R1_FB13_Msk (0x1UL << CAN_F11R1_FB13_Pos)

#define	CAN_F11R1_FB13 CAN_F11R1_FB13_Msk

#define	CAN_F11R1_FB14_Pos (14U)

#define	CAN_F11R1_FB14_Msk (0x1UL << CAN_F11R1_FB14_Pos)

#define	CAN_F11R1_FB14 CAN_F11R1_FB14_Msk

#define	CAN_F11R1_FB15_Pos (15U)

#define	CAN_F11R1_FB15_Msk (0x1UL << CAN_F11R1_FB15_Pos)

#define	CAN_F11R1_FB15 CAN_F11R1_FB15_Msk

#define	CAN_F11R1_FB16_Pos (16U)

#define	CAN_F11R1_FB16_Msk (0x1UL << CAN_F11R1_FB16_Pos)

#define	CAN_F11R1_FB16 CAN_F11R1_FB16_Msk

#define	CAN_F11R1_FB17_Pos (17U)

#define	CAN_F11R1_FB17_Msk (0x1UL << CAN_F11R1_FB17_Pos)

#define	CAN_F11R1_FB17 CAN_F11R1_FB17_Msk

#define	CAN_F11R1_FB18_Pos (18U)

#define	CAN_F11R1_FB18_Msk (0x1UL << CAN_F11R1_FB18_Pos)

#define	CAN_F11R1_FB18 CAN_F11R1_FB18_Msk

#define	CAN_F11R1_FB19_Pos (19U)

#define	CAN_F11R1_FB19_Msk (0x1UL << CAN_F11R1_FB19_Pos)

#define	CAN_F11R1_FB19 CAN_F11R1_FB19_Msk

#define	CAN_F11R1_FB20_Pos (20U)

#define	CAN_F11R1_FB20_Msk (0x1UL << CAN_F11R1_FB20_Pos)

#define	CAN_F11R1_FB20 CAN_F11R1_FB20_Msk

#define	CAN_F11R1_FB21_Pos (21U)

#define	CAN_F11R1_FB21_Msk (0x1UL << CAN_F11R1_FB21_Pos)

#define	CAN_F11R1_FB21 CAN_F11R1_FB21_Msk

#define	CAN_F11R1_FB22_Pos (22U)

#define	CAN_F11R1_FB22_Msk (0x1UL << CAN_F11R1_FB22_Pos)

#define	CAN_F11R1_FB22 CAN_F11R1_FB22_Msk

#define	CAN_F11R1_FB23_Pos (23U)

#define	CAN_F11R1_FB23_Msk (0x1UL << CAN_F11R1_FB23_Pos)

#define	CAN_F11R1_FB23 CAN_F11R1_FB23_Msk

#define	CAN_F11R1_FB24_Pos (24U)

#define	CAN_F11R1_FB24_Msk (0x1UL << CAN_F11R1_FB24_Pos)

#define	CAN_F11R1_FB24 CAN_F11R1_FB24_Msk

#define	CAN_F11R1_FB25_Pos (25U)

#define	CAN_F11R1_FB25_Msk (0x1UL << CAN_F11R1_FB25_Pos)

#define	CAN_F11R1_FB25 CAN_F11R1_FB25_Msk

#define	CAN_F11R1_FB26_Pos (26U)

#define	CAN_F11R1_FB26_Msk (0x1UL << CAN_F11R1_FB26_Pos)

#define	CAN_F11R1_FB26 CAN_F11R1_FB26_Msk

#define	CAN_F11R1_FB27_Pos (27U)

#define	CAN_F11R1_FB27_Msk (0x1UL << CAN_F11R1_FB27_Pos)

#define	CAN_F11R1_FB27 CAN_F11R1_FB27_Msk

#define	CAN_F11R1_FB28_Pos (28U)

#define	CAN_F11R1_FB28_Msk (0x1UL << CAN_F11R1_FB28_Pos)

#define	CAN_F11R1_FB28 CAN_F11R1_FB28_Msk

#define	CAN_F11R1_FB29_Pos (29U)

#define	CAN_F11R1_FB29_Msk (0x1UL << CAN_F11R1_FB29_Pos)

#define	CAN_F11R1_FB29 CAN_F11R1_FB29_Msk

#define	CAN_F11R1_FB30_Pos (30U)

#define	CAN_F11R1_FB30_Msk (0x1UL << CAN_F11R1_FB30_Pos)

#define	CAN_F11R1_FB30 CAN_F11R1_FB30_Msk

#define	CAN_F11R1_FB31_Pos (31U)

#define	CAN_F11R1_FB31_Msk (0x1UL << CAN_F11R1_FB31_Pos)

#define	CAN_F11R1_FB31 CAN_F11R1_FB31_Msk

#define	CAN_F12R1_FB0_Pos (0U)

#define	CAN_F12R1_FB0_Msk (0x1UL << CAN_F12R1_FB0_Pos)

#define	CAN_F12R1_FB0 CAN_F12R1_FB0_Msk

#define	CAN_F12R1_FB1_Pos (1U)

#define	CAN_F12R1_FB1_Msk (0x1UL << CAN_F12R1_FB1_Pos)

#define	CAN_F12R1_FB1 CAN_F12R1_FB1_Msk

#define	CAN_F12R1_FB2_Pos (2U)

#define	CAN_F12R1_FB2_Msk (0x1UL << CAN_F12R1_FB2_Pos)

#define	CAN_F12R1_FB2 CAN_F12R1_FB2_Msk

#define	CAN_F12R1_FB3_Pos (3U)

#define	CAN_F12R1_FB3_Msk (0x1UL << CAN_F12R1_FB3_Pos)

#define	CAN_F12R1_FB3 CAN_F12R1_FB3_Msk

#define	CAN_F12R1_FB4_Pos (4U)

#define	CAN_F12R1_FB4_Msk (0x1UL << CAN_F12R1_FB4_Pos)

#define	CAN_F12R1_FB4 CAN_F12R1_FB4_Msk

#define	CAN_F12R1_FB5_Pos (5U)

#define	CAN_F12R1_FB5_Msk (0x1UL << CAN_F12R1_FB5_Pos)

#define	CAN_F12R1_FB5 CAN_F12R1_FB5_Msk

#define	CAN_F12R1_FB6_Pos (6U)

#define	CAN_F12R1_FB6_Msk (0x1UL << CAN_F12R1_FB6_Pos)

#define	CAN_F12R1_FB6 CAN_F12R1_FB6_Msk

#define	CAN_F12R1_FB7_Pos (7U)

#define	CAN_F12R1_FB7_Msk (0x1UL << CAN_F12R1_FB7_Pos)

#define	CAN_F12R1_FB7 CAN_F12R1_FB7_Msk

#define	CAN_F12R1_FB8_Pos (8U)

#define	CAN_F12R1_FB8_Msk (0x1UL << CAN_F12R1_FB8_Pos)

#define	CAN_F12R1_FB8 CAN_F12R1_FB8_Msk

#define	CAN_F12R1_FB9_Pos (9U)

#define	CAN_F12R1_FB9_Msk (0x1UL << CAN_F12R1_FB9_Pos)

#define	CAN_F12R1_FB9 CAN_F12R1_FB9_Msk

#define	CAN_F12R1_FB10_Pos (10U)

#define	CAN_F12R1_FB10_Msk (0x1UL << CAN_F12R1_FB10_Pos)

#define	CAN_F12R1_FB10 CAN_F12R1_FB10_Msk

#define	CAN_F12R1_FB11_Pos (11U)

#define	CAN_F12R1_FB11_Msk (0x1UL << CAN_F12R1_FB11_Pos)

#define	CAN_F12R1_FB11 CAN_F12R1_FB11_Msk

#define	CAN_F12R1_FB12_Pos (12U)

#define	CAN_F12R1_FB12_Msk (0x1UL << CAN_F12R1_FB12_Pos)

#define	CAN_F12R1_FB12 CAN_F12R1_FB12_Msk

#define	CAN_F12R1_FB13_Pos (13U)

#define	CAN_F12R1_FB13_Msk (0x1UL << CAN_F12R1_FB13_Pos)

#define	CAN_F12R1_FB13 CAN_F12R1_FB13_Msk

#define	CAN_F12R1_FB14_Pos (14U)

#define	CAN_F12R1_FB14_Msk (0x1UL << CAN_F12R1_FB14_Pos)

#define	CAN_F12R1_FB14 CAN_F12R1_FB14_Msk

#define	CAN_F12R1_FB15_Pos (15U)

#define	CAN_F12R1_FB15_Msk (0x1UL << CAN_F12R1_FB15_Pos)

#define	CAN_F12R1_FB15 CAN_F12R1_FB15_Msk

#define	CAN_F12R1_FB16_Pos (16U)

#define	CAN_F12R1_FB16_Msk (0x1UL << CAN_F12R1_FB16_Pos)

#define	CAN_F12R1_FB16 CAN_F12R1_FB16_Msk

#define	CAN_F12R1_FB17_Pos (17U)

#define	CAN_F12R1_FB17_Msk (0x1UL << CAN_F12R1_FB17_Pos)

#define	CAN_F12R1_FB17 CAN_F12R1_FB17_Msk

#define	CAN_F12R1_FB18_Pos (18U)

#define	CAN_F12R1_FB18_Msk (0x1UL << CAN_F12R1_FB18_Pos)

#define	CAN_F12R1_FB18 CAN_F12R1_FB18_Msk

#define	CAN_F12R1_FB19_Pos (19U)

#define	CAN_F12R1_FB19_Msk (0x1UL << CAN_F12R1_FB19_Pos)

#define	CAN_F12R1_FB19 CAN_F12R1_FB19_Msk

#define	CAN_F12R1_FB20_Pos (20U)

#define	CAN_F12R1_FB20_Msk (0x1UL << CAN_F12R1_FB20_Pos)

#define	CAN_F12R1_FB20 CAN_F12R1_FB20_Msk

#define	CAN_F12R1_FB21_Pos (21U)

#define	CAN_F12R1_FB21_Msk (0x1UL << CAN_F12R1_FB21_Pos)

#define	CAN_F12R1_FB21 CAN_F12R1_FB21_Msk

#define	CAN_F12R1_FB22_Pos (22U)

#define	CAN_F12R1_FB22_Msk (0x1UL << CAN_F12R1_FB22_Pos)

#define	CAN_F12R1_FB22 CAN_F12R1_FB22_Msk

#define	CAN_F12R1_FB23_Pos (23U)

#define	CAN_F12R1_FB23_Msk (0x1UL << CAN_F12R1_FB23_Pos)

#define	CAN_F12R1_FB23 CAN_F12R1_FB23_Msk

#define	CAN_F12R1_FB24_Pos (24U)

#define	CAN_F12R1_FB24_Msk (0x1UL << CAN_F12R1_FB24_Pos)

#define	CAN_F12R1_FB24 CAN_F12R1_FB24_Msk

#define	CAN_F12R1_FB25_Pos (25U)

#define	CAN_F12R1_FB25_Msk (0x1UL << CAN_F12R1_FB25_Pos)

#define	CAN_F12R1_FB25 CAN_F12R1_FB25_Msk

#define	CAN_F12R1_FB26_Pos (26U)

#define	CAN_F12R1_FB26_Msk (0x1UL << CAN_F12R1_FB26_Pos)

#define	CAN_F12R1_FB26 CAN_F12R1_FB26_Msk

#define	CAN_F12R1_FB27_Pos (27U)

#define	CAN_F12R1_FB27_Msk (0x1UL << CAN_F12R1_FB27_Pos)

#define	CAN_F12R1_FB27 CAN_F12R1_FB27_Msk

#define	CAN_F12R1_FB28_Pos (28U)

#define	CAN_F12R1_FB28_Msk (0x1UL << CAN_F12R1_FB28_Pos)

#define	CAN_F12R1_FB28 CAN_F12R1_FB28_Msk

#define	CAN_F12R1_FB29_Pos (29U)

#define	CAN_F12R1_FB29_Msk (0x1UL << CAN_F12R1_FB29_Pos)

#define	CAN_F12R1_FB29 CAN_F12R1_FB29_Msk

#define	CAN_F12R1_FB30_Pos (30U)

#define	CAN_F12R1_FB30_Msk (0x1UL << CAN_F12R1_FB30_Pos)

#define	CAN_F12R1_FB30 CAN_F12R1_FB30_Msk

#define	CAN_F12R1_FB31_Pos (31U)

#define	CAN_F12R1_FB31_Msk (0x1UL << CAN_F12R1_FB31_Pos)

#define	CAN_F12R1_FB31 CAN_F12R1_FB31_Msk

#define	CAN_F13R1_FB0_Pos (0U)

#define	CAN_F13R1_FB0_Msk (0x1UL << CAN_F13R1_FB0_Pos)

#define	CAN_F13R1_FB0 CAN_F13R1_FB0_Msk

#define	CAN_F13R1_FB1_Pos (1U)

#define	CAN_F13R1_FB1_Msk (0x1UL << CAN_F13R1_FB1_Pos)

#define	CAN_F13R1_FB1 CAN_F13R1_FB1_Msk

#define	CAN_F13R1_FB2_Pos (2U)

#define	CAN_F13R1_FB2_Msk (0x1UL << CAN_F13R1_FB2_Pos)

#define	CAN_F13R1_FB2 CAN_F13R1_FB2_Msk

#define	CAN_F13R1_FB3_Pos (3U)

#define	CAN_F13R1_FB3_Msk (0x1UL << CAN_F13R1_FB3_Pos)

#define	CAN_F13R1_FB3 CAN_F13R1_FB3_Msk

#define	CAN_F13R1_FB4_Pos (4U)

#define	CAN_F13R1_FB4_Msk (0x1UL << CAN_F13R1_FB4_Pos)

#define	CAN_F13R1_FB4 CAN_F13R1_FB4_Msk

#define	CAN_F13R1_FB5_Pos (5U)

#define	CAN_F13R1_FB5_Msk (0x1UL << CAN_F13R1_FB5_Pos)

#define	CAN_F13R1_FB5 CAN_F13R1_FB5_Msk

#define	CAN_F13R1_FB6_Pos (6U)

#define	CAN_F13R1_FB6_Msk (0x1UL << CAN_F13R1_FB6_Pos)

#define	CAN_F13R1_FB6 CAN_F13R1_FB6_Msk

#define	CAN_F13R1_FB7_Pos (7U)

#define	CAN_F13R1_FB7_Msk (0x1UL << CAN_F13R1_FB7_Pos)

#define	CAN_F13R1_FB7 CAN_F13R1_FB7_Msk

#define	CAN_F13R1_FB8_Pos (8U)

#define	CAN_F13R1_FB8_Msk (0x1UL << CAN_F13R1_FB8_Pos)

#define	CAN_F13R1_FB8 CAN_F13R1_FB8_Msk

#define	CAN_F13R1_FB9_Pos (9U)

#define	CAN_F13R1_FB9_Msk (0x1UL << CAN_F13R1_FB9_Pos)

#define	CAN_F13R1_FB9 CAN_F13R1_FB9_Msk

#define	CAN_F13R1_FB10_Pos (10U)

#define	CAN_F13R1_FB10_Msk (0x1UL << CAN_F13R1_FB10_Pos)

#define	CAN_F13R1_FB10 CAN_F13R1_FB10_Msk

#define	CAN_F13R1_FB11_Pos (11U)

#define	CAN_F13R1_FB11_Msk (0x1UL << CAN_F13R1_FB11_Pos)

#define	CAN_F13R1_FB11 CAN_F13R1_FB11_Msk

#define	CAN_F13R1_FB12_Pos (12U)

#define	CAN_F13R1_FB12_Msk (0x1UL << CAN_F13R1_FB12_Pos)

#define	CAN_F13R1_FB12 CAN_F13R1_FB12_Msk

#define	CAN_F13R1_FB13_Pos (13U)

#define	CAN_F13R1_FB13_Msk (0x1UL << CAN_F13R1_FB13_Pos)

#define	CAN_F13R1_FB13 CAN_F13R1_FB13_Msk

#define	CAN_F13R1_FB14_Pos (14U)

#define	CAN_F13R1_FB14_Msk (0x1UL << CAN_F13R1_FB14_Pos)

#define	CAN_F13R1_FB14 CAN_F13R1_FB14_Msk

#define	CAN_F13R1_FB15_Pos (15U)

#define	CAN_F13R1_FB15_Msk (0x1UL << CAN_F13R1_FB15_Pos)

#define	CAN_F13R1_FB15 CAN_F13R1_FB15_Msk

#define	CAN_F13R1_FB16_Pos (16U)

#define	CAN_F13R1_FB16_Msk (0x1UL << CAN_F13R1_FB16_Pos)

#define	CAN_F13R1_FB16 CAN_F13R1_FB16_Msk

#define	CAN_F13R1_FB17_Pos (17U)

#define	CAN_F13R1_FB17_Msk (0x1UL << CAN_F13R1_FB17_Pos)

#define	CAN_F13R1_FB17 CAN_F13R1_FB17_Msk

#define	CAN_F13R1_FB18_Pos (18U)

#define	CAN_F13R1_FB18_Msk (0x1UL << CAN_F13R1_FB18_Pos)

#define	CAN_F13R1_FB18 CAN_F13R1_FB18_Msk

#define	CAN_F13R1_FB19_Pos (19U)

#define	CAN_F13R1_FB19_Msk (0x1UL << CAN_F13R1_FB19_Pos)

#define	CAN_F13R1_FB19 CAN_F13R1_FB19_Msk

#define	CAN_F13R1_FB20_Pos (20U)

#define	CAN_F13R1_FB20_Msk (0x1UL << CAN_F13R1_FB20_Pos)

#define	CAN_F13R1_FB20 CAN_F13R1_FB20_Msk

#define	CAN_F13R1_FB21_Pos (21U)

#define	CAN_F13R1_FB21_Msk (0x1UL << CAN_F13R1_FB21_Pos)

#define	CAN_F13R1_FB21 CAN_F13R1_FB21_Msk

#define	CAN_F13R1_FB22_Pos (22U)

#define	CAN_F13R1_FB22_Msk (0x1UL << CAN_F13R1_FB22_Pos)

#define	CAN_F13R1_FB22 CAN_F13R1_FB22_Msk

#define	CAN_F13R1_FB23_Pos (23U)

#define	CAN_F13R1_FB23_Msk (0x1UL << CAN_F13R1_FB23_Pos)

#define	CAN_F13R1_FB23 CAN_F13R1_FB23_Msk

#define	CAN_F13R1_FB24_Pos (24U)

#define	CAN_F13R1_FB24_Msk (0x1UL << CAN_F13R1_FB24_Pos)

#define	CAN_F13R1_FB24 CAN_F13R1_FB24_Msk

#define	CAN_F13R1_FB25_Pos (25U)

#define	CAN_F13R1_FB25_Msk (0x1UL << CAN_F13R1_FB25_Pos)

#define	CAN_F13R1_FB25 CAN_F13R1_FB25_Msk

#define	CAN_F13R1_FB26_Pos (26U)

#define	CAN_F13R1_FB26_Msk (0x1UL << CAN_F13R1_FB26_Pos)

#define	CAN_F13R1_FB26 CAN_F13R1_FB26_Msk

#define	CAN_F13R1_FB27_Pos (27U)

#define	CAN_F13R1_FB27_Msk (0x1UL << CAN_F13R1_FB27_Pos)

#define	CAN_F13R1_FB27 CAN_F13R1_FB27_Msk

#define	CAN_F13R1_FB28_Pos (28U)

#define	CAN_F13R1_FB28_Msk (0x1UL << CAN_F13R1_FB28_Pos)

#define	CAN_F13R1_FB28 CAN_F13R1_FB28_Msk

#define	CAN_F13R1_FB29_Pos (29U)

#define	CAN_F13R1_FB29_Msk (0x1UL << CAN_F13R1_FB29_Pos)

#define	CAN_F13R1_FB29 CAN_F13R1_FB29_Msk

#define	CAN_F13R1_FB30_Pos (30U)

#define	CAN_F13R1_FB30_Msk (0x1UL << CAN_F13R1_FB30_Pos)

#define	CAN_F13R1_FB30 CAN_F13R1_FB30_Msk

#define	CAN_F13R1_FB31_Pos (31U)

#define	CAN_F13R1_FB31_Msk (0x1UL << CAN_F13R1_FB31_Pos)

#define	CAN_F13R1_FB31 CAN_F13R1_FB31_Msk

#define	CAN_F0R2_FB0_Pos (0U)

#define	CAN_F0R2_FB0_Msk (0x1UL << CAN_F0R2_FB0_Pos)

#define	CAN_F0R2_FB0 CAN_F0R2_FB0_Msk

#define	CAN_F0R2_FB1_Pos (1U)

#define	CAN_F0R2_FB1_Msk (0x1UL << CAN_F0R2_FB1_Pos)

#define	CAN_F0R2_FB1 CAN_F0R2_FB1_Msk

#define	CAN_F0R2_FB2_Pos (2U)

#define	CAN_F0R2_FB2_Msk (0x1UL << CAN_F0R2_FB2_Pos)

#define	CAN_F0R2_FB2 CAN_F0R2_FB2_Msk

#define	CAN_F0R2_FB3_Pos (3U)

#define	CAN_F0R2_FB3_Msk (0x1UL << CAN_F0R2_FB3_Pos)

#define	CAN_F0R2_FB3 CAN_F0R2_FB3_Msk

#define	CAN_F0R2_FB4_Pos (4U)

#define	CAN_F0R2_FB4_Msk (0x1UL << CAN_F0R2_FB4_Pos)

#define	CAN_F0R2_FB4 CAN_F0R2_FB4_Msk

#define	CAN_F0R2_FB5_Pos (5U)

#define	CAN_F0R2_FB5_Msk (0x1UL << CAN_F0R2_FB5_Pos)

#define	CAN_F0R2_FB5 CAN_F0R2_FB5_Msk

#define	CAN_F0R2_FB6_Pos (6U)

#define	CAN_F0R2_FB6_Msk (0x1UL << CAN_F0R2_FB6_Pos)

#define	CAN_F0R2_FB6 CAN_F0R2_FB6_Msk

#define	CAN_F0R2_FB7_Pos (7U)

#define	CAN_F0R2_FB7_Msk (0x1UL << CAN_F0R2_FB7_Pos)

#define	CAN_F0R2_FB7 CAN_F0R2_FB7_Msk

#define	CAN_F0R2_FB8_Pos (8U)

#define	CAN_F0R2_FB8_Msk (0x1UL << CAN_F0R2_FB8_Pos)

#define	CAN_F0R2_FB8 CAN_F0R2_FB8_Msk

#define	CAN_F0R2_FB9_Pos (9U)

#define	CAN_F0R2_FB9_Msk (0x1UL << CAN_F0R2_FB9_Pos)

#define	CAN_F0R2_FB9 CAN_F0R2_FB9_Msk

#define	CAN_F0R2_FB10_Pos (10U)

#define	CAN_F0R2_FB10_Msk (0x1UL << CAN_F0R2_FB10_Pos)

#define	CAN_F0R2_FB10 CAN_F0R2_FB10_Msk

#define	CAN_F0R2_FB11_Pos (11U)

#define	CAN_F0R2_FB11_Msk (0x1UL << CAN_F0R2_FB11_Pos)

#define	CAN_F0R2_FB11 CAN_F0R2_FB11_Msk

#define	CAN_F0R2_FB12_Pos (12U)

#define	CAN_F0R2_FB12_Msk (0x1UL << CAN_F0R2_FB12_Pos)

#define	CAN_F0R2_FB12 CAN_F0R2_FB12_Msk

#define	CAN_F0R2_FB13_Pos (13U)

#define	CAN_F0R2_FB13_Msk (0x1UL << CAN_F0R2_FB13_Pos)

#define	CAN_F0R2_FB13 CAN_F0R2_FB13_Msk

#define	CAN_F0R2_FB14_Pos (14U)

#define	CAN_F0R2_FB14_Msk (0x1UL << CAN_F0R2_FB14_Pos)

#define	CAN_F0R2_FB14 CAN_F0R2_FB14_Msk

#define	CAN_F0R2_FB15_Pos (15U)

#define	CAN_F0R2_FB15_Msk (0x1UL << CAN_F0R2_FB15_Pos)

#define	CAN_F0R2_FB15 CAN_F0R2_FB15_Msk

#define	CAN_F0R2_FB16_Pos (16U)

#define	CAN_F0R2_FB16_Msk (0x1UL << CAN_F0R2_FB16_Pos)

#define	CAN_F0R2_FB16 CAN_F0R2_FB16_Msk

#define	CAN_F0R2_FB17_Pos (17U)

#define	CAN_F0R2_FB17_Msk (0x1UL << CAN_F0R2_FB17_Pos)

#define	CAN_F0R2_FB17 CAN_F0R2_FB17_Msk

#define	CAN_F0R2_FB18_Pos (18U)

#define	CAN_F0R2_FB18_Msk (0x1UL << CAN_F0R2_FB18_Pos)

#define	CAN_F0R2_FB18 CAN_F0R2_FB18_Msk

#define	CAN_F0R2_FB19_Pos (19U)

#define	CAN_F0R2_FB19_Msk (0x1UL << CAN_F0R2_FB19_Pos)

#define	CAN_F0R2_FB19 CAN_F0R2_FB19_Msk

#define	CAN_F0R2_FB20_Pos (20U)

#define	CAN_F0R2_FB20_Msk (0x1UL << CAN_F0R2_FB20_Pos)

#define	CAN_F0R2_FB20 CAN_F0R2_FB20_Msk

#define	CAN_F0R2_FB21_Pos (21U)

#define	CAN_F0R2_FB21_Msk (0x1UL << CAN_F0R2_FB21_Pos)

#define	CAN_F0R2_FB21 CAN_F0R2_FB21_Msk

#define	CAN_F0R2_FB22_Pos (22U)

#define	CAN_F0R2_FB22_Msk (0x1UL << CAN_F0R2_FB22_Pos)

#define	CAN_F0R2_FB22 CAN_F0R2_FB22_Msk

#define	CAN_F0R2_FB23_Pos (23U)

#define	CAN_F0R2_FB23_Msk (0x1UL << CAN_F0R2_FB23_Pos)

#define	CAN_F0R2_FB23 CAN_F0R2_FB23_Msk

#define	CAN_F0R2_FB24_Pos (24U)

#define	CAN_F0R2_FB24_Msk (0x1UL << CAN_F0R2_FB24_Pos)

#define	CAN_F0R2_FB24 CAN_F0R2_FB24_Msk

#define	CAN_F0R2_FB25_Pos (25U)

#define	CAN_F0R2_FB25_Msk (0x1UL << CAN_F0R2_FB25_Pos)

#define	CAN_F0R2_FB25 CAN_F0R2_FB25_Msk

#define	CAN_F0R2_FB26_Pos (26U)

#define	CAN_F0R2_FB26_Msk (0x1UL << CAN_F0R2_FB26_Pos)

#define	CAN_F0R2_FB26 CAN_F0R2_FB26_Msk

#define	CAN_F0R2_FB27_Pos (27U)

#define	CAN_F0R2_FB27_Msk (0x1UL << CAN_F0R2_FB27_Pos)

#define	CAN_F0R2_FB27 CAN_F0R2_FB27_Msk

#define	CAN_F0R2_FB28_Pos (28U)

#define	CAN_F0R2_FB28_Msk (0x1UL << CAN_F0R2_FB28_Pos)

#define	CAN_F0R2_FB28 CAN_F0R2_FB28_Msk

#define	CAN_F0R2_FB29_Pos (29U)

#define	CAN_F0R2_FB29_Msk (0x1UL << CAN_F0R2_FB29_Pos)

#define	CAN_F0R2_FB29 CAN_F0R2_FB29_Msk

#define	CAN_F0R2_FB30_Pos (30U)

#define	CAN_F0R2_FB30_Msk (0x1UL << CAN_F0R2_FB30_Pos)

#define	CAN_F0R2_FB30 CAN_F0R2_FB30_Msk

#define	CAN_F0R2_FB31_Pos (31U)

#define	CAN_F0R2_FB31_Msk (0x1UL << CAN_F0R2_FB31_Pos)

#define	CAN_F0R2_FB31 CAN_F0R2_FB31_Msk

#define	CAN_F1R2_FB0_Pos (0U)

#define	CAN_F1R2_FB0_Msk (0x1UL << CAN_F1R2_FB0_Pos)

#define	CAN_F1R2_FB0 CAN_F1R2_FB0_Msk

#define	CAN_F1R2_FB1_Pos (1U)

#define	CAN_F1R2_FB1_Msk (0x1UL << CAN_F1R2_FB1_Pos)

#define	CAN_F1R2_FB1 CAN_F1R2_FB1_Msk

#define	CAN_F1R2_FB2_Pos (2U)

#define	CAN_F1R2_FB2_Msk (0x1UL << CAN_F1R2_FB2_Pos)

#define	CAN_F1R2_FB2 CAN_F1R2_FB2_Msk

#define	CAN_F1R2_FB3_Pos (3U)

#define	CAN_F1R2_FB3_Msk (0x1UL << CAN_F1R2_FB3_Pos)

#define	CAN_F1R2_FB3 CAN_F1R2_FB3_Msk

#define	CAN_F1R2_FB4_Pos (4U)

#define	CAN_F1R2_FB4_Msk (0x1UL << CAN_F1R2_FB4_Pos)

#define	CAN_F1R2_FB4 CAN_F1R2_FB4_Msk

#define	CAN_F1R2_FB5_Pos (5U)

#define	CAN_F1R2_FB5_Msk (0x1UL << CAN_F1R2_FB5_Pos)

#define	CAN_F1R2_FB5 CAN_F1R2_FB5_Msk

#define	CAN_F1R2_FB6_Pos (6U)

#define	CAN_F1R2_FB6_Msk (0x1UL << CAN_F1R2_FB6_Pos)

#define	CAN_F1R2_FB6 CAN_F1R2_FB6_Msk

#define	CAN_F1R2_FB7_Pos (7U)

#define	CAN_F1R2_FB7_Msk (0x1UL << CAN_F1R2_FB7_Pos)

#define	CAN_F1R2_FB7 CAN_F1R2_FB7_Msk

#define	CAN_F1R2_FB8_Pos (8U)

#define	CAN_F1R2_FB8_Msk (0x1UL << CAN_F1R2_FB8_Pos)

#define	CAN_F1R2_FB8 CAN_F1R2_FB8_Msk

#define	CAN_F1R2_FB9_Pos (9U)

#define	CAN_F1R2_FB9_Msk (0x1UL << CAN_F1R2_FB9_Pos)

#define	CAN_F1R2_FB9 CAN_F1R2_FB9_Msk

#define	CAN_F1R2_FB10_Pos (10U)

#define	CAN_F1R2_FB10_Msk (0x1UL << CAN_F1R2_FB10_Pos)

#define	CAN_F1R2_FB10 CAN_F1R2_FB10_Msk

#define	CAN_F1R2_FB11_Pos (11U)

#define	CAN_F1R2_FB11_Msk (0x1UL << CAN_F1R2_FB11_Pos)

#define	CAN_F1R2_FB11 CAN_F1R2_FB11_Msk

#define	CAN_F1R2_FB12_Pos (12U)

#define	CAN_F1R2_FB12_Msk (0x1UL << CAN_F1R2_FB12_Pos)

#define	CAN_F1R2_FB12 CAN_F1R2_FB12_Msk

#define	CAN_F1R2_FB13_Pos (13U)

#define	CAN_F1R2_FB13_Msk (0x1UL << CAN_F1R2_FB13_Pos)

#define	CAN_F1R2_FB13 CAN_F1R2_FB13_Msk

#define	CAN_F1R2_FB14_Pos (14U)

#define	CAN_F1R2_FB14_Msk (0x1UL << CAN_F1R2_FB14_Pos)

#define	CAN_F1R2_FB14 CAN_F1R2_FB14_Msk

#define	CAN_F1R2_FB15_Pos (15U)

#define	CAN_F1R2_FB15_Msk (0x1UL << CAN_F1R2_FB15_Pos)

#define	CAN_F1R2_FB15 CAN_F1R2_FB15_Msk

#define	CAN_F1R2_FB16_Pos (16U)

#define	CAN_F1R2_FB16_Msk (0x1UL << CAN_F1R2_FB16_Pos)

#define	CAN_F1R2_FB16 CAN_F1R2_FB16_Msk

#define	CAN_F1R2_FB17_Pos (17U)

#define	CAN_F1R2_FB17_Msk (0x1UL << CAN_F1R2_FB17_Pos)

#define	CAN_F1R2_FB17 CAN_F1R2_FB17_Msk

#define	CAN_F1R2_FB18_Pos (18U)

#define	CAN_F1R2_FB18_Msk (0x1UL << CAN_F1R2_FB18_Pos)

#define	CAN_F1R2_FB18 CAN_F1R2_FB18_Msk

#define	CAN_F1R2_FB19_Pos (19U)

#define	CAN_F1R2_FB19_Msk (0x1UL << CAN_F1R2_FB19_Pos)

#define	CAN_F1R2_FB19 CAN_F1R2_FB19_Msk

#define	CAN_F1R2_FB20_Pos (20U)

#define	CAN_F1R2_FB20_Msk (0x1UL << CAN_F1R2_FB20_Pos)

#define	CAN_F1R2_FB20 CAN_F1R2_FB20_Msk

#define	CAN_F1R2_FB21_Pos (21U)

#define	CAN_F1R2_FB21_Msk (0x1UL << CAN_F1R2_FB21_Pos)

#define	CAN_F1R2_FB21 CAN_F1R2_FB21_Msk

#define	CAN_F1R2_FB22_Pos (22U)

#define	CAN_F1R2_FB22_Msk (0x1UL << CAN_F1R2_FB22_Pos)

#define	CAN_F1R2_FB22 CAN_F1R2_FB22_Msk

#define	CAN_F1R2_FB23_Pos (23U)

#define	CAN_F1R2_FB23_Msk (0x1UL << CAN_F1R2_FB23_Pos)

#define	CAN_F1R2_FB23 CAN_F1R2_FB23_Msk

#define	CAN_F1R2_FB24_Pos (24U)

#define	CAN_F1R2_FB24_Msk (0x1UL << CAN_F1R2_FB24_Pos)

#define	CAN_F1R2_FB24 CAN_F1R2_FB24_Msk

#define	CAN_F1R2_FB25_Pos (25U)

#define	CAN_F1R2_FB25_Msk (0x1UL << CAN_F1R2_FB25_Pos)

#define	CAN_F1R2_FB25 CAN_F1R2_FB25_Msk

#define	CAN_F1R2_FB26_Pos (26U)

#define	CAN_F1R2_FB26_Msk (0x1UL << CAN_F1R2_FB26_Pos)

#define	CAN_F1R2_FB26 CAN_F1R2_FB26_Msk

#define	CAN_F1R2_FB27_Pos (27U)

#define	CAN_F1R2_FB27_Msk (0x1UL << CAN_F1R2_FB27_Pos)

#define	CAN_F1R2_FB27 CAN_F1R2_FB27_Msk

#define	CAN_F1R2_FB28_Pos (28U)

#define	CAN_F1R2_FB28_Msk (0x1UL << CAN_F1R2_FB28_Pos)

#define	CAN_F1R2_FB28 CAN_F1R2_FB28_Msk

#define	CAN_F1R2_FB29_Pos (29U)

#define	CAN_F1R2_FB29_Msk (0x1UL << CAN_F1R2_FB29_Pos)

#define	CAN_F1R2_FB29 CAN_F1R2_FB29_Msk

#define	CAN_F1R2_FB30_Pos (30U)

#define	CAN_F1R2_FB30_Msk (0x1UL << CAN_F1R2_FB30_Pos)

#define	CAN_F1R2_FB30 CAN_F1R2_FB30_Msk

#define	CAN_F1R2_FB31_Pos (31U)

#define	CAN_F1R2_FB31_Msk (0x1UL << CAN_F1R2_FB31_Pos)

#define	CAN_F1R2_FB31 CAN_F1R2_FB31_Msk

#define	CAN_F2R2_FB0_Pos (0U)

#define	CAN_F2R2_FB0_Msk (0x1UL << CAN_F2R2_FB0_Pos)

#define	CAN_F2R2_FB0 CAN_F2R2_FB0_Msk

#define	CAN_F2R2_FB1_Pos (1U)

#define	CAN_F2R2_FB1_Msk (0x1UL << CAN_F2R2_FB1_Pos)

#define	CAN_F2R2_FB1 CAN_F2R2_FB1_Msk

#define	CAN_F2R2_FB2_Pos (2U)

#define	CAN_F2R2_FB2_Msk (0x1UL << CAN_F2R2_FB2_Pos)

#define	CAN_F2R2_FB2 CAN_F2R2_FB2_Msk

#define	CAN_F2R2_FB3_Pos (3U)

#define	CAN_F2R2_FB3_Msk (0x1UL << CAN_F2R2_FB3_Pos)

#define	CAN_F2R2_FB3 CAN_F2R2_FB3_Msk

#define	CAN_F2R2_FB4_Pos (4U)

#define	CAN_F2R2_FB4_Msk (0x1UL << CAN_F2R2_FB4_Pos)

#define	CAN_F2R2_FB4 CAN_F2R2_FB4_Msk

#define	CAN_F2R2_FB5_Pos (5U)

#define	CAN_F2R2_FB5_Msk (0x1UL << CAN_F2R2_FB5_Pos)

#define	CAN_F2R2_FB5 CAN_F2R2_FB5_Msk

#define	CAN_F2R2_FB6_Pos (6U)

#define	CAN_F2R2_FB6_Msk (0x1UL << CAN_F2R2_FB6_Pos)

#define	CAN_F2R2_FB6 CAN_F2R2_FB6_Msk

#define	CAN_F2R2_FB7_Pos (7U)

#define	CAN_F2R2_FB7_Msk (0x1UL << CAN_F2R2_FB7_Pos)

#define	CAN_F2R2_FB7 CAN_F2R2_FB7_Msk

#define	CAN_F2R2_FB8_Pos (8U)

#define	CAN_F2R2_FB8_Msk (0x1UL << CAN_F2R2_FB8_Pos)

#define	CAN_F2R2_FB8 CAN_F2R2_FB8_Msk

#define	CAN_F2R2_FB9_Pos (9U)

#define	CAN_F2R2_FB9_Msk (0x1UL << CAN_F2R2_FB9_Pos)

#define	CAN_F2R2_FB9 CAN_F2R2_FB9_Msk

#define	CAN_F2R2_FB10_Pos (10U)

#define	CAN_F2R2_FB10_Msk (0x1UL << CAN_F2R2_FB10_Pos)

#define	CAN_F2R2_FB10 CAN_F2R2_FB10_Msk

#define	CAN_F2R2_FB11_Pos (11U)

#define	CAN_F2R2_FB11_Msk (0x1UL << CAN_F2R2_FB11_Pos)

#define	CAN_F2R2_FB11 CAN_F2R2_FB11_Msk

#define	CAN_F2R2_FB12_Pos (12U)

#define	CAN_F2R2_FB12_Msk (0x1UL << CAN_F2R2_FB12_Pos)

#define	CAN_F2R2_FB12 CAN_F2R2_FB12_Msk

#define	CAN_F2R2_FB13_Pos (13U)

#define	CAN_F2R2_FB13_Msk (0x1UL << CAN_F2R2_FB13_Pos)

#define	CAN_F2R2_FB13 CAN_F2R2_FB13_Msk

#define	CAN_F2R2_FB14_Pos (14U)

#define	CAN_F2R2_FB14_Msk (0x1UL << CAN_F2R2_FB14_Pos)

#define	CAN_F2R2_FB14 CAN_F2R2_FB14_Msk

#define	CAN_F2R2_FB15_Pos (15U)

#define	CAN_F2R2_FB15_Msk (0x1UL << CAN_F2R2_FB15_Pos)

#define	CAN_F2R2_FB15 CAN_F2R2_FB15_Msk

#define	CAN_F2R2_FB16_Pos (16U)

#define	CAN_F2R2_FB16_Msk (0x1UL << CAN_F2R2_FB16_Pos)

#define	CAN_F2R2_FB16 CAN_F2R2_FB16_Msk

#define	CAN_F2R2_FB17_Pos (17U)

#define	CAN_F2R2_FB17_Msk (0x1UL << CAN_F2R2_FB17_Pos)

#define	CAN_F2R2_FB17 CAN_F2R2_FB17_Msk

#define	CAN_F2R2_FB18_Pos (18U)

#define	CAN_F2R2_FB18_Msk (0x1UL << CAN_F2R2_FB18_Pos)

#define	CAN_F2R2_FB18 CAN_F2R2_FB18_Msk

#define	CAN_F2R2_FB19_Pos (19U)

#define	CAN_F2R2_FB19_Msk (0x1UL << CAN_F2R2_FB19_Pos)

#define	CAN_F2R2_FB19 CAN_F2R2_FB19_Msk

#define	CAN_F2R2_FB20_Pos (20U)

#define	CAN_F2R2_FB20_Msk (0x1UL << CAN_F2R2_FB20_Pos)

#define	CAN_F2R2_FB20 CAN_F2R2_FB20_Msk

#define	CAN_F2R2_FB21_Pos (21U)

#define	CAN_F2R2_FB21_Msk (0x1UL << CAN_F2R2_FB21_Pos)

#define	CAN_F2R2_FB21 CAN_F2R2_FB21_Msk

#define	CAN_F2R2_FB22_Pos (22U)

#define	CAN_F2R2_FB22_Msk (0x1UL << CAN_F2R2_FB22_Pos)

#define	CAN_F2R2_FB22 CAN_F2R2_FB22_Msk

#define	CAN_F2R2_FB23_Pos (23U)

#define	CAN_F2R2_FB23_Msk (0x1UL << CAN_F2R2_FB23_Pos)

#define	CAN_F2R2_FB23 CAN_F2R2_FB23_Msk

#define	CAN_F2R2_FB24_Pos (24U)

#define	CAN_F2R2_FB24_Msk (0x1UL << CAN_F2R2_FB24_Pos)

#define	CAN_F2R2_FB24 CAN_F2R2_FB24_Msk

#define	CAN_F2R2_FB25_Pos (25U)

#define	CAN_F2R2_FB25_Msk (0x1UL << CAN_F2R2_FB25_Pos)

#define	CAN_F2R2_FB25 CAN_F2R2_FB25_Msk

#define	CAN_F2R2_FB26_Pos (26U)

#define	CAN_F2R2_FB26_Msk (0x1UL << CAN_F2R2_FB26_Pos)

#define	CAN_F2R2_FB26 CAN_F2R2_FB26_Msk

#define	CAN_F2R2_FB27_Pos (27U)

#define	CAN_F2R2_FB27_Msk (0x1UL << CAN_F2R2_FB27_Pos)

#define	CAN_F2R2_FB27 CAN_F2R2_FB27_Msk

#define	CAN_F2R2_FB28_Pos (28U)

#define	CAN_F2R2_FB28_Msk (0x1UL << CAN_F2R2_FB28_Pos)

#define	CAN_F2R2_FB28 CAN_F2R2_FB28_Msk

#define	CAN_F2R2_FB29_Pos (29U)

#define	CAN_F2R2_FB29_Msk (0x1UL << CAN_F2R2_FB29_Pos)

#define	CAN_F2R2_FB29 CAN_F2R2_FB29_Msk

#define	CAN_F2R2_FB30_Pos (30U)

#define	CAN_F2R2_FB30_Msk (0x1UL << CAN_F2R2_FB30_Pos)

#define	CAN_F2R2_FB30 CAN_F2R2_FB30_Msk

#define	CAN_F2R2_FB31_Pos (31U)

#define	CAN_F2R2_FB31_Msk (0x1UL << CAN_F2R2_FB31_Pos)

#define	CAN_F2R2_FB31 CAN_F2R2_FB31_Msk

#define	CAN_F3R2_FB0_Pos (0U)

#define	CAN_F3R2_FB0_Msk (0x1UL << CAN_F3R2_FB0_Pos)

#define	CAN_F3R2_FB0 CAN_F3R2_FB0_Msk

#define	CAN_F3R2_FB1_Pos (1U)

#define	CAN_F3R2_FB1_Msk (0x1UL << CAN_F3R2_FB1_Pos)

#define	CAN_F3R2_FB1 CAN_F3R2_FB1_Msk

#define	CAN_F3R2_FB2_Pos (2U)

#define	CAN_F3R2_FB2_Msk (0x1UL << CAN_F3R2_FB2_Pos)

#define	CAN_F3R2_FB2 CAN_F3R2_FB2_Msk

#define	CAN_F3R2_FB3_Pos (3U)

#define	CAN_F3R2_FB3_Msk (0x1UL << CAN_F3R2_FB3_Pos)

#define	CAN_F3R2_FB3 CAN_F3R2_FB3_Msk

#define	CAN_F3R2_FB4_Pos (4U)

#define	CAN_F3R2_FB4_Msk (0x1UL << CAN_F3R2_FB4_Pos)

#define	CAN_F3R2_FB4 CAN_F3R2_FB4_Msk

#define	CAN_F3R2_FB5_Pos (5U)

#define	CAN_F3R2_FB5_Msk (0x1UL << CAN_F3R2_FB5_Pos)

#define	CAN_F3R2_FB5 CAN_F3R2_FB5_Msk

#define	CAN_F3R2_FB6_Pos (6U)

#define	CAN_F3R2_FB6_Msk (0x1UL << CAN_F3R2_FB6_Pos)

#define	CAN_F3R2_FB6 CAN_F3R2_FB6_Msk

#define	CAN_F3R2_FB7_Pos (7U)

#define	CAN_F3R2_FB7_Msk (0x1UL << CAN_F3R2_FB7_Pos)

#define	CAN_F3R2_FB7 CAN_F3R2_FB7_Msk

#define	CAN_F3R2_FB8_Pos (8U)

#define	CAN_F3R2_FB8_Msk (0x1UL << CAN_F3R2_FB8_Pos)

#define	CAN_F3R2_FB8 CAN_F3R2_FB8_Msk

#define	CAN_F3R2_FB9_Pos (9U)

#define	CAN_F3R2_FB9_Msk (0x1UL << CAN_F3R2_FB9_Pos)

#define	CAN_F3R2_FB9 CAN_F3R2_FB9_Msk

#define	CAN_F3R2_FB10_Pos (10U)

#define	CAN_F3R2_FB10_Msk (0x1UL << CAN_F3R2_FB10_Pos)

#define	CAN_F3R2_FB10 CAN_F3R2_FB10_Msk

#define	CAN_F3R2_FB11_Pos (11U)

#define	CAN_F3R2_FB11_Msk (0x1UL << CAN_F3R2_FB11_Pos)

#define	CAN_F3R2_FB11 CAN_F3R2_FB11_Msk

#define	CAN_F3R2_FB12_Pos (12U)

#define	CAN_F3R2_FB12_Msk (0x1UL << CAN_F3R2_FB12_Pos)

#define	CAN_F3R2_FB12 CAN_F3R2_FB12_Msk

#define	CAN_F3R2_FB13_Pos (13U)

#define	CAN_F3R2_FB13_Msk (0x1UL << CAN_F3R2_FB13_Pos)

#define	CAN_F3R2_FB13 CAN_F3R2_FB13_Msk

#define	CAN_F3R2_FB14_Pos (14U)

#define	CAN_F3R2_FB14_Msk (0x1UL << CAN_F3R2_FB14_Pos)

#define	CAN_F3R2_FB14 CAN_F3R2_FB14_Msk

#define	CAN_F3R2_FB15_Pos (15U)

#define	CAN_F3R2_FB15_Msk (0x1UL << CAN_F3R2_FB15_Pos)

#define	CAN_F3R2_FB15 CAN_F3R2_FB15_Msk

#define	CAN_F3R2_FB16_Pos (16U)

#define	CAN_F3R2_FB16_Msk (0x1UL << CAN_F3R2_FB16_Pos)

#define	CAN_F3R2_FB16 CAN_F3R2_FB16_Msk

#define	CAN_F3R2_FB17_Pos (17U)

#define	CAN_F3R2_FB17_Msk (0x1UL << CAN_F3R2_FB17_Pos)

#define	CAN_F3R2_FB17 CAN_F3R2_FB17_Msk

#define	CAN_F3R2_FB18_Pos (18U)

#define	CAN_F3R2_FB18_Msk (0x1UL << CAN_F3R2_FB18_Pos)

#define	CAN_F3R2_FB18 CAN_F3R2_FB18_Msk

#define	CAN_F3R2_FB19_Pos (19U)

#define	CAN_F3R2_FB19_Msk (0x1UL << CAN_F3R2_FB19_Pos)

#define	CAN_F3R2_FB19 CAN_F3R2_FB19_Msk

#define	CAN_F3R2_FB20_Pos (20U)

#define	CAN_F3R2_FB20_Msk (0x1UL << CAN_F3R2_FB20_Pos)

#define	CAN_F3R2_FB20 CAN_F3R2_FB20_Msk

#define	CAN_F3R2_FB21_Pos (21U)

#define	CAN_F3R2_FB21_Msk (0x1UL << CAN_F3R2_FB21_Pos)

#define	CAN_F3R2_FB21 CAN_F3R2_FB21_Msk

#define	CAN_F3R2_FB22_Pos (22U)

#define	CAN_F3R2_FB22_Msk (0x1UL << CAN_F3R2_FB22_Pos)

#define	CAN_F3R2_FB22 CAN_F3R2_FB22_Msk

#define	CAN_F3R2_FB23_Pos (23U)

#define	CAN_F3R2_FB23_Msk (0x1UL << CAN_F3R2_FB23_Pos)

#define	CAN_F3R2_FB23 CAN_F3R2_FB23_Msk

#define	CAN_F3R2_FB24_Pos (24U)

#define	CAN_F3R2_FB24_Msk (0x1UL << CAN_F3R2_FB24_Pos)

#define	CAN_F3R2_FB24 CAN_F3R2_FB24_Msk

#define	CAN_F3R2_FB25_Pos (25U)

#define	CAN_F3R2_FB25_Msk (0x1UL << CAN_F3R2_FB25_Pos)

#define	CAN_F3R2_FB25 CAN_F3R2_FB25_Msk

#define	CAN_F3R2_FB26_Pos (26U)

#define	CAN_F3R2_FB26_Msk (0x1UL << CAN_F3R2_FB26_Pos)

#define	CAN_F3R2_FB26 CAN_F3R2_FB26_Msk

#define	CAN_F3R2_FB27_Pos (27U)

#define	CAN_F3R2_FB27_Msk (0x1UL << CAN_F3R2_FB27_Pos)

#define	CAN_F3R2_FB27 CAN_F3R2_FB27_Msk

#define	CAN_F3R2_FB28_Pos (28U)

#define	CAN_F3R2_FB28_Msk (0x1UL << CAN_F3R2_FB28_Pos)

#define	CAN_F3R2_FB28 CAN_F3R2_FB28_Msk

#define	CAN_F3R2_FB29_Pos (29U)

#define	CAN_F3R2_FB29_Msk (0x1UL << CAN_F3R2_FB29_Pos)

#define	CAN_F3R2_FB29 CAN_F3R2_FB29_Msk

#define	CAN_F3R2_FB30_Pos (30U)

#define	CAN_F3R2_FB30_Msk (0x1UL << CAN_F3R2_FB30_Pos)

#define	CAN_F3R2_FB30 CAN_F3R2_FB30_Msk

#define	CAN_F3R2_FB31_Pos (31U)

#define	CAN_F3R2_FB31_Msk (0x1UL << CAN_F3R2_FB31_Pos)

#define	CAN_F3R2_FB31 CAN_F3R2_FB31_Msk

#define	CAN_F4R2_FB0_Pos (0U)

#define	CAN_F4R2_FB0_Msk (0x1UL << CAN_F4R2_FB0_Pos)

#define	CAN_F4R2_FB0 CAN_F4R2_FB0_Msk

#define	CAN_F4R2_FB1_Pos (1U)

#define	CAN_F4R2_FB1_Msk (0x1UL << CAN_F4R2_FB1_Pos)

#define	CAN_F4R2_FB1 CAN_F4R2_FB1_Msk

#define	CAN_F4R2_FB2_Pos (2U)

#define	CAN_F4R2_FB2_Msk (0x1UL << CAN_F4R2_FB2_Pos)

#define	CAN_F4R2_FB2 CAN_F4R2_FB2_Msk

#define	CAN_F4R2_FB3_Pos (3U)

#define	CAN_F4R2_FB3_Msk (0x1UL << CAN_F4R2_FB3_Pos)

#define	CAN_F4R2_FB3 CAN_F4R2_FB3_Msk

#define	CAN_F4R2_FB4_Pos (4U)

#define	CAN_F4R2_FB4_Msk (0x1UL << CAN_F4R2_FB4_Pos)

#define	CAN_F4R2_FB4 CAN_F4R2_FB4_Msk

#define	CAN_F4R2_FB5_Pos (5U)

#define	CAN_F4R2_FB5_Msk (0x1UL << CAN_F4R2_FB5_Pos)

#define	CAN_F4R2_FB5 CAN_F4R2_FB5_Msk

#define	CAN_F4R2_FB6_Pos (6U)

#define	CAN_F4R2_FB6_Msk (0x1UL << CAN_F4R2_FB6_Pos)

#define	CAN_F4R2_FB6 CAN_F4R2_FB6_Msk

#define	CAN_F4R2_FB7_Pos (7U)

#define	CAN_F4R2_FB7_Msk (0x1UL << CAN_F4R2_FB7_Pos)

#define	CAN_F4R2_FB7 CAN_F4R2_FB7_Msk

#define	CAN_F4R2_FB8_Pos (8U)

#define	CAN_F4R2_FB8_Msk (0x1UL << CAN_F4R2_FB8_Pos)

#define	CAN_F4R2_FB8 CAN_F4R2_FB8_Msk

#define	CAN_F4R2_FB9_Pos (9U)

#define	CAN_F4R2_FB9_Msk (0x1UL << CAN_F4R2_FB9_Pos)

#define	CAN_F4R2_FB9 CAN_F4R2_FB9_Msk

#define	CAN_F4R2_FB10_Pos (10U)

#define	CAN_F4R2_FB10_Msk (0x1UL << CAN_F4R2_FB10_Pos)

#define	CAN_F4R2_FB10 CAN_F4R2_FB10_Msk

#define	CAN_F4R2_FB11_Pos (11U)

#define	CAN_F4R2_FB11_Msk (0x1UL << CAN_F4R2_FB11_Pos)

#define	CAN_F4R2_FB11 CAN_F4R2_FB11_Msk

#define	CAN_F4R2_FB12_Pos (12U)

#define	CAN_F4R2_FB12_Msk (0x1UL << CAN_F4R2_FB12_Pos)

#define	CAN_F4R2_FB12 CAN_F4R2_FB12_Msk

#define	CAN_F4R2_FB13_Pos (13U)

#define	CAN_F4R2_FB13_Msk (0x1UL << CAN_F4R2_FB13_Pos)

#define	CAN_F4R2_FB13 CAN_F4R2_FB13_Msk

#define	CAN_F4R2_FB14_Pos (14U)

#define	CAN_F4R2_FB14_Msk (0x1UL << CAN_F4R2_FB14_Pos)

#define	CAN_F4R2_FB14 CAN_F4R2_FB14_Msk

#define	CAN_F4R2_FB15_Pos (15U)

#define	CAN_F4R2_FB15_Msk (0x1UL << CAN_F4R2_FB15_Pos)

#define	CAN_F4R2_FB15 CAN_F4R2_FB15_Msk

#define	CAN_F4R2_FB16_Pos (16U)

#define	CAN_F4R2_FB16_Msk (0x1UL << CAN_F4R2_FB16_Pos)

#define	CAN_F4R2_FB16 CAN_F4R2_FB16_Msk

#define	CAN_F4R2_FB17_Pos (17U)

#define	CAN_F4R2_FB17_Msk (0x1UL << CAN_F4R2_FB17_Pos)

#define	CAN_F4R2_FB17 CAN_F4R2_FB17_Msk

#define	CAN_F4R2_FB18_Pos (18U)

#define	CAN_F4R2_FB18_Msk (0x1UL << CAN_F4R2_FB18_Pos)

#define	CAN_F4R2_FB18 CAN_F4R2_FB18_Msk

#define	CAN_F4R2_FB19_Pos (19U)

#define	CAN_F4R2_FB19_Msk (0x1UL << CAN_F4R2_FB19_Pos)

#define	CAN_F4R2_FB19 CAN_F4R2_FB19_Msk

#define	CAN_F4R2_FB20_Pos (20U)

#define	CAN_F4R2_FB20_Msk (0x1UL << CAN_F4R2_FB20_Pos)

#define	CAN_F4R2_FB20 CAN_F4R2_FB20_Msk

#define	CAN_F4R2_FB21_Pos (21U)

#define	CAN_F4R2_FB21_Msk (0x1UL << CAN_F4R2_FB21_Pos)

#define	CAN_F4R2_FB21 CAN_F4R2_FB21_Msk

#define	CAN_F4R2_FB22_Pos (22U)

#define	CAN_F4R2_FB22_Msk (0x1UL << CAN_F4R2_FB22_Pos)

#define	CAN_F4R2_FB22 CAN_F4R2_FB22_Msk

#define	CAN_F4R2_FB23_Pos (23U)

#define	CAN_F4R2_FB23_Msk (0x1UL << CAN_F4R2_FB23_Pos)

#define	CAN_F4R2_FB23 CAN_F4R2_FB23_Msk

#define	CAN_F4R2_FB24_Pos (24U)

#define	CAN_F4R2_FB24_Msk (0x1UL << CAN_F4R2_FB24_Pos)

#define	CAN_F4R2_FB24 CAN_F4R2_FB24_Msk

#define	CAN_F4R2_FB25_Pos (25U)

#define	CAN_F4R2_FB25_Msk (0x1UL << CAN_F4R2_FB25_Pos)

#define	CAN_F4R2_FB25 CAN_F4R2_FB25_Msk

#define	CAN_F4R2_FB26_Pos (26U)

#define	CAN_F4R2_FB26_Msk (0x1UL << CAN_F4R2_FB26_Pos)

#define	CAN_F4R2_FB26 CAN_F4R2_FB26_Msk

#define	CAN_F4R2_FB27_Pos (27U)

#define	CAN_F4R2_FB27_Msk (0x1UL << CAN_F4R2_FB27_Pos)

#define	CAN_F4R2_FB27 CAN_F4R2_FB27_Msk

#define	CAN_F4R2_FB28_Pos (28U)

#define	CAN_F4R2_FB28_Msk (0x1UL << CAN_F4R2_FB28_Pos)

#define	CAN_F4R2_FB28 CAN_F4R2_FB28_Msk

#define	CAN_F4R2_FB29_Pos (29U)

#define	CAN_F4R2_FB29_Msk (0x1UL << CAN_F4R2_FB29_Pos)

#define	CAN_F4R2_FB29 CAN_F4R2_FB29_Msk

#define	CAN_F4R2_FB30_Pos (30U)

#define	CAN_F4R2_FB30_Msk (0x1UL << CAN_F4R2_FB30_Pos)

#define	CAN_F4R2_FB30 CAN_F4R2_FB30_Msk

#define	CAN_F4R2_FB31_Pos (31U)

#define	CAN_F4R2_FB31_Msk (0x1UL << CAN_F4R2_FB31_Pos)

#define	CAN_F4R2_FB31 CAN_F4R2_FB31_Msk

#define	CAN_F5R2_FB0_Pos (0U)

#define	CAN_F5R2_FB0_Msk (0x1UL << CAN_F5R2_FB0_Pos)

#define	CAN_F5R2_FB0 CAN_F5R2_FB0_Msk

#define	CAN_F5R2_FB1_Pos (1U)

#define	CAN_F5R2_FB1_Msk (0x1UL << CAN_F5R2_FB1_Pos)

#define	CAN_F5R2_FB1 CAN_F5R2_FB1_Msk

#define	CAN_F5R2_FB2_Pos (2U)

#define	CAN_F5R2_FB2_Msk (0x1UL << CAN_F5R2_FB2_Pos)

#define	CAN_F5R2_FB2 CAN_F5R2_FB2_Msk

#define	CAN_F5R2_FB3_Pos (3U)

#define	CAN_F5R2_FB3_Msk (0x1UL << CAN_F5R2_FB3_Pos)

#define	CAN_F5R2_FB3 CAN_F5R2_FB3_Msk

#define	CAN_F5R2_FB4_Pos (4U)

#define	CAN_F5R2_FB4_Msk (0x1UL << CAN_F5R2_FB4_Pos)

#define	CAN_F5R2_FB4 CAN_F5R2_FB4_Msk

#define	CAN_F5R2_FB5_Pos (5U)

#define	CAN_F5R2_FB5_Msk (0x1UL << CAN_F5R2_FB5_Pos)

#define	CAN_F5R2_FB5 CAN_F5R2_FB5_Msk

#define	CAN_F5R2_FB6_Pos (6U)

#define	CAN_F5R2_FB6_Msk (0x1UL << CAN_F5R2_FB6_Pos)

#define	CAN_F5R2_FB6 CAN_F5R2_FB6_Msk

#define	CAN_F5R2_FB7_Pos (7U)

#define	CAN_F5R2_FB7_Msk (0x1UL << CAN_F5R2_FB7_Pos)

#define	CAN_F5R2_FB7 CAN_F5R2_FB7_Msk

#define	CAN_F5R2_FB8_Pos (8U)

#define	CAN_F5R2_FB8_Msk (0x1UL << CAN_F5R2_FB8_Pos)

#define	CAN_F5R2_FB8 CAN_F5R2_FB8_Msk

#define	CAN_F5R2_FB9_Pos (9U)

#define	CAN_F5R2_FB9_Msk (0x1UL << CAN_F5R2_FB9_Pos)

#define	CAN_F5R2_FB9 CAN_F5R2_FB9_Msk

#define	CAN_F5R2_FB10_Pos (10U)

#define	CAN_F5R2_FB10_Msk (0x1UL << CAN_F5R2_FB10_Pos)

#define	CAN_F5R2_FB10 CAN_F5R2_FB10_Msk

#define	CAN_F5R2_FB11_Pos (11U)

#define	CAN_F5R2_FB11_Msk (0x1UL << CAN_F5R2_FB11_Pos)

#define	CAN_F5R2_FB11 CAN_F5R2_FB11_Msk

#define	CAN_F5R2_FB12_Pos (12U)

#define	CAN_F5R2_FB12_Msk (0x1UL << CAN_F5R2_FB12_Pos)

#define	CAN_F5R2_FB12 CAN_F5R2_FB12_Msk

#define	CAN_F5R2_FB13_Pos (13U)

#define	CAN_F5R2_FB13_Msk (0x1UL << CAN_F5R2_FB13_Pos)

#define	CAN_F5R2_FB13 CAN_F5R2_FB13_Msk

#define	CAN_F5R2_FB14_Pos (14U)

#define	CAN_F5R2_FB14_Msk (0x1UL << CAN_F5R2_FB14_Pos)

#define	CAN_F5R2_FB14 CAN_F5R2_FB14_Msk

#define	CAN_F5R2_FB15_Pos (15U)

#define	CAN_F5R2_FB15_Msk (0x1UL << CAN_F5R2_FB15_Pos)

#define	CAN_F5R2_FB15 CAN_F5R2_FB15_Msk

#define	CAN_F5R2_FB16_Pos (16U)

#define	CAN_F5R2_FB16_Msk (0x1UL << CAN_F5R2_FB16_Pos)

#define	CAN_F5R2_FB16 CAN_F5R2_FB16_Msk

#define	CAN_F5R2_FB17_Pos (17U)

#define	CAN_F5R2_FB17_Msk (0x1UL << CAN_F5R2_FB17_Pos)

#define	CAN_F5R2_FB17 CAN_F5R2_FB17_Msk

#define	CAN_F5R2_FB18_Pos (18U)

#define	CAN_F5R2_FB18_Msk (0x1UL << CAN_F5R2_FB18_Pos)

#define	CAN_F5R2_FB18 CAN_F5R2_FB18_Msk

#define	CAN_F5R2_FB19_Pos (19U)

#define	CAN_F5R2_FB19_Msk (0x1UL << CAN_F5R2_FB19_Pos)

#define	CAN_F5R2_FB19 CAN_F5R2_FB19_Msk

#define	CAN_F5R2_FB20_Pos (20U)

#define	CAN_F5R2_FB20_Msk (0x1UL << CAN_F5R2_FB20_Pos)

#define	CAN_F5R2_FB20 CAN_F5R2_FB20_Msk

#define	CAN_F5R2_FB21_Pos (21U)

#define	CAN_F5R2_FB21_Msk (0x1UL << CAN_F5R2_FB21_Pos)

#define	CAN_F5R2_FB21 CAN_F5R2_FB21_Msk

#define	CAN_F5R2_FB22_Pos (22U)

#define	CAN_F5R2_FB22_Msk (0x1UL << CAN_F5R2_FB22_Pos)

#define	CAN_F5R2_FB22 CAN_F5R2_FB22_Msk

#define	CAN_F5R2_FB23_Pos (23U)

#define	CAN_F5R2_FB23_Msk (0x1UL << CAN_F5R2_FB23_Pos)

#define	CAN_F5R2_FB23 CAN_F5R2_FB23_Msk

#define	CAN_F5R2_FB24_Pos (24U)

#define	CAN_F5R2_FB24_Msk (0x1UL << CAN_F5R2_FB24_Pos)

#define	CAN_F5R2_FB24 CAN_F5R2_FB24_Msk

#define	CAN_F5R2_FB25_Pos (25U)

#define	CAN_F5R2_FB25_Msk (0x1UL << CAN_F5R2_FB25_Pos)

#define	CAN_F5R2_FB25 CAN_F5R2_FB25_Msk

#define	CAN_F5R2_FB26_Pos (26U)

#define	CAN_F5R2_FB26_Msk (0x1UL << CAN_F5R2_FB26_Pos)

#define	CAN_F5R2_FB26 CAN_F5R2_FB26_Msk

#define	CAN_F5R2_FB27_Pos (27U)

#define	CAN_F5R2_FB27_Msk (0x1UL << CAN_F5R2_FB27_Pos)

#define	CAN_F5R2_FB27 CAN_F5R2_FB27_Msk

#define	CAN_F5R2_FB28_Pos (28U)

#define	CAN_F5R2_FB28_Msk (0x1UL << CAN_F5R2_FB28_Pos)

#define	CAN_F5R2_FB28 CAN_F5R2_FB28_Msk

#define	CAN_F5R2_FB29_Pos (29U)

#define	CAN_F5R2_FB29_Msk (0x1UL << CAN_F5R2_FB29_Pos)

#define	CAN_F5R2_FB29 CAN_F5R2_FB29_Msk

#define	CAN_F5R2_FB30_Pos (30U)

#define	CAN_F5R2_FB30_Msk (0x1UL << CAN_F5R2_FB30_Pos)

#define	CAN_F5R2_FB30 CAN_F5R2_FB30_Msk

#define	CAN_F5R2_FB31_Pos (31U)

#define	CAN_F5R2_FB31_Msk (0x1UL << CAN_F5R2_FB31_Pos)

#define	CAN_F5R2_FB31 CAN_F5R2_FB31_Msk

#define	CAN_F6R2_FB0_Pos (0U)

#define	CAN_F6R2_FB0_Msk (0x1UL << CAN_F6R2_FB0_Pos)

#define	CAN_F6R2_FB0 CAN_F6R2_FB0_Msk

#define	CAN_F6R2_FB1_Pos (1U)

#define	CAN_F6R2_FB1_Msk (0x1UL << CAN_F6R2_FB1_Pos)

#define	CAN_F6R2_FB1 CAN_F6R2_FB1_Msk

#define	CAN_F6R2_FB2_Pos (2U)

#define	CAN_F6R2_FB2_Msk (0x1UL << CAN_F6R2_FB2_Pos)

#define	CAN_F6R2_FB2 CAN_F6R2_FB2_Msk

#define	CAN_F6R2_FB3_Pos (3U)

#define	CAN_F6R2_FB3_Msk (0x1UL << CAN_F6R2_FB3_Pos)

#define	CAN_F6R2_FB3 CAN_F6R2_FB3_Msk

#define	CAN_F6R2_FB4_Pos (4U)

#define	CAN_F6R2_FB4_Msk (0x1UL << CAN_F6R2_FB4_Pos)

#define	CAN_F6R2_FB4 CAN_F6R2_FB4_Msk

#define	CAN_F6R2_FB5_Pos (5U)

#define	CAN_F6R2_FB5_Msk (0x1UL << CAN_F6R2_FB5_Pos)

#define	CAN_F6R2_FB5 CAN_F6R2_FB5_Msk

#define	CAN_F6R2_FB6_Pos (6U)

#define	CAN_F6R2_FB6_Msk (0x1UL << CAN_F6R2_FB6_Pos)

#define	CAN_F6R2_FB6 CAN_F6R2_FB6_Msk

#define	CAN_F6R2_FB7_Pos (7U)

#define	CAN_F6R2_FB7_Msk (0x1UL << CAN_F6R2_FB7_Pos)

#define	CAN_F6R2_FB7 CAN_F6R2_FB7_Msk

#define	CAN_F6R2_FB8_Pos (8U)

#define	CAN_F6R2_FB8_Msk (0x1UL << CAN_F6R2_FB8_Pos)

#define	CAN_F6R2_FB8 CAN_F6R2_FB8_Msk

#define	CAN_F6R2_FB9_Pos (9U)

#define	CAN_F6R2_FB9_Msk (0x1UL << CAN_F6R2_FB9_Pos)

#define	CAN_F6R2_FB9 CAN_F6R2_FB9_Msk

#define	CAN_F6R2_FB10_Pos (10U)

#define	CAN_F6R2_FB10_Msk (0x1UL << CAN_F6R2_FB10_Pos)

#define	CAN_F6R2_FB10 CAN_F6R2_FB10_Msk

#define	CAN_F6R2_FB11_Pos (11U)

#define	CAN_F6R2_FB11_Msk (0x1UL << CAN_F6R2_FB11_Pos)

#define	CAN_F6R2_FB11 CAN_F6R2_FB11_Msk

#define	CAN_F6R2_FB12_Pos (12U)

#define	CAN_F6R2_FB12_Msk (0x1UL << CAN_F6R2_FB12_Pos)

#define	CAN_F6R2_FB12 CAN_F6R2_FB12_Msk

#define	CAN_F6R2_FB13_Pos (13U)

#define	CAN_F6R2_FB13_Msk (0x1UL << CAN_F6R2_FB13_Pos)

#define	CAN_F6R2_FB13 CAN_F6R2_FB13_Msk

#define	CAN_F6R2_FB14_Pos (14U)

#define	CAN_F6R2_FB14_Msk (0x1UL << CAN_F6R2_FB14_Pos)

#define	CAN_F6R2_FB14 CAN_F6R2_FB14_Msk

#define	CAN_F6R2_FB15_Pos (15U)

#define	CAN_F6R2_FB15_Msk (0x1UL << CAN_F6R2_FB15_Pos)

#define	CAN_F6R2_FB15 CAN_F6R2_FB15_Msk

#define	CAN_F6R2_FB16_Pos (16U)

#define	CAN_F6R2_FB16_Msk (0x1UL << CAN_F6R2_FB16_Pos)

#define	CAN_F6R2_FB16 CAN_F6R2_FB16_Msk

#define	CAN_F6R2_FB17_Pos (17U)

#define	CAN_F6R2_FB17_Msk (0x1UL << CAN_F6R2_FB17_Pos)

#define	CAN_F6R2_FB17 CAN_F6R2_FB17_Msk

#define	CAN_F6R2_FB18_Pos (18U)

#define	CAN_F6R2_FB18_Msk (0x1UL << CAN_F6R2_FB18_Pos)

#define	CAN_F6R2_FB18 CAN_F6R2_FB18_Msk

#define	CAN_F6R2_FB19_Pos (19U)

#define	CAN_F6R2_FB19_Msk (0x1UL << CAN_F6R2_FB19_Pos)

#define	CAN_F6R2_FB19 CAN_F6R2_FB19_Msk

#define	CAN_F6R2_FB20_Pos (20U)

#define	CAN_F6R2_FB20_Msk (0x1UL << CAN_F6R2_FB20_Pos)

#define	CAN_F6R2_FB20 CAN_F6R2_FB20_Msk

#define	CAN_F6R2_FB21_Pos (21U)

#define	CAN_F6R2_FB21_Msk (0x1UL << CAN_F6R2_FB21_Pos)

#define	CAN_F6R2_FB21 CAN_F6R2_FB21_Msk

#define	CAN_F6R2_FB22_Pos (22U)

#define	CAN_F6R2_FB22_Msk (0x1UL << CAN_F6R2_FB22_Pos)

#define	CAN_F6R2_FB22 CAN_F6R2_FB22_Msk

#define	CAN_F6R2_FB23_Pos (23U)

#define	CAN_F6R2_FB23_Msk (0x1UL << CAN_F6R2_FB23_Pos)

#define	CAN_F6R2_FB23 CAN_F6R2_FB23_Msk

#define	CAN_F6R2_FB24_Pos (24U)

#define	CAN_F6R2_FB24_Msk (0x1UL << CAN_F6R2_FB24_Pos)

#define	CAN_F6R2_FB24 CAN_F6R2_FB24_Msk

#define	CAN_F6R2_FB25_Pos (25U)

#define	CAN_F6R2_FB25_Msk (0x1UL << CAN_F6R2_FB25_Pos)

#define	CAN_F6R2_FB25 CAN_F6R2_FB25_Msk

#define	CAN_F6R2_FB26_Pos (26U)

#define	CAN_F6R2_FB26_Msk (0x1UL << CAN_F6R2_FB26_Pos)

#define	CAN_F6R2_FB26 CAN_F6R2_FB26_Msk

#define	CAN_F6R2_FB27_Pos (27U)

#define	CAN_F6R2_FB27_Msk (0x1UL << CAN_F6R2_FB27_Pos)

#define	CAN_F6R2_FB27 CAN_F6R2_FB27_Msk

#define	CAN_F6R2_FB28_Pos (28U)

#define	CAN_F6R2_FB28_Msk (0x1UL << CAN_F6R2_FB28_Pos)

#define	CAN_F6R2_FB28 CAN_F6R2_FB28_Msk

#define	CAN_F6R2_FB29_Pos (29U)

#define	CAN_F6R2_FB29_Msk (0x1UL << CAN_F6R2_FB29_Pos)

#define	CAN_F6R2_FB29 CAN_F6R2_FB29_Msk

#define	CAN_F6R2_FB30_Pos (30U)

#define	CAN_F6R2_FB30_Msk (0x1UL << CAN_F6R2_FB30_Pos)

#define	CAN_F6R2_FB30 CAN_F6R2_FB30_Msk

#define	CAN_F6R2_FB31_Pos (31U)

#define	CAN_F6R2_FB31_Msk (0x1UL << CAN_F6R2_FB31_Pos)

#define	CAN_F6R2_FB31 CAN_F6R2_FB31_Msk

#define	CAN_F7R2_FB0_Pos (0U)

#define	CAN_F7R2_FB0_Msk (0x1UL << CAN_F7R2_FB0_Pos)

#define	CAN_F7R2_FB0 CAN_F7R2_FB0_Msk

#define	CAN_F7R2_FB1_Pos (1U)

#define	CAN_F7R2_FB1_Msk (0x1UL << CAN_F7R2_FB1_Pos)

#define	CAN_F7R2_FB1 CAN_F7R2_FB1_Msk

#define	CAN_F7R2_FB2_Pos (2U)

#define	CAN_F7R2_FB2_Msk (0x1UL << CAN_F7R2_FB2_Pos)

#define	CAN_F7R2_FB2 CAN_F7R2_FB2_Msk

#define	CAN_F7R2_FB3_Pos (3U)

#define	CAN_F7R2_FB3_Msk (0x1UL << CAN_F7R2_FB3_Pos)

#define	CAN_F7R2_FB3 CAN_F7R2_FB3_Msk

#define	CAN_F7R2_FB4_Pos (4U)

#define	CAN_F7R2_FB4_Msk (0x1UL << CAN_F7R2_FB4_Pos)

#define	CAN_F7R2_FB4 CAN_F7R2_FB4_Msk

#define	CAN_F7R2_FB5_Pos (5U)

#define	CAN_F7R2_FB5_Msk (0x1UL << CAN_F7R2_FB5_Pos)

#define	CAN_F7R2_FB5 CAN_F7R2_FB5_Msk

#define	CAN_F7R2_FB6_Pos (6U)

#define	CAN_F7R2_FB6_Msk (0x1UL << CAN_F7R2_FB6_Pos)

#define	CAN_F7R2_FB6 CAN_F7R2_FB6_Msk

#define	CAN_F7R2_FB7_Pos (7U)

#define	CAN_F7R2_FB7_Msk (0x1UL << CAN_F7R2_FB7_Pos)

#define	CAN_F7R2_FB7 CAN_F7R2_FB7_Msk

#define	CAN_F7R2_FB8_Pos (8U)

#define	CAN_F7R2_FB8_Msk (0x1UL << CAN_F7R2_FB8_Pos)

#define	CAN_F7R2_FB8 CAN_F7R2_FB8_Msk

#define	CAN_F7R2_FB9_Pos (9U)

#define	CAN_F7R2_FB9_Msk (0x1UL << CAN_F7R2_FB9_Pos)

#define	CAN_F7R2_FB9 CAN_F7R2_FB9_Msk

#define	CAN_F7R2_FB10_Pos (10U)

#define	CAN_F7R2_FB10_Msk (0x1UL << CAN_F7R2_FB10_Pos)

#define	CAN_F7R2_FB10 CAN_F7R2_FB10_Msk

#define	CAN_F7R2_FB11_Pos (11U)

#define	CAN_F7R2_FB11_Msk (0x1UL << CAN_F7R2_FB11_Pos)

#define	CAN_F7R2_FB11 CAN_F7R2_FB11_Msk

#define	CAN_F7R2_FB12_Pos (12U)

#define	CAN_F7R2_FB12_Msk (0x1UL << CAN_F7R2_FB12_Pos)

#define	CAN_F7R2_FB12 CAN_F7R2_FB12_Msk

#define	CAN_F7R2_FB13_Pos (13U)

#define	CAN_F7R2_FB13_Msk (0x1UL << CAN_F7R2_FB13_Pos)

#define	CAN_F7R2_FB13 CAN_F7R2_FB13_Msk

#define	CAN_F7R2_FB14_Pos (14U)

#define	CAN_F7R2_FB14_Msk (0x1UL << CAN_F7R2_FB14_Pos)

#define	CAN_F7R2_FB14 CAN_F7R2_FB14_Msk

#define	CAN_F7R2_FB15_Pos (15U)

#define	CAN_F7R2_FB15_Msk (0x1UL << CAN_F7R2_FB15_Pos)

#define	CAN_F7R2_FB15 CAN_F7R2_FB15_Msk

#define	CAN_F7R2_FB16_Pos (16U)

#define	CAN_F7R2_FB16_Msk (0x1UL << CAN_F7R2_FB16_Pos)

#define	CAN_F7R2_FB16 CAN_F7R2_FB16_Msk

#define	CAN_F7R2_FB17_Pos (17U)

#define	CAN_F7R2_FB17_Msk (0x1UL << CAN_F7R2_FB17_Pos)

#define	CAN_F7R2_FB17 CAN_F7R2_FB17_Msk

#define	CAN_F7R2_FB18_Pos (18U)

#define	CAN_F7R2_FB18_Msk (0x1UL << CAN_F7R2_FB18_Pos)

#define	CAN_F7R2_FB18 CAN_F7R2_FB18_Msk

#define	CAN_F7R2_FB19_Pos (19U)

#define	CAN_F7R2_FB19_Msk (0x1UL << CAN_F7R2_FB19_Pos)

#define	CAN_F7R2_FB19 CAN_F7R2_FB19_Msk

#define	CAN_F7R2_FB20_Pos (20U)

#define	CAN_F7R2_FB20_Msk (0x1UL << CAN_F7R2_FB20_Pos)

#define	CAN_F7R2_FB20 CAN_F7R2_FB20_Msk

#define	CAN_F7R2_FB21_Pos (21U)

#define	CAN_F7R2_FB21_Msk (0x1UL << CAN_F7R2_FB21_Pos)

#define	CAN_F7R2_FB21 CAN_F7R2_FB21_Msk

#define	CAN_F7R2_FB22_Pos (22U)

#define	CAN_F7R2_FB22_Msk (0x1UL << CAN_F7R2_FB22_Pos)

#define	CAN_F7R2_FB22 CAN_F7R2_FB22_Msk

#define	CAN_F7R2_FB23_Pos (23U)

#define	CAN_F7R2_FB23_Msk (0x1UL << CAN_F7R2_FB23_Pos)

#define	CAN_F7R2_FB23 CAN_F7R2_FB23_Msk

#define	CAN_F7R2_FB24_Pos (24U)

#define	CAN_F7R2_FB24_Msk (0x1UL << CAN_F7R2_FB24_Pos)

#define	CAN_F7R2_FB24 CAN_F7R2_FB24_Msk

#define	CAN_F7R2_FB25_Pos (25U)

#define	CAN_F7R2_FB25_Msk (0x1UL << CAN_F7R2_FB25_Pos)

#define	CAN_F7R2_FB25 CAN_F7R2_FB25_Msk

#define	CAN_F7R2_FB26_Pos (26U)

#define	CAN_F7R2_FB26_Msk (0x1UL << CAN_F7R2_FB26_Pos)

#define	CAN_F7R2_FB26 CAN_F7R2_FB26_Msk

#define	CAN_F7R2_FB27_Pos (27U)

#define	CAN_F7R2_FB27_Msk (0x1UL << CAN_F7R2_FB27_Pos)

#define	CAN_F7R2_FB27 CAN_F7R2_FB27_Msk

#define	CAN_F7R2_FB28_Pos (28U)

#define	CAN_F7R2_FB28_Msk (0x1UL << CAN_F7R2_FB28_Pos)

#define	CAN_F7R2_FB28 CAN_F7R2_FB28_Msk

#define	CAN_F7R2_FB29_Pos (29U)

#define	CAN_F7R2_FB29_Msk (0x1UL << CAN_F7R2_FB29_Pos)

#define	CAN_F7R2_FB29 CAN_F7R2_FB29_Msk

#define	CAN_F7R2_FB30_Pos (30U)

#define	CAN_F7R2_FB30_Msk (0x1UL << CAN_F7R2_FB30_Pos)

#define	CAN_F7R2_FB30 CAN_F7R2_FB30_Msk

#define	CAN_F7R2_FB31_Pos (31U)

#define	CAN_F7R2_FB31_Msk (0x1UL << CAN_F7R2_FB31_Pos)

#define	CAN_F7R2_FB31 CAN_F7R2_FB31_Msk

#define	CAN_F8R2_FB0_Pos (0U)

#define	CAN_F8R2_FB0_Msk (0x1UL << CAN_F8R2_FB0_Pos)

#define	CAN_F8R2_FB0 CAN_F8R2_FB0_Msk

#define	CAN_F8R2_FB1_Pos (1U)

#define	CAN_F8R2_FB1_Msk (0x1UL << CAN_F8R2_FB1_Pos)

#define	CAN_F8R2_FB1 CAN_F8R2_FB1_Msk

#define	CAN_F8R2_FB2_Pos (2U)

#define	CAN_F8R2_FB2_Msk (0x1UL << CAN_F8R2_FB2_Pos)

#define	CAN_F8R2_FB2 CAN_F8R2_FB2_Msk

#define	CAN_F8R2_FB3_Pos (3U)

#define	CAN_F8R2_FB3_Msk (0x1UL << CAN_F8R2_FB3_Pos)

#define	CAN_F8R2_FB3 CAN_F8R2_FB3_Msk

#define	CAN_F8R2_FB4_Pos (4U)

#define	CAN_F8R2_FB4_Msk (0x1UL << CAN_F8R2_FB4_Pos)

#define	CAN_F8R2_FB4 CAN_F8R2_FB4_Msk

#define	CAN_F8R2_FB5_Pos (5U)

#define	CAN_F8R2_FB5_Msk (0x1UL << CAN_F8R2_FB5_Pos)

#define	CAN_F8R2_FB5 CAN_F8R2_FB5_Msk

#define	CAN_F8R2_FB6_Pos (6U)

#define	CAN_F8R2_FB6_Msk (0x1UL << CAN_F8R2_FB6_Pos)

#define	CAN_F8R2_FB6 CAN_F8R2_FB6_Msk

#define	CAN_F8R2_FB7_Pos (7U)

#define	CAN_F8R2_FB7_Msk (0x1UL << CAN_F8R2_FB7_Pos)

#define	CAN_F8R2_FB7 CAN_F8R2_FB7_Msk

#define	CAN_F8R2_FB8_Pos (8U)

#define	CAN_F8R2_FB8_Msk (0x1UL << CAN_F8R2_FB8_Pos)

#define	CAN_F8R2_FB8 CAN_F8R2_FB8_Msk

#define	CAN_F8R2_FB9_Pos (9U)

#define	CAN_F8R2_FB9_Msk (0x1UL << CAN_F8R2_FB9_Pos)

#define	CAN_F8R2_FB9 CAN_F8R2_FB9_Msk

#define	CAN_F8R2_FB10_Pos (10U)

#define	CAN_F8R2_FB10_Msk (0x1UL << CAN_F8R2_FB10_Pos)

#define	CAN_F8R2_FB10 CAN_F8R2_FB10_Msk

#define	CAN_F8R2_FB11_Pos (11U)

#define	CAN_F8R2_FB11_Msk (0x1UL << CAN_F8R2_FB11_Pos)

#define	CAN_F8R2_FB11 CAN_F8R2_FB11_Msk

#define	CAN_F8R2_FB12_Pos (12U)

#define	CAN_F8R2_FB12_Msk (0x1UL << CAN_F8R2_FB12_Pos)

#define	CAN_F8R2_FB12 CAN_F8R2_FB12_Msk

#define	CAN_F8R2_FB13_Pos (13U)

#define	CAN_F8R2_FB13_Msk (0x1UL << CAN_F8R2_FB13_Pos)

#define	CAN_F8R2_FB13 CAN_F8R2_FB13_Msk

#define	CAN_F8R2_FB14_Pos (14U)

#define	CAN_F8R2_FB14_Msk (0x1UL << CAN_F8R2_FB14_Pos)

#define	CAN_F8R2_FB14 CAN_F8R2_FB14_Msk

#define	CAN_F8R2_FB15_Pos (15U)

#define	CAN_F8R2_FB15_Msk (0x1UL << CAN_F8R2_FB15_Pos)

#define	CAN_F8R2_FB15 CAN_F8R2_FB15_Msk

#define	CAN_F8R2_FB16_Pos (16U)

#define	CAN_F8R2_FB16_Msk (0x1UL << CAN_F8R2_FB16_Pos)

#define	CAN_F8R2_FB16 CAN_F8R2_FB16_Msk

#define	CAN_F8R2_FB17_Pos (17U)

#define	CAN_F8R2_FB17_Msk (0x1UL << CAN_F8R2_FB17_Pos)

#define	CAN_F8R2_FB17 CAN_F8R2_FB17_Msk

#define	CAN_F8R2_FB18_Pos (18U)

#define	CAN_F8R2_FB18_Msk (0x1UL << CAN_F8R2_FB18_Pos)

#define	CAN_F8R2_FB18 CAN_F8R2_FB18_Msk

#define	CAN_F8R2_FB19_Pos (19U)

#define	CAN_F8R2_FB19_Msk (0x1UL << CAN_F8R2_FB19_Pos)

#define	CAN_F8R2_FB19 CAN_F8R2_FB19_Msk

#define	CAN_F8R2_FB20_Pos (20U)

#define	CAN_F8R2_FB20_Msk (0x1UL << CAN_F8R2_FB20_Pos)

#define	CAN_F8R2_FB20 CAN_F8R2_FB20_Msk

#define	CAN_F8R2_FB21_Pos (21U)

#define	CAN_F8R2_FB21_Msk (0x1UL << CAN_F8R2_FB21_Pos)

#define	CAN_F8R2_FB21 CAN_F8R2_FB21_Msk

#define	CAN_F8R2_FB22_Pos (22U)

#define	CAN_F8R2_FB22_Msk (0x1UL << CAN_F8R2_FB22_Pos)

#define	CAN_F8R2_FB22 CAN_F8R2_FB22_Msk

#define	CAN_F8R2_FB23_Pos (23U)

#define	CAN_F8R2_FB23_Msk (0x1UL << CAN_F8R2_FB23_Pos)

#define	CAN_F8R2_FB23 CAN_F8R2_FB23_Msk

#define	CAN_F8R2_FB24_Pos (24U)

#define	CAN_F8R2_FB24_Msk (0x1UL << CAN_F8R2_FB24_Pos)

#define	CAN_F8R2_FB24 CAN_F8R2_FB24_Msk

#define	CAN_F8R2_FB25_Pos (25U)

#define	CAN_F8R2_FB25_Msk (0x1UL << CAN_F8R2_FB25_Pos)

#define	CAN_F8R2_FB25 CAN_F8R2_FB25_Msk

#define	CAN_F8R2_FB26_Pos (26U)

#define	CAN_F8R2_FB26_Msk (0x1UL << CAN_F8R2_FB26_Pos)

#define	CAN_F8R2_FB26 CAN_F8R2_FB26_Msk

#define	CAN_F8R2_FB27_Pos (27U)

#define	CAN_F8R2_FB27_Msk (0x1UL << CAN_F8R2_FB27_Pos)

#define	CAN_F8R2_FB27 CAN_F8R2_FB27_Msk

#define	CAN_F8R2_FB28_Pos (28U)

#define	CAN_F8R2_FB28_Msk (0x1UL << CAN_F8R2_FB28_Pos)

#define	CAN_F8R2_FB28 CAN_F8R2_FB28_Msk

#define	CAN_F8R2_FB29_Pos (29U)

#define	CAN_F8R2_FB29_Msk (0x1UL << CAN_F8R2_FB29_Pos)

#define	CAN_F8R2_FB29 CAN_F8R2_FB29_Msk

#define	CAN_F8R2_FB30_Pos (30U)

#define	CAN_F8R2_FB30_Msk (0x1UL << CAN_F8R2_FB30_Pos)

#define	CAN_F8R2_FB30 CAN_F8R2_FB30_Msk

#define	CAN_F8R2_FB31_Pos (31U)

#define	CAN_F8R2_FB31_Msk (0x1UL << CAN_F8R2_FB31_Pos)

#define	CAN_F8R2_FB31 CAN_F8R2_FB31_Msk

#define	CAN_F9R2_FB0_Pos (0U)

#define	CAN_F9R2_FB0_Msk (0x1UL << CAN_F9R2_FB0_Pos)

#define	CAN_F9R2_FB0 CAN_F9R2_FB0_Msk

#define	CAN_F9R2_FB1_Pos (1U)

#define	CAN_F9R2_FB1_Msk (0x1UL << CAN_F9R2_FB1_Pos)

#define	CAN_F9R2_FB1 CAN_F9R2_FB1_Msk

#define	CAN_F9R2_FB2_Pos (2U)

#define	CAN_F9R2_FB2_Msk (0x1UL << CAN_F9R2_FB2_Pos)

#define	CAN_F9R2_FB2 CAN_F9R2_FB2_Msk

#define	CAN_F9R2_FB3_Pos (3U)

#define	CAN_F9R2_FB3_Msk (0x1UL << CAN_F9R2_FB3_Pos)

#define	CAN_F9R2_FB3 CAN_F9R2_FB3_Msk

#define	CAN_F9R2_FB4_Pos (4U)

#define	CAN_F9R2_FB4_Msk (0x1UL << CAN_F9R2_FB4_Pos)

#define	CAN_F9R2_FB4 CAN_F9R2_FB4_Msk

#define	CAN_F9R2_FB5_Pos (5U)

#define	CAN_F9R2_FB5_Msk (0x1UL << CAN_F9R2_FB5_Pos)

#define	CAN_F9R2_FB5 CAN_F9R2_FB5_Msk

#define	CAN_F9R2_FB6_Pos (6U)

#define	CAN_F9R2_FB6_Msk (0x1UL << CAN_F9R2_FB6_Pos)

#define	CAN_F9R2_FB6 CAN_F9R2_FB6_Msk

#define	CAN_F9R2_FB7_Pos (7U)

#define	CAN_F9R2_FB7_Msk (0x1UL << CAN_F9R2_FB7_Pos)

#define	CAN_F9R2_FB7 CAN_F9R2_FB7_Msk

#define	CAN_F9R2_FB8_Pos (8U)

#define	CAN_F9R2_FB8_Msk (0x1UL << CAN_F9R2_FB8_Pos)

#define	CAN_F9R2_FB8 CAN_F9R2_FB8_Msk

#define	CAN_F9R2_FB9_Pos (9U)

#define	CAN_F9R2_FB9_Msk (0x1UL << CAN_F9R2_FB9_Pos)

#define	CAN_F9R2_FB9 CAN_F9R2_FB9_Msk

#define	CAN_F9R2_FB10_Pos (10U)

#define	CAN_F9R2_FB10_Msk (0x1UL << CAN_F9R2_FB10_Pos)

#define	CAN_F9R2_FB10 CAN_F9R2_FB10_Msk

#define	CAN_F9R2_FB11_Pos (11U)

#define	CAN_F9R2_FB11_Msk (0x1UL << CAN_F9R2_FB11_Pos)

#define	CAN_F9R2_FB11 CAN_F9R2_FB11_Msk

#define	CAN_F9R2_FB12_Pos (12U)

#define	CAN_F9R2_FB12_Msk (0x1UL << CAN_F9R2_FB12_Pos)

#define	CAN_F9R2_FB12 CAN_F9R2_FB12_Msk

#define	CAN_F9R2_FB13_Pos (13U)

#define	CAN_F9R2_FB13_Msk (0x1UL << CAN_F9R2_FB13_Pos)

#define	CAN_F9R2_FB13 CAN_F9R2_FB13_Msk

#define	CAN_F9R2_FB14_Pos (14U)

#define	CAN_F9R2_FB14_Msk (0x1UL << CAN_F9R2_FB14_Pos)

#define	CAN_F9R2_FB14 CAN_F9R2_FB14_Msk

#define	CAN_F9R2_FB15_Pos (15U)

#define	CAN_F9R2_FB15_Msk (0x1UL << CAN_F9R2_FB15_Pos)

#define	CAN_F9R2_FB15 CAN_F9R2_FB15_Msk

#define	CAN_F9R2_FB16_Pos (16U)

#define	CAN_F9R2_FB16_Msk (0x1UL << CAN_F9R2_FB16_Pos)

#define	CAN_F9R2_FB16 CAN_F9R2_FB16_Msk

#define	CAN_F9R2_FB17_Pos (17U)

#define	CAN_F9R2_FB17_Msk (0x1UL << CAN_F9R2_FB17_Pos)

#define	CAN_F9R2_FB17 CAN_F9R2_FB17_Msk

#define	CAN_F9R2_FB18_Pos (18U)

#define	CAN_F9R2_FB18_Msk (0x1UL << CAN_F9R2_FB18_Pos)

#define	CAN_F9R2_FB18 CAN_F9R2_FB18_Msk

#define	CAN_F9R2_FB19_Pos (19U)

#define	CAN_F9R2_FB19_Msk (0x1UL << CAN_F9R2_FB19_Pos)

#define	CAN_F9R2_FB19 CAN_F9R2_FB19_Msk

#define	CAN_F9R2_FB20_Pos (20U)

#define	CAN_F9R2_FB20_Msk (0x1UL << CAN_F9R2_FB20_Pos)

#define	CAN_F9R2_FB20 CAN_F9R2_FB20_Msk

#define	CAN_F9R2_FB21_Pos (21U)

#define	CAN_F9R2_FB21_Msk (0x1UL << CAN_F9R2_FB21_Pos)

#define	CAN_F9R2_FB21 CAN_F9R2_FB21_Msk

#define	CAN_F9R2_FB22_Pos (22U)

#define	CAN_F9R2_FB22_Msk (0x1UL << CAN_F9R2_FB22_Pos)

#define	CAN_F9R2_FB22 CAN_F9R2_FB22_Msk

#define	CAN_F9R2_FB23_Pos (23U)

#define	CAN_F9R2_FB23_Msk (0x1UL << CAN_F9R2_FB23_Pos)

#define	CAN_F9R2_FB23 CAN_F9R2_FB23_Msk

#define	CAN_F9R2_FB24_Pos (24U)

#define	CAN_F9R2_FB24_Msk (0x1UL << CAN_F9R2_FB24_Pos)

#define	CAN_F9R2_FB24 CAN_F9R2_FB24_Msk

#define	CAN_F9R2_FB25_Pos (25U)

#define	CAN_F9R2_FB25_Msk (0x1UL << CAN_F9R2_FB25_Pos)

#define	CAN_F9R2_FB25 CAN_F9R2_FB25_Msk

#define	CAN_F9R2_FB26_Pos (26U)

#define	CAN_F9R2_FB26_Msk (0x1UL << CAN_F9R2_FB26_Pos)

#define	CAN_F9R2_FB26 CAN_F9R2_FB26_Msk

#define	CAN_F9R2_FB27_Pos (27U)

#define	CAN_F9R2_FB27_Msk (0x1UL << CAN_F9R2_FB27_Pos)

#define	CAN_F9R2_FB27 CAN_F9R2_FB27_Msk

#define	CAN_F9R2_FB28_Pos (28U)

#define	CAN_F9R2_FB28_Msk (0x1UL << CAN_F9R2_FB28_Pos)

#define	CAN_F9R2_FB28 CAN_F9R2_FB28_Msk

#define	CAN_F9R2_FB29_Pos (29U)

#define	CAN_F9R2_FB29_Msk (0x1UL << CAN_F9R2_FB29_Pos)

#define	CAN_F9R2_FB29 CAN_F9R2_FB29_Msk

#define	CAN_F9R2_FB30_Pos (30U)

#define	CAN_F9R2_FB30_Msk (0x1UL << CAN_F9R2_FB30_Pos)

#define	CAN_F9R2_FB30 CAN_F9R2_FB30_Msk

#define	CAN_F9R2_FB31_Pos (31U)

#define	CAN_F9R2_FB31_Msk (0x1UL << CAN_F9R2_FB31_Pos)

#define	CAN_F9R2_FB31 CAN_F9R2_FB31_Msk

#define	CAN_F10R2_FB0_Pos (0U)

#define	CAN_F10R2_FB0_Msk (0x1UL << CAN_F10R2_FB0_Pos)

#define	CAN_F10R2_FB0 CAN_F10R2_FB0_Msk

#define	CAN_F10R2_FB1_Pos (1U)

#define	CAN_F10R2_FB1_Msk (0x1UL << CAN_F10R2_FB1_Pos)

#define	CAN_F10R2_FB1 CAN_F10R2_FB1_Msk

#define	CAN_F10R2_FB2_Pos (2U)

#define	CAN_F10R2_FB2_Msk (0x1UL << CAN_F10R2_FB2_Pos)

#define	CAN_F10R2_FB2 CAN_F10R2_FB2_Msk

#define	CAN_F10R2_FB3_Pos (3U)

#define	CAN_F10R2_FB3_Msk (0x1UL << CAN_F10R2_FB3_Pos)

#define	CAN_F10R2_FB3 CAN_F10R2_FB3_Msk

#define	CAN_F10R2_FB4_Pos (4U)

#define	CAN_F10R2_FB4_Msk (0x1UL << CAN_F10R2_FB4_Pos)

#define	CAN_F10R2_FB4 CAN_F10R2_FB4_Msk

#define	CAN_F10R2_FB5_Pos (5U)

#define	CAN_F10R2_FB5_Msk (0x1UL << CAN_F10R2_FB5_Pos)

#define	CAN_F10R2_FB5 CAN_F10R2_FB5_Msk

#define	CAN_F10R2_FB6_Pos (6U)

#define	CAN_F10R2_FB6_Msk (0x1UL << CAN_F10R2_FB6_Pos)

#define	CAN_F10R2_FB6 CAN_F10R2_FB6_Msk

#define	CAN_F10R2_FB7_Pos (7U)

#define	CAN_F10R2_FB7_Msk (0x1UL << CAN_F10R2_FB7_Pos)

#define	CAN_F10R2_FB7 CAN_F10R2_FB7_Msk

#define	CAN_F10R2_FB8_Pos (8U)

#define	CAN_F10R2_FB8_Msk (0x1UL << CAN_F10R2_FB8_Pos)

#define	CAN_F10R2_FB8 CAN_F10R2_FB8_Msk

#define	CAN_F10R2_FB9_Pos (9U)

#define	CAN_F10R2_FB9_Msk (0x1UL << CAN_F10R2_FB9_Pos)

#define	CAN_F10R2_FB9 CAN_F10R2_FB9_Msk

#define	CAN_F10R2_FB10_Pos (10U)

#define	CAN_F10R2_FB10_Msk (0x1UL << CAN_F10R2_FB10_Pos)

#define	CAN_F10R2_FB10 CAN_F10R2_FB10_Msk

#define	CAN_F10R2_FB11_Pos (11U)

#define	CAN_F10R2_FB11_Msk (0x1UL << CAN_F10R2_FB11_Pos)

#define	CAN_F10R2_FB11 CAN_F10R2_FB11_Msk

#define	CAN_F10R2_FB12_Pos (12U)

#define	CAN_F10R2_FB12_Msk (0x1UL << CAN_F10R2_FB12_Pos)

#define	CAN_F10R2_FB12 CAN_F10R2_FB12_Msk

#define	CAN_F10R2_FB13_Pos (13U)

#define	CAN_F10R2_FB13_Msk (0x1UL << CAN_F10R2_FB13_Pos)

#define	CAN_F10R2_FB13 CAN_F10R2_FB13_Msk

#define	CAN_F10R2_FB14_Pos (14U)

#define	CAN_F10R2_FB14_Msk (0x1UL << CAN_F10R2_FB14_Pos)

#define	CAN_F10R2_FB14 CAN_F10R2_FB14_Msk

#define	CAN_F10R2_FB15_Pos (15U)

#define	CAN_F10R2_FB15_Msk (0x1UL << CAN_F10R2_FB15_Pos)

#define	CAN_F10R2_FB15 CAN_F10R2_FB15_Msk

#define	CAN_F10R2_FB16_Pos (16U)

#define	CAN_F10R2_FB16_Msk (0x1UL << CAN_F10R2_FB16_Pos)

#define	CAN_F10R2_FB16 CAN_F10R2_FB16_Msk

#define	CAN_F10R2_FB17_Pos (17U)

#define	CAN_F10R2_FB17_Msk (0x1UL << CAN_F10R2_FB17_Pos)

#define	CAN_F10R2_FB17 CAN_F10R2_FB17_Msk

#define	CAN_F10R2_FB18_Pos (18U)

#define	CAN_F10R2_FB18_Msk (0x1UL << CAN_F10R2_FB18_Pos)

#define	CAN_F10R2_FB18 CAN_F10R2_FB18_Msk

#define	CAN_F10R2_FB19_Pos (19U)

#define	CAN_F10R2_FB19_Msk (0x1UL << CAN_F10R2_FB19_Pos)

#define	CAN_F10R2_FB19 CAN_F10R2_FB19_Msk

#define	CAN_F10R2_FB20_Pos (20U)

#define	CAN_F10R2_FB20_Msk (0x1UL << CAN_F10R2_FB20_Pos)

#define	CAN_F10R2_FB20 CAN_F10R2_FB20_Msk

#define	CAN_F10R2_FB21_Pos (21U)

#define	CAN_F10R2_FB21_Msk (0x1UL << CAN_F10R2_FB21_Pos)

#define	CAN_F10R2_FB21 CAN_F10R2_FB21_Msk

#define	CAN_F10R2_FB22_Pos (22U)

#define	CAN_F10R2_FB22_Msk (0x1UL << CAN_F10R2_FB22_Pos)

#define	CAN_F10R2_FB22 CAN_F10R2_FB22_Msk

#define	CAN_F10R2_FB23_Pos (23U)

#define	CAN_F10R2_FB23_Msk (0x1UL << CAN_F10R2_FB23_Pos)

#define	CAN_F10R2_FB23 CAN_F10R2_FB23_Msk

#define	CAN_F10R2_FB24_Pos (24U)

#define	CAN_F10R2_FB24_Msk (0x1UL << CAN_F10R2_FB24_Pos)

#define	CAN_F10R2_FB24 CAN_F10R2_FB24_Msk

#define	CAN_F10R2_FB25_Pos (25U)

#define	CAN_F10R2_FB25_Msk (0x1UL << CAN_F10R2_FB25_Pos)

#define	CAN_F10R2_FB25 CAN_F10R2_FB25_Msk

#define	CAN_F10R2_FB26_Pos (26U)

#define	CAN_F10R2_FB26_Msk (0x1UL << CAN_F10R2_FB26_Pos)

#define	CAN_F10R2_FB26 CAN_F10R2_FB26_Msk

#define	CAN_F10R2_FB27_Pos (27U)

#define	CAN_F10R2_FB27_Msk (0x1UL << CAN_F10R2_FB27_Pos)

#define	CAN_F10R2_FB27 CAN_F10R2_FB27_Msk

#define	CAN_F10R2_FB28_Pos (28U)

#define	CAN_F10R2_FB28_Msk (0x1UL << CAN_F10R2_FB28_Pos)

#define	CAN_F10R2_FB28 CAN_F10R2_FB28_Msk

#define	CAN_F10R2_FB29_Pos (29U)

#define	CAN_F10R2_FB29_Msk (0x1UL << CAN_F10R2_FB29_Pos)

#define	CAN_F10R2_FB29 CAN_F10R2_FB29_Msk

#define	CAN_F10R2_FB30_Pos (30U)

#define	CAN_F10R2_FB30_Msk (0x1UL << CAN_F10R2_FB30_Pos)

#define	CAN_F10R2_FB30 CAN_F10R2_FB30_Msk

#define	CAN_F10R2_FB31_Pos (31U)

#define	CAN_F10R2_FB31_Msk (0x1UL << CAN_F10R2_FB31_Pos)

#define	CAN_F10R2_FB31 CAN_F10R2_FB31_Msk

#define	CAN_F11R2_FB0_Pos (0U)

#define	CAN_F11R2_FB0_Msk (0x1UL << CAN_F11R2_FB0_Pos)

#define	CAN_F11R2_FB0 CAN_F11R2_FB0_Msk

#define	CAN_F11R2_FB1_Pos (1U)

#define	CAN_F11R2_FB1_Msk (0x1UL << CAN_F11R2_FB1_Pos)

#define	CAN_F11R2_FB1 CAN_F11R2_FB1_Msk

#define	CAN_F11R2_FB2_Pos (2U)

#define	CAN_F11R2_FB2_Msk (0x1UL << CAN_F11R2_FB2_Pos)

#define	CAN_F11R2_FB2 CAN_F11R2_FB2_Msk

#define	CAN_F11R2_FB3_Pos (3U)

#define	CAN_F11R2_FB3_Msk (0x1UL << CAN_F11R2_FB3_Pos)

#define	CAN_F11R2_FB3 CAN_F11R2_FB3_Msk

#define	CAN_F11R2_FB4_Pos (4U)

#define	CAN_F11R2_FB4_Msk (0x1UL << CAN_F11R2_FB4_Pos)

#define	CAN_F11R2_FB4 CAN_F11R2_FB4_Msk

#define	CAN_F11R2_FB5_Pos (5U)

#define	CAN_F11R2_FB5_Msk (0x1UL << CAN_F11R2_FB5_Pos)

#define	CAN_F11R2_FB5 CAN_F11R2_FB5_Msk

#define	CAN_F11R2_FB6_Pos (6U)

#define	CAN_F11R2_FB6_Msk (0x1UL << CAN_F11R2_FB6_Pos)

#define	CAN_F11R2_FB6 CAN_F11R2_FB6_Msk

#define	CAN_F11R2_FB7_Pos (7U)

#define	CAN_F11R2_FB7_Msk (0x1UL << CAN_F11R2_FB7_Pos)

#define	CAN_F11R2_FB7 CAN_F11R2_FB7_Msk

#define	CAN_F11R2_FB8_Pos (8U)

#define	CAN_F11R2_FB8_Msk (0x1UL << CAN_F11R2_FB8_Pos)

#define	CAN_F11R2_FB8 CAN_F11R2_FB8_Msk

#define	CAN_F11R2_FB9_Pos (9U)

#define	CAN_F11R2_FB9_Msk (0x1UL << CAN_F11R2_FB9_Pos)

#define	CAN_F11R2_FB9 CAN_F11R2_FB9_Msk

#define	CAN_F11R2_FB10_Pos (10U)

#define	CAN_F11R2_FB10_Msk (0x1UL << CAN_F11R2_FB10_Pos)

#define	CAN_F11R2_FB10 CAN_F11R2_FB10_Msk

#define	CAN_F11R2_FB11_Pos (11U)

#define	CAN_F11R2_FB11_Msk (0x1UL << CAN_F11R2_FB11_Pos)

#define	CAN_F11R2_FB11 CAN_F11R2_FB11_Msk

#define	CAN_F11R2_FB12_Pos (12U)

#define	CAN_F11R2_FB12_Msk (0x1UL << CAN_F11R2_FB12_Pos)

#define	CAN_F11R2_FB12 CAN_F11R2_FB12_Msk

#define	CAN_F11R2_FB13_Pos (13U)

#define	CAN_F11R2_FB13_Msk (0x1UL << CAN_F11R2_FB13_Pos)

#define	CAN_F11R2_FB13 CAN_F11R2_FB13_Msk

#define	CAN_F11R2_FB14_Pos (14U)

#define	CAN_F11R2_FB14_Msk (0x1UL << CAN_F11R2_FB14_Pos)

#define	CAN_F11R2_FB14 CAN_F11R2_FB14_Msk

#define	CAN_F11R2_FB15_Pos (15U)

#define	CAN_F11R2_FB15_Msk (0x1UL << CAN_F11R2_FB15_Pos)

#define	CAN_F11R2_FB15 CAN_F11R2_FB15_Msk

#define	CAN_F11R2_FB16_Pos (16U)

#define	CAN_F11R2_FB16_Msk (0x1UL << CAN_F11R2_FB16_Pos)

#define	CAN_F11R2_FB16 CAN_F11R2_FB16_Msk

#define	CAN_F11R2_FB17_Pos (17U)

#define	CAN_F11R2_FB17_Msk (0x1UL << CAN_F11R2_FB17_Pos)

#define	CAN_F11R2_FB17 CAN_F11R2_FB17_Msk

#define	CAN_F11R2_FB18_Pos (18U)

#define	CAN_F11R2_FB18_Msk (0x1UL << CAN_F11R2_FB18_Pos)

#define	CAN_F11R2_FB18 CAN_F11R2_FB18_Msk

#define	CAN_F11R2_FB19_Pos (19U)

#define	CAN_F11R2_FB19_Msk (0x1UL << CAN_F11R2_FB19_Pos)

#define	CAN_F11R2_FB19 CAN_F11R2_FB19_Msk

#define	CAN_F11R2_FB20_Pos (20U)

#define	CAN_F11R2_FB20_Msk (0x1UL << CAN_F11R2_FB20_Pos)

#define	CAN_F11R2_FB20 CAN_F11R2_FB20_Msk

#define	CAN_F11R2_FB21_Pos (21U)

#define	CAN_F11R2_FB21_Msk (0x1UL << CAN_F11R2_FB21_Pos)

#define	CAN_F11R2_FB21 CAN_F11R2_FB21_Msk

#define	CAN_F11R2_FB22_Pos (22U)

#define	CAN_F11R2_FB22_Msk (0x1UL << CAN_F11R2_FB22_Pos)

#define	CAN_F11R2_FB22 CAN_F11R2_FB22_Msk

#define	CAN_F11R2_FB23_Pos (23U)

#define	CAN_F11R2_FB23_Msk (0x1UL << CAN_F11R2_FB23_Pos)

#define	CAN_F11R2_FB23 CAN_F11R2_FB23_Msk

#define	CAN_F11R2_FB24_Pos (24U)

#define	CAN_F11R2_FB24_Msk (0x1UL << CAN_F11R2_FB24_Pos)

#define	CAN_F11R2_FB24 CAN_F11R2_FB24_Msk

#define	CAN_F11R2_FB25_Pos (25U)

#define	CAN_F11R2_FB25_Msk (0x1UL << CAN_F11R2_FB25_Pos)

#define	CAN_F11R2_FB25 CAN_F11R2_FB25_Msk

#define	CAN_F11R2_FB26_Pos (26U)

#define	CAN_F11R2_FB26_Msk (0x1UL << CAN_F11R2_FB26_Pos)

#define	CAN_F11R2_FB26 CAN_F11R2_FB26_Msk

#define	CAN_F11R2_FB27_Pos (27U)

#define	CAN_F11R2_FB27_Msk (0x1UL << CAN_F11R2_FB27_Pos)

#define	CAN_F11R2_FB27 CAN_F11R2_FB27_Msk

#define	CAN_F11R2_FB28_Pos (28U)

#define	CAN_F11R2_FB28_Msk (0x1UL << CAN_F11R2_FB28_Pos)

#define	CAN_F11R2_FB28 CAN_F11R2_FB28_Msk

#define	CAN_F11R2_FB29_Pos (29U)

#define	CAN_F11R2_FB29_Msk (0x1UL << CAN_F11R2_FB29_Pos)

#define	CAN_F11R2_FB29 CAN_F11R2_FB29_Msk

#define	CAN_F11R2_FB30_Pos (30U)

#define	CAN_F11R2_FB30_Msk (0x1UL << CAN_F11R2_FB30_Pos)

#define	CAN_F11R2_FB30 CAN_F11R2_FB30_Msk

#define	CAN_F11R2_FB31_Pos (31U)

#define	CAN_F11R2_FB31_Msk (0x1UL << CAN_F11R2_FB31_Pos)

#define	CAN_F11R2_FB31 CAN_F11R2_FB31_Msk

#define	CAN_F12R2_FB0_Pos (0U)

#define	CAN_F12R2_FB0_Msk (0x1UL << CAN_F12R2_FB0_Pos)

#define	CAN_F12R2_FB0 CAN_F12R2_FB0_Msk

#define	CAN_F12R2_FB1_Pos (1U)

#define	CAN_F12R2_FB1_Msk (0x1UL << CAN_F12R2_FB1_Pos)

#define	CAN_F12R2_FB1 CAN_F12R2_FB1_Msk

#define	CAN_F12R2_FB2_Pos (2U)

#define	CAN_F12R2_FB2_Msk (0x1UL << CAN_F12R2_FB2_Pos)

#define	CAN_F12R2_FB2 CAN_F12R2_FB2_Msk

#define	CAN_F12R2_FB3_Pos (3U)

#define	CAN_F12R2_FB3_Msk (0x1UL << CAN_F12R2_FB3_Pos)

#define	CAN_F12R2_FB3 CAN_F12R2_FB3_Msk

#define	CAN_F12R2_FB4_Pos (4U)

#define	CAN_F12R2_FB4_Msk (0x1UL << CAN_F12R2_FB4_Pos)

#define	CAN_F12R2_FB4 CAN_F12R2_FB4_Msk

#define	CAN_F12R2_FB5_Pos (5U)

#define	CAN_F12R2_FB5_Msk (0x1UL << CAN_F12R2_FB5_Pos)

#define	CAN_F12R2_FB5 CAN_F12R2_FB5_Msk

#define	CAN_F12R2_FB6_Pos (6U)

#define	CAN_F12R2_FB6_Msk (0x1UL << CAN_F12R2_FB6_Pos)

#define	CAN_F12R2_FB6 CAN_F12R2_FB6_Msk

#define	CAN_F12R2_FB7_Pos (7U)

#define	CAN_F12R2_FB7_Msk (0x1UL << CAN_F12R2_FB7_Pos)

#define	CAN_F12R2_FB7 CAN_F12R2_FB7_Msk

#define	CAN_F12R2_FB8_Pos (8U)

#define	CAN_F12R2_FB8_Msk (0x1UL << CAN_F12R2_FB8_Pos)

#define	CAN_F12R2_FB8 CAN_F12R2_FB8_Msk

#define	CAN_F12R2_FB9_Pos (9U)

#define	CAN_F12R2_FB9_Msk (0x1UL << CAN_F12R2_FB9_Pos)

#define	CAN_F12R2_FB9 CAN_F12R2_FB9_Msk

#define	CAN_F12R2_FB10_Pos (10U)

#define	CAN_F12R2_FB10_Msk (0x1UL << CAN_F12R2_FB10_Pos)

#define	CAN_F12R2_FB10 CAN_F12R2_FB10_Msk

#define	CAN_F12R2_FB11_Pos (11U)

#define	CAN_F12R2_FB11_Msk (0x1UL << CAN_F12R2_FB11_Pos)

#define	CAN_F12R2_FB11 CAN_F12R2_FB11_Msk

#define	CAN_F12R2_FB12_Pos (12U)

#define	CAN_F12R2_FB12_Msk (0x1UL << CAN_F12R2_FB12_Pos)

#define	CAN_F12R2_FB12 CAN_F12R2_FB12_Msk

#define	CAN_F12R2_FB13_Pos (13U)

#define	CAN_F12R2_FB13_Msk (0x1UL << CAN_F12R2_FB13_Pos)

#define	CAN_F12R2_FB13 CAN_F12R2_FB13_Msk

#define	CAN_F12R2_FB14_Pos (14U)

#define	CAN_F12R2_FB14_Msk (0x1UL << CAN_F12R2_FB14_Pos)

#define	CAN_F12R2_FB14 CAN_F12R2_FB14_Msk

#define	CAN_F12R2_FB15_Pos (15U)

#define	CAN_F12R2_FB15_Msk (0x1UL << CAN_F12R2_FB15_Pos)

#define	CAN_F12R2_FB15 CAN_F12R2_FB15_Msk

#define	CAN_F12R2_FB16_Pos (16U)

#define	CAN_F12R2_FB16_Msk (0x1UL << CAN_F12R2_FB16_Pos)

#define	CAN_F12R2_FB16 CAN_F12R2_FB16_Msk

#define	CAN_F12R2_FB17_Pos (17U)

#define	CAN_F12R2_FB17_Msk (0x1UL << CAN_F12R2_FB17_Pos)

#define	CAN_F12R2_FB17 CAN_F12R2_FB17_Msk

#define	CAN_F12R2_FB18_Pos (18U)

#define	CAN_F12R2_FB18_Msk (0x1UL << CAN_F12R2_FB18_Pos)

#define	CAN_F12R2_FB18 CAN_F12R2_FB18_Msk

#define	CAN_F12R2_FB19_Pos (19U)

#define	CAN_F12R2_FB19_Msk (0x1UL << CAN_F12R2_FB19_Pos)

#define	CAN_F12R2_FB19 CAN_F12R2_FB19_Msk

#define	CAN_F12R2_FB20_Pos (20U)

#define	CAN_F12R2_FB20_Msk (0x1UL << CAN_F12R2_FB20_Pos)

#define	CAN_F12R2_FB20 CAN_F12R2_FB20_Msk

#define	CAN_F12R2_FB21_Pos (21U)

#define	CAN_F12R2_FB21_Msk (0x1UL << CAN_F12R2_FB21_Pos)

#define	CAN_F12R2_FB21 CAN_F12R2_FB21_Msk

#define	CAN_F12R2_FB22_Pos (22U)

#define	CAN_F12R2_FB22_Msk (0x1UL << CAN_F12R2_FB22_Pos)

#define	CAN_F12R2_FB22 CAN_F12R2_FB22_Msk

#define	CAN_F12R2_FB23_Pos (23U)

#define	CAN_F12R2_FB23_Msk (0x1UL << CAN_F12R2_FB23_Pos)

#define	CAN_F12R2_FB23 CAN_F12R2_FB23_Msk

#define	CAN_F12R2_FB24_Pos (24U)

#define	CAN_F12R2_FB24_Msk (0x1UL << CAN_F12R2_FB24_Pos)

#define	CAN_F12R2_FB24 CAN_F12R2_FB24_Msk

#define	CAN_F12R2_FB25_Pos (25U)

#define	CAN_F12R2_FB25_Msk (0x1UL << CAN_F12R2_FB25_Pos)

#define	CAN_F12R2_FB25 CAN_F12R2_FB25_Msk

#define	CAN_F12R2_FB26_Pos (26U)

#define	CAN_F12R2_FB26_Msk (0x1UL << CAN_F12R2_FB26_Pos)

#define	CAN_F12R2_FB26 CAN_F12R2_FB26_Msk

#define	CAN_F12R2_FB27_Pos (27U)

#define	CAN_F12R2_FB27_Msk (0x1UL << CAN_F12R2_FB27_Pos)

#define	CAN_F12R2_FB27 CAN_F12R2_FB27_Msk

#define	CAN_F12R2_FB28_Pos (28U)

#define	CAN_F12R2_FB28_Msk (0x1UL << CAN_F12R2_FB28_Pos)

#define	CAN_F12R2_FB28 CAN_F12R2_FB28_Msk

#define	CAN_F12R2_FB29_Pos (29U)

#define	CAN_F12R2_FB29_Msk (0x1UL << CAN_F12R2_FB29_Pos)

#define	CAN_F12R2_FB29 CAN_F12R2_FB29_Msk

#define	CAN_F12R2_FB30_Pos (30U)

#define	CAN_F12R2_FB30_Msk (0x1UL << CAN_F12R2_FB30_Pos)

#define	CAN_F12R2_FB30 CAN_F12R2_FB30_Msk

#define	CAN_F12R2_FB31_Pos (31U)

#define	CAN_F12R2_FB31_Msk (0x1UL << CAN_F12R2_FB31_Pos)

#define	CAN_F12R2_FB31 CAN_F12R2_FB31_Msk

#define	CAN_F13R2_FB0_Pos (0U)

#define	CAN_F13R2_FB0_Msk (0x1UL << CAN_F13R2_FB0_Pos)

#define	CAN_F13R2_FB0 CAN_F13R2_FB0_Msk

#define	CAN_F13R2_FB1_Pos (1U)

#define	CAN_F13R2_FB1_Msk (0x1UL << CAN_F13R2_FB1_Pos)

#define	CAN_F13R2_FB1 CAN_F13R2_FB1_Msk

#define	CAN_F13R2_FB2_Pos (2U)

#define	CAN_F13R2_FB2_Msk (0x1UL << CAN_F13R2_FB2_Pos)

#define	CAN_F13R2_FB2 CAN_F13R2_FB2_Msk

#define	CAN_F13R2_FB3_Pos (3U)

#define	CAN_F13R2_FB3_Msk (0x1UL << CAN_F13R2_FB3_Pos)

#define	CAN_F13R2_FB3 CAN_F13R2_FB3_Msk

#define	CAN_F13R2_FB4_Pos (4U)

#define	CAN_F13R2_FB4_Msk (0x1UL << CAN_F13R2_FB4_Pos)

#define	CAN_F13R2_FB4 CAN_F13R2_FB4_Msk

#define	CAN_F13R2_FB5_Pos (5U)

#define	CAN_F13R2_FB5_Msk (0x1UL << CAN_F13R2_FB5_Pos)

#define	CAN_F13R2_FB5 CAN_F13R2_FB5_Msk

#define	CAN_F13R2_FB6_Pos (6U)

#define	CAN_F13R2_FB6_Msk (0x1UL << CAN_F13R2_FB6_Pos)

#define	CAN_F13R2_FB6 CAN_F13R2_FB6_Msk

#define	CAN_F13R2_FB7_Pos (7U)

#define	CAN_F13R2_FB7_Msk (0x1UL << CAN_F13R2_FB7_Pos)

#define	CAN_F13R2_FB7 CAN_F13R2_FB7_Msk

#define	CAN_F13R2_FB8_Pos (8U)

#define	CAN_F13R2_FB8_Msk (0x1UL << CAN_F13R2_FB8_Pos)

#define	CAN_F13R2_FB8 CAN_F13R2_FB8_Msk

#define	CAN_F13R2_FB9_Pos (9U)

#define	CAN_F13R2_FB9_Msk (0x1UL << CAN_F13R2_FB9_Pos)

#define	CAN_F13R2_FB9 CAN_F13R2_FB9_Msk

#define	CAN_F13R2_FB10_Pos (10U)

#define	CAN_F13R2_FB10_Msk (0x1UL << CAN_F13R2_FB10_Pos)

#define	CAN_F13R2_FB10 CAN_F13R2_FB10_Msk

#define	CAN_F13R2_FB11_Pos (11U)

#define	CAN_F13R2_FB11_Msk (0x1UL << CAN_F13R2_FB11_Pos)

#define	CAN_F13R2_FB11 CAN_F13R2_FB11_Msk

#define	CAN_F13R2_FB12_Pos (12U)

#define	CAN_F13R2_FB12_Msk (0x1UL << CAN_F13R2_FB12_Pos)

#define	CAN_F13R2_FB12 CAN_F13R2_FB12_Msk

#define	CAN_F13R2_FB13_Pos (13U)

#define	CAN_F13R2_FB13_Msk (0x1UL << CAN_F13R2_FB13_Pos)

#define	CAN_F13R2_FB13 CAN_F13R2_FB13_Msk

#define	CAN_F13R2_FB14_Pos (14U)

#define	CAN_F13R2_FB14_Msk (0x1UL << CAN_F13R2_FB14_Pos)

#define	CAN_F13R2_FB14 CAN_F13R2_FB14_Msk

#define	CAN_F13R2_FB15_Pos (15U)

#define	CAN_F13R2_FB15_Msk (0x1UL << CAN_F13R2_FB15_Pos)

#define	CAN_F13R2_FB15 CAN_F13R2_FB15_Msk

#define	CAN_F13R2_FB16_Pos (16U)

#define	CAN_F13R2_FB16_Msk (0x1UL << CAN_F13R2_FB16_Pos)

#define	CAN_F13R2_FB16 CAN_F13R2_FB16_Msk

#define	CAN_F13R2_FB17_Pos (17U)

#define	CAN_F13R2_FB17_Msk (0x1UL << CAN_F13R2_FB17_Pos)

#define	CAN_F13R2_FB17 CAN_F13R2_FB17_Msk

#define	CAN_F13R2_FB18_Pos (18U)

#define	CAN_F13R2_FB18_Msk (0x1UL << CAN_F13R2_FB18_Pos)

#define	CAN_F13R2_FB18 CAN_F13R2_FB18_Msk

#define	CAN_F13R2_FB19_Pos (19U)

#define	CAN_F13R2_FB19_Msk (0x1UL << CAN_F13R2_FB19_Pos)

#define	CAN_F13R2_FB19 CAN_F13R2_FB19_Msk

#define	CAN_F13R2_FB20_Pos (20U)

#define	CAN_F13R2_FB20_Msk (0x1UL << CAN_F13R2_FB20_Pos)

#define	CAN_F13R2_FB20 CAN_F13R2_FB20_Msk

#define	CAN_F13R2_FB21_Pos (21U)

#define	CAN_F13R2_FB21_Msk (0x1UL << CAN_F13R2_FB21_Pos)

#define	CAN_F13R2_FB21 CAN_F13R2_FB21_Msk

#define	CAN_F13R2_FB22_Pos (22U)

#define	CAN_F13R2_FB22_Msk (0x1UL << CAN_F13R2_FB22_Pos)

#define	CAN_F13R2_FB22 CAN_F13R2_FB22_Msk

#define	CAN_F13R2_FB23_Pos (23U)

#define	CAN_F13R2_FB23_Msk (0x1UL << CAN_F13R2_FB23_Pos)

#define	CAN_F13R2_FB23 CAN_F13R2_FB23_Msk

#define	CAN_F13R2_FB24_Pos (24U)

#define	CAN_F13R2_FB24_Msk (0x1UL << CAN_F13R2_FB24_Pos)

#define	CAN_F13R2_FB24 CAN_F13R2_FB24_Msk

#define	CAN_F13R2_FB25_Pos (25U)

#define	CAN_F13R2_FB25_Msk (0x1UL << CAN_F13R2_FB25_Pos)

#define	CAN_F13R2_FB25 CAN_F13R2_FB25_Msk

#define	CAN_F13R2_FB26_Pos (26U)

#define	CAN_F13R2_FB26_Msk (0x1UL << CAN_F13R2_FB26_Pos)

#define	CAN_F13R2_FB26 CAN_F13R2_FB26_Msk

#define	CAN_F13R2_FB27_Pos (27U)

#define	CAN_F13R2_FB27_Msk (0x1UL << CAN_F13R2_FB27_Pos)

#define	CAN_F13R2_FB27 CAN_F13R2_FB27_Msk

#define	CAN_F13R2_FB28_Pos (28U)

#define	CAN_F13R2_FB28_Msk (0x1UL << CAN_F13R2_FB28_Pos)

#define	CAN_F13R2_FB28 CAN_F13R2_FB28_Msk

#define	CAN_F13R2_FB29_Pos (29U)

#define	CAN_F13R2_FB29_Msk (0x1UL << CAN_F13R2_FB29_Pos)

#define	CAN_F13R2_FB29 CAN_F13R2_FB29_Msk

#define	CAN_F13R2_FB30_Pos (30U)

#define	CAN_F13R2_FB30_Msk (0x1UL << CAN_F13R2_FB30_Pos)

#define	CAN_F13R2_FB30 CAN_F13R2_FB30_Msk

#define	CAN_F13R2_FB31_Pos (31U)

#define	CAN_F13R2_FB31_Msk (0x1UL << CAN_F13R2_FB31_Pos)

#define	CAN_F13R2_FB31 CAN_F13R2_FB31_Msk

#define	CRC_DR_DR_Pos (0U)

#define	CRC_DR_DR_Msk (0xFFFFFFFFUL << CRC_DR_DR_Pos)

#define	CRC_DR_DR CRC_DR_DR_Msk

#define	CRC_IDR_IDR ((uint8_t)0xFFU)

#define	CRC_CR_RESET_Pos (0U)

#define	CRC_CR_RESET_Msk (0x1UL << CRC_CR_RESET_Pos)

#define	CRC_CR_RESET CRC_CR_RESET_Msk

#define	CRC_CR_POLYSIZE_Pos (3U)

#define	CRC_CR_POLYSIZE_Msk (0x3UL << CRC_CR_POLYSIZE_Pos)

#define	CRC_CR_POLYSIZE CRC_CR_POLYSIZE_Msk

#define	CRC_CR_POLYSIZE_0 (0x1UL << CRC_CR_POLYSIZE_Pos)

#define	CRC_CR_POLYSIZE_1 (0x2UL << CRC_CR_POLYSIZE_Pos)

#define	CRC_CR_REV_IN_Pos (5U)

#define	CRC_CR_REV_IN_Msk (0x3UL << CRC_CR_REV_IN_Pos)

#define	CRC_CR_REV_IN CRC_CR_REV_IN_Msk

#define	CRC_CR_REV_IN_0 (0x1UL << CRC_CR_REV_IN_Pos)

#define	CRC_CR_REV_IN_1 (0x2UL << CRC_CR_REV_IN_Pos)

#define	CRC_CR_REV_OUT_Pos (7U)

#define	CRC_CR_REV_OUT_Msk (0x1UL << CRC_CR_REV_OUT_Pos)

#define	CRC_CR_REV_OUT CRC_CR_REV_OUT_Msk

#define	CRC_INIT_INIT_Pos (0U)

#define	CRC_INIT_INIT_Msk (0xFFFFFFFFUL << CRC_INIT_INIT_Pos)

#define	CRC_INIT_INIT CRC_INIT_INIT_Msk

#define	CRC_POL_POL_Pos (0U)

#define	CRC_POL_POL_Msk (0xFFFFFFFFUL << CRC_POL_POL_Pos)

#define	CRC_POL_POL CRC_POL_POL_Msk

#define	DAC_CHANNEL2_SUPPORT

#define	DAC_CR_EN1_Pos (0U)

#define	DAC_CR_EN1_Msk (0x1UL << DAC_CR_EN1_Pos)

#define	DAC_CR_EN1 DAC_CR_EN1_Msk

#define	DAC_CR_BOFF1_Pos (1U)

#define	DAC_CR_BOFF1_Msk (0x1UL << DAC_CR_BOFF1_Pos)

#define	DAC_CR_BOFF1 DAC_CR_BOFF1_Msk

#define	DAC_CR_TEN1_Pos (2U)

#define	DAC_CR_TEN1_Msk (0x1UL << DAC_CR_TEN1_Pos)

#define	DAC_CR_TEN1 DAC_CR_TEN1_Msk

#define	DAC_CR_TSEL1_Pos (3U)

#define	DAC_CR_TSEL1_Msk (0x7UL << DAC_CR_TSEL1_Pos)

#define	DAC_CR_TSEL1 DAC_CR_TSEL1_Msk

#define	DAC_CR_TSEL1_0 (0x1UL << DAC_CR_TSEL1_Pos)

#define	DAC_CR_TSEL1_1 (0x2UL << DAC_CR_TSEL1_Pos)

#define	DAC_CR_TSEL1_2 (0x4UL << DAC_CR_TSEL1_Pos)

#define	DAC_CR_WAVE1_Pos (6U)

#define	DAC_CR_WAVE1_Msk (0x3UL << DAC_CR_WAVE1_Pos)

#define	DAC_CR_WAVE1 DAC_CR_WAVE1_Msk

#define	DAC_CR_WAVE1_0 (0x1UL << DAC_CR_WAVE1_Pos)

#define	DAC_CR_WAVE1_1 (0x2UL << DAC_CR_WAVE1_Pos)

#define	DAC_CR_MAMP1_Pos (8U)

#define	DAC_CR_MAMP1_Msk (0xFUL << DAC_CR_MAMP1_Pos)

#define	DAC_CR_MAMP1 DAC_CR_MAMP1_Msk

#define	DAC_CR_MAMP1_0 (0x1UL << DAC_CR_MAMP1_Pos)

#define	DAC_CR_MAMP1_1 (0x2UL << DAC_CR_MAMP1_Pos)

#define	DAC_CR_MAMP1_2 (0x4UL << DAC_CR_MAMP1_Pos)

#define	DAC_CR_MAMP1_3 (0x8UL << DAC_CR_MAMP1_Pos)

#define	DAC_CR_DMAEN1_Pos (12U)

#define	DAC_CR_DMAEN1_Msk (0x1UL << DAC_CR_DMAEN1_Pos)

#define	DAC_CR_DMAEN1 DAC_CR_DMAEN1_Msk

#define	DAC_CR_DMAUDRIE1_Pos (13U)

#define	DAC_CR_DMAUDRIE1_Msk (0x1UL << DAC_CR_DMAUDRIE1_Pos)

#define	DAC_CR_DMAUDRIE1 DAC_CR_DMAUDRIE1_Msk

#define	DAC_CR_EN2_Pos (16U)

#define	DAC_CR_EN2_Msk (0x1UL << DAC_CR_EN2_Pos)

#define	DAC_CR_EN2 DAC_CR_EN2_Msk

#define	DAC_CR_BOFF2_Pos (17U)

#define	DAC_CR_BOFF2_Msk (0x1UL << DAC_CR_BOFF2_Pos)

#define	DAC_CR_BOFF2 DAC_CR_BOFF2_Msk

#define	DAC_CR_TEN2_Pos (18U)

#define	DAC_CR_TEN2_Msk (0x1UL << DAC_CR_TEN2_Pos)

#define	DAC_CR_TEN2 DAC_CR_TEN2_Msk

#define	DAC_CR_TSEL2_Pos (19U)

#define	DAC_CR_TSEL2_Msk (0x7UL << DAC_CR_TSEL2_Pos)

#define	DAC_CR_TSEL2 DAC_CR_TSEL2_Msk

#define	DAC_CR_TSEL2_0 (0x1UL << DAC_CR_TSEL2_Pos)

#define	DAC_CR_TSEL2_1 (0x2UL << DAC_CR_TSEL2_Pos)

#define	DAC_CR_TSEL2_2 (0x4UL << DAC_CR_TSEL2_Pos)

#define	DAC_CR_WAVE2_Pos (22U)

#define	DAC_CR_WAVE2_Msk (0x3UL << DAC_CR_WAVE2_Pos)

#define	DAC_CR_WAVE2 DAC_CR_WAVE2_Msk

#define	DAC_CR_WAVE2_0 (0x1UL << DAC_CR_WAVE2_Pos)

#define	DAC_CR_WAVE2_1 (0x2UL << DAC_CR_WAVE2_Pos)

#define	DAC_CR_MAMP2_Pos (24U)

#define	DAC_CR_MAMP2_Msk (0xFUL << DAC_CR_MAMP2_Pos)

#define	DAC_CR_MAMP2 DAC_CR_MAMP2_Msk

#define	DAC_CR_MAMP2_0 (0x1UL << DAC_CR_MAMP2_Pos)

#define	DAC_CR_MAMP2_1 (0x2UL << DAC_CR_MAMP2_Pos)

#define	DAC_CR_MAMP2_2 (0x4UL << DAC_CR_MAMP2_Pos)

#define	DAC_CR_MAMP2_3 (0x8UL << DAC_CR_MAMP2_Pos)

#define	DAC_CR_DMAEN2_Pos (28U)

#define	DAC_CR_DMAEN2_Msk (0x1UL << DAC_CR_DMAEN2_Pos)

#define	DAC_CR_DMAEN2 DAC_CR_DMAEN2_Msk

#define	DAC_CR_DMAUDRIE2_Pos (29U)

#define	DAC_CR_DMAUDRIE2_Msk (0x1UL << DAC_CR_DMAUDRIE2_Pos)

#define	DAC_CR_DMAUDRIE2 DAC_CR_DMAUDRIE2_Msk

#define	DAC_SWTRIGR_SWTRIG1_Pos (0U)

#define	DAC_SWTRIGR_SWTRIG1_Msk (0x1UL << DAC_SWTRIGR_SWTRIG1_Pos)

#define	DAC_SWTRIGR_SWTRIG1 DAC_SWTRIGR_SWTRIG1_Msk

#define	DAC_SWTRIGR_SWTRIG2_Pos (1U)

#define	DAC_SWTRIGR_SWTRIG2_Msk (0x1UL << DAC_SWTRIGR_SWTRIG2_Pos)

#define	DAC_SWTRIGR_SWTRIG2 DAC_SWTRIGR_SWTRIG2_Msk

#define	DAC_DHR12R1_DACC1DHR_Pos (0U)

#define	DAC_DHR12R1_DACC1DHR_Msk (0xFFFUL << DAC_DHR12R1_DACC1DHR_Pos)

#define	DAC_DHR12R1_DACC1DHR DAC_DHR12R1_DACC1DHR_Msk

#define	DAC_DHR12L1_DACC1DHR_Pos (4U)

#define	DAC_DHR12L1_DACC1DHR_Msk (0xFFFUL << DAC_DHR12L1_DACC1DHR_Pos)

#define	DAC_DHR12L1_DACC1DHR DAC_DHR12L1_DACC1DHR_Msk

#define	DAC_DHR8R1_DACC1DHR_Pos (0U)

#define	DAC_DHR8R1_DACC1DHR_Msk (0xFFUL << DAC_DHR8R1_DACC1DHR_Pos)

#define	DAC_DHR8R1_DACC1DHR DAC_DHR8R1_DACC1DHR_Msk

#define	DAC_DHR12R2_DACC2DHR_Pos (0U)

#define	DAC_DHR12R2_DACC2DHR_Msk (0xFFFUL << DAC_DHR12R2_DACC2DHR_Pos)

#define	DAC_DHR12R2_DACC2DHR DAC_DHR12R2_DACC2DHR_Msk

#define	DAC_DHR12L2_DACC2DHR_Pos (4U)

#define	DAC_DHR12L2_DACC2DHR_Msk (0xFFFUL << DAC_DHR12L2_DACC2DHR_Pos)

#define	DAC_DHR12L2_DACC2DHR DAC_DHR12L2_DACC2DHR_Msk

#define	DAC_DHR8R2_DACC2DHR_Pos (0U)

#define	DAC_DHR8R2_DACC2DHR_Msk (0xFFUL << DAC_DHR8R2_DACC2DHR_Pos)

#define	DAC_DHR8R2_DACC2DHR DAC_DHR8R2_DACC2DHR_Msk

#define	DAC_DHR12RD_DACC1DHR_Pos (0U)

#define	DAC_DHR12RD_DACC1DHR_Msk (0xFFFUL << DAC_DHR12RD_DACC1DHR_Pos)

#define	DAC_DHR12RD_DACC1DHR DAC_DHR12RD_DACC1DHR_Msk

#define	DAC_DHR12RD_DACC2DHR_Pos (16U)

#define	DAC_DHR12RD_DACC2DHR_Msk (0xFFFUL << DAC_DHR12RD_DACC2DHR_Pos)

#define	DAC_DHR12RD_DACC2DHR DAC_DHR12RD_DACC2DHR_Msk

#define	DAC_DHR12LD_DACC1DHR_Pos (4U)

#define	DAC_DHR12LD_DACC1DHR_Msk (0xFFFUL << DAC_DHR12LD_DACC1DHR_Pos)

#define	DAC_DHR12LD_DACC1DHR DAC_DHR12LD_DACC1DHR_Msk

#define	DAC_DHR12LD_DACC2DHR_Pos (20U)

#define	DAC_DHR12LD_DACC2DHR_Msk (0xFFFUL << DAC_DHR12LD_DACC2DHR_Pos)

#define	DAC_DHR12LD_DACC2DHR DAC_DHR12LD_DACC2DHR_Msk

#define	DAC_DHR8RD_DACC1DHR_Pos (0U)

#define	DAC_DHR8RD_DACC1DHR_Msk (0xFFUL << DAC_DHR8RD_DACC1DHR_Pos)

#define	DAC_DHR8RD_DACC1DHR DAC_DHR8RD_DACC1DHR_Msk

#define	DAC_DHR8RD_DACC2DHR_Pos (8U)

#define	DAC_DHR8RD_DACC2DHR_Msk (0xFFUL << DAC_DHR8RD_DACC2DHR_Pos)

#define	DAC_DHR8RD_DACC2DHR DAC_DHR8RD_DACC2DHR_Msk

#define	DAC_DOR1_DACC1DOR_Pos (0U)

#define	DAC_DOR1_DACC1DOR_Msk (0xFFFUL << DAC_DOR1_DACC1DOR_Pos)

#define	DAC_DOR1_DACC1DOR DAC_DOR1_DACC1DOR_Msk

#define	DAC_DOR2_DACC2DOR_Pos (0U)

#define	DAC_DOR2_DACC2DOR_Msk (0xFFFUL << DAC_DOR2_DACC2DOR_Pos)

#define	DAC_DOR2_DACC2DOR DAC_DOR2_DACC2DOR_Msk

#define	DAC_SR_DMAUDR1_Pos (13U)

#define	DAC_SR_DMAUDR1_Msk (0x1UL << DAC_SR_DMAUDR1_Pos)

#define	DAC_SR_DMAUDR1 DAC_SR_DMAUDR1_Msk

#define	DAC_SR_DMAUDR2_Pos (29U)

#define	DAC_SR_DMAUDR2_Msk (0x1UL << DAC_SR_DMAUDR2_Pos)

#define	DAC_SR_DMAUDR2 DAC_SR_DMAUDR2_Msk

#define	DBGMCU_IDCODE_DEV_ID_Pos (0U)

#define	DBGMCU_IDCODE_DEV_ID_Msk (0xFFFUL << DBGMCU_IDCODE_DEV_ID_Pos)

#define	DBGMCU_IDCODE_DEV_ID DBGMCU_IDCODE_DEV_ID_Msk

#define	DBGMCU_IDCODE_REV_ID_Pos (16U)

#define	DBGMCU_IDCODE_REV_ID_Msk (0xFFFFUL << DBGMCU_IDCODE_REV_ID_Pos)

#define	DBGMCU_IDCODE_REV_ID DBGMCU_IDCODE_REV_ID_Msk

#define	DBGMCU_CR_DBG_SLEEP_Pos (0U)

#define	DBGMCU_CR_DBG_SLEEP_Msk (0x1UL << DBGMCU_CR_DBG_SLEEP_Pos)

#define	DBGMCU_CR_DBG_SLEEP DBGMCU_CR_DBG_SLEEP_Msk

#define	DBGMCU_CR_DBG_STOP_Pos (1U)

#define	DBGMCU_CR_DBG_STOP_Msk (0x1UL << DBGMCU_CR_DBG_STOP_Pos)

#define	DBGMCU_CR_DBG_STOP DBGMCU_CR_DBG_STOP_Msk

#define	DBGMCU_CR_DBG_STANDBY_Pos (2U)

#define	DBGMCU_CR_DBG_STANDBY_Msk (0x1UL << DBGMCU_CR_DBG_STANDBY_Pos)

#define	DBGMCU_CR_DBG_STANDBY DBGMCU_CR_DBG_STANDBY_Msk

#define	DBGMCU_CR_TRACE_IOEN_Pos (5U)

#define	DBGMCU_CR_TRACE_IOEN_Msk (0x1UL << DBGMCU_CR_TRACE_IOEN_Pos)

#define	DBGMCU_CR_TRACE_IOEN DBGMCU_CR_TRACE_IOEN_Msk

#define	DBGMCU_CR_TRACE_MODE_Pos (6U)

#define	DBGMCU_CR_TRACE_MODE_Msk (0x3UL << DBGMCU_CR_TRACE_MODE_Pos)

#define	DBGMCU_CR_TRACE_MODE DBGMCU_CR_TRACE_MODE_Msk

#define	DBGMCU_CR_TRACE_MODE_0 (0x1UL << DBGMCU_CR_TRACE_MODE_Pos)

#define	DBGMCU_CR_TRACE_MODE_1 (0x2UL << DBGMCU_CR_TRACE_MODE_Pos)

#define	DBGMCU_APB1_FZ_DBG_TIM2_STOP_Pos (0U)

#define	DBGMCU_APB1_FZ_DBG_TIM2_STOP_Msk (0x1UL << DBGMCU_APB1_FZ_DBG_TIM2_STOP_Pos)

#define	DBGMCU_APB1_FZ_DBG_TIM2_STOP DBGMCU_APB1_FZ_DBG_TIM2_STOP_Msk

#define	DBGMCU_APB1_FZ_DBG_TIM3_STOP_Pos (1U)

#define	DBGMCU_APB1_FZ_DBG_TIM3_STOP_Msk (0x1UL << DBGMCU_APB1_FZ_DBG_TIM3_STOP_Pos)

#define	DBGMCU_APB1_FZ_DBG_TIM3_STOP DBGMCU_APB1_FZ_DBG_TIM3_STOP_Msk

#define	DBGMCU_APB1_FZ_DBG_TIM4_STOP_Pos (2U)

#define	DBGMCU_APB1_FZ_DBG_TIM4_STOP_Msk (0x1UL << DBGMCU_APB1_FZ_DBG_TIM4_STOP_Pos)

#define	DBGMCU_APB1_FZ_DBG_TIM4_STOP DBGMCU_APB1_FZ_DBG_TIM4_STOP_Msk

#define	DBGMCU_APB1_FZ_DBG_TIM6_STOP_Pos (4U)

#define	DBGMCU_APB1_FZ_DBG_TIM6_STOP_Msk (0x1UL << DBGMCU_APB1_FZ_DBG_TIM6_STOP_Pos)

#define	DBGMCU_APB1_FZ_DBG_TIM6_STOP DBGMCU_APB1_FZ_DBG_TIM6_STOP_Msk

#define	DBGMCU_APB1_FZ_DBG_TIM7_STOP_Pos (5U)

#define	DBGMCU_APB1_FZ_DBG_TIM7_STOP_Msk (0x1UL << DBGMCU_APB1_FZ_DBG_TIM7_STOP_Pos)

#define	DBGMCU_APB1_FZ_DBG_TIM7_STOP DBGMCU_APB1_FZ_DBG_TIM7_STOP_Msk

#define	DBGMCU_APB1_FZ_DBG_RTC_STOP_Pos (10U)

#define	DBGMCU_APB1_FZ_DBG_RTC_STOP_Msk (0x1UL << DBGMCU_APB1_FZ_DBG_RTC_STOP_Pos)

#define	DBGMCU_APB1_FZ_DBG_RTC_STOP DBGMCU_APB1_FZ_DBG_RTC_STOP_Msk

#define	DBGMCU_APB1_FZ_DBG_WWDG_STOP_Pos (11U)

#define	DBGMCU_APB1_FZ_DBG_WWDG_STOP_Msk (0x1UL << DBGMCU_APB1_FZ_DBG_WWDG_STOP_Pos)

#define	DBGMCU_APB1_FZ_DBG_WWDG_STOP DBGMCU_APB1_FZ_DBG_WWDG_STOP_Msk

#define	DBGMCU_APB1_FZ_DBG_IWDG_STOP_Pos (12U)

#define	DBGMCU_APB1_FZ_DBG_IWDG_STOP_Msk (0x1UL << DBGMCU_APB1_FZ_DBG_IWDG_STOP_Pos)

#define	DBGMCU_APB1_FZ_DBG_IWDG_STOP DBGMCU_APB1_FZ_DBG_IWDG_STOP_Msk

#define	DBGMCU_APB1_FZ_DBG_I2C1_SMBUS_TIMEOUT_Pos (21U)

#define	DBGMCU_APB1_FZ_DBG_I2C1_SMBUS_TIMEOUT_Msk (0x1UL << DBGMCU_APB1_FZ_DBG_I2C1_SMBUS_TIMEOUT_Pos)

#define	DBGMCU_APB1_FZ_DBG_I2C1_SMBUS_TIMEOUT DBGMCU_APB1_FZ_DBG_I2C1_SMBUS_TIMEOUT_Msk

#define	DBGMCU_APB1_FZ_DBG_I2C2_SMBUS_TIMEOUT_Pos (22U)

#define	DBGMCU_APB1_FZ_DBG_I2C2_SMBUS_TIMEOUT_Msk (0x1UL << DBGMCU_APB1_FZ_DBG_I2C2_SMBUS_TIMEOUT_Pos)

#define	DBGMCU_APB1_FZ_DBG_I2C2_SMBUS_TIMEOUT DBGMCU_APB1_FZ_DBG_I2C2_SMBUS_TIMEOUT_Msk

#define	DBGMCU_APB1_FZ_DBG_I2C3_SMBUS_TIMEOUT_Pos (30U)

#define	DBGMCU_APB1_FZ_DBG_I2C3_SMBUS_TIMEOUT_Msk (0x1UL << DBGMCU_APB1_FZ_DBG_I2C3_SMBUS_TIMEOUT_Pos)

#define	DBGMCU_APB1_FZ_DBG_I2C3_SMBUS_TIMEOUT DBGMCU_APB1_FZ_DBG_I2C3_SMBUS_TIMEOUT_Msk

#define	DBGMCU_APB1_FZ_DBG_CAN_STOP_Pos (25U)

#define	DBGMCU_APB1_FZ_DBG_CAN_STOP_Msk (0x1UL << DBGMCU_APB1_FZ_DBG_CAN_STOP_Pos)

#define	DBGMCU_APB1_FZ_DBG_CAN_STOP DBGMCU_APB1_FZ_DBG_CAN_STOP_Msk

#define	DBGMCU_APB2_FZ_DBG_TIM1_STOP_Pos (0U)

#define	DBGMCU_APB2_FZ_DBG_TIM1_STOP_Msk (0x1UL << DBGMCU_APB2_FZ_DBG_TIM1_STOP_Pos)

#define	DBGMCU_APB2_FZ_DBG_TIM1_STOP DBGMCU_APB2_FZ_DBG_TIM1_STOP_Msk

#define	DBGMCU_APB2_FZ_DBG_TIM8_STOP_Pos (1U)

#define	DBGMCU_APB2_FZ_DBG_TIM8_STOP_Msk (0x1UL << DBGMCU_APB2_FZ_DBG_TIM8_STOP_Pos)

#define	DBGMCU_APB2_FZ_DBG_TIM8_STOP DBGMCU_APB2_FZ_DBG_TIM8_STOP_Msk

#define	DBGMCU_APB2_FZ_DBG_TIM15_STOP_Pos (2U)

#define	DBGMCU_APB2_FZ_DBG_TIM15_STOP_Msk (0x1UL << DBGMCU_APB2_FZ_DBG_TIM15_STOP_Pos)

#define	DBGMCU_APB2_FZ_DBG_TIM15_STOP DBGMCU_APB2_FZ_DBG_TIM15_STOP_Msk

#define	DBGMCU_APB2_FZ_DBG_TIM16_STOP_Pos (3U)

#define	DBGMCU_APB2_FZ_DBG_TIM16_STOP_Msk (0x1UL << DBGMCU_APB2_FZ_DBG_TIM16_STOP_Pos)

#define	DBGMCU_APB2_FZ_DBG_TIM16_STOP DBGMCU_APB2_FZ_DBG_TIM16_STOP_Msk

#define	DBGMCU_APB2_FZ_DBG_TIM17_STOP_Pos (4U)

#define	DBGMCU_APB2_FZ_DBG_TIM17_STOP_Msk (0x1UL << DBGMCU_APB2_FZ_DBG_TIM17_STOP_Pos)

#define	DBGMCU_APB2_FZ_DBG_TIM17_STOP DBGMCU_APB2_FZ_DBG_TIM17_STOP_Msk

#define	DBGMCU_APB2_FZ_DBG_TIM20_STOP_Pos (5U)

#define	DBGMCU_APB2_FZ_DBG_TIM20_STOP_Msk (0x1UL << DBGMCU_APB2_FZ_DBG_TIM20_STOP_Pos)

#define	DBGMCU_APB2_FZ_DBG_TIM20_STOP DBGMCU_APB2_FZ_DBG_TIM20_STOP_Msk

#define	DMA_ISR_GIF1_Pos (0U)

#define	DMA_ISR_GIF1_Msk (0x1UL << DMA_ISR_GIF1_Pos)

#define	DMA_ISR_GIF1 DMA_ISR_GIF1_Msk

#define	DMA_ISR_TCIF1_Pos (1U)

#define	DMA_ISR_TCIF1_Msk (0x1UL << DMA_ISR_TCIF1_Pos)

#define	DMA_ISR_TCIF1 DMA_ISR_TCIF1_Msk

#define	DMA_ISR_HTIF1_Pos (2U)

#define	DMA_ISR_HTIF1_Msk (0x1UL << DMA_ISR_HTIF1_Pos)

#define	DMA_ISR_HTIF1 DMA_ISR_HTIF1_Msk

#define	DMA_ISR_TEIF1_Pos (3U)

#define	DMA_ISR_TEIF1_Msk (0x1UL << DMA_ISR_TEIF1_Pos)

#define	DMA_ISR_TEIF1 DMA_ISR_TEIF1_Msk

#define	DMA_ISR_GIF2_Pos (4U)

#define	DMA_ISR_GIF2_Msk (0x1UL << DMA_ISR_GIF2_Pos)

#define	DMA_ISR_GIF2 DMA_ISR_GIF2_Msk

#define	DMA_ISR_TCIF2_Pos (5U)

#define	DMA_ISR_TCIF2_Msk (0x1UL << DMA_ISR_TCIF2_Pos)

#define	DMA_ISR_TCIF2 DMA_ISR_TCIF2_Msk

#define	DMA_ISR_HTIF2_Pos (6U)

#define	DMA_ISR_HTIF2_Msk (0x1UL << DMA_ISR_HTIF2_Pos)

#define	DMA_ISR_HTIF2 DMA_ISR_HTIF2_Msk

#define	DMA_ISR_TEIF2_Pos (7U)

#define	DMA_ISR_TEIF2_Msk (0x1UL << DMA_ISR_TEIF2_Pos)

#define	DMA_ISR_TEIF2 DMA_ISR_TEIF2_Msk

#define	DMA_ISR_GIF3_Pos (8U)

#define	DMA_ISR_GIF3_Msk (0x1UL << DMA_ISR_GIF3_Pos)

#define	DMA_ISR_GIF3 DMA_ISR_GIF3_Msk

#define	DMA_ISR_TCIF3_Pos (9U)

#define	DMA_ISR_TCIF3_Msk (0x1UL << DMA_ISR_TCIF3_Pos)

#define	DMA_ISR_TCIF3 DMA_ISR_TCIF3_Msk

#define	DMA_ISR_HTIF3_Pos (10U)

#define	DMA_ISR_HTIF3_Msk (0x1UL << DMA_ISR_HTIF3_Pos)

#define	DMA_ISR_HTIF3 DMA_ISR_HTIF3_Msk

#define	DMA_ISR_TEIF3_Pos (11U)

#define	DMA_ISR_TEIF3_Msk (0x1UL << DMA_ISR_TEIF3_Pos)

#define	DMA_ISR_TEIF3 DMA_ISR_TEIF3_Msk

#define	DMA_ISR_GIF4_Pos (12U)

#define	DMA_ISR_GIF4_Msk (0x1UL << DMA_ISR_GIF4_Pos)

#define	DMA_ISR_GIF4 DMA_ISR_GIF4_Msk

#define	DMA_ISR_TCIF4_Pos (13U)

#define	DMA_ISR_TCIF4_Msk (0x1UL << DMA_ISR_TCIF4_Pos)

#define	DMA_ISR_TCIF4 DMA_ISR_TCIF4_Msk

#define	DMA_ISR_HTIF4_Pos (14U)

#define	DMA_ISR_HTIF4_Msk (0x1UL << DMA_ISR_HTIF4_Pos)

#define	DMA_ISR_HTIF4 DMA_ISR_HTIF4_Msk

#define	DMA_ISR_TEIF4_Pos (15U)

#define	DMA_ISR_TEIF4_Msk (0x1UL << DMA_ISR_TEIF4_Pos)

#define	DMA_ISR_TEIF4 DMA_ISR_TEIF4_Msk

#define	DMA_ISR_GIF5_Pos (16U)

#define	DMA_ISR_GIF5_Msk (0x1UL << DMA_ISR_GIF5_Pos)

#define	DMA_ISR_GIF5 DMA_ISR_GIF5_Msk

#define	DMA_ISR_TCIF5_Pos (17U)

#define	DMA_ISR_TCIF5_Msk (0x1UL << DMA_ISR_TCIF5_Pos)

#define	DMA_ISR_TCIF5 DMA_ISR_TCIF5_Msk

#define	DMA_ISR_HTIF5_Pos (18U)

#define	DMA_ISR_HTIF5_Msk (0x1UL << DMA_ISR_HTIF5_Pos)

#define	DMA_ISR_HTIF5 DMA_ISR_HTIF5_Msk

#define	DMA_ISR_TEIF5_Pos (19U)

#define	DMA_ISR_TEIF5_Msk (0x1UL << DMA_ISR_TEIF5_Pos)

#define	DMA_ISR_TEIF5 DMA_ISR_TEIF5_Msk

#define	DMA_ISR_GIF6_Pos (20U)

#define	DMA_ISR_GIF6_Msk (0x1UL << DMA_ISR_GIF6_Pos)

#define	DMA_ISR_GIF6 DMA_ISR_GIF6_Msk

#define	DMA_ISR_TCIF6_Pos (21U)

#define	DMA_ISR_TCIF6_Msk (0x1UL << DMA_ISR_TCIF6_Pos)

#define	DMA_ISR_TCIF6 DMA_ISR_TCIF6_Msk

#define	DMA_ISR_HTIF6_Pos (22U)

#define	DMA_ISR_HTIF6_Msk (0x1UL << DMA_ISR_HTIF6_Pos)

#define	DMA_ISR_HTIF6 DMA_ISR_HTIF6_Msk

#define	DMA_ISR_TEIF6_Pos (23U)

#define	DMA_ISR_TEIF6_Msk (0x1UL << DMA_ISR_TEIF6_Pos)

#define	DMA_ISR_TEIF6 DMA_ISR_TEIF6_Msk

#define	DMA_ISR_GIF7_Pos (24U)

#define	DMA_ISR_GIF7_Msk (0x1UL << DMA_ISR_GIF7_Pos)

#define	DMA_ISR_GIF7 DMA_ISR_GIF7_Msk

#define	DMA_ISR_TCIF7_Pos (25U)

#define	DMA_ISR_TCIF7_Msk (0x1UL << DMA_ISR_TCIF7_Pos)

#define	DMA_ISR_TCIF7 DMA_ISR_TCIF7_Msk

#define	DMA_ISR_HTIF7_Pos (26U)

#define	DMA_ISR_HTIF7_Msk (0x1UL << DMA_ISR_HTIF7_Pos)

#define	DMA_ISR_HTIF7 DMA_ISR_HTIF7_Msk

#define	DMA_ISR_TEIF7_Pos (27U)

#define	DMA_ISR_TEIF7_Msk (0x1UL << DMA_ISR_TEIF7_Pos)

#define	DMA_ISR_TEIF7 DMA_ISR_TEIF7_Msk

#define	DMA_IFCR_CGIF1_Pos (0U)

#define	DMA_IFCR_CGIF1_Msk (0x1UL << DMA_IFCR_CGIF1_Pos)

#define	DMA_IFCR_CGIF1 DMA_IFCR_CGIF1_Msk

#define	DMA_IFCR_CTCIF1_Pos (1U)

#define	DMA_IFCR_CTCIF1_Msk (0x1UL << DMA_IFCR_CTCIF1_Pos)

#define	DMA_IFCR_CTCIF1 DMA_IFCR_CTCIF1_Msk

#define	DMA_IFCR_CHTIF1_Pos (2U)

#define	DMA_IFCR_CHTIF1_Msk (0x1UL << DMA_IFCR_CHTIF1_Pos)

#define	DMA_IFCR_CHTIF1 DMA_IFCR_CHTIF1_Msk

#define	DMA_IFCR_CTEIF1_Pos (3U)

#define	DMA_IFCR_CTEIF1_Msk (0x1UL << DMA_IFCR_CTEIF1_Pos)

#define	DMA_IFCR_CTEIF1 DMA_IFCR_CTEIF1_Msk

#define	DMA_IFCR_CGIF2_Pos (4U)

#define	DMA_IFCR_CGIF2_Msk (0x1UL << DMA_IFCR_CGIF2_Pos)

#define	DMA_IFCR_CGIF2 DMA_IFCR_CGIF2_Msk

#define	DMA_IFCR_CTCIF2_Pos (5U)

#define	DMA_IFCR_CTCIF2_Msk (0x1UL << DMA_IFCR_CTCIF2_Pos)

#define	DMA_IFCR_CTCIF2 DMA_IFCR_CTCIF2_Msk

#define	DMA_IFCR_CHTIF2_Pos (6U)

#define	DMA_IFCR_CHTIF2_Msk (0x1UL << DMA_IFCR_CHTIF2_Pos)

#define	DMA_IFCR_CHTIF2 DMA_IFCR_CHTIF2_Msk

#define	DMA_IFCR_CTEIF2_Pos (7U)

#define	DMA_IFCR_CTEIF2_Msk (0x1UL << DMA_IFCR_CTEIF2_Pos)

#define	DMA_IFCR_CTEIF2 DMA_IFCR_CTEIF2_Msk

#define	DMA_IFCR_CGIF3_Pos (8U)

#define	DMA_IFCR_CGIF3_Msk (0x1UL << DMA_IFCR_CGIF3_Pos)

#define	DMA_IFCR_CGIF3 DMA_IFCR_CGIF3_Msk

#define	DMA_IFCR_CTCIF3_Pos (9U)

#define	DMA_IFCR_CTCIF3_Msk (0x1UL << DMA_IFCR_CTCIF3_Pos)

#define	DMA_IFCR_CTCIF3 DMA_IFCR_CTCIF3_Msk

#define	DMA_IFCR_CHTIF3_Pos (10U)

#define	DMA_IFCR_CHTIF3_Msk (0x1UL << DMA_IFCR_CHTIF3_Pos)

#define	DMA_IFCR_CHTIF3 DMA_IFCR_CHTIF3_Msk

#define	DMA_IFCR_CTEIF3_Pos (11U)

#define	DMA_IFCR_CTEIF3_Msk (0x1UL << DMA_IFCR_CTEIF3_Pos)

#define	DMA_IFCR_CTEIF3 DMA_IFCR_CTEIF3_Msk

#define	DMA_IFCR_CGIF4_Pos (12U)

#define	DMA_IFCR_CGIF4_Msk (0x1UL << DMA_IFCR_CGIF4_Pos)

#define	DMA_IFCR_CGIF4 DMA_IFCR_CGIF4_Msk

#define	DMA_IFCR_CTCIF4_Pos (13U)

#define	DMA_IFCR_CTCIF4_Msk (0x1UL << DMA_IFCR_CTCIF4_Pos)

#define	DMA_IFCR_CTCIF4 DMA_IFCR_CTCIF4_Msk

#define	DMA_IFCR_CHTIF4_Pos (14U)

#define	DMA_IFCR_CHTIF4_Msk (0x1UL << DMA_IFCR_CHTIF4_Pos)

#define	DMA_IFCR_CHTIF4 DMA_IFCR_CHTIF4_Msk

#define	DMA_IFCR_CTEIF4_Pos (15U)

#define	DMA_IFCR_CTEIF4_Msk (0x1UL << DMA_IFCR_CTEIF4_Pos)

#define	DMA_IFCR_CTEIF4 DMA_IFCR_CTEIF4_Msk

#define	DMA_IFCR_CGIF5_Pos (16U)

#define	DMA_IFCR_CGIF5_Msk (0x1UL << DMA_IFCR_CGIF5_Pos)

#define	DMA_IFCR_CGIF5 DMA_IFCR_CGIF5_Msk

#define	DMA_IFCR_CTCIF5_Pos (17U)

#define	DMA_IFCR_CTCIF5_Msk (0x1UL << DMA_IFCR_CTCIF5_Pos)

#define	DMA_IFCR_CTCIF5 DMA_IFCR_CTCIF5_Msk

#define	DMA_IFCR_CHTIF5_Pos (18U)

#define	DMA_IFCR_CHTIF5_Msk (0x1UL << DMA_IFCR_CHTIF5_Pos)

#define	DMA_IFCR_CHTIF5 DMA_IFCR_CHTIF5_Msk

#define	DMA_IFCR_CTEIF5_Pos (19U)

#define	DMA_IFCR_CTEIF5_Msk (0x1UL << DMA_IFCR_CTEIF5_Pos)

#define	DMA_IFCR_CTEIF5 DMA_IFCR_CTEIF5_Msk

#define	DMA_IFCR_CGIF6_Pos (20U)

#define	DMA_IFCR_CGIF6_Msk (0x1UL << DMA_IFCR_CGIF6_Pos)

#define	DMA_IFCR_CGIF6 DMA_IFCR_CGIF6_Msk

#define	DMA_IFCR_CTCIF6_Pos (21U)

#define	DMA_IFCR_CTCIF6_Msk (0x1UL << DMA_IFCR_CTCIF6_Pos)

#define	DMA_IFCR_CTCIF6 DMA_IFCR_CTCIF6_Msk

#define	DMA_IFCR_CHTIF6_Pos (22U)

#define	DMA_IFCR_CHTIF6_Msk (0x1UL << DMA_IFCR_CHTIF6_Pos)

#define	DMA_IFCR_CHTIF6 DMA_IFCR_CHTIF6_Msk

#define	DMA_IFCR_CTEIF6_Pos (23U)

#define	DMA_IFCR_CTEIF6_Msk (0x1UL << DMA_IFCR_CTEIF6_Pos)

#define	DMA_IFCR_CTEIF6 DMA_IFCR_CTEIF6_Msk

#define	DMA_IFCR_CGIF7_Pos (24U)

#define	DMA_IFCR_CGIF7_Msk (0x1UL << DMA_IFCR_CGIF7_Pos)

#define	DMA_IFCR_CGIF7 DMA_IFCR_CGIF7_Msk

#define	DMA_IFCR_CTCIF7_Pos (25U)

#define	DMA_IFCR_CTCIF7_Msk (0x1UL << DMA_IFCR_CTCIF7_Pos)

#define	DMA_IFCR_CTCIF7 DMA_IFCR_CTCIF7_Msk

#define	DMA_IFCR_CHTIF7_Pos (26U)

#define	DMA_IFCR_CHTIF7_Msk (0x1UL << DMA_IFCR_CHTIF7_Pos)

#define	DMA_IFCR_CHTIF7 DMA_IFCR_CHTIF7_Msk

#define	DMA_IFCR_CTEIF7_Pos (27U)

#define	DMA_IFCR_CTEIF7_Msk (0x1UL << DMA_IFCR_CTEIF7_Pos)

#define	DMA_IFCR_CTEIF7 DMA_IFCR_CTEIF7_Msk

#define	DMA_CCR_EN_Pos (0U)

#define	DMA_CCR_EN_Msk (0x1UL << DMA_CCR_EN_Pos)

#define	DMA_CCR_EN DMA_CCR_EN_Msk

#define	DMA_CCR_TCIE_Pos (1U)

#define	DMA_CCR_TCIE_Msk (0x1UL << DMA_CCR_TCIE_Pos)

#define	DMA_CCR_TCIE DMA_CCR_TCIE_Msk

#define	DMA_CCR_HTIE_Pos (2U)

#define	DMA_CCR_HTIE_Msk (0x1UL << DMA_CCR_HTIE_Pos)

#define	DMA_CCR_HTIE DMA_CCR_HTIE_Msk

#define	DMA_CCR_TEIE_Pos (3U)

#define	DMA_CCR_TEIE_Msk (0x1UL << DMA_CCR_TEIE_Pos)

#define	DMA_CCR_TEIE DMA_CCR_TEIE_Msk

#define	DMA_CCR_DIR_Pos (4U)

#define	DMA_CCR_DIR_Msk (0x1UL << DMA_CCR_DIR_Pos)

#define	DMA_CCR_DIR DMA_CCR_DIR_Msk

#define	DMA_CCR_CIRC_Pos (5U)

#define	DMA_CCR_CIRC_Msk (0x1UL << DMA_CCR_CIRC_Pos)

#define	DMA_CCR_CIRC DMA_CCR_CIRC_Msk

#define	DMA_CCR_PINC_Pos (6U)

#define	DMA_CCR_PINC_Msk (0x1UL << DMA_CCR_PINC_Pos)

#define	DMA_CCR_PINC DMA_CCR_PINC_Msk

#define	DMA_CCR_MINC_Pos (7U)

#define	DMA_CCR_MINC_Msk (0x1UL << DMA_CCR_MINC_Pos)

#define	DMA_CCR_MINC DMA_CCR_MINC_Msk

#define	DMA_CCR_PSIZE_Pos (8U)

#define	DMA_CCR_PSIZE_Msk (0x3UL << DMA_CCR_PSIZE_Pos)

#define	DMA_CCR_PSIZE DMA_CCR_PSIZE_Msk

#define	DMA_CCR_PSIZE_0 (0x1UL << DMA_CCR_PSIZE_Pos)

#define	DMA_CCR_PSIZE_1 (0x2UL << DMA_CCR_PSIZE_Pos)

#define	DMA_CCR_MSIZE_Pos (10U)

#define	DMA_CCR_MSIZE_Msk (0x3UL << DMA_CCR_MSIZE_Pos)

#define	DMA_CCR_MSIZE DMA_CCR_MSIZE_Msk

#define	DMA_CCR_MSIZE_0 (0x1UL << DMA_CCR_MSIZE_Pos)

#define	DMA_CCR_MSIZE_1 (0x2UL << DMA_CCR_MSIZE_Pos)

#define	DMA_CCR_PL_Pos (12U)

#define	DMA_CCR_PL_Msk (0x3UL << DMA_CCR_PL_Pos)

#define	DMA_CCR_PL DMA_CCR_PL_Msk

#define	DMA_CCR_PL_0 (0x1UL << DMA_CCR_PL_Pos)

#define	DMA_CCR_PL_1 (0x2UL << DMA_CCR_PL_Pos)

#define	DMA_CCR_MEM2MEM_Pos (14U)

#define	DMA_CCR_MEM2MEM_Msk (0x1UL << DMA_CCR_MEM2MEM_Pos)

#define	DMA_CCR_MEM2MEM DMA_CCR_MEM2MEM_Msk

#define	DMA_CNDTR_NDT_Pos (0U)

#define	DMA_CNDTR_NDT_Msk (0xFFFFUL << DMA_CNDTR_NDT_Pos)

#define	DMA_CNDTR_NDT DMA_CNDTR_NDT_Msk

#define	DMA_CPAR_PA_Pos (0U)

#define	DMA_CPAR_PA_Msk (0xFFFFFFFFUL << DMA_CPAR_PA_Pos)

#define	DMA_CPAR_PA DMA_CPAR_PA_Msk

#define	DMA_CMAR_MA_Pos (0U)

#define	DMA_CMAR_MA_Msk (0xFFFFFFFFUL << DMA_CMAR_MA_Pos)

#define	DMA_CMAR_MA DMA_CMAR_MA_Msk

#define	EXTI_IMR_MR0_Pos (0U)

#define	EXTI_IMR_MR0_Msk (0x1UL << EXTI_IMR_MR0_Pos)

#define	EXTI_IMR_MR0 EXTI_IMR_MR0_Msk

#define	EXTI_IMR_MR1_Pos (1U)

#define	EXTI_IMR_MR1_Msk (0x1UL << EXTI_IMR_MR1_Pos)

#define	EXTI_IMR_MR1 EXTI_IMR_MR1_Msk

#define	EXTI_IMR_MR2_Pos (2U)

#define	EXTI_IMR_MR2_Msk (0x1UL << EXTI_IMR_MR2_Pos)

#define	EXTI_IMR_MR2 EXTI_IMR_MR2_Msk

#define	EXTI_IMR_MR3_Pos (3U)

#define	EXTI_IMR_MR3_Msk (0x1UL << EXTI_IMR_MR3_Pos)

#define	EXTI_IMR_MR3 EXTI_IMR_MR3_Msk

#define	EXTI_IMR_MR4_Pos (4U)

#define	EXTI_IMR_MR4_Msk (0x1UL << EXTI_IMR_MR4_Pos)

#define	EXTI_IMR_MR4 EXTI_IMR_MR4_Msk

#define	EXTI_IMR_MR5_Pos (5U)

#define	EXTI_IMR_MR5_Msk (0x1UL << EXTI_IMR_MR5_Pos)

#define	EXTI_IMR_MR5 EXTI_IMR_MR5_Msk

#define	EXTI_IMR_MR6_Pos (6U)

#define	EXTI_IMR_MR6_Msk (0x1UL << EXTI_IMR_MR6_Pos)

#define	EXTI_IMR_MR6 EXTI_IMR_MR6_Msk

#define	EXTI_IMR_MR7_Pos (7U)

#define	EXTI_IMR_MR7_Msk (0x1UL << EXTI_IMR_MR7_Pos)

#define	EXTI_IMR_MR7 EXTI_IMR_MR7_Msk

#define	EXTI_IMR_MR8_Pos (8U)

#define	EXTI_IMR_MR8_Msk (0x1UL << EXTI_IMR_MR8_Pos)

#define	EXTI_IMR_MR8 EXTI_IMR_MR8_Msk

#define	EXTI_IMR_MR9_Pos (9U)

#define	EXTI_IMR_MR9_Msk (0x1UL << EXTI_IMR_MR9_Pos)

#define	EXTI_IMR_MR9 EXTI_IMR_MR9_Msk

#define	EXTI_IMR_MR10_Pos (10U)

#define	EXTI_IMR_MR10_Msk (0x1UL << EXTI_IMR_MR10_Pos)

#define	EXTI_IMR_MR10 EXTI_IMR_MR10_Msk

#define	EXTI_IMR_MR11_Pos (11U)

#define	EXTI_IMR_MR11_Msk (0x1UL << EXTI_IMR_MR11_Pos)

#define	EXTI_IMR_MR11 EXTI_IMR_MR11_Msk

#define	EXTI_IMR_MR12_Pos (12U)

#define	EXTI_IMR_MR12_Msk (0x1UL << EXTI_IMR_MR12_Pos)

#define	EXTI_IMR_MR12 EXTI_IMR_MR12_Msk

#define	EXTI_IMR_MR13_Pos (13U)

#define	EXTI_IMR_MR13_Msk (0x1UL << EXTI_IMR_MR13_Pos)

#define	EXTI_IMR_MR13 EXTI_IMR_MR13_Msk

#define	EXTI_IMR_MR14_Pos (14U)

#define	EXTI_IMR_MR14_Msk (0x1UL << EXTI_IMR_MR14_Pos)

#define	EXTI_IMR_MR14 EXTI_IMR_MR14_Msk

#define	EXTI_IMR_MR15_Pos (15U)

#define	EXTI_IMR_MR15_Msk (0x1UL << EXTI_IMR_MR15_Pos)

#define	EXTI_IMR_MR15 EXTI_IMR_MR15_Msk

#define	EXTI_IMR_MR16_Pos (16U)

#define	EXTI_IMR_MR16_Msk (0x1UL << EXTI_IMR_MR16_Pos)

#define	EXTI_IMR_MR16 EXTI_IMR_MR16_Msk

#define	EXTI_IMR_MR17_Pos (17U)

#define	EXTI_IMR_MR17_Msk (0x1UL << EXTI_IMR_MR17_Pos)

#define	EXTI_IMR_MR17 EXTI_IMR_MR17_Msk

#define	EXTI_IMR_MR18_Pos (18U)

#define	EXTI_IMR_MR18_Msk (0x1UL << EXTI_IMR_MR18_Pos)

#define	EXTI_IMR_MR18 EXTI_IMR_MR18_Msk

#define	EXTI_IMR_MR19_Pos (19U)

#define	EXTI_IMR_MR19_Msk (0x1UL << EXTI_IMR_MR19_Pos)

#define	EXTI_IMR_MR19 EXTI_IMR_MR19_Msk

#define	EXTI_IMR_MR20_Pos (20U)

#define	EXTI_IMR_MR20_Msk (0x1UL << EXTI_IMR_MR20_Pos)

#define	EXTI_IMR_MR20 EXTI_IMR_MR20_Msk

#define	EXTI_IMR_MR21_Pos (21U)

#define	EXTI_IMR_MR21_Msk (0x1UL << EXTI_IMR_MR21_Pos)

#define	EXTI_IMR_MR21 EXTI_IMR_MR21_Msk

#define	EXTI_IMR_MR22_Pos (22U)

#define	EXTI_IMR_MR22_Msk (0x1UL << EXTI_IMR_MR22_Pos)

#define	EXTI_IMR_MR22 EXTI_IMR_MR22_Msk

#define	EXTI_IMR_MR23_Pos (23U)

#define	EXTI_IMR_MR23_Msk (0x1UL << EXTI_IMR_MR23_Pos)

#define	EXTI_IMR_MR23 EXTI_IMR_MR23_Msk

#define	EXTI_IMR_MR24_Pos (24U)

#define	EXTI_IMR_MR24_Msk (0x1UL << EXTI_IMR_MR24_Pos)

#define	EXTI_IMR_MR24 EXTI_IMR_MR24_Msk

#define	EXTI_IMR_MR25_Pos (25U)

#define	EXTI_IMR_MR25_Msk (0x1UL << EXTI_IMR_MR25_Pos)

#define	EXTI_IMR_MR25 EXTI_IMR_MR25_Msk

#define	EXTI_IMR_MR26_Pos (26U)

#define	EXTI_IMR_MR26_Msk (0x1UL << EXTI_IMR_MR26_Pos)

#define	EXTI_IMR_MR26 EXTI_IMR_MR26_Msk

#define	EXTI_IMR_MR27_Pos (27U)

#define	EXTI_IMR_MR27_Msk (0x1UL << EXTI_IMR_MR27_Pos)

#define	EXTI_IMR_MR27 EXTI_IMR_MR27_Msk

#define	EXTI_IMR_MR28_Pos (28U)

#define	EXTI_IMR_MR28_Msk (0x1UL << EXTI_IMR_MR28_Pos)

#define	EXTI_IMR_MR28 EXTI_IMR_MR28_Msk

#define	EXTI_IMR_MR29_Pos (29U)

#define	EXTI_IMR_MR29_Msk (0x1UL << EXTI_IMR_MR29_Pos)

#define	EXTI_IMR_MR29 EXTI_IMR_MR29_Msk

#define	EXTI_IMR_MR30_Pos (30U)

#define	EXTI_IMR_MR30_Msk (0x1UL << EXTI_IMR_MR30_Pos)

#define	EXTI_IMR_MR30 EXTI_IMR_MR30_Msk

#define	EXTI_IMR_MR31_Pos (31U)

#define	EXTI_IMR_MR31_Msk (0x1UL << EXTI_IMR_MR31_Pos)

#define	EXTI_IMR_MR31 EXTI_IMR_MR31_Msk

#define	EXTI_IMR_IM0 EXTI_IMR_MR0

#define	EXTI_IMR_IM1 EXTI_IMR_MR1

#define	EXTI_IMR_IM2 EXTI_IMR_MR2

#define	EXTI_IMR_IM3 EXTI_IMR_MR3

#define	EXTI_IMR_IM4 EXTI_IMR_MR4

#define	EXTI_IMR_IM5 EXTI_IMR_MR5

#define	EXTI_IMR_IM6 EXTI_IMR_MR6

#define	EXTI_IMR_IM7 EXTI_IMR_MR7

#define	EXTI_IMR_IM8 EXTI_IMR_MR8

#define	EXTI_IMR_IM9 EXTI_IMR_MR9

#define	EXTI_IMR_IM10 EXTI_IMR_MR10

#define	EXTI_IMR_IM11 EXTI_IMR_MR11

#define	EXTI_IMR_IM12 EXTI_IMR_MR12

#define	EXTI_IMR_IM13 EXTI_IMR_MR13

#define	EXTI_IMR_IM14 EXTI_IMR_MR14

#define	EXTI_IMR_IM15 EXTI_IMR_MR15

#define	EXTI_IMR_IM16 EXTI_IMR_MR16

#define	EXTI_IMR_IM17 EXTI_IMR_MR17

#define	EXTI_IMR_IM18 EXTI_IMR_MR18

#define	EXTI_IMR_IM19 EXTI_IMR_MR19

#define	EXTI_IMR_IM20 EXTI_IMR_MR20

#define	EXTI_IMR_IM21 EXTI_IMR_MR21

#define	EXTI_IMR_IM22 EXTI_IMR_MR22

#define	EXTI_IMR_IM23 EXTI_IMR_MR23

#define	EXTI_IMR_IM24 EXTI_IMR_MR24

#define	EXTI_IMR_IM25 EXTI_IMR_MR25

#define	EXTI_IMR_IM26 EXTI_IMR_MR26

#define	EXTI_IMR_IM27 EXTI_IMR_MR27

#define	EXTI_IMR_IM28 EXTI_IMR_MR28

#define	EXTI_IMR_IM29 EXTI_IMR_MR29

#define	EXTI_IMR_IM30 EXTI_IMR_MR30

#define	EXTI_IMR_IM31 EXTI_IMR_MR31

#define	EXTI_IMR_IM_Pos (0U)

#define	EXTI_IMR_IM_Msk (0xFFFFFFFFUL << EXTI_IMR_IM_Pos)

#define	EXTI_IMR_IM EXTI_IMR_IM_Msk

#define	EXTI_EMR_MR0_Pos (0U)

#define	EXTI_EMR_MR0_Msk (0x1UL << EXTI_EMR_MR0_Pos)

#define	EXTI_EMR_MR0 EXTI_EMR_MR0_Msk

#define	EXTI_EMR_MR1_Pos (1U)

#define	EXTI_EMR_MR1_Msk (0x1UL << EXTI_EMR_MR1_Pos)

#define	EXTI_EMR_MR1 EXTI_EMR_MR1_Msk

#define	EXTI_EMR_MR2_Pos (2U)

#define	EXTI_EMR_MR2_Msk (0x1UL << EXTI_EMR_MR2_Pos)

#define	EXTI_EMR_MR2 EXTI_EMR_MR2_Msk

#define	EXTI_EMR_MR3_Pos (3U)

#define	EXTI_EMR_MR3_Msk (0x1UL << EXTI_EMR_MR3_Pos)

#define	EXTI_EMR_MR3 EXTI_EMR_MR3_Msk

#define	EXTI_EMR_MR4_Pos (4U)

#define	EXTI_EMR_MR4_Msk (0x1UL << EXTI_EMR_MR4_Pos)

#define	EXTI_EMR_MR4 EXTI_EMR_MR4_Msk

#define	EXTI_EMR_MR5_Pos (5U)

#define	EXTI_EMR_MR5_Msk (0x1UL << EXTI_EMR_MR5_Pos)

#define	EXTI_EMR_MR5 EXTI_EMR_MR5_Msk

#define	EXTI_EMR_MR6_Pos (6U)

#define	EXTI_EMR_MR6_Msk (0x1UL << EXTI_EMR_MR6_Pos)

#define	EXTI_EMR_MR6 EXTI_EMR_MR6_Msk

#define	EXTI_EMR_MR7_Pos (7U)

#define	EXTI_EMR_MR7_Msk (0x1UL << EXTI_EMR_MR7_Pos)

#define	EXTI_EMR_MR7 EXTI_EMR_MR7_Msk

#define	EXTI_EMR_MR8_Pos (8U)

#define	EXTI_EMR_MR8_Msk (0x1UL << EXTI_EMR_MR8_Pos)

#define	EXTI_EMR_MR8 EXTI_EMR_MR8_Msk

#define	EXTI_EMR_MR9_Pos (9U)

#define	EXTI_EMR_MR9_Msk (0x1UL << EXTI_EMR_MR9_Pos)

#define	EXTI_EMR_MR9 EXTI_EMR_MR9_Msk

#define	EXTI_EMR_MR10_Pos (10U)

#define	EXTI_EMR_MR10_Msk (0x1UL << EXTI_EMR_MR10_Pos)

#define	EXTI_EMR_MR10 EXTI_EMR_MR10_Msk

#define	EXTI_EMR_MR11_Pos (11U)

#define	EXTI_EMR_MR11_Msk (0x1UL << EXTI_EMR_MR11_Pos)

#define	EXTI_EMR_MR11 EXTI_EMR_MR11_Msk

#define	EXTI_EMR_MR12_Pos (12U)

#define	EXTI_EMR_MR12_Msk (0x1UL << EXTI_EMR_MR12_Pos)

#define	EXTI_EMR_MR12 EXTI_EMR_MR12_Msk

#define	EXTI_EMR_MR13_Pos (13U)

#define	EXTI_EMR_MR13_Msk (0x1UL << EXTI_EMR_MR13_Pos)

#define	EXTI_EMR_MR13 EXTI_EMR_MR13_Msk

#define	EXTI_EMR_MR14_Pos (14U)

#define	EXTI_EMR_MR14_Msk (0x1UL << EXTI_EMR_MR14_Pos)

#define	EXTI_EMR_MR14 EXTI_EMR_MR14_Msk

#define	EXTI_EMR_MR15_Pos (15U)

#define	EXTI_EMR_MR15_Msk (0x1UL << EXTI_EMR_MR15_Pos)

#define	EXTI_EMR_MR15 EXTI_EMR_MR15_Msk

#define	EXTI_EMR_MR16_Pos (16U)

#define	EXTI_EMR_MR16_Msk (0x1UL << EXTI_EMR_MR16_Pos)

#define	EXTI_EMR_MR16 EXTI_EMR_MR16_Msk

#define	EXTI_EMR_MR17_Pos (17U)

#define	EXTI_EMR_MR17_Msk (0x1UL << EXTI_EMR_MR17_Pos)

#define	EXTI_EMR_MR17 EXTI_EMR_MR17_Msk

#define	EXTI_EMR_MR18_Pos (18U)

#define	EXTI_EMR_MR18_Msk (0x1UL << EXTI_EMR_MR18_Pos)

#define	EXTI_EMR_MR18 EXTI_EMR_MR18_Msk

#define	EXTI_EMR_MR19_Pos (19U)

#define	EXTI_EMR_MR19_Msk (0x1UL << EXTI_EMR_MR19_Pos)

#define	EXTI_EMR_MR19 EXTI_EMR_MR19_Msk

#define	EXTI_EMR_MR20_Pos (20U)

#define	EXTI_EMR_MR20_Msk (0x1UL << EXTI_EMR_MR20_Pos)

#define	EXTI_EMR_MR20 EXTI_EMR_MR20_Msk

#define	EXTI_EMR_MR21_Pos (21U)

#define	EXTI_EMR_MR21_Msk (0x1UL << EXTI_EMR_MR21_Pos)

#define	EXTI_EMR_MR21 EXTI_EMR_MR21_Msk

#define	EXTI_EMR_MR22_Pos (22U)

#define	EXTI_EMR_MR22_Msk (0x1UL << EXTI_EMR_MR22_Pos)

#define	EXTI_EMR_MR22 EXTI_EMR_MR22_Msk

#define	EXTI_EMR_MR23_Pos (23U)

#define	EXTI_EMR_MR23_Msk (0x1UL << EXTI_EMR_MR23_Pos)

#define	EXTI_EMR_MR23 EXTI_EMR_MR23_Msk

#define	EXTI_EMR_MR24_Pos (24U)

#define	EXTI_EMR_MR24_Msk (0x1UL << EXTI_EMR_MR24_Pos)

#define	EXTI_EMR_MR24 EXTI_EMR_MR24_Msk

#define	EXTI_EMR_MR25_Pos (25U)

#define	EXTI_EMR_MR25_Msk (0x1UL << EXTI_EMR_MR25_Pos)

#define	EXTI_EMR_MR25 EXTI_EMR_MR25_Msk

#define	EXTI_EMR_MR26_Pos (26U)

#define	EXTI_EMR_MR26_Msk (0x1UL << EXTI_EMR_MR26_Pos)

#define	EXTI_EMR_MR26 EXTI_EMR_MR26_Msk

#define	EXTI_EMR_MR27_Pos (27U)

#define	EXTI_EMR_MR27_Msk (0x1UL << EXTI_EMR_MR27_Pos)

#define	EXTI_EMR_MR27 EXTI_EMR_MR27_Msk

#define	EXTI_EMR_MR28_Pos (28U)

#define	EXTI_EMR_MR28_Msk (0x1UL << EXTI_EMR_MR28_Pos)

#define	EXTI_EMR_MR28 EXTI_EMR_MR28_Msk

#define	EXTI_EMR_MR29_Pos (29U)

#define	EXTI_EMR_MR29_Msk (0x1UL << EXTI_EMR_MR29_Pos)

#define	EXTI_EMR_MR29 EXTI_EMR_MR29_Msk

#define	EXTI_EMR_MR30_Pos (30U)

#define	EXTI_EMR_MR30_Msk (0x1UL << EXTI_EMR_MR30_Pos)

#define	EXTI_EMR_MR30 EXTI_EMR_MR30_Msk

#define	EXTI_EMR_MR31_Pos (31U)

#define	EXTI_EMR_MR31_Msk (0x1UL << EXTI_EMR_MR31_Pos)

#define	EXTI_EMR_MR31 EXTI_EMR_MR31_Msk

#define	EXTI_EMR_EM0 EXTI_EMR_MR0

#define	EXTI_EMR_EM1 EXTI_EMR_MR1

#define	EXTI_EMR_EM2 EXTI_EMR_MR2

#define	EXTI_EMR_EM3 EXTI_EMR_MR3

#define	EXTI_EMR_EM4 EXTI_EMR_MR4

#define	EXTI_EMR_EM5 EXTI_EMR_MR5

#define	EXTI_EMR_EM6 EXTI_EMR_MR6

#define	EXTI_EMR_EM7 EXTI_EMR_MR7

#define	EXTI_EMR_EM8 EXTI_EMR_MR8

#define	EXTI_EMR_EM9 EXTI_EMR_MR9

#define	EXTI_EMR_EM10 EXTI_EMR_MR10

#define	EXTI_EMR_EM11 EXTI_EMR_MR11

#define	EXTI_EMR_EM12 EXTI_EMR_MR12

#define	EXTI_EMR_EM13 EXTI_EMR_MR13

#define	EXTI_EMR_EM14 EXTI_EMR_MR14

#define	EXTI_EMR_EM15 EXTI_EMR_MR15

#define	EXTI_EMR_EM16 EXTI_EMR_MR16

#define	EXTI_EMR_EM17 EXTI_EMR_MR17

#define	EXTI_EMR_EM18 EXTI_EMR_MR18

#define	EXTI_EMR_EM19 EXTI_EMR_MR19

#define	EXTI_EMR_EM20 EXTI_EMR_MR20

#define	EXTI_EMR_EM21 EXTI_EMR_MR21

#define	EXTI_EMR_EM22 EXTI_EMR_MR22

#define	EXTI_EMR_EM23 EXTI_EMR_MR23

#define	EXTI_EMR_EM24 EXTI_EMR_MR24

#define	EXTI_EMR_EM25 EXTI_EMR_MR25

#define	EXTI_EMR_EM26 EXTI_EMR_MR26

#define	EXTI_EMR_EM27 EXTI_EMR_MR27

#define	EXTI_EMR_EM28 EXTI_EMR_MR28

#define	EXTI_EMR_EM29 EXTI_EMR_MR29

#define	EXTI_EMR_EM30 EXTI_EMR_MR30

#define	EXTI_EMR_EM31 EXTI_EMR_MR31

#define	EXTI_RTSR_TR0_Pos (0U)

#define	EXTI_RTSR_TR0_Msk (0x1UL << EXTI_RTSR_TR0_Pos)

#define	EXTI_RTSR_TR0 EXTI_RTSR_TR0_Msk

#define	EXTI_RTSR_TR1_Pos (1U)

#define	EXTI_RTSR_TR1_Msk (0x1UL << EXTI_RTSR_TR1_Pos)

#define	EXTI_RTSR_TR1 EXTI_RTSR_TR1_Msk

#define	EXTI_RTSR_TR2_Pos (2U)

#define	EXTI_RTSR_TR2_Msk (0x1UL << EXTI_RTSR_TR2_Pos)

#define	EXTI_RTSR_TR2 EXTI_RTSR_TR2_Msk

#define	EXTI_RTSR_TR3_Pos (3U)

#define	EXTI_RTSR_TR3_Msk (0x1UL << EXTI_RTSR_TR3_Pos)

#define	EXTI_RTSR_TR3 EXTI_RTSR_TR3_Msk

#define	EXTI_RTSR_TR4_Pos (4U)

#define	EXTI_RTSR_TR4_Msk (0x1UL << EXTI_RTSR_TR4_Pos)

#define	EXTI_RTSR_TR4 EXTI_RTSR_TR4_Msk

#define	EXTI_RTSR_TR5_Pos (5U)

#define	EXTI_RTSR_TR5_Msk (0x1UL << EXTI_RTSR_TR5_Pos)

#define	EXTI_RTSR_TR5 EXTI_RTSR_TR5_Msk

#define	EXTI_RTSR_TR6_Pos (6U)

#define	EXTI_RTSR_TR6_Msk (0x1UL << EXTI_RTSR_TR6_Pos)

#define	EXTI_RTSR_TR6 EXTI_RTSR_TR6_Msk

#define	EXTI_RTSR_TR7_Pos (7U)

#define	EXTI_RTSR_TR7_Msk (0x1UL << EXTI_RTSR_TR7_Pos)

#define	EXTI_RTSR_TR7 EXTI_RTSR_TR7_Msk

#define	EXTI_RTSR_TR8_Pos (8U)

#define	EXTI_RTSR_TR8_Msk (0x1UL << EXTI_RTSR_TR8_Pos)

#define	EXTI_RTSR_TR8 EXTI_RTSR_TR8_Msk

#define	EXTI_RTSR_TR9_Pos (9U)

#define	EXTI_RTSR_TR9_Msk (0x1UL << EXTI_RTSR_TR9_Pos)

#define	EXTI_RTSR_TR9 EXTI_RTSR_TR9_Msk

#define	EXTI_RTSR_TR10_Pos (10U)

#define	EXTI_RTSR_TR10_Msk (0x1UL << EXTI_RTSR_TR10_Pos)

#define	EXTI_RTSR_TR10 EXTI_RTSR_TR10_Msk

#define	EXTI_RTSR_TR11_Pos (11U)

#define	EXTI_RTSR_TR11_Msk (0x1UL << EXTI_RTSR_TR11_Pos)

#define	EXTI_RTSR_TR11 EXTI_RTSR_TR11_Msk

#define	EXTI_RTSR_TR12_Pos (12U)

#define	EXTI_RTSR_TR12_Msk (0x1UL << EXTI_RTSR_TR12_Pos)

#define	EXTI_RTSR_TR12 EXTI_RTSR_TR12_Msk

#define	EXTI_RTSR_TR13_Pos (13U)

#define	EXTI_RTSR_TR13_Msk (0x1UL << EXTI_RTSR_TR13_Pos)

#define	EXTI_RTSR_TR13 EXTI_RTSR_TR13_Msk

#define	EXTI_RTSR_TR14_Pos (14U)

#define	EXTI_RTSR_TR14_Msk (0x1UL << EXTI_RTSR_TR14_Pos)

#define	EXTI_RTSR_TR14 EXTI_RTSR_TR14_Msk

#define	EXTI_RTSR_TR15_Pos (15U)

#define	EXTI_RTSR_TR15_Msk (0x1UL << EXTI_RTSR_TR15_Pos)

#define	EXTI_RTSR_TR15 EXTI_RTSR_TR15_Msk

#define	EXTI_RTSR_TR16_Pos (16U)

#define	EXTI_RTSR_TR16_Msk (0x1UL << EXTI_RTSR_TR16_Pos)

#define	EXTI_RTSR_TR16 EXTI_RTSR_TR16_Msk

#define	EXTI_RTSR_TR17_Pos (17U)

#define	EXTI_RTSR_TR17_Msk (0x1UL << EXTI_RTSR_TR17_Pos)

#define	EXTI_RTSR_TR17 EXTI_RTSR_TR17_Msk

#define	EXTI_RTSR_TR18_Pos (18U)

#define	EXTI_RTSR_TR18_Msk (0x1UL << EXTI_RTSR_TR18_Pos)

#define	EXTI_RTSR_TR18 EXTI_RTSR_TR18_Msk

#define	EXTI_RTSR_TR19_Pos (19U)

#define	EXTI_RTSR_TR19_Msk (0x1UL << EXTI_RTSR_TR19_Pos)

#define	EXTI_RTSR_TR19 EXTI_RTSR_TR19_Msk

#define	EXTI_RTSR_TR20_Pos (20U)

#define	EXTI_RTSR_TR20_Msk (0x1UL << EXTI_RTSR_TR20_Pos)

#define	EXTI_RTSR_TR20 EXTI_RTSR_TR20_Msk

#define	EXTI_RTSR_TR21_Pos (21U)

#define	EXTI_RTSR_TR21_Msk (0x1UL << EXTI_RTSR_TR21_Pos)

#define	EXTI_RTSR_TR21 EXTI_RTSR_TR21_Msk

#define	EXTI_RTSR_TR22_Pos (22U)

#define	EXTI_RTSR_TR22_Msk (0x1UL << EXTI_RTSR_TR22_Pos)

#define	EXTI_RTSR_TR22 EXTI_RTSR_TR22_Msk

#define	EXTI_RTSR_TR29_Pos (29U)

#define	EXTI_RTSR_TR29_Msk (0x1UL << EXTI_RTSR_TR29_Pos)

#define	EXTI_RTSR_TR29 EXTI_RTSR_TR29_Msk

#define	EXTI_RTSR_TR30_Pos (30U)

#define	EXTI_RTSR_TR30_Msk (0x1UL << EXTI_RTSR_TR30_Pos)

#define	EXTI_RTSR_TR30 EXTI_RTSR_TR30_Msk

#define	EXTI_RTSR_TR31_Pos (31U)

#define	EXTI_RTSR_TR31_Msk (0x1UL << EXTI_RTSR_TR31_Pos)

#define	EXTI_RTSR_TR31 EXTI_RTSR_TR31_Msk

#define	EXTI_RTSR_RT0 EXTI_RTSR_TR0

#define	EXTI_RTSR_RT1 EXTI_RTSR_TR1

#define	EXTI_RTSR_RT2 EXTI_RTSR_TR2

#define	EXTI_RTSR_RT3 EXTI_RTSR_TR3

#define	EXTI_RTSR_RT4 EXTI_RTSR_TR4

#define	EXTI_RTSR_RT5 EXTI_RTSR_TR5

#define	EXTI_RTSR_RT6 EXTI_RTSR_TR6

#define	EXTI_RTSR_RT7 EXTI_RTSR_TR7

#define	EXTI_RTSR_RT8 EXTI_RTSR_TR8

#define	EXTI_RTSR_RT9 EXTI_RTSR_TR9

#define	EXTI_RTSR_RT10 EXTI_RTSR_TR10

#define	EXTI_RTSR_RT11 EXTI_RTSR_TR11

#define	EXTI_RTSR_RT12 EXTI_RTSR_TR12

#define	EXTI_RTSR_RT13 EXTI_RTSR_TR13

#define	EXTI_RTSR_RT14 EXTI_RTSR_TR14

#define	EXTI_RTSR_RT15 EXTI_RTSR_TR15

#define	EXTI_RTSR_RT16 EXTI_RTSR_TR16

#define	EXTI_RTSR_RT17 EXTI_RTSR_TR17

#define	EXTI_RTSR_RT18 EXTI_RTSR_TR18

#define	EXTI_RTSR_RT19 EXTI_RTSR_TR19

#define	EXTI_RTSR_RT20 EXTI_RTSR_TR20

#define	EXTI_RTSR_RT21 EXTI_RTSR_TR21

#define	EXTI_RTSR_RT22 EXTI_RTSR_TR22

#define	EXTI_RTSR_RT29 EXTI_RTSR_TR29

#define	EXTI_RTSR_RT30 EXTI_RTSR_TR30

#define	EXTI_RTSR_RT31 EXTI_RTSR_TR31

#define	EXTI_FTSR_TR0_Pos (0U)

#define	EXTI_FTSR_TR0_Msk (0x1UL << EXTI_FTSR_TR0_Pos)

#define	EXTI_FTSR_TR0 EXTI_FTSR_TR0_Msk

#define	EXTI_FTSR_TR1_Pos (1U)

#define	EXTI_FTSR_TR1_Msk (0x1UL << EXTI_FTSR_TR1_Pos)

#define	EXTI_FTSR_TR1 EXTI_FTSR_TR1_Msk

#define	EXTI_FTSR_TR2_Pos (2U)

#define	EXTI_FTSR_TR2_Msk (0x1UL << EXTI_FTSR_TR2_Pos)

#define	EXTI_FTSR_TR2 EXTI_FTSR_TR2_Msk

#define	EXTI_FTSR_TR3_Pos (3U)

#define	EXTI_FTSR_TR3_Msk (0x1UL << EXTI_FTSR_TR3_Pos)

#define	EXTI_FTSR_TR3 EXTI_FTSR_TR3_Msk

#define	EXTI_FTSR_TR4_Pos (4U)

#define	EXTI_FTSR_TR4_Msk (0x1UL << EXTI_FTSR_TR4_Pos)

#define	EXTI_FTSR_TR4 EXTI_FTSR_TR4_Msk

#define	EXTI_FTSR_TR5_Pos (5U)

#define	EXTI_FTSR_TR5_Msk (0x1UL << EXTI_FTSR_TR5_Pos)

#define	EXTI_FTSR_TR5 EXTI_FTSR_TR5_Msk

#define	EXTI_FTSR_TR6_Pos (6U)

#define	EXTI_FTSR_TR6_Msk (0x1UL << EXTI_FTSR_TR6_Pos)

#define	EXTI_FTSR_TR6 EXTI_FTSR_TR6_Msk

#define	EXTI_FTSR_TR7_Pos (7U)

#define	EXTI_FTSR_TR7_Msk (0x1UL << EXTI_FTSR_TR7_Pos)

#define	EXTI_FTSR_TR7 EXTI_FTSR_TR7_Msk

#define	EXTI_FTSR_TR8_Pos (8U)

#define	EXTI_FTSR_TR8_Msk (0x1UL << EXTI_FTSR_TR8_Pos)

#define	EXTI_FTSR_TR8 EXTI_FTSR_TR8_Msk

#define	EXTI_FTSR_TR9_Pos (9U)

#define	EXTI_FTSR_TR9_Msk (0x1UL << EXTI_FTSR_TR9_Pos)

#define	EXTI_FTSR_TR9 EXTI_FTSR_TR9_Msk

#define	EXTI_FTSR_TR10_Pos (10U)

#define	EXTI_FTSR_TR10_Msk (0x1UL << EXTI_FTSR_TR10_Pos)

#define	EXTI_FTSR_TR10 EXTI_FTSR_TR10_Msk

#define	EXTI_FTSR_TR11_Pos (11U)

#define	EXTI_FTSR_TR11_Msk (0x1UL << EXTI_FTSR_TR11_Pos)

#define	EXTI_FTSR_TR11 EXTI_FTSR_TR11_Msk

#define	EXTI_FTSR_TR12_Pos (12U)

#define	EXTI_FTSR_TR12_Msk (0x1UL << EXTI_FTSR_TR12_Pos)

#define	EXTI_FTSR_TR12 EXTI_FTSR_TR12_Msk

#define	EXTI_FTSR_TR13_Pos (13U)

#define	EXTI_FTSR_TR13_Msk (0x1UL << EXTI_FTSR_TR13_Pos)

#define	EXTI_FTSR_TR13 EXTI_FTSR_TR13_Msk

#define	EXTI_FTSR_TR14_Pos (14U)

#define	EXTI_FTSR_TR14_Msk (0x1UL << EXTI_FTSR_TR14_Pos)

#define	EXTI_FTSR_TR14 EXTI_FTSR_TR14_Msk

#define	EXTI_FTSR_TR15_Pos (15U)

#define	EXTI_FTSR_TR15_Msk (0x1UL << EXTI_FTSR_TR15_Pos)

#define	EXTI_FTSR_TR15 EXTI_FTSR_TR15_Msk

#define	EXTI_FTSR_TR16_Pos (16U)

#define	EXTI_FTSR_TR16_Msk (0x1UL << EXTI_FTSR_TR16_Pos)

#define	EXTI_FTSR_TR16 EXTI_FTSR_TR16_Msk

#define	EXTI_FTSR_TR17_Pos (17U)

#define	EXTI_FTSR_TR17_Msk (0x1UL << EXTI_FTSR_TR17_Pos)

#define	EXTI_FTSR_TR17 EXTI_FTSR_TR17_Msk

#define	EXTI_FTSR_TR18_Pos (18U)

#define	EXTI_FTSR_TR18_Msk (0x1UL << EXTI_FTSR_TR18_Pos)

#define	EXTI_FTSR_TR18 EXTI_FTSR_TR18_Msk

#define	EXTI_FTSR_TR19_Pos (19U)

#define	EXTI_FTSR_TR19_Msk (0x1UL << EXTI_FTSR_TR19_Pos)

#define	EXTI_FTSR_TR19 EXTI_FTSR_TR19_Msk

#define	EXTI_FTSR_TR20_Pos (20U)

#define	EXTI_FTSR_TR20_Msk (0x1UL << EXTI_FTSR_TR20_Pos)

#define	EXTI_FTSR_TR20 EXTI_FTSR_TR20_Msk

#define	EXTI_FTSR_TR21_Pos (21U)

#define	EXTI_FTSR_TR21_Msk (0x1UL << EXTI_FTSR_TR21_Pos)

#define	EXTI_FTSR_TR21 EXTI_FTSR_TR21_Msk

#define	EXTI_FTSR_TR22_Pos (22U)

#define	EXTI_FTSR_TR22_Msk (0x1UL << EXTI_FTSR_TR22_Pos)

#define	EXTI_FTSR_TR22 EXTI_FTSR_TR22_Msk

#define	EXTI_FTSR_TR29_Pos (29U)

#define	EXTI_FTSR_TR29_Msk (0x1UL << EXTI_FTSR_TR29_Pos)

#define	EXTI_FTSR_TR29 EXTI_FTSR_TR29_Msk

#define	EXTI_FTSR_TR30_Pos (30U)

#define	EXTI_FTSR_TR30_Msk (0x1UL << EXTI_FTSR_TR30_Pos)

#define	EXTI_FTSR_TR30 EXTI_FTSR_TR30_Msk

#define	EXTI_FTSR_TR31_Pos (31U)

#define	EXTI_FTSR_TR31_Msk (0x1UL << EXTI_FTSR_TR31_Pos)

#define	EXTI_FTSR_TR31 EXTI_FTSR_TR31_Msk

#define	EXTI_FTSR_FT0 EXTI_FTSR_TR0

#define	EXTI_FTSR_FT1 EXTI_FTSR_TR1

#define	EXTI_FTSR_FT2 EXTI_FTSR_TR2

#define	EXTI_FTSR_FT3 EXTI_FTSR_TR3

#define	EXTI_FTSR_FT4 EXTI_FTSR_TR4

#define	EXTI_FTSR_FT5 EXTI_FTSR_TR5

#define	EXTI_FTSR_FT6 EXTI_FTSR_TR6

#define	EXTI_FTSR_FT7 EXTI_FTSR_TR7

#define	EXTI_FTSR_FT8 EXTI_FTSR_TR8

#define	EXTI_FTSR_FT9 EXTI_FTSR_TR9

#define	EXTI_FTSR_FT10 EXTI_FTSR_TR10

#define	EXTI_FTSR_FT11 EXTI_FTSR_TR11

#define	EXTI_FTSR_FT12 EXTI_FTSR_TR12

#define	EXTI_FTSR_FT13 EXTI_FTSR_TR13

#define	EXTI_FTSR_FT14 EXTI_FTSR_TR14

#define	EXTI_FTSR_FT15 EXTI_FTSR_TR15

#define	EXTI_FTSR_FT16 EXTI_FTSR_TR16

#define	EXTI_FTSR_FT17 EXTI_FTSR_TR17

#define	EXTI_FTSR_FT18 EXTI_FTSR_TR18

#define	EXTI_FTSR_FT19 EXTI_FTSR_TR19

#define	EXTI_FTSR_FT20 EXTI_FTSR_TR20

#define	EXTI_FTSR_FT21 EXTI_FTSR_TR21

#define	EXTI_FTSR_FT22 EXTI_FTSR_TR22

#define	EXTI_FTSR_FT29 EXTI_FTSR_TR29

#define	EXTI_FTSR_FT30 EXTI_FTSR_TR30

#define	EXTI_FTSR_FT31 EXTI_FTSR_TR31

#define	EXTI_SWIER_SWIER0_Pos (0U)

#define	EXTI_SWIER_SWIER0_Msk (0x1UL << EXTI_SWIER_SWIER0_Pos)

#define	EXTI_SWIER_SWIER0 EXTI_SWIER_SWIER0_Msk

#define	EXTI_SWIER_SWIER1_Pos (1U)

#define	EXTI_SWIER_SWIER1_Msk (0x1UL << EXTI_SWIER_SWIER1_Pos)

#define	EXTI_SWIER_SWIER1 EXTI_SWIER_SWIER1_Msk

#define	EXTI_SWIER_SWIER2_Pos (2U)

#define	EXTI_SWIER_SWIER2_Msk (0x1UL << EXTI_SWIER_SWIER2_Pos)

#define	EXTI_SWIER_SWIER2 EXTI_SWIER_SWIER2_Msk

#define	EXTI_SWIER_SWIER3_Pos (3U)

#define	EXTI_SWIER_SWIER3_Msk (0x1UL << EXTI_SWIER_SWIER3_Pos)

#define	EXTI_SWIER_SWIER3 EXTI_SWIER_SWIER3_Msk

#define	EXTI_SWIER_SWIER4_Pos (4U)

#define	EXTI_SWIER_SWIER4_Msk (0x1UL << EXTI_SWIER_SWIER4_Pos)

#define	EXTI_SWIER_SWIER4 EXTI_SWIER_SWIER4_Msk

#define	EXTI_SWIER_SWIER5_Pos (5U)

#define	EXTI_SWIER_SWIER5_Msk (0x1UL << EXTI_SWIER_SWIER5_Pos)

#define	EXTI_SWIER_SWIER5 EXTI_SWIER_SWIER5_Msk

#define	EXTI_SWIER_SWIER6_Pos (6U)

#define	EXTI_SWIER_SWIER6_Msk (0x1UL << EXTI_SWIER_SWIER6_Pos)

#define	EXTI_SWIER_SWIER6 EXTI_SWIER_SWIER6_Msk

#define	EXTI_SWIER_SWIER7_Pos (7U)

#define	EXTI_SWIER_SWIER7_Msk (0x1UL << EXTI_SWIER_SWIER7_Pos)

#define	EXTI_SWIER_SWIER7 EXTI_SWIER_SWIER7_Msk

#define	EXTI_SWIER_SWIER8_Pos (8U)

#define	EXTI_SWIER_SWIER8_Msk (0x1UL << EXTI_SWIER_SWIER8_Pos)

#define	EXTI_SWIER_SWIER8 EXTI_SWIER_SWIER8_Msk

#define	EXTI_SWIER_SWIER9_Pos (9U)

#define	EXTI_SWIER_SWIER9_Msk (0x1UL << EXTI_SWIER_SWIER9_Pos)

#define	EXTI_SWIER_SWIER9 EXTI_SWIER_SWIER9_Msk

#define	EXTI_SWIER_SWIER10_Pos (10U)

#define	EXTI_SWIER_SWIER10_Msk (0x1UL << EXTI_SWIER_SWIER10_Pos)

#define	EXTI_SWIER_SWIER10 EXTI_SWIER_SWIER10_Msk

#define	EXTI_SWIER_SWIER11_Pos (11U)

#define	EXTI_SWIER_SWIER11_Msk (0x1UL << EXTI_SWIER_SWIER11_Pos)

#define	EXTI_SWIER_SWIER11 EXTI_SWIER_SWIER11_Msk

#define	EXTI_SWIER_SWIER12_Pos (12U)

#define	EXTI_SWIER_SWIER12_Msk (0x1UL << EXTI_SWIER_SWIER12_Pos)

#define	EXTI_SWIER_SWIER12 EXTI_SWIER_SWIER12_Msk

#define	EXTI_SWIER_SWIER13_Pos (13U)

#define	EXTI_SWIER_SWIER13_Msk (0x1UL << EXTI_SWIER_SWIER13_Pos)

#define	EXTI_SWIER_SWIER13 EXTI_SWIER_SWIER13_Msk

#define	EXTI_SWIER_SWIER14_Pos (14U)

#define	EXTI_SWIER_SWIER14_Msk (0x1UL << EXTI_SWIER_SWIER14_Pos)

#define	EXTI_SWIER_SWIER14 EXTI_SWIER_SWIER14_Msk

#define	EXTI_SWIER_SWIER15_Pos (15U)

#define	EXTI_SWIER_SWIER15_Msk (0x1UL << EXTI_SWIER_SWIER15_Pos)

#define	EXTI_SWIER_SWIER15 EXTI_SWIER_SWIER15_Msk

#define	EXTI_SWIER_SWIER16_Pos (16U)

#define	EXTI_SWIER_SWIER16_Msk (0x1UL << EXTI_SWIER_SWIER16_Pos)

#define	EXTI_SWIER_SWIER16 EXTI_SWIER_SWIER16_Msk

#define	EXTI_SWIER_SWIER17_Pos (17U)

#define	EXTI_SWIER_SWIER17_Msk (0x1UL << EXTI_SWIER_SWIER17_Pos)

#define	EXTI_SWIER_SWIER17 EXTI_SWIER_SWIER17_Msk

#define	EXTI_SWIER_SWIER18_Pos (18U)

#define	EXTI_SWIER_SWIER18_Msk (0x1UL << EXTI_SWIER_SWIER18_Pos)

#define	EXTI_SWIER_SWIER18 EXTI_SWIER_SWIER18_Msk

#define	EXTI_SWIER_SWIER19_Pos (19U)

#define	EXTI_SWIER_SWIER19_Msk (0x1UL << EXTI_SWIER_SWIER19_Pos)

#define	EXTI_SWIER_SWIER19 EXTI_SWIER_SWIER19_Msk

#define	EXTI_SWIER_SWIER20_Pos (20U)

#define	EXTI_SWIER_SWIER20_Msk (0x1UL << EXTI_SWIER_SWIER20_Pos)

#define	EXTI_SWIER_SWIER20 EXTI_SWIER_SWIER20_Msk

#define	EXTI_SWIER_SWIER21_Pos (21U)

#define	EXTI_SWIER_SWIER21_Msk (0x1UL << EXTI_SWIER_SWIER21_Pos)

#define	EXTI_SWIER_SWIER21 EXTI_SWIER_SWIER21_Msk

#define	EXTI_SWIER_SWIER22_Pos (22U)

#define	EXTI_SWIER_SWIER22_Msk (0x1UL << EXTI_SWIER_SWIER22_Pos)

#define	EXTI_SWIER_SWIER22 EXTI_SWIER_SWIER22_Msk

#define	EXTI_SWIER_SWIER29_Pos (29U)

#define	EXTI_SWIER_SWIER29_Msk (0x1UL << EXTI_SWIER_SWIER29_Pos)

#define	EXTI_SWIER_SWIER29 EXTI_SWIER_SWIER29_Msk

#define	EXTI_SWIER_SWIER30_Pos (30U)

#define	EXTI_SWIER_SWIER30_Msk (0x1UL << EXTI_SWIER_SWIER30_Pos)

#define	EXTI_SWIER_SWIER30 EXTI_SWIER_SWIER30_Msk

#define	EXTI_SWIER_SWIER31_Pos (31U)

#define	EXTI_SWIER_SWIER31_Msk (0x1UL << EXTI_SWIER_SWIER31_Pos)

#define	EXTI_SWIER_SWIER31 EXTI_SWIER_SWIER31_Msk

#define	EXTI_SWIER_SWI0 EXTI_SWIER_SWIER0

#define	EXTI_SWIER_SWI1 EXTI_SWIER_SWIER1

#define	EXTI_SWIER_SWI2 EXTI_SWIER_SWIER2

#define	EXTI_SWIER_SWI3 EXTI_SWIER_SWIER3

#define	EXTI_SWIER_SWI4 EXTI_SWIER_SWIER4

#define	EXTI_SWIER_SWI5 EXTI_SWIER_SWIER5

#define	EXTI_SWIER_SWI6 EXTI_SWIER_SWIER6

#define	EXTI_SWIER_SWI7 EXTI_SWIER_SWIER7

#define	EXTI_SWIER_SWI8 EXTI_SWIER_SWIER8

#define	EXTI_SWIER_SWI9 EXTI_SWIER_SWIER9

#define	EXTI_SWIER_SWI10 EXTI_SWIER_SWIER10

#define	EXTI_SWIER_SWI11 EXTI_SWIER_SWIER11

#define	EXTI_SWIER_SWI12 EXTI_SWIER_SWIER12

#define	EXTI_SWIER_SWI13 EXTI_SWIER_SWIER13

#define	EXTI_SWIER_SWI14 EXTI_SWIER_SWIER14

#define	EXTI_SWIER_SWI15 EXTI_SWIER_SWIER15

#define	EXTI_SWIER_SWI16 EXTI_SWIER_SWIER16

#define	EXTI_SWIER_SWI17 EXTI_SWIER_SWIER17

#define	EXTI_SWIER_SWI18 EXTI_SWIER_SWIER18

#define	EXTI_SWIER_SWI19 EXTI_SWIER_SWIER19

#define	EXTI_SWIER_SWI20 EXTI_SWIER_SWIER20

#define	EXTI_SWIER_SWI21 EXTI_SWIER_SWIER21

#define	EXTI_SWIER_SWI22 EXTI_SWIER_SWIER22

#define	EXTI_SWIER_SWI29 EXTI_SWIER_SWIER29

#define	EXTI_SWIER_SWI30 EXTI_SWIER_SWIER30

#define	EXTI_SWIER_SWI31 EXTI_SWIER_SWIER31

#define	EXTI_PR_PR0_Pos (0U)

#define	EXTI_PR_PR0_Msk (0x1UL << EXTI_PR_PR0_Pos)

#define	EXTI_PR_PR0 EXTI_PR_PR0_Msk

#define	EXTI_PR_PR1_Pos (1U)

#define	EXTI_PR_PR1_Msk (0x1UL << EXTI_PR_PR1_Pos)

#define	EXTI_PR_PR1 EXTI_PR_PR1_Msk

#define	EXTI_PR_PR2_Pos (2U)

#define	EXTI_PR_PR2_Msk (0x1UL << EXTI_PR_PR2_Pos)

#define	EXTI_PR_PR2 EXTI_PR_PR2_Msk

#define	EXTI_PR_PR3_Pos (3U)

#define	EXTI_PR_PR3_Msk (0x1UL << EXTI_PR_PR3_Pos)

#define	EXTI_PR_PR3 EXTI_PR_PR3_Msk

#define	EXTI_PR_PR4_Pos (4U)

#define	EXTI_PR_PR4_Msk (0x1UL << EXTI_PR_PR4_Pos)

#define	EXTI_PR_PR4 EXTI_PR_PR4_Msk

#define	EXTI_PR_PR5_Pos (5U)

#define	EXTI_PR_PR5_Msk (0x1UL << EXTI_PR_PR5_Pos)

#define	EXTI_PR_PR5 EXTI_PR_PR5_Msk

#define	EXTI_PR_PR6_Pos (6U)

#define	EXTI_PR_PR6_Msk (0x1UL << EXTI_PR_PR6_Pos)

#define	EXTI_PR_PR6 EXTI_PR_PR6_Msk

#define	EXTI_PR_PR7_Pos (7U)

#define	EXTI_PR_PR7_Msk (0x1UL << EXTI_PR_PR7_Pos)

#define	EXTI_PR_PR7 EXTI_PR_PR7_Msk

#define	EXTI_PR_PR8_Pos (8U)

#define	EXTI_PR_PR8_Msk (0x1UL << EXTI_PR_PR8_Pos)

#define	EXTI_PR_PR8 EXTI_PR_PR8_Msk

#define	EXTI_PR_PR9_Pos (9U)

#define	EXTI_PR_PR9_Msk (0x1UL << EXTI_PR_PR9_Pos)

#define	EXTI_PR_PR9 EXTI_PR_PR9_Msk

#define	EXTI_PR_PR10_Pos (10U)

#define	EXTI_PR_PR10_Msk (0x1UL << EXTI_PR_PR10_Pos)

#define	EXTI_PR_PR10 EXTI_PR_PR10_Msk

#define	EXTI_PR_PR11_Pos (11U)

#define	EXTI_PR_PR11_Msk (0x1UL << EXTI_PR_PR11_Pos)

#define	EXTI_PR_PR11 EXTI_PR_PR11_Msk

#define	EXTI_PR_PR12_Pos (12U)

#define	EXTI_PR_PR12_Msk (0x1UL << EXTI_PR_PR12_Pos)

#define	EXTI_PR_PR12 EXTI_PR_PR12_Msk

#define	EXTI_PR_PR13_Pos (13U)

#define	EXTI_PR_PR13_Msk (0x1UL << EXTI_PR_PR13_Pos)

#define	EXTI_PR_PR13 EXTI_PR_PR13_Msk

#define	EXTI_PR_PR14_Pos (14U)

#define	EXTI_PR_PR14_Msk (0x1UL << EXTI_PR_PR14_Pos)

#define	EXTI_PR_PR14 EXTI_PR_PR14_Msk

#define	EXTI_PR_PR15_Pos (15U)

#define	EXTI_PR_PR15_Msk (0x1UL << EXTI_PR_PR15_Pos)

#define	EXTI_PR_PR15 EXTI_PR_PR15_Msk

#define	EXTI_PR_PR16_Pos (16U)

#define	EXTI_PR_PR16_Msk (0x1UL << EXTI_PR_PR16_Pos)

#define	EXTI_PR_PR16 EXTI_PR_PR16_Msk

#define	EXTI_PR_PR17_Pos (17U)

#define	EXTI_PR_PR17_Msk (0x1UL << EXTI_PR_PR17_Pos)

#define	EXTI_PR_PR17 EXTI_PR_PR17_Msk

#define	EXTI_PR_PR18_Pos (18U)

#define	EXTI_PR_PR18_Msk (0x1UL << EXTI_PR_PR18_Pos)

#define	EXTI_PR_PR18 EXTI_PR_PR18_Msk

#define	EXTI_PR_PR19_Pos (19U)

#define	EXTI_PR_PR19_Msk (0x1UL << EXTI_PR_PR19_Pos)

#define	EXTI_PR_PR19 EXTI_PR_PR19_Msk

#define	EXTI_PR_PR20_Pos (20U)

#define	EXTI_PR_PR20_Msk (0x1UL << EXTI_PR_PR20_Pos)

#define	EXTI_PR_PR20 EXTI_PR_PR20_Msk

#define	EXTI_PR_PR21_Pos (21U)

#define	EXTI_PR_PR21_Msk (0x1UL << EXTI_PR_PR21_Pos)

#define	EXTI_PR_PR21 EXTI_PR_PR21_Msk

#define	EXTI_PR_PR22_Pos (22U)

#define	EXTI_PR_PR22_Msk (0x1UL << EXTI_PR_PR22_Pos)

#define	EXTI_PR_PR22 EXTI_PR_PR22_Msk

#define	EXTI_PR_PR29_Pos (29U)

#define	EXTI_PR_PR29_Msk (0x1UL << EXTI_PR_PR29_Pos)

#define	EXTI_PR_PR29 EXTI_PR_PR29_Msk

#define	EXTI_PR_PR30_Pos (30U)

#define	EXTI_PR_PR30_Msk (0x1UL << EXTI_PR_PR30_Pos)

#define	EXTI_PR_PR30 EXTI_PR_PR30_Msk

#define	EXTI_PR_PR31_Pos (31U)

#define	EXTI_PR_PR31_Msk (0x1UL << EXTI_PR_PR31_Pos)

#define	EXTI_PR_PR31 EXTI_PR_PR31_Msk

#define	EXTI_PR_PIF0 EXTI_PR_PR0

#define	EXTI_PR_PIF1 EXTI_PR_PR1

#define	EXTI_PR_PIF2 EXTI_PR_PR2

#define	EXTI_PR_PIF3 EXTI_PR_PR3

#define	EXTI_PR_PIF4 EXTI_PR_PR4

#define	EXTI_PR_PIF5 EXTI_PR_PR5

#define	EXTI_PR_PIF6 EXTI_PR_PR6

#define	EXTI_PR_PIF6 EXTI_PR_PR6

#define	EXTI_PR_PIF7 EXTI_PR_PR7

#define	EXTI_PR_PIF8 EXTI_PR_PR8

#define	EXTI_PR_PIF9 EXTI_PR_PR9

#define	EXTI_PR_PIF10 EXTI_PR_PR10

#define	EXTI_PR_PIF11 EXTI_PR_PR11

#define	EXTI_PR_PIF12 EXTI_PR_PR12

#define	EXTI_PR_PIF13 EXTI_PR_PR13

#define	EXTI_PR_PIF14 EXTI_PR_PR14

#define	EXTI_PR_PIF15 EXTI_PR_PR15

#define	EXTI_PR_PIF16 EXTI_PR_PR16

#define	EXTI_PR_PIF17 EXTI_PR_PR17

#define	EXTI_PR_PIF18 EXTI_PR_PR18

#define	EXTI_PR_PIF19 EXTI_PR_PR19

#define	EXTI_PR_PIF20 EXTI_PR_PR20

#define	EXTI_PR_PIF21 EXTI_PR_PR21

#define	EXTI_PR_PIF22 EXTI_PR_PR22

#define	EXTI_PR_PIF29 EXTI_PR_PR29

#define	EXTI_PR_PIF30 EXTI_PR_PR30

#define	EXTI_PR_PIF31 EXTI_PR_PR31

#define	EXTI_32_63_SUPPORT /* EXTI support more than 32 lines */

#define	EXTI_IMR2_MR32_Pos (0U)

#define	EXTI_IMR2_MR32_Msk (0x1UL << EXTI_IMR2_MR32_Pos)

#define	EXTI_IMR2_MR32 EXTI_IMR2_MR32_Msk

#define	EXTI_IMR2_MR33_Pos (1U)

#define	EXTI_IMR2_MR33_Msk (0x1UL << EXTI_IMR2_MR33_Pos)

#define	EXTI_IMR2_MR33 EXTI_IMR2_MR33_Msk

#define	EXTI_IMR2_MR34_Pos (2U)

#define	EXTI_IMR2_MR34_Msk (0x1UL << EXTI_IMR2_MR34_Pos)

#define	EXTI_IMR2_MR34 EXTI_IMR2_MR34_Msk

#define	EXTI_IMR2_MR35_Pos (3U)

#define	EXTI_IMR2_MR35_Msk (0x1UL << EXTI_IMR2_MR35_Pos)

#define	EXTI_IMR2_MR35 EXTI_IMR2_MR35_Msk

#define	EXTI_IMR2_IM32 EXTI_IMR2_MR32

#define	EXTI_IMR2_IM33 EXTI_IMR2_MR33

#define	EXTI_IMR2_IM34 EXTI_IMR2_MR34

#define	EXTI_IMR2_IM35 EXTI_IMR2_MR35

#define	EXTI_IMR2_IM_Pos (0U)

#define	EXTI_IMR2_IM_Msk (0xFUL << EXTI_IMR2_IM_Pos)

#define	EXTI_IMR2_IM EXTI_IMR2_IM_Msk

#define	EXTI_EMR2_MR32_Pos (0U)

#define	EXTI_EMR2_MR32_Msk (0x1UL << EXTI_EMR2_MR32_Pos)

#define	EXTI_EMR2_MR32 EXTI_EMR2_MR32_Msk

#define	EXTI_EMR2_MR33_Pos (1U)

#define	EXTI_EMR2_MR33_Msk (0x1UL << EXTI_EMR2_MR33_Pos)

#define	EXTI_EMR2_MR33 EXTI_EMR2_MR33_Msk

#define	EXTI_EMR2_MR34_Pos (2U)

#define	EXTI_EMR2_MR34_Msk (0x1UL << EXTI_EMR2_MR34_Pos)

#define	EXTI_EMR2_MR34 EXTI_EMR2_MR34_Msk

#define	EXTI_EMR2_MR35_Pos (3U)

#define	EXTI_EMR2_MR35_Msk (0x1UL << EXTI_EMR2_MR35_Pos)

#define	EXTI_EMR2_MR35 EXTI_EMR2_MR35_Msk

#define	EXTI_EMR2_EM32 EXTI_EMR2_MR32

#define	EXTI_EMR2_EM33 EXTI_EMR2_MR33

#define	EXTI_EMR2_EM34 EXTI_EMR2_MR34

#define	EXTI_EMR2_EM35 EXTI_EMR2_MR35

#define	EXTI_EMR2_EM_Pos (0U)

#define	EXTI_EMR2_EM_Msk (0xFUL << EXTI_EMR2_EM_Pos)

#define	EXTI_EMR2_EM EXTI_EMR2_EM_Msk

#define	EXTI_RTSR2_TR32_Pos (0U)

#define	EXTI_RTSR2_TR32_Msk (0x1UL << EXTI_RTSR2_TR32_Pos)

#define	EXTI_RTSR2_TR32 EXTI_RTSR2_TR32_Msk

#define	EXTI_RTSR2_TR33_Pos (1U)

#define	EXTI_RTSR2_TR33_Msk (0x1UL << EXTI_RTSR2_TR33_Pos)

#define	EXTI_RTSR2_TR33 EXTI_RTSR2_TR33_Msk

#define	EXTI_RTSR2_RT32 EXTI_RTSR2_TR32

#define	EXTI_RTSR2_RT33 EXTI_RTSR2_TR33

#define	EXTI_FTSR2_TR32_Pos (0U)

#define	EXTI_FTSR2_TR32_Msk (0x1UL << EXTI_FTSR2_TR32_Pos)

#define	EXTI_FTSR2_TR32 EXTI_FTSR2_TR32_Msk

#define	EXTI_FTSR2_TR33_Pos (1U)

#define	EXTI_FTSR2_TR33_Msk (0x1UL << EXTI_FTSR2_TR33_Pos)

#define	EXTI_FTSR2_TR33 EXTI_FTSR2_TR33_Msk

#define	EXTI_FTSR2_FT32 EXTI_FTSR2_TR32

#define	EXTI_FTSR2_FT33 EXTI_FTSR2_TR33

#define	EXTI_SWIER2_SWIER32_Pos (0U)

#define	EXTI_SWIER2_SWIER32_Msk (0x1UL << EXTI_SWIER2_SWIER32_Pos)

#define	EXTI_SWIER2_SWIER32 EXTI_SWIER2_SWIER32_Msk

#define	EXTI_SWIER2_SWIER33_Pos (1U)

#define	EXTI_SWIER2_SWIER33_Msk (0x1UL << EXTI_SWIER2_SWIER33_Pos)

#define	EXTI_SWIER2_SWIER33 EXTI_SWIER2_SWIER33_Msk

#define	EXTI_SWIER2_SWI32 EXTI_SWIER2_SWIER32

#define	EXTI_SWIER2_SWI33 EXTI_SWIER2_SWIER33

#define	EXTI_PR2_PR32_Pos (0U)

#define	EXTI_PR2_PR32_Msk (0x1UL << EXTI_PR2_PR32_Pos)

#define	EXTI_PR2_PR32 EXTI_PR2_PR32_Msk

#define	EXTI_PR2_PR33_Pos (1U)

#define	EXTI_PR2_PR33_Msk (0x1UL << EXTI_PR2_PR33_Pos)

#define	EXTI_PR2_PR33 EXTI_PR2_PR33_Msk

#define	EXTI_PR2_PIF32 EXTI_PR2_PR32

#define	EXTI_PR2_PIF33 EXTI_PR2_PR33

#define	FLASH_ACR_LATENCY_Pos (0U)

#define	FLASH_ACR_LATENCY_Msk (0x7UL << FLASH_ACR_LATENCY_Pos)

#define	FLASH_ACR_LATENCY FLASH_ACR_LATENCY_Msk

#define	FLASH_ACR_LATENCY_0 (0x1UL << FLASH_ACR_LATENCY_Pos)

#define	FLASH_ACR_LATENCY_1 (0x2UL << FLASH_ACR_LATENCY_Pos)

#define	FLASH_ACR_LATENCY_2 (0x4UL << FLASH_ACR_LATENCY_Pos)

#define	FLASH_ACR_HLFCYA_Pos (3U)

#define	FLASH_ACR_HLFCYA_Msk (0x1UL << FLASH_ACR_HLFCYA_Pos)

#define	FLASH_ACR_HLFCYA FLASH_ACR_HLFCYA_Msk

#define	FLASH_ACR_PRFTBE_Pos (4U)

#define	FLASH_ACR_PRFTBE_Msk (0x1UL << FLASH_ACR_PRFTBE_Pos)

#define	FLASH_ACR_PRFTBE FLASH_ACR_PRFTBE_Msk

#define	FLASH_ACR_PRFTBS_Pos (5U)

#define	FLASH_ACR_PRFTBS_Msk (0x1UL << FLASH_ACR_PRFTBS_Pos)

#define	FLASH_ACR_PRFTBS FLASH_ACR_PRFTBS_Msk

#define	FLASH_KEYR_FKEYR_Pos (0U)

#define	FLASH_KEYR_FKEYR_Msk (0xFFFFFFFFUL << FLASH_KEYR_FKEYR_Pos)

#define	FLASH_KEYR_FKEYR FLASH_KEYR_FKEYR_Msk

#define	RDP_KEY_Pos (0U)

#define	RDP_KEY_Msk (0xA5UL << RDP_KEY_Pos)

#define	RDP_KEY RDP_KEY_Msk

#define	FLASH_KEY1_Pos (0U)

#define	FLASH_KEY1_Msk (0x45670123UL << FLASH_KEY1_Pos)

#define	FLASH_KEY1 FLASH_KEY1_Msk

#define	FLASH_KEY2_Pos (0U)

#define	FLASH_KEY2_Msk (0xCDEF89ABUL << FLASH_KEY2_Pos)

#define	FLASH_KEY2 FLASH_KEY2_Msk

#define	FLASH_OPTKEYR_OPTKEYR_Pos (0U)

#define	FLASH_OPTKEYR_OPTKEYR_Msk (0xFFFFFFFFUL << FLASH_OPTKEYR_OPTKEYR_Pos)

#define	FLASH_OPTKEYR_OPTKEYR FLASH_OPTKEYR_OPTKEYR_Msk

#define	FLASH_OPTKEY1 FLASH_KEY1

#define	FLASH_OPTKEY2 FLASH_KEY2

#define	FLASH_SR_BSY_Pos (0U)

#define	FLASH_SR_BSY_Msk (0x1UL << FLASH_SR_BSY_Pos)

#define	FLASH_SR_BSY FLASH_SR_BSY_Msk

#define	FLASH_SR_PGERR_Pos (2U)

#define	FLASH_SR_PGERR_Msk (0x1UL << FLASH_SR_PGERR_Pos)

#define	FLASH_SR_PGERR FLASH_SR_PGERR_Msk

#define	FLASH_SR_WRPERR_Pos (4U)

#define	FLASH_SR_WRPERR_Msk (0x1UL << FLASH_SR_WRPERR_Pos)

#define	FLASH_SR_WRPERR FLASH_SR_WRPERR_Msk

#define	FLASH_SR_EOP_Pos (5U)

#define	FLASH_SR_EOP_Msk (0x1UL << FLASH_SR_EOP_Pos)

#define	FLASH_SR_EOP FLASH_SR_EOP_Msk

#define	FLASH_CR_PG_Pos (0U)

#define	FLASH_CR_PG_Msk (0x1UL << FLASH_CR_PG_Pos)

#define	FLASH_CR_PG FLASH_CR_PG_Msk

#define	FLASH_CR_PER_Pos (1U)

#define	FLASH_CR_PER_Msk (0x1UL << FLASH_CR_PER_Pos)

#define	FLASH_CR_PER FLASH_CR_PER_Msk

#define	FLASH_CR_MER_Pos (2U)

#define	FLASH_CR_MER_Msk (0x1UL << FLASH_CR_MER_Pos)

#define	FLASH_CR_MER FLASH_CR_MER_Msk

#define	FLASH_CR_OPTPG_Pos (4U)

#define	FLASH_CR_OPTPG_Msk (0x1UL << FLASH_CR_OPTPG_Pos)

#define	FLASH_CR_OPTPG FLASH_CR_OPTPG_Msk

#define	FLASH_CR_OPTER_Pos (5U)

#define	FLASH_CR_OPTER_Msk (0x1UL << FLASH_CR_OPTER_Pos)

#define	FLASH_CR_OPTER FLASH_CR_OPTER_Msk

#define	FLASH_CR_STRT_Pos (6U)

#define	FLASH_CR_STRT_Msk (0x1UL << FLASH_CR_STRT_Pos)

#define	FLASH_CR_STRT FLASH_CR_STRT_Msk

#define	FLASH_CR_LOCK_Pos (7U)

#define	FLASH_CR_LOCK_Msk (0x1UL << FLASH_CR_LOCK_Pos)

#define	FLASH_CR_LOCK FLASH_CR_LOCK_Msk

#define	FLASH_CR_OPTWRE_Pos (9U)

#define	FLASH_CR_OPTWRE_Msk (0x1UL << FLASH_CR_OPTWRE_Pos)

#define	FLASH_CR_OPTWRE FLASH_CR_OPTWRE_Msk

#define	FLASH_CR_ERRIE_Pos (10U)

#define	FLASH_CR_ERRIE_Msk (0x1UL << FLASH_CR_ERRIE_Pos)

#define	FLASH_CR_ERRIE FLASH_CR_ERRIE_Msk

#define	FLASH_CR_EOPIE_Pos (12U)

#define	FLASH_CR_EOPIE_Msk (0x1UL << FLASH_CR_EOPIE_Pos)

#define	FLASH_CR_EOPIE FLASH_CR_EOPIE_Msk

#define	FLASH_CR_OBL_LAUNCH_Pos (13U)

#define	FLASH_CR_OBL_LAUNCH_Msk (0x1UL << FLASH_CR_OBL_LAUNCH_Pos)

#define	FLASH_CR_OBL_LAUNCH FLASH_CR_OBL_LAUNCH_Msk

#define	FLASH_AR_FAR_Pos (0U)

#define	FLASH_AR_FAR_Msk (0xFFFFFFFFUL << FLASH_AR_FAR_Pos)

#define	FLASH_AR_FAR FLASH_AR_FAR_Msk

#define	FLASH_OBR_OPTERR_Pos (0U)

#define	FLASH_OBR_OPTERR_Msk (0x1UL << FLASH_OBR_OPTERR_Pos)

#define	FLASH_OBR_OPTERR FLASH_OBR_OPTERR_Msk

#define	FLASH_OBR_RDPRT_Pos (1U)

#define	FLASH_OBR_RDPRT_Msk (0x3UL << FLASH_OBR_RDPRT_Pos)

#define	FLASH_OBR_RDPRT FLASH_OBR_RDPRT_Msk

#define	FLASH_OBR_RDPRT_1 (0x1UL << FLASH_OBR_RDPRT_Pos)

#define	FLASH_OBR_RDPRT_2 (0x3UL << FLASH_OBR_RDPRT_Pos)

#define	FLASH_OBR_USER_Pos (8U)

#define	FLASH_OBR_USER_Msk (0x77UL << FLASH_OBR_USER_Pos)

#define	FLASH_OBR_USER FLASH_OBR_USER_Msk

#define	FLASH_OBR_IWDG_SW_Pos (8U)

#define	FLASH_OBR_IWDG_SW_Msk (0x1UL << FLASH_OBR_IWDG_SW_Pos)

#define	FLASH_OBR_IWDG_SW FLASH_OBR_IWDG_SW_Msk

#define	FLASH_OBR_nRST_STOP_Pos (9U)

#define	FLASH_OBR_nRST_STOP_Msk (0x1UL << FLASH_OBR_nRST_STOP_Pos)

#define	FLASH_OBR_nRST_STOP FLASH_OBR_nRST_STOP_Msk

#define	FLASH_OBR_nRST_STDBY_Pos (10U)

#define	FLASH_OBR_nRST_STDBY_Msk (0x1UL << FLASH_OBR_nRST_STDBY_Pos)

#define	FLASH_OBR_nRST_STDBY FLASH_OBR_nRST_STDBY_Msk

#define	FLASH_OBR_nBOOT1_Pos (12U)

#define	FLASH_OBR_nBOOT1_Msk (0x1UL << FLASH_OBR_nBOOT1_Pos)

#define	FLASH_OBR_nBOOT1 FLASH_OBR_nBOOT1_Msk

#define	FLASH_OBR_VDDA_MONITOR_Pos (13U)

#define	FLASH_OBR_VDDA_MONITOR_Msk (0x1UL << FLASH_OBR_VDDA_MONITOR_Pos)

#define	FLASH_OBR_VDDA_MONITOR FLASH_OBR_VDDA_MONITOR_Msk

#define	FLASH_OBR_SRAM_PE_Pos (14U)

#define	FLASH_OBR_SRAM_PE_Msk (0x1UL << FLASH_OBR_SRAM_PE_Pos)

#define	FLASH_OBR_SRAM_PE FLASH_OBR_SRAM_PE_Msk

#define	FLASH_OBR_DATA0_Pos (16U)

#define	FLASH_OBR_DATA0_Msk (0xFFUL << FLASH_OBR_DATA0_Pos)

#define	FLASH_OBR_DATA0 FLASH_OBR_DATA0_Msk

#define	FLASH_OBR_DATA1_Pos (24U)

#define	FLASH_OBR_DATA1_Msk (0xFFUL << FLASH_OBR_DATA1_Pos)

#define	FLASH_OBR_DATA1 FLASH_OBR_DATA1_Msk

#define	FLASH_OBR_WDG_SW FLASH_OBR_IWDG_SW

#define	FLASH_WRPR_WRP_Pos (0U)

#define	FLASH_WRPR_WRP_Msk (0xFFFFFFFFUL << FLASH_WRPR_WRP_Pos)

#define	FLASH_WRPR_WRP FLASH_WRPR_WRP_Msk

#define	OB_RDP_RDP_Pos (0U)

#define	OB_RDP_RDP_Msk (0xFFUL << OB_RDP_RDP_Pos)

#define	OB_RDP_RDP OB_RDP_RDP_Msk

#define	OB_RDP_nRDP_Pos (8U)

#define	OB_RDP_nRDP_Msk (0xFFUL << OB_RDP_nRDP_Pos)

#define	OB_RDP_nRDP OB_RDP_nRDP_Msk

#define	OB_USER_USER_Pos (16U)

#define	OB_USER_USER_Msk (0xFFUL << OB_USER_USER_Pos)

#define	OB_USER_USER OB_USER_USER_Msk

#define	OB_USER_nUSER_Pos (24U)

#define	OB_USER_nUSER_Msk (0xFFUL << OB_USER_nUSER_Pos)

#define	OB_USER_nUSER OB_USER_nUSER_Msk

#define	OB_WRP0_WRP0_Pos (0U)

#define	OB_WRP0_WRP0_Msk (0xFFUL << OB_WRP0_WRP0_Pos)

#define	OB_WRP0_WRP0 OB_WRP0_WRP0_Msk

#define	OB_WRP0_nWRP0_Pos (8U)

#define	OB_WRP0_nWRP0_Msk (0xFFUL << OB_WRP0_nWRP0_Pos)

#define	OB_WRP0_nWRP0 OB_WRP0_nWRP0_Msk

#define	OB_WRP1_WRP1_Pos (16U)

#define	OB_WRP1_WRP1_Msk (0xFFUL << OB_WRP1_WRP1_Pos)

#define	OB_WRP1_WRP1 OB_WRP1_WRP1_Msk

#define	OB_WRP1_nWRP1_Pos (24U)

#define	OB_WRP1_nWRP1_Msk (0xFFUL << OB_WRP1_nWRP1_Pos)

#define	OB_WRP1_nWRP1 OB_WRP1_nWRP1_Msk

#define	OB_WRP2_WRP2_Pos (0U)

#define	OB_WRP2_WRP2_Msk (0xFFUL << OB_WRP2_WRP2_Pos)

#define	OB_WRP2_WRP2 OB_WRP2_WRP2_Msk

#define	OB_WRP2_nWRP2_Pos (8U)

#define	OB_WRP2_nWRP2_Msk (0xFFUL << OB_WRP2_nWRP2_Pos)

#define	OB_WRP2_nWRP2 OB_WRP2_nWRP2_Msk

#define	OB_WRP3_WRP3_Pos (16U)

#define	OB_WRP3_WRP3_Msk (0xFFUL << OB_WRP3_WRP3_Pos)

#define	OB_WRP3_WRP3 OB_WRP3_WRP3_Msk

#define	OB_WRP3_nWRP3_Pos (24U)

#define	OB_WRP3_nWRP3_Msk (0xFFUL << OB_WRP3_nWRP3_Pos)

#define	OB_WRP3_nWRP3 OB_WRP3_nWRP3_Msk

#define	FMC_BCRx_MBKEN_Pos (0U)

#define	FMC_BCRx_MBKEN_Msk (0x1UL << FMC_BCRx_MBKEN_Pos)

#define	FMC_BCRx_MBKEN FMC_BCRx_MBKEN_Msk

#define	FMC_BCRx_MUXEN_Pos (1U)

#define	FMC_BCRx_MUXEN_Msk (0x1UL << FMC_BCRx_MUXEN_Pos)

#define	FMC_BCRx_MUXEN FMC_BCRx_MUXEN_Msk

#define	FMC_BCRx_MTYP_Pos (2U)

#define	FMC_BCRx_MTYP_Msk (0x3UL << FMC_BCRx_MTYP_Pos)

#define	FMC_BCRx_MTYP FMC_BCRx_MTYP_Msk

#define	FMC_BCRx_MTYP_0 (0x1UL << FMC_BCRx_MTYP_Pos)

#define	FMC_BCRx_MTYP_1 (0x2UL << FMC_BCRx_MTYP_Pos)

#define	FMC_BCRx_MWID_Pos (4U)

#define	FMC_BCRx_MWID_Msk (0x3UL << FMC_BCRx_MWID_Pos)

#define	FMC_BCRx_MWID FMC_BCRx_MWID_Msk

#define	FMC_BCRx_MWID_0 (0x1UL << FMC_BCRx_MWID_Pos)

#define	FMC_BCRx_MWID_1 (0x2UL << FMC_BCRx_MWID_Pos)

#define	FMC_BCRx_FACCEN_Pos (6U)

#define	FMC_BCRx_FACCEN_Msk (0x1UL << FMC_BCRx_FACCEN_Pos)

#define	FMC_BCRx_FACCEN FMC_BCRx_FACCEN_Msk

#define	FMC_BCRx_BURSTEN_Pos (8U)

#define	FMC_BCRx_BURSTEN_Msk (0x1UL << FMC_BCRx_BURSTEN_Pos)

#define	FMC_BCRx_BURSTEN FMC_BCRx_BURSTEN_Msk

#define	FMC_BCRx_WAITPOL_Pos (9U)

#define	FMC_BCRx_WAITPOL_Msk (0x1UL << FMC_BCRx_WAITPOL_Pos)

#define	FMC_BCRx_WAITPOL FMC_BCRx_WAITPOL_Msk

#define	FMC_BCRx_WRAPMOD_Pos (10U)

#define	FMC_BCRx_WRAPMOD_Msk (0x1UL << FMC_BCRx_WRAPMOD_Pos)

#define	FMC_BCRx_WRAPMOD FMC_BCRx_WRAPMOD_Msk

#define	FMC_BCRx_WAITCFG_Pos (11U)

#define	FMC_BCRx_WAITCFG_Msk (0x1UL << FMC_BCRx_WAITCFG_Pos)

#define	FMC_BCRx_WAITCFG FMC_BCRx_WAITCFG_Msk

#define	FMC_BCRx_WREN_Pos (12U)

#define	FMC_BCRx_WREN_Msk (0x1UL << FMC_BCRx_WREN_Pos)

#define	FMC_BCRx_WREN FMC_BCRx_WREN_Msk

#define	FMC_BCRx_WAITEN_Pos (13U)

#define	FMC_BCRx_WAITEN_Msk (0x1UL << FMC_BCRx_WAITEN_Pos)

#define	FMC_BCRx_WAITEN FMC_BCRx_WAITEN_Msk

#define	FMC_BCRx_EXTMOD_Pos (14U)

#define	FMC_BCRx_EXTMOD_Msk (0x1UL << FMC_BCRx_EXTMOD_Pos)

#define	FMC_BCRx_EXTMOD FMC_BCRx_EXTMOD_Msk

#define	FMC_BCRx_ASYNCWAIT_Pos (15U)

#define	FMC_BCRx_ASYNCWAIT_Msk (0x1UL << FMC_BCRx_ASYNCWAIT_Pos)

#define	FMC_BCRx_ASYNCWAIT FMC_BCRx_ASYNCWAIT_Msk

#define	FMC_BCRx_CBURSTRW_Pos (19U)

#define	FMC_BCRx_CBURSTRW_Msk (0x1UL << FMC_BCRx_CBURSTRW_Pos)

#define	FMC_BCRx_CBURSTRW FMC_BCRx_CBURSTRW_Msk

#define	FMC_BCR1_MBKEN_Pos (0U)

#define	FMC_BCR1_MBKEN_Msk (0x1UL << FMC_BCR1_MBKEN_Pos)

#define	FMC_BCR1_MBKEN FMC_BCR1_MBKEN_Msk

#define	FMC_BCR1_MUXEN_Pos (1U)

#define	FMC_BCR1_MUXEN_Msk (0x1UL << FMC_BCR1_MUXEN_Pos)

#define	FMC_BCR1_MUXEN FMC_BCR1_MUXEN_Msk

#define	FMC_BCR1_MTYP_Pos (2U)

#define	FMC_BCR1_MTYP_Msk (0x3UL << FMC_BCR1_MTYP_Pos)

#define	FMC_BCR1_MTYP FMC_BCR1_MTYP_Msk

#define	FMC_BCR1_MTYP_0 (0x1UL << FMC_BCR1_MTYP_Pos)

#define	FMC_BCR1_MTYP_1 (0x2UL << FMC_BCR1_MTYP_Pos)

#define	FMC_BCR1_MWID_Pos (4U)

#define	FMC_BCR1_MWID_Msk (0x3UL << FMC_BCR1_MWID_Pos)

#define	FMC_BCR1_MWID FMC_BCR1_MWID_Msk

#define	FMC_BCR1_MWID_0 (0x1UL << FMC_BCR1_MWID_Pos)

#define	FMC_BCR1_MWID_1 (0x2UL << FMC_BCR1_MWID_Pos)

#define	FMC_BCR1_FACCEN_Pos (6U)

#define	FMC_BCR1_FACCEN_Msk (0x1UL << FMC_BCR1_FACCEN_Pos)

#define	FMC_BCR1_FACCEN FMC_BCR1_FACCEN_Msk

#define	FMC_BCR1_BURSTEN_Pos (8U)

#define	FMC_BCR1_BURSTEN_Msk (0x1UL << FMC_BCR1_BURSTEN_Pos)

#define	FMC_BCR1_BURSTEN FMC_BCR1_BURSTEN_Msk

#define	FMC_BCR1_WAITPOL_Pos (9U)

#define	FMC_BCR1_WAITPOL_Msk (0x1UL << FMC_BCR1_WAITPOL_Pos)

#define	FMC_BCR1_WAITPOL FMC_BCR1_WAITPOL_Msk

#define	FMC_BCR1_WRAPMOD_Pos (10U)

#define	FMC_BCR1_WRAPMOD_Msk (0x1UL << FMC_BCR1_WRAPMOD_Pos)

#define	FMC_BCR1_WRAPMOD FMC_BCR1_WRAPMOD_Msk

#define	FMC_BCR1_WAITCFG_Pos (11U)

#define	FMC_BCR1_WAITCFG_Msk (0x1UL << FMC_BCR1_WAITCFG_Pos)

#define	FMC_BCR1_WAITCFG FMC_BCR1_WAITCFG_Msk

#define	FMC_BCR1_WREN_Pos (12U)

#define	FMC_BCR1_WREN_Msk (0x1UL << FMC_BCR1_WREN_Pos)

#define	FMC_BCR1_WREN FMC_BCR1_WREN_Msk

#define	FMC_BCR1_WAITEN_Pos (13U)

#define	FMC_BCR1_WAITEN_Msk (0x1UL << FMC_BCR1_WAITEN_Pos)

#define	FMC_BCR1_WAITEN FMC_BCR1_WAITEN_Msk

#define	FMC_BCR1_EXTMOD_Pos (14U)

#define	FMC_BCR1_EXTMOD_Msk (0x1UL << FMC_BCR1_EXTMOD_Pos)

#define	FMC_BCR1_EXTMOD FMC_BCR1_EXTMOD_Msk

#define	FMC_BCR1_ASYNCWAIT_Pos (15U)

#define	FMC_BCR1_ASYNCWAIT_Msk (0x1UL << FMC_BCR1_ASYNCWAIT_Pos)

#define	FMC_BCR1_ASYNCWAIT FMC_BCR1_ASYNCWAIT_Msk

#define	FMC_BCR1_CBURSTRW_Pos (19U)

#define	FMC_BCR1_CBURSTRW_Msk (0x1UL << FMC_BCR1_CBURSTRW_Pos)

#define	FMC_BCR1_CBURSTRW FMC_BCR1_CBURSTRW_Msk

#define	FMC_BCR1_CCLKEN_Pos (20U)

#define	FMC_BCR1_CCLKEN_Msk (0x1UL << FMC_BCR1_CCLKEN_Pos)

#define	FMC_BCR1_CCLKEN FMC_BCR1_CCLKEN_Msk

#define	FMC_BCR2_MBKEN_Pos (0U)

#define	FMC_BCR2_MBKEN_Msk (0x1UL << FMC_BCR2_MBKEN_Pos)

#define	FMC_BCR2_MBKEN FMC_BCR2_MBKEN_Msk

#define	FMC_BCR2_MUXEN_Pos (1U)

#define	FMC_BCR2_MUXEN_Msk (0x1UL << FMC_BCR2_MUXEN_Pos)

#define	FMC_BCR2_MUXEN FMC_BCR2_MUXEN_Msk

#define	FMC_BCR2_MTYP_Pos (2U)

#define	FMC_BCR2_MTYP_Msk (0x3UL << FMC_BCR2_MTYP_Pos)

#define	FMC_BCR2_MTYP FMC_BCR2_MTYP_Msk

#define	FMC_BCR2_MTYP_0 (0x1UL << FMC_BCR2_MTYP_Pos)

#define	FMC_BCR2_MTYP_1 (0x2UL << FMC_BCR2_MTYP_Pos)

#define	FMC_BCR2_MWID_Pos (4U)

#define	FMC_BCR2_MWID_Msk (0x3UL << FMC_BCR2_MWID_Pos)

#define	FMC_BCR2_MWID FMC_BCR2_MWID_Msk

#define	FMC_BCR2_MWID_0 (0x1UL << FMC_BCR2_MWID_Pos)

#define	FMC_BCR2_MWID_1 (0x2UL << FMC_BCR2_MWID_Pos)

#define	FMC_BCR2_FACCEN_Pos (6U)

#define	FMC_BCR2_FACCEN_Msk (0x1UL << FMC_BCR2_FACCEN_Pos)

#define	FMC_BCR2_FACCEN FMC_BCR2_FACCEN_Msk

#define	FMC_BCR2_BURSTEN_Pos (8U)

#define	FMC_BCR2_BURSTEN_Msk (0x1UL << FMC_BCR2_BURSTEN_Pos)

#define	FMC_BCR2_BURSTEN FMC_BCR2_BURSTEN_Msk

#define	FMC_BCR2_WAITPOL_Pos (9U)

#define	FMC_BCR2_WAITPOL_Msk (0x1UL << FMC_BCR2_WAITPOL_Pos)

#define	FMC_BCR2_WAITPOL FMC_BCR2_WAITPOL_Msk

#define	FMC_BCR2_WRAPMOD_Pos (10U)

#define	FMC_BCR2_WRAPMOD_Msk (0x1UL << FMC_BCR2_WRAPMOD_Pos)

#define	FMC_BCR2_WRAPMOD FMC_BCR2_WRAPMOD_Msk

#define	FMC_BCR2_WAITCFG_Pos (11U)

#define	FMC_BCR2_WAITCFG_Msk (0x1UL << FMC_BCR2_WAITCFG_Pos)

#define	FMC_BCR2_WAITCFG FMC_BCR2_WAITCFG_Msk

#define	FMC_BCR2_WREN_Pos (12U)

#define	FMC_BCR2_WREN_Msk (0x1UL << FMC_BCR2_WREN_Pos)

#define	FMC_BCR2_WREN FMC_BCR2_WREN_Msk

#define	FMC_BCR2_WAITEN_Pos (13U)

#define	FMC_BCR2_WAITEN_Msk (0x1UL << FMC_BCR2_WAITEN_Pos)

#define	FMC_BCR2_WAITEN FMC_BCR2_WAITEN_Msk

#define	FMC_BCR2_EXTMOD_Pos (14U)

#define	FMC_BCR2_EXTMOD_Msk (0x1UL << FMC_BCR2_EXTMOD_Pos)

#define	FMC_BCR2_EXTMOD FMC_BCR2_EXTMOD_Msk

#define	FMC_BCR2_ASYNCWAIT_Pos (15U)

#define	FMC_BCR2_ASYNCWAIT_Msk (0x1UL << FMC_BCR2_ASYNCWAIT_Pos)

#define	FMC_BCR2_ASYNCWAIT FMC_BCR2_ASYNCWAIT_Msk

#define	FMC_BCR2_CBURSTRW_Pos (19U)

#define	FMC_BCR2_CBURSTRW_Msk (0x1UL << FMC_BCR2_CBURSTRW_Pos)

#define	FMC_BCR2_CBURSTRW FMC_BCR2_CBURSTRW_Msk

#define	FMC_BCR3_MBKEN_Pos (0U)

#define	FMC_BCR3_MBKEN_Msk (0x1UL << FMC_BCR3_MBKEN_Pos)

#define	FMC_BCR3_MBKEN FMC_BCR3_MBKEN_Msk

#define	FMC_BCR3_MUXEN_Pos (1U)

#define	FMC_BCR3_MUXEN_Msk (0x1UL << FMC_BCR3_MUXEN_Pos)

#define	FMC_BCR3_MUXEN FMC_BCR3_MUXEN_Msk

#define	FMC_BCR3_MTYP_Pos (2U)

#define	FMC_BCR3_MTYP_Msk (0x3UL << FMC_BCR3_MTYP_Pos)

#define	FMC_BCR3_MTYP FMC_BCR3_MTYP_Msk

#define	FMC_BCR3_MTYP_0 (0x1UL << FMC_BCR3_MTYP_Pos)

#define	FMC_BCR3_MTYP_1 (0x2UL << FMC_BCR3_MTYP_Pos)

#define	FMC_BCR3_MWID_Pos (4U)

#define	FMC_BCR3_MWID_Msk (0x3UL << FMC_BCR3_MWID_Pos)

#define	FMC_BCR3_MWID FMC_BCR3_MWID_Msk

#define	FMC_BCR3_MWID_0 (0x1UL << FMC_BCR3_MWID_Pos)

#define	FMC_BCR3_MWID_1 (0x2UL << FMC_BCR3_MWID_Pos)

#define	FMC_BCR3_FACCEN_Pos (6U)

#define	FMC_BCR3_FACCEN_Msk (0x1UL << FMC_BCR3_FACCEN_Pos)

#define	FMC_BCR3_FACCEN FMC_BCR3_FACCEN_Msk

#define	FMC_BCR3_BURSTEN_Pos (8U)

#define	FMC_BCR3_BURSTEN_Msk (0x1UL << FMC_BCR3_BURSTEN_Pos)

#define	FMC_BCR3_BURSTEN FMC_BCR3_BURSTEN_Msk

#define	FMC_BCR3_WAITPOL_Pos (9U)

#define	FMC_BCR3_WAITPOL_Msk (0x1UL << FMC_BCR3_WAITPOL_Pos)

#define	FMC_BCR3_WAITPOL FMC_BCR3_WAITPOL_Msk

#define	FMC_BCR3_WRAPMOD_Pos (10U)

#define	FMC_BCR3_WRAPMOD_Msk (0x1UL << FMC_BCR3_WRAPMOD_Pos)

#define	FMC_BCR3_WRAPMOD FMC_BCR3_WRAPMOD_Msk

#define	FMC_BCR3_WAITCFG_Pos (11U)

#define	FMC_BCR3_WAITCFG_Msk (0x1UL << FMC_BCR3_WAITCFG_Pos)

#define	FMC_BCR3_WAITCFG FMC_BCR3_WAITCFG_Msk

#define	FMC_BCR3_WREN_Pos (12U)

#define	FMC_BCR3_WREN_Msk (0x1UL << FMC_BCR3_WREN_Pos)

#define	FMC_BCR3_WREN FMC_BCR3_WREN_Msk

#define	FMC_BCR3_WAITEN_Pos (13U)

#define	FMC_BCR3_WAITEN_Msk (0x1UL << FMC_BCR3_WAITEN_Pos)

#define	FMC_BCR3_WAITEN FMC_BCR3_WAITEN_Msk

#define	FMC_BCR3_EXTMOD_Pos (14U)

#define	FMC_BCR3_EXTMOD_Msk (0x1UL << FMC_BCR3_EXTMOD_Pos)

#define	FMC_BCR3_EXTMOD FMC_BCR3_EXTMOD_Msk

#define	FMC_BCR3_ASYNCWAIT_Pos (15U)

#define	FMC_BCR3_ASYNCWAIT_Msk (0x1UL << FMC_BCR3_ASYNCWAIT_Pos)

#define	FMC_BCR3_ASYNCWAIT FMC_BCR3_ASYNCWAIT_Msk

#define	FMC_BCR3_CBURSTRW_Pos (19U)

#define	FMC_BCR3_CBURSTRW_Msk (0x1UL << FMC_BCR3_CBURSTRW_Pos)

#define	FMC_BCR3_CBURSTRW FMC_BCR3_CBURSTRW_Msk

#define	FMC_BCR4_MBKEN_Pos (0U)

#define	FMC_BCR4_MBKEN_Msk (0x1UL << FMC_BCR4_MBKEN_Pos)

#define	FMC_BCR4_MBKEN FMC_BCR4_MBKEN_Msk

#define	FMC_BCR4_MUXEN_Pos (1U)

#define	FMC_BCR4_MUXEN_Msk (0x1UL << FMC_BCR4_MUXEN_Pos)

#define	FMC_BCR4_MUXEN FMC_BCR4_MUXEN_Msk

#define	FMC_BCR4_MTYP_Pos (2U)

#define	FMC_BCR4_MTYP_Msk (0x3UL << FMC_BCR4_MTYP_Pos)

#define	FMC_BCR4_MTYP FMC_BCR4_MTYP_Msk

#define	FMC_BCR4_MTYP_0 (0x1UL << FMC_BCR4_MTYP_Pos)

#define	FMC_BCR4_MTYP_1 (0x2UL << FMC_BCR4_MTYP_Pos)

#define	FMC_BCR4_MWID_Pos (4U)

#define	FMC_BCR4_MWID_Msk (0x3UL << FMC_BCR4_MWID_Pos)

#define	FMC_BCR4_MWID FMC_BCR4_MWID_Msk

#define	FMC_BCR4_MWID_0 (0x1UL << FMC_BCR4_MWID_Pos)

#define	FMC_BCR4_MWID_1 (0x2UL << FMC_BCR4_MWID_Pos)

#define	FMC_BCR4_FACCEN_Pos (6U)

#define	FMC_BCR4_FACCEN_Msk (0x1UL << FMC_BCR4_FACCEN_Pos)

#define	FMC_BCR4_FACCEN FMC_BCR4_FACCEN_Msk

#define	FMC_BCR4_BURSTEN_Pos (8U)

#define	FMC_BCR4_BURSTEN_Msk (0x1UL << FMC_BCR4_BURSTEN_Pos)

#define	FMC_BCR4_BURSTEN FMC_BCR4_BURSTEN_Msk

#define	FMC_BCR4_WAITPOL_Pos (9U)

#define	FMC_BCR4_WAITPOL_Msk (0x1UL << FMC_BCR4_WAITPOL_Pos)

#define	FMC_BCR4_WAITPOL FMC_BCR4_WAITPOL_Msk

#define	FMC_BCR4_WRAPMOD_Pos (10U)

#define	FMC_BCR4_WRAPMOD_Msk (0x1UL << FMC_BCR4_WRAPMOD_Pos)

#define	FMC_BCR4_WRAPMOD FMC_BCR4_WRAPMOD_Msk

#define	FMC_BCR4_WAITCFG_Pos (11U)

#define	FMC_BCR4_WAITCFG_Msk (0x1UL << FMC_BCR4_WAITCFG_Pos)

#define	FMC_BCR4_WAITCFG FMC_BCR4_WAITCFG_Msk

#define	FMC_BCR4_WREN_Pos (12U)

#define	FMC_BCR4_WREN_Msk (0x1UL << FMC_BCR4_WREN_Pos)

#define	FMC_BCR4_WREN FMC_BCR4_WREN_Msk

#define	FMC_BCR4_WAITEN_Pos (13U)

#define	FMC_BCR4_WAITEN_Msk (0x1UL << FMC_BCR4_WAITEN_Pos)

#define	FMC_BCR4_WAITEN FMC_BCR4_WAITEN_Msk

#define	FMC_BCR4_EXTMOD_Pos (14U)

#define	FMC_BCR4_EXTMOD_Msk (0x1UL << FMC_BCR4_EXTMOD_Pos)

#define	FMC_BCR4_EXTMOD FMC_BCR4_EXTMOD_Msk

#define	FMC_BCR4_ASYNCWAIT_Pos (15U)

#define	FMC_BCR4_ASYNCWAIT_Msk (0x1UL << FMC_BCR4_ASYNCWAIT_Pos)

#define	FMC_BCR4_ASYNCWAIT FMC_BCR4_ASYNCWAIT_Msk

#define	FMC_BCR4_CBURSTRW_Pos (19U)

#define	FMC_BCR4_CBURSTRW_Msk (0x1UL << FMC_BCR4_CBURSTRW_Pos)

#define	FMC_BCR4_CBURSTRW FMC_BCR4_CBURSTRW_Msk

#define	FMC_BTRx_ADDSET_Pos (0U)

#define	FMC_BTRx_ADDSET_Msk (0xFUL << FMC_BTRx_ADDSET_Pos)

#define	FMC_BTRx_ADDSET FMC_BTRx_ADDSET_Msk

#define	FMC_BTRx_ADDSET_0 (0x1UL << FMC_BTRx_ADDSET_Pos)

#define	FMC_BTRx_ADDSET_1 (0x2UL << FMC_BTRx_ADDSET_Pos)

#define	FMC_BTRx_ADDSET_2 (0x4UL << FMC_BTRx_ADDSET_Pos)

#define	FMC_BTR_ADDSET_3 (0x00000008U)

#define	FMC_BTRx_ADDHLD_Pos (4U)

#define	FMC_BTRx_ADDHLD_Msk (0xFUL << FMC_BTRx_ADDHLD_Pos)

#define	FMC_BTRx_ADDHLD FMC_BTRx_ADDHLD_Msk

#define	FMC_BTRx_ADDHLD_0 (0x1UL << FMC_BTRx_ADDHLD_Pos)

#define	FMC_BTRx_ADDHLD_1 (0x2UL << FMC_BTRx_ADDHLD_Pos)

#define	FMC_BTRx_ADDHLD_2 (0x4UL << FMC_BTRx_ADDHLD_Pos)

#define	FMC_BTRx_ADDHLD_3 (0x8UL << FMC_BTRx_ADDHLD_Pos)

#define	FMC_BTRx_DATAST_Pos (8U)

#define	FMC_BTRx_DATAST_Msk (0xFFUL << FMC_BTRx_DATAST_Pos)

#define	FMC_BTRx_DATAST FMC_BTRx_DATAST_Msk

#define	FMC_BTR_DATAST_0 (0x00000100U)

#define	FMC_BTRx_DATAST_1 (0x00000200U)

#define	FMC_BTRx_DATAST_2 (0x00000400U)

#define	FMC_BTRx_DATAST_3 (0x00000800U)

#define	FMC_BTRx_DATAST_4 (0x00001000U)

#define	FMC_BTRx_DATAST_5 (0x00002000U)

#define	FMC_BTRx_DATAST_6 (0x00004000U)

#define	FMC_BTRx_DATAST_7 (0x00008000U)

#define	FMC_BTRx_BUSTURN_Pos (16U)

#define	FMC_BTRx_BUSTURN_Msk (0xFUL << FMC_BTRx_BUSTURN_Pos)

#define	FMC_BTRx_BUSTURN FMC_BTRx_BUSTURN_Msk

#define	FMC_BTRx_BUSTURN_0 (0x1UL << FMC_BTRx_BUSTURN_Pos)

#define	FMC_BTRx_BUSTURN_1 (0x2UL << FMC_BTRx_BUSTURN_Pos)

#define	FMC_BTRx_BUSTURN_2 (0x4UL << FMC_BTRx_BUSTURN_Pos)

#define	FMC_BTRx_BUSTURN_3 (0x8UL << FMC_BTRx_BUSTURN_Pos)

#define	FMC_BTRx_CLKDIV_Pos (20U)

#define	FMC_BTRx_CLKDIV_Msk (0xFUL << FMC_BTRx_CLKDIV_Pos)

#define	FMC_BTRx_CLKDIV FMC_BTRx_CLKDIV_Msk

#define	FMC_BTRx_CLKDIV_0 (0x1UL << FMC_BTRx_CLKDIV_Pos)

#define	FMC_BTRx_CLKDIV_1 (0x2UL << FMC_BTRx_CLKDIV_Pos)

#define	FMC_BTRx_CLKDIV_2 (0x4UL << FMC_BTRx_CLKDIV_Pos)

#define	FMC_BTRx_CLKDIV_3 (0x8UL << FMC_BTRx_CLKDIV_Pos)

#define	FMC_BTRx_DATLAT_Pos (24U)

#define	FMC_BTRx_DATLAT_Msk (0xFUL << FMC_BTRx_DATLAT_Pos)

#define	FMC_BTRx_DATLAT FMC_BTRx_DATLAT_Msk

#define	FMC_BTRx_DATLAT_0 (0x1UL << FMC_BTRx_DATLAT_Pos)

#define	FMC_BTRx_DATLAT_1 (0x2UL << FMC_BTRx_DATLAT_Pos)

#define	FMC_BTRx_DATLAT_2 (0x4UL << FMC_BTRx_DATLAT_Pos)

#define	FMC_BTRx_DATLAT_3 (0x8UL << FMC_BTRx_DATLAT_Pos)

#define	FMC_BTRx_ACCMOD_Pos (28U)

#define	FMC_BTRx_ACCMOD_Msk (0x3UL << FMC_BTRx_ACCMOD_Pos)

#define	FMC_BTRx_ACCMOD FMC_BTRx_ACCMOD_Msk

#define	FMC_BTRx_ACCMOD_0 (0x1UL << FMC_BTRx_ACCMOD_Pos)

#define	FMC_BTRx_ACCMOD_1 (0x2UL << FMC_BTRx_ACCMOD_Pos)

#define	FMC_BTR1_ADDSET_Pos (0U)

#define	FMC_BTR1_ADDSET_Msk (0xFUL << FMC_BTR1_ADDSET_Pos)

#define	FMC_BTR1_ADDSET FMC_BTR1_ADDSET_Msk

#define	FMC_BTR1_ADDSET_0 (0x1UL << FMC_BTR1_ADDSET_Pos)

#define	FMC_BTR1_ADDSET_1 (0x2UL << FMC_BTR1_ADDSET_Pos)

#define	FMC_BTR1_ADDSET_2 (0x4UL << FMC_BTR1_ADDSET_Pos)

#define	FMC_BTR1_ADDSET_3 (0x8UL << FMC_BTR1_ADDSET_Pos)

#define	FMC_BTR1_ADDHLD_Pos (4U)

#define	FMC_BTR1_ADDHLD_Msk (0xFUL << FMC_BTR1_ADDHLD_Pos)

#define	FMC_BTR1_ADDHLD FMC_BTR1_ADDHLD_Msk

#define	FMC_BTR1_ADDHLD_0 (0x1UL << FMC_BTR1_ADDHLD_Pos)

#define	FMC_BTR1_ADDHLD_1 (0x2UL << FMC_BTR1_ADDHLD_Pos)

#define	FMC_BTR1_ADDHLD_2 (0x4UL << FMC_BTR1_ADDHLD_Pos)

#define	FMC_BTR1_ADDHLD_3 (0x8UL << FMC_BTR1_ADDHLD_Pos)

#define	FMC_BTR1_DATAST_Pos (8U)

#define	FMC_BTR1_DATAST_Msk (0xFFUL << FMC_BTR1_DATAST_Pos)

#define	FMC_BTR1_DATAST FMC_BTR1_DATAST_Msk

#define	FMC_BTR1_DATAST_0 (0x01UL << FMC_BTR1_DATAST_Pos)

#define	FMC_BTR1_DATAST_1 (0x02UL << FMC_BTR1_DATAST_Pos)

#define	FMC_BTR1_DATAST_2 (0x04UL << FMC_BTR1_DATAST_Pos)

#define	FMC_BTR1_DATAST_3 (0x08UL << FMC_BTR1_DATAST_Pos)

#define	FMC_BTR1_DATAST_4 (0x10UL << FMC_BTR1_DATAST_Pos)

#define	FMC_BTR1_DATAST_5 (0x20UL << FMC_BTR1_DATAST_Pos)

#define	FMC_BTR1_DATAST_6 (0x40UL << FMC_BTR1_DATAST_Pos)

#define	FMC_BTR1_DATAST_7 (0x80UL << FMC_BTR1_DATAST_Pos)

#define	FMC_BTR1_BUSTURN_Pos (16U)

#define	FMC_BTR1_BUSTURN_Msk (0xFUL << FMC_BTR1_BUSTURN_Pos)

#define	FMC_BTR1_BUSTURN FMC_BTR1_BUSTURN_Msk

#define	FMC_BTR1_BUSTURN_0 (0x1UL << FMC_BTR1_BUSTURN_Pos)

#define	FMC_BTR1_BUSTURN_1 (0x2UL << FMC_BTR1_BUSTURN_Pos)

#define	FMC_BTR1_BUSTURN_2 (0x4UL << FMC_BTR1_BUSTURN_Pos)

#define	FMC_BTR1_BUSTURN_3 (0x8UL << FMC_BTR1_BUSTURN_Pos)

#define	FMC_BTR1_CLKDIV_Pos (20U)

#define	FMC_BTR1_CLKDIV_Msk (0xFUL << FMC_BTR1_CLKDIV_Pos)

#define	FMC_BTR1_CLKDIV FMC_BTR1_CLKDIV_Msk

#define	FMC_BTR1_CLKDIV_0 (0x1UL << FMC_BTR1_CLKDIV_Pos)

#define	FMC_BTR1_CLKDIV_1 (0x2UL << FMC_BTR1_CLKDIV_Pos)

#define	FMC_BTR1_CLKDIV_2 (0x4UL << FMC_BTR1_CLKDIV_Pos)

#define	FMC_BTR1_CLKDIV_3 (0x8UL << FMC_BTR1_CLKDIV_Pos)

#define	FMC_BTR1_DATLAT_Pos (24U)

#define	FMC_BTR1_DATLAT_Msk (0xFUL << FMC_BTR1_DATLAT_Pos)

#define	FMC_BTR1_DATLAT FMC_BTR1_DATLAT_Msk

#define	FMC_BTR1_DATLAT_0 (0x1UL << FMC_BTR1_DATLAT_Pos)

#define	FMC_BTR1_DATLAT_1 (0x2UL << FMC_BTR1_DATLAT_Pos)

#define	FMC_BTR1_DATLAT_2 (0x4UL << FMC_BTR1_DATLAT_Pos)

#define	FMC_BTR1_DATLAT_3 (0x8UL << FMC_BTR1_DATLAT_Pos)

#define	FMC_BTR1_ACCMOD_Pos (28U)

#define	FMC_BTR1_ACCMOD_Msk (0x3UL << FMC_BTR1_ACCMOD_Pos)

#define	FMC_BTR1_ACCMOD FMC_BTR1_ACCMOD_Msk

#define	FMC_BTR1_ACCMOD_0 (0x1UL << FMC_BTR1_ACCMOD_Pos)

#define	FMC_BTR1_ACCMOD_1 (0x2UL << FMC_BTR1_ACCMOD_Pos)

#define	FMC_BTR2_ADDSET_Pos (0U)

#define	FMC_BTR2_ADDSET_Msk (0xFUL << FMC_BTR2_ADDSET_Pos)

#define	FMC_BTR2_ADDSET FMC_BTR2_ADDSET_Msk

#define	FMC_BTR2_ADDSET_0 (0x1UL << FMC_BTR2_ADDSET_Pos)

#define	FMC_BTR2_ADDSET_1 (0x2UL << FMC_BTR2_ADDSET_Pos)

#define	FMC_BTR2_ADDSET_2 (0x4UL << FMC_BTR2_ADDSET_Pos)

#define	FMC_BTR2_ADDSET_3 (0x8UL << FMC_BTR2_ADDSET_Pos)

#define	FMC_BTR2_ADDHLD_Pos (4U)

#define	FMC_BTR2_ADDHLD_Msk (0xFUL << FMC_BTR2_ADDHLD_Pos)

#define	FMC_BTR2_ADDHLD FMC_BTR2_ADDHLD_Msk

#define	FMC_BTR2_ADDHLD_0 (0x1UL << FMC_BTR2_ADDHLD_Pos)

#define	FMC_BTR2_ADDHLD_1 (0x2UL << FMC_BTR2_ADDHLD_Pos)

#define	FMC_BTR2_ADDHLD_2 (0x4UL << FMC_BTR2_ADDHLD_Pos)

#define	FMC_BTR2_ADDHLD_3 (0x8UL << FMC_BTR2_ADDHLD_Pos)

#define	FMC_BTR2_DATAST_Pos (8U)

#define	FMC_BTR2_DATAST_Msk (0xFFUL << FMC_BTR2_DATAST_Pos)

#define	FMC_BTR2_DATAST FMC_BTR2_DATAST_Msk

#define	FMC_BTR2_DATAST_0 (0x01UL << FMC_BTR2_DATAST_Pos)

#define	FMC_BTR2_DATAST_1 (0x02UL << FMC_BTR2_DATAST_Pos)

#define	FMC_BTR2_DATAST_2 (0x04UL << FMC_BTR2_DATAST_Pos)

#define	FMC_BTR2_DATAST_3 (0x08UL << FMC_BTR2_DATAST_Pos)

#define	FMC_BTR2_DATAST_4 (0x10UL << FMC_BTR2_DATAST_Pos)

#define	FMC_BTR2_DATAST_5 (0x20UL << FMC_BTR2_DATAST_Pos)

#define	FMC_BTR2_DATAST_6 (0x40UL << FMC_BTR2_DATAST_Pos)

#define	FMC_BTR2_DATAST_7 (0x80UL << FMC_BTR2_DATAST_Pos)

#define	FMC_BTR2_BUSTURN_Pos (16U)

#define	FMC_BTR2_BUSTURN_Msk (0xFUL << FMC_BTR2_BUSTURN_Pos)

#define	FMC_BTR2_BUSTURN FMC_BTR2_BUSTURN_Msk

#define	FMC_BTR2_BUSTURN_0 (0x1UL << FMC_BTR2_BUSTURN_Pos)

#define	FMC_BTR2_BUSTURN_1 (0x2UL << FMC_BTR2_BUSTURN_Pos)

#define	FMC_BTR2_BUSTURN_2 (0x4UL << FMC_BTR2_BUSTURN_Pos)

#define	FMC_BTR2_BUSTURN_3 (0x8UL << FMC_BTR2_BUSTURN_Pos)

#define	FMC_BTR2_CLKDIV_Pos (20U)

#define	FMC_BTR2_CLKDIV_Msk (0xFUL << FMC_BTR2_CLKDIV_Pos)

#define	FMC_BTR2_CLKDIV FMC_BTR2_CLKDIV_Msk

#define	FMC_BTR2_CLKDIV_0 (0x1UL << FMC_BTR2_CLKDIV_Pos)

#define	FMC_BTR2_CLKDIV_1 (0x2UL << FMC_BTR2_CLKDIV_Pos)

#define	FMC_BTR2_CLKDIV_2 (0x4UL << FMC_BTR2_CLKDIV_Pos)

#define	FMC_BTR2_CLKDIV_3 (0x8UL << FMC_BTR2_CLKDIV_Pos)

#define	FMC_BTR2_DATLAT_Pos (24U)

#define	FMC_BTR2_DATLAT_Msk (0xFUL << FMC_BTR2_DATLAT_Pos)

#define	FMC_BTR2_DATLAT FMC_BTR2_DATLAT_Msk

#define	FMC_BTR2_DATLAT_0 (0x1UL << FMC_BTR2_DATLAT_Pos)

#define	FMC_BTR2_DATLAT_1 (0x2UL << FMC_BTR2_DATLAT_Pos)

#define	FMC_BTR2_DATLAT_2 (0x4UL << FMC_BTR2_DATLAT_Pos)

#define	FMC_BTR2_DATLAT_3 (0x8UL << FMC_BTR2_DATLAT_Pos)

#define	FMC_BTR2_ACCMOD_Pos (28U)

#define	FMC_BTR2_ACCMOD_Msk (0x3UL << FMC_BTR2_ACCMOD_Pos)

#define	FMC_BTR2_ACCMOD FMC_BTR2_ACCMOD_Msk

#define	FMC_BTR2_ACCMOD_0 (0x1UL << FMC_BTR2_ACCMOD_Pos)

#define	FMC_BTR2_ACCMOD_1 (0x2UL << FMC_BTR2_ACCMOD_Pos)

#define	FMC_BTR3_ADDSET_Pos (0U)

#define	FMC_BTR3_ADDSET_Msk (0xFUL << FMC_BTR3_ADDSET_Pos)

#define	FMC_BTR3_ADDSET FMC_BTR3_ADDSET_Msk

#define	FMC_BTR3_ADDSET_0 (0x1UL << FMC_BTR3_ADDSET_Pos)

#define	FMC_BTR3_ADDSET_1 (0x2UL << FMC_BTR3_ADDSET_Pos)

#define	FMC_BTR3_ADDSET_2 (0x4UL << FMC_BTR3_ADDSET_Pos)

#define	FMC_BTR3_ADDSET_3 (0x8UL << FMC_BTR3_ADDSET_Pos)

#define	FMC_BTR3_ADDHLD_Pos (4U)

#define	FMC_BTR3_ADDHLD_Msk (0xFUL << FMC_BTR3_ADDHLD_Pos)

#define	FMC_BTR3_ADDHLD FMC_BTR3_ADDHLD_Msk

#define	FMC_BTR3_ADDHLD_0 (0x1UL << FMC_BTR3_ADDHLD_Pos)

#define	FMC_BTR3_ADDHLD_1 (0x2UL << FMC_BTR3_ADDHLD_Pos)

#define	FMC_BTR3_ADDHLD_2 (0x4UL << FMC_BTR3_ADDHLD_Pos)

#define	FMC_BTR3_ADDHLD_3 (0x8UL << FMC_BTR3_ADDHLD_Pos)

#define	FMC_BTR3_DATAST_Pos (8U)

#define	FMC_BTR3_DATAST_Msk (0xFFUL << FMC_BTR3_DATAST_Pos)

#define	FMC_BTR3_DATAST FMC_BTR3_DATAST_Msk

#define	FMC_BTR3_DATAST_0 (0x01UL << FMC_BTR3_DATAST_Pos)

#define	FMC_BTR3_DATAST_1 (0x02UL << FMC_BTR3_DATAST_Pos)

#define	FMC_BTR3_DATAST_2 (0x04UL << FMC_BTR3_DATAST_Pos)

#define	FMC_BTR3_DATAST_3 (0x08UL << FMC_BTR3_DATAST_Pos)

#define	FMC_BTR3_DATAST_4 (0x10UL << FMC_BTR3_DATAST_Pos)

#define	FMC_BTR3_DATAST_5 (0x20UL << FMC_BTR3_DATAST_Pos)

#define	FMC_BTR3_DATAST_6 (0x40UL << FMC_BTR3_DATAST_Pos)

#define	FMC_BTR3_DATAST_7 (0x80UL << FMC_BTR3_DATAST_Pos)

#define	FMC_BTR3_BUSTURN_Pos (16U)

#define	FMC_BTR3_BUSTURN_Msk (0xFUL << FMC_BTR3_BUSTURN_Pos)

#define	FMC_BTR3_BUSTURN FMC_BTR3_BUSTURN_Msk

#define	FMC_BTR3_BUSTURN_0 (0x1UL << FMC_BTR3_BUSTURN_Pos)

#define	FMC_BTR3_BUSTURN_1 (0x2UL << FMC_BTR3_BUSTURN_Pos)

#define	FMC_BTR3_BUSTURN_2 (0x4UL << FMC_BTR3_BUSTURN_Pos)

#define	FMC_BTR3_BUSTURN_3 (0x8UL << FMC_BTR3_BUSTURN_Pos)

#define	FMC_BTR3_CLKDIV_Pos (20U)

#define	FMC_BTR3_CLKDIV_Msk (0xFUL << FMC_BTR3_CLKDIV_Pos)

#define	FMC_BTR3_CLKDIV FMC_BTR3_CLKDIV_Msk

#define	FMC_BTR3_CLKDIV_0 (0x1UL << FMC_BTR3_CLKDIV_Pos)

#define	FMC_BTR3_CLKDIV_1 (0x2UL << FMC_BTR3_CLKDIV_Pos)

#define	FMC_BTR3_CLKDIV_2 (0x4UL << FMC_BTR3_CLKDIV_Pos)

#define	FMC_BTR3_CLKDIV_3 (0x8UL << FMC_BTR3_CLKDIV_Pos)

#define	FMC_BTR3_DATLAT_Pos (24U)

#define	FMC_BTR3_DATLAT_Msk (0xFUL << FMC_BTR3_DATLAT_Pos)

#define	FMC_BTR3_DATLAT FMC_BTR3_DATLAT_Msk

#define	FMC_BTR3_DATLAT_0 (0x1UL << FMC_BTR3_DATLAT_Pos)

#define	FMC_BTR3_DATLAT_1 (0x2UL << FMC_BTR3_DATLAT_Pos)

#define	FMC_BTR3_DATLAT_2 (0x4UL << FMC_BTR3_DATLAT_Pos)

#define	FMC_BTR3_DATLAT_3 (0x8UL << FMC_BTR3_DATLAT_Pos)

#define	FMC_BTR3_ACCMOD_Pos (28U)

#define	FMC_BTR3_ACCMOD_Msk (0x3UL << FMC_BTR3_ACCMOD_Pos)

#define	FMC_BTR3_ACCMOD FMC_BTR3_ACCMOD_Msk

#define	FMC_BTR3_ACCMOD_0 (0x1UL << FMC_BTR3_ACCMOD_Pos)

#define	FMC_BTR3_ACCMOD_1 (0x2UL << FMC_BTR3_ACCMOD_Pos)

#define	FMC_BTR4_ADDSET_Pos (0U)

#define	FMC_BTR4_ADDSET_Msk (0xFUL << FMC_BTR4_ADDSET_Pos)

#define	FMC_BTR4_ADDSET FMC_BTR4_ADDSET_Msk

#define	FMC_BTR4_ADDSET_0 (0x1UL << FMC_BTR4_ADDSET_Pos)

#define	FMC_BTR4_ADDSET_1 (0x2UL << FMC_BTR4_ADDSET_Pos)

#define	FMC_BTR4_ADDSET_2 (0x4UL << FMC_BTR4_ADDSET_Pos)

#define	FMC_BTR4_ADDSET_3 (0x8UL << FMC_BTR4_ADDSET_Pos)

#define	FMC_BTR4_ADDHLD_Pos (4U)

#define	FMC_BTR4_ADDHLD_Msk (0xFUL << FMC_BTR4_ADDHLD_Pos)

#define	FMC_BTR4_ADDHLD FMC_BTR4_ADDHLD_Msk

#define	FMC_BTR4_ADDHLD_0 (0x1UL << FMC_BTR4_ADDHLD_Pos)

#define	FMC_BTR4_ADDHLD_1 (0x2UL << FMC_BTR4_ADDHLD_Pos)

#define	FMC_BTR4_ADDHLD_2 (0x4UL << FMC_BTR4_ADDHLD_Pos)

#define	FMC_BTR4_ADDHLD_3 (0x8UL << FMC_BTR4_ADDHLD_Pos)

#define	FMC_BTR4_DATAST_Pos (8U)

#define	FMC_BTR4_DATAST_Msk (0xFFUL << FMC_BTR4_DATAST_Pos)

#define	FMC_BTR4_DATAST FMC_BTR4_DATAST_Msk

#define	FMC_BTR4_DATAST_0 (0x01UL << FMC_BTR4_DATAST_Pos)

#define	FMC_BTR4_DATAST_1 (0x02UL << FMC_BTR4_DATAST_Pos)

#define	FMC_BTR4_DATAST_2 (0x04UL << FMC_BTR4_DATAST_Pos)

#define	FMC_BTR4_DATAST_3 (0x08UL << FMC_BTR4_DATAST_Pos)

#define	FMC_BTR4_DATAST_4 (0x10UL << FMC_BTR4_DATAST_Pos)

#define	FMC_BTR4_DATAST_5 (0x20UL << FMC_BTR4_DATAST_Pos)

#define	FMC_BTR4_DATAST_6 (0x40UL << FMC_BTR4_DATAST_Pos)

#define	FMC_BTR4_DATAST_7 (0x80UL << FMC_BTR4_DATAST_Pos)

#define	FMC_BTR4_BUSTURN_Pos (16U)

#define	FMC_BTR4_BUSTURN_Msk (0xFUL << FMC_BTR4_BUSTURN_Pos)

#define	FMC_BTR4_BUSTURN FMC_BTR4_BUSTURN_Msk

#define	FMC_BTR4_BUSTURN_0 (0x1UL << FMC_BTR4_BUSTURN_Pos)

#define	FMC_BTR4_BUSTURN_1 (0x2UL << FMC_BTR4_BUSTURN_Pos)

#define	FMC_BTR4_BUSTURN_2 (0x4UL << FMC_BTR4_BUSTURN_Pos)

#define	FMC_BTR4_BUSTURN_3 (0x8UL << FMC_BTR4_BUSTURN_Pos)

#define	FMC_BTR4_CLKDIV_Pos (20U)

#define	FMC_BTR4_CLKDIV_Msk (0xFUL << FMC_BTR4_CLKDIV_Pos)

#define	FMC_BTR4_CLKDIV FMC_BTR4_CLKDIV_Msk

#define	FMC_BTR4_CLKDIV_0 (0x1UL << FMC_BTR4_CLKDIV_Pos)

#define	FMC_BTR4_CLKDIV_1 (0x2UL << FMC_BTR4_CLKDIV_Pos)

#define	FMC_BTR4_CLKDIV_2 (0x4UL << FMC_BTR4_CLKDIV_Pos)

#define	FMC_BTR4_CLKDIV_3 (0x8UL << FMC_BTR4_CLKDIV_Pos)

#define	FMC_BTR4_DATLAT_Pos (24U)

#define	FMC_BTR4_DATLAT_Msk (0xFUL << FMC_BTR4_DATLAT_Pos)

#define	FMC_BTR4_DATLAT FMC_BTR4_DATLAT_Msk

#define	FMC_BTR4_DATLAT_0 (0x1UL << FMC_BTR4_DATLAT_Pos)

#define	FMC_BTR4_DATLAT_1 (0x2UL << FMC_BTR4_DATLAT_Pos)

#define	FMC_BTR4_DATLAT_2 (0x4UL << FMC_BTR4_DATLAT_Pos)

#define	FMC_BTR4_DATLAT_3 (0x8UL << FMC_BTR4_DATLAT_Pos)

#define	FMC_BTR4_ACCMOD_Pos (28U)

#define	FMC_BTR4_ACCMOD_Msk (0x3UL << FMC_BTR4_ACCMOD_Pos)

#define	FMC_BTR4_ACCMOD FMC_BTR4_ACCMOD_Msk

#define	FMC_BTR4_ACCMOD_0 (0x1UL << FMC_BTR4_ACCMOD_Pos)

#define	FMC_BTR4_ACCMOD_1 (0x2UL << FMC_BTR4_ACCMOD_Pos)

#define	FMC_BWTRx_ADDSET_Pos (0U)

#define	FMC_BWTRx_ADDSET_Msk (0xFUL << FMC_BWTRx_ADDSET_Pos)

#define	FMC_BWTRx_ADDSET FMC_BWTRx_ADDSET_Msk

#define	FMC_BWTRx_ADDSET_0 (0x1UL << FMC_BWTRx_ADDSET_Pos)

#define	FMC_BWTRx_ADDSET_1 (0x2UL << FMC_BWTRx_ADDSET_Pos)

#define	FMC_BWTRx_ADDSET_2 (0x4UL << FMC_BWTRx_ADDSET_Pos)

#define	FMC_BWTRx_ADDSET_3 (0x8UL << FMC_BWTRx_ADDSET_Pos)

#define	FMC_BWTRx_ADDHLD_Pos (4U)

#define	FMC_BWTRx_ADDHLD_Msk (0xFUL << FMC_BWTRx_ADDHLD_Pos)

#define	FMC_BWTRx_ADDHLD FMC_BWTRx_ADDHLD_Msk

#define	FMC_BWTRx_ADDHLD_0 (0x1UL << FMC_BWTRx_ADDHLD_Pos)

#define	FMC_BWTRx_ADDHLD_1 (0x2UL << FMC_BWTRx_ADDHLD_Pos)

#define	FMC_BWTRx_ADDHLD_2 (0x4UL << FMC_BWTRx_ADDHLD_Pos)

#define	FMC_BWTRx_ADDHLD_3 (0x8UL << FMC_BWTRx_ADDHLD_Pos)

#define	FMC_BWTRx_DATAST_Pos (8U)

#define	FMC_BWTRx_DATAST_Msk (0xFFUL << FMC_BWTRx_DATAST_Pos)

#define	FMC_BWTRx_DATAST FMC_BWTRx_DATAST_Msk

#define	FMC_BWTRx_DATAST_0 (0x01UL << FMC_BWTRx_DATAST_Pos)

#define	FMC_BWTRx_DATAST_1 (0x02UL << FMC_BWTRx_DATAST_Pos)

#define	FMC_BWTRx_DATAST_2 (0x04UL << FMC_BWTRx_DATAST_Pos)

#define	FMC_BWTRx_DATAST_3 (0x08UL << FMC_BWTRx_DATAST_Pos)

#define	FMC_BWTRx_DATAST_4 (0x10UL << FMC_BWTRx_DATAST_Pos)

#define	FMC_BWTRx_DATAST_5 (0x20UL << FMC_BWTRx_DATAST_Pos)

#define	FMC_BWTRx_DATAST_6 (0x40UL << FMC_BWTRx_DATAST_Pos)

#define	FMC_BWTRx_DATAST_7 (0x80UL << FMC_BWTRx_DATAST_Pos)

#define	FMC_BWTRx_ACCMOD_Pos (28U)

#define	FMC_BWTRx_ACCMOD_Msk (0x3UL << FMC_BWTRx_ACCMOD_Pos)

#define	FMC_BWTRx_ACCMOD FMC_BWTRx_ACCMOD_Msk

#define	FMC_BWTRx_ACCMOD_0 (0x1UL << FMC_BWTRx_ACCMOD_Pos)

#define	FMC_BWTRx_ACCMOD_1 (0x2UL << FMC_BWTRx_ACCMOD_Pos)

#define	FMC_BWTRx_ADDSETx FMC_BWTRx_ADDSET

#define	FMC_BWTRx_ADDSETx_0 FMC_BWTRx_ADDSET_0

#define	FMC_BWTRx_ADDSETx_1 FMC_BWTRx_ADDSET_1

#define	FMC_BWTRx_ADDSETx_2 FMC_BWTRx_ADDSET_2

#define	FMC_BWTRx_ADDSETx_3 FMC_BWTRx_ADDSET_3

#define	FMC_BWTRx_ADDHLDx FMC_BWTRx_ADDHLD

#define	FMC_BWTRx_ADDHLDx_0 FMC_BWTRx_ADDHLD_0

#define	FMC_BWTRx_ADDHLDx_1 FMC_BWTRx_ADDHLD_1

#define	FMC_BWTRx_ADDHLDx_2 FMC_BWTRx_ADDHLD_2

#define	FMC_BWTRx_ADDHLDx_3 FMC_BWTRx_ADDHLD_3

#define	FMC_BWTRx_DATASTx FMC_BWTRx_DATAST

#define	FMC_BWTRx_DATASTx_0 FMC_BWTRx_DATAST_0

#define	FMC_BWTRx_DATASTx_1 FMC_BWTRx_DATAST_1

#define	FMC_BWTRx_DATASTx_2 FMC_BWTRx_DATAST_2

#define	FMC_BWTRx_DATASTx_3 FMC_BWTRx_DATAST_3

#define	FMC_BWTRx_DATASTx_4 FMC_BWTRx_DATAST_4

#define	FMC_BWTRx_DATASTx_5 FMC_BWTRx_DATAST_5

#define	FMC_BWTRx_DATASTx_6 FMC_BWTRx_DATAST_6

#define	FMC_BWTRx_DATASTx_7 FMC_BWTRx_DATAST_7

#define	FMC_BWTRx_ACCMODx FMC_BWTRx_ACCMOD

#define	FMC_BWTRx_ACCMODx_0 FMC_BWTRx_ACCMOD_0

#define	FMC_BWTRx_ACCMODx_1 FMC_BWTRx_ACCMOD_1

#define	FMC_BWTR1_ADDSET_Pos (0U)

#define	FMC_BWTR1_ADDSET_Msk (0xFUL << FMC_BWTR1_ADDSET_Pos)

#define	FMC_BWTR1_ADDSET FMC_BWTR1_ADDSET_Msk

#define	FMC_BWTR1_ADDSET_0 (0x1UL << FMC_BWTR1_ADDSET_Pos)

#define	FMC_BWTR1_ADDSET_1 (0x2UL << FMC_BWTR1_ADDSET_Pos)

#define	FMC_BWTR1_ADDSET_2 (0x4UL << FMC_BWTR1_ADDSET_Pos)

#define	FMC_BWTR1_ADDSET_3 (0x8UL << FMC_BWTR1_ADDSET_Pos)

#define	FMC_BWTR1_ADDHLD_Pos (4U)

#define	FMC_BWTR1_ADDHLD_Msk (0xFUL << FMC_BWTR1_ADDHLD_Pos)

#define	FMC_BWTR1_ADDHLD FMC_BWTR1_ADDHLD_Msk

#define	FMC_BWTR1_ADDHLD_0 (0x1UL << FMC_BWTR1_ADDHLD_Pos)

#define	FMC_BWTR1_ADDHLD_1 (0x2UL << FMC_BWTR1_ADDHLD_Pos)

#define	FMC_BWTR1_ADDHLD_2 (0x4UL << FMC_BWTR1_ADDHLD_Pos)

#define	FMC_BWTR1_ADDHLD_3 (0x8UL << FMC_BWTR1_ADDHLD_Pos)

#define	FMC_BWTR1_DATAST_Pos (8U)

#define	FMC_BWTR1_DATAST_Msk (0xFFUL << FMC_BWTR1_DATAST_Pos)

#define	FMC_BWTR1_DATAST FMC_BWTR1_DATAST_Msk

#define	FMC_BWTR1_DATAST_0 (0x01UL << FMC_BWTR1_DATAST_Pos)

#define	FMC_BWTR1_DATAST_1 (0x02UL << FMC_BWTR1_DATAST_Pos)

#define	FMC_BWTR1_DATAST_2 (0x04UL << FMC_BWTR1_DATAST_Pos)

#define	FMC_BWTR1_DATAST_3 (0x08UL << FMC_BWTR1_DATAST_Pos)

#define	FMC_BWTR1_DATAST_4 (0x10UL << FMC_BWTR1_DATAST_Pos)

#define	FMC_BWTR1_DATAST_5 (0x20UL << FMC_BWTR1_DATAST_Pos)

#define	FMC_BWTR1_DATAST_6 (0x40UL << FMC_BWTR1_DATAST_Pos)

#define	FMC_BWTR1_DATAST_7 (0x80UL << FMC_BWTR1_DATAST_Pos)

#define	FMC_BWTR1_CLKDIV_Pos (20U)

#define	FMC_BWTR1_CLKDIV_Msk (0xFUL << FMC_BWTR1_CLKDIV_Pos)

#define	FMC_BWTR1_CLKDIV FMC_BWTR1_CLKDIV_Msk

#define	FMC_BWTR1_CLKDIV_0 (0x1UL << FMC_BWTR1_CLKDIV_Pos)

#define	FMC_BWTR1_CLKDIV_1 (0x2UL << FMC_BWTR1_CLKDIV_Pos)

#define	FMC_BWTR1_CLKDIV_2 (0x4UL << FMC_BWTR1_CLKDIV_Pos)

#define	FMC_BWTR1_CLKDIV_3 (0x8UL << FMC_BWTR1_CLKDIV_Pos)

#define	FMC_BWTR1_DATLAT_Pos (24U)

#define	FMC_BWTR1_DATLAT_Msk (0xFUL << FMC_BWTR1_DATLAT_Pos)

#define	FMC_BWTR1_DATLAT FMC_BWTR1_DATLAT_Msk

#define	FMC_BWTR1_DATLAT_0 (0x1UL << FMC_BWTR1_DATLAT_Pos)

#define	FMC_BWTR1_DATLAT_1 (0x2UL << FMC_BWTR1_DATLAT_Pos)

#define	FMC_BWTR1_DATLAT_2 (0x4UL << FMC_BWTR1_DATLAT_Pos)

#define	FMC_BWTR1_DATLAT_3 (0x8UL << FMC_BWTR1_DATLAT_Pos)

#define	FMC_BWTR1_ACCMOD_Pos (28U)

#define	FMC_BWTR1_ACCMOD_Msk (0x3UL << FMC_BWTR1_ACCMOD_Pos)

#define	FMC_BWTR1_ACCMOD FMC_BWTR1_ACCMOD_Msk

#define	FMC_BWTR1_ACCMOD_0 (0x1UL << FMC_BWTR1_ACCMOD_Pos)

#define	FMC_BWTR1_ACCMOD_1 (0x2UL << FMC_BWTR1_ACCMOD_Pos)

#define	FMC_BWTR2_ADDSET_Pos (0U)

#define	FMC_BWTR2_ADDSET_Msk (0xFUL << FMC_BWTR2_ADDSET_Pos)

#define	FMC_BWTR2_ADDSET FMC_BWTR2_ADDSET_Msk

#define	FMC_BWTR2_ADDSET_0 (0x1UL << FMC_BWTR2_ADDSET_Pos)

#define	FMC_BWTR2_ADDSET_1 (0x2UL << FMC_BWTR2_ADDSET_Pos)

#define	FMC_BWTR2_ADDSET_2 (0x4UL << FMC_BWTR2_ADDSET_Pos)

#define	FMC_BWTR2_ADDSET_3 (0x8UL << FMC_BWTR2_ADDSET_Pos)

#define	FMC_BWTR2_ADDHLD_Pos (4U)

#define	FMC_BWTR2_ADDHLD_Msk (0xFUL << FMC_BWTR2_ADDHLD_Pos)

#define	FMC_BWTR2_ADDHLD FMC_BWTR2_ADDHLD_Msk

#define	FMC_BWTR2_ADDHLD_0 (0x1UL << FMC_BWTR2_ADDHLD_Pos)

#define	FMC_BWTR2_ADDHLD_1 (0x2UL << FMC_BWTR2_ADDHLD_Pos)

#define	FMC_BWTR2_ADDHLD_2 (0x4UL << FMC_BWTR2_ADDHLD_Pos)

#define	FMC_BWTR2_ADDHLD_3 (0x8UL << FMC_BWTR2_ADDHLD_Pos)

#define	FMC_BWTR2_DATAST_Pos (8U)

#define	FMC_BWTR2_DATAST_Msk (0xFFUL << FMC_BWTR2_DATAST_Pos)

#define	FMC_BWTR2_DATAST FMC_BWTR2_DATAST_Msk

#define	FMC_BWTR2_DATAST_0 (0x01UL << FMC_BWTR2_DATAST_Pos)

#define	FMC_BWTR2_DATAST_1 (0x02UL << FMC_BWTR2_DATAST_Pos)

#define	FMC_BWTR2_DATAST_2 (0x04UL << FMC_BWTR2_DATAST_Pos)

#define	FMC_BWTR2_DATAST_3 (0x08UL << FMC_BWTR2_DATAST_Pos)

#define	FMC_BWTR2_DATAST_4 (0x10UL << FMC_BWTR2_DATAST_Pos)

#define	FMC_BWTR2_DATAST_5 (0x20UL << FMC_BWTR2_DATAST_Pos)

#define	FMC_BWTR2_DATAST_6 (0x40UL << FMC_BWTR2_DATAST_Pos)

#define	FMC_BWTR2_DATAST_7 (0x80UL << FMC_BWTR2_DATAST_Pos)

#define	FMC_BWTR2_CLKDIV_Pos (20U)

#define	FMC_BWTR2_CLKDIV_Msk (0xFUL << FMC_BWTR2_CLKDIV_Pos)

#define	FMC_BWTR2_CLKDIV FMC_BWTR2_CLKDIV_Msk

#define	FMC_BWTR2_CLKDIV_0 (0x1UL << FMC_BWTR2_CLKDIV_Pos)

#define	FMC_BWTR2_CLKDIV_1 (0x2UL << FMC_BWTR2_CLKDIV_Pos)

#define	FMC_BWTR2_CLKDIV_2 (0x4UL << FMC_BWTR2_CLKDIV_Pos)

#define	FMC_BWTR2_CLKDIV_3 (0x8UL << FMC_BWTR2_CLKDIV_Pos)

#define	FMC_BWTR2_DATLAT_Pos (24U)

#define	FMC_BWTR2_DATLAT_Msk (0xFUL << FMC_BWTR2_DATLAT_Pos)

#define	FMC_BWTR2_DATLAT FMC_BWTR2_DATLAT_Msk

#define	FMC_BWTR2_DATLAT_0 (0x1UL << FMC_BWTR2_DATLAT_Pos)

#define	FMC_BWTR2_DATLAT_1 (0x2UL << FMC_BWTR2_DATLAT_Pos)

#define	FMC_BWTR2_DATLAT_2 (0x4UL << FMC_BWTR2_DATLAT_Pos)

#define	FMC_BWTR2_DATLAT_3 (0x8UL << FMC_BWTR2_DATLAT_Pos)

#define	FMC_BWTR2_ACCMOD_Pos (28U)

#define	FMC_BWTR2_ACCMOD_Msk (0x3UL << FMC_BWTR2_ACCMOD_Pos)

#define	FMC_BWTR2_ACCMOD FMC_BWTR2_ACCMOD_Msk

#define	FMC_BWTR2_ACCMOD_0 (0x1UL << FMC_BWTR2_ACCMOD_Pos)

#define	FMC_BWTR2_ACCMOD_1 (0x2UL << FMC_BWTR2_ACCMOD_Pos)

#define	FMC_BWTR3_ADDSET_Pos (0U)

#define	FMC_BWTR3_ADDSET_Msk (0xFUL << FMC_BWTR3_ADDSET_Pos)

#define	FMC_BWTR3_ADDSET FMC_BWTR3_ADDSET_Msk

#define	FMC_BWTR3_ADDSET_0 (0x1UL << FMC_BWTR3_ADDSET_Pos)

#define	FMC_BWTR3_ADDSET_1 (0x2UL << FMC_BWTR3_ADDSET_Pos)

#define	FMC_BWTR3_ADDSET_2 (0x4UL << FMC_BWTR3_ADDSET_Pos)

#define	FMC_BWTR3_ADDSET_3 (0x8UL << FMC_BWTR3_ADDSET_Pos)

#define	FMC_BWTR3_ADDHLD_Pos (4U)

#define	FMC_BWTR3_ADDHLD_Msk (0xFUL << FMC_BWTR3_ADDHLD_Pos)

#define	FMC_BWTR3_ADDHLD FMC_BWTR3_ADDHLD_Msk

#define	FMC_BWTR3_ADDHLD_0 (0x1UL << FMC_BWTR3_ADDHLD_Pos)

#define	FMC_BWTR3_ADDHLD_1 (0x2UL << FMC_BWTR3_ADDHLD_Pos)

#define	FMC_BWTR3_ADDHLD_2 (0x4UL << FMC_BWTR3_ADDHLD_Pos)

#define	FMC_BWTR3_ADDHLD_3 (0x8UL << FMC_BWTR3_ADDHLD_Pos)

#define	FMC_BWTR3_DATAST_Pos (8U)

#define	FMC_BWTR3_DATAST_Msk (0xFFUL << FMC_BWTR3_DATAST_Pos)

#define	FMC_BWTR3_DATAST FMC_BWTR3_DATAST_Msk

#define	FMC_BWTR3_DATAST_0 (0x01UL << FMC_BWTR3_DATAST_Pos)

#define	FMC_BWTR3_DATAST_1 (0x02UL << FMC_BWTR3_DATAST_Pos)

#define	FMC_BWTR3_DATAST_2 (0x04UL << FMC_BWTR3_DATAST_Pos)

#define	FMC_BWTR3_DATAST_3 (0x08UL << FMC_BWTR3_DATAST_Pos)

#define	FMC_BWTR3_DATAST_4 (0x10UL << FMC_BWTR3_DATAST_Pos)

#define	FMC_BWTR3_DATAST_5 (0x20UL << FMC_BWTR3_DATAST_Pos)

#define	FMC_BWTR3_DATAST_6 (0x40UL << FMC_BWTR3_DATAST_Pos)

#define	FMC_BWTR3_DATAST_7 (0x80UL << FMC_BWTR3_DATAST_Pos)

#define	FMC_BWTR3_CLKDIV_Pos (20U)

#define	FMC_BWTR3_CLKDIV_Msk (0xFUL << FMC_BWTR3_CLKDIV_Pos)

#define	FMC_BWTR3_CLKDIV FMC_BWTR3_CLKDIV_Msk

#define	FMC_BWTR3_CLKDIV_0 (0x1UL << FMC_BWTR3_CLKDIV_Pos)

#define	FMC_BWTR3_CLKDIV_1 (0x2UL << FMC_BWTR3_CLKDIV_Pos)

#define	FMC_BWTR3_CLKDIV_2 (0x4UL << FMC_BWTR3_CLKDIV_Pos)

#define	FMC_BWTR3_CLKDIV_3 (0x8UL << FMC_BWTR3_CLKDIV_Pos)

#define	FMC_BWTR3_DATLAT_Pos (24U)

#define	FMC_BWTR3_DATLAT_Msk (0xFUL << FMC_BWTR3_DATLAT_Pos)

#define	FMC_BWTR3_DATLAT FMC_BWTR3_DATLAT_Msk

#define	FMC_BWTR3_DATLAT_0 (0x1UL << FMC_BWTR3_DATLAT_Pos)

#define	FMC_BWTR3_DATLAT_1 (0x2UL << FMC_BWTR3_DATLAT_Pos)

#define	FMC_BWTR3_DATLAT_2 (0x4UL << FMC_BWTR3_DATLAT_Pos)

#define	FMC_BWTR3_DATLAT_3 (0x8UL << FMC_BWTR3_DATLAT_Pos)

#define	FMC_BWTR3_ACCMOD_Pos (28U)

#define	FMC_BWTR3_ACCMOD_Msk (0x3UL << FMC_BWTR3_ACCMOD_Pos)

#define	FMC_BWTR3_ACCMOD FMC_BWTR3_ACCMOD_Msk

#define	FMC_BWTR3_ACCMOD_0 (0x1UL << FMC_BWTR3_ACCMOD_Pos)

#define	FMC_BWTR3_ACCMOD_1 (0x2UL << FMC_BWTR3_ACCMOD_Pos)

#define	FMC_BWTR4_ADDSET_Pos (0U)

#define	FMC_BWTR4_ADDSET_Msk (0xFUL << FMC_BWTR4_ADDSET_Pos)

#define	FMC_BWTR4_ADDSET FMC_BWTR4_ADDSET_Msk

#define	FMC_BWTR4_ADDSET_0 (0x1UL << FMC_BWTR4_ADDSET_Pos)

#define	FMC_BWTR4_ADDSET_1 (0x2UL << FMC_BWTR4_ADDSET_Pos)

#define	FMC_BWTR4_ADDSET_2 (0x4UL << FMC_BWTR4_ADDSET_Pos)

#define	FMC_BWTR4_ADDSET_3 (0x8UL << FMC_BWTR4_ADDSET_Pos)

#define	FMC_BWTR4_ADDHLD_Pos (4U)

#define	FMC_BWTR4_ADDHLD_Msk (0xFUL << FMC_BWTR4_ADDHLD_Pos)

#define	FMC_BWTR4_ADDHLD FMC_BWTR4_ADDHLD_Msk

#define	FMC_BWTR4_ADDHLD_0 (0x1UL << FMC_BWTR4_ADDHLD_Pos)

#define	FMC_BWTR4_ADDHLD_1 (0x2UL << FMC_BWTR4_ADDHLD_Pos)

#define	FMC_BWTR4_ADDHLD_2 (0x4UL << FMC_BWTR4_ADDHLD_Pos)

#define	FMC_BWTR4_ADDHLD_3 (0x8UL << FMC_BWTR4_ADDHLD_Pos)

#define	FMC_BWTR4_DATAST_Pos (8U)

#define	FMC_BWTR4_DATAST_Msk (0xFFUL << FMC_BWTR4_DATAST_Pos)

#define	FMC_BWTR4_DATAST FMC_BWTR4_DATAST_Msk

#define	FMC_BWTR4_DATAST_0 (0x01UL << FMC_BWTR4_DATAST_Pos)

#define	FMC_BWTR4_DATAST_1 (0x02UL << FMC_BWTR4_DATAST_Pos)

#define	FMC_BWTR4_DATAST_2 (0x04UL << FMC_BWTR4_DATAST_Pos)

#define	FMC_BWTR4_DATAST_3 (0x08UL << FMC_BWTR4_DATAST_Pos)

#define	FMC_BWTR4_DATAST_4 (0x10UL << FMC_BWTR4_DATAST_Pos)

#define	FMC_BWTR4_DATAST_5 (0x20UL << FMC_BWTR4_DATAST_Pos)

#define	FMC_BWTR4_DATAST_6 (0x40UL << FMC_BWTR4_DATAST_Pos)

#define	FMC_BWTR4_DATAST_7 (0x80UL << FMC_BWTR4_DATAST_Pos)

#define	FMC_BWTR4_CLKDIV_Pos (20U)

#define	FMC_BWTR4_CLKDIV_Msk (0xFUL << FMC_BWTR4_CLKDIV_Pos)

#define	FMC_BWTR4_CLKDIV FMC_BWTR4_CLKDIV_Msk

#define	FMC_BWTR4_CLKDIV_0 (0x1UL << FMC_BWTR4_CLKDIV_Pos)

#define	FMC_BWTR4_CLKDIV_1 (0x2UL << FMC_BWTR4_CLKDIV_Pos)

#define	FMC_BWTR4_CLKDIV_2 (0x4UL << FMC_BWTR4_CLKDIV_Pos)

#define	FMC_BWTR4_CLKDIV_3 (0x8UL << FMC_BWTR4_CLKDIV_Pos)

#define	FMC_BWTR4_DATLAT_Pos (24U)

#define	FMC_BWTR4_DATLAT_Msk (0xFUL << FMC_BWTR4_DATLAT_Pos)

#define	FMC_BWTR4_DATLAT FMC_BWTR4_DATLAT_Msk

#define	FMC_BWTR4_DATLAT_0 (0x1UL << FMC_BWTR4_DATLAT_Pos)

#define	FMC_BWTR4_DATLAT_1 (0x2UL << FMC_BWTR4_DATLAT_Pos)

#define	FMC_BWTR4_DATLAT_2 (0x4UL << FMC_BWTR4_DATLAT_Pos)

#define	FMC_BWTR4_DATLAT_3 (0x8UL << FMC_BWTR4_DATLAT_Pos)

#define	FMC_BWTR4_ACCMOD_Pos (28U)

#define	FMC_BWTR4_ACCMOD_Msk (0x3UL << FMC_BWTR4_ACCMOD_Pos)

#define	FMC_BWTR4_ACCMOD FMC_BWTR4_ACCMOD_Msk

#define	FMC_BWTR4_ACCMOD_0 (0x1UL << FMC_BWTR4_ACCMOD_Pos)

#define	FMC_BWTR4_ACCMOD_1 (0x2UL << FMC_BWTR4_ACCMOD_Pos)

#define	FMC_PCRx_PWAITEN_Pos (1U)

#define	FMC_PCRx_PWAITEN_Msk (0x1UL << FMC_PCRx_PWAITEN_Pos)

#define	FMC_PCRx_PWAITEN FMC_PCRx_PWAITEN_Msk

#define	FMC_PCRx_PBKEN_Pos (2U)

#define	FMC_PCRx_PBKEN_Msk (0x1UL << FMC_PCRx_PBKEN_Pos)

#define	FMC_PCRx_PBKEN FMC_PCRx_PBKEN_Msk

#define	FMC_PCRx_PTYP_Pos (3U)

#define	FMC_PCRx_PTYP_Msk (0x1UL << FMC_PCRx_PTYP_Pos)

#define	FMC_PCRx_PTYP FMC_PCRx_PTYP_Msk

#define	FMC_PCRx_PWID_Pos (4U)

#define	FMC_PCRx_PWID_Msk (0x3UL << FMC_PCRx_PWID_Pos)

#define	FMC_PCRx_PWID FMC_PCRx_PWID_Msk

#define	FMC_PCRx_PWID_0 (0x1UL << FMC_PCRx_PWID_Pos)

#define	FMC_PCRx_PWID_1 (0x2UL << FMC_PCRx_PWID_Pos)

#define	FMC_PCRx_ECCEN_Pos (6U)

#define	FMC_PCRx_ECCEN_Msk (0x1UL << FMC_PCRx_ECCEN_Pos)

#define	FMC_PCRx_ECCEN FMC_PCRx_ECCEN_Msk

#define	FMC_PCRx_TCLR_Pos (9U)

#define	FMC_PCRx_TCLR_Msk (0xFUL << FMC_PCRx_TCLR_Pos)

#define	FMC_PCRx_TCLR FMC_PCRx_TCLR_Msk

#define	FMC_PCRx_TCLR_0 (0x1UL << FMC_PCRx_TCLR_Pos)

#define	FMC_PCRx_TCLR_1 (0x2UL << FMC_PCRx_TCLR_Pos)

#define	FMC_PCRx_TCLR_2 (0x4UL << FMC_PCRx_TCLR_Pos)

#define	FMC_PCRx_TCLR_3 (0x8UL << FMC_PCRx_TCLR_Pos)

#define	FMC_PCRx_TAR_Pos (13U)

#define	FMC_PCRx_TAR_Msk (0xFUL << FMC_PCRx_TAR_Pos)

#define	FMC_PCRx_TAR FMC_PCRx_TAR_Msk

#define	FMC_PCRx_TAR_0 (0x1UL << FMC_PCRx_TAR_Pos)

#define	FMC_PCRx_TAR_1 (0x2UL << FMC_PCRx_TAR_Pos)

#define	FMC_PCRx_TAR_2 (0x4UL << FMC_PCRx_TAR_Pos)

#define	FMC_PCRx_TAR_3 (0x8UL << FMC_PCRx_TAR_Pos)

#define	FMC_PCRx_ECCPS_Pos (17U)

#define	FMC_PCRx_ECCPS_Msk (0x7UL << FMC_PCRx_ECCPS_Pos)

#define	FMC_PCRx_ECCPS FMC_PCRx_ECCPS_Msk

#define	FMC_PCRx_ECCPS_0 (0x1UL << FMC_PCRx_ECCPS_Pos)

#define	FMC_PCRx_ECCPS_1 (0x2UL << FMC_PCRx_ECCPS_Pos)

#define	FMC_PCRx_ECCPS_2 (0x4UL << FMC_PCRx_ECCPS_Pos)

#define	FMC_PCR2_PWAITEN_Pos (1U)

#define	FMC_PCR2_PWAITEN_Msk (0x1UL << FMC_PCR2_PWAITEN_Pos)

#define	FMC_PCR2_PWAITEN FMC_PCR2_PWAITEN_Msk

#define	FMC_PCR2_PBKEN_Pos (2U)

#define	FMC_PCR2_PBKEN_Msk (0x1UL << FMC_PCR2_PBKEN_Pos)

#define	FMC_PCR2_PBKEN FMC_PCR2_PBKEN_Msk

#define	FMC_PCR2_PTYP_Pos (3U)

#define	FMC_PCR2_PTYP_Msk (0x1UL << FMC_PCR2_PTYP_Pos)

#define	FMC_PCR2_PTYP FMC_PCR2_PTYP_Msk

#define	FMC_PCR2_PWID_Pos (4U)

#define	FMC_PCR2_PWID_Msk (0x3UL << FMC_PCR2_PWID_Pos)

#define	FMC_PCR2_PWID FMC_PCR2_PWID_Msk

#define	FMC_PCR2_PWID_0 (0x1UL << FMC_PCR2_PWID_Pos)

#define	FMC_PCR2_PWID_1 (0x2UL << FMC_PCR2_PWID_Pos)

#define	FMC_PCR2_ECCEN_Pos (6U)

#define	FMC_PCR2_ECCEN_Msk (0x1UL << FMC_PCR2_ECCEN_Pos)

#define	FMC_PCR2_ECCEN FMC_PCR2_ECCEN_Msk

#define	FMC_PCR2_TCLR_Pos (9U)

#define	FMC_PCR2_TCLR_Msk (0xFUL << FMC_PCR2_TCLR_Pos)

#define	FMC_PCR2_TCLR FMC_PCR2_TCLR_Msk

#define	FMC_PCR2_TCLR_0 (0x1UL << FMC_PCR2_TCLR_Pos)

#define	FMC_PCR2_TCLR_1 (0x2UL << FMC_PCR2_TCLR_Pos)

#define	FMC_PCR2_TCLR_2 (0x4UL << FMC_PCR2_TCLR_Pos)

#define	FMC_PCR2_TCLR_3 (0x8UL << FMC_PCR2_TCLR_Pos)

#define	FMC_PCR2_TAR_Pos (13U)

#define	FMC_PCR2_TAR_Msk (0xFUL << FMC_PCR2_TAR_Pos)

#define	FMC_PCR2_TAR FMC_PCR2_TAR_Msk

#define	FMC_PCR2_TAR_0 (0x1UL << FMC_PCR2_TAR_Pos)

#define	FMC_PCR2_TAR_1 (0x2UL << FMC_PCR2_TAR_Pos)

#define	FMC_PCR2_TAR_2 (0x4UL << FMC_PCR2_TAR_Pos)

#define	FMC_PCR2_TAR_3 (0x8UL << FMC_PCR2_TAR_Pos)

#define	FMC_PCR2_ECCPS_Pos (17U)

#define	FMC_PCR2_ECCPS_Msk (0x7UL << FMC_PCR2_ECCPS_Pos)

#define	FMC_PCR2_ECCPS FMC_PCR2_ECCPS_Msk

#define	FMC_PCR2_ECCPS_0 (0x1UL << FMC_PCR2_ECCPS_Pos)

#define	FMC_PCR2_ECCPS_1 (0x2UL << FMC_PCR2_ECCPS_Pos)

#define	FMC_PCR2_ECCPS_2 (0x4UL << FMC_PCR2_ECCPS_Pos)

#define	FMC_PCR3_PWAITEN_Pos (1U)

#define	FMC_PCR3_PWAITEN_Msk (0x1UL << FMC_PCR3_PWAITEN_Pos)

#define	FMC_PCR3_PWAITEN FMC_PCR3_PWAITEN_Msk

#define	FMC_PCR3_PBKEN_Pos (2U)

#define	FMC_PCR3_PBKEN_Msk (0x1UL << FMC_PCR3_PBKEN_Pos)

#define	FMC_PCR3_PBKEN FMC_PCR3_PBKEN_Msk

#define	FMC_PCR3_PTYP_Pos (3U)

#define	FMC_PCR3_PTYP_Msk (0x1UL << FMC_PCR3_PTYP_Pos)

#define	FMC_PCR3_PTYP FMC_PCR3_PTYP_Msk

#define	FMC_PCR3_PWID_Pos (4U)

#define	FMC_PCR3_PWID_Msk (0x3UL << FMC_PCR3_PWID_Pos)

#define	FMC_PCR3_PWID FMC_PCR3_PWID_Msk

#define	FMC_PCR3_PWID_0 (0x1UL << FMC_PCR3_PWID_Pos)

#define	FMC_PCR3_PWID_1 (0x2UL << FMC_PCR3_PWID_Pos)

#define	FMC_PCR3_ECCEN_Pos (6U)

#define	FMC_PCR3_ECCEN_Msk (0x1UL << FMC_PCR3_ECCEN_Pos)

#define	FMC_PCR3_ECCEN FMC_PCR3_ECCEN_Msk

#define	FMC_PCR3_TCLR_Pos (9U)

#define	FMC_PCR3_TCLR_Msk (0xFUL << FMC_PCR3_TCLR_Pos)

#define	FMC_PCR3_TCLR FMC_PCR3_TCLR_Msk

#define	FMC_PCR3_TCLR_0 (0x1UL << FMC_PCR3_TCLR_Pos)

#define	FMC_PCR3_TCLR_1 (0x2UL << FMC_PCR3_TCLR_Pos)

#define	FMC_PCR3_TCLR_2 (0x4UL << FMC_PCR3_TCLR_Pos)

#define	FMC_PCR3_TCLR_3 (0x8UL << FMC_PCR3_TCLR_Pos)

#define	FMC_PCR3_TAR_Pos (13U)

#define	FMC_PCR3_TAR_Msk (0xFUL << FMC_PCR3_TAR_Pos)

#define	FMC_PCR3_TAR FMC_PCR3_TAR_Msk

#define	FMC_PCR3_TAR_0 (0x1UL << FMC_PCR3_TAR_Pos)

#define	FMC_PCR3_TAR_1 (0x2UL << FMC_PCR3_TAR_Pos)

#define	FMC_PCR3_TAR_2 (0x4UL << FMC_PCR3_TAR_Pos)

#define	FMC_PCR3_TAR_3 (0x8UL << FMC_PCR3_TAR_Pos)

#define	FMC_PCR3_ECCPS_Pos (17U)

#define	FMC_PCR3_ECCPS_Msk (0x7UL << FMC_PCR3_ECCPS_Pos)

#define	FMC_PCR3_ECCPS FMC_PCR3_ECCPS_Msk

#define	FMC_PCR3_ECCPS_0 (0x1UL << FMC_PCR3_ECCPS_Pos)

#define	FMC_PCR3_ECCPS_1 (0x2UL << FMC_PCR3_ECCPS_Pos)

#define	FMC_PCR3_ECCPS_2 (0x4UL << FMC_PCR3_ECCPS_Pos)

#define	FMC_PCR4_PWAITEN_Pos (1U)

#define	FMC_PCR4_PWAITEN_Msk (0x1UL << FMC_PCR4_PWAITEN_Pos)

#define	FMC_PCR4_PWAITEN FMC_PCR4_PWAITEN_Msk

#define	FMC_PCR4_PBKEN_Pos (2U)

#define	FMC_PCR4_PBKEN_Msk (0x1UL << FMC_PCR4_PBKEN_Pos)

#define	FMC_PCR4_PBKEN FMC_PCR4_PBKEN_Msk

#define	FMC_PCR4_PTYP_Pos (3U)

#define	FMC_PCR4_PTYP_Msk (0x1UL << FMC_PCR4_PTYP_Pos)

#define	FMC_PCR4_PTYP FMC_PCR4_PTYP_Msk

#define	FMC_PCR4_PWID_Pos (4U)

#define	FMC_PCR4_PWID_Msk (0x3UL << FMC_PCR4_PWID_Pos)

#define	FMC_PCR4_PWID FMC_PCR4_PWID_Msk

#define	FMC_PCR4_PWID_0 (0x1UL << FMC_PCR4_PWID_Pos)

#define	FMC_PCR4_PWID_1 (0x2UL << FMC_PCR4_PWID_Pos)

#define	FMC_PCR4_ECCEN_Pos (6U)

#define	FMC_PCR4_ECCEN_Msk (0x1UL << FMC_PCR4_ECCEN_Pos)

#define	FMC_PCR4_ECCEN FMC_PCR4_ECCEN_Msk

#define	FMC_PCR4_TCLR_Pos (9U)

#define	FMC_PCR4_TCLR_Msk (0xFUL << FMC_PCR4_TCLR_Pos)

#define	FMC_PCR4_TCLR FMC_PCR4_TCLR_Msk

#define	FMC_PCR4_TCLR_0 (0x1UL << FMC_PCR4_TCLR_Pos)

#define	FMC_PCR4_TCLR_1 (0x2UL << FMC_PCR4_TCLR_Pos)

#define	FMC_PCR4_TCLR_2 (0x4UL << FMC_PCR4_TCLR_Pos)

#define	FMC_PCR4_TCLR_3 (0x8UL << FMC_PCR4_TCLR_Pos)

#define	FMC_PCR4_TAR_Pos (13U)

#define	FMC_PCR4_TAR_Msk (0xFUL << FMC_PCR4_TAR_Pos)

#define	FMC_PCR4_TAR FMC_PCR4_TAR_Msk

#define	FMC_PCR4_TAR_0 (0x1UL << FMC_PCR4_TAR_Pos)

#define	FMC_PCR4_TAR_1 (0x2UL << FMC_PCR4_TAR_Pos)

#define	FMC_PCR4_TAR_2 (0x4UL << FMC_PCR4_TAR_Pos)

#define	FMC_PCR4_TAR_3 (0x8UL << FMC_PCR4_TAR_Pos)

#define	FMC_PCR4_ECCPS_Pos (17U)

#define	FMC_PCR4_ECCPS_Msk (0x7UL << FMC_PCR4_ECCPS_Pos)

#define	FMC_PCR4_ECCPS FMC_PCR4_ECCPS_Msk

#define	FMC_PCR4_ECCPS_0 (0x1UL << FMC_PCR4_ECCPS_Pos)

#define	FMC_PCR4_ECCPS_1 (0x2UL << FMC_PCR4_ECCPS_Pos)

#define	FMC_PCR4_ECCPS_2 (0x4UL << FMC_PCR4_ECCPS_Pos)

#define	FMC_SRx_IRS_Pos (0U)

#define	FMC_SRx_IRS_Msk (0x1UL << FMC_SRx_IRS_Pos)

#define	FMC_SRx_IRS FMC_SRx_IRS_Msk

#define	FMC_SRx_ILS_Pos (1U)

#define	FMC_SRx_ILS_Msk (0x1UL << FMC_SRx_ILS_Pos)

#define	FMC_SRx_ILS FMC_SRx_ILS_Msk

#define	FMC_SRx_IFS_Pos (2U)

#define	FMC_SRx_IFS_Msk (0x1UL << FMC_SRx_IFS_Pos)

#define	FMC_SRx_IFS FMC_SRx_IFS_Msk

#define	FMC_SRx_IREN_Pos (3U)

#define	FMC_SRx_IREN_Msk (0x1UL << FMC_SRx_IREN_Pos)

#define	FMC_SRx_IREN FMC_SRx_IREN_Msk

#define	FMC_SRx_ILEN_Pos (4U)

#define	FMC_SRx_ILEN_Msk (0x1UL << FMC_SRx_ILEN_Pos)

#define	FMC_SRx_ILEN FMC_SRx_ILEN_Msk

#define	FMC_SRx_IFEN_Pos (5U)

#define	FMC_SRx_IFEN_Msk (0x1UL << FMC_SRx_IFEN_Pos)

#define	FMC_SRx_IFEN FMC_SRx_IFEN_Msk

#define	FMC_SRx_FEMPT_Pos (6U)

#define	FMC_SRx_FEMPT_Msk (0x1UL << FMC_SRx_FEMPT_Pos)

#define	FMC_SRx_FEMPT FMC_SRx_FEMPT_Msk

#define	FMC_SR2_IRS_Pos (0U)

#define	FMC_SR2_IRS_Msk (0x1UL << FMC_SR2_IRS_Pos)

#define	FMC_SR2_IRS FMC_SR2_IRS_Msk

#define	FMC_SR2_ILS_Pos (1U)

#define	FMC_SR2_ILS_Msk (0x1UL << FMC_SR2_ILS_Pos)

#define	FMC_SR2_ILS FMC_SR2_ILS_Msk

#define	FMC_SR2_IFS_Pos (2U)

#define	FMC_SR2_IFS_Msk (0x1UL << FMC_SR2_IFS_Pos)

#define	FMC_SR2_IFS FMC_SR2_IFS_Msk

#define	FMC_SR2_IREN_Pos (3U)

#define	FMC_SR2_IREN_Msk (0x1UL << FMC_SR2_IREN_Pos)

#define	FMC_SR2_IREN FMC_SR2_IREN_Msk

#define	FMC_SR2_ILEN_Pos (4U)

#define	FMC_SR2_ILEN_Msk (0x1UL << FMC_SR2_ILEN_Pos)

#define	FMC_SR2_ILEN FMC_SR2_ILEN_Msk

#define	FMC_SR2_IFEN_Pos (5U)

#define	FMC_SR2_IFEN_Msk (0x1UL << FMC_SR2_IFEN_Pos)

#define	FMC_SR2_IFEN FMC_SR2_IFEN_Msk

#define	FMC_SR2_FEMPT_Pos (6U)

#define	FMC_SR2_FEMPT_Msk (0x1UL << FMC_SR2_FEMPT_Pos)

#define	FMC_SR2_FEMPT FMC_SR2_FEMPT_Msk

#define	FMC_SR3_IRS_Pos (0U)

#define	FMC_SR3_IRS_Msk (0x1UL << FMC_SR3_IRS_Pos)

#define	FMC_SR3_IRS FMC_SR3_IRS_Msk

#define	FMC_SR3_ILS_Pos (1U)

#define	FMC_SR3_ILS_Msk (0x1UL << FMC_SR3_ILS_Pos)

#define	FMC_SR3_ILS FMC_SR3_ILS_Msk

#define	FMC_SR3_IFS_Pos (2U)

#define	FMC_SR3_IFS_Msk (0x1UL << FMC_SR3_IFS_Pos)

#define	FMC_SR3_IFS FMC_SR3_IFS_Msk

#define	FMC_SR3_IREN_Pos (3U)

#define	FMC_SR3_IREN_Msk (0x1UL << FMC_SR3_IREN_Pos)

#define	FMC_SR3_IREN FMC_SR3_IREN_Msk

#define	FMC_SR3_ILEN_Pos (4U)

#define	FMC_SR3_ILEN_Msk (0x1UL << FMC_SR3_ILEN_Pos)

#define	FMC_SR3_ILEN FMC_SR3_ILEN_Msk

#define	FMC_SR3_IFEN_Pos (5U)

#define	FMC_SR3_IFEN_Msk (0x1UL << FMC_SR3_IFEN_Pos)

#define	FMC_SR3_IFEN FMC_SR3_IFEN_Msk

#define	FMC_SR3_FEMPT_Pos (6U)

#define	FMC_SR3_FEMPT_Msk (0x1UL << FMC_SR3_FEMPT_Pos)

#define	FMC_SR3_FEMPT FMC_SR3_FEMPT_Msk

#define	FMC_SR4_IRS_Pos (0U)

#define	FMC_SR4_IRS_Msk (0x1UL << FMC_SR4_IRS_Pos)

#define	FMC_SR4_IRS FMC_SR4_IRS_Msk

#define	FMC_SR4_ILS_Pos (1U)

#define	FMC_SR4_ILS_Msk (0x1UL << FMC_SR4_ILS_Pos)

#define	FMC_SR4_ILS FMC_SR4_ILS_Msk

#define	FMC_SR4_IFS_Pos (2U)

#define	FMC_SR4_IFS_Msk (0x1UL << FMC_SR4_IFS_Pos)

#define	FMC_SR4_IFS FMC_SR4_IFS_Msk

#define	FMC_SR4_IREN_Pos (3U)

#define	FMC_SR4_IREN_Msk (0x1UL << FMC_SR4_IREN_Pos)

#define	FMC_SR4_IREN FMC_SR4_IREN_Msk

#define	FMC_SR4_ILEN_Pos (4U)

#define	FMC_SR4_ILEN_Msk (0x1UL << FMC_SR4_ILEN_Pos)

#define	FMC_SR4_ILEN FMC_SR4_ILEN_Msk

#define	FMC_SR4_IFEN_Pos (5U)

#define	FMC_SR4_IFEN_Msk (0x1UL << FMC_SR4_IFEN_Pos)

#define	FMC_SR4_IFEN FMC_SR4_IFEN_Msk

#define	FMC_SR4_FEMPT_Pos (6U)

#define	FMC_SR4_FEMPT_Msk (0x1UL << FMC_SR4_FEMPT_Pos)

#define	FMC_SR4_FEMPT FMC_SR4_FEMPT_Msk

#define	FMC_PMEMx_MEMSETx_Pos (0U)

#define	FMC_PMEMx_MEMSETx_Msk (0xFFUL << FMC_PMEMx_MEMSETx_Pos)

#define	FMC_PMEMx_MEMSETx FMC_PMEMx_MEMSETx_Msk

#define	FMC_PMEMx_MEMSETx_0 (0x01UL << FMC_PMEMx_MEMSETx_Pos)

#define	FMC_PMEMx_MEMSETx_1 (0x02UL << FMC_PMEMx_MEMSETx_Pos)

#define	FMC_PMEMx_MEMSETx_2 (0x04UL << FMC_PMEMx_MEMSETx_Pos)

#define	FMC_PMEMx_MEMSETx_3 (0x08UL << FMC_PMEMx_MEMSETx_Pos)

#define	FMC_PMEMx_MEMSETx_4 (0x10UL << FMC_PMEMx_MEMSETx_Pos)

#define	FMC_PMEMx_MEMSETx_5 (0x20UL << FMC_PMEMx_MEMSETx_Pos)

#define	FMC_PMEMx_MEMSETx_6 (0x40UL << FMC_PMEMx_MEMSETx_Pos)

#define	FMC_PMEMx_MEMSETx_7 (0x80UL << FMC_PMEMx_MEMSETx_Pos)

#define	FMC_PMEMx_MEMWAITx_Pos (8U)

#define	FMC_PMEMx_MEMWAITx_Msk (0xFFUL << FMC_PMEMx_MEMWAITx_Pos)

#define	FMC_PMEMx_MEMWAITx FMC_PMEMx_MEMWAITx_Msk

#define	FMC_PMEMx_MEMWAITx_0 (0x01UL << FMC_PMEMx_MEMWAITx_Pos)

#define	FMC_PMEMx_MEMWAITx_1 (0x02UL << FMC_PMEMx_MEMWAITx_Pos)

#define	FMC_PMEMx_MEMWAITx_2 (0x04UL << FMC_PMEMx_MEMWAITx_Pos)

#define	FMC_PMEMx_MEMWAITx_3 (0x08UL << FMC_PMEMx_MEMWAITx_Pos)

#define	FMC_PMEMx_MEMWAITx_4 (0x10UL << FMC_PMEMx_MEMWAITx_Pos)

#define	FMC_PMEMx_MEMWAITx_5 (0x20UL << FMC_PMEMx_MEMWAITx_Pos)

#define	FMC_PMEMx_MEMWAITx_6 (0x40UL << FMC_PMEMx_MEMWAITx_Pos)

#define	FMC_PMEMx_MEMWAITx_7 (0x80UL << FMC_PMEMx_MEMWAITx_Pos)

#define	FMC_PMEMx_MEMHOLDx_Pos (16U)

#define	FMC_PMEMx_MEMHOLDx_Msk (0xFFUL << FMC_PMEMx_MEMHOLDx_Pos)

#define	FMC_PMEMx_MEMHOLDx FMC_PMEMx_MEMHOLDx_Msk

#define	FMC_PMEMx_MEMHOLDx_0 (0x01UL << FMC_PMEMx_MEMHOLDx_Pos)

#define	FMC_PMEMx_MEMHOLDx_1 (0x02UL << FMC_PMEMx_MEMHOLDx_Pos)

#define	FMC_PMEMx_MEMHOLDx_2 (0x04UL << FMC_PMEMx_MEMHOLDx_Pos)

#define	FMC_PMEMx_MEMHOLDx_3 (0x08UL << FMC_PMEMx_MEMHOLDx_Pos)

#define	FMC_PMEMx_MEMHOLDx_4 (0x10UL << FMC_PMEMx_MEMHOLDx_Pos)

#define	FMC_PMEMx_MEMHOLDx_5 (0x20UL << FMC_PMEMx_MEMHOLDx_Pos)

#define	FMC_PMEMx_MEMHOLDx_6 (0x40UL << FMC_PMEMx_MEMHOLDx_Pos)

#define	FMC_PMEMx_MEMHOLDx_7 (0x80UL << FMC_PMEMx_MEMHOLDx_Pos)

#define	FMC_PMEMx_MEMHIZx_Pos (24U)

#define	FMC_PMEMx_MEMHIZx_Msk (0xFFUL << FMC_PMEMx_MEMHIZx_Pos)

#define	FMC_PMEMx_MEMHIZx FMC_PMEMx_MEMHIZx_Msk

#define	FMC_PMEMx_MEMHIZx_0 (0x01UL << FMC_PMEMx_MEMHIZx_Pos)

#define	FMC_PMEMx_MEMHIZx_1 (0x02UL << FMC_PMEMx_MEMHIZx_Pos)

#define	FMC_PMEMx_MEMHIZx_2 (0x04UL << FMC_PMEMx_MEMHIZx_Pos)

#define	FMC_PMEMx_MEMHIZx_3 (0x08UL << FMC_PMEMx_MEMHIZx_Pos)

#define	FMC_PMEMx_MEMHIZx_4 (0x10UL << FMC_PMEMx_MEMHIZx_Pos)

#define	FMC_PMEMx_MEMHIZx_5 (0x20UL << FMC_PMEMx_MEMHIZx_Pos)

#define	FMC_PMEMx_MEMHIZx_6 (0x40UL << FMC_PMEMx_MEMHIZx_Pos)

#define	FMC_PMEMx_MEMHIZx_7 (0x80UL << FMC_PMEMx_MEMHIZx_Pos)

#define	FMC_PMEM2_MEMSET2_Pos (0U)

#define	FMC_PMEM2_MEMSET2_Msk (0xFFUL << FMC_PMEM2_MEMSET2_Pos)

#define	FMC_PMEM2_MEMSET2 FMC_PMEM2_MEMSET2_Msk

#define	FMC_PMEM2_MEMSET2_0 (0x01UL << FMC_PMEM2_MEMSET2_Pos)

#define	FMC_PMEM2_MEMSET2_1 (0x02UL << FMC_PMEM2_MEMSET2_Pos)

#define	FMC_PMEM2_MEMSET2_2 (0x04UL << FMC_PMEM2_MEMSET2_Pos)

#define	FMC_PMEM2_MEMSET2_3 (0x08UL << FMC_PMEM2_MEMSET2_Pos)

#define	FMC_PMEM2_MEMSET2_4 (0x10UL << FMC_PMEM2_MEMSET2_Pos)

#define	FMC_PMEM2_MEMSET2_5 (0x20UL << FMC_PMEM2_MEMSET2_Pos)

#define	FMC_PMEM2_MEMSET2_6 (0x40UL << FMC_PMEM2_MEMSET2_Pos)

#define	FMC_PMEM2_MEMSET2_7 (0x80UL << FMC_PMEM2_MEMSET2_Pos)

#define	FMC_PMEM2_MEMWAIT2_Pos (8U)

#define	FMC_PMEM2_MEMWAIT2_Msk (0xFFUL << FMC_PMEM2_MEMWAIT2_Pos)

#define	FMC_PMEM2_MEMWAIT2 FMC_PMEM2_MEMWAIT2_Msk

#define	FMC_PMEM2_MEMWAIT2_0 (0x01UL << FMC_PMEM2_MEMWAIT2_Pos)

#define	FMC_PMEM2_MEMWAIT2_1 (0x02UL << FMC_PMEM2_MEMWAIT2_Pos)

#define	FMC_PMEM2_MEMWAIT2_2 (0x04UL << FMC_PMEM2_MEMWAIT2_Pos)

#define	FMC_PMEM2_MEMWAIT2_3 (0x08UL << FMC_PMEM2_MEMWAIT2_Pos)

#define	FMC_PMEM2_MEMWAIT2_4 (0x10UL << FMC_PMEM2_MEMWAIT2_Pos)

#define	FMC_PMEM2_MEMWAIT2_5 (0x20UL << FMC_PMEM2_MEMWAIT2_Pos)

#define	FMC_PMEM2_MEMWAIT2_6 (0x40UL << FMC_PMEM2_MEMWAIT2_Pos)

#define	FMC_PMEM2_MEMWAIT2_7 (0x80UL << FMC_PMEM2_MEMWAIT2_Pos)

#define	FMC_PMEM2_MEMHOLD2_Pos (16U)

#define	FMC_PMEM2_MEMHOLD2_Msk (0xFFUL << FMC_PMEM2_MEMHOLD2_Pos)

#define	FMC_PMEM2_MEMHOLD2 FMC_PMEM2_MEMHOLD2_Msk

#define	FMC_PMEM2_MEMHOLD2_0 (0x01UL << FMC_PMEM2_MEMHOLD2_Pos)

#define	FMC_PMEM2_MEMHOLD2_1 (0x02UL << FMC_PMEM2_MEMHOLD2_Pos)

#define	FMC_PMEM2_MEMHOLD2_2 (0x04UL << FMC_PMEM2_MEMHOLD2_Pos)

#define	FMC_PMEM2_MEMHOLD2_3 (0x08UL << FMC_PMEM2_MEMHOLD2_Pos)

#define	FMC_PMEM2_MEMHOLD2_4 (0x10UL << FMC_PMEM2_MEMHOLD2_Pos)

#define	FMC_PMEM2_MEMHOLD2_5 (0x20UL << FMC_PMEM2_MEMHOLD2_Pos)

#define	FMC_PMEM2_MEMHOLD2_6 (0x40UL << FMC_PMEM2_MEMHOLD2_Pos)

#define	FMC_PMEM2_MEMHOLD2_7 (0x80UL << FMC_PMEM2_MEMHOLD2_Pos)

#define	FMC_PMEM2_MEMHIZ2_Pos (24U)

#define	FMC_PMEM2_MEMHIZ2_Msk (0xFFUL << FMC_PMEM2_MEMHIZ2_Pos)

#define	FMC_PMEM2_MEMHIZ2 FMC_PMEM2_MEMHIZ2_Msk

#define	FMC_PMEM2_MEMHIZ2_0 (0x01UL << FMC_PMEM2_MEMHIZ2_Pos)

#define	FMC_PMEM2_MEMHIZ2_1 (0x02UL << FMC_PMEM2_MEMHIZ2_Pos)

#define	FMC_PMEM2_MEMHIZ2_2 (0x04UL << FMC_PMEM2_MEMHIZ2_Pos)

#define	FMC_PMEM2_MEMHIZ2_3 (0x08UL << FMC_PMEM2_MEMHIZ2_Pos)

#define	FMC_PMEM2_MEMHIZ2_4 (0x10UL << FMC_PMEM2_MEMHIZ2_Pos)

#define	FMC_PMEM2_MEMHIZ2_5 (0x20UL << FMC_PMEM2_MEMHIZ2_Pos)

#define	FMC_PMEM2_MEMHIZ2_6 (0x40UL << FMC_PMEM2_MEMHIZ2_Pos)

#define	FMC_PMEM2_MEMHIZ2_7 (0x80UL << FMC_PMEM2_MEMHIZ2_Pos)

#define	FMC_PMEM3_MEMSET3_Pos (0U)

#define	FMC_PMEM3_MEMSET3_Msk (0xFFUL << FMC_PMEM3_MEMSET3_Pos)

#define	FMC_PMEM3_MEMSET3 FMC_PMEM3_MEMSET3_Msk

#define	FMC_PMEM3_MEMSET3_0 (0x01UL << FMC_PMEM3_MEMSET3_Pos)

#define	FMC_PMEM3_MEMSET3_1 (0x02UL << FMC_PMEM3_MEMSET3_Pos)

#define	FMC_PMEM3_MEMSET3_2 (0x04UL << FMC_PMEM3_MEMSET3_Pos)

#define	FMC_PMEM3_MEMSET3_3 (0x08UL << FMC_PMEM3_MEMSET3_Pos)

#define	FMC_PMEM3_MEMSET3_4 (0x10UL << FMC_PMEM3_MEMSET3_Pos)

#define	FMC_PMEM3_MEMSET3_5 (0x20UL << FMC_PMEM3_MEMSET3_Pos)

#define	FMC_PMEM3_MEMSET3_6 (0x40UL << FMC_PMEM3_MEMSET3_Pos)

#define	FMC_PMEM3_MEMSET3_7 (0x80UL << FMC_PMEM3_MEMSET3_Pos)

#define	FMC_PMEM3_MEMWAIT3_Pos (8U)

#define	FMC_PMEM3_MEMWAIT3_Msk (0xFFUL << FMC_PMEM3_MEMWAIT3_Pos)

#define	FMC_PMEM3_MEMWAIT3 FMC_PMEM3_MEMWAIT3_Msk

#define	FMC_PMEM3_MEMWAIT3_0 (0x01UL << FMC_PMEM3_MEMWAIT3_Pos)

#define	FMC_PMEM3_MEMWAIT3_1 (0x02UL << FMC_PMEM3_MEMWAIT3_Pos)

#define	FMC_PMEM3_MEMWAIT3_2 (0x04UL << FMC_PMEM3_MEMWAIT3_Pos)

#define	FMC_PMEM3_MEMWAIT3_3 (0x08UL << FMC_PMEM3_MEMWAIT3_Pos)

#define	FMC_PMEM3_MEMWAIT3_4 (0x10UL << FMC_PMEM3_MEMWAIT3_Pos)

#define	FMC_PMEM3_MEMWAIT3_5 (0x20UL << FMC_PMEM3_MEMWAIT3_Pos)

#define	FMC_PMEM3_MEMWAIT3_6 (0x40UL << FMC_PMEM3_MEMWAIT3_Pos)

#define	FMC_PMEM3_MEMWAIT3_7 (0x80UL << FMC_PMEM3_MEMWAIT3_Pos)

#define	FMC_PMEM3_MEMHOLD3_Pos (16U)

#define	FMC_PMEM3_MEMHOLD3_Msk (0xFFUL << FMC_PMEM3_MEMHOLD3_Pos)

#define	FMC_PMEM3_MEMHOLD3 FMC_PMEM3_MEMHOLD3_Msk

#define	FMC_PMEM3_MEMHOLD3_0 (0x01UL << FMC_PMEM3_MEMHOLD3_Pos)

#define	FMC_PMEM3_MEMHOLD3_1 (0x02UL << FMC_PMEM3_MEMHOLD3_Pos)

#define	FMC_PMEM3_MEMHOLD3_2 (0x04UL << FMC_PMEM3_MEMHOLD3_Pos)

#define	FMC_PMEM3_MEMHOLD3_3 (0x08UL << FMC_PMEM3_MEMHOLD3_Pos)

#define	FMC_PMEM3_MEMHOLD3_4 (0x10UL << FMC_PMEM3_MEMHOLD3_Pos)

#define	FMC_PMEM3_MEMHOLD3_5 (0x20UL << FMC_PMEM3_MEMHOLD3_Pos)

#define	FMC_PMEM3_MEMHOLD3_6 (0x40UL << FMC_PMEM3_MEMHOLD3_Pos)

#define	FMC_PMEM3_MEMHOLD3_7 (0x80UL << FMC_PMEM3_MEMHOLD3_Pos)

#define	FMC_PMEM3_MEMHIZ3_Pos (24U)

#define	FMC_PMEM3_MEMHIZ3_Msk (0xFFUL << FMC_PMEM3_MEMHIZ3_Pos)

#define	FMC_PMEM3_MEMHIZ3 FMC_PMEM3_MEMHIZ3_Msk

#define	FMC_PMEM3_MEMHIZ3_0 (0x01UL << FMC_PMEM3_MEMHIZ3_Pos)

#define	FMC_PMEM3_MEMHIZ3_1 (0x02UL << FMC_PMEM3_MEMHIZ3_Pos)

#define	FMC_PMEM3_MEMHIZ3_2 (0x04UL << FMC_PMEM3_MEMHIZ3_Pos)

#define	FMC_PMEM3_MEMHIZ3_3 (0x08UL << FMC_PMEM3_MEMHIZ3_Pos)

#define	FMC_PMEM3_MEMHIZ3_4 (0x10UL << FMC_PMEM3_MEMHIZ3_Pos)

#define	FMC_PMEM3_MEMHIZ3_5 (0x20UL << FMC_PMEM3_MEMHIZ3_Pos)

#define	FMC_PMEM3_MEMHIZ3_6 (0x40UL << FMC_PMEM3_MEMHIZ3_Pos)

#define	FMC_PMEM3_MEMHIZ3_7 (0x80UL << FMC_PMEM3_MEMHIZ3_Pos)

#define	FMC_PMEM4_MEMSET4_Pos (0U)

#define	FMC_PMEM4_MEMSET4_Msk (0xFFUL << FMC_PMEM4_MEMSET4_Pos)

#define	FMC_PMEM4_MEMSET4 FMC_PMEM4_MEMSET4_Msk

#define	FMC_PMEM4_MEMSET4_0 (0x01UL << FMC_PMEM4_MEMSET4_Pos)

#define	FMC_PMEM4_MEMSET4_1 (0x02UL << FMC_PMEM4_MEMSET4_Pos)

#define	FMC_PMEM4_MEMSET4_2 (0x04UL << FMC_PMEM4_MEMSET4_Pos)

#define	FMC_PMEM4_MEMSET4_3 (0x08UL << FMC_PMEM4_MEMSET4_Pos)

#define	FMC_PMEM4_MEMSET4_4 (0x10UL << FMC_PMEM4_MEMSET4_Pos)

#define	FMC_PMEM4_MEMSET4_5 (0x20UL << FMC_PMEM4_MEMSET4_Pos)

#define	FMC_PMEM4_MEMSET4_6 (0x40UL << FMC_PMEM4_MEMSET4_Pos)

#define	FMC_PMEM4_MEMSET4_7 (0x80UL << FMC_PMEM4_MEMSET4_Pos)

#define	FMC_PMEM4_MEMWAIT4_Pos (8U)

#define	FMC_PMEM4_MEMWAIT4_Msk (0xFFUL << FMC_PMEM4_MEMWAIT4_Pos)

#define	FMC_PMEM4_MEMWAIT4 FMC_PMEM4_MEMWAIT4_Msk

#define	FMC_PMEM4_MEMWAIT4_0 (0x01UL << FMC_PMEM4_MEMWAIT4_Pos)

#define	FMC_PMEM4_MEMWAIT4_1 (0x02UL << FMC_PMEM4_MEMWAIT4_Pos)

#define	FMC_PMEM4_MEMWAIT4_2 (0x04UL << FMC_PMEM4_MEMWAIT4_Pos)

#define	FMC_PMEM4_MEMWAIT4_3 (0x08UL << FMC_PMEM4_MEMWAIT4_Pos)

#define	FMC_PMEM4_MEMWAIT4_4 (0x10UL << FMC_PMEM4_MEMWAIT4_Pos)

#define	FMC_PMEM4_MEMWAIT4_5 (0x20UL << FMC_PMEM4_MEMWAIT4_Pos)

#define	FMC_PMEM4_MEMWAIT4_6 (0x40UL << FMC_PMEM4_MEMWAIT4_Pos)

#define	FMC_PMEM4_MEMWAIT4_7 (0x80UL << FMC_PMEM4_MEMWAIT4_Pos)

#define	FMC_PMEM4_MEMHOLD4_Pos (16U)

#define	FMC_PMEM4_MEMHOLD4_Msk (0xFFUL << FMC_PMEM4_MEMHOLD4_Pos)

#define	FMC_PMEM4_MEMHOLD4 FMC_PMEM4_MEMHOLD4_Msk

#define	FMC_PMEM4_MEMHOLD4_0 (0x01UL << FMC_PMEM4_MEMHOLD4_Pos)

#define	FMC_PMEM4_MEMHOLD4_1 (0x02UL << FMC_PMEM4_MEMHOLD4_Pos)

#define	FMC_PMEM4_MEMHOLD4_2 (0x04UL << FMC_PMEM4_MEMHOLD4_Pos)

#define	FMC_PMEM4_MEMHOLD4_3 (0x08UL << FMC_PMEM4_MEMHOLD4_Pos)

#define	FMC_PMEM4_MEMHOLD4_4 (0x10UL << FMC_PMEM4_MEMHOLD4_Pos)

#define	FMC_PMEM4_MEMHOLD4_5 (0x20UL << FMC_PMEM4_MEMHOLD4_Pos)

#define	FMC_PMEM4_MEMHOLD4_6 (0x40UL << FMC_PMEM4_MEMHOLD4_Pos)

#define	FMC_PMEM4_MEMHOLD4_7 (0x80UL << FMC_PMEM4_MEMHOLD4_Pos)

#define	FMC_PMEM4_MEMHIZ4_Pos (24U)

#define	FMC_PMEM4_MEMHIZ4_Msk (0xFFUL << FMC_PMEM4_MEMHIZ4_Pos)

#define	FMC_PMEM4_MEMHIZ4 FMC_PMEM4_MEMHIZ4_Msk

#define	FMC_PMEM4_MEMHIZ4_0 (0x01UL << FMC_PMEM4_MEMHIZ4_Pos)

#define	FMC_PMEM4_MEMHIZ4_1 (0x02UL << FMC_PMEM4_MEMHIZ4_Pos)

#define	FMC_PMEM4_MEMHIZ4_2 (0x04UL << FMC_PMEM4_MEMHIZ4_Pos)

#define	FMC_PMEM4_MEMHIZ4_3 (0x08UL << FMC_PMEM4_MEMHIZ4_Pos)

#define	FMC_PMEM4_MEMHIZ4_4 (0x10UL << FMC_PMEM4_MEMHIZ4_Pos)

#define	FMC_PMEM4_MEMHIZ4_5 (0x20UL << FMC_PMEM4_MEMHIZ4_Pos)

#define	FMC_PMEM4_MEMHIZ4_6 (0x40UL << FMC_PMEM4_MEMHIZ4_Pos)

#define	FMC_PMEM4_MEMHIZ4_7 (0x80UL << FMC_PMEM4_MEMHIZ4_Pos)

#define	FMC_PATTx_ATTSETx_Pos (0U)

#define	FMC_PATTx_ATTSETx_Msk (0xFFUL << FMC_PATTx_ATTSETx_Pos)

#define	FMC_PATTx_ATTSETx FMC_PATTx_ATTSETx_Msk

#define	FMC_PATTx_ATTSETx_0 (0x01UL << FMC_PATTx_ATTSETx_Pos)

#define	FMC_PATTx_ATTSETx_1 (0x02UL << FMC_PATTx_ATTSETx_Pos)

#define	FMC_PATTx_ATTSETx_2 (0x04UL << FMC_PATTx_ATTSETx_Pos)

#define	FMC_PATTx_ATTSETx_3 (0x08UL << FMC_PATTx_ATTSETx_Pos)

#define	FMC_PATTx_ATTSETx_4 (0x10UL << FMC_PATTx_ATTSETx_Pos)

#define	FMC_PATTx_ATTSETx_5 (0x20UL << FMC_PATTx_ATTSETx_Pos)

#define	FMC_PATTx_ATTSETx_6 (0x40UL << FMC_PATTx_ATTSETx_Pos)

#define	FMC_PATTx_ATTSETx_7 (0x80UL << FMC_PATTx_ATTSETx_Pos)

#define	FMC_PATTx_ATTWAITx_Pos (8U)

#define	FMC_PATTx_ATTWAITx_Msk (0xFFUL << FMC_PATTx_ATTWAITx_Pos)

#define	FMC_PATTx_ATTWAITx FMC_PATTx_ATTWAITx_Msk

#define	FMC_PATTx_ATTWAITx_0 (0x01UL << FMC_PATTx_ATTWAITx_Pos)

#define	FMC_PATTx_ATTWAITx_1 (0x02UL << FMC_PATTx_ATTWAITx_Pos)

#define	FMC_PATTx_ATTWAITx_2 (0x04UL << FMC_PATTx_ATTWAITx_Pos)

#define	FMC_PATTx_ATTWAITx_3 (0x08UL << FMC_PATTx_ATTWAITx_Pos)

#define	FMC_PATTx_ATTWAITx_4 (0x10UL << FMC_PATTx_ATTWAITx_Pos)

#define	FMC_PATTx_ATTWAITx_5 (0x20UL << FMC_PATTx_ATTWAITx_Pos)

#define	FMC_PATTx_ATTWAITx_6 (0x40UL << FMC_PATTx_ATTWAITx_Pos)

#define	FMC_PATTx_ATTWAITx_7 (0x80UL << FMC_PATTx_ATTWAITx_Pos)

#define	FMC_PATTx_ATTHOLDx_Pos (16U)

#define	FMC_PATTx_ATTHOLDx_Msk (0xFFUL << FMC_PATTx_ATTHOLDx_Pos)

#define	FMC_PATTx_ATTHOLDx FMC_PATTx_ATTHOLDx_Msk

#define	FMC_PATTx_ATTHOLDx_0 (0x01UL << FMC_PATTx_ATTHOLDx_Pos)

#define	FMC_PATTx_ATTHOLDx_1 (0x02UL << FMC_PATTx_ATTHOLDx_Pos)

#define	FMC_PATTx_ATTHOLDx_2 (0x04UL << FMC_PATTx_ATTHOLDx_Pos)

#define	FMC_PATTx_ATTHOLDx_3 (0x08UL << FMC_PATTx_ATTHOLDx_Pos)

#define	FMC_PATTx_ATTHOLDx_4 (0x10UL << FMC_PATTx_ATTHOLDx_Pos)

#define	FMC_PATTx_ATTHOLDx_5 (0x20UL << FMC_PATTx_ATTHOLDx_Pos)

#define	FMC_PATTx_ATTHOLDx_6 (0x40UL << FMC_PATTx_ATTHOLDx_Pos)

#define	FMC_PATTx_ATTHOLDx_7 (0x80UL << FMC_PATTx_ATTHOLDx_Pos)

#define	FMC_PATTx_ATTHIZx_Pos (24U)

#define	FMC_PATTx_ATTHIZx_Msk (0xFFUL << FMC_PATTx_ATTHIZx_Pos)

#define	FMC_PATTx_ATTHIZx FMC_PATTx_ATTHIZx_Msk

#define	FMC_PATTx_ATTHIZx_0 (0x01UL << FMC_PATTx_ATTHIZx_Pos)

#define	FMC_PATTx_ATTHIZx_1 (0x02UL << FMC_PATTx_ATTHIZx_Pos)

#define	FMC_PATTx_ATTHIZx_2 (0x04UL << FMC_PATTx_ATTHIZx_Pos)

#define	FMC_PATTx_ATTHIZx_3 (0x08UL << FMC_PATTx_ATTHIZx_Pos)

#define	FMC_PATTx_ATTHIZx_4 (0x10UL << FMC_PATTx_ATTHIZx_Pos)

#define	FMC_PATTx_ATTHIZx_5 (0x20UL << FMC_PATTx_ATTHIZx_Pos)

#define	FMC_PATTx_ATTHIZx_6 (0x40UL << FMC_PATTx_ATTHIZx_Pos)

#define	FMC_PATTx_ATTHIZx_7 (0x80UL << FMC_PATTx_ATTHIZx_Pos)

#define	FMC_PATT2_ATTSET2_Pos (0U)

#define	FMC_PATT2_ATTSET2_Msk (0xFFUL << FMC_PATT2_ATTSET2_Pos)

#define	FMC_PATT2_ATTSET2 FMC_PATT2_ATTSET2_Msk

#define	FMC_PATT2_ATTSET2_0 (0x01UL << FMC_PATT2_ATTSET2_Pos)

#define	FMC_PATT2_ATTSET2_1 (0x02UL << FMC_PATT2_ATTSET2_Pos)

#define	FMC_PATT2_ATTSET2_2 (0x04UL << FMC_PATT2_ATTSET2_Pos)

#define	FMC_PATT2_ATTSET2_3 (0x08UL << FMC_PATT2_ATTSET2_Pos)

#define	FMC_PATT2_ATTSET2_4 (0x10UL << FMC_PATT2_ATTSET2_Pos)

#define	FMC_PATT2_ATTSET2_5 (0x20UL << FMC_PATT2_ATTSET2_Pos)

#define	FMC_PATT2_ATTSET2_6 (0x40UL << FMC_PATT2_ATTSET2_Pos)

#define	FMC_PATT2_ATTSET2_7 (0x80UL << FMC_PATT2_ATTSET2_Pos)

#define	FMC_PATT2_ATTWAIT2_Pos (8U)

#define	FMC_PATT2_ATTWAIT2_Msk (0xFFUL << FMC_PATT2_ATTWAIT2_Pos)

#define	FMC_PATT2_ATTWAIT2 FMC_PATT2_ATTWAIT2_Msk

#define	FMC_PATT2_ATTWAIT2_0 (0x01UL << FMC_PATT2_ATTWAIT2_Pos)

#define	FMC_PATT2_ATTWAIT2_1 (0x02UL << FMC_PATT2_ATTWAIT2_Pos)

#define	FMC_PATT2_ATTWAIT2_2 (0x04UL << FMC_PATT2_ATTWAIT2_Pos)

#define	FMC_PATT2_ATTWAIT2_3 (0x08UL << FMC_PATT2_ATTWAIT2_Pos)

#define	FMC_PATT2_ATTWAIT2_4 (0x10UL << FMC_PATT2_ATTWAIT2_Pos)

#define	FMC_PATT2_ATTWAIT2_5 (0x20UL << FMC_PATT2_ATTWAIT2_Pos)

#define	FMC_PATT2_ATTWAIT2_6 (0x40UL << FMC_PATT2_ATTWAIT2_Pos)

#define	FMC_PATT2_ATTWAIT2_7 (0x80UL << FMC_PATT2_ATTWAIT2_Pos)

#define	FMC_PATT2_ATTHOLD2_Pos (16U)

#define	FMC_PATT2_ATTHOLD2_Msk (0xFFUL << FMC_PATT2_ATTHOLD2_Pos)

#define	FMC_PATT2_ATTHOLD2 FMC_PATT2_ATTHOLD2_Msk

#define	FMC_PATT2_ATTHOLD2_0 (0x01UL << FMC_PATT2_ATTHOLD2_Pos)

#define	FMC_PATT2_ATTHOLD2_1 (0x02UL << FMC_PATT2_ATTHOLD2_Pos)

#define	FMC_PATT2_ATTHOLD2_2 (0x04UL << FMC_PATT2_ATTHOLD2_Pos)

#define	FMC_PATT2_ATTHOLD2_3 (0x08UL << FMC_PATT2_ATTHOLD2_Pos)

#define	FMC_PATT2_ATTHOLD2_4 (0x10UL << FMC_PATT2_ATTHOLD2_Pos)

#define	FMC_PATT2_ATTHOLD2_5 (0x20UL << FMC_PATT2_ATTHOLD2_Pos)

#define	FMC_PATT2_ATTHOLD2_6 (0x40UL << FMC_PATT2_ATTHOLD2_Pos)

#define	FMC_PATT2_ATTHOLD2_7 (0x80UL << FMC_PATT2_ATTHOLD2_Pos)

#define	FMC_PATT2_ATTHIZ2_Pos (24U)

#define	FMC_PATT2_ATTHIZ2_Msk (0xFFUL << FMC_PATT2_ATTHIZ2_Pos)

#define	FMC_PATT2_ATTHIZ2 FMC_PATT2_ATTHIZ2_Msk

#define	FMC_PATT2_ATTHIZ2_0 (0x01UL << FMC_PATT2_ATTHIZ2_Pos)

#define	FMC_PATT2_ATTHIZ2_1 (0x02UL << FMC_PATT2_ATTHIZ2_Pos)

#define	FMC_PATT2_ATTHIZ2_2 (0x04UL << FMC_PATT2_ATTHIZ2_Pos)

#define	FMC_PATT2_ATTHIZ2_3 (0x08UL << FMC_PATT2_ATTHIZ2_Pos)

#define	FMC_PATT2_ATTHIZ2_4 (0x10UL << FMC_PATT2_ATTHIZ2_Pos)

#define	FMC_PATT2_ATTHIZ2_5 (0x20UL << FMC_PATT2_ATTHIZ2_Pos)

#define	FMC_PATT2_ATTHIZ2_6 (0x40UL << FMC_PATT2_ATTHIZ2_Pos)

#define	FMC_PATT2_ATTHIZ2_7 (0x80UL << FMC_PATT2_ATTHIZ2_Pos)

#define	FMC_PATT3_ATTSET3_Pos (0U)

#define	FMC_PATT3_ATTSET3_Msk (0xFFUL << FMC_PATT3_ATTSET3_Pos)

#define	FMC_PATT3_ATTSET3 FMC_PATT3_ATTSET3_Msk

#define	FMC_PATT3_ATTSET3_0 (0x01UL << FMC_PATT3_ATTSET3_Pos)

#define	FMC_PATT3_ATTSET3_1 (0x02UL << FMC_PATT3_ATTSET3_Pos)

#define	FMC_PATT3_ATTSET3_2 (0x04UL << FMC_PATT3_ATTSET3_Pos)

#define	FMC_PATT3_ATTSET3_3 (0x08UL << FMC_PATT3_ATTSET3_Pos)

#define	FMC_PATT3_ATTSET3_4 (0x10UL << FMC_PATT3_ATTSET3_Pos)

#define	FMC_PATT3_ATTSET3_5 (0x20UL << FMC_PATT3_ATTSET3_Pos)

#define	FMC_PATT3_ATTSET3_6 (0x40UL << FMC_PATT3_ATTSET3_Pos)

#define	FMC_PATT3_ATTSET3_7 (0x80UL << FMC_PATT3_ATTSET3_Pos)

#define	FMC_PATT3_ATTWAIT3_Pos (8U)

#define	FMC_PATT3_ATTWAIT3_Msk (0xFFUL << FMC_PATT3_ATTWAIT3_Pos)

#define	FMC_PATT3_ATTWAIT3 FMC_PATT3_ATTWAIT3_Msk

#define	FMC_PATT3_ATTWAIT3_0 (0x01UL << FMC_PATT3_ATTWAIT3_Pos)

#define	FMC_PATT3_ATTWAIT3_1 (0x02UL << FMC_PATT3_ATTWAIT3_Pos)

#define	FMC_PATT3_ATTWAIT3_2 (0x04UL << FMC_PATT3_ATTWAIT3_Pos)

#define	FMC_PATT3_ATTWAIT3_3 (0x08UL << FMC_PATT3_ATTWAIT3_Pos)

#define	FMC_PATT3_ATTWAIT3_4 (0x10UL << FMC_PATT3_ATTWAIT3_Pos)

#define	FMC_PATT3_ATTWAIT3_5 (0x20UL << FMC_PATT3_ATTWAIT3_Pos)

#define	FMC_PATT3_ATTWAIT3_6 (0x40UL << FMC_PATT3_ATTWAIT3_Pos)

#define	FMC_PATT3_ATTWAIT3_7 (0x80UL << FMC_PATT3_ATTWAIT3_Pos)

#define	FMC_PATT3_ATTHOLD3_Pos (16U)

#define	FMC_PATT3_ATTHOLD3_Msk (0xFFUL << FMC_PATT3_ATTHOLD3_Pos)

#define	FMC_PATT3_ATTHOLD3 FMC_PATT3_ATTHOLD3_Msk

#define	FMC_PATT3_ATTHOLD3_0 (0x01UL << FMC_PATT3_ATTHOLD3_Pos)

#define	FMC_PATT3_ATTHOLD3_1 (0x02UL << FMC_PATT3_ATTHOLD3_Pos)

#define	FMC_PATT3_ATTHOLD3_2 (0x04UL << FMC_PATT3_ATTHOLD3_Pos)

#define	FMC_PATT3_ATTHOLD3_3 (0x08UL << FMC_PATT3_ATTHOLD3_Pos)

#define	FMC_PATT3_ATTHOLD3_4 (0x10UL << FMC_PATT3_ATTHOLD3_Pos)

#define	FMC_PATT3_ATTHOLD3_5 (0x20UL << FMC_PATT3_ATTHOLD3_Pos)

#define	FMC_PATT3_ATTHOLD3_6 (0x40UL << FMC_PATT3_ATTHOLD3_Pos)

#define	FMC_PATT3_ATTHOLD3_7 (0x80UL << FMC_PATT3_ATTHOLD3_Pos)

#define	FMC_PATT3_ATTHIZ3_Pos (24U)

#define	FMC_PATT3_ATTHIZ3_Msk (0xFFUL << FMC_PATT3_ATTHIZ3_Pos)

#define	FMC_PATT3_ATTHIZ3 FMC_PATT3_ATTHIZ3_Msk

#define	FMC_PATT3_ATTHIZ3_0 (0x01UL << FMC_PATT3_ATTHIZ3_Pos)

#define	FMC_PATT3_ATTHIZ3_1 (0x02UL << FMC_PATT3_ATTHIZ3_Pos)

#define	FMC_PATT3_ATTHIZ3_2 (0x04UL << FMC_PATT3_ATTHIZ3_Pos)

#define	FMC_PATT3_ATTHIZ3_3 (0x08UL << FMC_PATT3_ATTHIZ3_Pos)

#define	FMC_PATT3_ATTHIZ3_4 (0x10UL << FMC_PATT3_ATTHIZ3_Pos)

#define	FMC_PATT3_ATTHIZ3_5 (0x20UL << FMC_PATT3_ATTHIZ3_Pos)

#define	FMC_PATT3_ATTHIZ3_6 (0x40UL << FMC_PATT3_ATTHIZ3_Pos)

#define	FMC_PATT3_ATTHIZ3_7 (0x80UL << FMC_PATT3_ATTHIZ3_Pos)

#define	FMC_PATT4_ATTSET4_Pos (0U)

#define	FMC_PATT4_ATTSET4_Msk (0xFFUL << FMC_PATT4_ATTSET4_Pos)

#define	FMC_PATT4_ATTSET4 FMC_PATT4_ATTSET4_Msk

#define	FMC_PATT4_ATTSET4_0 (0x01UL << FMC_PATT4_ATTSET4_Pos)

#define	FMC_PATT4_ATTSET4_1 (0x02UL << FMC_PATT4_ATTSET4_Pos)

#define	FMC_PATT4_ATTSET4_2 (0x04UL << FMC_PATT4_ATTSET4_Pos)

#define	FMC_PATT4_ATTSET4_3 (0x08UL << FMC_PATT4_ATTSET4_Pos)

#define	FMC_PATT4_ATTSET4_4 (0x10UL << FMC_PATT4_ATTSET4_Pos)

#define	FMC_PATT4_ATTSET4_5 (0x20UL << FMC_PATT4_ATTSET4_Pos)

#define	FMC_PATT4_ATTSET4_6 (0x40UL << FMC_PATT4_ATTSET4_Pos)

#define	FMC_PATT4_ATTSET4_7 (0x80UL << FMC_PATT4_ATTSET4_Pos)

#define	FMC_PATT4_ATTWAIT4_Pos (8U)

#define	FMC_PATT4_ATTWAIT4_Msk (0xFFUL << FMC_PATT4_ATTWAIT4_Pos)

#define	FMC_PATT4_ATTWAIT4 FMC_PATT4_ATTWAIT4_Msk

#define	FMC_PATT4_ATTWAIT4_0 (0x01UL << FMC_PATT4_ATTWAIT4_Pos)

#define	FMC_PATT4_ATTWAIT4_1 (0x02UL << FMC_PATT4_ATTWAIT4_Pos)

#define	FMC_PATT4_ATTWAIT4_2 (0x04UL << FMC_PATT4_ATTWAIT4_Pos)

#define	FMC_PATT4_ATTWAIT4_3 (0x08UL << FMC_PATT4_ATTWAIT4_Pos)

#define	FMC_PATT4_ATTWAIT4_4 (0x10UL << FMC_PATT4_ATTWAIT4_Pos)

#define	FMC_PATT4_ATTWAIT4_5 (0x20UL << FMC_PATT4_ATTWAIT4_Pos)

#define	FMC_PATT4_ATTWAIT4_6 (0x40UL << FMC_PATT4_ATTWAIT4_Pos)

#define	FMC_PATT4_ATTWAIT4_7 (0x80UL << FMC_PATT4_ATTWAIT4_Pos)

#define	FMC_PATT4_ATTHOLD4_Pos (16U)

#define	FMC_PATT4_ATTHOLD4_Msk (0xFFUL << FMC_PATT4_ATTHOLD4_Pos)

#define	FMC_PATT4_ATTHOLD4 FMC_PATT4_ATTHOLD4_Msk

#define	FMC_PATT4_ATTHOLD4_0 (0x01UL << FMC_PATT4_ATTHOLD4_Pos)

#define	FMC_PATT4_ATTHOLD4_1 (0x02UL << FMC_PATT4_ATTHOLD4_Pos)

#define	FMC_PATT4_ATTHOLD4_2 (0x04UL << FMC_PATT4_ATTHOLD4_Pos)

#define	FMC_PATT4_ATTHOLD4_3 (0x08UL << FMC_PATT4_ATTHOLD4_Pos)

#define	FMC_PATT4_ATTHOLD4_4 (0x10UL << FMC_PATT4_ATTHOLD4_Pos)

#define	FMC_PATT4_ATTHOLD4_5 (0x20UL << FMC_PATT4_ATTHOLD4_Pos)

#define	FMC_PATT4_ATTHOLD4_6 (0x40UL << FMC_PATT4_ATTHOLD4_Pos)

#define	FMC_PATT4_ATTHOLD4_7 (0x80UL << FMC_PATT4_ATTHOLD4_Pos)

#define	FMC_PATT4_ATTHIZ4_Pos (24U)

#define	FMC_PATT4_ATTHIZ4_Msk (0xFFUL << FMC_PATT4_ATTHIZ4_Pos)

#define	FMC_PATT4_ATTHIZ4 FMC_PATT4_ATTHIZ4_Msk

#define	FMC_PATT4_ATTHIZ4_0 (0x01UL << FMC_PATT4_ATTHIZ4_Pos)

#define	FMC_PATT4_ATTHIZ4_1 (0x02UL << FMC_PATT4_ATTHIZ4_Pos)

#define	FMC_PATT4_ATTHIZ4_2 (0x04UL << FMC_PATT4_ATTHIZ4_Pos)

#define	FMC_PATT4_ATTHIZ4_3 (0x08UL << FMC_PATT4_ATTHIZ4_Pos)

#define	FMC_PATT4_ATTHIZ4_4 (0x10UL << FMC_PATT4_ATTHIZ4_Pos)

#define	FMC_PATT4_ATTHIZ4_5 (0x20UL << FMC_PATT4_ATTHIZ4_Pos)

#define	FMC_PATT4_ATTHIZ4_6 (0x40UL << FMC_PATT4_ATTHIZ4_Pos)

#define	FMC_PATT4_ATTHIZ4_7 (0x80UL << FMC_PATT4_ATTHIZ4_Pos)

#define	FMC_PIO4_IOSET4_Pos (0U)

#define	FMC_PIO4_IOSET4_Msk (0xFFUL << FMC_PIO4_IOSET4_Pos)

#define	FMC_PIO4_IOSET4 FMC_PIO4_IOSET4_Msk

#define	FMC_PIO4_IOSET4_0 (0x01UL << FMC_PIO4_IOSET4_Pos)

#define	FMC_PIO4_IOSET4_1 (0x02UL << FMC_PIO4_IOSET4_Pos)

#define	FMC_PIO4_IOSET4_2 (0x04UL << FMC_PIO4_IOSET4_Pos)

#define	FMC_PIO4_IOSET4_3 (0x08UL << FMC_PIO4_IOSET4_Pos)

#define	FMC_PIO4_IOSET4_4 (0x10UL << FMC_PIO4_IOSET4_Pos)

#define	FMC_PIO4_IOSET4_5 (0x20UL << FMC_PIO4_IOSET4_Pos)

#define	FMC_PIO4_IOSET4_6 (0x40UL << FMC_PIO4_IOSET4_Pos)

#define	FMC_PIO4_IOSET4_7 (0x80UL << FMC_PIO4_IOSET4_Pos)

#define	FMC_PIO4_IOWAIT4_Pos (8U)

#define	FMC_PIO4_IOWAIT4_Msk (0xFFUL << FMC_PIO4_IOWAIT4_Pos)

#define	FMC_PIO4_IOWAIT4 FMC_PIO4_IOWAIT4_Msk

#define	FMC_PIO4_IOWAIT4_0 (0x01UL << FMC_PIO4_IOWAIT4_Pos)

#define	FMC_PIO4_IOWAIT4_1 (0x02UL << FMC_PIO4_IOWAIT4_Pos)

#define	FMC_PIO4_IOWAIT4_2 (0x04UL << FMC_PIO4_IOWAIT4_Pos)

#define	FMC_PIO4_IOWAIT4_3 (0x08UL << FMC_PIO4_IOWAIT4_Pos)

#define	FMC_PIO4_IOWAIT4_4 (0x10UL << FMC_PIO4_IOWAIT4_Pos)

#define	FMC_PIO4_IOWAIT4_5 (0x20UL << FMC_PIO4_IOWAIT4_Pos)

#define	FMC_PIO4_IOWAIT4_6 (0x40UL << FMC_PIO4_IOWAIT4_Pos)

#define	FMC_PIO4_IOWAIT4_7 (0x80UL << FMC_PIO4_IOWAIT4_Pos)

#define	FMC_PIO4_IOHOLD4_Pos (16U)

#define	FMC_PIO4_IOHOLD4_Msk (0xFFUL << FMC_PIO4_IOHOLD4_Pos)

#define	FMC_PIO4_IOHOLD4 FMC_PIO4_IOHOLD4_Msk

#define	FMC_PIO4_IOHOLD4_0 (0x01UL << FMC_PIO4_IOHOLD4_Pos)

#define	FMC_PIO4_IOHOLD4_1 (0x02UL << FMC_PIO4_IOHOLD4_Pos)

#define	FMC_PIO4_IOHOLD4_2 (0x04UL << FMC_PIO4_IOHOLD4_Pos)

#define	FMC_PIO4_IOHOLD4_3 (0x08UL << FMC_PIO4_IOHOLD4_Pos)

#define	FMC_PIO4_IOHOLD4_4 (0x10UL << FMC_PIO4_IOHOLD4_Pos)

#define	FMC_PIO4_IOHOLD4_5 (0x20UL << FMC_PIO4_IOHOLD4_Pos)

#define	FMC_PIO4_IOHOLD4_6 (0x40UL << FMC_PIO4_IOHOLD4_Pos)

#define	FMC_PIO4_IOHOLD4_7 (0x80UL << FMC_PIO4_IOHOLD4_Pos)

#define	FMC_PIO4_IOHIZ4_Pos (24U)

#define	FMC_PIO4_IOHIZ4_Msk (0xFFUL << FMC_PIO4_IOHIZ4_Pos)

#define	FMC_PIO4_IOHIZ4 FMC_PIO4_IOHIZ4_Msk

#define	FMC_PIO4_IOHIZ4_0 (0x01UL << FMC_PIO4_IOHIZ4_Pos)

#define	FMC_PIO4_IOHIZ4_1 (0x02UL << FMC_PIO4_IOHIZ4_Pos)

#define	FMC_PIO4_IOHIZ4_2 (0x04UL << FMC_PIO4_IOHIZ4_Pos)

#define	FMC_PIO4_IOHIZ4_3 (0x08UL << FMC_PIO4_IOHIZ4_Pos)

#define	FMC_PIO4_IOHIZ4_4 (0x10UL << FMC_PIO4_IOHIZ4_Pos)

#define	FMC_PIO4_IOHIZ4_5 (0x20UL << FMC_PIO4_IOHIZ4_Pos)

#define	FMC_PIO4_IOHIZ4_6 (0x40UL << FMC_PIO4_IOHIZ4_Pos)

#define	FMC_PIO4_IOHIZ4_7 (0x80UL << FMC_PIO4_IOHIZ4_Pos)

#define	FMC_ECCR2_ECC2_Pos (0U)

#define	FMC_ECCR2_ECC2_Msk (0xFFFFFFFFUL << FMC_ECCR2_ECC2_Pos)

#define	FMC_ECCR2_ECC2 FMC_ECCR2_ECC2_Msk

#define	FMC_ECCR3_ECC3_Pos (0U)

#define	FMC_ECCR3_ECC3_Msk (0xFFFFFFFFUL << FMC_ECCR3_ECC3_Pos)

#define	FMC_ECCR3_ECC3 FMC_ECCR3_ECC3_Msk

#define	GPIO_MODER_MODER0_Pos (0U)

#define	GPIO_MODER_MODER0_Msk (0x3UL << GPIO_MODER_MODER0_Pos)

#define	GPIO_MODER_MODER0 GPIO_MODER_MODER0_Msk

#define	GPIO_MODER_MODER0_0 (0x1UL << GPIO_MODER_MODER0_Pos)

#define	GPIO_MODER_MODER0_1 (0x2UL << GPIO_MODER_MODER0_Pos)

#define	GPIO_MODER_MODER1_Pos (2U)

#define	GPIO_MODER_MODER1_Msk (0x3UL << GPIO_MODER_MODER1_Pos)

#define	GPIO_MODER_MODER1 GPIO_MODER_MODER1_Msk

#define	GPIO_MODER_MODER1_0 (0x1UL << GPIO_MODER_MODER1_Pos)

#define	GPIO_MODER_MODER1_1 (0x2UL << GPIO_MODER_MODER1_Pos)

#define	GPIO_MODER_MODER2_Pos (4U)

#define	GPIO_MODER_MODER2_Msk (0x3UL << GPIO_MODER_MODER2_Pos)

#define	GPIO_MODER_MODER2 GPIO_MODER_MODER2_Msk

#define	GPIO_MODER_MODER2_0 (0x1UL << GPIO_MODER_MODER2_Pos)

#define	GPIO_MODER_MODER2_1 (0x2UL << GPIO_MODER_MODER2_Pos)

#define	GPIO_MODER_MODER3_Pos (6U)

#define	GPIO_MODER_MODER3_Msk (0x3UL << GPIO_MODER_MODER3_Pos)

#define	GPIO_MODER_MODER3 GPIO_MODER_MODER3_Msk

#define	GPIO_MODER_MODER3_0 (0x1UL << GPIO_MODER_MODER3_Pos)

#define	GPIO_MODER_MODER3_1 (0x2UL << GPIO_MODER_MODER3_Pos)

#define	GPIO_MODER_MODER4_Pos (8U)

#define	GPIO_MODER_MODER4_Msk (0x3UL << GPIO_MODER_MODER4_Pos)

#define	GPIO_MODER_MODER4 GPIO_MODER_MODER4_Msk

#define	GPIO_MODER_MODER4_0 (0x1UL << GPIO_MODER_MODER4_Pos)

#define	GPIO_MODER_MODER4_1 (0x2UL << GPIO_MODER_MODER4_Pos)

#define	GPIO_MODER_MODER5_Pos (10U)

#define	GPIO_MODER_MODER5_Msk (0x3UL << GPIO_MODER_MODER5_Pos)

#define	GPIO_MODER_MODER5 GPIO_MODER_MODER5_Msk

#define	GPIO_MODER_MODER5_0 (0x1UL << GPIO_MODER_MODER5_Pos)

#define	GPIO_MODER_MODER5_1 (0x2UL << GPIO_MODER_MODER5_Pos)

#define	GPIO_MODER_MODER6_Pos (12U)

#define	GPIO_MODER_MODER6_Msk (0x3UL << GPIO_MODER_MODER6_Pos)

#define	GPIO_MODER_MODER6 GPIO_MODER_MODER6_Msk

#define	GPIO_MODER_MODER6_0 (0x1UL << GPIO_MODER_MODER6_Pos)

#define	GPIO_MODER_MODER6_1 (0x2UL << GPIO_MODER_MODER6_Pos)

#define	GPIO_MODER_MODER7_Pos (14U)

#define	GPIO_MODER_MODER7_Msk (0x3UL << GPIO_MODER_MODER7_Pos)

#define	GPIO_MODER_MODER7 GPIO_MODER_MODER7_Msk

#define	GPIO_MODER_MODER7_0 (0x1UL << GPIO_MODER_MODER7_Pos)

#define	GPIO_MODER_MODER7_1 (0x2UL << GPIO_MODER_MODER7_Pos)

#define	GPIO_MODER_MODER8_Pos (16U)

#define	GPIO_MODER_MODER8_Msk (0x3UL << GPIO_MODER_MODER8_Pos)

#define	GPIO_MODER_MODER8 GPIO_MODER_MODER8_Msk

#define	GPIO_MODER_MODER8_0 (0x1UL << GPIO_MODER_MODER8_Pos)

#define	GPIO_MODER_MODER8_1 (0x2UL << GPIO_MODER_MODER8_Pos)

#define	GPIO_MODER_MODER9_Pos (18U)

#define	GPIO_MODER_MODER9_Msk (0x3UL << GPIO_MODER_MODER9_Pos)

#define	GPIO_MODER_MODER9 GPIO_MODER_MODER9_Msk

#define	GPIO_MODER_MODER9_0 (0x1UL << GPIO_MODER_MODER9_Pos)

#define	GPIO_MODER_MODER9_1 (0x2UL << GPIO_MODER_MODER9_Pos)

#define	GPIO_MODER_MODER10_Pos (20U)

#define	GPIO_MODER_MODER10_Msk (0x3UL << GPIO_MODER_MODER10_Pos)

#define	GPIO_MODER_MODER10 GPIO_MODER_MODER10_Msk

#define	GPIO_MODER_MODER10_0 (0x1UL << GPIO_MODER_MODER10_Pos)

#define	GPIO_MODER_MODER10_1 (0x2UL << GPIO_MODER_MODER10_Pos)

#define	GPIO_MODER_MODER11_Pos (22U)

#define	GPIO_MODER_MODER11_Msk (0x3UL << GPIO_MODER_MODER11_Pos)

#define	GPIO_MODER_MODER11 GPIO_MODER_MODER11_Msk

#define	GPIO_MODER_MODER11_0 (0x1UL << GPIO_MODER_MODER11_Pos)

#define	GPIO_MODER_MODER11_1 (0x2UL << GPIO_MODER_MODER11_Pos)

#define	GPIO_MODER_MODER12_Pos (24U)

#define	GPIO_MODER_MODER12_Msk (0x3UL << GPIO_MODER_MODER12_Pos)

#define	GPIO_MODER_MODER12 GPIO_MODER_MODER12_Msk

#define	GPIO_MODER_MODER12_0 (0x1UL << GPIO_MODER_MODER12_Pos)

#define	GPIO_MODER_MODER12_1 (0x2UL << GPIO_MODER_MODER12_Pos)

#define	GPIO_MODER_MODER13_Pos (26U)

#define	GPIO_MODER_MODER13_Msk (0x3UL << GPIO_MODER_MODER13_Pos)

#define	GPIO_MODER_MODER13 GPIO_MODER_MODER13_Msk

#define	GPIO_MODER_MODER13_0 (0x1UL << GPIO_MODER_MODER13_Pos)

#define	GPIO_MODER_MODER13_1 (0x2UL << GPIO_MODER_MODER13_Pos)

#define	GPIO_MODER_MODER14_Pos (28U)

#define	GPIO_MODER_MODER14_Msk (0x3UL << GPIO_MODER_MODER14_Pos)

#define	GPIO_MODER_MODER14 GPIO_MODER_MODER14_Msk

#define	GPIO_MODER_MODER14_0 (0x1UL << GPIO_MODER_MODER14_Pos)

#define	GPIO_MODER_MODER14_1 (0x2UL << GPIO_MODER_MODER14_Pos)

#define	GPIO_MODER_MODER15_Pos (30U)

#define	GPIO_MODER_MODER15_Msk (0x3UL << GPIO_MODER_MODER15_Pos)

#define	GPIO_MODER_MODER15 GPIO_MODER_MODER15_Msk

#define	GPIO_MODER_MODER15_0 (0x1UL << GPIO_MODER_MODER15_Pos)

#define	GPIO_MODER_MODER15_1 (0x2UL << GPIO_MODER_MODER15_Pos)

#define	GPIO_OTYPER_OT_0 (0x00000001U)

#define	GPIO_OTYPER_OT_1 (0x00000002U)

#define	GPIO_OTYPER_OT_2 (0x00000004U)

#define	GPIO_OTYPER_OT_3 (0x00000008U)

#define	GPIO_OTYPER_OT_4 (0x00000010U)

#define	GPIO_OTYPER_OT_5 (0x00000020U)

#define	GPIO_OTYPER_OT_6 (0x00000040U)

#define	GPIO_OTYPER_OT_7 (0x00000080U)

#define	GPIO_OTYPER_OT_8 (0x00000100U)

#define	GPIO_OTYPER_OT_9 (0x00000200U)

#define	GPIO_OTYPER_OT_10 (0x00000400U)

#define	GPIO_OTYPER_OT_11 (0x00000800U)

#define	GPIO_OTYPER_OT_12 (0x00001000U)

#define	GPIO_OTYPER_OT_13 (0x00002000U)

#define	GPIO_OTYPER_OT_14 (0x00004000U)

#define	GPIO_OTYPER_OT_15 (0x00008000U)

#define	GPIO_OSPEEDER_OSPEEDR0_Pos (0U)

#define	GPIO_OSPEEDER_OSPEEDR0_Msk (0x3UL << GPIO_OSPEEDER_OSPEEDR0_Pos)

#define	GPIO_OSPEEDER_OSPEEDR0 GPIO_OSPEEDER_OSPEEDR0_Msk

#define	GPIO_OSPEEDER_OSPEEDR0_0 (0x1UL << GPIO_OSPEEDER_OSPEEDR0_Pos)

#define	GPIO_OSPEEDER_OSPEEDR0_1 (0x2UL << GPIO_OSPEEDER_OSPEEDR0_Pos)

#define	GPIO_OSPEEDER_OSPEEDR1_Pos (2U)

#define	GPIO_OSPEEDER_OSPEEDR1_Msk (0x3UL << GPIO_OSPEEDER_OSPEEDR1_Pos)

#define	GPIO_OSPEEDER_OSPEEDR1 GPIO_OSPEEDER_OSPEEDR1_Msk

#define	GPIO_OSPEEDER_OSPEEDR1_0 (0x1UL << GPIO_OSPEEDER_OSPEEDR1_Pos)

#define	GPIO_OSPEEDER_OSPEEDR1_1 (0x2UL << GPIO_OSPEEDER_OSPEEDR1_Pos)

#define	GPIO_OSPEEDER_OSPEEDR2_Pos (4U)

#define	GPIO_OSPEEDER_OSPEEDR2_Msk (0x3UL << GPIO_OSPEEDER_OSPEEDR2_Pos)

#define	GPIO_OSPEEDER_OSPEEDR2 GPIO_OSPEEDER_OSPEEDR2_Msk

#define	GPIO_OSPEEDER_OSPEEDR2_0 (0x1UL << GPIO_OSPEEDER_OSPEEDR2_Pos)

#define	GPIO_OSPEEDER_OSPEEDR2_1 (0x2UL << GPIO_OSPEEDER_OSPEEDR2_Pos)

#define	GPIO_OSPEEDER_OSPEEDR3_Pos (6U)

#define	GPIO_OSPEEDER_OSPEEDR3_Msk (0x3UL << GPIO_OSPEEDER_OSPEEDR3_Pos)

#define	GPIO_OSPEEDER_OSPEEDR3 GPIO_OSPEEDER_OSPEEDR3_Msk

#define	GPIO_OSPEEDER_OSPEEDR3_0 (0x1UL << GPIO_OSPEEDER_OSPEEDR3_Pos)

#define	GPIO_OSPEEDER_OSPEEDR3_1 (0x2UL << GPIO_OSPEEDER_OSPEEDR3_Pos)

#define	GPIO_OSPEEDER_OSPEEDR4_Pos (8U)

#define	GPIO_OSPEEDER_OSPEEDR4_Msk (0x3UL << GPIO_OSPEEDER_OSPEEDR4_Pos)

#define	GPIO_OSPEEDER_OSPEEDR4 GPIO_OSPEEDER_OSPEEDR4_Msk

#define	GPIO_OSPEEDER_OSPEEDR4_0 (0x1UL << GPIO_OSPEEDER_OSPEEDR4_Pos)

#define	GPIO_OSPEEDER_OSPEEDR4_1 (0x2UL << GPIO_OSPEEDER_OSPEEDR4_Pos)

#define	GPIO_OSPEEDER_OSPEEDR5_Pos (10U)

#define	GPIO_OSPEEDER_OSPEEDR5_Msk (0x3UL << GPIO_OSPEEDER_OSPEEDR5_Pos)

#define	GPIO_OSPEEDER_OSPEEDR5 GPIO_OSPEEDER_OSPEEDR5_Msk

#define	GPIO_OSPEEDER_OSPEEDR5_0 (0x1UL << GPIO_OSPEEDER_OSPEEDR5_Pos)

#define	GPIO_OSPEEDER_OSPEEDR5_1 (0x2UL << GPIO_OSPEEDER_OSPEEDR5_Pos)

#define	GPIO_OSPEEDER_OSPEEDR6_Pos (12U)

#define	GPIO_OSPEEDER_OSPEEDR6_Msk (0x3UL << GPIO_OSPEEDER_OSPEEDR6_Pos)

#define	GPIO_OSPEEDER_OSPEEDR6 GPIO_OSPEEDER_OSPEEDR6_Msk

#define	GPIO_OSPEEDER_OSPEEDR6_0 (0x1UL << GPIO_OSPEEDER_OSPEEDR6_Pos)

#define	GPIO_OSPEEDER_OSPEEDR6_1 (0x2UL << GPIO_OSPEEDER_OSPEEDR6_Pos)

#define	GPIO_OSPEEDER_OSPEEDR7_Pos (14U)

#define	GPIO_OSPEEDER_OSPEEDR7_Msk (0x3UL << GPIO_OSPEEDER_OSPEEDR7_Pos)

#define	GPIO_OSPEEDER_OSPEEDR7 GPIO_OSPEEDER_OSPEEDR7_Msk

#define	GPIO_OSPEEDER_OSPEEDR7_0 (0x1UL << GPIO_OSPEEDER_OSPEEDR7_Pos)

#define	GPIO_OSPEEDER_OSPEEDR7_1 (0x2UL << GPIO_OSPEEDER_OSPEEDR7_Pos)

#define	GPIO_OSPEEDER_OSPEEDR8_Pos (16U)

#define	GPIO_OSPEEDER_OSPEEDR8_Msk (0x3UL << GPIO_OSPEEDER_OSPEEDR8_Pos)

#define	GPIO_OSPEEDER_OSPEEDR8 GPIO_OSPEEDER_OSPEEDR8_Msk

#define	GPIO_OSPEEDER_OSPEEDR8_0 (0x1UL << GPIO_OSPEEDER_OSPEEDR8_Pos)

#define	GPIO_OSPEEDER_OSPEEDR8_1 (0x2UL << GPIO_OSPEEDER_OSPEEDR8_Pos)

#define	GPIO_OSPEEDER_OSPEEDR9_Pos (18U)

#define	GPIO_OSPEEDER_OSPEEDR9_Msk (0x3UL << GPIO_OSPEEDER_OSPEEDR9_Pos)

#define	GPIO_OSPEEDER_OSPEEDR9 GPIO_OSPEEDER_OSPEEDR9_Msk

#define	GPIO_OSPEEDER_OSPEEDR9_0 (0x1UL << GPIO_OSPEEDER_OSPEEDR9_Pos)

#define	GPIO_OSPEEDER_OSPEEDR9_1 (0x2UL << GPIO_OSPEEDER_OSPEEDR9_Pos)

#define	GPIO_OSPEEDER_OSPEEDR10_Pos (20U)

#define	GPIO_OSPEEDER_OSPEEDR10_Msk (0x3UL << GPIO_OSPEEDER_OSPEEDR10_Pos)

#define	GPIO_OSPEEDER_OSPEEDR10 GPIO_OSPEEDER_OSPEEDR10_Msk

#define	GPIO_OSPEEDER_OSPEEDR10_0 (0x1UL << GPIO_OSPEEDER_OSPEEDR10_Pos)

#define	GPIO_OSPEEDER_OSPEEDR10_1 (0x2UL << GPIO_OSPEEDER_OSPEEDR10_Pos)

#define	GPIO_OSPEEDER_OSPEEDR11_Pos (22U)

#define	GPIO_OSPEEDER_OSPEEDR11_Msk (0x3UL << GPIO_OSPEEDER_OSPEEDR11_Pos)

#define	GPIO_OSPEEDER_OSPEEDR11 GPIO_OSPEEDER_OSPEEDR11_Msk

#define	GPIO_OSPEEDER_OSPEEDR11_0 (0x1UL << GPIO_OSPEEDER_OSPEEDR11_Pos)

#define	GPIO_OSPEEDER_OSPEEDR11_1 (0x2UL << GPIO_OSPEEDER_OSPEEDR11_Pos)

#define	GPIO_OSPEEDER_OSPEEDR12_Pos (24U)

#define	GPIO_OSPEEDER_OSPEEDR12_Msk (0x3UL << GPIO_OSPEEDER_OSPEEDR12_Pos)

#define	GPIO_OSPEEDER_OSPEEDR12 GPIO_OSPEEDER_OSPEEDR12_Msk

#define	GPIO_OSPEEDER_OSPEEDR12_0 (0x1UL << GPIO_OSPEEDER_OSPEEDR12_Pos)

#define	GPIO_OSPEEDER_OSPEEDR12_1 (0x2UL << GPIO_OSPEEDER_OSPEEDR12_Pos)

#define	GPIO_OSPEEDER_OSPEEDR13_Pos (26U)

#define	GPIO_OSPEEDER_OSPEEDR13_Msk (0x3UL << GPIO_OSPEEDER_OSPEEDR13_Pos)

#define	GPIO_OSPEEDER_OSPEEDR13 GPIO_OSPEEDER_OSPEEDR13_Msk

#define	GPIO_OSPEEDER_OSPEEDR13_0 (0x1UL << GPIO_OSPEEDER_OSPEEDR13_Pos)

#define	GPIO_OSPEEDER_OSPEEDR13_1 (0x2UL << GPIO_OSPEEDER_OSPEEDR13_Pos)

#define	GPIO_OSPEEDER_OSPEEDR14_Pos (28U)

#define	GPIO_OSPEEDER_OSPEEDR14_Msk (0x3UL << GPIO_OSPEEDER_OSPEEDR14_Pos)

#define	GPIO_OSPEEDER_OSPEEDR14 GPIO_OSPEEDER_OSPEEDR14_Msk

#define	GPIO_OSPEEDER_OSPEEDR14_0 (0x1UL << GPIO_OSPEEDER_OSPEEDR14_Pos)

#define	GPIO_OSPEEDER_OSPEEDR14_1 (0x2UL << GPIO_OSPEEDER_OSPEEDR14_Pos)

#define	GPIO_OSPEEDER_OSPEEDR15_Pos (30U)

#define	GPIO_OSPEEDER_OSPEEDR15_Msk (0x3UL << GPIO_OSPEEDER_OSPEEDR15_Pos)

#define	GPIO_OSPEEDER_OSPEEDR15 GPIO_OSPEEDER_OSPEEDR15_Msk

#define	GPIO_OSPEEDER_OSPEEDR15_0 (0x1UL << GPIO_OSPEEDER_OSPEEDR15_Pos)

#define	GPIO_OSPEEDER_OSPEEDR15_1 (0x2UL << GPIO_OSPEEDER_OSPEEDR15_Pos)

#define	GPIO_PUPDR_PUPDR0_Pos (0U)

#define	GPIO_PUPDR_PUPDR0_Msk (0x3UL << GPIO_PUPDR_PUPDR0_Pos)

#define	GPIO_PUPDR_PUPDR0 GPIO_PUPDR_PUPDR0_Msk

#define	GPIO_PUPDR_PUPDR0_0 (0x1UL << GPIO_PUPDR_PUPDR0_Pos)

#define	GPIO_PUPDR_PUPDR0_1 (0x2UL << GPIO_PUPDR_PUPDR0_Pos)

#define	GPIO_PUPDR_PUPDR1_Pos (2U)

#define	GPIO_PUPDR_PUPDR1_Msk (0x3UL << GPIO_PUPDR_PUPDR1_Pos)

#define	GPIO_PUPDR_PUPDR1 GPIO_PUPDR_PUPDR1_Msk

#define	GPIO_PUPDR_PUPDR1_0 (0x1UL << GPIO_PUPDR_PUPDR1_Pos)

#define	GPIO_PUPDR_PUPDR1_1 (0x2UL << GPIO_PUPDR_PUPDR1_Pos)

#define	GPIO_PUPDR_PUPDR2_Pos (4U)

#define	GPIO_PUPDR_PUPDR2_Msk (0x3UL << GPIO_PUPDR_PUPDR2_Pos)

#define	GPIO_PUPDR_PUPDR2 GPIO_PUPDR_PUPDR2_Msk

#define	GPIO_PUPDR_PUPDR2_0 (0x1UL << GPIO_PUPDR_PUPDR2_Pos)

#define	GPIO_PUPDR_PUPDR2_1 (0x2UL << GPIO_PUPDR_PUPDR2_Pos)

#define	GPIO_PUPDR_PUPDR3_Pos (6U)

#define	GPIO_PUPDR_PUPDR3_Msk (0x3UL << GPIO_PUPDR_PUPDR3_Pos)

#define	GPIO_PUPDR_PUPDR3 GPIO_PUPDR_PUPDR3_Msk

#define	GPIO_PUPDR_PUPDR3_0 (0x1UL << GPIO_PUPDR_PUPDR3_Pos)

#define	GPIO_PUPDR_PUPDR3_1 (0x2UL << GPIO_PUPDR_PUPDR3_Pos)

#define	GPIO_PUPDR_PUPDR4_Pos (8U)

#define	GPIO_PUPDR_PUPDR4_Msk (0x3UL << GPIO_PUPDR_PUPDR4_Pos)

#define	GPIO_PUPDR_PUPDR4 GPIO_PUPDR_PUPDR4_Msk

#define	GPIO_PUPDR_PUPDR4_0 (0x1UL << GPIO_PUPDR_PUPDR4_Pos)

#define	GPIO_PUPDR_PUPDR4_1 (0x2UL << GPIO_PUPDR_PUPDR4_Pos)

#define	GPIO_PUPDR_PUPDR5_Pos (10U)

#define	GPIO_PUPDR_PUPDR5_Msk (0x3UL << GPIO_PUPDR_PUPDR5_Pos)

#define	GPIO_PUPDR_PUPDR5 GPIO_PUPDR_PUPDR5_Msk

#define	GPIO_PUPDR_PUPDR5_0 (0x1UL << GPIO_PUPDR_PUPDR5_Pos)

#define	GPIO_PUPDR_PUPDR5_1 (0x2UL << GPIO_PUPDR_PUPDR5_Pos)

#define	GPIO_PUPDR_PUPDR6_Pos (12U)

#define	GPIO_PUPDR_PUPDR6_Msk (0x3UL << GPIO_PUPDR_PUPDR6_Pos)

#define	GPIO_PUPDR_PUPDR6 GPIO_PUPDR_PUPDR6_Msk

#define	GPIO_PUPDR_PUPDR6_0 (0x1UL << GPIO_PUPDR_PUPDR6_Pos)

#define	GPIO_PUPDR_PUPDR6_1 (0x2UL << GPIO_PUPDR_PUPDR6_Pos)

#define	GPIO_PUPDR_PUPDR7_Pos (14U)

#define	GPIO_PUPDR_PUPDR7_Msk (0x3UL << GPIO_PUPDR_PUPDR7_Pos)

#define	GPIO_PUPDR_PUPDR7 GPIO_PUPDR_PUPDR7_Msk

#define	GPIO_PUPDR_PUPDR7_0 (0x1UL << GPIO_PUPDR_PUPDR7_Pos)

#define	GPIO_PUPDR_PUPDR7_1 (0x2UL << GPIO_PUPDR_PUPDR7_Pos)

#define	GPIO_PUPDR_PUPDR8_Pos (16U)

#define	GPIO_PUPDR_PUPDR8_Msk (0x3UL << GPIO_PUPDR_PUPDR8_Pos)

#define	GPIO_PUPDR_PUPDR8 GPIO_PUPDR_PUPDR8_Msk

#define	GPIO_PUPDR_PUPDR8_0 (0x1UL << GPIO_PUPDR_PUPDR8_Pos)

#define	GPIO_PUPDR_PUPDR8_1 (0x2UL << GPIO_PUPDR_PUPDR8_Pos)

#define	GPIO_PUPDR_PUPDR9_Pos (18U)

#define	GPIO_PUPDR_PUPDR9_Msk (0x3UL << GPIO_PUPDR_PUPDR9_Pos)

#define	GPIO_PUPDR_PUPDR9 GPIO_PUPDR_PUPDR9_Msk

#define	GPIO_PUPDR_PUPDR9_0 (0x1UL << GPIO_PUPDR_PUPDR9_Pos)

#define	GPIO_PUPDR_PUPDR9_1 (0x2UL << GPIO_PUPDR_PUPDR9_Pos)

#define	GPIO_PUPDR_PUPDR10_Pos (20U)

#define	GPIO_PUPDR_PUPDR10_Msk (0x3UL << GPIO_PUPDR_PUPDR10_Pos)

#define	GPIO_PUPDR_PUPDR10 GPIO_PUPDR_PUPDR10_Msk

#define	GPIO_PUPDR_PUPDR10_0 (0x1UL << GPIO_PUPDR_PUPDR10_Pos)

#define	GPIO_PUPDR_PUPDR10_1 (0x2UL << GPIO_PUPDR_PUPDR10_Pos)

#define	GPIO_PUPDR_PUPDR11_Pos (22U)

#define	GPIO_PUPDR_PUPDR11_Msk (0x3UL << GPIO_PUPDR_PUPDR11_Pos)

#define	GPIO_PUPDR_PUPDR11 GPIO_PUPDR_PUPDR11_Msk

#define	GPIO_PUPDR_PUPDR11_0 (0x1UL << GPIO_PUPDR_PUPDR11_Pos)

#define	GPIO_PUPDR_PUPDR11_1 (0x2UL << GPIO_PUPDR_PUPDR11_Pos)

#define	GPIO_PUPDR_PUPDR12_Pos (24U)

#define	GPIO_PUPDR_PUPDR12_Msk (0x3UL << GPIO_PUPDR_PUPDR12_Pos)

#define	GPIO_PUPDR_PUPDR12 GPIO_PUPDR_PUPDR12_Msk

#define	GPIO_PUPDR_PUPDR12_0 (0x1UL << GPIO_PUPDR_PUPDR12_Pos)

#define	GPIO_PUPDR_PUPDR12_1 (0x2UL << GPIO_PUPDR_PUPDR12_Pos)

#define	GPIO_PUPDR_PUPDR13_Pos (26U)

#define	GPIO_PUPDR_PUPDR13_Msk (0x3UL << GPIO_PUPDR_PUPDR13_Pos)

#define	GPIO_PUPDR_PUPDR13 GPIO_PUPDR_PUPDR13_Msk

#define	GPIO_PUPDR_PUPDR13_0 (0x1UL << GPIO_PUPDR_PUPDR13_Pos)

#define	GPIO_PUPDR_PUPDR13_1 (0x2UL << GPIO_PUPDR_PUPDR13_Pos)

#define	GPIO_PUPDR_PUPDR14_Pos (28U)

#define	GPIO_PUPDR_PUPDR14_Msk (0x3UL << GPIO_PUPDR_PUPDR14_Pos)

#define	GPIO_PUPDR_PUPDR14 GPIO_PUPDR_PUPDR14_Msk

#define	GPIO_PUPDR_PUPDR14_0 (0x1UL << GPIO_PUPDR_PUPDR14_Pos)

#define	GPIO_PUPDR_PUPDR14_1 (0x2UL << GPIO_PUPDR_PUPDR14_Pos)

#define	GPIO_PUPDR_PUPDR15_Pos (30U)

#define	GPIO_PUPDR_PUPDR15_Msk (0x3UL << GPIO_PUPDR_PUPDR15_Pos)

#define	GPIO_PUPDR_PUPDR15 GPIO_PUPDR_PUPDR15_Msk

#define	GPIO_PUPDR_PUPDR15_0 (0x1UL << GPIO_PUPDR_PUPDR15_Pos)

#define	GPIO_PUPDR_PUPDR15_1 (0x2UL << GPIO_PUPDR_PUPDR15_Pos)

#define	GPIO_IDR_0 (0x00000001U)

#define	GPIO_IDR_1 (0x00000002U)

#define	GPIO_IDR_2 (0x00000004U)

#define	GPIO_IDR_3 (0x00000008U)

#define	GPIO_IDR_4 (0x00000010U)

#define	GPIO_IDR_5 (0x00000020U)

#define	GPIO_IDR_6 (0x00000040U)

#define	GPIO_IDR_7 (0x00000080U)

#define	GPIO_IDR_8 (0x00000100U)

#define	GPIO_IDR_9 (0x00000200U)

#define	GPIO_IDR_10 (0x00000400U)

#define	GPIO_IDR_11 (0x00000800U)

#define	GPIO_IDR_12 (0x00001000U)

#define	GPIO_IDR_13 (0x00002000U)

#define	GPIO_IDR_14 (0x00004000U)

#define	GPIO_IDR_15 (0x00008000U)

#define	GPIO_ODR_0 (0x00000001U)

#define	GPIO_ODR_1 (0x00000002U)

#define	GPIO_ODR_2 (0x00000004U)

#define	GPIO_ODR_3 (0x00000008U)

#define	GPIO_ODR_4 (0x00000010U)

#define	GPIO_ODR_5 (0x00000020U)

#define	GPIO_ODR_6 (0x00000040U)

#define	GPIO_ODR_7 (0x00000080U)

#define	GPIO_ODR_8 (0x00000100U)

#define	GPIO_ODR_9 (0x00000200U)

#define	GPIO_ODR_10 (0x00000400U)

#define	GPIO_ODR_11 (0x00000800U)

#define	GPIO_ODR_12 (0x00001000U)

#define	GPIO_ODR_13 (0x00002000U)

#define	GPIO_ODR_14 (0x00004000U)

#define	GPIO_ODR_15 (0x00008000U)

#define	GPIO_BSRR_BS_0 (0x00000001U)

#define	GPIO_BSRR_BS_1 (0x00000002U)

#define	GPIO_BSRR_BS_2 (0x00000004U)

#define	GPIO_BSRR_BS_3 (0x00000008U)

#define	GPIO_BSRR_BS_4 (0x00000010U)

#define	GPIO_BSRR_BS_5 (0x00000020U)

#define	GPIO_BSRR_BS_6 (0x00000040U)

#define	GPIO_BSRR_BS_7 (0x00000080U)

#define	GPIO_BSRR_BS_8 (0x00000100U)

#define	GPIO_BSRR_BS_9 (0x00000200U)

#define	GPIO_BSRR_BS_10 (0x00000400U)

#define	GPIO_BSRR_BS_11 (0x00000800U)

#define	GPIO_BSRR_BS_12 (0x00001000U)

#define	GPIO_BSRR_BS_13 (0x00002000U)

#define	GPIO_BSRR_BS_14 (0x00004000U)

#define	GPIO_BSRR_BS_15 (0x00008000U)

#define	GPIO_BSRR_BR_0 (0x00010000U)

#define	GPIO_BSRR_BR_1 (0x00020000U)

#define	GPIO_BSRR_BR_2 (0x00040000U)

#define	GPIO_BSRR_BR_3 (0x00080000U)

#define	GPIO_BSRR_BR_4 (0x00100000U)

#define	GPIO_BSRR_BR_5 (0x00200000U)

#define	GPIO_BSRR_BR_6 (0x00400000U)

#define	GPIO_BSRR_BR_7 (0x00800000U)

#define	GPIO_BSRR_BR_8 (0x01000000U)

#define	GPIO_BSRR_BR_9 (0x02000000U)

#define	GPIO_BSRR_BR_10 (0x04000000U)

#define	GPIO_BSRR_BR_11 (0x08000000U)

#define	GPIO_BSRR_BR_12 (0x10000000U)

#define	GPIO_BSRR_BR_13 (0x20000000U)

#define	GPIO_BSRR_BR_14 (0x40000000U)

#define	GPIO_BSRR_BR_15 (0x80000000U)

#define	GPIO_LCKR_LCK0_Pos (0U)

#define	GPIO_LCKR_LCK0_Msk (0x1UL << GPIO_LCKR_LCK0_Pos)

#define	GPIO_LCKR_LCK0 GPIO_LCKR_LCK0_Msk

#define	GPIO_LCKR_LCK1_Pos (1U)

#define	GPIO_LCKR_LCK1_Msk (0x1UL << GPIO_LCKR_LCK1_Pos)

#define	GPIO_LCKR_LCK1 GPIO_LCKR_LCK1_Msk

#define	GPIO_LCKR_LCK2_Pos (2U)

#define	GPIO_LCKR_LCK2_Msk (0x1UL << GPIO_LCKR_LCK2_Pos)

#define	GPIO_LCKR_LCK2 GPIO_LCKR_LCK2_Msk

#define	GPIO_LCKR_LCK3_Pos (3U)

#define	GPIO_LCKR_LCK3_Msk (0x1UL << GPIO_LCKR_LCK3_Pos)

#define	GPIO_LCKR_LCK3 GPIO_LCKR_LCK3_Msk

#define	GPIO_LCKR_LCK4_Pos (4U)

#define	GPIO_LCKR_LCK4_Msk (0x1UL << GPIO_LCKR_LCK4_Pos)

#define	GPIO_LCKR_LCK4 GPIO_LCKR_LCK4_Msk

#define	GPIO_LCKR_LCK5_Pos (5U)

#define	GPIO_LCKR_LCK5_Msk (0x1UL << GPIO_LCKR_LCK5_Pos)

#define	GPIO_LCKR_LCK5 GPIO_LCKR_LCK5_Msk

#define	GPIO_LCKR_LCK6_Pos (6U)

#define	GPIO_LCKR_LCK6_Msk (0x1UL << GPIO_LCKR_LCK6_Pos)

#define	GPIO_LCKR_LCK6 GPIO_LCKR_LCK6_Msk

#define	GPIO_LCKR_LCK7_Pos (7U)

#define	GPIO_LCKR_LCK7_Msk (0x1UL << GPIO_LCKR_LCK7_Pos)

#define	GPIO_LCKR_LCK7 GPIO_LCKR_LCK7_Msk

#define	GPIO_LCKR_LCK8_Pos (8U)

#define	GPIO_LCKR_LCK8_Msk (0x1UL << GPIO_LCKR_LCK8_Pos)

#define	GPIO_LCKR_LCK8 GPIO_LCKR_LCK8_Msk

#define	GPIO_LCKR_LCK9_Pos (9U)

#define	GPIO_LCKR_LCK9_Msk (0x1UL << GPIO_LCKR_LCK9_Pos)

#define	GPIO_LCKR_LCK9 GPIO_LCKR_LCK9_Msk

#define	GPIO_LCKR_LCK10_Pos (10U)

#define	GPIO_LCKR_LCK10_Msk (0x1UL << GPIO_LCKR_LCK10_Pos)

#define	GPIO_LCKR_LCK10 GPIO_LCKR_LCK10_Msk

#define	GPIO_LCKR_LCK11_Pos (11U)

#define	GPIO_LCKR_LCK11_Msk (0x1UL << GPIO_LCKR_LCK11_Pos)

#define	GPIO_LCKR_LCK11 GPIO_LCKR_LCK11_Msk

#define	GPIO_LCKR_LCK12_Pos (12U)

#define	GPIO_LCKR_LCK12_Msk (0x1UL << GPIO_LCKR_LCK12_Pos)

#define	GPIO_LCKR_LCK12 GPIO_LCKR_LCK12_Msk

#define	GPIO_LCKR_LCK13_Pos (13U)

#define	GPIO_LCKR_LCK13_Msk (0x1UL << GPIO_LCKR_LCK13_Pos)

#define	GPIO_LCKR_LCK13 GPIO_LCKR_LCK13_Msk

#define	GPIO_LCKR_LCK14_Pos (14U)

#define	GPIO_LCKR_LCK14_Msk (0x1UL << GPIO_LCKR_LCK14_Pos)

#define	GPIO_LCKR_LCK14 GPIO_LCKR_LCK14_Msk

#define	GPIO_LCKR_LCK15_Pos (15U)

#define	GPIO_LCKR_LCK15_Msk (0x1UL << GPIO_LCKR_LCK15_Pos)

#define	GPIO_LCKR_LCK15 GPIO_LCKR_LCK15_Msk

#define	GPIO_LCKR_LCKK_Pos (16U)

#define	GPIO_LCKR_LCKK_Msk (0x1UL << GPIO_LCKR_LCKK_Pos)

#define	GPIO_LCKR_LCKK GPIO_LCKR_LCKK_Msk

#define	GPIO_AFRL_AFRL0_Pos (0U)

#define	GPIO_AFRL_AFRL0_Msk (0xFUL << GPIO_AFRL_AFRL0_Pos)

#define	GPIO_AFRL_AFRL0 GPIO_AFRL_AFRL0_Msk

#define	GPIO_AFRL_AFRL1_Pos (4U)

#define	GPIO_AFRL_AFRL1_Msk (0xFUL << GPIO_AFRL_AFRL1_Pos)

#define	GPIO_AFRL_AFRL1 GPIO_AFRL_AFRL1_Msk

#define	GPIO_AFRL_AFRL2_Pos (8U)

#define	GPIO_AFRL_AFRL2_Msk (0xFUL << GPIO_AFRL_AFRL2_Pos)

#define	GPIO_AFRL_AFRL2 GPIO_AFRL_AFRL2_Msk

#define	GPIO_AFRL_AFRL3_Pos (12U)

#define	GPIO_AFRL_AFRL3_Msk (0xFUL << GPIO_AFRL_AFRL3_Pos)

#define	GPIO_AFRL_AFRL3 GPIO_AFRL_AFRL3_Msk

#define	GPIO_AFRL_AFRL4_Pos (16U)

#define	GPIO_AFRL_AFRL4_Msk (0xFUL << GPIO_AFRL_AFRL4_Pos)

#define	GPIO_AFRL_AFRL4 GPIO_AFRL_AFRL4_Msk

#define	GPIO_AFRL_AFRL5_Pos (20U)

#define	GPIO_AFRL_AFRL5_Msk (0xFUL << GPIO_AFRL_AFRL5_Pos)

#define	GPIO_AFRL_AFRL5 GPIO_AFRL_AFRL5_Msk

#define	GPIO_AFRL_AFRL6_Pos (24U)

#define	GPIO_AFRL_AFRL6_Msk (0xFUL << GPIO_AFRL_AFRL6_Pos)

#define	GPIO_AFRL_AFRL6 GPIO_AFRL_AFRL6_Msk

#define	GPIO_AFRL_AFRL7_Pos (28U)

#define	GPIO_AFRL_AFRL7_Msk (0xFUL << GPIO_AFRL_AFRL7_Pos)

#define	GPIO_AFRL_AFRL7 GPIO_AFRL_AFRL7_Msk

#define	GPIO_AFRH_AFRH0_Pos (0U)

#define	GPIO_AFRH_AFRH0_Msk (0xFUL << GPIO_AFRH_AFRH0_Pos)

#define	GPIO_AFRH_AFRH0 GPIO_AFRH_AFRH0_Msk

#define	GPIO_AFRH_AFRH1_Pos (4U)

#define	GPIO_AFRH_AFRH1_Msk (0xFUL << GPIO_AFRH_AFRH1_Pos)

#define	GPIO_AFRH_AFRH1 GPIO_AFRH_AFRH1_Msk

#define	GPIO_AFRH_AFRH2_Pos (8U)

#define	GPIO_AFRH_AFRH2_Msk (0xFUL << GPIO_AFRH_AFRH2_Pos)

#define	GPIO_AFRH_AFRH2 GPIO_AFRH_AFRH2_Msk

#define	GPIO_AFRH_AFRH3_Pos (12U)

#define	GPIO_AFRH_AFRH3_Msk (0xFUL << GPIO_AFRH_AFRH3_Pos)

#define	GPIO_AFRH_AFRH3 GPIO_AFRH_AFRH3_Msk

#define	GPIO_AFRH_AFRH4_Pos (16U)

#define	GPIO_AFRH_AFRH4_Msk (0xFUL << GPIO_AFRH_AFRH4_Pos)

#define	GPIO_AFRH_AFRH4 GPIO_AFRH_AFRH4_Msk

#define	GPIO_AFRH_AFRH5_Pos (20U)

#define	GPIO_AFRH_AFRH5_Msk (0xFUL << GPIO_AFRH_AFRH5_Pos)

#define	GPIO_AFRH_AFRH5 GPIO_AFRH_AFRH5_Msk

#define	GPIO_AFRH_AFRH6_Pos (24U)

#define	GPIO_AFRH_AFRH6_Msk (0xFUL << GPIO_AFRH_AFRH6_Pos)

#define	GPIO_AFRH_AFRH6 GPIO_AFRH_AFRH6_Msk

#define	GPIO_AFRH_AFRH7_Pos (28U)

#define	GPIO_AFRH_AFRH7_Msk (0xFUL << GPIO_AFRH_AFRH7_Pos)

#define	GPIO_AFRH_AFRH7 GPIO_AFRH_AFRH7_Msk

#define	GPIO_BRR_BR_0 (0x00000001U)

#define	GPIO_BRR_BR_1 (0x00000002U)

#define	GPIO_BRR_BR_2 (0x00000004U)

#define	GPIO_BRR_BR_3 (0x00000008U)

#define	GPIO_BRR_BR_4 (0x00000010U)

#define	GPIO_BRR_BR_5 (0x00000020U)

#define	GPIO_BRR_BR_6 (0x00000040U)

#define	GPIO_BRR_BR_7 (0x00000080U)

#define	GPIO_BRR_BR_8 (0x00000100U)

#define	GPIO_BRR_BR_9 (0x00000200U)

#define	GPIO_BRR_BR_10 (0x00000400U)

#define	GPIO_BRR_BR_11 (0x00000800U)

#define	GPIO_BRR_BR_12 (0x00001000U)

#define	GPIO_BRR_BR_13 (0x00002000U)

#define	GPIO_BRR_BR_14 (0x00004000U)

#define	GPIO_BRR_BR_15 (0x00008000U)

#define	I2C_CR1_PE_Pos (0U)

#define	I2C_CR1_PE_Msk (0x1UL << I2C_CR1_PE_Pos)

#define	I2C_CR1_PE I2C_CR1_PE_Msk

#define	I2C_CR1_TXIE_Pos (1U)

#define	I2C_CR1_TXIE_Msk (0x1UL << I2C_CR1_TXIE_Pos)

#define	I2C_CR1_TXIE I2C_CR1_TXIE_Msk

#define	I2C_CR1_RXIE_Pos (2U)

#define	I2C_CR1_RXIE_Msk (0x1UL << I2C_CR1_RXIE_Pos)

#define	I2C_CR1_RXIE I2C_CR1_RXIE_Msk

#define	I2C_CR1_ADDRIE_Pos (3U)

#define	I2C_CR1_ADDRIE_Msk (0x1UL << I2C_CR1_ADDRIE_Pos)

#define	I2C_CR1_ADDRIE I2C_CR1_ADDRIE_Msk

#define	I2C_CR1_NACKIE_Pos (4U)

#define	I2C_CR1_NACKIE_Msk (0x1UL << I2C_CR1_NACKIE_Pos)

#define	I2C_CR1_NACKIE I2C_CR1_NACKIE_Msk

#define	I2C_CR1_STOPIE_Pos (5U)

#define	I2C_CR1_STOPIE_Msk (0x1UL << I2C_CR1_STOPIE_Pos)

#define	I2C_CR1_STOPIE I2C_CR1_STOPIE_Msk

#define	I2C_CR1_TCIE_Pos (6U)

#define	I2C_CR1_TCIE_Msk (0x1UL << I2C_CR1_TCIE_Pos)

#define	I2C_CR1_TCIE I2C_CR1_TCIE_Msk

#define	I2C_CR1_ERRIE_Pos (7U)

#define	I2C_CR1_ERRIE_Msk (0x1UL << I2C_CR1_ERRIE_Pos)

#define	I2C_CR1_ERRIE I2C_CR1_ERRIE_Msk

#define	I2C_CR1_DNF_Pos (8U)

#define	I2C_CR1_DNF_Msk (0xFUL << I2C_CR1_DNF_Pos)

#define	I2C_CR1_DNF I2C_CR1_DNF_Msk

#define	I2C_CR1_ANFOFF_Pos (12U)

#define	I2C_CR1_ANFOFF_Msk (0x1UL << I2C_CR1_ANFOFF_Pos)

#define	I2C_CR1_ANFOFF I2C_CR1_ANFOFF_Msk

#define	I2C_CR1_SWRST_Pos (13U)

#define	I2C_CR1_SWRST_Msk (0x1UL << I2C_CR1_SWRST_Pos)

#define	I2C_CR1_SWRST I2C_CR1_SWRST_Msk

#define	I2C_CR1_TXDMAEN_Pos (14U)

#define	I2C_CR1_TXDMAEN_Msk (0x1UL << I2C_CR1_TXDMAEN_Pos)

#define	I2C_CR1_TXDMAEN I2C_CR1_TXDMAEN_Msk

#define	I2C_CR1_RXDMAEN_Pos (15U)

#define	I2C_CR1_RXDMAEN_Msk (0x1UL << I2C_CR1_RXDMAEN_Pos)

#define	I2C_CR1_RXDMAEN I2C_CR1_RXDMAEN_Msk

#define	I2C_CR1_SBC_Pos (16U)

#define	I2C_CR1_SBC_Msk (0x1UL << I2C_CR1_SBC_Pos)

#define	I2C_CR1_SBC I2C_CR1_SBC_Msk

#define	I2C_CR1_NOSTRETCH_Pos (17U)

#define	I2C_CR1_NOSTRETCH_Msk (0x1UL << I2C_CR1_NOSTRETCH_Pos)

#define	I2C_CR1_NOSTRETCH I2C_CR1_NOSTRETCH_Msk

#define	I2C_CR1_WUPEN_Pos (18U)

#define	I2C_CR1_WUPEN_Msk (0x1UL << I2C_CR1_WUPEN_Pos)

#define	I2C_CR1_WUPEN I2C_CR1_WUPEN_Msk

#define	I2C_CR1_GCEN_Pos (19U)

#define	I2C_CR1_GCEN_Msk (0x1UL << I2C_CR1_GCEN_Pos)

#define	I2C_CR1_GCEN I2C_CR1_GCEN_Msk

#define	I2C_CR1_SMBHEN_Pos (20U)

#define	I2C_CR1_SMBHEN_Msk (0x1UL << I2C_CR1_SMBHEN_Pos)

#define	I2C_CR1_SMBHEN I2C_CR1_SMBHEN_Msk

#define	I2C_CR1_SMBDEN_Pos (21U)

#define	I2C_CR1_SMBDEN_Msk (0x1UL << I2C_CR1_SMBDEN_Pos)

#define	I2C_CR1_SMBDEN I2C_CR1_SMBDEN_Msk

#define	I2C_CR1_ALERTEN_Pos (22U)

#define	I2C_CR1_ALERTEN_Msk (0x1UL << I2C_CR1_ALERTEN_Pos)

#define	I2C_CR1_ALERTEN I2C_CR1_ALERTEN_Msk

#define	I2C_CR1_PECEN_Pos (23U)

#define	I2C_CR1_PECEN_Msk (0x1UL << I2C_CR1_PECEN_Pos)

#define	I2C_CR1_PECEN I2C_CR1_PECEN_Msk

#define	I2C_CR1_DFN I2C_CR1_DNF

#define	I2C_CR2_SADD_Pos (0U)

#define	I2C_CR2_SADD_Msk (0x3FFUL << I2C_CR2_SADD_Pos)

#define	I2C_CR2_SADD I2C_CR2_SADD_Msk

#define	I2C_CR2_RD_WRN_Pos (10U)

#define	I2C_CR2_RD_WRN_Msk (0x1UL << I2C_CR2_RD_WRN_Pos)

#define	I2C_CR2_RD_WRN I2C_CR2_RD_WRN_Msk

#define	I2C_CR2_ADD10_Pos (11U)

#define	I2C_CR2_ADD10_Msk (0x1UL << I2C_CR2_ADD10_Pos)

#define	I2C_CR2_ADD10 I2C_CR2_ADD10_Msk

#define	I2C_CR2_HEAD10R_Pos (12U)

#define	I2C_CR2_HEAD10R_Msk (0x1UL << I2C_CR2_HEAD10R_Pos)

#define	I2C_CR2_HEAD10R I2C_CR2_HEAD10R_Msk

#define	I2C_CR2_START_Pos (13U)

#define	I2C_CR2_START_Msk (0x1UL << I2C_CR2_START_Pos)

#define	I2C_CR2_START I2C_CR2_START_Msk

#define	I2C_CR2_STOP_Pos (14U)

#define	I2C_CR2_STOP_Msk (0x1UL << I2C_CR2_STOP_Pos)

#define	I2C_CR2_STOP I2C_CR2_STOP_Msk

#define	I2C_CR2_NACK_Pos (15U)

#define	I2C_CR2_NACK_Msk (0x1UL << I2C_CR2_NACK_Pos)

#define	I2C_CR2_NACK I2C_CR2_NACK_Msk

#define	I2C_CR2_NBYTES_Pos (16U)

#define	I2C_CR2_NBYTES_Msk (0xFFUL << I2C_CR2_NBYTES_Pos)

#define	I2C_CR2_NBYTES I2C_CR2_NBYTES_Msk

#define	I2C_CR2_RELOAD_Pos (24U)

#define	I2C_CR2_RELOAD_Msk (0x1UL << I2C_CR2_RELOAD_Pos)

#define	I2C_CR2_RELOAD I2C_CR2_RELOAD_Msk

#define	I2C_CR2_AUTOEND_Pos (25U)

#define	I2C_CR2_AUTOEND_Msk (0x1UL << I2C_CR2_AUTOEND_Pos)

#define	I2C_CR2_AUTOEND I2C_CR2_AUTOEND_Msk

#define	I2C_CR2_PECBYTE_Pos (26U)

#define	I2C_CR2_PECBYTE_Msk (0x1UL << I2C_CR2_PECBYTE_Pos)

#define	I2C_CR2_PECBYTE I2C_CR2_PECBYTE_Msk

#define	I2C_OAR1_OA1_Pos (0U)

#define	I2C_OAR1_OA1_Msk (0x3FFUL << I2C_OAR1_OA1_Pos)

#define	I2C_OAR1_OA1 I2C_OAR1_OA1_Msk

#define	I2C_OAR1_OA1MODE_Pos (10U)

#define	I2C_OAR1_OA1MODE_Msk (0x1UL << I2C_OAR1_OA1MODE_Pos)

#define	I2C_OAR1_OA1MODE I2C_OAR1_OA1MODE_Msk

#define	I2C_OAR1_OA1EN_Pos (15U)

#define	I2C_OAR1_OA1EN_Msk (0x1UL << I2C_OAR1_OA1EN_Pos)

#define	I2C_OAR1_OA1EN I2C_OAR1_OA1EN_Msk

#define	I2C_OAR2_OA2_Pos (1U)

#define	I2C_OAR2_OA2_Msk (0x7FUL << I2C_OAR2_OA2_Pos)

#define	I2C_OAR2_OA2 I2C_OAR2_OA2_Msk

#define	I2C_OAR2_OA2MSK_Pos (8U)

#define	I2C_OAR2_OA2MSK_Msk (0x7UL << I2C_OAR2_OA2MSK_Pos)

#define	I2C_OAR2_OA2MSK I2C_OAR2_OA2MSK_Msk

#define	I2C_OAR2_OA2NOMASK (0x00000000U)

#define	I2C_OAR2_OA2MASK01_Pos (8U)

#define	I2C_OAR2_OA2MASK01_Msk (0x1UL << I2C_OAR2_OA2MASK01_Pos)

#define	I2C_OAR2_OA2MASK01 I2C_OAR2_OA2MASK01_Msk

#define	I2C_OAR2_OA2MASK02_Pos (9U)

#define	I2C_OAR2_OA2MASK02_Msk (0x1UL << I2C_OAR2_OA2MASK02_Pos)

#define	I2C_OAR2_OA2MASK02 I2C_OAR2_OA2MASK02_Msk

#define	I2C_OAR2_OA2MASK03_Pos (8U)

#define	I2C_OAR2_OA2MASK03_Msk (0x3UL << I2C_OAR2_OA2MASK03_Pos)

#define	I2C_OAR2_OA2MASK03 I2C_OAR2_OA2MASK03_Msk

#define	I2C_OAR2_OA2MASK04_Pos (10U)

#define	I2C_OAR2_OA2MASK04_Msk (0x1UL << I2C_OAR2_OA2MASK04_Pos)

#define	I2C_OAR2_OA2MASK04 I2C_OAR2_OA2MASK04_Msk

#define	I2C_OAR2_OA2MASK05_Pos (8U)

#define	I2C_OAR2_OA2MASK05_Msk (0x5UL << I2C_OAR2_OA2MASK05_Pos)

#define	I2C_OAR2_OA2MASK05 I2C_OAR2_OA2MASK05_Msk

#define	I2C_OAR2_OA2MASK06_Pos (9U)

#define	I2C_OAR2_OA2MASK06_Msk (0x3UL << I2C_OAR2_OA2MASK06_Pos)

#define	I2C_OAR2_OA2MASK06 I2C_OAR2_OA2MASK06_Msk

#define	I2C_OAR2_OA2MASK07_Pos (8U)

#define	I2C_OAR2_OA2MASK07_Msk (0x7UL << I2C_OAR2_OA2MASK07_Pos)

#define	I2C_OAR2_OA2MASK07 I2C_OAR2_OA2MASK07_Msk

#define	I2C_OAR2_OA2EN_Pos (15U)

#define	I2C_OAR2_OA2EN_Msk (0x1UL << I2C_OAR2_OA2EN_Pos)

#define	I2C_OAR2_OA2EN I2C_OAR2_OA2EN_Msk

#define	I2C_TIMINGR_SCLL_Pos (0U)

#define	I2C_TIMINGR_SCLL_Msk (0xFFUL << I2C_TIMINGR_SCLL_Pos)

#define	I2C_TIMINGR_SCLL I2C_TIMINGR_SCLL_Msk

#define	I2C_TIMINGR_SCLH_Pos (8U)

#define	I2C_TIMINGR_SCLH_Msk (0xFFUL << I2C_TIMINGR_SCLH_Pos)

#define	I2C_TIMINGR_SCLH I2C_TIMINGR_SCLH_Msk

#define	I2C_TIMINGR_SDADEL_Pos (16U)

#define	I2C_TIMINGR_SDADEL_Msk (0xFUL << I2C_TIMINGR_SDADEL_Pos)

#define	I2C_TIMINGR_SDADEL I2C_TIMINGR_SDADEL_Msk

#define	I2C_TIMINGR_SCLDEL_Pos (20U)

#define	I2C_TIMINGR_SCLDEL_Msk (0xFUL << I2C_TIMINGR_SCLDEL_Pos)

#define	I2C_TIMINGR_SCLDEL I2C_TIMINGR_SCLDEL_Msk

#define	I2C_TIMINGR_PRESC_Pos (28U)

#define	I2C_TIMINGR_PRESC_Msk (0xFUL << I2C_TIMINGR_PRESC_Pos)

#define	I2C_TIMINGR_PRESC I2C_TIMINGR_PRESC_Msk

#define	I2C_TIMEOUTR_TIMEOUTA_Pos (0U)

#define	I2C_TIMEOUTR_TIMEOUTA_Msk (0xFFFUL << I2C_TIMEOUTR_TIMEOUTA_Pos)

#define	I2C_TIMEOUTR_TIMEOUTA I2C_TIMEOUTR_TIMEOUTA_Msk

#define	I2C_TIMEOUTR_TIDLE_Pos (12U)

#define	I2C_TIMEOUTR_TIDLE_Msk (0x1UL << I2C_TIMEOUTR_TIDLE_Pos)

#define	I2C_TIMEOUTR_TIDLE I2C_TIMEOUTR_TIDLE_Msk

#define	I2C_TIMEOUTR_TIMOUTEN_Pos (15U)

#define	I2C_TIMEOUTR_TIMOUTEN_Msk (0x1UL << I2C_TIMEOUTR_TIMOUTEN_Pos)

#define	I2C_TIMEOUTR_TIMOUTEN I2C_TIMEOUTR_TIMOUTEN_Msk

#define	I2C_TIMEOUTR_TIMEOUTB_Pos (16U)

#define	I2C_TIMEOUTR_TIMEOUTB_Msk (0xFFFUL << I2C_TIMEOUTR_TIMEOUTB_Pos)

#define	I2C_TIMEOUTR_TIMEOUTB I2C_TIMEOUTR_TIMEOUTB_Msk

#define	I2C_TIMEOUTR_TEXTEN_Pos (31U)

#define	I2C_TIMEOUTR_TEXTEN_Msk (0x1UL << I2C_TIMEOUTR_TEXTEN_Pos)

#define	I2C_TIMEOUTR_TEXTEN I2C_TIMEOUTR_TEXTEN_Msk

#define	I2C_ISR_TXE_Pos (0U)

#define	I2C_ISR_TXE_Msk (0x1UL << I2C_ISR_TXE_Pos)

#define	I2C_ISR_TXE I2C_ISR_TXE_Msk

#define	I2C_ISR_TXIS_Pos (1U)

#define	I2C_ISR_TXIS_Msk (0x1UL << I2C_ISR_TXIS_Pos)

#define	I2C_ISR_TXIS I2C_ISR_TXIS_Msk

#define	I2C_ISR_RXNE_Pos (2U)

#define	I2C_ISR_RXNE_Msk (0x1UL << I2C_ISR_RXNE_Pos)

#define	I2C_ISR_RXNE I2C_ISR_RXNE_Msk

#define	I2C_ISR_ADDR_Pos (3U)

#define	I2C_ISR_ADDR_Msk (0x1UL << I2C_ISR_ADDR_Pos)

#define	I2C_ISR_ADDR I2C_ISR_ADDR_Msk

#define	I2C_ISR_NACKF_Pos (4U)

#define	I2C_ISR_NACKF_Msk (0x1UL << I2C_ISR_NACKF_Pos)

#define	I2C_ISR_NACKF I2C_ISR_NACKF_Msk

#define	I2C_ISR_STOPF_Pos (5U)

#define	I2C_ISR_STOPF_Msk (0x1UL << I2C_ISR_STOPF_Pos)

#define	I2C_ISR_STOPF I2C_ISR_STOPF_Msk

#define	I2C_ISR_TC_Pos (6U)

#define	I2C_ISR_TC_Msk (0x1UL << I2C_ISR_TC_Pos)

#define	I2C_ISR_TC I2C_ISR_TC_Msk

#define	I2C_ISR_TCR_Pos (7U)

#define	I2C_ISR_TCR_Msk (0x1UL << I2C_ISR_TCR_Pos)

#define	I2C_ISR_TCR I2C_ISR_TCR_Msk

#define	I2C_ISR_BERR_Pos (8U)

#define	I2C_ISR_BERR_Msk (0x1UL << I2C_ISR_BERR_Pos)

#define	I2C_ISR_BERR I2C_ISR_BERR_Msk

#define	I2C_ISR_ARLO_Pos (9U)

#define	I2C_ISR_ARLO_Msk (0x1UL << I2C_ISR_ARLO_Pos)

#define	I2C_ISR_ARLO I2C_ISR_ARLO_Msk

#define	I2C_ISR_OVR_Pos (10U)

#define	I2C_ISR_OVR_Msk (0x1UL << I2C_ISR_OVR_Pos)

#define	I2C_ISR_OVR I2C_ISR_OVR_Msk

#define	I2C_ISR_PECERR_Pos (11U)

#define	I2C_ISR_PECERR_Msk (0x1UL << I2C_ISR_PECERR_Pos)

#define	I2C_ISR_PECERR I2C_ISR_PECERR_Msk

#define	I2C_ISR_TIMEOUT_Pos (12U)

#define	I2C_ISR_TIMEOUT_Msk (0x1UL << I2C_ISR_TIMEOUT_Pos)

#define	I2C_ISR_TIMEOUT I2C_ISR_TIMEOUT_Msk

#define	I2C_ISR_ALERT_Pos (13U)

#define	I2C_ISR_ALERT_Msk (0x1UL << I2C_ISR_ALERT_Pos)

#define	I2C_ISR_ALERT I2C_ISR_ALERT_Msk

#define	I2C_ISR_BUSY_Pos (15U)

#define	I2C_ISR_BUSY_Msk (0x1UL << I2C_ISR_BUSY_Pos)

#define	I2C_ISR_BUSY I2C_ISR_BUSY_Msk

#define	I2C_ISR_DIR_Pos (16U)

#define	I2C_ISR_DIR_Msk (0x1UL << I2C_ISR_DIR_Pos)

#define	I2C_ISR_DIR I2C_ISR_DIR_Msk

#define	I2C_ISR_ADDCODE_Pos (17U)

#define	I2C_ISR_ADDCODE_Msk (0x7FUL << I2C_ISR_ADDCODE_Pos)

#define	I2C_ISR_ADDCODE I2C_ISR_ADDCODE_Msk

#define	I2C_ICR_ADDRCF_Pos (3U)

#define	I2C_ICR_ADDRCF_Msk (0x1UL << I2C_ICR_ADDRCF_Pos)

#define	I2C_ICR_ADDRCF I2C_ICR_ADDRCF_Msk

#define	I2C_ICR_NACKCF_Pos (4U)

#define	I2C_ICR_NACKCF_Msk (0x1UL << I2C_ICR_NACKCF_Pos)

#define	I2C_ICR_NACKCF I2C_ICR_NACKCF_Msk

#define	I2C_ICR_STOPCF_Pos (5U)

#define	I2C_ICR_STOPCF_Msk (0x1UL << I2C_ICR_STOPCF_Pos)

#define	I2C_ICR_STOPCF I2C_ICR_STOPCF_Msk

#define	I2C_ICR_BERRCF_Pos (8U)

#define	I2C_ICR_BERRCF_Msk (0x1UL << I2C_ICR_BERRCF_Pos)

#define	I2C_ICR_BERRCF I2C_ICR_BERRCF_Msk

#define	I2C_ICR_ARLOCF_Pos (9U)

#define	I2C_ICR_ARLOCF_Msk (0x1UL << I2C_ICR_ARLOCF_Pos)

#define	I2C_ICR_ARLOCF I2C_ICR_ARLOCF_Msk

#define	I2C_ICR_OVRCF_Pos (10U)

#define	I2C_ICR_OVRCF_Msk (0x1UL << I2C_ICR_OVRCF_Pos)

#define	I2C_ICR_OVRCF I2C_ICR_OVRCF_Msk

#define	I2C_ICR_PECCF_Pos (11U)

#define	I2C_ICR_PECCF_Msk (0x1UL << I2C_ICR_PECCF_Pos)

#define	I2C_ICR_PECCF I2C_ICR_PECCF_Msk

#define	I2C_ICR_TIMOUTCF_Pos (12U)

#define	I2C_ICR_TIMOUTCF_Msk (0x1UL << I2C_ICR_TIMOUTCF_Pos)

#define	I2C_ICR_TIMOUTCF I2C_ICR_TIMOUTCF_Msk

#define	I2C_ICR_ALERTCF_Pos (13U)

#define	I2C_ICR_ALERTCF_Msk (0x1UL << I2C_ICR_ALERTCF_Pos)

#define	I2C_ICR_ALERTCF I2C_ICR_ALERTCF_Msk

#define	I2C_PECR_PEC_Pos (0U)

#define	I2C_PECR_PEC_Msk (0xFFUL << I2C_PECR_PEC_Pos)

#define	I2C_PECR_PEC I2C_PECR_PEC_Msk

#define	I2C_RXDR_RXDATA_Pos (0U)

#define	I2C_RXDR_RXDATA_Msk (0xFFUL << I2C_RXDR_RXDATA_Pos)

#define	I2C_RXDR_RXDATA I2C_RXDR_RXDATA_Msk

#define	I2C_TXDR_TXDATA_Pos (0U)

#define	I2C_TXDR_TXDATA_Msk (0xFFUL << I2C_TXDR_TXDATA_Pos)

#define	I2C_TXDR_TXDATA I2C_TXDR_TXDATA_Msk

#define	IWDG_KR_KEY_Pos (0U)

#define	IWDG_KR_KEY_Msk (0xFFFFUL << IWDG_KR_KEY_Pos)

#define	IWDG_KR_KEY IWDG_KR_KEY_Msk

#define	IWDG_PR_PR_Pos (0U)

#define	IWDG_PR_PR_Msk (0x7UL << IWDG_PR_PR_Pos)

#define	IWDG_PR_PR IWDG_PR_PR_Msk

#define	IWDG_PR_PR_0 (0x1UL << IWDG_PR_PR_Pos)

#define	IWDG_PR_PR_1 (0x2UL << IWDG_PR_PR_Pos)

#define	IWDG_PR_PR_2 (0x4UL << IWDG_PR_PR_Pos)

#define	IWDG_RLR_RL_Pos (0U)

#define	IWDG_RLR_RL_Msk (0xFFFUL << IWDG_RLR_RL_Pos)

#define	IWDG_RLR_RL IWDG_RLR_RL_Msk

#define	IWDG_SR_PVU_Pos (0U)

#define	IWDG_SR_PVU_Msk (0x1UL << IWDG_SR_PVU_Pos)

#define	IWDG_SR_PVU IWDG_SR_PVU_Msk

#define	IWDG_SR_RVU_Pos (1U)

#define	IWDG_SR_RVU_Msk (0x1UL << IWDG_SR_RVU_Pos)

#define	IWDG_SR_RVU IWDG_SR_RVU_Msk

#define	IWDG_SR_WVU_Pos (2U)

#define	IWDG_SR_WVU_Msk (0x1UL << IWDG_SR_WVU_Pos)

#define	IWDG_SR_WVU IWDG_SR_WVU_Msk

#define	IWDG_WINR_WIN_Pos (0U)

#define	IWDG_WINR_WIN_Msk (0xFFFUL << IWDG_WINR_WIN_Pos)

#define	IWDG_WINR_WIN IWDG_WINR_WIN_Msk

#define	PWR_PVD_SUPPORT

#define	PWR_CR_LPDS_Pos (0U)

#define	PWR_CR_LPDS_Msk (0x1UL << PWR_CR_LPDS_Pos)

#define	PWR_CR_LPDS PWR_CR_LPDS_Msk

#define	PWR_CR_PDDS_Pos (1U)

#define	PWR_CR_PDDS_Msk (0x1UL << PWR_CR_PDDS_Pos)

#define	PWR_CR_PDDS PWR_CR_PDDS_Msk

#define	PWR_CR_CWUF_Pos (2U)

#define	PWR_CR_CWUF_Msk (0x1UL << PWR_CR_CWUF_Pos)

#define	PWR_CR_CWUF PWR_CR_CWUF_Msk

#define	PWR_CR_CSBF_Pos (3U)

#define	PWR_CR_CSBF_Msk (0x1UL << PWR_CR_CSBF_Pos)

#define	PWR_CR_CSBF PWR_CR_CSBF_Msk

#define	PWR_CR_PVDE_Pos (4U)

#define	PWR_CR_PVDE_Msk (0x1UL << PWR_CR_PVDE_Pos)

#define	PWR_CR_PVDE PWR_CR_PVDE_Msk

#define	PWR_CR_PLS_Pos (5U)

#define	PWR_CR_PLS_Msk (0x7UL << PWR_CR_PLS_Pos)

#define	PWR_CR_PLS PWR_CR_PLS_Msk

#define	PWR_CR_PLS_0 (0x1UL << PWR_CR_PLS_Pos)

#define	PWR_CR_PLS_1 (0x2UL << PWR_CR_PLS_Pos)

#define	PWR_CR_PLS_2 (0x4UL << PWR_CR_PLS_Pos)

#define	PWR_CR_PLS_LEV0 (0x00000000U)

#define	PWR_CR_PLS_LEV1 (0x00000020U)

#define	PWR_CR_PLS_LEV2 (0x00000040U)

#define	PWR_CR_PLS_LEV3 (0x00000060U)

#define	PWR_CR_PLS_LEV4 (0x00000080U)

#define	PWR_CR_PLS_LEV5 (0x000000A0U)

#define	PWR_CR_PLS_LEV6 (0x000000C0U)

#define	PWR_CR_PLS_LEV7 (0x000000E0U)

#define	PWR_CR_DBP_Pos (8U)

#define	PWR_CR_DBP_Msk (0x1UL << PWR_CR_DBP_Pos)

#define	PWR_CR_DBP PWR_CR_DBP_Msk

#define	PWR_CSR_WUF_Pos (0U)

#define	PWR_CSR_WUF_Msk (0x1UL << PWR_CSR_WUF_Pos)

#define	PWR_CSR_WUF PWR_CSR_WUF_Msk

#define	PWR_CSR_SBF_Pos (1U)

#define	PWR_CSR_SBF_Msk (0x1UL << PWR_CSR_SBF_Pos)

#define	PWR_CSR_SBF PWR_CSR_SBF_Msk

#define	PWR_CSR_PVDO_Pos (2U)

#define	PWR_CSR_PVDO_Msk (0x1UL << PWR_CSR_PVDO_Pos)

#define	PWR_CSR_PVDO PWR_CSR_PVDO_Msk

#define	PWR_CSR_VREFINTRDYF_Pos (3U)

#define	PWR_CSR_VREFINTRDYF_Msk (0x1UL << PWR_CSR_VREFINTRDYF_Pos)

#define	PWR_CSR_VREFINTRDYF PWR_CSR_VREFINTRDYF_Msk

#define	PWR_CSR_EWUP1_Pos (8U)

#define	PWR_CSR_EWUP1_Msk (0x1UL << PWR_CSR_EWUP1_Pos)

#define	PWR_CSR_EWUP1 PWR_CSR_EWUP1_Msk

#define	PWR_CSR_EWUP2_Pos (9U)

#define	PWR_CSR_EWUP2_Msk (0x1UL << PWR_CSR_EWUP2_Pos)

#define	PWR_CSR_EWUP2 PWR_CSR_EWUP2_Msk

#define	PWR_CSR_EWUP3_Pos (10U)

#define	PWR_CSR_EWUP3_Msk (0x1UL << PWR_CSR_EWUP3_Pos)

#define	PWR_CSR_EWUP3 PWR_CSR_EWUP3_Msk

#define	RCC_PLLSRC_PREDIV1_SUPPORT

#define	RCC_CR_HSION_Pos (0U)

#define	RCC_CR_HSION_Msk (0x1UL << RCC_CR_HSION_Pos)

#define	RCC_CR_HSION RCC_CR_HSION_Msk

#define	RCC_CR_HSIRDY_Pos (1U)

#define	RCC_CR_HSIRDY_Msk (0x1UL << RCC_CR_HSIRDY_Pos)

#define	RCC_CR_HSIRDY RCC_CR_HSIRDY_Msk

#define	RCC_CR_HSITRIM_Pos (3U)

#define	RCC_CR_HSITRIM_Msk (0x1FUL << RCC_CR_HSITRIM_Pos)

#define	RCC_CR_HSITRIM RCC_CR_HSITRIM_Msk

#define	RCC_CR_HSITRIM_0 (0x01UL << RCC_CR_HSITRIM_Pos)

#define	RCC_CR_HSITRIM_1 (0x02UL << RCC_CR_HSITRIM_Pos)

#define	RCC_CR_HSITRIM_2 (0x04UL << RCC_CR_HSITRIM_Pos)

#define	RCC_CR_HSITRIM_3 (0x08UL << RCC_CR_HSITRIM_Pos)

#define	RCC_CR_HSITRIM_4 (0x10UL << RCC_CR_HSITRIM_Pos)

#define	RCC_CR_HSICAL_Pos (8U)

#define	RCC_CR_HSICAL_Msk (0xFFUL << RCC_CR_HSICAL_Pos)

#define	RCC_CR_HSICAL RCC_CR_HSICAL_Msk

#define	RCC_CR_HSICAL_0 (0x01UL << RCC_CR_HSICAL_Pos)

#define	RCC_CR_HSICAL_1 (0x02UL << RCC_CR_HSICAL_Pos)

#define	RCC_CR_HSICAL_2 (0x04UL << RCC_CR_HSICAL_Pos)

#define	RCC_CR_HSICAL_3 (0x08UL << RCC_CR_HSICAL_Pos)

#define	RCC_CR_HSICAL_4 (0x10UL << RCC_CR_HSICAL_Pos)

#define	RCC_CR_HSICAL_5 (0x20UL << RCC_CR_HSICAL_Pos)

#define	RCC_CR_HSICAL_6 (0x40UL << RCC_CR_HSICAL_Pos)

#define	RCC_CR_HSICAL_7 (0x80UL << RCC_CR_HSICAL_Pos)

#define	RCC_CR_HSEON_Pos (16U)

#define	RCC_CR_HSEON_Msk (0x1UL << RCC_CR_HSEON_Pos)

#define	RCC_CR_HSEON RCC_CR_HSEON_Msk

#define	RCC_CR_HSERDY_Pos (17U)

#define	RCC_CR_HSERDY_Msk (0x1UL << RCC_CR_HSERDY_Pos)

#define	RCC_CR_HSERDY RCC_CR_HSERDY_Msk

#define	RCC_CR_HSEBYP_Pos (18U)

#define	RCC_CR_HSEBYP_Msk (0x1UL << RCC_CR_HSEBYP_Pos)

#define	RCC_CR_HSEBYP RCC_CR_HSEBYP_Msk

#define	RCC_CR_CSSON_Pos (19U)

#define	RCC_CR_CSSON_Msk (0x1UL << RCC_CR_CSSON_Pos)

#define	RCC_CR_CSSON RCC_CR_CSSON_Msk

#define	RCC_CR_PLLON_Pos (24U)

#define	RCC_CR_PLLON_Msk (0x1UL << RCC_CR_PLLON_Pos)

#define	RCC_CR_PLLON RCC_CR_PLLON_Msk

#define	RCC_CR_PLLRDY_Pos (25U)

#define	RCC_CR_PLLRDY_Msk (0x1UL << RCC_CR_PLLRDY_Pos)

#define	RCC_CR_PLLRDY RCC_CR_PLLRDY_Msk

#define	RCC_CFGR_SW_Pos (0U)

#define	RCC_CFGR_SW_Msk (0x3UL << RCC_CFGR_SW_Pos)

#define	RCC_CFGR_SW RCC_CFGR_SW_Msk

#define	RCC_CFGR_SW_0 (0x1UL << RCC_CFGR_SW_Pos)

#define	RCC_CFGR_SW_1 (0x2UL << RCC_CFGR_SW_Pos)

#define	RCC_CFGR_SW_HSI (0x00000000U)

#define	RCC_CFGR_SW_HSE (0x00000001U)

#define	RCC_CFGR_SW_PLL (0x00000002U)

#define	RCC_CFGR_SWS_Pos (2U)

#define	RCC_CFGR_SWS_Msk (0x3UL << RCC_CFGR_SWS_Pos)

#define	RCC_CFGR_SWS RCC_CFGR_SWS_Msk

#define	RCC_CFGR_SWS_0 (0x1UL << RCC_CFGR_SWS_Pos)

#define	RCC_CFGR_SWS_1 (0x2UL << RCC_CFGR_SWS_Pos)

#define	RCC_CFGR_SWS_HSI (0x00000000U)

#define	RCC_CFGR_SWS_HSE (0x00000004U)

#define	RCC_CFGR_SWS_PLL (0x00000008U)

#define	RCC_CFGR_HPRE_Pos (4U)

#define	RCC_CFGR_HPRE_Msk (0xFUL << RCC_CFGR_HPRE_Pos)

#define	RCC_CFGR_HPRE RCC_CFGR_HPRE_Msk

#define	RCC_CFGR_HPRE_0 (0x1UL << RCC_CFGR_HPRE_Pos)

#define	RCC_CFGR_HPRE_1 (0x2UL << RCC_CFGR_HPRE_Pos)

#define	RCC_CFGR_HPRE_2 (0x4UL << RCC_CFGR_HPRE_Pos)

#define	RCC_CFGR_HPRE_3 (0x8UL << RCC_CFGR_HPRE_Pos)

#define	RCC_CFGR_HPRE_DIV1 (0x00000000U)

#define	RCC_CFGR_HPRE_DIV2 (0x00000080U)

#define	RCC_CFGR_HPRE_DIV4 (0x00000090U)

#define	RCC_CFGR_HPRE_DIV8 (0x000000A0U)

#define	RCC_CFGR_HPRE_DIV16 (0x000000B0U)

#define	RCC_CFGR_HPRE_DIV64 (0x000000C0U)

#define	RCC_CFGR_HPRE_DIV128 (0x000000D0U)

#define	RCC_CFGR_HPRE_DIV256 (0x000000E0U)

#define	RCC_CFGR_HPRE_DIV512 (0x000000F0U)

#define	RCC_CFGR_PPRE1_Pos (8U)

#define	RCC_CFGR_PPRE1_Msk (0x7UL << RCC_CFGR_PPRE1_Pos)

#define	RCC_CFGR_PPRE1 RCC_CFGR_PPRE1_Msk

#define	RCC_CFGR_PPRE1_0 (0x1UL << RCC_CFGR_PPRE1_Pos)

#define	RCC_CFGR_PPRE1_1 (0x2UL << RCC_CFGR_PPRE1_Pos)

#define	RCC_CFGR_PPRE1_2 (0x4UL << RCC_CFGR_PPRE1_Pos)

#define	RCC_CFGR_PPRE1_DIV1 (0x00000000U)

#define	RCC_CFGR_PPRE1_DIV2 (0x00000400U)

#define	RCC_CFGR_PPRE1_DIV4 (0x00000500U)

#define	RCC_CFGR_PPRE1_DIV8 (0x00000600U)

#define	RCC_CFGR_PPRE1_DIV16 (0x00000700U)

#define	RCC_CFGR_PPRE2_Pos (11U)

#define	RCC_CFGR_PPRE2_Msk (0x7UL << RCC_CFGR_PPRE2_Pos)

#define	RCC_CFGR_PPRE2 RCC_CFGR_PPRE2_Msk

#define	RCC_CFGR_PPRE2_0 (0x1UL << RCC_CFGR_PPRE2_Pos)

#define	RCC_CFGR_PPRE2_1 (0x2UL << RCC_CFGR_PPRE2_Pos)

#define	RCC_CFGR_PPRE2_2 (0x4UL << RCC_CFGR_PPRE2_Pos)

#define	RCC_CFGR_PPRE2_DIV1 (0x00000000U)

#define	RCC_CFGR_PPRE2_DIV2 (0x00002000U)

#define	RCC_CFGR_PPRE2_DIV4 (0x00002800U)

#define	RCC_CFGR_PPRE2_DIV8 (0x00003000U)

#define	RCC_CFGR_PPRE2_DIV16 (0x00003800U)

#define	RCC_CFGR_PLLSRC_Pos (15U)

#define	RCC_CFGR_PLLSRC_Msk (0x3UL << RCC_CFGR_PLLSRC_Pos)

#define	RCC_CFGR_PLLSRC RCC_CFGR_PLLSRC_Msk

#define	RCC_CFGR_PLLSRC_HSI_PREDIV (0x00008000U)

#define	RCC_CFGR_PLLSRC_HSE_PREDIV (0x00010000U)

#define	RCC_CFGR_PLLXTPRE_Pos (17U)

#define	RCC_CFGR_PLLXTPRE_Msk (0x1UL << RCC_CFGR_PLLXTPRE_Pos)

#define	RCC_CFGR_PLLXTPRE RCC_CFGR_PLLXTPRE_Msk

#define	RCC_CFGR_PLLXTPRE_HSE_PREDIV_DIV1 (0x00000000U)

#define	RCC_CFGR_PLLXTPRE_HSE_PREDIV_DIV2 (0x00020000U)

#define	RCC_CFGR_PLLMUL_Pos (18U)

#define	RCC_CFGR_PLLMUL_Msk (0xFUL << RCC_CFGR_PLLMUL_Pos)

#define	RCC_CFGR_PLLMUL RCC_CFGR_PLLMUL_Msk

#define	RCC_CFGR_PLLMUL_0 (0x1UL << RCC_CFGR_PLLMUL_Pos)

#define	RCC_CFGR_PLLMUL_1 (0x2UL << RCC_CFGR_PLLMUL_Pos)

#define	RCC_CFGR_PLLMUL_2 (0x4UL << RCC_CFGR_PLLMUL_Pos)

#define	RCC_CFGR_PLLMUL_3 (0x8UL << RCC_CFGR_PLLMUL_Pos)

#define	RCC_CFGR_PLLMUL2 (0x00000000U)

#define	RCC_CFGR_PLLMUL3 (0x00040000U)

#define	RCC_CFGR_PLLMUL4 (0x00080000U)

#define	RCC_CFGR_PLLMUL5 (0x000C0000U)

#define	RCC_CFGR_PLLMUL6 (0x00100000U)

#define	RCC_CFGR_PLLMUL7 (0x00140000U)

#define	RCC_CFGR_PLLMUL8 (0x00180000U)

#define	RCC_CFGR_PLLMUL9 (0x001C0000U)

#define	RCC_CFGR_PLLMUL10 (0x00200000U)

#define	RCC_CFGR_PLLMUL11 (0x00240000U)

#define	RCC_CFGR_PLLMUL12 (0x00280000U)

#define	RCC_CFGR_PLLMUL13 (0x002C0000U)

#define	RCC_CFGR_PLLMUL14 (0x00300000U)

#define	RCC_CFGR_PLLMUL15 (0x00340000U)

#define	RCC_CFGR_PLLMUL16 (0x00380000U)

#define	RCC_CFGR_USBPRE_Pos (22U)

#define	RCC_CFGR_USBPRE_Msk (0x1UL << RCC_CFGR_USBPRE_Pos)

#define	RCC_CFGR_USBPRE RCC_CFGR_USBPRE_Msk

#define	RCC_CFGR_USBPRE_DIV1_5 (0x00000000U)

#define	RCC_CFGR_USBPRE_DIV1 (0x00400000U)

#define	RCC_CFGR_I2SSRC_Pos (23U)

#define	RCC_CFGR_I2SSRC_Msk (0x1UL << RCC_CFGR_I2SSRC_Pos)

#define	RCC_CFGR_I2SSRC RCC_CFGR_I2SSRC_Msk

#define	RCC_CFGR_I2SSRC_SYSCLK (0x00000000U)

#define	RCC_CFGR_I2SSRC_EXT (0x00800000U)

#define	RCC_CFGR_MCO_Pos (24U)

#define	RCC_CFGR_MCO_Msk (0x7UL << RCC_CFGR_MCO_Pos)

#define	RCC_CFGR_MCO RCC_CFGR_MCO_Msk

#define	RCC_CFGR_MCO_0 (0x1UL << RCC_CFGR_MCO_Pos)

#define	RCC_CFGR_MCO_1 (0x2UL << RCC_CFGR_MCO_Pos)

#define	RCC_CFGR_MCO_2 (0x4UL << RCC_CFGR_MCO_Pos)

#define	RCC_CFGR_MCO_NOCLOCK (0x00000000U)

#define	RCC_CFGR_MCO_LSI (0x02000000U)

#define	RCC_CFGR_MCO_LSE (0x03000000U)

#define	RCC_CFGR_MCO_SYSCLK (0x04000000U)

#define	RCC_CFGR_MCO_HSI (0x05000000U)

#define	RCC_CFGR_MCO_HSE (0x06000000U)

#define	RCC_CFGR_MCO_PLL (0x07000000U)

#define	RCC_CFGR_MCOPRE_Pos (28U)

#define	RCC_CFGR_MCOPRE_Msk (0x7UL << RCC_CFGR_MCOPRE_Pos)

#define	RCC_CFGR_MCOPRE RCC_CFGR_MCOPRE_Msk

#define	RCC_CFGR_MCOPRE_0 (0x1UL << RCC_CFGR_MCOPRE_Pos)

#define	RCC_CFGR_MCOPRE_1 (0x2UL << RCC_CFGR_MCOPRE_Pos)

#define	RCC_CFGR_MCOPRE_2 (0x4UL << RCC_CFGR_MCOPRE_Pos)

#define	RCC_CFGR_MCOPRE_DIV1 (0x00000000U)

#define	RCC_CFGR_MCOPRE_DIV2 (0x10000000U)

#define	RCC_CFGR_MCOPRE_DIV4 (0x20000000U)

#define	RCC_CFGR_MCOPRE_DIV8 (0x30000000U)

#define	RCC_CFGR_MCOPRE_DIV16 (0x40000000U)

#define	RCC_CFGR_MCOPRE_DIV32 (0x50000000U)

#define	RCC_CFGR_MCOPRE_DIV64 (0x60000000U)

#define	RCC_CFGR_MCOPRE_DIV128 (0x70000000U)

#define	RCC_CFGR_PLLNODIV_Pos (31U)

#define	RCC_CFGR_PLLNODIV_Msk (0x1UL << RCC_CFGR_PLLNODIV_Pos)

#define	RCC_CFGR_PLLNODIV RCC_CFGR_PLLNODIV_Msk

#define	RCC_CFGR_MCOSEL RCC_CFGR_MCO

#define	RCC_CFGR_MCOSEL_0 RCC_CFGR_MCO_0

#define	RCC_CFGR_MCOSEL_1 RCC_CFGR_MCO_1

#define	RCC_CFGR_MCOSEL_2 RCC_CFGR_MCO_2

#define	RCC_CFGR_MCOSEL_NOCLOCK RCC_CFGR_MCO_NOCLOCK

#define	RCC_CFGR_MCOSEL_LSI RCC_CFGR_MCO_LSI

#define	RCC_CFGR_MCOSEL_LSE RCC_CFGR_MCO_LSE

#define	RCC_CFGR_MCOSEL_SYSCLK RCC_CFGR_MCO_SYSCLK

#define	RCC_CFGR_MCOSEL_HSI RCC_CFGR_MCO_HSI

#define	RCC_CFGR_MCOSEL_HSE RCC_CFGR_MCO_HSE

#define	RCC_CFGR_MCOSEL_PLL_DIV2 RCC_CFGR_MCO_PLL

#define	RCC_CIR_LSIRDYF_Pos (0U)

#define	RCC_CIR_LSIRDYF_Msk (0x1UL << RCC_CIR_LSIRDYF_Pos)

#define	RCC_CIR_LSIRDYF RCC_CIR_LSIRDYF_Msk

#define	RCC_CIR_LSERDYF_Pos (1U)

#define	RCC_CIR_LSERDYF_Msk (0x1UL << RCC_CIR_LSERDYF_Pos)

#define	RCC_CIR_LSERDYF RCC_CIR_LSERDYF_Msk

#define	RCC_CIR_HSIRDYF_Pos (2U)

#define	RCC_CIR_HSIRDYF_Msk (0x1UL << RCC_CIR_HSIRDYF_Pos)

#define	RCC_CIR_HSIRDYF RCC_CIR_HSIRDYF_Msk

#define	RCC_CIR_HSERDYF_Pos (3U)

#define	RCC_CIR_HSERDYF_Msk (0x1UL << RCC_CIR_HSERDYF_Pos)

#define	RCC_CIR_HSERDYF RCC_CIR_HSERDYF_Msk

#define	RCC_CIR_PLLRDYF_Pos (4U)

#define	RCC_CIR_PLLRDYF_Msk (0x1UL << RCC_CIR_PLLRDYF_Pos)

#define	RCC_CIR_PLLRDYF RCC_CIR_PLLRDYF_Msk

#define	RCC_CIR_CSSF_Pos (7U)

#define	RCC_CIR_CSSF_Msk (0x1UL << RCC_CIR_CSSF_Pos)

#define	RCC_CIR_CSSF RCC_CIR_CSSF_Msk

#define	RCC_CIR_LSIRDYIE_Pos (8U)

#define	RCC_CIR_LSIRDYIE_Msk (0x1UL << RCC_CIR_LSIRDYIE_Pos)

#define	RCC_CIR_LSIRDYIE RCC_CIR_LSIRDYIE_Msk

#define	RCC_CIR_LSERDYIE_Pos (9U)

#define	RCC_CIR_LSERDYIE_Msk (0x1UL << RCC_CIR_LSERDYIE_Pos)

#define	RCC_CIR_LSERDYIE RCC_CIR_LSERDYIE_Msk

#define	RCC_CIR_HSIRDYIE_Pos (10U)

#define	RCC_CIR_HSIRDYIE_Msk (0x1UL << RCC_CIR_HSIRDYIE_Pos)

#define	RCC_CIR_HSIRDYIE RCC_CIR_HSIRDYIE_Msk

#define	RCC_CIR_HSERDYIE_Pos (11U)

#define	RCC_CIR_HSERDYIE_Msk (0x1UL << RCC_CIR_HSERDYIE_Pos)

#define	RCC_CIR_HSERDYIE RCC_CIR_HSERDYIE_Msk

#define	RCC_CIR_PLLRDYIE_Pos (12U)

#define	RCC_CIR_PLLRDYIE_Msk (0x1UL << RCC_CIR_PLLRDYIE_Pos)

#define	RCC_CIR_PLLRDYIE RCC_CIR_PLLRDYIE_Msk

#define	RCC_CIR_LSIRDYC_Pos (16U)

#define	RCC_CIR_LSIRDYC_Msk (0x1UL << RCC_CIR_LSIRDYC_Pos)

#define	RCC_CIR_LSIRDYC RCC_CIR_LSIRDYC_Msk

#define	RCC_CIR_LSERDYC_Pos (17U)

#define	RCC_CIR_LSERDYC_Msk (0x1UL << RCC_CIR_LSERDYC_Pos)

#define	RCC_CIR_LSERDYC RCC_CIR_LSERDYC_Msk

#define	RCC_CIR_HSIRDYC_Pos (18U)

#define	RCC_CIR_HSIRDYC_Msk (0x1UL << RCC_CIR_HSIRDYC_Pos)

#define	RCC_CIR_HSIRDYC RCC_CIR_HSIRDYC_Msk

#define	RCC_CIR_HSERDYC_Pos (19U)

#define	RCC_CIR_HSERDYC_Msk (0x1UL << RCC_CIR_HSERDYC_Pos)

#define	RCC_CIR_HSERDYC RCC_CIR_HSERDYC_Msk

#define	RCC_CIR_PLLRDYC_Pos (20U)

#define	RCC_CIR_PLLRDYC_Msk (0x1UL << RCC_CIR_PLLRDYC_Pos)

#define	RCC_CIR_PLLRDYC RCC_CIR_PLLRDYC_Msk

#define	RCC_CIR_CSSC_Pos (23U)

#define	RCC_CIR_CSSC_Msk (0x1UL << RCC_CIR_CSSC_Pos)

#define	RCC_CIR_CSSC RCC_CIR_CSSC_Msk

#define	RCC_APB2RSTR_SYSCFGRST_Pos (0U)

#define	RCC_APB2RSTR_SYSCFGRST_Msk (0x1UL << RCC_APB2RSTR_SYSCFGRST_Pos)

#define	RCC_APB2RSTR_SYSCFGRST RCC_APB2RSTR_SYSCFGRST_Msk

#define	RCC_APB2RSTR_TIM1RST_Pos (11U)

#define	RCC_APB2RSTR_TIM1RST_Msk (0x1UL << RCC_APB2RSTR_TIM1RST_Pos)

#define	RCC_APB2RSTR_TIM1RST RCC_APB2RSTR_TIM1RST_Msk

#define	RCC_APB2RSTR_SPI1RST_Pos (12U)

#define	RCC_APB2RSTR_SPI1RST_Msk (0x1UL << RCC_APB2RSTR_SPI1RST_Pos)

#define	RCC_APB2RSTR_SPI1RST RCC_APB2RSTR_SPI1RST_Msk

#define	RCC_APB2RSTR_TIM8RST_Pos (13U)

#define	RCC_APB2RSTR_TIM8RST_Msk (0x1UL << RCC_APB2RSTR_TIM8RST_Pos)

#define	RCC_APB2RSTR_TIM8RST RCC_APB2RSTR_TIM8RST_Msk

#define	RCC_APB2RSTR_USART1RST_Pos (14U)

#define	RCC_APB2RSTR_USART1RST_Msk (0x1UL << RCC_APB2RSTR_USART1RST_Pos)

#define	RCC_APB2RSTR_USART1RST RCC_APB2RSTR_USART1RST_Msk

#define	RCC_APB2RSTR_SPI4RST_Pos (15U)

#define	RCC_APB2RSTR_SPI4RST_Msk (0x1UL << RCC_APB2RSTR_SPI4RST_Pos)

#define	RCC_APB2RSTR_SPI4RST RCC_APB2RSTR_SPI4RST_Msk

#define	RCC_APB2RSTR_TIM15RST_Pos (16U)

#define	RCC_APB2RSTR_TIM15RST_Msk (0x1UL << RCC_APB2RSTR_TIM15RST_Pos)

#define	RCC_APB2RSTR_TIM15RST RCC_APB2RSTR_TIM15RST_Msk

#define	RCC_APB2RSTR_TIM16RST_Pos (17U)

#define	RCC_APB2RSTR_TIM16RST_Msk (0x1UL << RCC_APB2RSTR_TIM16RST_Pos)

#define	RCC_APB2RSTR_TIM16RST RCC_APB2RSTR_TIM16RST_Msk

#define	RCC_APB2RSTR_TIM17RST_Pos (18U)

#define	RCC_APB2RSTR_TIM17RST_Msk (0x1UL << RCC_APB2RSTR_TIM17RST_Pos)

#define	RCC_APB2RSTR_TIM17RST RCC_APB2RSTR_TIM17RST_Msk

#define	RCC_APB2RSTR_TIM20RST_Pos (20U)

#define	RCC_APB2RSTR_TIM20RST_Msk (0x1UL << RCC_APB2RSTR_TIM20RST_Pos)

#define	RCC_APB2RSTR_TIM20RST RCC_APB2RSTR_TIM20RST_Msk

#define	RCC_APB1RSTR_TIM2RST_Pos (0U)

#define	RCC_APB1RSTR_TIM2RST_Msk (0x1UL << RCC_APB1RSTR_TIM2RST_Pos)

#define	RCC_APB1RSTR_TIM2RST RCC_APB1RSTR_TIM2RST_Msk

#define	RCC_APB1RSTR_TIM3RST_Pos (1U)

#define	RCC_APB1RSTR_TIM3RST_Msk (0x1UL << RCC_APB1RSTR_TIM3RST_Pos)

#define	RCC_APB1RSTR_TIM3RST RCC_APB1RSTR_TIM3RST_Msk

#define	RCC_APB1RSTR_TIM4RST_Pos (2U)

#define	RCC_APB1RSTR_TIM4RST_Msk (0x1UL << RCC_APB1RSTR_TIM4RST_Pos)

#define	RCC_APB1RSTR_TIM4RST RCC_APB1RSTR_TIM4RST_Msk

#define	RCC_APB1RSTR_TIM6RST_Pos (4U)

#define	RCC_APB1RSTR_TIM6RST_Msk (0x1UL << RCC_APB1RSTR_TIM6RST_Pos)

#define	RCC_APB1RSTR_TIM6RST RCC_APB1RSTR_TIM6RST_Msk

#define	RCC_APB1RSTR_TIM7RST_Pos (5U)

#define	RCC_APB1RSTR_TIM7RST_Msk (0x1UL << RCC_APB1RSTR_TIM7RST_Pos)

#define	RCC_APB1RSTR_TIM7RST RCC_APB1RSTR_TIM7RST_Msk

#define	RCC_APB1RSTR_WWDGRST_Pos (11U)

#define	RCC_APB1RSTR_WWDGRST_Msk (0x1UL << RCC_APB1RSTR_WWDGRST_Pos)

#define	RCC_APB1RSTR_WWDGRST RCC_APB1RSTR_WWDGRST_Msk

#define	RCC_APB1RSTR_SPI2RST_Pos (14U)

#define	RCC_APB1RSTR_SPI2RST_Msk (0x1UL << RCC_APB1RSTR_SPI2RST_Pos)

#define	RCC_APB1RSTR_SPI2RST RCC_APB1RSTR_SPI2RST_Msk

#define	RCC_APB1RSTR_SPI3RST_Pos (15U)

#define	RCC_APB1RSTR_SPI3RST_Msk (0x1UL << RCC_APB1RSTR_SPI3RST_Pos)

#define	RCC_APB1RSTR_SPI3RST RCC_APB1RSTR_SPI3RST_Msk

#define	RCC_APB1RSTR_USART2RST_Pos (17U)

#define	RCC_APB1RSTR_USART2RST_Msk (0x1UL << RCC_APB1RSTR_USART2RST_Pos)

#define	RCC_APB1RSTR_USART2RST RCC_APB1RSTR_USART2RST_Msk

#define	RCC_APB1RSTR_USART3RST_Pos (18U)

#define	RCC_APB1RSTR_USART3RST_Msk (0x1UL << RCC_APB1RSTR_USART3RST_Pos)

#define	RCC_APB1RSTR_USART3RST RCC_APB1RSTR_USART3RST_Msk

#define	RCC_APB1RSTR_UART4RST_Pos (19U)

#define	RCC_APB1RSTR_UART4RST_Msk (0x1UL << RCC_APB1RSTR_UART4RST_Pos)

#define	RCC_APB1RSTR_UART4RST RCC_APB1RSTR_UART4RST_Msk

#define	RCC_APB1RSTR_UART5RST_Pos (20U)

#define	RCC_APB1RSTR_UART5RST_Msk (0x1UL << RCC_APB1RSTR_UART5RST_Pos)

#define	RCC_APB1RSTR_UART5RST RCC_APB1RSTR_UART5RST_Msk

#define	RCC_APB1RSTR_I2C1RST_Pos (21U)

#define	RCC_APB1RSTR_I2C1RST_Msk (0x1UL << RCC_APB1RSTR_I2C1RST_Pos)

#define	RCC_APB1RSTR_I2C1RST RCC_APB1RSTR_I2C1RST_Msk

#define	RCC_APB1RSTR_I2C2RST_Pos (22U)

#define	RCC_APB1RSTR_I2C2RST_Msk (0x1UL << RCC_APB1RSTR_I2C2RST_Pos)

#define	RCC_APB1RSTR_I2C2RST RCC_APB1RSTR_I2C2RST_Msk

#define	RCC_APB1RSTR_USBRST_Pos (23U)

#define	RCC_APB1RSTR_USBRST_Msk (0x1UL << RCC_APB1RSTR_USBRST_Pos)

#define	RCC_APB1RSTR_USBRST RCC_APB1RSTR_USBRST_Msk

#define	RCC_APB1RSTR_CANRST_Pos (25U)

#define	RCC_APB1RSTR_CANRST_Msk (0x1UL << RCC_APB1RSTR_CANRST_Pos)

#define	RCC_APB1RSTR_CANRST RCC_APB1RSTR_CANRST_Msk

#define	RCC_APB1RSTR_PWRRST_Pos (28U)

#define	RCC_APB1RSTR_PWRRST_Msk (0x1UL << RCC_APB1RSTR_PWRRST_Pos)

#define	RCC_APB1RSTR_PWRRST RCC_APB1RSTR_PWRRST_Msk

#define	RCC_APB1RSTR_DAC1RST_Pos (29U)

#define	RCC_APB1RSTR_DAC1RST_Msk (0x1UL << RCC_APB1RSTR_DAC1RST_Pos)

#define	RCC_APB1RSTR_DAC1RST RCC_APB1RSTR_DAC1RST_Msk

#define	RCC_APB1RSTR_I2C3RST_Pos (30U)

#define	RCC_APB1RSTR_I2C3RST_Msk (0x1UL << RCC_APB1RSTR_I2C3RST_Pos)

#define	RCC_APB1RSTR_I2C3RST RCC_APB1RSTR_I2C3RST_Msk

#define	RCC_AHBENR_DMA1EN_Pos (0U)

#define	RCC_AHBENR_DMA1EN_Msk (0x1UL << RCC_AHBENR_DMA1EN_Pos)

#define	RCC_AHBENR_DMA1EN RCC_AHBENR_DMA1EN_Msk

#define	RCC_AHBENR_DMA2EN_Pos (1U)

#define	RCC_AHBENR_DMA2EN_Msk (0x1UL << RCC_AHBENR_DMA2EN_Pos)

#define	RCC_AHBENR_DMA2EN RCC_AHBENR_DMA2EN_Msk

#define	RCC_AHBENR_SRAMEN_Pos (2U)

#define	RCC_AHBENR_SRAMEN_Msk (0x1UL << RCC_AHBENR_SRAMEN_Pos)

#define	RCC_AHBENR_SRAMEN RCC_AHBENR_SRAMEN_Msk

#define	RCC_AHBENR_FLITFEN_Pos (4U)

#define	RCC_AHBENR_FLITFEN_Msk (0x1UL << RCC_AHBENR_FLITFEN_Pos)

#define	RCC_AHBENR_FLITFEN RCC_AHBENR_FLITFEN_Msk

#define	RCC_AHBENR_FMCEN_Pos (5U)

#define	RCC_AHBENR_FMCEN_Msk (0x1UL << RCC_AHBENR_FMCEN_Pos)

#define	RCC_AHBENR_FMCEN RCC_AHBENR_FMCEN_Msk

#define	RCC_AHBENR_CRCEN_Pos (6U)

#define	RCC_AHBENR_CRCEN_Msk (0x1UL << RCC_AHBENR_CRCEN_Pos)

#define	RCC_AHBENR_CRCEN RCC_AHBENR_CRCEN_Msk

#define	RCC_AHBENR_GPIOHEN_Pos (16U)

#define	RCC_AHBENR_GPIOHEN_Msk (0x1UL << RCC_AHBENR_GPIOHEN_Pos)

#define	RCC_AHBENR_GPIOHEN RCC_AHBENR_GPIOHEN_Msk

#define	RCC_AHBENR_GPIOAEN_Pos (17U)

#define	RCC_AHBENR_GPIOAEN_Msk (0x1UL << RCC_AHBENR_GPIOAEN_Pos)

#define	RCC_AHBENR_GPIOAEN RCC_AHBENR_GPIOAEN_Msk

#define	RCC_AHBENR_GPIOBEN_Pos (18U)

#define	RCC_AHBENR_GPIOBEN_Msk (0x1UL << RCC_AHBENR_GPIOBEN_Pos)

#define	RCC_AHBENR_GPIOBEN RCC_AHBENR_GPIOBEN_Msk

#define	RCC_AHBENR_GPIOCEN_Pos (19U)

#define	RCC_AHBENR_GPIOCEN_Msk (0x1UL << RCC_AHBENR_GPIOCEN_Pos)

#define	RCC_AHBENR_GPIOCEN RCC_AHBENR_GPIOCEN_Msk

#define	RCC_AHBENR_GPIODEN_Pos (20U)

#define	RCC_AHBENR_GPIODEN_Msk (0x1UL << RCC_AHBENR_GPIODEN_Pos)

#define	RCC_AHBENR_GPIODEN RCC_AHBENR_GPIODEN_Msk

#define	RCC_AHBENR_GPIOEEN_Pos (21U)

#define	RCC_AHBENR_GPIOEEN_Msk (0x1UL << RCC_AHBENR_GPIOEEN_Pos)

#define	RCC_AHBENR_GPIOEEN RCC_AHBENR_GPIOEEN_Msk

#define	RCC_AHBENR_GPIOFEN_Pos (22U)

#define	RCC_AHBENR_GPIOFEN_Msk (0x1UL << RCC_AHBENR_GPIOFEN_Pos)

#define	RCC_AHBENR_GPIOFEN RCC_AHBENR_GPIOFEN_Msk

#define	RCC_AHBENR_GPIOGEN_Pos (23U)

#define	RCC_AHBENR_GPIOGEN_Msk (0x1UL << RCC_AHBENR_GPIOGEN_Pos)

#define	RCC_AHBENR_GPIOGEN RCC_AHBENR_GPIOGEN_Msk

#define	RCC_AHBENR_TSCEN_Pos (24U)

#define	RCC_AHBENR_TSCEN_Msk (0x1UL << RCC_AHBENR_TSCEN_Pos)

#define	RCC_AHBENR_TSCEN RCC_AHBENR_TSCEN_Msk

#define	RCC_AHBENR_ADC12EN_Pos (28U)

#define	RCC_AHBENR_ADC12EN_Msk (0x1UL << RCC_AHBENR_ADC12EN_Pos)

#define	RCC_AHBENR_ADC12EN RCC_AHBENR_ADC12EN_Msk

#define	RCC_AHBENR_ADC34EN_Pos (29U)

#define	RCC_AHBENR_ADC34EN_Msk (0x1UL << RCC_AHBENR_ADC34EN_Pos)

#define	RCC_AHBENR_ADC34EN RCC_AHBENR_ADC34EN_Msk

#define	RCC_APB2ENR_SYSCFGEN_Pos (0U)

#define	RCC_APB2ENR_SYSCFGEN_Msk (0x1UL << RCC_APB2ENR_SYSCFGEN_Pos)

#define	RCC_APB2ENR_SYSCFGEN RCC_APB2ENR_SYSCFGEN_Msk

#define	RCC_APB2ENR_TIM1EN_Pos (11U)

#define	RCC_APB2ENR_TIM1EN_Msk (0x1UL << RCC_APB2ENR_TIM1EN_Pos)

#define	RCC_APB2ENR_TIM1EN RCC_APB2ENR_TIM1EN_Msk

#define	RCC_APB2ENR_SPI1EN_Pos (12U)

#define	RCC_APB2ENR_SPI1EN_Msk (0x1UL << RCC_APB2ENR_SPI1EN_Pos)

#define	RCC_APB2ENR_SPI1EN RCC_APB2ENR_SPI1EN_Msk

#define	RCC_APB2ENR_TIM8EN_Pos (13U)

#define	RCC_APB2ENR_TIM8EN_Msk (0x1UL << RCC_APB2ENR_TIM8EN_Pos)

#define	RCC_APB2ENR_TIM8EN RCC_APB2ENR_TIM8EN_Msk

#define	RCC_APB2ENR_USART1EN_Pos (14U)

#define	RCC_APB2ENR_USART1EN_Msk (0x1UL << RCC_APB2ENR_USART1EN_Pos)

#define	RCC_APB2ENR_USART1EN RCC_APB2ENR_USART1EN_Msk

#define	RCC_APB2ENR_SPI4EN_Pos (15U)

#define	RCC_APB2ENR_SPI4EN_Msk (0x1UL << RCC_APB2ENR_SPI4EN_Pos)

#define	RCC_APB2ENR_SPI4EN RCC_APB2ENR_SPI4EN_Msk

#define	RCC_APB2ENR_TIM15EN_Pos (16U)

#define	RCC_APB2ENR_TIM15EN_Msk (0x1UL << RCC_APB2ENR_TIM15EN_Pos)

#define	RCC_APB2ENR_TIM15EN RCC_APB2ENR_TIM15EN_Msk

#define	RCC_APB2ENR_TIM16EN_Pos (17U)

#define	RCC_APB2ENR_TIM16EN_Msk (0x1UL << RCC_APB2ENR_TIM16EN_Pos)

#define	RCC_APB2ENR_TIM16EN RCC_APB2ENR_TIM16EN_Msk

#define	RCC_APB2ENR_TIM17EN_Pos (18U)

#define	RCC_APB2ENR_TIM17EN_Msk (0x1UL << RCC_APB2ENR_TIM17EN_Pos)

#define	RCC_APB2ENR_TIM17EN RCC_APB2ENR_TIM17EN_Msk

#define	RCC_APB2ENR_TIM20EN_Pos (20U)

#define	RCC_APB2ENR_TIM20EN_Msk (0x1UL << RCC_APB2ENR_TIM20EN_Pos)

#define	RCC_APB2ENR_TIM20EN RCC_APB2ENR_TIM20EN_Msk

#define	RCC_APB1ENR_TIM2EN_Pos (0U)

#define	RCC_APB1ENR_TIM2EN_Msk (0x1UL << RCC_APB1ENR_TIM2EN_Pos)

#define	RCC_APB1ENR_TIM2EN RCC_APB1ENR_TIM2EN_Msk

#define	RCC_APB1ENR_TIM3EN_Pos (1U)

#define	RCC_APB1ENR_TIM3EN_Msk (0x1UL << RCC_APB1ENR_TIM3EN_Pos)

#define	RCC_APB1ENR_TIM3EN RCC_APB1ENR_TIM3EN_Msk

#define	RCC_APB1ENR_TIM4EN_Pos (2U)

#define	RCC_APB1ENR_TIM4EN_Msk (0x1UL << RCC_APB1ENR_TIM4EN_Pos)

#define	RCC_APB1ENR_TIM4EN RCC_APB1ENR_TIM4EN_Msk

#define	RCC_APB1ENR_TIM6EN_Pos (4U)

#define	RCC_APB1ENR_TIM6EN_Msk (0x1UL << RCC_APB1ENR_TIM6EN_Pos)

#define	RCC_APB1ENR_TIM6EN RCC_APB1ENR_TIM6EN_Msk

#define	RCC_APB1ENR_TIM7EN_Pos (5U)

#define	RCC_APB1ENR_TIM7EN_Msk (0x1UL << RCC_APB1ENR_TIM7EN_Pos)

#define	RCC_APB1ENR_TIM7EN RCC_APB1ENR_TIM7EN_Msk

#define	RCC_APB1ENR_WWDGEN_Pos (11U)

#define	RCC_APB1ENR_WWDGEN_Msk (0x1UL << RCC_APB1ENR_WWDGEN_Pos)

#define	RCC_APB1ENR_WWDGEN RCC_APB1ENR_WWDGEN_Msk

#define	RCC_APB1ENR_SPI2EN_Pos (14U)

#define	RCC_APB1ENR_SPI2EN_Msk (0x1UL << RCC_APB1ENR_SPI2EN_Pos)

#define	RCC_APB1ENR_SPI2EN RCC_APB1ENR_SPI2EN_Msk

#define	RCC_APB1ENR_SPI3EN_Pos (15U)

#define	RCC_APB1ENR_SPI3EN_Msk (0x1UL << RCC_APB1ENR_SPI3EN_Pos)

#define	RCC_APB1ENR_SPI3EN RCC_APB1ENR_SPI3EN_Msk

#define	RCC_APB1ENR_USART2EN_Pos (17U)

#define	RCC_APB1ENR_USART2EN_Msk (0x1UL << RCC_APB1ENR_USART2EN_Pos)

#define	RCC_APB1ENR_USART2EN RCC_APB1ENR_USART2EN_Msk

#define	RCC_APB1ENR_USART3EN_Pos (18U)

#define	RCC_APB1ENR_USART3EN_Msk (0x1UL << RCC_APB1ENR_USART3EN_Pos)

#define	RCC_APB1ENR_USART3EN RCC_APB1ENR_USART3EN_Msk

#define	RCC_APB1ENR_UART4EN_Pos (19U)

#define	RCC_APB1ENR_UART4EN_Msk (0x1UL << RCC_APB1ENR_UART4EN_Pos)

#define	RCC_APB1ENR_UART4EN RCC_APB1ENR_UART4EN_Msk

#define	RCC_APB1ENR_UART5EN_Pos (20U)

#define	RCC_APB1ENR_UART5EN_Msk (0x1UL << RCC_APB1ENR_UART5EN_Pos)

#define	RCC_APB1ENR_UART5EN RCC_APB1ENR_UART5EN_Msk

#define	RCC_APB1ENR_I2C1EN_Pos (21U)

#define	RCC_APB1ENR_I2C1EN_Msk (0x1UL << RCC_APB1ENR_I2C1EN_Pos)

#define	RCC_APB1ENR_I2C1EN RCC_APB1ENR_I2C1EN_Msk

#define	RCC_APB1ENR_I2C2EN_Pos (22U)

#define	RCC_APB1ENR_I2C2EN_Msk (0x1UL << RCC_APB1ENR_I2C2EN_Pos)

#define	RCC_APB1ENR_I2C2EN RCC_APB1ENR_I2C2EN_Msk

#define	RCC_APB1ENR_USBEN_Pos (23U)

#define	RCC_APB1ENR_USBEN_Msk (0x1UL << RCC_APB1ENR_USBEN_Pos)

#define	RCC_APB1ENR_USBEN RCC_APB1ENR_USBEN_Msk

#define	RCC_APB1ENR_CANEN_Pos (25U)

#define	RCC_APB1ENR_CANEN_Msk (0x1UL << RCC_APB1ENR_CANEN_Pos)

#define	RCC_APB1ENR_CANEN RCC_APB1ENR_CANEN_Msk

#define	RCC_APB1ENR_PWREN_Pos (28U)

#define	RCC_APB1ENR_PWREN_Msk (0x1UL << RCC_APB1ENR_PWREN_Pos)

#define	RCC_APB1ENR_PWREN RCC_APB1ENR_PWREN_Msk

#define	RCC_APB1ENR_DAC1EN_Pos (29U)

#define	RCC_APB1ENR_DAC1EN_Msk (0x1UL << RCC_APB1ENR_DAC1EN_Pos)

#define	RCC_APB1ENR_DAC1EN RCC_APB1ENR_DAC1EN_Msk

#define	RCC_APB1ENR_I2C3EN_Pos (30U)

#define	RCC_APB1ENR_I2C3EN_Msk (0x1UL << RCC_APB1ENR_I2C3EN_Pos)

#define	RCC_APB1ENR_I2C3EN RCC_APB1ENR_I2C3EN_Msk

#define	RCC_BDCR_LSE_Pos (0U)

#define	RCC_BDCR_LSE_Msk (0x7UL << RCC_BDCR_LSE_Pos)

#define	RCC_BDCR_LSE RCC_BDCR_LSE_Msk

#define	RCC_BDCR_LSEON_Pos (0U)

#define	RCC_BDCR_LSEON_Msk (0x1UL << RCC_BDCR_LSEON_Pos)

#define	RCC_BDCR_LSEON RCC_BDCR_LSEON_Msk

#define	RCC_BDCR_LSERDY_Pos (1U)

#define	RCC_BDCR_LSERDY_Msk (0x1UL << RCC_BDCR_LSERDY_Pos)

#define	RCC_BDCR_LSERDY RCC_BDCR_LSERDY_Msk

#define	RCC_BDCR_LSEBYP_Pos (2U)

#define	RCC_BDCR_LSEBYP_Msk (0x1UL << RCC_BDCR_LSEBYP_Pos)

#define	RCC_BDCR_LSEBYP RCC_BDCR_LSEBYP_Msk

#define	RCC_BDCR_LSEDRV_Pos (3U)

#define	RCC_BDCR_LSEDRV_Msk (0x3UL << RCC_BDCR_LSEDRV_Pos)

#define	RCC_BDCR_LSEDRV RCC_BDCR_LSEDRV_Msk

#define	RCC_BDCR_LSEDRV_0 (0x1UL << RCC_BDCR_LSEDRV_Pos)

#define	RCC_BDCR_LSEDRV_1 (0x2UL << RCC_BDCR_LSEDRV_Pos)

#define	RCC_BDCR_RTCSEL_Pos (8U)

#define	RCC_BDCR_RTCSEL_Msk (0x3UL << RCC_BDCR_RTCSEL_Pos)

#define	RCC_BDCR_RTCSEL RCC_BDCR_RTCSEL_Msk

#define	RCC_BDCR_RTCSEL_0 (0x1UL << RCC_BDCR_RTCSEL_Pos)

#define	RCC_BDCR_RTCSEL_1 (0x2UL << RCC_BDCR_RTCSEL_Pos)

#define	RCC_BDCR_RTCSEL_NOCLOCK (0x00000000U)

#define	RCC_BDCR_RTCSEL_LSE (0x00000100U)

#define	RCC_BDCR_RTCSEL_LSI (0x00000200U)

#define	RCC_BDCR_RTCSEL_HSE (0x00000300U)

#define	RCC_BDCR_RTCEN_Pos (15U)

#define	RCC_BDCR_RTCEN_Msk (0x1UL << RCC_BDCR_RTCEN_Pos)

#define	RCC_BDCR_RTCEN RCC_BDCR_RTCEN_Msk

#define	RCC_BDCR_BDRST_Pos (16U)

#define	RCC_BDCR_BDRST_Msk (0x1UL << RCC_BDCR_BDRST_Pos)

#define	RCC_BDCR_BDRST RCC_BDCR_BDRST_Msk

#define	RCC_CSR_LSION_Pos (0U)

#define	RCC_CSR_LSION_Msk (0x1UL << RCC_CSR_LSION_Pos)

#define	RCC_CSR_LSION RCC_CSR_LSION_Msk

#define	RCC_CSR_LSIRDY_Pos (1U)

#define	RCC_CSR_LSIRDY_Msk (0x1UL << RCC_CSR_LSIRDY_Pos)

#define	RCC_CSR_LSIRDY RCC_CSR_LSIRDY_Msk

#define	RCC_CSR_V18PWRRSTF_Pos (23U)

#define	RCC_CSR_V18PWRRSTF_Msk (0x1UL << RCC_CSR_V18PWRRSTF_Pos)

#define	RCC_CSR_V18PWRRSTF RCC_CSR_V18PWRRSTF_Msk

#define	RCC_CSR_RMVF_Pos (24U)

#define	RCC_CSR_RMVF_Msk (0x1UL << RCC_CSR_RMVF_Pos)

#define	RCC_CSR_RMVF RCC_CSR_RMVF_Msk

#define	RCC_CSR_OBLRSTF_Pos (25U)

#define	RCC_CSR_OBLRSTF_Msk (0x1UL << RCC_CSR_OBLRSTF_Pos)

#define	RCC_CSR_OBLRSTF RCC_CSR_OBLRSTF_Msk

#define	RCC_CSR_PINRSTF_Pos (26U)

#define	RCC_CSR_PINRSTF_Msk (0x1UL << RCC_CSR_PINRSTF_Pos)

#define	RCC_CSR_PINRSTF RCC_CSR_PINRSTF_Msk

#define	RCC_CSR_PORRSTF_Pos (27U)

#define	RCC_CSR_PORRSTF_Msk (0x1UL << RCC_CSR_PORRSTF_Pos)

#define	RCC_CSR_PORRSTF RCC_CSR_PORRSTF_Msk

#define	RCC_CSR_SFTRSTF_Pos (28U)

#define	RCC_CSR_SFTRSTF_Msk (0x1UL << RCC_CSR_SFTRSTF_Pos)

#define	RCC_CSR_SFTRSTF RCC_CSR_SFTRSTF_Msk

#define	RCC_CSR_IWDGRSTF_Pos (29U)

#define	RCC_CSR_IWDGRSTF_Msk (0x1UL << RCC_CSR_IWDGRSTF_Pos)

#define	RCC_CSR_IWDGRSTF RCC_CSR_IWDGRSTF_Msk

#define	RCC_CSR_WWDGRSTF_Pos (30U)

#define	RCC_CSR_WWDGRSTF_Msk (0x1UL << RCC_CSR_WWDGRSTF_Pos)

#define	RCC_CSR_WWDGRSTF RCC_CSR_WWDGRSTF_Msk

#define	RCC_CSR_LPWRRSTF_Pos (31U)

#define	RCC_CSR_LPWRRSTF_Msk (0x1UL << RCC_CSR_LPWRRSTF_Pos)

#define	RCC_CSR_LPWRRSTF RCC_CSR_LPWRRSTF_Msk

#define	RCC_CSR_VREGRSTF RCC_CSR_V18PWRRSTF

#define	RCC_AHBRSTR_FMCRST_Pos (5U)

#define	RCC_AHBRSTR_FMCRST_Msk (0x1UL << RCC_AHBRSTR_FMCRST_Pos)

#define	RCC_AHBRSTR_FMCRST RCC_AHBRSTR_FMCRST_Msk

#define	RCC_AHBRSTR_GPIOHRST_Pos (16U)

#define	RCC_AHBRSTR_GPIOHRST_Msk (0x1UL << RCC_AHBRSTR_GPIOHRST_Pos)

#define	RCC_AHBRSTR_GPIOHRST RCC_AHBRSTR_GPIOHRST_Msk

#define	RCC_AHBRSTR_GPIOARST_Pos (17U)

#define	RCC_AHBRSTR_GPIOARST_Msk (0x1UL << RCC_AHBRSTR_GPIOARST_Pos)

#define	RCC_AHBRSTR_GPIOARST RCC_AHBRSTR_GPIOARST_Msk

#define	RCC_AHBRSTR_GPIOBRST_Pos (18U)

#define	RCC_AHBRSTR_GPIOBRST_Msk (0x1UL << RCC_AHBRSTR_GPIOBRST_Pos)

#define	RCC_AHBRSTR_GPIOBRST RCC_AHBRSTR_GPIOBRST_Msk

#define	RCC_AHBRSTR_GPIOCRST_Pos (19U)

#define	RCC_AHBRSTR_GPIOCRST_Msk (0x1UL << RCC_AHBRSTR_GPIOCRST_Pos)

#define	RCC_AHBRSTR_GPIOCRST RCC_AHBRSTR_GPIOCRST_Msk

#define	RCC_AHBRSTR_GPIODRST_Pos (20U)

#define	RCC_AHBRSTR_GPIODRST_Msk (0x1UL << RCC_AHBRSTR_GPIODRST_Pos)

#define	RCC_AHBRSTR_GPIODRST RCC_AHBRSTR_GPIODRST_Msk

#define	RCC_AHBRSTR_GPIOERST_Pos (21U)

#define	RCC_AHBRSTR_GPIOERST_Msk (0x1UL << RCC_AHBRSTR_GPIOERST_Pos)

#define	RCC_AHBRSTR_GPIOERST RCC_AHBRSTR_GPIOERST_Msk

#define	RCC_AHBRSTR_GPIOFRST_Pos (22U)

#define	RCC_AHBRSTR_GPIOFRST_Msk (0x1UL << RCC_AHBRSTR_GPIOFRST_Pos)

#define	RCC_AHBRSTR_GPIOFRST RCC_AHBRSTR_GPIOFRST_Msk

#define	RCC_AHBRSTR_GPIOGRST_Pos (23U)

#define	RCC_AHBRSTR_GPIOGRST_Msk (0x1UL << RCC_AHBRSTR_GPIOGRST_Pos)

#define	RCC_AHBRSTR_GPIOGRST RCC_AHBRSTR_GPIOGRST_Msk

#define	RCC_AHBRSTR_TSCRST_Pos (24U)

#define	RCC_AHBRSTR_TSCRST_Msk (0x1UL << RCC_AHBRSTR_TSCRST_Pos)

#define	RCC_AHBRSTR_TSCRST RCC_AHBRSTR_TSCRST_Msk

#define	RCC_AHBRSTR_ADC12RST_Pos (28U)

#define	RCC_AHBRSTR_ADC12RST_Msk (0x1UL << RCC_AHBRSTR_ADC12RST_Pos)

#define	RCC_AHBRSTR_ADC12RST RCC_AHBRSTR_ADC12RST_Msk

#define	RCC_AHBRSTR_ADC34RST_Pos (29U)

#define	RCC_AHBRSTR_ADC34RST_Msk (0x1UL << RCC_AHBRSTR_ADC34RST_Pos)

#define	RCC_AHBRSTR_ADC34RST RCC_AHBRSTR_ADC34RST_Msk

#define	RCC_CFGR2_PREDIV_Pos (0U)

#define	RCC_CFGR2_PREDIV_Msk (0xFUL << RCC_CFGR2_PREDIV_Pos)

#define	RCC_CFGR2_PREDIV RCC_CFGR2_PREDIV_Msk

#define	RCC_CFGR2_PREDIV_0 (0x1UL << RCC_CFGR2_PREDIV_Pos)

#define	RCC_CFGR2_PREDIV_1 (0x2UL << RCC_CFGR2_PREDIV_Pos)

#define	RCC_CFGR2_PREDIV_2 (0x4UL << RCC_CFGR2_PREDIV_Pos)

#define	RCC_CFGR2_PREDIV_3 (0x8UL << RCC_CFGR2_PREDIV_Pos)

#define	RCC_CFGR2_PREDIV_DIV1 (0x00000000U)

#define	RCC_CFGR2_PREDIV_DIV2 (0x00000001U)

#define	RCC_CFGR2_PREDIV_DIV3 (0x00000002U)

#define	RCC_CFGR2_PREDIV_DIV4 (0x00000003U)

#define	RCC_CFGR2_PREDIV_DIV5 (0x00000004U)

#define	RCC_CFGR2_PREDIV_DIV6 (0x00000005U)

#define	RCC_CFGR2_PREDIV_DIV7 (0x00000006U)

#define	RCC_CFGR2_PREDIV_DIV8 (0x00000007U)

#define	RCC_CFGR2_PREDIV_DIV9 (0x00000008U)

#define	RCC_CFGR2_PREDIV_DIV10 (0x00000009U)

#define	RCC_CFGR2_PREDIV_DIV11 (0x0000000AU)

#define	RCC_CFGR2_PREDIV_DIV12 (0x0000000BU)

#define	RCC_CFGR2_PREDIV_DIV13 (0x0000000CU)

#define	RCC_CFGR2_PREDIV_DIV14 (0x0000000DU)

#define	RCC_CFGR2_PREDIV_DIV15 (0x0000000EU)

#define	RCC_CFGR2_PREDIV_DIV16 (0x0000000FU)

#define	RCC_CFGR2_ADCPRE12_Pos (4U)

#define	RCC_CFGR2_ADCPRE12_Msk (0x1FUL << RCC_CFGR2_ADCPRE12_Pos)

#define	RCC_CFGR2_ADCPRE12 RCC_CFGR2_ADCPRE12_Msk

#define	RCC_CFGR2_ADCPRE12_0 (0x01UL << RCC_CFGR2_ADCPRE12_Pos)

#define	RCC_CFGR2_ADCPRE12_1 (0x02UL << RCC_CFGR2_ADCPRE12_Pos)

#define	RCC_CFGR2_ADCPRE12_2 (0x04UL << RCC_CFGR2_ADCPRE12_Pos)

#define	RCC_CFGR2_ADCPRE12_3 (0x08UL << RCC_CFGR2_ADCPRE12_Pos)

#define	RCC_CFGR2_ADCPRE12_4 (0x10UL << RCC_CFGR2_ADCPRE12_Pos)

#define	RCC_CFGR2_ADCPRE12_NO (0x00000000U)

#define	RCC_CFGR2_ADCPRE12_DIV1 (0x00000100U)

#define	RCC_CFGR2_ADCPRE12_DIV2 (0x00000110U)

#define	RCC_CFGR2_ADCPRE12_DIV4 (0x00000120U)

#define	RCC_CFGR2_ADCPRE12_DIV6 (0x00000130U)

#define	RCC_CFGR2_ADCPRE12_DIV8 (0x00000140U)

#define	RCC_CFGR2_ADCPRE12_DIV10 (0x00000150U)

#define	RCC_CFGR2_ADCPRE12_DIV12 (0x00000160U)

#define	RCC_CFGR2_ADCPRE12_DIV16 (0x00000170U)

#define	RCC_CFGR2_ADCPRE12_DIV32 (0x00000180U)

#define	RCC_CFGR2_ADCPRE12_DIV64 (0x00000190U)

#define	RCC_CFGR2_ADCPRE12_DIV128 (0x000001A0U)

#define	RCC_CFGR2_ADCPRE12_DIV256 (0x000001B0U)

#define	RCC_CFGR2_ADCPRE34_Pos (9U)

#define	RCC_CFGR2_ADCPRE34_Msk (0x1FUL << RCC_CFGR2_ADCPRE34_Pos)

#define	RCC_CFGR2_ADCPRE34 RCC_CFGR2_ADCPRE34_Msk

#define	RCC_CFGR2_ADCPRE34_0 (0x01UL << RCC_CFGR2_ADCPRE34_Pos)

#define	RCC_CFGR2_ADCPRE34_1 (0x02UL << RCC_CFGR2_ADCPRE34_Pos)

#define	RCC_CFGR2_ADCPRE34_2 (0x04UL << RCC_CFGR2_ADCPRE34_Pos)

#define	RCC_CFGR2_ADCPRE34_3 (0x08UL << RCC_CFGR2_ADCPRE34_Pos)

#define	RCC_CFGR2_ADCPRE34_4 (0x10UL << RCC_CFGR2_ADCPRE34_Pos)

#define	RCC_CFGR2_ADCPRE34_NO (0x00000000U)

#define	RCC_CFGR2_ADCPRE34_DIV1 (0x00002000U)

#define	RCC_CFGR2_ADCPRE34_DIV2 (0x00002200U)

#define	RCC_CFGR2_ADCPRE34_DIV4 (0x00002400U)

#define	RCC_CFGR2_ADCPRE34_DIV6 (0x00002600U)

#define	RCC_CFGR2_ADCPRE34_DIV8 (0x00002800U)

#define	RCC_CFGR2_ADCPRE34_DIV10 (0x00002A00U)

#define	RCC_CFGR2_ADCPRE34_DIV12 (0x00002C00U)

#define	RCC_CFGR2_ADCPRE34_DIV16 (0x00002E00U)

#define	RCC_CFGR2_ADCPRE34_DIV32 (0x00003000U)

#define	RCC_CFGR2_ADCPRE34_DIV64 (0x00003200U)

#define	RCC_CFGR2_ADCPRE34_DIV128 (0x00003400U)

#define	RCC_CFGR2_ADCPRE34_DIV256 (0x00003600U)

#define	RCC_CFGR3_USART1SW_Pos (0U)

#define	RCC_CFGR3_USART1SW_Msk (0x3UL << RCC_CFGR3_USART1SW_Pos)

#define	RCC_CFGR3_USART1SW RCC_CFGR3_USART1SW_Msk

#define	RCC_CFGR3_USART1SW_0 (0x1UL << RCC_CFGR3_USART1SW_Pos)

#define	RCC_CFGR3_USART1SW_1 (0x2UL << RCC_CFGR3_USART1SW_Pos)

#define	RCC_CFGR3_USART1SW_PCLK2 (0x00000000U)

#define	RCC_CFGR3_USART1SW_SYSCLK (0x00000001U)

#define	RCC_CFGR3_USART1SW_LSE (0x00000002U)

#define	RCC_CFGR3_USART1SW_HSI (0x00000003U)

#define	RCC_CFGR3_USART1SW_PCLK RCC_CFGR3_USART1SW_PCLK2

#define	RCC_CFGR3_I2CSW_Pos (4U)

#define	RCC_CFGR3_I2CSW_Msk (0x7UL << RCC_CFGR3_I2CSW_Pos)

#define	RCC_CFGR3_I2CSW RCC_CFGR3_I2CSW_Msk

#define	RCC_CFGR3_I2C1SW_Pos (4U)

#define	RCC_CFGR3_I2C1SW_Msk (0x1UL << RCC_CFGR3_I2C1SW_Pos)

#define	RCC_CFGR3_I2C1SW RCC_CFGR3_I2C1SW_Msk

#define	RCC_CFGR3_I2C2SW_Pos (5U)

#define	RCC_CFGR3_I2C2SW_Msk (0x1UL << RCC_CFGR3_I2C2SW_Pos)

#define	RCC_CFGR3_I2C2SW RCC_CFGR3_I2C2SW_Msk

#define	RCC_CFGR3_I2C3SW_Pos (6U)

#define	RCC_CFGR3_I2C3SW_Msk (0x1UL << RCC_CFGR3_I2C3SW_Pos)

#define	RCC_CFGR3_I2C3SW RCC_CFGR3_I2C3SW_Msk

#define	RCC_CFGR3_I2C1SW_HSI (0x00000000U)

#define	RCC_CFGR3_I2C1SW_SYSCLK_Pos (4U)

#define	RCC_CFGR3_I2C1SW_SYSCLK_Msk (0x1UL << RCC_CFGR3_I2C1SW_SYSCLK_Pos)

#define	RCC_CFGR3_I2C1SW_SYSCLK RCC_CFGR3_I2C1SW_SYSCLK_Msk

#define	RCC_CFGR3_I2C2SW_HSI (0x00000000U)

#define	RCC_CFGR3_I2C2SW_SYSCLK_Pos (5U)

#define	RCC_CFGR3_I2C2SW_SYSCLK_Msk (0x1UL << RCC_CFGR3_I2C2SW_SYSCLK_Pos)

#define	RCC_CFGR3_I2C2SW_SYSCLK RCC_CFGR3_I2C2SW_SYSCLK_Msk

#define	RCC_CFGR3_I2C3SW_HSI (0x00000000U)

#define	RCC_CFGR3_I2C3SW_SYSCLK_Pos (6U)

#define	RCC_CFGR3_I2C3SW_SYSCLK_Msk (0x1UL << RCC_CFGR3_I2C3SW_SYSCLK_Pos)

#define	RCC_CFGR3_I2C3SW_SYSCLK RCC_CFGR3_I2C3SW_SYSCLK_Msk

#define	RCC_CFGR3_TIMSW_Pos (8U)

#define	RCC_CFGR3_TIMSW_Msk (0xAFUL << RCC_CFGR3_TIMSW_Pos)

#define	RCC_CFGR3_TIMSW RCC_CFGR3_TIMSW_Msk

#define	RCC_CFGR3_TIM1SW_Pos (8U)

#define	RCC_CFGR3_TIM1SW_Msk (0x1UL << RCC_CFGR3_TIM1SW_Pos)

#define	RCC_CFGR3_TIM1SW RCC_CFGR3_TIM1SW_Msk

#define	RCC_CFGR3_TIM8SW_Pos (9U)

#define	RCC_CFGR3_TIM8SW_Msk (0x1UL << RCC_CFGR3_TIM8SW_Pos)

#define	RCC_CFGR3_TIM8SW RCC_CFGR3_TIM8SW_Msk

#define	RCC_CFGR3_TIM15SW_Pos (10U)

#define	RCC_CFGR3_TIM15SW_Msk (0x1UL << RCC_CFGR3_TIM15SW_Pos)

#define	RCC_CFGR3_TIM15SW RCC_CFGR3_TIM15SW_Msk

#define	RCC_CFGR3_TIM16SW_Pos (11U)

#define	RCC_CFGR3_TIM16SW_Msk (0x1UL << RCC_CFGR3_TIM16SW_Pos)

#define	RCC_CFGR3_TIM16SW RCC_CFGR3_TIM16SW_Msk

#define	RCC_CFGR3_TIM17SW_Pos (13U)

#define	RCC_CFGR3_TIM17SW_Msk (0x1UL << RCC_CFGR3_TIM17SW_Pos)

#define	RCC_CFGR3_TIM17SW RCC_CFGR3_TIM17SW_Msk

#define	RCC_CFGR3_TIM20SW_Pos (15U)

#define	RCC_CFGR3_TIM20SW_Msk (0x1UL << RCC_CFGR3_TIM20SW_Pos)

#define	RCC_CFGR3_TIM20SW RCC_CFGR3_TIM20SW_Msk

#define	RCC_CFGR3_TIM2SW_Pos (24U)

#define	RCC_CFGR3_TIM2SW_Msk (0x1UL << RCC_CFGR3_TIM2SW_Pos)

#define	RCC_CFGR3_TIM2SW RCC_CFGR3_TIM2SW_Msk

#define	RCC_CFGR3_TIM34SW_Pos (25U)

#define	RCC_CFGR3_TIM34SW_Msk (0x1UL << RCC_CFGR3_TIM34SW_Pos)

#define	RCC_CFGR3_TIM34SW RCC_CFGR3_TIM34SW_Msk

#define	RCC_CFGR3_TIM1SW_PCLK2 (0x00000000U)

#define	RCC_CFGR3_TIM1SW_PLL_Pos (8U)

#define	RCC_CFGR3_TIM1SW_PLL_Msk (0x1UL << RCC_CFGR3_TIM1SW_PLL_Pos)

#define	RCC_CFGR3_TIM1SW_PLL RCC_CFGR3_TIM1SW_PLL_Msk

#define	RCC_CFGR3_TIM8SW_PCLK2 (0x00000000U)

#define	RCC_CFGR3_TIM8SW_PLL_Pos (9U)

#define	RCC_CFGR3_TIM8SW_PLL_Msk (0x1UL << RCC_CFGR3_TIM8SW_PLL_Pos)

#define	RCC_CFGR3_TIM8SW_PLL RCC_CFGR3_TIM8SW_PLL_Msk

#define	RCC_CFGR3_TIM15SW_PCLK2 (0x00000000U)

#define	RCC_CFGR3_TIM15SW_PLL_Pos (10U)

#define	RCC_CFGR3_TIM15SW_PLL_Msk (0x1UL << RCC_CFGR3_TIM15SW_PLL_Pos)

#define	RCC_CFGR3_TIM15SW_PLL RCC_CFGR3_TIM15SW_PLL_Msk

#define	RCC_CFGR3_TIM16SW_PCLK2 (0x00000000U)

#define	RCC_CFGR3_TIM16SW_PLL_Pos (11U)

#define	RCC_CFGR3_TIM16SW_PLL_Msk (0x1UL << RCC_CFGR3_TIM16SW_PLL_Pos)

#define	RCC_CFGR3_TIM16SW_PLL RCC_CFGR3_TIM16SW_PLL_Msk

#define	RCC_CFGR3_TIM17SW_PCLK2 (0x00000000U)

#define	RCC_CFGR3_TIM17SW_PLL_Pos (13U)

#define	RCC_CFGR3_TIM17SW_PLL_Msk (0x1UL << RCC_CFGR3_TIM17SW_PLL_Pos)

#define	RCC_CFGR3_TIM17SW_PLL RCC_CFGR3_TIM17SW_PLL_Msk

#define	RCC_CFGR3_TIM20SW_PCLK2 (0x00000000U)

#define	RCC_CFGR3_TIM20SW_PLL_Pos (15U)

#define	RCC_CFGR3_TIM20SW_PLL_Msk (0x1UL << RCC_CFGR3_TIM20SW_PLL_Pos)

#define	RCC_CFGR3_TIM20SW_PLL RCC_CFGR3_TIM20SW_PLL_Msk

#define	RCC_CFGR3_USART2SW_Pos (16U)

#define	RCC_CFGR3_USART2SW_Msk (0x3UL << RCC_CFGR3_USART2SW_Pos)

#define	RCC_CFGR3_USART2SW RCC_CFGR3_USART2SW_Msk

#define	RCC_CFGR3_USART2SW_0 (0x1UL << RCC_CFGR3_USART2SW_Pos)

#define	RCC_CFGR3_USART2SW_1 (0x2UL << RCC_CFGR3_USART2SW_Pos)

#define	RCC_CFGR3_USART2SW_PCLK (0x00000000U)

#define	RCC_CFGR3_USART2SW_SYSCLK (0x00010000U)

#define	RCC_CFGR3_USART2SW_LSE (0x00020000U)

#define	RCC_CFGR3_USART2SW_HSI (0x00030000U)

#define	RCC_CFGR3_USART3SW_Pos (18U)

#define	RCC_CFGR3_USART3SW_Msk (0x3UL << RCC_CFGR3_USART3SW_Pos)

#define	RCC_CFGR3_USART3SW RCC_CFGR3_USART3SW_Msk

#define	RCC_CFGR3_USART3SW_0 (0x1UL << RCC_CFGR3_USART3SW_Pos)

#define	RCC_CFGR3_USART3SW_1 (0x2UL << RCC_CFGR3_USART3SW_Pos)

#define	RCC_CFGR3_USART3SW_PCLK (0x00000000U)

#define	RCC_CFGR3_USART3SW_SYSCLK (0x00040000U)

#define	RCC_CFGR3_USART3SW_LSE (0x00080000U)

#define	RCC_CFGR3_USART3SW_HSI (0x000C0000U)

#define	RCC_CFGR3_UART4SW_Pos (20U)

#define	RCC_CFGR3_UART4SW_Msk (0x3UL << RCC_CFGR3_UART4SW_Pos)

#define	RCC_CFGR3_UART4SW RCC_CFGR3_UART4SW_Msk

#define	RCC_CFGR3_UART4SW_0 (0x1UL << RCC_CFGR3_UART4SW_Pos)

#define	RCC_CFGR3_UART4SW_1 (0x2UL << RCC_CFGR3_UART4SW_Pos)

#define	RCC_CFGR3_UART4SW_PCLK (0x00000000U)

#define	RCC_CFGR3_UART4SW_SYSCLK (0x00100000U)

#define	RCC_CFGR3_UART4SW_LSE (0x00200000U)

#define	RCC_CFGR3_UART4SW_HSI (0x00300000U)

#define	RCC_CFGR3_UART5SW_Pos (22U)

#define	RCC_CFGR3_UART5SW_Msk (0x3UL << RCC_CFGR3_UART5SW_Pos)

#define	RCC_CFGR3_UART5SW RCC_CFGR3_UART5SW_Msk

#define	RCC_CFGR3_UART5SW_0 (0x1UL << RCC_CFGR3_UART5SW_Pos)

#define	RCC_CFGR3_UART5SW_1 (0x2UL << RCC_CFGR3_UART5SW_Pos)

#define	RCC_CFGR3_UART5SW_PCLK (0x00000000U)

#define	RCC_CFGR3_UART5SW_SYSCLK (0x00400000U)

#define	RCC_CFGR3_UART5SW_LSE (0x00800000U)

#define	RCC_CFGR3_UART5SW_HSI (0x00C00000U)

#define	RCC_CFGR3_TIM2SW_PCLK1 (0x00000000U)

#define	RCC_CFGR3_TIM2SW_PLL_Pos (24U)

#define	RCC_CFGR3_TIM2SW_PLL_Msk (0x1UL << RCC_CFGR3_TIM2SW_PLL_Pos)

#define	RCC_CFGR3_TIM2SW_PLL RCC_CFGR3_TIM2SW_PLL_Msk

#define	RCC_CFGR3_TIM34SW_PCLK1 (0x00000000U)

#define	RCC_CFGR3_TIM34SW_PLL_Pos (25U)

#define	RCC_CFGR3_TIM34SW_PLL_Msk (0x1UL << RCC_CFGR3_TIM34SW_PLL_Pos)

#define	RCC_CFGR3_TIM34SW_PLL RCC_CFGR3_TIM34SW_PLL_Msk

#define	RCC_CFGR3_TIM1SW_HCLK RCC_CFGR3_TIM1SW_PCLK2

#define	RCC_CFGR3_TIM8SW_HCLK RCC_CFGR3_TIM8SW_PCLK2

#define	RCC_CFGR3_TIM15SW_HCLK RCC_CFGR3_TIM15SW_PCLK2

#define	RCC_CFGR3_TIM16SW_HCLK RCC_CFGR3_TIM16SW_PCLK2

#define	RCC_CFGR3_TIM17SW_HCLK RCC_CFGR3_TIM17SW_PCLK2

#define	RCC_CFGR3_TIM20SW_HCLK RCC_CFGR3_TIM20SW_PCLK2

#define	RCC_CFGR3_TIM2SW_HCLK RCC_CFGR3_TIM2SW_PCLK1

#define	RCC_CFGR3_TIM34SW_HCLK RCC_CFGR3_TIM34SW_PCLK1

#define	RTC_TAMPER1_SUPPORT

#define	RTC_TAMPER2_SUPPORT

#define	RTC_TAMPER3_SUPPORT

#define	RTC_BACKUP_SUPPORT

#define	RTC_WAKEUP_SUPPORT

#define	RTC_TR_PM_Pos (22U)

#define	RTC_TR_PM_Msk (0x1UL << RTC_TR_PM_Pos)

#define	RTC_TR_PM RTC_TR_PM_Msk

#define	RTC_TR_HT_Pos (20U)

#define	RTC_TR_HT_Msk (0x3UL << RTC_TR_HT_Pos)

#define	RTC_TR_HT RTC_TR_HT_Msk

#define	RTC_TR_HT_0 (0x1UL << RTC_TR_HT_Pos)

#define	RTC_TR_HT_1 (0x2UL << RTC_TR_HT_Pos)

#define	RTC_TR_HU_Pos (16U)

#define	RTC_TR_HU_Msk (0xFUL << RTC_TR_HU_Pos)

#define	RTC_TR_HU RTC_TR_HU_Msk

#define	RTC_TR_HU_0 (0x1UL << RTC_TR_HU_Pos)

#define	RTC_TR_HU_1 (0x2UL << RTC_TR_HU_Pos)

#define	RTC_TR_HU_2 (0x4UL << RTC_TR_HU_Pos)

#define	RTC_TR_HU_3 (0x8UL << RTC_TR_HU_Pos)

#define	RTC_TR_MNT_Pos (12U)

#define	RTC_TR_MNT_Msk (0x7UL << RTC_TR_MNT_Pos)

#define	RTC_TR_MNT RTC_TR_MNT_Msk

#define	RTC_TR_MNT_0 (0x1UL << RTC_TR_MNT_Pos)

#define	RTC_TR_MNT_1 (0x2UL << RTC_TR_MNT_Pos)

#define	RTC_TR_MNT_2 (0x4UL << RTC_TR_MNT_Pos)

#define	RTC_TR_MNU_Pos (8U)

#define	RTC_TR_MNU_Msk (0xFUL << RTC_TR_MNU_Pos)

#define	RTC_TR_MNU RTC_TR_MNU_Msk

#define	RTC_TR_MNU_0 (0x1UL << RTC_TR_MNU_Pos)

#define	RTC_TR_MNU_1 (0x2UL << RTC_TR_MNU_Pos)

#define	RTC_TR_MNU_2 (0x4UL << RTC_TR_MNU_Pos)

#define	RTC_TR_MNU_3 (0x8UL << RTC_TR_MNU_Pos)

#define	RTC_TR_ST_Pos (4U)

#define	RTC_TR_ST_Msk (0x7UL << RTC_TR_ST_Pos)

#define	RTC_TR_ST RTC_TR_ST_Msk

#define	RTC_TR_ST_0 (0x1UL << RTC_TR_ST_Pos)

#define	RTC_TR_ST_1 (0x2UL << RTC_TR_ST_Pos)

#define	RTC_TR_ST_2 (0x4UL << RTC_TR_ST_Pos)

#define	RTC_TR_SU_Pos (0U)

#define	RTC_TR_SU_Msk (0xFUL << RTC_TR_SU_Pos)

#define	RTC_TR_SU RTC_TR_SU_Msk

#define	RTC_TR_SU_0 (0x1UL << RTC_TR_SU_Pos)

#define	RTC_TR_SU_1 (0x2UL << RTC_TR_SU_Pos)

#define	RTC_TR_SU_2 (0x4UL << RTC_TR_SU_Pos)

#define	RTC_TR_SU_3 (0x8UL << RTC_TR_SU_Pos)

#define	RTC_DR_YT_Pos (20U)

#define	RTC_DR_YT_Msk (0xFUL << RTC_DR_YT_Pos)

#define	RTC_DR_YT RTC_DR_YT_Msk

#define	RTC_DR_YT_0 (0x1UL << RTC_DR_YT_Pos)

#define	RTC_DR_YT_1 (0x2UL << RTC_DR_YT_Pos)

#define	RTC_DR_YT_2 (0x4UL << RTC_DR_YT_Pos)

#define	RTC_DR_YT_3 (0x8UL << RTC_DR_YT_Pos)

#define	RTC_DR_YU_Pos (16U)

#define	RTC_DR_YU_Msk (0xFUL << RTC_DR_YU_Pos)

#define	RTC_DR_YU RTC_DR_YU_Msk

#define	RTC_DR_YU_0 (0x1UL << RTC_DR_YU_Pos)

#define	RTC_DR_YU_1 (0x2UL << RTC_DR_YU_Pos)

#define	RTC_DR_YU_2 (0x4UL << RTC_DR_YU_Pos)

#define	RTC_DR_YU_3 (0x8UL << RTC_DR_YU_Pos)

#define	RTC_DR_WDU_Pos (13U)

#define	RTC_DR_WDU_Msk (0x7UL << RTC_DR_WDU_Pos)

#define	RTC_DR_WDU RTC_DR_WDU_Msk

#define	RTC_DR_WDU_0 (0x1UL << RTC_DR_WDU_Pos)

#define	RTC_DR_WDU_1 (0x2UL << RTC_DR_WDU_Pos)

#define	RTC_DR_WDU_2 (0x4UL << RTC_DR_WDU_Pos)

#define	RTC_DR_MT_Pos (12U)

#define	RTC_DR_MT_Msk (0x1UL << RTC_DR_MT_Pos)

#define	RTC_DR_MT RTC_DR_MT_Msk

#define	RTC_DR_MU_Pos (8U)

#define	RTC_DR_MU_Msk (0xFUL << RTC_DR_MU_Pos)

#define	RTC_DR_MU RTC_DR_MU_Msk

#define	RTC_DR_MU_0 (0x1UL << RTC_DR_MU_Pos)

#define	RTC_DR_MU_1 (0x2UL << RTC_DR_MU_Pos)

#define	RTC_DR_MU_2 (0x4UL << RTC_DR_MU_Pos)

#define	RTC_DR_MU_3 (0x8UL << RTC_DR_MU_Pos)

#define	RTC_DR_DT_Pos (4U)

#define	RTC_DR_DT_Msk (0x3UL << RTC_DR_DT_Pos)

#define	RTC_DR_DT RTC_DR_DT_Msk

#define	RTC_DR_DT_0 (0x1UL << RTC_DR_DT_Pos)

#define	RTC_DR_DT_1 (0x2UL << RTC_DR_DT_Pos)

#define	RTC_DR_DU_Pos (0U)

#define	RTC_DR_DU_Msk (0xFUL << RTC_DR_DU_Pos)

#define	RTC_DR_DU RTC_DR_DU_Msk

#define	RTC_DR_DU_0 (0x1UL << RTC_DR_DU_Pos)

#define	RTC_DR_DU_1 (0x2UL << RTC_DR_DU_Pos)

#define	RTC_DR_DU_2 (0x4UL << RTC_DR_DU_Pos)

#define	RTC_DR_DU_3 (0x8UL << RTC_DR_DU_Pos)

#define	RTC_CR_COE_Pos (23U)

#define	RTC_CR_COE_Msk (0x1UL << RTC_CR_COE_Pos)

#define	RTC_CR_COE RTC_CR_COE_Msk

#define	RTC_CR_OSEL_Pos (21U)

#define	RTC_CR_OSEL_Msk (0x3UL << RTC_CR_OSEL_Pos)

#define	RTC_CR_OSEL RTC_CR_OSEL_Msk

#define	RTC_CR_OSEL_0 (0x1UL << RTC_CR_OSEL_Pos)

#define	RTC_CR_OSEL_1 (0x2UL << RTC_CR_OSEL_Pos)

#define	RTC_CR_POL_Pos (20U)

#define	RTC_CR_POL_Msk (0x1UL << RTC_CR_POL_Pos)

#define	RTC_CR_POL RTC_CR_POL_Msk

#define	RTC_CR_COSEL_Pos (19U)

#define	RTC_CR_COSEL_Msk (0x1UL << RTC_CR_COSEL_Pos)

#define	RTC_CR_COSEL RTC_CR_COSEL_Msk

#define	RTC_CR_BKP_Pos (18U)

#define	RTC_CR_BKP_Msk (0x1UL << RTC_CR_BKP_Pos)

#define	RTC_CR_BKP RTC_CR_BKP_Msk

#define	RTC_CR_SUB1H_Pos (17U)

#define	RTC_CR_SUB1H_Msk (0x1UL << RTC_CR_SUB1H_Pos)

#define	RTC_CR_SUB1H RTC_CR_SUB1H_Msk

#define	RTC_CR_ADD1H_Pos (16U)

#define	RTC_CR_ADD1H_Msk (0x1UL << RTC_CR_ADD1H_Pos)

#define	RTC_CR_ADD1H RTC_CR_ADD1H_Msk

#define	RTC_CR_TSIE_Pos (15U)

#define	RTC_CR_TSIE_Msk (0x1UL << RTC_CR_TSIE_Pos)

#define	RTC_CR_TSIE RTC_CR_TSIE_Msk

#define	RTC_CR_WUTIE_Pos (14U)

#define	RTC_CR_WUTIE_Msk (0x1UL << RTC_CR_WUTIE_Pos)

#define	RTC_CR_WUTIE RTC_CR_WUTIE_Msk

#define	RTC_CR_ALRBIE_Pos (13U)

#define	RTC_CR_ALRBIE_Msk (0x1UL << RTC_CR_ALRBIE_Pos)

#define	RTC_CR_ALRBIE RTC_CR_ALRBIE_Msk

#define	RTC_CR_ALRAIE_Pos (12U)

#define	RTC_CR_ALRAIE_Msk (0x1UL << RTC_CR_ALRAIE_Pos)

#define	RTC_CR_ALRAIE RTC_CR_ALRAIE_Msk

#define	RTC_CR_TSE_Pos (11U)

#define	RTC_CR_TSE_Msk (0x1UL << RTC_CR_TSE_Pos)

#define	RTC_CR_TSE RTC_CR_TSE_Msk

#define	RTC_CR_WUTE_Pos (10U)

#define	RTC_CR_WUTE_Msk (0x1UL << RTC_CR_WUTE_Pos)

#define	RTC_CR_WUTE RTC_CR_WUTE_Msk

#define	RTC_CR_ALRBE_Pos (9U)

#define	RTC_CR_ALRBE_Msk (0x1UL << RTC_CR_ALRBE_Pos)

#define	RTC_CR_ALRBE RTC_CR_ALRBE_Msk

#define	RTC_CR_ALRAE_Pos (8U)

#define	RTC_CR_ALRAE_Msk (0x1UL << RTC_CR_ALRAE_Pos)

#define	RTC_CR_ALRAE RTC_CR_ALRAE_Msk

#define	RTC_CR_FMT_Pos (6U)

#define	RTC_CR_FMT_Msk (0x1UL << RTC_CR_FMT_Pos)

#define	RTC_CR_FMT RTC_CR_FMT_Msk

#define	RTC_CR_BYPSHAD_Pos (5U)

#define	RTC_CR_BYPSHAD_Msk (0x1UL << RTC_CR_BYPSHAD_Pos)

#define	RTC_CR_BYPSHAD RTC_CR_BYPSHAD_Msk

#define	RTC_CR_REFCKON_Pos (4U)

#define	RTC_CR_REFCKON_Msk (0x1UL << RTC_CR_REFCKON_Pos)

#define	RTC_CR_REFCKON RTC_CR_REFCKON_Msk

#define	RTC_CR_TSEDGE_Pos (3U)

#define	RTC_CR_TSEDGE_Msk (0x1UL << RTC_CR_TSEDGE_Pos)

#define	RTC_CR_TSEDGE RTC_CR_TSEDGE_Msk

#define	RTC_CR_WUCKSEL_Pos (0U)

#define	RTC_CR_WUCKSEL_Msk (0x7UL << RTC_CR_WUCKSEL_Pos)

#define	RTC_CR_WUCKSEL RTC_CR_WUCKSEL_Msk

#define	RTC_CR_WUCKSEL_0 (0x1UL << RTC_CR_WUCKSEL_Pos)

#define	RTC_CR_WUCKSEL_1 (0x2UL << RTC_CR_WUCKSEL_Pos)

#define	RTC_CR_WUCKSEL_2 (0x4UL << RTC_CR_WUCKSEL_Pos)

#define	RTC_CR_BCK_Pos RTC_CR_BKP_Pos

#define	RTC_CR_BCK_Msk RTC_CR_BKP_Msk

#define	RTC_CR_BCK RTC_CR_BKP

#define	RTC_ISR_RECALPF_Pos (16U)

#define	RTC_ISR_RECALPF_Msk (0x1UL << RTC_ISR_RECALPF_Pos)

#define	RTC_ISR_RECALPF RTC_ISR_RECALPF_Msk

#define	RTC_ISR_TAMP3F_Pos (15U)

#define	RTC_ISR_TAMP3F_Msk (0x1UL << RTC_ISR_TAMP3F_Pos)

#define	RTC_ISR_TAMP3F RTC_ISR_TAMP3F_Msk

#define	RTC_ISR_TAMP2F_Pos (14U)

#define	RTC_ISR_TAMP2F_Msk (0x1UL << RTC_ISR_TAMP2F_Pos)

#define	RTC_ISR_TAMP2F RTC_ISR_TAMP2F_Msk

#define	RTC_ISR_TAMP1F_Pos (13U)

#define	RTC_ISR_TAMP1F_Msk (0x1UL << RTC_ISR_TAMP1F_Pos)

#define	RTC_ISR_TAMP1F RTC_ISR_TAMP1F_Msk

#define	RTC_ISR_TSOVF_Pos (12U)

#define	RTC_ISR_TSOVF_Msk (0x1UL << RTC_ISR_TSOVF_Pos)

#define	RTC_ISR_TSOVF RTC_ISR_TSOVF_Msk

#define	RTC_ISR_TSF_Pos (11U)

#define	RTC_ISR_TSF_Msk (0x1UL << RTC_ISR_TSF_Pos)

#define	RTC_ISR_TSF RTC_ISR_TSF_Msk

#define	RTC_ISR_WUTF_Pos (10U)

#define	RTC_ISR_WUTF_Msk (0x1UL << RTC_ISR_WUTF_Pos)

#define	RTC_ISR_WUTF RTC_ISR_WUTF_Msk

#define	RTC_ISR_ALRBF_Pos (9U)

#define	RTC_ISR_ALRBF_Msk (0x1UL << RTC_ISR_ALRBF_Pos)

#define	RTC_ISR_ALRBF RTC_ISR_ALRBF_Msk

#define	RTC_ISR_ALRAF_Pos (8U)

#define	RTC_ISR_ALRAF_Msk (0x1UL << RTC_ISR_ALRAF_Pos)

#define	RTC_ISR_ALRAF RTC_ISR_ALRAF_Msk

#define	RTC_ISR_INIT_Pos (7U)

#define	RTC_ISR_INIT_Msk (0x1UL << RTC_ISR_INIT_Pos)

#define	RTC_ISR_INIT RTC_ISR_INIT_Msk

#define	RTC_ISR_INITF_Pos (6U)

#define	RTC_ISR_INITF_Msk (0x1UL << RTC_ISR_INITF_Pos)

#define	RTC_ISR_INITF RTC_ISR_INITF_Msk

#define	RTC_ISR_RSF_Pos (5U)

#define	RTC_ISR_RSF_Msk (0x1UL << RTC_ISR_RSF_Pos)

#define	RTC_ISR_RSF RTC_ISR_RSF_Msk

#define	RTC_ISR_INITS_Pos (4U)

#define	RTC_ISR_INITS_Msk (0x1UL << RTC_ISR_INITS_Pos)

#define	RTC_ISR_INITS RTC_ISR_INITS_Msk

#define	RTC_ISR_SHPF_Pos (3U)

#define	RTC_ISR_SHPF_Msk (0x1UL << RTC_ISR_SHPF_Pos)

#define	RTC_ISR_SHPF RTC_ISR_SHPF_Msk

#define	RTC_ISR_WUTWF_Pos (2U)

#define	RTC_ISR_WUTWF_Msk (0x1UL << RTC_ISR_WUTWF_Pos)

#define	RTC_ISR_WUTWF RTC_ISR_WUTWF_Msk

#define	RTC_ISR_ALRBWF_Pos (1U)

#define	RTC_ISR_ALRBWF_Msk (0x1UL << RTC_ISR_ALRBWF_Pos)

#define	RTC_ISR_ALRBWF RTC_ISR_ALRBWF_Msk

#define	RTC_ISR_ALRAWF_Pos (0U)

#define	RTC_ISR_ALRAWF_Msk (0x1UL << RTC_ISR_ALRAWF_Pos)

#define	RTC_ISR_ALRAWF RTC_ISR_ALRAWF_Msk

#define	RTC_PRER_PREDIV_A_Pos (16U)

#define	RTC_PRER_PREDIV_A_Msk (0x7FUL << RTC_PRER_PREDIV_A_Pos)

#define	RTC_PRER_PREDIV_A RTC_PRER_PREDIV_A_Msk

#define	RTC_PRER_PREDIV_S_Pos (0U)

#define	RTC_PRER_PREDIV_S_Msk (0x7FFFUL << RTC_PRER_PREDIV_S_Pos)

#define	RTC_PRER_PREDIV_S RTC_PRER_PREDIV_S_Msk

#define	RTC_WUTR_WUT_Pos (0U)

#define	RTC_WUTR_WUT_Msk (0xFFFFUL << RTC_WUTR_WUT_Pos)

#define	RTC_WUTR_WUT RTC_WUTR_WUT_Msk

#define	RTC_ALRMAR_MSK4_Pos (31U)

#define	RTC_ALRMAR_MSK4_Msk (0x1UL << RTC_ALRMAR_MSK4_Pos)

#define	RTC_ALRMAR_MSK4 RTC_ALRMAR_MSK4_Msk

#define	RTC_ALRMAR_WDSEL_Pos (30U)

#define	RTC_ALRMAR_WDSEL_Msk (0x1UL << RTC_ALRMAR_WDSEL_Pos)

#define	RTC_ALRMAR_WDSEL RTC_ALRMAR_WDSEL_Msk

#define	RTC_ALRMAR_DT_Pos (28U)

#define	RTC_ALRMAR_DT_Msk (0x3UL << RTC_ALRMAR_DT_Pos)

#define	RTC_ALRMAR_DT RTC_ALRMAR_DT_Msk

#define	RTC_ALRMAR_DT_0 (0x1UL << RTC_ALRMAR_DT_Pos)

#define	RTC_ALRMAR_DT_1 (0x2UL << RTC_ALRMAR_DT_Pos)

#define	RTC_ALRMAR_DU_Pos (24U)

#define	RTC_ALRMAR_DU_Msk (0xFUL << RTC_ALRMAR_DU_Pos)

#define	RTC_ALRMAR_DU RTC_ALRMAR_DU_Msk

#define	RTC_ALRMAR_DU_0 (0x1UL << RTC_ALRMAR_DU_Pos)

#define	RTC_ALRMAR_DU_1 (0x2UL << RTC_ALRMAR_DU_Pos)

#define	RTC_ALRMAR_DU_2 (0x4UL << RTC_ALRMAR_DU_Pos)

#define	RTC_ALRMAR_DU_3 (0x8UL << RTC_ALRMAR_DU_Pos)

#define	RTC_ALRMAR_MSK3_Pos (23U)

#define	RTC_ALRMAR_MSK3_Msk (0x1UL << RTC_ALRMAR_MSK3_Pos)

#define	RTC_ALRMAR_MSK3 RTC_ALRMAR_MSK3_Msk

#define	RTC_ALRMAR_PM_Pos (22U)

#define	RTC_ALRMAR_PM_Msk (0x1UL << RTC_ALRMAR_PM_Pos)

#define	RTC_ALRMAR_PM RTC_ALRMAR_PM_Msk

#define	RTC_ALRMAR_HT_Pos (20U)

#define	RTC_ALRMAR_HT_Msk (0x3UL << RTC_ALRMAR_HT_Pos)

#define	RTC_ALRMAR_HT RTC_ALRMAR_HT_Msk

#define	RTC_ALRMAR_HT_0 (0x1UL << RTC_ALRMAR_HT_Pos)

#define	RTC_ALRMAR_HT_1 (0x2UL << RTC_ALRMAR_HT_Pos)

#define	RTC_ALRMAR_HU_Pos (16U)

#define	RTC_ALRMAR_HU_Msk (0xFUL << RTC_ALRMAR_HU_Pos)

#define	RTC_ALRMAR_HU RTC_ALRMAR_HU_Msk

#define	RTC_ALRMAR_HU_0 (0x1UL << RTC_ALRMAR_HU_Pos)

#define	RTC_ALRMAR_HU_1 (0x2UL << RTC_ALRMAR_HU_Pos)

#define	RTC_ALRMAR_HU_2 (0x4UL << RTC_ALRMAR_HU_Pos)

#define	RTC_ALRMAR_HU_3 (0x8UL << RTC_ALRMAR_HU_Pos)

#define	RTC_ALRMAR_MSK2_Pos (15U)

#define	RTC_ALRMAR_MSK2_Msk (0x1UL << RTC_ALRMAR_MSK2_Pos)

#define	RTC_ALRMAR_MSK2 RTC_ALRMAR_MSK2_Msk

#define	RTC_ALRMAR_MNT_Pos (12U)

#define	RTC_ALRMAR_MNT_Msk (0x7UL << RTC_ALRMAR_MNT_Pos)

#define	RTC_ALRMAR_MNT RTC_ALRMAR_MNT_Msk

#define	RTC_ALRMAR_MNT_0 (0x1UL << RTC_ALRMAR_MNT_Pos)

#define	RTC_ALRMAR_MNT_1 (0x2UL << RTC_ALRMAR_MNT_Pos)

#define	RTC_ALRMAR_MNT_2 (0x4UL << RTC_ALRMAR_MNT_Pos)

#define	RTC_ALRMAR_MNU_Pos (8U)

#define	RTC_ALRMAR_MNU_Msk (0xFUL << RTC_ALRMAR_MNU_Pos)

#define	RTC_ALRMAR_MNU RTC_ALRMAR_MNU_Msk

#define	RTC_ALRMAR_MNU_0 (0x1UL << RTC_ALRMAR_MNU_Pos)

#define	RTC_ALRMAR_MNU_1 (0x2UL << RTC_ALRMAR_MNU_Pos)

#define	RTC_ALRMAR_MNU_2 (0x4UL << RTC_ALRMAR_MNU_Pos)

#define	RTC_ALRMAR_MNU_3 (0x8UL << RTC_ALRMAR_MNU_Pos)

#define	RTC_ALRMAR_MSK1_Pos (7U)

#define	RTC_ALRMAR_MSK1_Msk (0x1UL << RTC_ALRMAR_MSK1_Pos)

#define	RTC_ALRMAR_MSK1 RTC_ALRMAR_MSK1_Msk

#define	RTC_ALRMAR_ST_Pos (4U)

#define	RTC_ALRMAR_ST_Msk (0x7UL << RTC_ALRMAR_ST_Pos)

#define	RTC_ALRMAR_ST RTC_ALRMAR_ST_Msk

#define	RTC_ALRMAR_ST_0 (0x1UL << RTC_ALRMAR_ST_Pos)

#define	RTC_ALRMAR_ST_1 (0x2UL << RTC_ALRMAR_ST_Pos)

#define	RTC_ALRMAR_ST_2 (0x4UL << RTC_ALRMAR_ST_Pos)

#define	RTC_ALRMAR_SU_Pos (0U)

#define	RTC_ALRMAR_SU_Msk (0xFUL << RTC_ALRMAR_SU_Pos)

#define	RTC_ALRMAR_SU RTC_ALRMAR_SU_Msk

#define	RTC_ALRMAR_SU_0 (0x1UL << RTC_ALRMAR_SU_Pos)

#define	RTC_ALRMAR_SU_1 (0x2UL << RTC_ALRMAR_SU_Pos)

#define	RTC_ALRMAR_SU_2 (0x4UL << RTC_ALRMAR_SU_Pos)

#define	RTC_ALRMAR_SU_3 (0x8UL << RTC_ALRMAR_SU_Pos)

#define	RTC_ALRMBR_MSK4_Pos (31U)

#define	RTC_ALRMBR_MSK4_Msk (0x1UL << RTC_ALRMBR_MSK4_Pos)

#define	RTC_ALRMBR_MSK4 RTC_ALRMBR_MSK4_Msk

#define	RTC_ALRMBR_WDSEL_Pos (30U)

#define	RTC_ALRMBR_WDSEL_Msk (0x1UL << RTC_ALRMBR_WDSEL_Pos)

#define	RTC_ALRMBR_WDSEL RTC_ALRMBR_WDSEL_Msk

#define	RTC_ALRMBR_DT_Pos (28U)

#define	RTC_ALRMBR_DT_Msk (0x3UL << RTC_ALRMBR_DT_Pos)

#define	RTC_ALRMBR_DT RTC_ALRMBR_DT_Msk

#define	RTC_ALRMBR_DT_0 (0x1UL << RTC_ALRMBR_DT_Pos)

#define	RTC_ALRMBR_DT_1 (0x2UL << RTC_ALRMBR_DT_Pos)

#define	RTC_ALRMBR_DU_Pos (24U)

#define	RTC_ALRMBR_DU_Msk (0xFUL << RTC_ALRMBR_DU_Pos)

#define	RTC_ALRMBR_DU RTC_ALRMBR_DU_Msk

#define	RTC_ALRMBR_DU_0 (0x1UL << RTC_ALRMBR_DU_Pos)

#define	RTC_ALRMBR_DU_1 (0x2UL << RTC_ALRMBR_DU_Pos)

#define	RTC_ALRMBR_DU_2 (0x4UL << RTC_ALRMBR_DU_Pos)

#define	RTC_ALRMBR_DU_3 (0x8UL << RTC_ALRMBR_DU_Pos)

#define	RTC_ALRMBR_MSK3_Pos (23U)

#define	RTC_ALRMBR_MSK3_Msk (0x1UL << RTC_ALRMBR_MSK3_Pos)

#define	RTC_ALRMBR_MSK3 RTC_ALRMBR_MSK3_Msk

#define	RTC_ALRMBR_PM_Pos (22U)

#define	RTC_ALRMBR_PM_Msk (0x1UL << RTC_ALRMBR_PM_Pos)

#define	RTC_ALRMBR_PM RTC_ALRMBR_PM_Msk

#define	RTC_ALRMBR_HT_Pos (20U)

#define	RTC_ALRMBR_HT_Msk (0x3UL << RTC_ALRMBR_HT_Pos)

#define	RTC_ALRMBR_HT RTC_ALRMBR_HT_Msk

#define	RTC_ALRMBR_HT_0 (0x1UL << RTC_ALRMBR_HT_Pos)

#define	RTC_ALRMBR_HT_1 (0x2UL << RTC_ALRMBR_HT_Pos)

#define	RTC_ALRMBR_HU_Pos (16U)

#define	RTC_ALRMBR_HU_Msk (0xFUL << RTC_ALRMBR_HU_Pos)

#define	RTC_ALRMBR_HU RTC_ALRMBR_HU_Msk

#define	RTC_ALRMBR_HU_0 (0x1UL << RTC_ALRMBR_HU_Pos)

#define	RTC_ALRMBR_HU_1 (0x2UL << RTC_ALRMBR_HU_Pos)

#define	RTC_ALRMBR_HU_2 (0x4UL << RTC_ALRMBR_HU_Pos)

#define	RTC_ALRMBR_HU_3 (0x8UL << RTC_ALRMBR_HU_Pos)

#define	RTC_ALRMBR_MSK2_Pos (15U)

#define	RTC_ALRMBR_MSK2_Msk (0x1UL << RTC_ALRMBR_MSK2_Pos)

#define	RTC_ALRMBR_MSK2 RTC_ALRMBR_MSK2_Msk

#define	RTC_ALRMBR_MNT_Pos (12U)

#define	RTC_ALRMBR_MNT_Msk (0x7UL << RTC_ALRMBR_MNT_Pos)

#define	RTC_ALRMBR_MNT RTC_ALRMBR_MNT_Msk

#define	RTC_ALRMBR_MNT_0 (0x1UL << RTC_ALRMBR_MNT_Pos)

#define	RTC_ALRMBR_MNT_1 (0x2UL << RTC_ALRMBR_MNT_Pos)

#define	RTC_ALRMBR_MNT_2 (0x4UL << RTC_ALRMBR_MNT_Pos)

#define	RTC_ALRMBR_MNU_Pos (8U)

#define	RTC_ALRMBR_MNU_Msk (0xFUL << RTC_ALRMBR_MNU_Pos)

#define	RTC_ALRMBR_MNU RTC_ALRMBR_MNU_Msk

#define	RTC_ALRMBR_MNU_0 (0x1UL << RTC_ALRMBR_MNU_Pos)

#define	RTC_ALRMBR_MNU_1 (0x2UL << RTC_ALRMBR_MNU_Pos)

#define	RTC_ALRMBR_MNU_2 (0x4UL << RTC_ALRMBR_MNU_Pos)

#define	RTC_ALRMBR_MNU_3 (0x8UL << RTC_ALRMBR_MNU_Pos)

#define	RTC_ALRMBR_MSK1_Pos (7U)

#define	RTC_ALRMBR_MSK1_Msk (0x1UL << RTC_ALRMBR_MSK1_Pos)

#define	RTC_ALRMBR_MSK1 RTC_ALRMBR_MSK1_Msk

#define	RTC_ALRMBR_ST_Pos (4U)

#define	RTC_ALRMBR_ST_Msk (0x7UL << RTC_ALRMBR_ST_Pos)

#define	RTC_ALRMBR_ST RTC_ALRMBR_ST_Msk

#define	RTC_ALRMBR_ST_0 (0x1UL << RTC_ALRMBR_ST_Pos)

#define	RTC_ALRMBR_ST_1 (0x2UL << RTC_ALRMBR_ST_Pos)

#define	RTC_ALRMBR_ST_2 (0x4UL << RTC_ALRMBR_ST_Pos)

#define	RTC_ALRMBR_SU_Pos (0U)

#define	RTC_ALRMBR_SU_Msk (0xFUL << RTC_ALRMBR_SU_Pos)

#define	RTC_ALRMBR_SU RTC_ALRMBR_SU_Msk

#define	RTC_ALRMBR_SU_0 (0x1UL << RTC_ALRMBR_SU_Pos)

#define	RTC_ALRMBR_SU_1 (0x2UL << RTC_ALRMBR_SU_Pos)

#define	RTC_ALRMBR_SU_2 (0x4UL << RTC_ALRMBR_SU_Pos)

#define	RTC_ALRMBR_SU_3 (0x8UL << RTC_ALRMBR_SU_Pos)

#define	RTC_WPR_KEY_Pos (0U)

#define	RTC_WPR_KEY_Msk (0xFFUL << RTC_WPR_KEY_Pos)

#define	RTC_WPR_KEY RTC_WPR_KEY_Msk

#define	RTC_SSR_SS_Pos (0U)

#define	RTC_SSR_SS_Msk (0xFFFFUL << RTC_SSR_SS_Pos)

#define	RTC_SSR_SS RTC_SSR_SS_Msk

#define	RTC_SHIFTR_SUBFS_Pos (0U)

#define	RTC_SHIFTR_SUBFS_Msk (0x7FFFUL << RTC_SHIFTR_SUBFS_Pos)

#define	RTC_SHIFTR_SUBFS RTC_SHIFTR_SUBFS_Msk

#define	RTC_SHIFTR_ADD1S_Pos (31U)

#define	RTC_SHIFTR_ADD1S_Msk (0x1UL << RTC_SHIFTR_ADD1S_Pos)

#define	RTC_SHIFTR_ADD1S RTC_SHIFTR_ADD1S_Msk

#define	RTC_TSTR_PM_Pos (22U)

#define	RTC_TSTR_PM_Msk (0x1UL << RTC_TSTR_PM_Pos)

#define	RTC_TSTR_PM RTC_TSTR_PM_Msk

#define	RTC_TSTR_HT_Pos (20U)

#define	RTC_TSTR_HT_Msk (0x3UL << RTC_TSTR_HT_Pos)

#define	RTC_TSTR_HT RTC_TSTR_HT_Msk

#define	RTC_TSTR_HT_0 (0x1UL << RTC_TSTR_HT_Pos)

#define	RTC_TSTR_HT_1 (0x2UL << RTC_TSTR_HT_Pos)

#define	RTC_TSTR_HU_Pos (16U)

#define	RTC_TSTR_HU_Msk (0xFUL << RTC_TSTR_HU_Pos)

#define	RTC_TSTR_HU RTC_TSTR_HU_Msk

#define	RTC_TSTR_HU_0 (0x1UL << RTC_TSTR_HU_Pos)

#define	RTC_TSTR_HU_1 (0x2UL << RTC_TSTR_HU_Pos)

#define	RTC_TSTR_HU_2 (0x4UL << RTC_TSTR_HU_Pos)

#define	RTC_TSTR_HU_3 (0x8UL << RTC_TSTR_HU_Pos)

#define	RTC_TSTR_MNT_Pos (12U)

#define	RTC_TSTR_MNT_Msk (0x7UL << RTC_TSTR_MNT_Pos)

#define	RTC_TSTR_MNT RTC_TSTR_MNT_Msk

#define	RTC_TSTR_MNT_0 (0x1UL << RTC_TSTR_MNT_Pos)

#define	RTC_TSTR_MNT_1 (0x2UL << RTC_TSTR_MNT_Pos)

#define	RTC_TSTR_MNT_2 (0x4UL << RTC_TSTR_MNT_Pos)

#define	RTC_TSTR_MNU_Pos (8U)

#define	RTC_TSTR_MNU_Msk (0xFUL << RTC_TSTR_MNU_Pos)

#define	RTC_TSTR_MNU RTC_TSTR_MNU_Msk

#define	RTC_TSTR_MNU_0 (0x1UL << RTC_TSTR_MNU_Pos)

#define	RTC_TSTR_MNU_1 (0x2UL << RTC_TSTR_MNU_Pos)

#define	RTC_TSTR_MNU_2 (0x4UL << RTC_TSTR_MNU_Pos)

#define	RTC_TSTR_MNU_3 (0x8UL << RTC_TSTR_MNU_Pos)

#define	RTC_TSTR_ST_Pos (4U)

#define	RTC_TSTR_ST_Msk (0x7UL << RTC_TSTR_ST_Pos)

#define	RTC_TSTR_ST RTC_TSTR_ST_Msk

#define	RTC_TSTR_ST_0 (0x1UL << RTC_TSTR_ST_Pos)

#define	RTC_TSTR_ST_1 (0x2UL << RTC_TSTR_ST_Pos)

#define	RTC_TSTR_ST_2 (0x4UL << RTC_TSTR_ST_Pos)

#define	RTC_TSTR_SU_Pos (0U)

#define	RTC_TSTR_SU_Msk (0xFUL << RTC_TSTR_SU_Pos)

#define	RTC_TSTR_SU RTC_TSTR_SU_Msk

#define	RTC_TSTR_SU_0 (0x1UL << RTC_TSTR_SU_Pos)

#define	RTC_TSTR_SU_1 (0x2UL << RTC_TSTR_SU_Pos)

#define	RTC_TSTR_SU_2 (0x4UL << RTC_TSTR_SU_Pos)

#define	RTC_TSTR_SU_3 (0x8UL << RTC_TSTR_SU_Pos)

#define	RTC_TSDR_WDU_Pos (13U)

#define	RTC_TSDR_WDU_Msk (0x7UL << RTC_TSDR_WDU_Pos)

#define	RTC_TSDR_WDU RTC_TSDR_WDU_Msk

#define	RTC_TSDR_WDU_0 (0x1UL << RTC_TSDR_WDU_Pos)

#define	RTC_TSDR_WDU_1 (0x2UL << RTC_TSDR_WDU_Pos)

#define	RTC_TSDR_WDU_2 (0x4UL << RTC_TSDR_WDU_Pos)

#define	RTC_TSDR_MT_Pos (12U)

#define	RTC_TSDR_MT_Msk (0x1UL << RTC_TSDR_MT_Pos)

#define	RTC_TSDR_MT RTC_TSDR_MT_Msk

#define	RTC_TSDR_MU_Pos (8U)

#define	RTC_TSDR_MU_Msk (0xFUL << RTC_TSDR_MU_Pos)

#define	RTC_TSDR_MU RTC_TSDR_MU_Msk

#define	RTC_TSDR_MU_0 (0x1UL << RTC_TSDR_MU_Pos)

#define	RTC_TSDR_MU_1 (0x2UL << RTC_TSDR_MU_Pos)

#define	RTC_TSDR_MU_2 (0x4UL << RTC_TSDR_MU_Pos)

#define	RTC_TSDR_MU_3 (0x8UL << RTC_TSDR_MU_Pos)

#define	RTC_TSDR_DT_Pos (4U)

#define	RTC_TSDR_DT_Msk (0x3UL << RTC_TSDR_DT_Pos)

#define	RTC_TSDR_DT RTC_TSDR_DT_Msk

#define	RTC_TSDR_DT_0 (0x1UL << RTC_TSDR_DT_Pos)

#define	RTC_TSDR_DT_1 (0x2UL << RTC_TSDR_DT_Pos)

#define	RTC_TSDR_DU_Pos (0U)

#define	RTC_TSDR_DU_Msk (0xFUL << RTC_TSDR_DU_Pos)

#define	RTC_TSDR_DU RTC_TSDR_DU_Msk

#define	RTC_TSDR_DU_0 (0x1UL << RTC_TSDR_DU_Pos)

#define	RTC_TSDR_DU_1 (0x2UL << RTC_TSDR_DU_Pos)

#define	RTC_TSDR_DU_2 (0x4UL << RTC_TSDR_DU_Pos)

#define	RTC_TSDR_DU_3 (0x8UL << RTC_TSDR_DU_Pos)

#define	RTC_TSSSR_SS_Pos (0U)

#define	RTC_TSSSR_SS_Msk (0xFFFFUL << RTC_TSSSR_SS_Pos)

#define	RTC_TSSSR_SS RTC_TSSSR_SS_Msk

#define	RTC_CALR_CALP_Pos (15U)

#define	RTC_CALR_CALP_Msk (0x1UL << RTC_CALR_CALP_Pos)

#define	RTC_CALR_CALP RTC_CALR_CALP_Msk

#define	RTC_CALR_CALW8_Pos (14U)

#define	RTC_CALR_CALW8_Msk (0x1UL << RTC_CALR_CALW8_Pos)

#define	RTC_CALR_CALW8 RTC_CALR_CALW8_Msk

#define	RTC_CALR_CALW16_Pos (13U)

#define	RTC_CALR_CALW16_Msk (0x1UL << RTC_CALR_CALW16_Pos)

#define	RTC_CALR_CALW16 RTC_CALR_CALW16_Msk

#define	RTC_CALR_CALM_Pos (0U)

#define	RTC_CALR_CALM_Msk (0x1FFUL << RTC_CALR_CALM_Pos)

#define	RTC_CALR_CALM RTC_CALR_CALM_Msk

#define	RTC_CALR_CALM_0 (0x001UL << RTC_CALR_CALM_Pos)

#define	RTC_CALR_CALM_1 (0x002UL << RTC_CALR_CALM_Pos)

#define	RTC_CALR_CALM_2 (0x004UL << RTC_CALR_CALM_Pos)

#define	RTC_CALR_CALM_3 (0x008UL << RTC_CALR_CALM_Pos)

#define	RTC_CALR_CALM_4 (0x010UL << RTC_CALR_CALM_Pos)

#define	RTC_CALR_CALM_5 (0x020UL << RTC_CALR_CALM_Pos)

#define	RTC_CALR_CALM_6 (0x040UL << RTC_CALR_CALM_Pos)

#define	RTC_CALR_CALM_7 (0x080UL << RTC_CALR_CALM_Pos)

#define	RTC_CALR_CALM_8 (0x100UL << RTC_CALR_CALM_Pos)

#define	RTC_TAFCR_PC15MODE_Pos (23U)

#define	RTC_TAFCR_PC15MODE_Msk (0x1UL << RTC_TAFCR_PC15MODE_Pos)

#define	RTC_TAFCR_PC15MODE RTC_TAFCR_PC15MODE_Msk

#define	RTC_TAFCR_PC15VALUE_Pos (22U)

#define	RTC_TAFCR_PC15VALUE_Msk (0x1UL << RTC_TAFCR_PC15VALUE_Pos)

#define	RTC_TAFCR_PC15VALUE RTC_TAFCR_PC15VALUE_Msk

#define	RTC_TAFCR_PC14MODE_Pos (21U)

#define	RTC_TAFCR_PC14MODE_Msk (0x1UL << RTC_TAFCR_PC14MODE_Pos)

#define	RTC_TAFCR_PC14MODE RTC_TAFCR_PC14MODE_Msk

#define	RTC_TAFCR_PC14VALUE_Pos (20U)

#define	RTC_TAFCR_PC14VALUE_Msk (0x1UL << RTC_TAFCR_PC14VALUE_Pos)

#define	RTC_TAFCR_PC14VALUE RTC_TAFCR_PC14VALUE_Msk

#define	RTC_TAFCR_PC13MODE_Pos (19U)

#define	RTC_TAFCR_PC13MODE_Msk (0x1UL << RTC_TAFCR_PC13MODE_Pos)

#define	RTC_TAFCR_PC13MODE RTC_TAFCR_PC13MODE_Msk

#define	RTC_TAFCR_PC13VALUE_Pos (18U)

#define	RTC_TAFCR_PC13VALUE_Msk (0x1UL << RTC_TAFCR_PC13VALUE_Pos)

#define	RTC_TAFCR_PC13VALUE RTC_TAFCR_PC13VALUE_Msk

#define	RTC_TAFCR_TAMPPUDIS_Pos (15U)

#define	RTC_TAFCR_TAMPPUDIS_Msk (0x1UL << RTC_TAFCR_TAMPPUDIS_Pos)

#define	RTC_TAFCR_TAMPPUDIS RTC_TAFCR_TAMPPUDIS_Msk

#define	RTC_TAFCR_TAMPPRCH_Pos (13U)

#define	RTC_TAFCR_TAMPPRCH_Msk (0x3UL << RTC_TAFCR_TAMPPRCH_Pos)

#define	RTC_TAFCR_TAMPPRCH RTC_TAFCR_TAMPPRCH_Msk

#define	RTC_TAFCR_TAMPPRCH_0 (0x1UL << RTC_TAFCR_TAMPPRCH_Pos)

#define	RTC_TAFCR_TAMPPRCH_1 (0x2UL << RTC_TAFCR_TAMPPRCH_Pos)

#define	RTC_TAFCR_TAMPFLT_Pos (11U)

#define	RTC_TAFCR_TAMPFLT_Msk (0x3UL << RTC_TAFCR_TAMPFLT_Pos)

#define	RTC_TAFCR_TAMPFLT RTC_TAFCR_TAMPFLT_Msk

#define	RTC_TAFCR_TAMPFLT_0 (0x1UL << RTC_TAFCR_TAMPFLT_Pos)

#define	RTC_TAFCR_TAMPFLT_1 (0x2UL << RTC_TAFCR_TAMPFLT_Pos)

#define	RTC_TAFCR_TAMPFREQ_Pos (8U)

#define	RTC_TAFCR_TAMPFREQ_Msk (0x7UL << RTC_TAFCR_TAMPFREQ_Pos)

#define	RTC_TAFCR_TAMPFREQ RTC_TAFCR_TAMPFREQ_Msk

#define	RTC_TAFCR_TAMPFREQ_0 (0x1UL << RTC_TAFCR_TAMPFREQ_Pos)

#define	RTC_TAFCR_TAMPFREQ_1 (0x2UL << RTC_TAFCR_TAMPFREQ_Pos)

#define	RTC_TAFCR_TAMPFREQ_2 (0x4UL << RTC_TAFCR_TAMPFREQ_Pos)

#define	RTC_TAFCR_TAMPTS_Pos (7U)

#define	RTC_TAFCR_TAMPTS_Msk (0x1UL << RTC_TAFCR_TAMPTS_Pos)

#define	RTC_TAFCR_TAMPTS RTC_TAFCR_TAMPTS_Msk

#define	RTC_TAFCR_TAMP3TRG_Pos (6U)

#define	RTC_TAFCR_TAMP3TRG_Msk (0x1UL << RTC_TAFCR_TAMP3TRG_Pos)

#define	RTC_TAFCR_TAMP3TRG RTC_TAFCR_TAMP3TRG_Msk

#define	RTC_TAFCR_TAMP3E_Pos (5U)

#define	RTC_TAFCR_TAMP3E_Msk (0x1UL << RTC_TAFCR_TAMP3E_Pos)

#define	RTC_TAFCR_TAMP3E RTC_TAFCR_TAMP3E_Msk

#define	RTC_TAFCR_TAMP2TRG_Pos (4U)

#define	RTC_TAFCR_TAMP2TRG_Msk (0x1UL << RTC_TAFCR_TAMP2TRG_Pos)

#define	RTC_TAFCR_TAMP2TRG RTC_TAFCR_TAMP2TRG_Msk

#define	RTC_TAFCR_TAMP2E_Pos (3U)

#define	RTC_TAFCR_TAMP2E_Msk (0x1UL << RTC_TAFCR_TAMP2E_Pos)

#define	RTC_TAFCR_TAMP2E RTC_TAFCR_TAMP2E_Msk

#define	RTC_TAFCR_TAMPIE_Pos (2U)

#define	RTC_TAFCR_TAMPIE_Msk (0x1UL << RTC_TAFCR_TAMPIE_Pos)

#define	RTC_TAFCR_TAMPIE RTC_TAFCR_TAMPIE_Msk

#define	RTC_TAFCR_TAMP1TRG_Pos (1U)

#define	RTC_TAFCR_TAMP1TRG_Msk (0x1UL << RTC_TAFCR_TAMP1TRG_Pos)

#define	RTC_TAFCR_TAMP1TRG RTC_TAFCR_TAMP1TRG_Msk

#define	RTC_TAFCR_TAMP1E_Pos (0U)

#define	RTC_TAFCR_TAMP1E_Msk (0x1UL << RTC_TAFCR_TAMP1E_Pos)

#define	RTC_TAFCR_TAMP1E RTC_TAFCR_TAMP1E_Msk

#define	RTC_TAFCR_ALARMOUTTYPE RTC_TAFCR_PC13VALUE

#define	RTC_ALRMASSR_MASKSS_Pos (24U)

#define	RTC_ALRMASSR_MASKSS_Msk (0xFUL << RTC_ALRMASSR_MASKSS_Pos)

#define	RTC_ALRMASSR_MASKSS RTC_ALRMASSR_MASKSS_Msk

#define	RTC_ALRMASSR_MASKSS_0 (0x1UL << RTC_ALRMASSR_MASKSS_Pos)

#define	RTC_ALRMASSR_MASKSS_1 (0x2UL << RTC_ALRMASSR_MASKSS_Pos)

#define	RTC_ALRMASSR_MASKSS_2 (0x4UL << RTC_ALRMASSR_MASKSS_Pos)

#define	RTC_ALRMASSR_MASKSS_3 (0x8UL << RTC_ALRMASSR_MASKSS_Pos)

#define	RTC_ALRMASSR_SS_Pos (0U)

#define	RTC_ALRMASSR_SS_Msk (0x7FFFUL << RTC_ALRMASSR_SS_Pos)

#define	RTC_ALRMASSR_SS RTC_ALRMASSR_SS_Msk

#define	RTC_ALRMBSSR_MASKSS_Pos (24U)

#define	RTC_ALRMBSSR_MASKSS_Msk (0xFUL << RTC_ALRMBSSR_MASKSS_Pos)

#define	RTC_ALRMBSSR_MASKSS RTC_ALRMBSSR_MASKSS_Msk

#define	RTC_ALRMBSSR_MASKSS_0 (0x1UL << RTC_ALRMBSSR_MASKSS_Pos)

#define	RTC_ALRMBSSR_MASKSS_1 (0x2UL << RTC_ALRMBSSR_MASKSS_Pos)

#define	RTC_ALRMBSSR_MASKSS_2 (0x4UL << RTC_ALRMBSSR_MASKSS_Pos)

#define	RTC_ALRMBSSR_MASKSS_3 (0x8UL << RTC_ALRMBSSR_MASKSS_Pos)

#define	RTC_ALRMBSSR_SS_Pos (0U)

#define	RTC_ALRMBSSR_SS_Msk (0x7FFFUL << RTC_ALRMBSSR_SS_Pos)

#define	RTC_ALRMBSSR_SS RTC_ALRMBSSR_SS_Msk

#define	RTC_BKP0R_Pos (0U)

#define	RTC_BKP0R_Msk (0xFFFFFFFFUL << RTC_BKP0R_Pos)

#define	RTC_BKP0R RTC_BKP0R_Msk

#define	RTC_BKP1R_Pos (0U)

#define	RTC_BKP1R_Msk (0xFFFFFFFFUL << RTC_BKP1R_Pos)

#define	RTC_BKP1R RTC_BKP1R_Msk

#define	RTC_BKP2R_Pos (0U)

#define	RTC_BKP2R_Msk (0xFFFFFFFFUL << RTC_BKP2R_Pos)

#define	RTC_BKP2R RTC_BKP2R_Msk

#define	RTC_BKP3R_Pos (0U)

#define	RTC_BKP3R_Msk (0xFFFFFFFFUL << RTC_BKP3R_Pos)

#define	RTC_BKP3R RTC_BKP3R_Msk

#define	RTC_BKP4R_Pos (0U)

#define	RTC_BKP4R_Msk (0xFFFFFFFFUL << RTC_BKP4R_Pos)

#define	RTC_BKP4R RTC_BKP4R_Msk

#define	RTC_BKP5R_Pos (0U)

#define	RTC_BKP5R_Msk (0xFFFFFFFFUL << RTC_BKP5R_Pos)

#define	RTC_BKP5R RTC_BKP5R_Msk

#define	RTC_BKP6R_Pos (0U)

#define	RTC_BKP6R_Msk (0xFFFFFFFFUL << RTC_BKP6R_Pos)

#define	RTC_BKP6R RTC_BKP6R_Msk

#define	RTC_BKP7R_Pos (0U)

#define	RTC_BKP7R_Msk (0xFFFFFFFFUL << RTC_BKP7R_Pos)

#define	RTC_BKP7R RTC_BKP7R_Msk

#define	RTC_BKP8R_Pos (0U)

#define	RTC_BKP8R_Msk (0xFFFFFFFFUL << RTC_BKP8R_Pos)

#define	RTC_BKP8R RTC_BKP8R_Msk

#define	RTC_BKP9R_Pos (0U)

#define	RTC_BKP9R_Msk (0xFFFFFFFFUL << RTC_BKP9R_Pos)

#define	RTC_BKP9R RTC_BKP9R_Msk

#define	RTC_BKP10R_Pos (0U)

#define	RTC_BKP10R_Msk (0xFFFFFFFFUL << RTC_BKP10R_Pos)

#define	RTC_BKP10R RTC_BKP10R_Msk

#define	RTC_BKP11R_Pos (0U)

#define	RTC_BKP11R_Msk (0xFFFFFFFFUL << RTC_BKP11R_Pos)

#define	RTC_BKP11R RTC_BKP11R_Msk

#define	RTC_BKP12R_Pos (0U)

#define	RTC_BKP12R_Msk (0xFFFFFFFFUL << RTC_BKP12R_Pos)

#define	RTC_BKP12R RTC_BKP12R_Msk

#define	RTC_BKP13R_Pos (0U)

#define	RTC_BKP13R_Msk (0xFFFFFFFFUL << RTC_BKP13R_Pos)

#define	RTC_BKP13R RTC_BKP13R_Msk

#define	RTC_BKP14R_Pos (0U)

#define	RTC_BKP14R_Msk (0xFFFFFFFFUL << RTC_BKP14R_Pos)

#define	RTC_BKP14R RTC_BKP14R_Msk

#define	RTC_BKP15R_Pos (0U)

#define	RTC_BKP15R_Msk (0xFFFFFFFFUL << RTC_BKP15R_Pos)

#define	RTC_BKP15R RTC_BKP15R_Msk

#define	RTC_BKP_NUMBER 16

#define	SPI_I2S_SUPPORT

#define	SPI_I2S_FULLDUPLEX_SUPPORT

#define	SPI_CR1_CPHA_Pos (0U)

#define	SPI_CR1_CPHA_Msk (0x1UL << SPI_CR1_CPHA_Pos)

#define	SPI_CR1_CPHA SPI_CR1_CPHA_Msk

#define	SPI_CR1_CPOL_Pos (1U)

#define	SPI_CR1_CPOL_Msk (0x1UL << SPI_CR1_CPOL_Pos)

#define	SPI_CR1_CPOL SPI_CR1_CPOL_Msk

#define	SPI_CR1_MSTR_Pos (2U)

#define	SPI_CR1_MSTR_Msk (0x1UL << SPI_CR1_MSTR_Pos)

#define	SPI_CR1_MSTR SPI_CR1_MSTR_Msk

#define	SPI_CR1_BR_Pos (3U)

#define	SPI_CR1_BR_Msk (0x7UL << SPI_CR1_BR_Pos)

#define	SPI_CR1_BR SPI_CR1_BR_Msk

#define	SPI_CR1_BR_0 (0x1UL << SPI_CR1_BR_Pos)

#define	SPI_CR1_BR_1 (0x2UL << SPI_CR1_BR_Pos)

#define	SPI_CR1_BR_2 (0x4UL << SPI_CR1_BR_Pos)

#define	SPI_CR1_SPE_Pos (6U)

#define	SPI_CR1_SPE_Msk (0x1UL << SPI_CR1_SPE_Pos)

#define	SPI_CR1_SPE SPI_CR1_SPE_Msk

#define	SPI_CR1_LSBFIRST_Pos (7U)

#define	SPI_CR1_LSBFIRST_Msk (0x1UL << SPI_CR1_LSBFIRST_Pos)

#define	SPI_CR1_LSBFIRST SPI_CR1_LSBFIRST_Msk

#define	SPI_CR1_SSI_Pos (8U)

#define	SPI_CR1_SSI_Msk (0x1UL << SPI_CR1_SSI_Pos)

#define	SPI_CR1_SSI SPI_CR1_SSI_Msk

#define	SPI_CR1_SSM_Pos (9U)

#define	SPI_CR1_SSM_Msk (0x1UL << SPI_CR1_SSM_Pos)

#define	SPI_CR1_SSM SPI_CR1_SSM_Msk

#define	SPI_CR1_RXONLY_Pos (10U)

#define	SPI_CR1_RXONLY_Msk (0x1UL << SPI_CR1_RXONLY_Pos)

#define	SPI_CR1_RXONLY SPI_CR1_RXONLY_Msk

#define	SPI_CR1_CRCL_Pos (11U)

#define	SPI_CR1_CRCL_Msk (0x1UL << SPI_CR1_CRCL_Pos)

#define	SPI_CR1_CRCL SPI_CR1_CRCL_Msk

#define	SPI_CR1_CRCNEXT_Pos (12U)

#define	SPI_CR1_CRCNEXT_Msk (0x1UL << SPI_CR1_CRCNEXT_Pos)

#define	SPI_CR1_CRCNEXT SPI_CR1_CRCNEXT_Msk

#define	SPI_CR1_CRCEN_Pos (13U)

#define	SPI_CR1_CRCEN_Msk (0x1UL << SPI_CR1_CRCEN_Pos)

#define	SPI_CR1_CRCEN SPI_CR1_CRCEN_Msk

#define	SPI_CR1_BIDIOE_Pos (14U)

#define	SPI_CR1_BIDIOE_Msk (0x1UL << SPI_CR1_BIDIOE_Pos)

#define	SPI_CR1_BIDIOE SPI_CR1_BIDIOE_Msk

#define	SPI_CR1_BIDIMODE_Pos (15U)

#define	SPI_CR1_BIDIMODE_Msk (0x1UL << SPI_CR1_BIDIMODE_Pos)

#define	SPI_CR1_BIDIMODE SPI_CR1_BIDIMODE_Msk

#define	SPI_CR2_RXDMAEN_Pos (0U)

#define	SPI_CR2_RXDMAEN_Msk (0x1UL << SPI_CR2_RXDMAEN_Pos)

#define	SPI_CR2_RXDMAEN SPI_CR2_RXDMAEN_Msk

#define	SPI_CR2_TXDMAEN_Pos (1U)

#define	SPI_CR2_TXDMAEN_Msk (0x1UL << SPI_CR2_TXDMAEN_Pos)

#define	SPI_CR2_TXDMAEN SPI_CR2_TXDMAEN_Msk

#define	SPI_CR2_SSOE_Pos (2U)

#define	SPI_CR2_SSOE_Msk (0x1UL << SPI_CR2_SSOE_Pos)

#define	SPI_CR2_SSOE SPI_CR2_SSOE_Msk

#define	SPI_CR2_NSSP_Pos (3U)

#define	SPI_CR2_NSSP_Msk (0x1UL << SPI_CR2_NSSP_Pos)

#define	SPI_CR2_NSSP SPI_CR2_NSSP_Msk

#define	SPI_CR2_FRF_Pos (4U)

#define	SPI_CR2_FRF_Msk (0x1UL << SPI_CR2_FRF_Pos)

#define	SPI_CR2_FRF SPI_CR2_FRF_Msk

#define	SPI_CR2_ERRIE_Pos (5U)

#define	SPI_CR2_ERRIE_Msk (0x1UL << SPI_CR2_ERRIE_Pos)

#define	SPI_CR2_ERRIE SPI_CR2_ERRIE_Msk

#define	SPI_CR2_RXNEIE_Pos (6U)

#define	SPI_CR2_RXNEIE_Msk (0x1UL << SPI_CR2_RXNEIE_Pos)

#define	SPI_CR2_RXNEIE SPI_CR2_RXNEIE_Msk

#define	SPI_CR2_TXEIE_Pos (7U)

#define	SPI_CR2_TXEIE_Msk (0x1UL << SPI_CR2_TXEIE_Pos)

#define	SPI_CR2_TXEIE SPI_CR2_TXEIE_Msk

#define	SPI_CR2_DS_Pos (8U)

#define	SPI_CR2_DS_Msk (0xFUL << SPI_CR2_DS_Pos)

#define	SPI_CR2_DS SPI_CR2_DS_Msk

#define	SPI_CR2_DS_0 (0x1UL << SPI_CR2_DS_Pos)

#define	SPI_CR2_DS_1 (0x2UL << SPI_CR2_DS_Pos)

#define	SPI_CR2_DS_2 (0x4UL << SPI_CR2_DS_Pos)

#define	SPI_CR2_DS_3 (0x8UL << SPI_CR2_DS_Pos)

#define	SPI_CR2_FRXTH_Pos (12U)

#define	SPI_CR2_FRXTH_Msk (0x1UL << SPI_CR2_FRXTH_Pos)

#define	SPI_CR2_FRXTH SPI_CR2_FRXTH_Msk

#define	SPI_CR2_LDMARX_Pos (13U)

#define	SPI_CR2_LDMARX_Msk (0x1UL << SPI_CR2_LDMARX_Pos)

#define	SPI_CR2_LDMARX SPI_CR2_LDMARX_Msk

#define	SPI_CR2_LDMATX_Pos (14U)

#define	SPI_CR2_LDMATX_Msk (0x1UL << SPI_CR2_LDMATX_Pos)

#define	SPI_CR2_LDMATX SPI_CR2_LDMATX_Msk

#define	SPI_SR_RXNE_Pos (0U)

#define	SPI_SR_RXNE_Msk (0x1UL << SPI_SR_RXNE_Pos)

#define	SPI_SR_RXNE SPI_SR_RXNE_Msk

#define	SPI_SR_TXE_Pos (1U)

#define	SPI_SR_TXE_Msk (0x1UL << SPI_SR_TXE_Pos)

#define	SPI_SR_TXE SPI_SR_TXE_Msk

#define	SPI_SR_CHSIDE_Pos (2U)

#define	SPI_SR_CHSIDE_Msk (0x1UL << SPI_SR_CHSIDE_Pos)

#define	SPI_SR_CHSIDE SPI_SR_CHSIDE_Msk

#define	SPI_SR_UDR_Pos (3U)

#define	SPI_SR_UDR_Msk (0x1UL << SPI_SR_UDR_Pos)

#define	SPI_SR_UDR SPI_SR_UDR_Msk

#define	SPI_SR_CRCERR_Pos (4U)

#define	SPI_SR_CRCERR_Msk (0x1UL << SPI_SR_CRCERR_Pos)

#define	SPI_SR_CRCERR SPI_SR_CRCERR_Msk

#define	SPI_SR_MODF_Pos (5U)

#define	SPI_SR_MODF_Msk (0x1UL << SPI_SR_MODF_Pos)

#define	SPI_SR_MODF SPI_SR_MODF_Msk

#define	SPI_SR_OVR_Pos (6U)

#define	SPI_SR_OVR_Msk (0x1UL << SPI_SR_OVR_Pos)

#define	SPI_SR_OVR SPI_SR_OVR_Msk

#define	SPI_SR_BSY_Pos (7U)

#define	SPI_SR_BSY_Msk (0x1UL << SPI_SR_BSY_Pos)

#define	SPI_SR_BSY SPI_SR_BSY_Msk

#define	SPI_SR_FRE_Pos (8U)

#define	SPI_SR_FRE_Msk (0x1UL << SPI_SR_FRE_Pos)

#define	SPI_SR_FRE SPI_SR_FRE_Msk

#define	SPI_SR_FRLVL_Pos (9U)

#define	SPI_SR_FRLVL_Msk (0x3UL << SPI_SR_FRLVL_Pos)

#define	SPI_SR_FRLVL SPI_SR_FRLVL_Msk

#define	SPI_SR_FRLVL_0 (0x1UL << SPI_SR_FRLVL_Pos)

#define	SPI_SR_FRLVL_1 (0x2UL << SPI_SR_FRLVL_Pos)

#define	SPI_SR_FTLVL_Pos (11U)

#define	SPI_SR_FTLVL_Msk (0x3UL << SPI_SR_FTLVL_Pos)

#define	SPI_SR_FTLVL SPI_SR_FTLVL_Msk

#define	SPI_SR_FTLVL_0 (0x1UL << SPI_SR_FTLVL_Pos)

#define	SPI_SR_FTLVL_1 (0x2UL << SPI_SR_FTLVL_Pos)

#define	SPI_DR_DR_Pos (0U)

#define	SPI_DR_DR_Msk (0xFFFFUL << SPI_DR_DR_Pos)

#define	SPI_DR_DR SPI_DR_DR_Msk

#define	SPI_CRCPR_CRCPOLY_Pos (0U)

#define	SPI_CRCPR_CRCPOLY_Msk (0xFFFFUL << SPI_CRCPR_CRCPOLY_Pos)

#define	SPI_CRCPR_CRCPOLY SPI_CRCPR_CRCPOLY_Msk

#define	SPI_RXCRCR_RXCRC_Pos (0U)

#define	SPI_RXCRCR_RXCRC_Msk (0xFFFFUL << SPI_RXCRCR_RXCRC_Pos)

#define	SPI_RXCRCR_RXCRC SPI_RXCRCR_RXCRC_Msk

#define	SPI_TXCRCR_TXCRC_Pos (0U)

#define	SPI_TXCRCR_TXCRC_Msk (0xFFFFUL << SPI_TXCRCR_TXCRC_Pos)

#define	SPI_TXCRCR_TXCRC SPI_TXCRCR_TXCRC_Msk

#define	SPI_I2SCFGR_CHLEN_Pos (0U)

#define	SPI_I2SCFGR_CHLEN_Msk (0x1UL << SPI_I2SCFGR_CHLEN_Pos)

#define	SPI_I2SCFGR_CHLEN SPI_I2SCFGR_CHLEN_Msk

#define	SPI_I2SCFGR_DATLEN_Pos (1U)

#define	SPI_I2SCFGR_DATLEN_Msk (0x3UL << SPI_I2SCFGR_DATLEN_Pos)

#define	SPI_I2SCFGR_DATLEN SPI_I2SCFGR_DATLEN_Msk

#define	SPI_I2SCFGR_DATLEN_0 (0x1UL << SPI_I2SCFGR_DATLEN_Pos)

#define	SPI_I2SCFGR_DATLEN_1 (0x2UL << SPI_I2SCFGR_DATLEN_Pos)

#define	SPI_I2SCFGR_CKPOL_Pos (3U)

#define	SPI_I2SCFGR_CKPOL_Msk (0x1UL << SPI_I2SCFGR_CKPOL_Pos)

#define	SPI_I2SCFGR_CKPOL SPI_I2SCFGR_CKPOL_Msk

#define	SPI_I2SCFGR_I2SSTD_Pos (4U)

#define	SPI_I2SCFGR_I2SSTD_Msk (0x3UL << SPI_I2SCFGR_I2SSTD_Pos)

#define	SPI_I2SCFGR_I2SSTD SPI_I2SCFGR_I2SSTD_Msk

#define	SPI_I2SCFGR_I2SSTD_0 (0x1UL << SPI_I2SCFGR_I2SSTD_Pos)

#define	SPI_I2SCFGR_I2SSTD_1 (0x2UL << SPI_I2SCFGR_I2SSTD_Pos)

#define	SPI_I2SCFGR_PCMSYNC_Pos (7U)

#define	SPI_I2SCFGR_PCMSYNC_Msk (0x1UL << SPI_I2SCFGR_PCMSYNC_Pos)

#define	SPI_I2SCFGR_PCMSYNC SPI_I2SCFGR_PCMSYNC_Msk

#define	SPI_I2SCFGR_I2SCFG_Pos (8U)

#define	SPI_I2SCFGR_I2SCFG_Msk (0x3UL << SPI_I2SCFGR_I2SCFG_Pos)

#define	SPI_I2SCFGR_I2SCFG SPI_I2SCFGR_I2SCFG_Msk

#define	SPI_I2SCFGR_I2SCFG_0 (0x1UL << SPI_I2SCFGR_I2SCFG_Pos)

#define	SPI_I2SCFGR_I2SCFG_1 (0x2UL << SPI_I2SCFGR_I2SCFG_Pos)

#define	SPI_I2SCFGR_I2SE_Pos (10U)

#define	SPI_I2SCFGR_I2SE_Msk (0x1UL << SPI_I2SCFGR_I2SE_Pos)

#define	SPI_I2SCFGR_I2SE SPI_I2SCFGR_I2SE_Msk

#define	SPI_I2SCFGR_I2SMOD_Pos (11U)

#define	SPI_I2SCFGR_I2SMOD_Msk (0x1UL << SPI_I2SCFGR_I2SMOD_Pos)

#define	SPI_I2SCFGR_I2SMOD SPI_I2SCFGR_I2SMOD_Msk

#define	SPI_I2SPR_I2SDIV_Pos (0U)

#define	SPI_I2SPR_I2SDIV_Msk (0xFFUL << SPI_I2SPR_I2SDIV_Pos)

#define	SPI_I2SPR_I2SDIV SPI_I2SPR_I2SDIV_Msk

#define	SPI_I2SPR_ODD_Pos (8U)

#define	SPI_I2SPR_ODD_Msk (0x1UL << SPI_I2SPR_ODD_Pos)

#define	SPI_I2SPR_ODD SPI_I2SPR_ODD_Msk

#define	SPI_I2SPR_MCKOE_Pos (9U)

#define	SPI_I2SPR_MCKOE_Msk (0x1UL << SPI_I2SPR_MCKOE_Pos)

#define	SPI_I2SPR_MCKOE SPI_I2SPR_MCKOE_Msk

#define	SYSCFG_CFGR1_MEM_MODE_Pos (0U)

#define	SYSCFG_CFGR1_MEM_MODE_Msk (0x7UL << SYSCFG_CFGR1_MEM_MODE_Pos)

#define	SYSCFG_CFGR1_MEM_MODE SYSCFG_CFGR1_MEM_MODE_Msk

#define	SYSCFG_CFGR1_MEM_MODE_0 (0x00000001U)

#define	SYSCFG_CFGR1_MEM_MODE_1 (0x00000002U)

#define	SYSCFG_CFGR1_MEM_MODE_2 (0x00000004U)

#define	SYSCFG_CFGR1_USB_IT_RMP_Pos (5U)

#define	SYSCFG_CFGR1_USB_IT_RMP_Msk (0x1UL << SYSCFG_CFGR1_USB_IT_RMP_Pos)

#define	SYSCFG_CFGR1_USB_IT_RMP SYSCFG_CFGR1_USB_IT_RMP_Msk

#define	SYSCFG_CFGR1_TIM1_ITR3_RMP_Pos (6U)

#define	SYSCFG_CFGR1_TIM1_ITR3_RMP_Msk (0x1UL << SYSCFG_CFGR1_TIM1_ITR3_RMP_Pos)

#define	SYSCFG_CFGR1_TIM1_ITR3_RMP SYSCFG_CFGR1_TIM1_ITR3_RMP_Msk

#define	SYSCFG_CFGR1_DAC1_TRIG1_RMP_Pos (7U)

#define	SYSCFG_CFGR1_DAC1_TRIG1_RMP_Msk (0x1UL << SYSCFG_CFGR1_DAC1_TRIG1_RMP_Pos)

#define	SYSCFG_CFGR1_DAC1_TRIG1_RMP SYSCFG_CFGR1_DAC1_TRIG1_RMP_Msk

#define	SYSCFG_CFGR1_DMA_RMP_Pos (8U)

#define	SYSCFG_CFGR1_DMA_RMP_Msk (0x79UL << SYSCFG_CFGR1_DMA_RMP_Pos)

#define	SYSCFG_CFGR1_DMA_RMP SYSCFG_CFGR1_DMA_RMP_Msk

#define	SYSCFG_CFGR1_ADC24_DMA_RMP_Pos (8U)

#define	SYSCFG_CFGR1_ADC24_DMA_RMP_Msk (0x1UL << SYSCFG_CFGR1_ADC24_DMA_RMP_Pos)

#define	SYSCFG_CFGR1_ADC24_DMA_RMP SYSCFG_CFGR1_ADC24_DMA_RMP_Msk

#define	SYSCFG_CFGR1_TIM16_DMA_RMP_Pos (11U)

#define	SYSCFG_CFGR1_TIM16_DMA_RMP_Msk (0x1UL << SYSCFG_CFGR1_TIM16_DMA_RMP_Pos)

#define	SYSCFG_CFGR1_TIM16_DMA_RMP SYSCFG_CFGR1_TIM16_DMA_RMP_Msk

#define	SYSCFG_CFGR1_TIM17_DMA_RMP_Pos (12U)

#define	SYSCFG_CFGR1_TIM17_DMA_RMP_Msk (0x1UL << SYSCFG_CFGR1_TIM17_DMA_RMP_Pos)

#define	SYSCFG_CFGR1_TIM17_DMA_RMP SYSCFG_CFGR1_TIM17_DMA_RMP_Msk

#define	SYSCFG_CFGR1_TIM6DAC1Ch1_DMA_RMP_Pos (13U)

#define	SYSCFG_CFGR1_TIM6DAC1Ch1_DMA_RMP_Msk (0x1UL << SYSCFG_CFGR1_TIM6DAC1Ch1_DMA_RMP_Pos)

#define	SYSCFG_CFGR1_TIM6DAC1Ch1_DMA_RMP SYSCFG_CFGR1_TIM6DAC1Ch1_DMA_RMP_Msk

#define	SYSCFG_CFGR1_TIM7DAC1Ch2_DMA_RMP_Pos (14U)

#define	SYSCFG_CFGR1_TIM7DAC1Ch2_DMA_RMP_Msk (0x1UL << SYSCFG_CFGR1_TIM7DAC1Ch2_DMA_RMP_Pos)

#define	SYSCFG_CFGR1_TIM7DAC1Ch2_DMA_RMP SYSCFG_CFGR1_TIM7DAC1Ch2_DMA_RMP_Msk

#define	SYSCFG_CFGR1_I2C_PB6_FMP_Pos (16U)

#define	SYSCFG_CFGR1_I2C_PB6_FMP_Msk (0x1UL << SYSCFG_CFGR1_I2C_PB6_FMP_Pos)

#define	SYSCFG_CFGR1_I2C_PB6_FMP SYSCFG_CFGR1_I2C_PB6_FMP_Msk

#define	SYSCFG_CFGR1_I2C_PB7_FMP_Pos (17U)

#define	SYSCFG_CFGR1_I2C_PB7_FMP_Msk (0x1UL << SYSCFG_CFGR1_I2C_PB7_FMP_Pos)

#define	SYSCFG_CFGR1_I2C_PB7_FMP SYSCFG_CFGR1_I2C_PB7_FMP_Msk

#define	SYSCFG_CFGR1_I2C_PB8_FMP_Pos (18U)

#define	SYSCFG_CFGR1_I2C_PB8_FMP_Msk (0x1UL << SYSCFG_CFGR1_I2C_PB8_FMP_Pos)

#define	SYSCFG_CFGR1_I2C_PB8_FMP SYSCFG_CFGR1_I2C_PB8_FMP_Msk

#define	SYSCFG_CFGR1_I2C_PB9_FMP_Pos (19U)

#define	SYSCFG_CFGR1_I2C_PB9_FMP_Msk (0x1UL << SYSCFG_CFGR1_I2C_PB9_FMP_Pos)

#define	SYSCFG_CFGR1_I2C_PB9_FMP SYSCFG_CFGR1_I2C_PB9_FMP_Msk

#define	SYSCFG_CFGR1_I2C1_FMP_Pos (20U)

#define	SYSCFG_CFGR1_I2C1_FMP_Msk (0x1UL << SYSCFG_CFGR1_I2C1_FMP_Pos)

#define	SYSCFG_CFGR1_I2C1_FMP SYSCFG_CFGR1_I2C1_FMP_Msk

#define	SYSCFG_CFGR1_I2C2_FMP_Pos (21U)

#define	SYSCFG_CFGR1_I2C2_FMP_Msk (0x1UL << SYSCFG_CFGR1_I2C2_FMP_Pos)

#define	SYSCFG_CFGR1_I2C2_FMP SYSCFG_CFGR1_I2C2_FMP_Msk

#define	SYSCFG_CFGR1_ENCODER_MODE_Pos (22U)

#define	SYSCFG_CFGR1_ENCODER_MODE_Msk (0x3UL << SYSCFG_CFGR1_ENCODER_MODE_Pos)

#define	SYSCFG_CFGR1_ENCODER_MODE SYSCFG_CFGR1_ENCODER_MODE_Msk

#define	SYSCFG_CFGR1_ENCODER_MODE_0 (0x1UL << SYSCFG_CFGR1_ENCODER_MODE_Pos)

#define	SYSCFG_CFGR1_ENCODER_MODE_1 (0x2UL << SYSCFG_CFGR1_ENCODER_MODE_Pos)

#define	SYSCFG_CFGR1_ENCODER_MODE_TIM2_Pos (22U)

#define	SYSCFG_CFGR1_ENCODER_MODE_TIM2_Msk (0x1UL << SYSCFG_CFGR1_ENCODER_MODE_TIM2_Pos)

#define	SYSCFG_CFGR1_ENCODER_MODE_TIM2 SYSCFG_CFGR1_ENCODER_MODE_TIM2_Msk

#define	SYSCFG_CFGR1_ENCODER_MODE_TIM3_Pos (23U)

#define	SYSCFG_CFGR1_ENCODER_MODE_TIM3_Msk (0x1UL << SYSCFG_CFGR1_ENCODER_MODE_TIM3_Pos)

#define	SYSCFG_CFGR1_ENCODER_MODE_TIM3 SYSCFG_CFGR1_ENCODER_MODE_TIM3_Msk

#define	SYSCFG_CFGR1_I2C3_FMP_Pos (24U)

#define	SYSCFG_CFGR1_I2C3_FMP_Msk (0x1UL << SYSCFG_CFGR1_I2C3_FMP_Pos)

#define	SYSCFG_CFGR1_I2C3_FMP SYSCFG_CFGR1_I2C3_FMP_Msk

#define	SYSCFG_CFGR1_FPU_IE_Pos (26U)

#define	SYSCFG_CFGR1_FPU_IE_Msk (0x3FUL << SYSCFG_CFGR1_FPU_IE_Pos)

#define	SYSCFG_CFGR1_FPU_IE SYSCFG_CFGR1_FPU_IE_Msk

#define	SYSCFG_CFGR1_FPU_IE_0 (0x01UL << SYSCFG_CFGR1_FPU_IE_Pos)

#define	SYSCFG_CFGR1_FPU_IE_1 (0x02UL << SYSCFG_CFGR1_FPU_IE_Pos)

#define	SYSCFG_CFGR1_FPU_IE_2 (0x04UL << SYSCFG_CFGR1_FPU_IE_Pos)

#define	SYSCFG_CFGR1_FPU_IE_3 (0x08UL << SYSCFG_CFGR1_FPU_IE_Pos)

#define	SYSCFG_CFGR1_FPU_IE_4 (0x10UL << SYSCFG_CFGR1_FPU_IE_Pos)

#define	SYSCFG_CFGR1_FPU_IE_5 (0x20UL << SYSCFG_CFGR1_FPU_IE_Pos)

#define	SYSCFG_RCR_PAGE0_Pos (0U)

#define	SYSCFG_RCR_PAGE0_Msk (0x1UL << SYSCFG_RCR_PAGE0_Pos)

#define	SYSCFG_RCR_PAGE0 SYSCFG_RCR_PAGE0_Msk

#define	SYSCFG_RCR_PAGE1_Pos (1U)

#define	SYSCFG_RCR_PAGE1_Msk (0x1UL << SYSCFG_RCR_PAGE1_Pos)

#define	SYSCFG_RCR_PAGE1 SYSCFG_RCR_PAGE1_Msk

#define	SYSCFG_RCR_PAGE2_Pos (2U)

#define	SYSCFG_RCR_PAGE2_Msk (0x1UL << SYSCFG_RCR_PAGE2_Pos)

#define	SYSCFG_RCR_PAGE2 SYSCFG_RCR_PAGE2_Msk

#define	SYSCFG_RCR_PAGE3_Pos (3U)

#define	SYSCFG_RCR_PAGE3_Msk (0x1UL << SYSCFG_RCR_PAGE3_Pos)

#define	SYSCFG_RCR_PAGE3 SYSCFG_RCR_PAGE3_Msk

#define	SYSCFG_RCR_PAGE4_Pos (4U)

#define	SYSCFG_RCR_PAGE4_Msk (0x1UL << SYSCFG_RCR_PAGE4_Pos)

#define	SYSCFG_RCR_PAGE4 SYSCFG_RCR_PAGE4_Msk

#define	SYSCFG_RCR_PAGE5_Pos (5U)

#define	SYSCFG_RCR_PAGE5_Msk (0x1UL << SYSCFG_RCR_PAGE5_Pos)

#define	SYSCFG_RCR_PAGE5 SYSCFG_RCR_PAGE5_Msk

#define	SYSCFG_RCR_PAGE6_Pos (6U)

#define	SYSCFG_RCR_PAGE6_Msk (0x1UL << SYSCFG_RCR_PAGE6_Pos)

#define	SYSCFG_RCR_PAGE6 SYSCFG_RCR_PAGE6_Msk

#define	SYSCFG_RCR_PAGE7_Pos (7U)

#define	SYSCFG_RCR_PAGE7_Msk (0x1UL << SYSCFG_RCR_PAGE7_Pos)

#define	SYSCFG_RCR_PAGE7 SYSCFG_RCR_PAGE7_Msk

#define	SYSCFG_RCR_PAGE8_Pos (8U)

#define	SYSCFG_RCR_PAGE8_Msk (0x1UL << SYSCFG_RCR_PAGE8_Pos)

#define	SYSCFG_RCR_PAGE8 SYSCFG_RCR_PAGE8_Msk

#define	SYSCFG_RCR_PAGE9_Pos (9U)

#define	SYSCFG_RCR_PAGE9_Msk (0x1UL << SYSCFG_RCR_PAGE9_Pos)

#define	SYSCFG_RCR_PAGE9 SYSCFG_RCR_PAGE9_Msk

#define	SYSCFG_RCR_PAGE10_Pos (10U)

#define	SYSCFG_RCR_PAGE10_Msk (0x1UL << SYSCFG_RCR_PAGE10_Pos)

#define	SYSCFG_RCR_PAGE10 SYSCFG_RCR_PAGE10_Msk

#define	SYSCFG_RCR_PAGE11_Pos (11U)

#define	SYSCFG_RCR_PAGE11_Msk (0x1UL << SYSCFG_RCR_PAGE11_Pos)

#define	SYSCFG_RCR_PAGE11 SYSCFG_RCR_PAGE11_Msk

#define	SYSCFG_RCR_PAGE12_Pos (12U)

#define	SYSCFG_RCR_PAGE12_Msk (0x1UL << SYSCFG_RCR_PAGE12_Pos)

#define	SYSCFG_RCR_PAGE12 SYSCFG_RCR_PAGE12_Msk

#define	SYSCFG_RCR_PAGE13_Pos (13U)

#define	SYSCFG_RCR_PAGE13_Msk (0x1UL << SYSCFG_RCR_PAGE13_Pos)

#define	SYSCFG_RCR_PAGE13 SYSCFG_RCR_PAGE13_Msk

#define	SYSCFG_RCR_PAGE14_Pos (14U)

#define	SYSCFG_RCR_PAGE14_Msk (0x1UL << SYSCFG_RCR_PAGE14_Pos)

#define	SYSCFG_RCR_PAGE14 SYSCFG_RCR_PAGE14_Msk

#define	SYSCFG_RCR_PAGE15_Pos (15U)

#define	SYSCFG_RCR_PAGE15_Msk (0x1UL << SYSCFG_RCR_PAGE15_Pos)

#define	SYSCFG_RCR_PAGE15 SYSCFG_RCR_PAGE15_Msk

#define	SYSCFG_EXTICR1_EXTI0_Pos (0U)

#define	SYSCFG_EXTICR1_EXTI0_Msk (0xFUL << SYSCFG_EXTICR1_EXTI0_Pos)

#define	SYSCFG_EXTICR1_EXTI0 SYSCFG_EXTICR1_EXTI0_Msk

#define	SYSCFG_EXTICR1_EXTI1_Pos (4U)

#define	SYSCFG_EXTICR1_EXTI1_Msk (0xFUL << SYSCFG_EXTICR1_EXTI1_Pos)

#define	SYSCFG_EXTICR1_EXTI1 SYSCFG_EXTICR1_EXTI1_Msk

#define	SYSCFG_EXTICR1_EXTI2_Pos (8U)

#define	SYSCFG_EXTICR1_EXTI2_Msk (0xFUL << SYSCFG_EXTICR1_EXTI2_Pos)

#define	SYSCFG_EXTICR1_EXTI2 SYSCFG_EXTICR1_EXTI2_Msk

#define	SYSCFG_EXTICR1_EXTI3_Pos (12U)

#define	SYSCFG_EXTICR1_EXTI3_Msk (0xFUL << SYSCFG_EXTICR1_EXTI3_Pos)

#define	SYSCFG_EXTICR1_EXTI3 SYSCFG_EXTICR1_EXTI3_Msk
	EXTI0 configuration.

#define	SYSCFG_EXTICR1_EXTI0_PA (0x00000000U)

#define	SYSCFG_EXTICR1_EXTI0_PB (0x00000001U)

#define	SYSCFG_EXTICR1_EXTI0_PC (0x00000002U)

#define	SYSCFG_EXTICR1_EXTI0_PD (0x00000003U)

#define	SYSCFG_EXTICR1_EXTI0_PE (0x00000004U)

#define	SYSCFG_EXTICR1_EXTI0_PF (0x00000005U)

#define	SYSCFG_EXTICR1_EXTI0_PG (0x00000006U)

#define	SYSCFG_EXTICR1_EXTI0_PH (0x00000007U)
	EXTI1 configuration.

#define	SYSCFG_EXTICR1_EXTI1_PA (0x00000000U)

#define	SYSCFG_EXTICR1_EXTI1_PB (0x00000010U)

#define	SYSCFG_EXTICR1_EXTI1_PC (0x00000020U)

#define	SYSCFG_EXTICR1_EXTI1_PD (0x00000030U)

#define	SYSCFG_EXTICR1_EXTI1_PE (0x00000040U)

#define	SYSCFG_EXTICR1_EXTI1_PF (0x00000050U)

#define	SYSCFG_EXTICR1_EXTI1_PG (0x00000060U)

#define	SYSCFG_EXTICR1_EXTI1_PH (0x00000070U)
	EXTI2 configuration.

#define	SYSCFG_EXTICR1_EXTI2_PA (0x00000000U)

#define	SYSCFG_EXTICR1_EXTI2_PB (0x00000100U)

#define	SYSCFG_EXTICR1_EXTI2_PC (0x00000200U)

#define	SYSCFG_EXTICR1_EXTI2_PD (0x00000300U)

#define	SYSCFG_EXTICR1_EXTI2_PE (0x00000400U)

#define	SYSCFG_EXTICR1_EXTI2_PF (0x00000500U)

#define	SYSCFG_EXTICR1_EXTI2_PG (0x00000600U)
	EXTI3 configuration.

#define	SYSCFG_EXTICR1_EXTI3_PA (0x00000000U)

#define	SYSCFG_EXTICR1_EXTI3_PB (0x00001000U)

#define	SYSCFG_EXTICR1_EXTI3_PC (0x00002000U)

#define	SYSCFG_EXTICR1_EXTI3_PD (0x00003000U)

#define	SYSCFG_EXTICR1_EXTI3_PE (0x00004000U)

#define	SYSCFG_EXTICR1_EXTI3_PF (0x00005000U)

#define	SYSCFG_EXTICR1_EXTI3_PG (0x00006000U)

#define	SYSCFG_EXTICR2_EXTI4_Pos (0U)

#define	SYSCFG_EXTICR2_EXTI4_Msk (0xFUL << SYSCFG_EXTICR2_EXTI4_Pos)

#define	SYSCFG_EXTICR2_EXTI4 SYSCFG_EXTICR2_EXTI4_Msk

#define	SYSCFG_EXTICR2_EXTI5_Pos (4U)

#define	SYSCFG_EXTICR2_EXTI5_Msk (0xFUL << SYSCFG_EXTICR2_EXTI5_Pos)

#define	SYSCFG_EXTICR2_EXTI5 SYSCFG_EXTICR2_EXTI5_Msk

#define	SYSCFG_EXTICR2_EXTI6_Pos (8U)

#define	SYSCFG_EXTICR2_EXTI6_Msk (0xFUL << SYSCFG_EXTICR2_EXTI6_Pos)

#define	SYSCFG_EXTICR2_EXTI6 SYSCFG_EXTICR2_EXTI6_Msk

#define	SYSCFG_EXTICR2_EXTI7_Pos (12U)

#define	SYSCFG_EXTICR2_EXTI7_Msk (0xFUL << SYSCFG_EXTICR2_EXTI7_Pos)

#define	SYSCFG_EXTICR2_EXTI7 SYSCFG_EXTICR2_EXTI7_Msk
	EXTI4 configuration.

#define	SYSCFG_EXTICR2_EXTI4_PA (0x00000000U)

#define	SYSCFG_EXTICR2_EXTI4_PB (0x00000001U)

#define	SYSCFG_EXTICR2_EXTI4_PC (0x00000002U)

#define	SYSCFG_EXTICR2_EXTI4_PD (0x00000003U)

#define	SYSCFG_EXTICR2_EXTI4_PE (0x00000004U)

#define	SYSCFG_EXTICR2_EXTI4_PF (0x00000005U)

#define	SYSCFG_EXTICR2_EXTI4_PG (0x00000006U)

#define	SYSCFG_EXTICR2_EXTI4_PH (0x00000007U)
	EXTI5 configuration.

#define	SYSCFG_EXTICR2_EXTI5_PA (0x00000000U)

#define	SYSCFG_EXTICR2_EXTI5_PB (0x00000010U)

#define	SYSCFG_EXTICR2_EXTI5_PC (0x00000020U)

#define	SYSCFG_EXTICR2_EXTI5_PD (0x00000030U)

#define	SYSCFG_EXTICR2_EXTI5_PE (0x00000040U)

#define	SYSCFG_EXTICR2_EXTI5_PF (0x00000050U)

#define	SYSCFG_EXTICR2_EXTI5_PG (0x00000060U)
	EXTI6 configuration.

#define	SYSCFG_EXTICR2_EXTI6_PA (0x00000000U)

#define	SYSCFG_EXTICR2_EXTI6_PB (0x00000100U)

#define	SYSCFG_EXTICR2_EXTI6_PC (0x00000200U)

#define	SYSCFG_EXTICR2_EXTI6_PD (0x00000300U)

#define	SYSCFG_EXTICR2_EXTI6_PE (0x00000400U)

#define	SYSCFG_EXTICR2_EXTI6_PF (0x00000500U)

#define	SYSCFG_EXTICR2_EXTI6_PG (0x00000600U)
	EXTI7 configuration.

#define	SYSCFG_EXTICR2_EXTI7_PA (0x00000000U)

#define	SYSCFG_EXTICR2_EXTI7_PB (0x00001000U)

#define	SYSCFG_EXTICR2_EXTI7_PC (0x00002000U)

#define	SYSCFG_EXTICR2_EXTI7_PD (0x00003000U)

#define	SYSCFG_EXTICR2_EXTI7_PE (0x00004000U)

#define	SYSCFG_EXTICR2_EXTI7_PF (0x00005000U)

#define	SYSCFG_EXTICR2_EXTI7_PG (0x00006000U)

#define	SYSCFG_EXTICR3_EXTI8_Pos (0U)

#define	SYSCFG_EXTICR3_EXTI8_Msk (0xFUL << SYSCFG_EXTICR3_EXTI8_Pos)

#define	SYSCFG_EXTICR3_EXTI8 SYSCFG_EXTICR3_EXTI8_Msk

#define	SYSCFG_EXTICR3_EXTI9_Pos (4U)

#define	SYSCFG_EXTICR3_EXTI9_Msk (0xFUL << SYSCFG_EXTICR3_EXTI9_Pos)

#define	SYSCFG_EXTICR3_EXTI9 SYSCFG_EXTICR3_EXTI9_Msk

#define	SYSCFG_EXTICR3_EXTI10_Pos (8U)

#define	SYSCFG_EXTICR3_EXTI10_Msk (0xFUL << SYSCFG_EXTICR3_EXTI10_Pos)

#define	SYSCFG_EXTICR3_EXTI10 SYSCFG_EXTICR3_EXTI10_Msk

#define	SYSCFG_EXTICR3_EXTI11_Pos (12U)

#define	SYSCFG_EXTICR3_EXTI11_Msk (0xFUL << SYSCFG_EXTICR3_EXTI11_Pos)

#define	SYSCFG_EXTICR3_EXTI11 SYSCFG_EXTICR3_EXTI11_Msk
	EXTI8 configuration.

#define	SYSCFG_EXTICR3_EXTI8_PA (0x00000000U)

#define	SYSCFG_EXTICR3_EXTI8_PB (0x00000001U)

#define	SYSCFG_EXTICR3_EXTI8_PC (0x00000002U)

#define	SYSCFG_EXTICR3_EXTI8_PD (0x00000003U)

#define	SYSCFG_EXTICR3_EXTI8_PE (0x00000004U)

#define	SYSCFG_EXTICR3_EXTI8_PF (0x00000005U)

#define	SYSCFG_EXTICR3_EXTI8_PG (0x00000006U)
	EXTI9 configuration.

#define	SYSCFG_EXTICR3_EXTI9_PA (0x00000000U)

#define	SYSCFG_EXTICR3_EXTI9_PB (0x00000010U)

#define	SYSCFG_EXTICR3_EXTI9_PC (0x00000020U)

#define	SYSCFG_EXTICR3_EXTI9_PD (0x00000030U)

#define	SYSCFG_EXTICR3_EXTI9_PE (0x00000040U)

#define	SYSCFG_EXTICR3_EXTI9_PF (0x00000050U)

#define	SYSCFG_EXTICR3_EXTI9_PG (0x00000060U)
	EXTI10 configuration.

#define	SYSCFG_EXTICR3_EXTI10_PA (0x00000000U)

#define	SYSCFG_EXTICR3_EXTI10_PB (0x00000100U)

#define	SYSCFG_EXTICR3_EXTI10_PC (0x00000200U)

#define	SYSCFG_EXTICR3_EXTI10_PD (0x00000300U)

#define	SYSCFG_EXTICR3_EXTI10_PE (0x00000400U)

#define	SYSCFG_EXTICR3_EXTI10_PF (0x00000500U)

#define	SYSCFG_EXTICR3_EXTI10_PG (0x00000600U)
	EXTI11 configuration.

#define	SYSCFG_EXTICR3_EXTI11_PA (0x00000000U)

#define	SYSCFG_EXTICR3_EXTI11_PB (0x00001000U)

#define	SYSCFG_EXTICR3_EXTI11_PC (0x00002000U)

#define	SYSCFG_EXTICR3_EXTI11_PD (0x00003000U)

#define	SYSCFG_EXTICR3_EXTI11_PE (0x00004000U)

#define	SYSCFG_EXTICR3_EXTI11_PF (0x00005000U)

#define	SYSCFG_EXTICR3_EXTI11_PG (0x00006000U)

#define	SYSCFG_EXTICR4_EXTI12_Pos (0U)

#define	SYSCFG_EXTICR4_EXTI12_Msk (0xFUL << SYSCFG_EXTICR4_EXTI12_Pos)

#define	SYSCFG_EXTICR4_EXTI12 SYSCFG_EXTICR4_EXTI12_Msk

#define	SYSCFG_EXTICR4_EXTI13_Pos (4U)

#define	SYSCFG_EXTICR4_EXTI13_Msk (0xFUL << SYSCFG_EXTICR4_EXTI13_Pos)

#define	SYSCFG_EXTICR4_EXTI13 SYSCFG_EXTICR4_EXTI13_Msk

#define	SYSCFG_EXTICR4_EXTI14_Pos (8U)

#define	SYSCFG_EXTICR4_EXTI14_Msk (0xFUL << SYSCFG_EXTICR4_EXTI14_Pos)

#define	SYSCFG_EXTICR4_EXTI14 SYSCFG_EXTICR4_EXTI14_Msk

#define	SYSCFG_EXTICR4_EXTI15_Pos (12U)

#define	SYSCFG_EXTICR4_EXTI15_Msk (0xFUL << SYSCFG_EXTICR4_EXTI15_Pos)

#define	SYSCFG_EXTICR4_EXTI15 SYSCFG_EXTICR4_EXTI15_Msk
	EXTI12 configuration.

#define	SYSCFG_EXTICR4_EXTI12_PA (0x00000000U)

#define	SYSCFG_EXTICR4_EXTI12_PB (0x00000001U)

#define	SYSCFG_EXTICR4_EXTI12_PC (0x00000002U)

#define	SYSCFG_EXTICR4_EXTI12_PD (0x00000003U)

#define	SYSCFG_EXTICR4_EXTI12_PE (0x00000004U)

#define	SYSCFG_EXTICR4_EXTI12_PF (0x00000005U)

#define	SYSCFG_EXTICR4_EXTI12_PG (0x00000006U)
	EXTI13 configuration.

#define	SYSCFG_EXTICR4_EXTI13_PA (0x00000000U)

#define	SYSCFG_EXTICR4_EXTI13_PB (0x00000010U)

#define	SYSCFG_EXTICR4_EXTI13_PC (0x00000020U)

#define	SYSCFG_EXTICR4_EXTI13_PD (0x00000030U)

#define	SYSCFG_EXTICR4_EXTI13_PE (0x00000040U)

#define	SYSCFG_EXTICR4_EXTI13_PF (0x00000050U)

#define	SYSCFG_EXTICR4_EXTI13_PG (0x00000060U)
	EXTI14 configuration.

#define	SYSCFG_EXTICR4_EXTI14_PA (0x00000000U)

#define	SYSCFG_EXTICR4_EXTI14_PB (0x00000100U)

#define	SYSCFG_EXTICR4_EXTI14_PC (0x00000200U)

#define	SYSCFG_EXTICR4_EXTI14_PD (0x00000300U)

#define	SYSCFG_EXTICR4_EXTI14_PE (0x00000400U)

#define	SYSCFG_EXTICR4_EXTI14_PF (0x00000500U)

#define	SYSCFG_EXTICR4_EXTI14_PG (0x00000600U)
	EXTI15 configuration.

#define	SYSCFG_EXTICR4_EXTI15_PA (0x00000000U)

#define	SYSCFG_EXTICR4_EXTI15_PB (0x00001000U)

#define	SYSCFG_EXTICR4_EXTI15_PC (0x00002000U)

#define	SYSCFG_EXTICR4_EXTI15_PD (0x00003000U)

#define	SYSCFG_EXTICR4_EXTI15_PE (0x00004000U)

#define	SYSCFG_EXTICR4_EXTI15_PF (0x00005000U)

#define	SYSCFG_EXTICR4_EXTI15_PG (0x00006000U)

#define	SYSCFG_CFGR2_LOCKUP_LOCK_Pos (0U)

#define	SYSCFG_CFGR2_LOCKUP_LOCK_Msk (0x1UL << SYSCFG_CFGR2_LOCKUP_LOCK_Pos)

#define	SYSCFG_CFGR2_LOCKUP_LOCK SYSCFG_CFGR2_LOCKUP_LOCK_Msk

#define	SYSCFG_CFGR2_SRAM_PARITY_LOCK_Pos (1U)

#define	SYSCFG_CFGR2_SRAM_PARITY_LOCK_Msk (0x1UL << SYSCFG_CFGR2_SRAM_PARITY_LOCK_Pos)

#define	SYSCFG_CFGR2_SRAM_PARITY_LOCK SYSCFG_CFGR2_SRAM_PARITY_LOCK_Msk

#define	SYSCFG_CFGR2_PVD_LOCK_Pos (2U)

#define	SYSCFG_CFGR2_PVD_LOCK_Msk (0x1UL << SYSCFG_CFGR2_PVD_LOCK_Pos)

#define	SYSCFG_CFGR2_PVD_LOCK SYSCFG_CFGR2_PVD_LOCK_Msk

#define	SYSCFG_CFGR2_BYP_ADDR_PAR_Pos (4U)

#define	SYSCFG_CFGR2_BYP_ADDR_PAR_Msk (0x1UL << SYSCFG_CFGR2_BYP_ADDR_PAR_Pos)

#define	SYSCFG_CFGR2_BYP_ADDR_PAR SYSCFG_CFGR2_BYP_ADDR_PAR_Msk

#define	SYSCFG_CFGR2_SRAM_PE_Pos (8U)

#define	SYSCFG_CFGR2_SRAM_PE_Msk (0x1UL << SYSCFG_CFGR2_SRAM_PE_Pos)

#define	SYSCFG_CFGR2_SRAM_PE SYSCFG_CFGR2_SRAM_PE_Msk

#define	SYSCFG_CFGR4_ADC12_EXT2_RMP_Pos (0U)

#define	SYSCFG_CFGR4_ADC12_EXT2_RMP_Msk (0x1UL << SYSCFG_CFGR4_ADC12_EXT2_RMP_Pos)

#define	SYSCFG_CFGR4_ADC12_EXT2_RMP SYSCFG_CFGR4_ADC12_EXT2_RMP_Msk

#define	SYSCFG_CFGR4_ADC12_EXT3_RMP_Pos (1U)

#define	SYSCFG_CFGR4_ADC12_EXT3_RMP_Msk (0x1UL << SYSCFG_CFGR4_ADC12_EXT3_RMP_Pos)

#define	SYSCFG_CFGR4_ADC12_EXT3_RMP SYSCFG_CFGR4_ADC12_EXT3_RMP_Msk

#define	SYSCFG_CFGR4_ADC12_EXT5_RMP_Pos (2U)

#define	SYSCFG_CFGR4_ADC12_EXT5_RMP_Msk (0x1UL << SYSCFG_CFGR4_ADC12_EXT5_RMP_Pos)

#define	SYSCFG_CFGR4_ADC12_EXT5_RMP SYSCFG_CFGR4_ADC12_EXT5_RMP_Msk

#define	SYSCFG_CFGR4_ADC12_EXT13_RMP_Pos (3U)

#define	SYSCFG_CFGR4_ADC12_EXT13_RMP_Msk (0x1UL << SYSCFG_CFGR4_ADC12_EXT13_RMP_Pos)

#define	SYSCFG_CFGR4_ADC12_EXT13_RMP SYSCFG_CFGR4_ADC12_EXT13_RMP_Msk

#define	SYSCFG_CFGR4_ADC12_EXT15_RMP_Pos (4U)

#define	SYSCFG_CFGR4_ADC12_EXT15_RMP_Msk (0x1UL << SYSCFG_CFGR4_ADC12_EXT15_RMP_Pos)

#define	SYSCFG_CFGR4_ADC12_EXT15_RMP SYSCFG_CFGR4_ADC12_EXT15_RMP_Msk

#define	SYSCFG_CFGR4_ADC12_JEXT3_RMP_Pos (5U)

#define	SYSCFG_CFGR4_ADC12_JEXT3_RMP_Msk (0x1UL << SYSCFG_CFGR4_ADC12_JEXT3_RMP_Pos)

#define	SYSCFG_CFGR4_ADC12_JEXT3_RMP SYSCFG_CFGR4_ADC12_JEXT3_RMP_Msk

#define	SYSCFG_CFGR4_ADC12_JEXT6_RMP_Pos (6U)

#define	SYSCFG_CFGR4_ADC12_JEXT6_RMP_Msk (0x1UL << SYSCFG_CFGR4_ADC12_JEXT6_RMP_Pos)

#define	SYSCFG_CFGR4_ADC12_JEXT6_RMP SYSCFG_CFGR4_ADC12_JEXT6_RMP_Msk

#define	SYSCFG_CFGR4_ADC12_JEXT13_RMP_Pos (7U)

#define	SYSCFG_CFGR4_ADC12_JEXT13_RMP_Msk (0x1UL << SYSCFG_CFGR4_ADC12_JEXT13_RMP_Pos)

#define	SYSCFG_CFGR4_ADC12_JEXT13_RMP SYSCFG_CFGR4_ADC12_JEXT13_RMP_Msk

#define	SYSCFG_CFGR4_ADC34_EXT5_RMP_Pos (8U)

#define	SYSCFG_CFGR4_ADC34_EXT5_RMP_Msk (0x1UL << SYSCFG_CFGR4_ADC34_EXT5_RMP_Pos)

#define	SYSCFG_CFGR4_ADC34_EXT5_RMP SYSCFG_CFGR4_ADC34_EXT5_RMP_Msk

#define	SYSCFG_CFGR4_ADC34_EXT6_RMP_Pos (9U)

#define	SYSCFG_CFGR4_ADC34_EXT6_RMP_Msk (0x1UL << SYSCFG_CFGR4_ADC34_EXT6_RMP_Pos)

#define	SYSCFG_CFGR4_ADC34_EXT6_RMP SYSCFG_CFGR4_ADC34_EXT6_RMP_Msk

#define	SYSCFG_CFGR4_ADC34_EXT15_RMP_Pos (10U)

#define	SYSCFG_CFGR4_ADC34_EXT15_RMP_Msk (0x1UL << SYSCFG_CFGR4_ADC34_EXT15_RMP_Pos)

#define	SYSCFG_CFGR4_ADC34_EXT15_RMP SYSCFG_CFGR4_ADC34_EXT15_RMP_Msk

#define	SYSCFG_CFGR4_ADC34_JEXT5_RMP_Pos (11U)

#define	SYSCFG_CFGR4_ADC34_JEXT5_RMP_Msk (0x1UL << SYSCFG_CFGR4_ADC34_JEXT5_RMP_Pos)

#define	SYSCFG_CFGR4_ADC34_JEXT5_RMP SYSCFG_CFGR4_ADC34_JEXT5_RMP_Msk

#define	SYSCFG_CFGR4_ADC34_JEXT11_RMP_Pos (12U)

#define	SYSCFG_CFGR4_ADC34_JEXT11_RMP_Msk (0x1UL << SYSCFG_CFGR4_ADC34_JEXT11_RMP_Pos)

#define	SYSCFG_CFGR4_ADC34_JEXT11_RMP SYSCFG_CFGR4_ADC34_JEXT11_RMP_Msk

#define	SYSCFG_CFGR4_ADC34_JEXT14_RMP_Pos (13U)

#define	SYSCFG_CFGR4_ADC34_JEXT14_RMP_Msk (0x1UL << SYSCFG_CFGR4_ADC34_JEXT14_RMP_Pos)

#define	SYSCFG_CFGR4_ADC34_JEXT14_RMP SYSCFG_CFGR4_ADC34_JEXT14_RMP_Msk

#define	TIM_CR1_CEN_Pos (0U)

#define	TIM_CR1_CEN_Msk (0x1UL << TIM_CR1_CEN_Pos)

#define	TIM_CR1_CEN TIM_CR1_CEN_Msk

#define	TIM_CR1_UDIS_Pos (1U)

#define	TIM_CR1_UDIS_Msk (0x1UL << TIM_CR1_UDIS_Pos)

#define	TIM_CR1_UDIS TIM_CR1_UDIS_Msk

#define	TIM_CR1_URS_Pos (2U)

#define	TIM_CR1_URS_Msk (0x1UL << TIM_CR1_URS_Pos)

#define	TIM_CR1_URS TIM_CR1_URS_Msk

#define	TIM_CR1_OPM_Pos (3U)

#define	TIM_CR1_OPM_Msk (0x1UL << TIM_CR1_OPM_Pos)

#define	TIM_CR1_OPM TIM_CR1_OPM_Msk

#define	TIM_CR1_DIR_Pos (4U)

#define	TIM_CR1_DIR_Msk (0x1UL << TIM_CR1_DIR_Pos)

#define	TIM_CR1_DIR TIM_CR1_DIR_Msk

#define	TIM_CR1_CMS_Pos (5U)

#define	TIM_CR1_CMS_Msk (0x3UL << TIM_CR1_CMS_Pos)

#define	TIM_CR1_CMS TIM_CR1_CMS_Msk

#define	TIM_CR1_CMS_0 (0x1UL << TIM_CR1_CMS_Pos)

#define	TIM_CR1_CMS_1 (0x2UL << TIM_CR1_CMS_Pos)

#define	TIM_CR1_ARPE_Pos (7U)

#define	TIM_CR1_ARPE_Msk (0x1UL << TIM_CR1_ARPE_Pos)

#define	TIM_CR1_ARPE TIM_CR1_ARPE_Msk

#define	TIM_CR1_CKD_Pos (8U)

#define	TIM_CR1_CKD_Msk (0x3UL << TIM_CR1_CKD_Pos)

#define	TIM_CR1_CKD TIM_CR1_CKD_Msk

#define	TIM_CR1_CKD_0 (0x1UL << TIM_CR1_CKD_Pos)

#define	TIM_CR1_CKD_1 (0x2UL << TIM_CR1_CKD_Pos)

#define	TIM_CR1_UIFREMAP_Pos (11U)

#define	TIM_CR1_UIFREMAP_Msk (0x1UL << TIM_CR1_UIFREMAP_Pos)

#define	TIM_CR1_UIFREMAP TIM_CR1_UIFREMAP_Msk

#define	TIM_CR2_CCPC_Pos (0U)

#define	TIM_CR2_CCPC_Msk (0x1UL << TIM_CR2_CCPC_Pos)

#define	TIM_CR2_CCPC TIM_CR2_CCPC_Msk

#define	TIM_CR2_CCUS_Pos (2U)

#define	TIM_CR2_CCUS_Msk (0x1UL << TIM_CR2_CCUS_Pos)

#define	TIM_CR2_CCUS TIM_CR2_CCUS_Msk

#define	TIM_CR2_CCDS_Pos (3U)

#define	TIM_CR2_CCDS_Msk (0x1UL << TIM_CR2_CCDS_Pos)

#define	TIM_CR2_CCDS TIM_CR2_CCDS_Msk

#define	TIM_CR2_MMS_Pos (4U)

#define	TIM_CR2_MMS_Msk (0x7UL << TIM_CR2_MMS_Pos)

#define	TIM_CR2_MMS TIM_CR2_MMS_Msk

#define	TIM_CR2_MMS_0 (0x1UL << TIM_CR2_MMS_Pos)

#define	TIM_CR2_MMS_1 (0x2UL << TIM_CR2_MMS_Pos)

#define	TIM_CR2_MMS_2 (0x4UL << TIM_CR2_MMS_Pos)

#define	TIM_CR2_TI1S_Pos (7U)

#define	TIM_CR2_TI1S_Msk (0x1UL << TIM_CR2_TI1S_Pos)

#define	TIM_CR2_TI1S TIM_CR2_TI1S_Msk

#define	TIM_CR2_OIS1_Pos (8U)

#define	TIM_CR2_OIS1_Msk (0x1UL << TIM_CR2_OIS1_Pos)

#define	TIM_CR2_OIS1 TIM_CR2_OIS1_Msk

#define	TIM_CR2_OIS1N_Pos (9U)

#define	TIM_CR2_OIS1N_Msk (0x1UL << TIM_CR2_OIS1N_Pos)

#define	TIM_CR2_OIS1N TIM_CR2_OIS1N_Msk

#define	TIM_CR2_OIS2_Pos (10U)

#define	TIM_CR2_OIS2_Msk (0x1UL << TIM_CR2_OIS2_Pos)

#define	TIM_CR2_OIS2 TIM_CR2_OIS2_Msk

#define	TIM_CR2_OIS2N_Pos (11U)

#define	TIM_CR2_OIS2N_Msk (0x1UL << TIM_CR2_OIS2N_Pos)

#define	TIM_CR2_OIS2N TIM_CR2_OIS2N_Msk

#define	TIM_CR2_OIS3_Pos (12U)

#define	TIM_CR2_OIS3_Msk (0x1UL << TIM_CR2_OIS3_Pos)

#define	TIM_CR2_OIS3 TIM_CR2_OIS3_Msk

#define	TIM_CR2_OIS3N_Pos (13U)

#define	TIM_CR2_OIS3N_Msk (0x1UL << TIM_CR2_OIS3N_Pos)

#define	TIM_CR2_OIS3N TIM_CR2_OIS3N_Msk

#define	TIM_CR2_OIS4_Pos (14U)

#define	TIM_CR2_OIS4_Msk (0x1UL << TIM_CR2_OIS4_Pos)

#define	TIM_CR2_OIS4 TIM_CR2_OIS4_Msk

#define	TIM_CR2_OIS5_Pos (16U)

#define	TIM_CR2_OIS5_Msk (0x1UL << TIM_CR2_OIS5_Pos)

#define	TIM_CR2_OIS5 TIM_CR2_OIS5_Msk

#define	TIM_CR2_OIS6_Pos (18U)

#define	TIM_CR2_OIS6_Msk (0x1UL << TIM_CR2_OIS6_Pos)

#define	TIM_CR2_OIS6 TIM_CR2_OIS6_Msk

#define	TIM_CR2_MMS2_Pos (20U)

#define	TIM_CR2_MMS2_Msk (0xFUL << TIM_CR2_MMS2_Pos)

#define	TIM_CR2_MMS2 TIM_CR2_MMS2_Msk

#define	TIM_CR2_MMS2_0 (0x1UL << TIM_CR2_MMS2_Pos)

#define	TIM_CR2_MMS2_1 (0x2UL << TIM_CR2_MMS2_Pos)

#define	TIM_CR2_MMS2_2 (0x4UL << TIM_CR2_MMS2_Pos)

#define	TIM_CR2_MMS2_3 (0x8UL << TIM_CR2_MMS2_Pos)

#define	TIM_SMCR_SMS_Pos (0U)

#define	TIM_SMCR_SMS_Msk (0x10007UL << TIM_SMCR_SMS_Pos)

#define	TIM_SMCR_SMS TIM_SMCR_SMS_Msk

#define	TIM_SMCR_SMS_0 (0x00000001U)

#define	TIM_SMCR_SMS_1 (0x00000002U)

#define	TIM_SMCR_SMS_2 (0x00000004U)

#define	TIM_SMCR_SMS_3 (0x00010000U)

#define	TIM_SMCR_OCCS_Pos (3U)

#define	TIM_SMCR_OCCS_Msk (0x1UL << TIM_SMCR_OCCS_Pos)

#define	TIM_SMCR_OCCS TIM_SMCR_OCCS_Msk

#define	TIM_SMCR_TS_Pos (4U)

#define	TIM_SMCR_TS_Msk (0x7UL << TIM_SMCR_TS_Pos)

#define	TIM_SMCR_TS TIM_SMCR_TS_Msk

#define	TIM_SMCR_TS_0 (0x1UL << TIM_SMCR_TS_Pos)

#define	TIM_SMCR_TS_1 (0x2UL << TIM_SMCR_TS_Pos)

#define	TIM_SMCR_TS_2 (0x4UL << TIM_SMCR_TS_Pos)

#define	TIM_SMCR_MSM_Pos (7U)

#define	TIM_SMCR_MSM_Msk (0x1UL << TIM_SMCR_MSM_Pos)

#define	TIM_SMCR_MSM TIM_SMCR_MSM_Msk

#define	TIM_SMCR_ETF_Pos (8U)

#define	TIM_SMCR_ETF_Msk (0xFUL << TIM_SMCR_ETF_Pos)

#define	TIM_SMCR_ETF TIM_SMCR_ETF_Msk

#define	TIM_SMCR_ETF_0 (0x1UL << TIM_SMCR_ETF_Pos)

#define	TIM_SMCR_ETF_1 (0x2UL << TIM_SMCR_ETF_Pos)

#define	TIM_SMCR_ETF_2 (0x4UL << TIM_SMCR_ETF_Pos)

#define	TIM_SMCR_ETF_3 (0x8UL << TIM_SMCR_ETF_Pos)

#define	TIM_SMCR_ETPS_Pos (12U)

#define	TIM_SMCR_ETPS_Msk (0x3UL << TIM_SMCR_ETPS_Pos)

#define	TIM_SMCR_ETPS TIM_SMCR_ETPS_Msk

#define	TIM_SMCR_ETPS_0 (0x1UL << TIM_SMCR_ETPS_Pos)

#define	TIM_SMCR_ETPS_1 (0x2UL << TIM_SMCR_ETPS_Pos)

#define	TIM_SMCR_ECE_Pos (14U)

#define	TIM_SMCR_ECE_Msk (0x1UL << TIM_SMCR_ECE_Pos)

#define	TIM_SMCR_ECE TIM_SMCR_ECE_Msk

#define	TIM_SMCR_ETP_Pos (15U)

#define	TIM_SMCR_ETP_Msk (0x1UL << TIM_SMCR_ETP_Pos)

#define	TIM_SMCR_ETP TIM_SMCR_ETP_Msk

#define	TIM_DIER_UIE_Pos (0U)

#define	TIM_DIER_UIE_Msk (0x1UL << TIM_DIER_UIE_Pos)

#define	TIM_DIER_UIE TIM_DIER_UIE_Msk

#define	TIM_DIER_CC1IE_Pos (1U)

#define	TIM_DIER_CC1IE_Msk (0x1UL << TIM_DIER_CC1IE_Pos)

#define	TIM_DIER_CC1IE TIM_DIER_CC1IE_Msk

#define	TIM_DIER_CC2IE_Pos (2U)

#define	TIM_DIER_CC2IE_Msk (0x1UL << TIM_DIER_CC2IE_Pos)

#define	TIM_DIER_CC2IE TIM_DIER_CC2IE_Msk

#define	TIM_DIER_CC3IE_Pos (3U)

#define	TIM_DIER_CC3IE_Msk (0x1UL << TIM_DIER_CC3IE_Pos)

#define	TIM_DIER_CC3IE TIM_DIER_CC3IE_Msk

#define	TIM_DIER_CC4IE_Pos (4U)

#define	TIM_DIER_CC4IE_Msk (0x1UL << TIM_DIER_CC4IE_Pos)

#define	TIM_DIER_CC4IE TIM_DIER_CC4IE_Msk

#define	TIM_DIER_COMIE_Pos (5U)

#define	TIM_DIER_COMIE_Msk (0x1UL << TIM_DIER_COMIE_Pos)

#define	TIM_DIER_COMIE TIM_DIER_COMIE_Msk

#define	TIM_DIER_TIE_Pos (6U)

#define	TIM_DIER_TIE_Msk (0x1UL << TIM_DIER_TIE_Pos)

#define	TIM_DIER_TIE TIM_DIER_TIE_Msk

#define	TIM_DIER_BIE_Pos (7U)

#define	TIM_DIER_BIE_Msk (0x1UL << TIM_DIER_BIE_Pos)

#define	TIM_DIER_BIE TIM_DIER_BIE_Msk

#define	TIM_DIER_UDE_Pos (8U)

#define	TIM_DIER_UDE_Msk (0x1UL << TIM_DIER_UDE_Pos)

#define	TIM_DIER_UDE TIM_DIER_UDE_Msk

#define	TIM_DIER_CC1DE_Pos (9U)

#define	TIM_DIER_CC1DE_Msk (0x1UL << TIM_DIER_CC1DE_Pos)

#define	TIM_DIER_CC1DE TIM_DIER_CC1DE_Msk

#define	TIM_DIER_CC2DE_Pos (10U)

#define	TIM_DIER_CC2DE_Msk (0x1UL << TIM_DIER_CC2DE_Pos)

#define	TIM_DIER_CC2DE TIM_DIER_CC2DE_Msk

#define	TIM_DIER_CC3DE_Pos (11U)

#define	TIM_DIER_CC3DE_Msk (0x1UL << TIM_DIER_CC3DE_Pos)

#define	TIM_DIER_CC3DE TIM_DIER_CC3DE_Msk

#define	TIM_DIER_CC4DE_Pos (12U)

#define	TIM_DIER_CC4DE_Msk (0x1UL << TIM_DIER_CC4DE_Pos)

#define	TIM_DIER_CC4DE TIM_DIER_CC4DE_Msk

#define	TIM_DIER_COMDE_Pos (13U)

#define	TIM_DIER_COMDE_Msk (0x1UL << TIM_DIER_COMDE_Pos)

#define	TIM_DIER_COMDE TIM_DIER_COMDE_Msk

#define	TIM_DIER_TDE_Pos (14U)

#define	TIM_DIER_TDE_Msk (0x1UL << TIM_DIER_TDE_Pos)

#define	TIM_DIER_TDE TIM_DIER_TDE_Msk

#define	TIM_SR_UIF_Pos (0U)

#define	TIM_SR_UIF_Msk (0x1UL << TIM_SR_UIF_Pos)

#define	TIM_SR_UIF TIM_SR_UIF_Msk

#define	TIM_SR_CC1IF_Pos (1U)

#define	TIM_SR_CC1IF_Msk (0x1UL << TIM_SR_CC1IF_Pos)

#define	TIM_SR_CC1IF TIM_SR_CC1IF_Msk

#define	TIM_SR_CC2IF_Pos (2U)

#define	TIM_SR_CC2IF_Msk (0x1UL << TIM_SR_CC2IF_Pos)

#define	TIM_SR_CC2IF TIM_SR_CC2IF_Msk

#define	TIM_SR_CC3IF_Pos (3U)

#define	TIM_SR_CC3IF_Msk (0x1UL << TIM_SR_CC3IF_Pos)

#define	TIM_SR_CC3IF TIM_SR_CC3IF_Msk

#define	TIM_SR_CC4IF_Pos (4U)

#define	TIM_SR_CC4IF_Msk (0x1UL << TIM_SR_CC4IF_Pos)

#define	TIM_SR_CC4IF TIM_SR_CC4IF_Msk

#define	TIM_SR_COMIF_Pos (5U)

#define	TIM_SR_COMIF_Msk (0x1UL << TIM_SR_COMIF_Pos)

#define	TIM_SR_COMIF TIM_SR_COMIF_Msk

#define	TIM_SR_TIF_Pos (6U)

#define	TIM_SR_TIF_Msk (0x1UL << TIM_SR_TIF_Pos)

#define	TIM_SR_TIF TIM_SR_TIF_Msk

#define	TIM_SR_BIF_Pos (7U)

#define	TIM_SR_BIF_Msk (0x1UL << TIM_SR_BIF_Pos)

#define	TIM_SR_BIF TIM_SR_BIF_Msk

#define	TIM_SR_B2IF_Pos (8U)

#define	TIM_SR_B2IF_Msk (0x1UL << TIM_SR_B2IF_Pos)

#define	TIM_SR_B2IF TIM_SR_B2IF_Msk

#define	TIM_SR_CC1OF_Pos (9U)

#define	TIM_SR_CC1OF_Msk (0x1UL << TIM_SR_CC1OF_Pos)

#define	TIM_SR_CC1OF TIM_SR_CC1OF_Msk

#define	TIM_SR_CC2OF_Pos (10U)

#define	TIM_SR_CC2OF_Msk (0x1UL << TIM_SR_CC2OF_Pos)

#define	TIM_SR_CC2OF TIM_SR_CC2OF_Msk

#define	TIM_SR_CC3OF_Pos (11U)

#define	TIM_SR_CC3OF_Msk (0x1UL << TIM_SR_CC3OF_Pos)

#define	TIM_SR_CC3OF TIM_SR_CC3OF_Msk

#define	TIM_SR_CC4OF_Pos (12U)

#define	TIM_SR_CC4OF_Msk (0x1UL << TIM_SR_CC4OF_Pos)

#define	TIM_SR_CC4OF TIM_SR_CC4OF_Msk

#define	TIM_SR_CC5IF_Pos (16U)

#define	TIM_SR_CC5IF_Msk (0x1UL << TIM_SR_CC5IF_Pos)

#define	TIM_SR_CC5IF TIM_SR_CC5IF_Msk

#define	TIM_SR_CC6IF_Pos (17U)

#define	TIM_SR_CC6IF_Msk (0x1UL << TIM_SR_CC6IF_Pos)

#define	TIM_SR_CC6IF TIM_SR_CC6IF_Msk

#define	TIM_EGR_UG_Pos (0U)

#define	TIM_EGR_UG_Msk (0x1UL << TIM_EGR_UG_Pos)

#define	TIM_EGR_UG TIM_EGR_UG_Msk

#define	TIM_EGR_CC1G_Pos (1U)

#define	TIM_EGR_CC1G_Msk (0x1UL << TIM_EGR_CC1G_Pos)

#define	TIM_EGR_CC1G TIM_EGR_CC1G_Msk

#define	TIM_EGR_CC2G_Pos (2U)

#define	TIM_EGR_CC2G_Msk (0x1UL << TIM_EGR_CC2G_Pos)

#define	TIM_EGR_CC2G TIM_EGR_CC2G_Msk

#define	TIM_EGR_CC3G_Pos (3U)

#define	TIM_EGR_CC3G_Msk (0x1UL << TIM_EGR_CC3G_Pos)

#define	TIM_EGR_CC3G TIM_EGR_CC3G_Msk

#define	TIM_EGR_CC4G_Pos (4U)

#define	TIM_EGR_CC4G_Msk (0x1UL << TIM_EGR_CC4G_Pos)

#define	TIM_EGR_CC4G TIM_EGR_CC4G_Msk

#define	TIM_EGR_COMG_Pos (5U)

#define	TIM_EGR_COMG_Msk (0x1UL << TIM_EGR_COMG_Pos)

#define	TIM_EGR_COMG TIM_EGR_COMG_Msk

#define	TIM_EGR_TG_Pos (6U)

#define	TIM_EGR_TG_Msk (0x1UL << TIM_EGR_TG_Pos)

#define	TIM_EGR_TG TIM_EGR_TG_Msk

#define	TIM_EGR_BG_Pos (7U)

#define	TIM_EGR_BG_Msk (0x1UL << TIM_EGR_BG_Pos)

#define	TIM_EGR_BG TIM_EGR_BG_Msk

#define	TIM_EGR_B2G_Pos (8U)

#define	TIM_EGR_B2G_Msk (0x1UL << TIM_EGR_B2G_Pos)

#define	TIM_EGR_B2G TIM_EGR_B2G_Msk

#define	TIM_CCMR1_CC1S_Pos (0U)

#define	TIM_CCMR1_CC1S_Msk (0x3UL << TIM_CCMR1_CC1S_Pos)

#define	TIM_CCMR1_CC1S TIM_CCMR1_CC1S_Msk

#define	TIM_CCMR1_CC1S_0 (0x1UL << TIM_CCMR1_CC1S_Pos)

#define	TIM_CCMR1_CC1S_1 (0x2UL << TIM_CCMR1_CC1S_Pos)

#define	TIM_CCMR1_OC1FE_Pos (2U)

#define	TIM_CCMR1_OC1FE_Msk (0x1UL << TIM_CCMR1_OC1FE_Pos)

#define	TIM_CCMR1_OC1FE TIM_CCMR1_OC1FE_Msk

#define	TIM_CCMR1_OC1PE_Pos (3U)

#define	TIM_CCMR1_OC1PE_Msk (0x1UL << TIM_CCMR1_OC1PE_Pos)

#define	TIM_CCMR1_OC1PE TIM_CCMR1_OC1PE_Msk

#define	TIM_CCMR1_OC1M_Pos (4U)

#define	TIM_CCMR1_OC1M_Msk (0x1007UL << TIM_CCMR1_OC1M_Pos)

#define	TIM_CCMR1_OC1M TIM_CCMR1_OC1M_Msk

#define	TIM_CCMR1_OC1M_0 (0x00000010U)

#define	TIM_CCMR1_OC1M_1 (0x00000020U)

#define	TIM_CCMR1_OC1M_2 (0x00000040U)

#define	TIM_CCMR1_OC1M_3 (0x00010000U)

#define	TIM_CCMR1_OC1CE_Pos (7U)

#define	TIM_CCMR1_OC1CE_Msk (0x1UL << TIM_CCMR1_OC1CE_Pos)

#define	TIM_CCMR1_OC1CE TIM_CCMR1_OC1CE_Msk

#define	TIM_CCMR1_CC2S_Pos (8U)

#define	TIM_CCMR1_CC2S_Msk (0x3UL << TIM_CCMR1_CC2S_Pos)

#define	TIM_CCMR1_CC2S TIM_CCMR1_CC2S_Msk

#define	TIM_CCMR1_CC2S_0 (0x1UL << TIM_CCMR1_CC2S_Pos)

#define	TIM_CCMR1_CC2S_1 (0x2UL << TIM_CCMR1_CC2S_Pos)

#define	TIM_CCMR1_OC2FE_Pos (10U)

#define	TIM_CCMR1_OC2FE_Msk (0x1UL << TIM_CCMR1_OC2FE_Pos)

#define	TIM_CCMR1_OC2FE TIM_CCMR1_OC2FE_Msk

#define	TIM_CCMR1_OC2PE_Pos (11U)

#define	TIM_CCMR1_OC2PE_Msk (0x1UL << TIM_CCMR1_OC2PE_Pos)

#define	TIM_CCMR1_OC2PE TIM_CCMR1_OC2PE_Msk

#define	TIM_CCMR1_OC2M_Pos (12U)

#define	TIM_CCMR1_OC2M_Msk (0x1007UL << TIM_CCMR1_OC2M_Pos)

#define	TIM_CCMR1_OC2M TIM_CCMR1_OC2M_Msk

#define	TIM_CCMR1_OC2M_0 (0x00001000U)

#define	TIM_CCMR1_OC2M_1 (0x00002000U)

#define	TIM_CCMR1_OC2M_2 (0x00004000U)

#define	TIM_CCMR1_OC2M_3 (0x01000000U)

#define	TIM_CCMR1_OC2CE_Pos (15U)

#define	TIM_CCMR1_OC2CE_Msk (0x1UL << TIM_CCMR1_OC2CE_Pos)

#define	TIM_CCMR1_OC2CE TIM_CCMR1_OC2CE_Msk

#define	TIM_CCMR1_IC1PSC_Pos (2U)

#define	TIM_CCMR1_IC1PSC_Msk (0x3UL << TIM_CCMR1_IC1PSC_Pos)

#define	TIM_CCMR1_IC1PSC TIM_CCMR1_IC1PSC_Msk

#define	TIM_CCMR1_IC1PSC_0 (0x1UL << TIM_CCMR1_IC1PSC_Pos)

#define	TIM_CCMR1_IC1PSC_1 (0x2UL << TIM_CCMR1_IC1PSC_Pos)

#define	TIM_CCMR1_IC1F_Pos (4U)

#define	TIM_CCMR1_IC1F_Msk (0xFUL << TIM_CCMR1_IC1F_Pos)

#define	TIM_CCMR1_IC1F TIM_CCMR1_IC1F_Msk

#define	TIM_CCMR1_IC1F_0 (0x1UL << TIM_CCMR1_IC1F_Pos)

#define	TIM_CCMR1_IC1F_1 (0x2UL << TIM_CCMR1_IC1F_Pos)

#define	TIM_CCMR1_IC1F_2 (0x4UL << TIM_CCMR1_IC1F_Pos)

#define	TIM_CCMR1_IC1F_3 (0x8UL << TIM_CCMR1_IC1F_Pos)

#define	TIM_CCMR1_IC2PSC_Pos (10U)

#define	TIM_CCMR1_IC2PSC_Msk (0x3UL << TIM_CCMR1_IC2PSC_Pos)

#define	TIM_CCMR1_IC2PSC TIM_CCMR1_IC2PSC_Msk

#define	TIM_CCMR1_IC2PSC_0 (0x1UL << TIM_CCMR1_IC2PSC_Pos)

#define	TIM_CCMR1_IC2PSC_1 (0x2UL << TIM_CCMR1_IC2PSC_Pos)

#define	TIM_CCMR1_IC2F_Pos (12U)

#define	TIM_CCMR1_IC2F_Msk (0xFUL << TIM_CCMR1_IC2F_Pos)

#define	TIM_CCMR1_IC2F TIM_CCMR1_IC2F_Msk

#define	TIM_CCMR1_IC2F_0 (0x1UL << TIM_CCMR1_IC2F_Pos)

#define	TIM_CCMR1_IC2F_1 (0x2UL << TIM_CCMR1_IC2F_Pos)

#define	TIM_CCMR1_IC2F_2 (0x4UL << TIM_CCMR1_IC2F_Pos)

#define	TIM_CCMR1_IC2F_3 (0x8UL << TIM_CCMR1_IC2F_Pos)

#define	TIM_CCMR2_CC3S_Pos (0U)

#define	TIM_CCMR2_CC3S_Msk (0x3UL << TIM_CCMR2_CC3S_Pos)

#define	TIM_CCMR2_CC3S TIM_CCMR2_CC3S_Msk

#define	TIM_CCMR2_CC3S_0 (0x1UL << TIM_CCMR2_CC3S_Pos)

#define	TIM_CCMR2_CC3S_1 (0x2UL << TIM_CCMR2_CC3S_Pos)

#define	TIM_CCMR2_OC3FE_Pos (2U)

#define	TIM_CCMR2_OC3FE_Msk (0x1UL << TIM_CCMR2_OC3FE_Pos)

#define	TIM_CCMR2_OC3FE TIM_CCMR2_OC3FE_Msk

#define	TIM_CCMR2_OC3PE_Pos (3U)

#define	TIM_CCMR2_OC3PE_Msk (0x1UL << TIM_CCMR2_OC3PE_Pos)

#define	TIM_CCMR2_OC3PE TIM_CCMR2_OC3PE_Msk

#define	TIM_CCMR2_OC3M_Pos (4U)

#define	TIM_CCMR2_OC3M_Msk (0x1007UL << TIM_CCMR2_OC3M_Pos)

#define	TIM_CCMR2_OC3M TIM_CCMR2_OC3M_Msk

#define	TIM_CCMR2_OC3M_0 (0x00000010U)

#define	TIM_CCMR2_OC3M_1 (0x00000020U)

#define	TIM_CCMR2_OC3M_2 (0x00000040U)

#define	TIM_CCMR2_OC3M_3 (0x00010000U)

#define	TIM_CCMR2_OC3CE_Pos (7U)

#define	TIM_CCMR2_OC3CE_Msk (0x1UL << TIM_CCMR2_OC3CE_Pos)

#define	TIM_CCMR2_OC3CE TIM_CCMR2_OC3CE_Msk

#define	TIM_CCMR2_CC4S_Pos (8U)

#define	TIM_CCMR2_CC4S_Msk (0x3UL << TIM_CCMR2_CC4S_Pos)

#define	TIM_CCMR2_CC4S TIM_CCMR2_CC4S_Msk

#define	TIM_CCMR2_CC4S_0 (0x1UL << TIM_CCMR2_CC4S_Pos)

#define	TIM_CCMR2_CC4S_1 (0x2UL << TIM_CCMR2_CC4S_Pos)

#define	TIM_CCMR2_OC4FE_Pos (10U)

#define	TIM_CCMR2_OC4FE_Msk (0x1UL << TIM_CCMR2_OC4FE_Pos)

#define	TIM_CCMR2_OC4FE TIM_CCMR2_OC4FE_Msk

#define	TIM_CCMR2_OC4PE_Pos (11U)

#define	TIM_CCMR2_OC4PE_Msk (0x1UL << TIM_CCMR2_OC4PE_Pos)

#define	TIM_CCMR2_OC4PE TIM_CCMR2_OC4PE_Msk

#define	TIM_CCMR2_OC4M_Pos (12U)

#define	TIM_CCMR2_OC4M_Msk (0x1007UL << TIM_CCMR2_OC4M_Pos)

#define	TIM_CCMR2_OC4M TIM_CCMR2_OC4M_Msk

#define	TIM_CCMR2_OC4M_0 (0x00001000U)

#define	TIM_CCMR2_OC4M_1 (0x00002000U)

#define	TIM_CCMR2_OC4M_2 (0x00004000U)

#define	TIM_CCMR2_OC4M_3 (0x01000000U)

#define	TIM_CCMR2_OC4CE_Pos (15U)

#define	TIM_CCMR2_OC4CE_Msk (0x1UL << TIM_CCMR2_OC4CE_Pos)

#define	TIM_CCMR2_OC4CE TIM_CCMR2_OC4CE_Msk

#define	TIM_CCMR2_IC3PSC_Pos (2U)

#define	TIM_CCMR2_IC3PSC_Msk (0x3UL << TIM_CCMR2_IC3PSC_Pos)

#define	TIM_CCMR2_IC3PSC TIM_CCMR2_IC3PSC_Msk

#define	TIM_CCMR2_IC3PSC_0 (0x1UL << TIM_CCMR2_IC3PSC_Pos)

#define	TIM_CCMR2_IC3PSC_1 (0x2UL << TIM_CCMR2_IC3PSC_Pos)

#define	TIM_CCMR2_IC3F_Pos (4U)

#define	TIM_CCMR2_IC3F_Msk (0xFUL << TIM_CCMR2_IC3F_Pos)

#define	TIM_CCMR2_IC3F TIM_CCMR2_IC3F_Msk

#define	TIM_CCMR2_IC3F_0 (0x1UL << TIM_CCMR2_IC3F_Pos)

#define	TIM_CCMR2_IC3F_1 (0x2UL << TIM_CCMR2_IC3F_Pos)

#define	TIM_CCMR2_IC3F_2 (0x4UL << TIM_CCMR2_IC3F_Pos)

#define	TIM_CCMR2_IC3F_3 (0x8UL << TIM_CCMR2_IC3F_Pos)

#define	TIM_CCMR2_IC4PSC_Pos (10U)

#define	TIM_CCMR2_IC4PSC_Msk (0x3UL << TIM_CCMR2_IC4PSC_Pos)

#define	TIM_CCMR2_IC4PSC TIM_CCMR2_IC4PSC_Msk

#define	TIM_CCMR2_IC4PSC_0 (0x1UL << TIM_CCMR2_IC4PSC_Pos)

#define	TIM_CCMR2_IC4PSC_1 (0x2UL << TIM_CCMR2_IC4PSC_Pos)

#define	TIM_CCMR2_IC4F_Pos (12U)

#define	TIM_CCMR2_IC4F_Msk (0xFUL << TIM_CCMR2_IC4F_Pos)

#define	TIM_CCMR2_IC4F TIM_CCMR2_IC4F_Msk

#define	TIM_CCMR2_IC4F_0 (0x1UL << TIM_CCMR2_IC4F_Pos)

#define	TIM_CCMR2_IC4F_1 (0x2UL << TIM_CCMR2_IC4F_Pos)

#define	TIM_CCMR2_IC4F_2 (0x4UL << TIM_CCMR2_IC4F_Pos)

#define	TIM_CCMR2_IC4F_3 (0x8UL << TIM_CCMR2_IC4F_Pos)

#define	TIM_CCER_CC1E_Pos (0U)

#define	TIM_CCER_CC1E_Msk (0x1UL << TIM_CCER_CC1E_Pos)

#define	TIM_CCER_CC1E TIM_CCER_CC1E_Msk

#define	TIM_CCER_CC1P_Pos (1U)

#define	TIM_CCER_CC1P_Msk (0x1UL << TIM_CCER_CC1P_Pos)

#define	TIM_CCER_CC1P TIM_CCER_CC1P_Msk

#define	TIM_CCER_CC1NE_Pos (2U)

#define	TIM_CCER_CC1NE_Msk (0x1UL << TIM_CCER_CC1NE_Pos)

#define	TIM_CCER_CC1NE TIM_CCER_CC1NE_Msk

#define	TIM_CCER_CC1NP_Pos (3U)

#define	TIM_CCER_CC1NP_Msk (0x1UL << TIM_CCER_CC1NP_Pos)

#define	TIM_CCER_CC1NP TIM_CCER_CC1NP_Msk

#define	TIM_CCER_CC2E_Pos (4U)

#define	TIM_CCER_CC2E_Msk (0x1UL << TIM_CCER_CC2E_Pos)

#define	TIM_CCER_CC2E TIM_CCER_CC2E_Msk

#define	TIM_CCER_CC2P_Pos (5U)

#define	TIM_CCER_CC2P_Msk (0x1UL << TIM_CCER_CC2P_Pos)

#define	TIM_CCER_CC2P TIM_CCER_CC2P_Msk

#define	TIM_CCER_CC2NE_Pos (6U)

#define	TIM_CCER_CC2NE_Msk (0x1UL << TIM_CCER_CC2NE_Pos)

#define	TIM_CCER_CC2NE TIM_CCER_CC2NE_Msk

#define	TIM_CCER_CC2NP_Pos (7U)

#define	TIM_CCER_CC2NP_Msk (0x1UL << TIM_CCER_CC2NP_Pos)

#define	TIM_CCER_CC2NP TIM_CCER_CC2NP_Msk

#define	TIM_CCER_CC3E_Pos (8U)

#define	TIM_CCER_CC3E_Msk (0x1UL << TIM_CCER_CC3E_Pos)

#define	TIM_CCER_CC3E TIM_CCER_CC3E_Msk

#define	TIM_CCER_CC3P_Pos (9U)

#define	TIM_CCER_CC3P_Msk (0x1UL << TIM_CCER_CC3P_Pos)

#define	TIM_CCER_CC3P TIM_CCER_CC3P_Msk

#define	TIM_CCER_CC3NE_Pos (10U)

#define	TIM_CCER_CC3NE_Msk (0x1UL << TIM_CCER_CC3NE_Pos)

#define	TIM_CCER_CC3NE TIM_CCER_CC3NE_Msk

#define	TIM_CCER_CC3NP_Pos (11U)

#define	TIM_CCER_CC3NP_Msk (0x1UL << TIM_CCER_CC3NP_Pos)

#define	TIM_CCER_CC3NP TIM_CCER_CC3NP_Msk

#define	TIM_CCER_CC4E_Pos (12U)

#define	TIM_CCER_CC4E_Msk (0x1UL << TIM_CCER_CC4E_Pos)

#define	TIM_CCER_CC4E TIM_CCER_CC4E_Msk

#define	TIM_CCER_CC4P_Pos (13U)

#define	TIM_CCER_CC4P_Msk (0x1UL << TIM_CCER_CC4P_Pos)

#define	TIM_CCER_CC4P TIM_CCER_CC4P_Msk

#define	TIM_CCER_CC4NP_Pos (15U)

#define	TIM_CCER_CC4NP_Msk (0x1UL << TIM_CCER_CC4NP_Pos)

#define	TIM_CCER_CC4NP TIM_CCER_CC4NP_Msk

#define	TIM_CCER_CC5E_Pos (16U)

#define	TIM_CCER_CC5E_Msk (0x1UL << TIM_CCER_CC5E_Pos)

#define	TIM_CCER_CC5E TIM_CCER_CC5E_Msk

#define	TIM_CCER_CC5P_Pos (17U)

#define	TIM_CCER_CC5P_Msk (0x1UL << TIM_CCER_CC5P_Pos)

#define	TIM_CCER_CC5P TIM_CCER_CC5P_Msk

#define	TIM_CCER_CC6E_Pos (20U)

#define	TIM_CCER_CC6E_Msk (0x1UL << TIM_CCER_CC6E_Pos)

#define	TIM_CCER_CC6E TIM_CCER_CC6E_Msk

#define	TIM_CCER_CC6P_Pos (21U)

#define	TIM_CCER_CC6P_Msk (0x1UL << TIM_CCER_CC6P_Pos)

#define	TIM_CCER_CC6P TIM_CCER_CC6P_Msk

#define	TIM_CNT_CNT_Pos (0U)

#define	TIM_CNT_CNT_Msk (0xFFFFFFFFUL << TIM_CNT_CNT_Pos)

#define	TIM_CNT_CNT TIM_CNT_CNT_Msk

#define	TIM_CNT_UIFCPY_Pos (31U)

#define	TIM_CNT_UIFCPY_Msk (0x1UL << TIM_CNT_UIFCPY_Pos)

#define	TIM_CNT_UIFCPY TIM_CNT_UIFCPY_Msk

#define	TIM_PSC_PSC_Pos (0U)

#define	TIM_PSC_PSC_Msk (0xFFFFUL << TIM_PSC_PSC_Pos)

#define	TIM_PSC_PSC TIM_PSC_PSC_Msk

#define	TIM_ARR_ARR_Pos (0U)

#define	TIM_ARR_ARR_Msk (0xFFFFFFFFUL << TIM_ARR_ARR_Pos)

#define	TIM_ARR_ARR TIM_ARR_ARR_Msk

#define	TIM_RCR_REP_Pos (0U)

#define	TIM_RCR_REP_Msk (0xFFFFUL << TIM_RCR_REP_Pos)

#define	TIM_RCR_REP TIM_RCR_REP_Msk

#define	TIM_CCR1_CCR1_Pos (0U)

#define	TIM_CCR1_CCR1_Msk (0xFFFFUL << TIM_CCR1_CCR1_Pos)

#define	TIM_CCR1_CCR1 TIM_CCR1_CCR1_Msk

#define	TIM_CCR2_CCR2_Pos (0U)

#define	TIM_CCR2_CCR2_Msk (0xFFFFUL << TIM_CCR2_CCR2_Pos)

#define	TIM_CCR2_CCR2 TIM_CCR2_CCR2_Msk

#define	TIM_CCR3_CCR3_Pos (0U)

#define	TIM_CCR3_CCR3_Msk (0xFFFFUL << TIM_CCR3_CCR3_Pos)

#define	TIM_CCR3_CCR3 TIM_CCR3_CCR3_Msk

#define	TIM_CCR4_CCR4_Pos (0U)

#define	TIM_CCR4_CCR4_Msk (0xFFFFUL << TIM_CCR4_CCR4_Pos)

#define	TIM_CCR4_CCR4 TIM_CCR4_CCR4_Msk

#define	TIM_CCR5_CCR5_Pos (0U)

#define	TIM_CCR5_CCR5_Msk (0xFFFFFFFFUL << TIM_CCR5_CCR5_Pos)

#define	TIM_CCR5_CCR5 TIM_CCR5_CCR5_Msk

#define	TIM_CCR5_GC5C1_Pos (29U)

#define	TIM_CCR5_GC5C1_Msk (0x1UL << TIM_CCR5_GC5C1_Pos)

#define	TIM_CCR5_GC5C1 TIM_CCR5_GC5C1_Msk

#define	TIM_CCR5_GC5C2_Pos (30U)

#define	TIM_CCR5_GC5C2_Msk (0x1UL << TIM_CCR5_GC5C2_Pos)

#define	TIM_CCR5_GC5C2 TIM_CCR5_GC5C2_Msk

#define	TIM_CCR5_GC5C3_Pos (31U)

#define	TIM_CCR5_GC5C3_Msk (0x1UL << TIM_CCR5_GC5C3_Pos)

#define	TIM_CCR5_GC5C3 TIM_CCR5_GC5C3_Msk

#define	TIM_CCR6_CCR6_Pos (0U)

#define	TIM_CCR6_CCR6_Msk (0xFFFFUL << TIM_CCR6_CCR6_Pos)

#define	TIM_CCR6_CCR6 TIM_CCR6_CCR6_Msk

#define	TIM_BDTR_DTG_Pos (0U)

#define	TIM_BDTR_DTG_Msk (0xFFUL << TIM_BDTR_DTG_Pos)

#define	TIM_BDTR_DTG TIM_BDTR_DTG_Msk

#define	TIM_BDTR_DTG_0 (0x01UL << TIM_BDTR_DTG_Pos)

#define	TIM_BDTR_DTG_1 (0x02UL << TIM_BDTR_DTG_Pos)

#define	TIM_BDTR_DTG_2 (0x04UL << TIM_BDTR_DTG_Pos)

#define	TIM_BDTR_DTG_3 (0x08UL << TIM_BDTR_DTG_Pos)

#define	TIM_BDTR_DTG_4 (0x10UL << TIM_BDTR_DTG_Pos)

#define	TIM_BDTR_DTG_5 (0x20UL << TIM_BDTR_DTG_Pos)

#define	TIM_BDTR_DTG_6 (0x40UL << TIM_BDTR_DTG_Pos)

#define	TIM_BDTR_DTG_7 (0x80UL << TIM_BDTR_DTG_Pos)

#define	TIM_BDTR_LOCK_Pos (8U)

#define	TIM_BDTR_LOCK_Msk (0x3UL << TIM_BDTR_LOCK_Pos)

#define	TIM_BDTR_LOCK TIM_BDTR_LOCK_Msk

#define	TIM_BDTR_LOCK_0 (0x1UL << TIM_BDTR_LOCK_Pos)

#define	TIM_BDTR_LOCK_1 (0x2UL << TIM_BDTR_LOCK_Pos)

#define	TIM_BDTR_OSSI_Pos (10U)

#define	TIM_BDTR_OSSI_Msk (0x1UL << TIM_BDTR_OSSI_Pos)

#define	TIM_BDTR_OSSI TIM_BDTR_OSSI_Msk

#define	TIM_BDTR_OSSR_Pos (11U)

#define	TIM_BDTR_OSSR_Msk (0x1UL << TIM_BDTR_OSSR_Pos)

#define	TIM_BDTR_OSSR TIM_BDTR_OSSR_Msk

#define	TIM_BDTR_BKE_Pos (12U)

#define	TIM_BDTR_BKE_Msk (0x1UL << TIM_BDTR_BKE_Pos)

#define	TIM_BDTR_BKE TIM_BDTR_BKE_Msk

#define	TIM_BDTR_BKP_Pos (13U)

#define	TIM_BDTR_BKP_Msk (0x1UL << TIM_BDTR_BKP_Pos)

#define	TIM_BDTR_BKP TIM_BDTR_BKP_Msk

#define	TIM_BDTR_AOE_Pos (14U)

#define	TIM_BDTR_AOE_Msk (0x1UL << TIM_BDTR_AOE_Pos)

#define	TIM_BDTR_AOE TIM_BDTR_AOE_Msk

#define	TIM_BDTR_MOE_Pos (15U)

#define	TIM_BDTR_MOE_Msk (0x1UL << TIM_BDTR_MOE_Pos)

#define	TIM_BDTR_MOE TIM_BDTR_MOE_Msk

#define	TIM_BDTR_BKF_Pos (16U)

#define	TIM_BDTR_BKF_Msk (0xFUL << TIM_BDTR_BKF_Pos)

#define	TIM_BDTR_BKF TIM_BDTR_BKF_Msk

#define	TIM_BDTR_BK2F_Pos (20U)

#define	TIM_BDTR_BK2F_Msk (0xFUL << TIM_BDTR_BK2F_Pos)

#define	TIM_BDTR_BK2F TIM_BDTR_BK2F_Msk

#define	TIM_BDTR_BK2E_Pos (24U)

#define	TIM_BDTR_BK2E_Msk (0x1UL << TIM_BDTR_BK2E_Pos)

#define	TIM_BDTR_BK2E TIM_BDTR_BK2E_Msk

#define	TIM_BDTR_BK2P_Pos (25U)

#define	TIM_BDTR_BK2P_Msk (0x1UL << TIM_BDTR_BK2P_Pos)

#define	TIM_BDTR_BK2P TIM_BDTR_BK2P_Msk

#define	TIM_DCR_DBA_Pos (0U)

#define	TIM_DCR_DBA_Msk (0x1FUL << TIM_DCR_DBA_Pos)

#define	TIM_DCR_DBA TIM_DCR_DBA_Msk

#define	TIM_DCR_DBA_0 (0x01UL << TIM_DCR_DBA_Pos)

#define	TIM_DCR_DBA_1 (0x02UL << TIM_DCR_DBA_Pos)

#define	TIM_DCR_DBA_2 (0x04UL << TIM_DCR_DBA_Pos)

#define	TIM_DCR_DBA_3 (0x08UL << TIM_DCR_DBA_Pos)

#define	TIM_DCR_DBA_4 (0x10UL << TIM_DCR_DBA_Pos)

#define	TIM_DCR_DBL_Pos (8U)

#define	TIM_DCR_DBL_Msk (0x1FUL << TIM_DCR_DBL_Pos)

#define	TIM_DCR_DBL TIM_DCR_DBL_Msk

#define	TIM_DCR_DBL_0 (0x01UL << TIM_DCR_DBL_Pos)

#define	TIM_DCR_DBL_1 (0x02UL << TIM_DCR_DBL_Pos)

#define	TIM_DCR_DBL_2 (0x04UL << TIM_DCR_DBL_Pos)

#define	TIM_DCR_DBL_3 (0x08UL << TIM_DCR_DBL_Pos)

#define	TIM_DCR_DBL_4 (0x10UL << TIM_DCR_DBL_Pos)

#define	TIM_DMAR_DMAB_Pos (0U)

#define	TIM_DMAR_DMAB_Msk (0xFFFFUL << TIM_DMAR_DMAB_Pos)

#define	TIM_DMAR_DMAB TIM_DMAR_DMAB_Msk

#define	TIM16_OR_TI1_RMP_Pos (0U)

#define	TIM16_OR_TI1_RMP_Msk (0x3UL << TIM16_OR_TI1_RMP_Pos)

#define	TIM16_OR_TI1_RMP TIM16_OR_TI1_RMP_Msk

#define	TIM16_OR_TI1_RMP_0 (0x1UL << TIM16_OR_TI1_RMP_Pos)

#define	TIM16_OR_TI1_RMP_1 (0x2UL << TIM16_OR_TI1_RMP_Pos)

#define	TIM1_OR_ETR_RMP_Pos (0U)

#define	TIM1_OR_ETR_RMP_Msk (0xFUL << TIM1_OR_ETR_RMP_Pos)

#define	TIM1_OR_ETR_RMP TIM1_OR_ETR_RMP_Msk

#define	TIM1_OR_ETR_RMP_0 (0x1UL << TIM1_OR_ETR_RMP_Pos)

#define	TIM1_OR_ETR_RMP_1 (0x2UL << TIM1_OR_ETR_RMP_Pos)

#define	TIM1_OR_ETR_RMP_2 (0x4UL << TIM1_OR_ETR_RMP_Pos)

#define	TIM1_OR_ETR_RMP_3 (0x8UL << TIM1_OR_ETR_RMP_Pos)

#define	TIM8_OR_ETR_RMP_Pos (0U)

#define	TIM8_OR_ETR_RMP_Msk (0xFUL << TIM8_OR_ETR_RMP_Pos)

#define	TIM8_OR_ETR_RMP TIM8_OR_ETR_RMP_Msk

#define	TIM8_OR_ETR_RMP_0 (0x1UL << TIM8_OR_ETR_RMP_Pos)

#define	TIM8_OR_ETR_RMP_1 (0x2UL << TIM8_OR_ETR_RMP_Pos)

#define	TIM8_OR_ETR_RMP_2 (0x4UL << TIM8_OR_ETR_RMP_Pos)

#define	TIM8_OR_ETR_RMP_3 (0x8UL << TIM8_OR_ETR_RMP_Pos)

#define	TIM20_OR_ETR_RMP_Pos (0U)

#define	TIM20_OR_ETR_RMP_Msk (0xFUL << TIM20_OR_ETR_RMP_Pos)

#define	TIM20_OR_ETR_RMP TIM20_OR_ETR_RMP_Msk

#define	TIM20_OR_ETR_RMP_0 (0x1UL << TIM20_OR_ETR_RMP_Pos)

#define	TIM20_OR_ETR_RMP_1 (0x2UL << TIM20_OR_ETR_RMP_Pos)

#define	TIM20_OR_ETR_RMP_2 (0x4UL << TIM20_OR_ETR_RMP_Pos)

#define	TIM20_OR_ETR_RMP_3 (0x8UL << TIM20_OR_ETR_RMP_Pos)

#define	TIM_CCMR3_OC5FE_Pos (2U)

#define	TIM_CCMR3_OC5FE_Msk (0x1UL << TIM_CCMR3_OC5FE_Pos)

#define	TIM_CCMR3_OC5FE TIM_CCMR3_OC5FE_Msk

#define	TIM_CCMR3_OC5PE_Pos (3U)

#define	TIM_CCMR3_OC5PE_Msk (0x1UL << TIM_CCMR3_OC5PE_Pos)

#define	TIM_CCMR3_OC5PE TIM_CCMR3_OC5PE_Msk

#define	TIM_CCMR3_OC5M_Pos (4U)

#define	TIM_CCMR3_OC5M_Msk (0x1007UL << TIM_CCMR3_OC5M_Pos)

#define	TIM_CCMR3_OC5M TIM_CCMR3_OC5M_Msk

#define	TIM_CCMR3_OC5M_0 (0x0001UL << TIM_CCMR3_OC5M_Pos)

#define	TIM_CCMR3_OC5M_1 (0x0002UL << TIM_CCMR3_OC5M_Pos)

#define	TIM_CCMR3_OC5M_2 (0x0004UL << TIM_CCMR3_OC5M_Pos)

#define	TIM_CCMR3_OC5M_3 (0x1000UL << TIM_CCMR3_OC5M_Pos)

#define	TIM_CCMR3_OC5CE_Pos (7U)

#define	TIM_CCMR3_OC5CE_Msk (0x1UL << TIM_CCMR3_OC5CE_Pos)

#define	TIM_CCMR3_OC5CE TIM_CCMR3_OC5CE_Msk

#define	TIM_CCMR3_OC6FE_Pos (10U)

#define	TIM_CCMR3_OC6FE_Msk (0x1UL << TIM_CCMR3_OC6FE_Pos)

#define	TIM_CCMR3_OC6FE TIM_CCMR3_OC6FE_Msk

#define	TIM_CCMR3_OC6PE_Pos (11U)

#define	TIM_CCMR3_OC6PE_Msk (0x1UL << TIM_CCMR3_OC6PE_Pos)

#define	TIM_CCMR3_OC6PE TIM_CCMR3_OC6PE_Msk

#define	TIM_CCMR3_OC6M_Pos (12U)

#define	TIM_CCMR3_OC6M_Msk (0x1007UL << TIM_CCMR3_OC6M_Pos)

#define	TIM_CCMR3_OC6M TIM_CCMR3_OC6M_Msk

#define	TIM_CCMR3_OC6M_0 (0x0001UL << TIM_CCMR3_OC6M_Pos)

#define	TIM_CCMR3_OC6M_1 (0x0002UL << TIM_CCMR3_OC6M_Pos)

#define	TIM_CCMR3_OC6M_2 (0x0004UL << TIM_CCMR3_OC6M_Pos)

#define	TIM_CCMR3_OC6M_3 (0x1000UL << TIM_CCMR3_OC6M_Pos)

#define	TIM_CCMR3_OC6CE_Pos (15U)

#define	TIM_CCMR3_OC6CE_Msk (0x1UL << TIM_CCMR3_OC6CE_Pos)

#define	TIM_CCMR3_OC6CE TIM_CCMR3_OC6CE_Msk

#define	TSC_CR_TSCE_Pos (0U)

#define	TSC_CR_TSCE_Msk (0x1UL << TSC_CR_TSCE_Pos)

#define	TSC_CR_TSCE TSC_CR_TSCE_Msk

#define	TSC_CR_START_Pos (1U)

#define	TSC_CR_START_Msk (0x1UL << TSC_CR_START_Pos)

#define	TSC_CR_START TSC_CR_START_Msk

#define	TSC_CR_AM_Pos (2U)

#define	TSC_CR_AM_Msk (0x1UL << TSC_CR_AM_Pos)

#define	TSC_CR_AM TSC_CR_AM_Msk

#define	TSC_CR_SYNCPOL_Pos (3U)

#define	TSC_CR_SYNCPOL_Msk (0x1UL << TSC_CR_SYNCPOL_Pos)

#define	TSC_CR_SYNCPOL TSC_CR_SYNCPOL_Msk

#define	TSC_CR_IODEF_Pos (4U)

#define	TSC_CR_IODEF_Msk (0x1UL << TSC_CR_IODEF_Pos)

#define	TSC_CR_IODEF TSC_CR_IODEF_Msk

#define	TSC_CR_MCV_Pos (5U)

#define	TSC_CR_MCV_Msk (0x7UL << TSC_CR_MCV_Pos)

#define	TSC_CR_MCV TSC_CR_MCV_Msk

#define	TSC_CR_MCV_0 (0x1UL << TSC_CR_MCV_Pos)

#define	TSC_CR_MCV_1 (0x2UL << TSC_CR_MCV_Pos)

#define	TSC_CR_MCV_2 (0x4UL << TSC_CR_MCV_Pos)

#define	TSC_CR_PGPSC_Pos (12U)

#define	TSC_CR_PGPSC_Msk (0x7UL << TSC_CR_PGPSC_Pos)

#define	TSC_CR_PGPSC TSC_CR_PGPSC_Msk

#define	TSC_CR_PGPSC_0 (0x1UL << TSC_CR_PGPSC_Pos)

#define	TSC_CR_PGPSC_1 (0x2UL << TSC_CR_PGPSC_Pos)

#define	TSC_CR_PGPSC_2 (0x4UL << TSC_CR_PGPSC_Pos)

#define	TSC_CR_SSPSC_Pos (15U)

#define	TSC_CR_SSPSC_Msk (0x1UL << TSC_CR_SSPSC_Pos)

#define	TSC_CR_SSPSC TSC_CR_SSPSC_Msk

#define	TSC_CR_SSE_Pos (16U)

#define	TSC_CR_SSE_Msk (0x1UL << TSC_CR_SSE_Pos)

#define	TSC_CR_SSE TSC_CR_SSE_Msk

#define	TSC_CR_SSD_Pos (17U)

#define	TSC_CR_SSD_Msk (0x7FUL << TSC_CR_SSD_Pos)

#define	TSC_CR_SSD TSC_CR_SSD_Msk

#define	TSC_CR_SSD_0 (0x01UL << TSC_CR_SSD_Pos)

#define	TSC_CR_SSD_1 (0x02UL << TSC_CR_SSD_Pos)

#define	TSC_CR_SSD_2 (0x04UL << TSC_CR_SSD_Pos)

#define	TSC_CR_SSD_3 (0x08UL << TSC_CR_SSD_Pos)

#define	TSC_CR_SSD_4 (0x10UL << TSC_CR_SSD_Pos)

#define	TSC_CR_SSD_5 (0x20UL << TSC_CR_SSD_Pos)

#define	TSC_CR_SSD_6 (0x40UL << TSC_CR_SSD_Pos)

#define	TSC_CR_CTPL_Pos (24U)

#define	TSC_CR_CTPL_Msk (0xFUL << TSC_CR_CTPL_Pos)

#define	TSC_CR_CTPL TSC_CR_CTPL_Msk

#define	TSC_CR_CTPL_0 (0x1UL << TSC_CR_CTPL_Pos)

#define	TSC_CR_CTPL_1 (0x2UL << TSC_CR_CTPL_Pos)

#define	TSC_CR_CTPL_2 (0x4UL << TSC_CR_CTPL_Pos)

#define	TSC_CR_CTPL_3 (0x8UL << TSC_CR_CTPL_Pos)

#define	TSC_CR_CTPH_Pos (28U)

#define	TSC_CR_CTPH_Msk (0xFUL << TSC_CR_CTPH_Pos)

#define	TSC_CR_CTPH TSC_CR_CTPH_Msk

#define	TSC_CR_CTPH_0 (0x1UL << TSC_CR_CTPH_Pos)

#define	TSC_CR_CTPH_1 (0x2UL << TSC_CR_CTPH_Pos)

#define	TSC_CR_CTPH_2 (0x4UL << TSC_CR_CTPH_Pos)

#define	TSC_CR_CTPH_3 (0x8UL << TSC_CR_CTPH_Pos)

#define	TSC_IER_EOAIE_Pos (0U)

#define	TSC_IER_EOAIE_Msk (0x1UL << TSC_IER_EOAIE_Pos)

#define	TSC_IER_EOAIE TSC_IER_EOAIE_Msk

#define	TSC_IER_MCEIE_Pos (1U)

#define	TSC_IER_MCEIE_Msk (0x1UL << TSC_IER_MCEIE_Pos)

#define	TSC_IER_MCEIE TSC_IER_MCEIE_Msk

#define	TSC_ICR_EOAIC_Pos (0U)

#define	TSC_ICR_EOAIC_Msk (0x1UL << TSC_ICR_EOAIC_Pos)

#define	TSC_ICR_EOAIC TSC_ICR_EOAIC_Msk

#define	TSC_ICR_MCEIC_Pos (1U)

#define	TSC_ICR_MCEIC_Msk (0x1UL << TSC_ICR_MCEIC_Pos)

#define	TSC_ICR_MCEIC TSC_ICR_MCEIC_Msk

#define	TSC_ISR_EOAF_Pos (0U)

#define	TSC_ISR_EOAF_Msk (0x1UL << TSC_ISR_EOAF_Pos)

#define	TSC_ISR_EOAF TSC_ISR_EOAF_Msk

#define	TSC_ISR_MCEF_Pos (1U)

#define	TSC_ISR_MCEF_Msk (0x1UL << TSC_ISR_MCEF_Pos)

#define	TSC_ISR_MCEF TSC_ISR_MCEF_Msk

#define	TSC_IOHCR_G1_IO1_Pos (0U)

#define	TSC_IOHCR_G1_IO1_Msk (0x1UL << TSC_IOHCR_G1_IO1_Pos)

#define	TSC_IOHCR_G1_IO1 TSC_IOHCR_G1_IO1_Msk

#define	TSC_IOHCR_G1_IO2_Pos (1U)

#define	TSC_IOHCR_G1_IO2_Msk (0x1UL << TSC_IOHCR_G1_IO2_Pos)

#define	TSC_IOHCR_G1_IO2 TSC_IOHCR_G1_IO2_Msk

#define	TSC_IOHCR_G1_IO3_Pos (2U)

#define	TSC_IOHCR_G1_IO3_Msk (0x1UL << TSC_IOHCR_G1_IO3_Pos)

#define	TSC_IOHCR_G1_IO3 TSC_IOHCR_G1_IO3_Msk

#define	TSC_IOHCR_G1_IO4_Pos (3U)

#define	TSC_IOHCR_G1_IO4_Msk (0x1UL << TSC_IOHCR_G1_IO4_Pos)

#define	TSC_IOHCR_G1_IO4 TSC_IOHCR_G1_IO4_Msk

#define	TSC_IOHCR_G2_IO1_Pos (4U)

#define	TSC_IOHCR_G2_IO1_Msk (0x1UL << TSC_IOHCR_G2_IO1_Pos)

#define	TSC_IOHCR_G2_IO1 TSC_IOHCR_G2_IO1_Msk

#define	TSC_IOHCR_G2_IO2_Pos (5U)

#define	TSC_IOHCR_G2_IO2_Msk (0x1UL << TSC_IOHCR_G2_IO2_Pos)

#define	TSC_IOHCR_G2_IO2 TSC_IOHCR_G2_IO2_Msk

#define	TSC_IOHCR_G2_IO3_Pos (6U)

#define	TSC_IOHCR_G2_IO3_Msk (0x1UL << TSC_IOHCR_G2_IO3_Pos)

#define	TSC_IOHCR_G2_IO3 TSC_IOHCR_G2_IO3_Msk

#define	TSC_IOHCR_G2_IO4_Pos (7U)

#define	TSC_IOHCR_G2_IO4_Msk (0x1UL << TSC_IOHCR_G2_IO4_Pos)

#define	TSC_IOHCR_G2_IO4 TSC_IOHCR_G2_IO4_Msk

#define	TSC_IOHCR_G3_IO1_Pos (8U)

#define	TSC_IOHCR_G3_IO1_Msk (0x1UL << TSC_IOHCR_G3_IO1_Pos)

#define	TSC_IOHCR_G3_IO1 TSC_IOHCR_G3_IO1_Msk

#define	TSC_IOHCR_G3_IO2_Pos (9U)

#define	TSC_IOHCR_G3_IO2_Msk (0x1UL << TSC_IOHCR_G3_IO2_Pos)

#define	TSC_IOHCR_G3_IO2 TSC_IOHCR_G3_IO2_Msk

#define	TSC_IOHCR_G3_IO3_Pos (10U)

#define	TSC_IOHCR_G3_IO3_Msk (0x1UL << TSC_IOHCR_G3_IO3_Pos)

#define	TSC_IOHCR_G3_IO3 TSC_IOHCR_G3_IO3_Msk

#define	TSC_IOHCR_G3_IO4_Pos (11U)

#define	TSC_IOHCR_G3_IO4_Msk (0x1UL << TSC_IOHCR_G3_IO4_Pos)

#define	TSC_IOHCR_G3_IO4 TSC_IOHCR_G3_IO4_Msk

#define	TSC_IOHCR_G4_IO1_Pos (12U)

#define	TSC_IOHCR_G4_IO1_Msk (0x1UL << TSC_IOHCR_G4_IO1_Pos)

#define	TSC_IOHCR_G4_IO1 TSC_IOHCR_G4_IO1_Msk

#define	TSC_IOHCR_G4_IO2_Pos (13U)

#define	TSC_IOHCR_G4_IO2_Msk (0x1UL << TSC_IOHCR_G4_IO2_Pos)

#define	TSC_IOHCR_G4_IO2 TSC_IOHCR_G4_IO2_Msk

#define	TSC_IOHCR_G4_IO3_Pos (14U)

#define	TSC_IOHCR_G4_IO3_Msk (0x1UL << TSC_IOHCR_G4_IO3_Pos)

#define	TSC_IOHCR_G4_IO3 TSC_IOHCR_G4_IO3_Msk

#define	TSC_IOHCR_G4_IO4_Pos (15U)

#define	TSC_IOHCR_G4_IO4_Msk (0x1UL << TSC_IOHCR_G4_IO4_Pos)

#define	TSC_IOHCR_G4_IO4 TSC_IOHCR_G4_IO4_Msk

#define	TSC_IOHCR_G5_IO1_Pos (16U)

#define	TSC_IOHCR_G5_IO1_Msk (0x1UL << TSC_IOHCR_G5_IO1_Pos)

#define	TSC_IOHCR_G5_IO1 TSC_IOHCR_G5_IO1_Msk

#define	TSC_IOHCR_G5_IO2_Pos (17U)

#define	TSC_IOHCR_G5_IO2_Msk (0x1UL << TSC_IOHCR_G5_IO2_Pos)

#define	TSC_IOHCR_G5_IO2 TSC_IOHCR_G5_IO2_Msk

#define	TSC_IOHCR_G5_IO3_Pos (18U)

#define	TSC_IOHCR_G5_IO3_Msk (0x1UL << TSC_IOHCR_G5_IO3_Pos)

#define	TSC_IOHCR_G5_IO3 TSC_IOHCR_G5_IO3_Msk

#define	TSC_IOHCR_G5_IO4_Pos (19U)

#define	TSC_IOHCR_G5_IO4_Msk (0x1UL << TSC_IOHCR_G5_IO4_Pos)

#define	TSC_IOHCR_G5_IO4 TSC_IOHCR_G5_IO4_Msk

#define	TSC_IOHCR_G6_IO1_Pos (20U)

#define	TSC_IOHCR_G6_IO1_Msk (0x1UL << TSC_IOHCR_G6_IO1_Pos)

#define	TSC_IOHCR_G6_IO1 TSC_IOHCR_G6_IO1_Msk

#define	TSC_IOHCR_G6_IO2_Pos (21U)

#define	TSC_IOHCR_G6_IO2_Msk (0x1UL << TSC_IOHCR_G6_IO2_Pos)

#define	TSC_IOHCR_G6_IO2 TSC_IOHCR_G6_IO2_Msk

#define	TSC_IOHCR_G6_IO3_Pos (22U)

#define	TSC_IOHCR_G6_IO3_Msk (0x1UL << TSC_IOHCR_G6_IO3_Pos)

#define	TSC_IOHCR_G6_IO3 TSC_IOHCR_G6_IO3_Msk

#define	TSC_IOHCR_G6_IO4_Pos (23U)

#define	TSC_IOHCR_G6_IO4_Msk (0x1UL << TSC_IOHCR_G6_IO4_Pos)

#define	TSC_IOHCR_G6_IO4 TSC_IOHCR_G6_IO4_Msk

#define	TSC_IOHCR_G7_IO1_Pos (24U)

#define	TSC_IOHCR_G7_IO1_Msk (0x1UL << TSC_IOHCR_G7_IO1_Pos)

#define	TSC_IOHCR_G7_IO1 TSC_IOHCR_G7_IO1_Msk

#define	TSC_IOHCR_G7_IO2_Pos (25U)

#define	TSC_IOHCR_G7_IO2_Msk (0x1UL << TSC_IOHCR_G7_IO2_Pos)

#define	TSC_IOHCR_G7_IO2 TSC_IOHCR_G7_IO2_Msk

#define	TSC_IOHCR_G7_IO3_Pos (26U)

#define	TSC_IOHCR_G7_IO3_Msk (0x1UL << TSC_IOHCR_G7_IO3_Pos)

#define	TSC_IOHCR_G7_IO3 TSC_IOHCR_G7_IO3_Msk

#define	TSC_IOHCR_G7_IO4_Pos (27U)

#define	TSC_IOHCR_G7_IO4_Msk (0x1UL << TSC_IOHCR_G7_IO4_Pos)

#define	TSC_IOHCR_G7_IO4 TSC_IOHCR_G7_IO4_Msk

#define	TSC_IOHCR_G8_IO1_Pos (28U)

#define	TSC_IOHCR_G8_IO1_Msk (0x1UL << TSC_IOHCR_G8_IO1_Pos)

#define	TSC_IOHCR_G8_IO1 TSC_IOHCR_G8_IO1_Msk

#define	TSC_IOHCR_G8_IO2_Pos (29U)

#define	TSC_IOHCR_G8_IO2_Msk (0x1UL << TSC_IOHCR_G8_IO2_Pos)

#define	TSC_IOHCR_G8_IO2 TSC_IOHCR_G8_IO2_Msk

#define	TSC_IOHCR_G8_IO3_Pos (30U)

#define	TSC_IOHCR_G8_IO3_Msk (0x1UL << TSC_IOHCR_G8_IO3_Pos)

#define	TSC_IOHCR_G8_IO3 TSC_IOHCR_G8_IO3_Msk

#define	TSC_IOHCR_G8_IO4_Pos (31U)

#define	TSC_IOHCR_G8_IO4_Msk (0x1UL << TSC_IOHCR_G8_IO4_Pos)

#define	TSC_IOHCR_G8_IO4 TSC_IOHCR_G8_IO4_Msk

#define	TSC_IOASCR_G1_IO1_Pos (0U)

#define	TSC_IOASCR_G1_IO1_Msk (0x1UL << TSC_IOASCR_G1_IO1_Pos)

#define	TSC_IOASCR_G1_IO1 TSC_IOASCR_G1_IO1_Msk

#define	TSC_IOASCR_G1_IO2_Pos (1U)

#define	TSC_IOASCR_G1_IO2_Msk (0x1UL << TSC_IOASCR_G1_IO2_Pos)

#define	TSC_IOASCR_G1_IO2 TSC_IOASCR_G1_IO2_Msk

#define	TSC_IOASCR_G1_IO3_Pos (2U)

#define	TSC_IOASCR_G1_IO3_Msk (0x1UL << TSC_IOASCR_G1_IO3_Pos)

#define	TSC_IOASCR_G1_IO3 TSC_IOASCR_G1_IO3_Msk

#define	TSC_IOASCR_G1_IO4_Pos (3U)

#define	TSC_IOASCR_G1_IO4_Msk (0x1UL << TSC_IOASCR_G1_IO4_Pos)

#define	TSC_IOASCR_G1_IO4 TSC_IOASCR_G1_IO4_Msk

#define	TSC_IOASCR_G2_IO1_Pos (4U)

#define	TSC_IOASCR_G2_IO1_Msk (0x1UL << TSC_IOASCR_G2_IO1_Pos)

#define	TSC_IOASCR_G2_IO1 TSC_IOASCR_G2_IO1_Msk

#define	TSC_IOASCR_G2_IO2_Pos (5U)

#define	TSC_IOASCR_G2_IO2_Msk (0x1UL << TSC_IOASCR_G2_IO2_Pos)

#define	TSC_IOASCR_G2_IO2 TSC_IOASCR_G2_IO2_Msk

#define	TSC_IOASCR_G2_IO3_Pos (6U)

#define	TSC_IOASCR_G2_IO3_Msk (0x1UL << TSC_IOASCR_G2_IO3_Pos)

#define	TSC_IOASCR_G2_IO3 TSC_IOASCR_G2_IO3_Msk

#define	TSC_IOASCR_G2_IO4_Pos (7U)

#define	TSC_IOASCR_G2_IO4_Msk (0x1UL << TSC_IOASCR_G2_IO4_Pos)

#define	TSC_IOASCR_G2_IO4 TSC_IOASCR_G2_IO4_Msk

#define	TSC_IOASCR_G3_IO1_Pos (8U)

#define	TSC_IOASCR_G3_IO1_Msk (0x1UL << TSC_IOASCR_G3_IO1_Pos)

#define	TSC_IOASCR_G3_IO1 TSC_IOASCR_G3_IO1_Msk

#define	TSC_IOASCR_G3_IO2_Pos (9U)

#define	TSC_IOASCR_G3_IO2_Msk (0x1UL << TSC_IOASCR_G3_IO2_Pos)

#define	TSC_IOASCR_G3_IO2 TSC_IOASCR_G3_IO2_Msk

#define	TSC_IOASCR_G3_IO3_Pos (10U)

#define	TSC_IOASCR_G3_IO3_Msk (0x1UL << TSC_IOASCR_G3_IO3_Pos)

#define	TSC_IOASCR_G3_IO3 TSC_IOASCR_G3_IO3_Msk

#define	TSC_IOASCR_G3_IO4_Pos (11U)

#define	TSC_IOASCR_G3_IO4_Msk (0x1UL << TSC_IOASCR_G3_IO4_Pos)

#define	TSC_IOASCR_G3_IO4 TSC_IOASCR_G3_IO4_Msk

#define	TSC_IOASCR_G4_IO1_Pos (12U)

#define	TSC_IOASCR_G4_IO1_Msk (0x1UL << TSC_IOASCR_G4_IO1_Pos)

#define	TSC_IOASCR_G4_IO1 TSC_IOASCR_G4_IO1_Msk

#define	TSC_IOASCR_G4_IO2_Pos (13U)

#define	TSC_IOASCR_G4_IO2_Msk (0x1UL << TSC_IOASCR_G4_IO2_Pos)

#define	TSC_IOASCR_G4_IO2 TSC_IOASCR_G4_IO2_Msk

#define	TSC_IOASCR_G4_IO3_Pos (14U)

#define	TSC_IOASCR_G4_IO3_Msk (0x1UL << TSC_IOASCR_G4_IO3_Pos)

#define	TSC_IOASCR_G4_IO3 TSC_IOASCR_G4_IO3_Msk

#define	TSC_IOASCR_G4_IO4_Pos (15U)

#define	TSC_IOASCR_G4_IO4_Msk (0x1UL << TSC_IOASCR_G4_IO4_Pos)

#define	TSC_IOASCR_G4_IO4 TSC_IOASCR_G4_IO4_Msk

#define	TSC_IOASCR_G5_IO1_Pos (16U)

#define	TSC_IOASCR_G5_IO1_Msk (0x1UL << TSC_IOASCR_G5_IO1_Pos)

#define	TSC_IOASCR_G5_IO1 TSC_IOASCR_G5_IO1_Msk

#define	TSC_IOASCR_G5_IO2_Pos (17U)

#define	TSC_IOASCR_G5_IO2_Msk (0x1UL << TSC_IOASCR_G5_IO2_Pos)

#define	TSC_IOASCR_G5_IO2 TSC_IOASCR_G5_IO2_Msk

#define	TSC_IOASCR_G5_IO3_Pos (18U)

#define	TSC_IOASCR_G5_IO3_Msk (0x1UL << TSC_IOASCR_G5_IO3_Pos)

#define	TSC_IOASCR_G5_IO3 TSC_IOASCR_G5_IO3_Msk

#define	TSC_IOASCR_G5_IO4_Pos (19U)

#define	TSC_IOASCR_G5_IO4_Msk (0x1UL << TSC_IOASCR_G5_IO4_Pos)

#define	TSC_IOASCR_G5_IO4 TSC_IOASCR_G5_IO4_Msk

#define	TSC_IOASCR_G6_IO1_Pos (20U)

#define	TSC_IOASCR_G6_IO1_Msk (0x1UL << TSC_IOASCR_G6_IO1_Pos)

#define	TSC_IOASCR_G6_IO1 TSC_IOASCR_G6_IO1_Msk

#define	TSC_IOASCR_G6_IO2_Pos (21U)

#define	TSC_IOASCR_G6_IO2_Msk (0x1UL << TSC_IOASCR_G6_IO2_Pos)

#define	TSC_IOASCR_G6_IO2 TSC_IOASCR_G6_IO2_Msk

#define	TSC_IOASCR_G6_IO3_Pos (22U)

#define	TSC_IOASCR_G6_IO3_Msk (0x1UL << TSC_IOASCR_G6_IO3_Pos)

#define	TSC_IOASCR_G6_IO3 TSC_IOASCR_G6_IO3_Msk

#define	TSC_IOASCR_G6_IO4_Pos (23U)

#define	TSC_IOASCR_G6_IO4_Msk (0x1UL << TSC_IOASCR_G6_IO4_Pos)

#define	TSC_IOASCR_G6_IO4 TSC_IOASCR_G6_IO4_Msk

#define	TSC_IOASCR_G7_IO1_Pos (24U)

#define	TSC_IOASCR_G7_IO1_Msk (0x1UL << TSC_IOASCR_G7_IO1_Pos)

#define	TSC_IOASCR_G7_IO1 TSC_IOASCR_G7_IO1_Msk

#define	TSC_IOASCR_G7_IO2_Pos (25U)

#define	TSC_IOASCR_G7_IO2_Msk (0x1UL << TSC_IOASCR_G7_IO2_Pos)

#define	TSC_IOASCR_G7_IO2 TSC_IOASCR_G7_IO2_Msk

#define	TSC_IOASCR_G7_IO3_Pos (26U)

#define	TSC_IOASCR_G7_IO3_Msk (0x1UL << TSC_IOASCR_G7_IO3_Pos)

#define	TSC_IOASCR_G7_IO3 TSC_IOASCR_G7_IO3_Msk

#define	TSC_IOASCR_G7_IO4_Pos (27U)

#define	TSC_IOASCR_G7_IO4_Msk (0x1UL << TSC_IOASCR_G7_IO4_Pos)

#define	TSC_IOASCR_G7_IO4 TSC_IOASCR_G7_IO4_Msk

#define	TSC_IOASCR_G8_IO1_Pos (28U)

#define	TSC_IOASCR_G8_IO1_Msk (0x1UL << TSC_IOASCR_G8_IO1_Pos)

#define	TSC_IOASCR_G8_IO1 TSC_IOASCR_G8_IO1_Msk

#define	TSC_IOASCR_G8_IO2_Pos (29U)

#define	TSC_IOASCR_G8_IO2_Msk (0x1UL << TSC_IOASCR_G8_IO2_Pos)

#define	TSC_IOASCR_G8_IO2 TSC_IOASCR_G8_IO2_Msk

#define	TSC_IOASCR_G8_IO3_Pos (30U)

#define	TSC_IOASCR_G8_IO3_Msk (0x1UL << TSC_IOASCR_G8_IO3_Pos)

#define	TSC_IOASCR_G8_IO3 TSC_IOASCR_G8_IO3_Msk

#define	TSC_IOASCR_G8_IO4_Pos (31U)

#define	TSC_IOASCR_G8_IO4_Msk (0x1UL << TSC_IOASCR_G8_IO4_Pos)

#define	TSC_IOASCR_G8_IO4 TSC_IOASCR_G8_IO4_Msk

#define	TSC_IOSCR_G1_IO1_Pos (0U)

#define	TSC_IOSCR_G1_IO1_Msk (0x1UL << TSC_IOSCR_G1_IO1_Pos)

#define	TSC_IOSCR_G1_IO1 TSC_IOSCR_G1_IO1_Msk

#define	TSC_IOSCR_G1_IO2_Pos (1U)

#define	TSC_IOSCR_G1_IO2_Msk (0x1UL << TSC_IOSCR_G1_IO2_Pos)

#define	TSC_IOSCR_G1_IO2 TSC_IOSCR_G1_IO2_Msk

#define	TSC_IOSCR_G1_IO3_Pos (2U)

#define	TSC_IOSCR_G1_IO3_Msk (0x1UL << TSC_IOSCR_G1_IO3_Pos)

#define	TSC_IOSCR_G1_IO3 TSC_IOSCR_G1_IO3_Msk

#define	TSC_IOSCR_G1_IO4_Pos (3U)

#define	TSC_IOSCR_G1_IO4_Msk (0x1UL << TSC_IOSCR_G1_IO4_Pos)

#define	TSC_IOSCR_G1_IO4 TSC_IOSCR_G1_IO4_Msk

#define	TSC_IOSCR_G2_IO1_Pos (4U)

#define	TSC_IOSCR_G2_IO1_Msk (0x1UL << TSC_IOSCR_G2_IO1_Pos)

#define	TSC_IOSCR_G2_IO1 TSC_IOSCR_G2_IO1_Msk

#define	TSC_IOSCR_G2_IO2_Pos (5U)

#define	TSC_IOSCR_G2_IO2_Msk (0x1UL << TSC_IOSCR_G2_IO2_Pos)

#define	TSC_IOSCR_G2_IO2 TSC_IOSCR_G2_IO2_Msk

#define	TSC_IOSCR_G2_IO3_Pos (6U)

#define	TSC_IOSCR_G2_IO3_Msk (0x1UL << TSC_IOSCR_G2_IO3_Pos)

#define	TSC_IOSCR_G2_IO3 TSC_IOSCR_G2_IO3_Msk

#define	TSC_IOSCR_G2_IO4_Pos (7U)

#define	TSC_IOSCR_G2_IO4_Msk (0x1UL << TSC_IOSCR_G2_IO4_Pos)

#define	TSC_IOSCR_G2_IO4 TSC_IOSCR_G2_IO4_Msk

#define	TSC_IOSCR_G3_IO1_Pos (8U)

#define	TSC_IOSCR_G3_IO1_Msk (0x1UL << TSC_IOSCR_G3_IO1_Pos)

#define	TSC_IOSCR_G3_IO1 TSC_IOSCR_G3_IO1_Msk

#define	TSC_IOSCR_G3_IO2_Pos (9U)

#define	TSC_IOSCR_G3_IO2_Msk (0x1UL << TSC_IOSCR_G3_IO2_Pos)

#define	TSC_IOSCR_G3_IO2 TSC_IOSCR_G3_IO2_Msk

#define	TSC_IOSCR_G3_IO3_Pos (10U)

#define	TSC_IOSCR_G3_IO3_Msk (0x1UL << TSC_IOSCR_G3_IO3_Pos)

#define	TSC_IOSCR_G3_IO3 TSC_IOSCR_G3_IO3_Msk

#define	TSC_IOSCR_G3_IO4_Pos (11U)

#define	TSC_IOSCR_G3_IO4_Msk (0x1UL << TSC_IOSCR_G3_IO4_Pos)

#define	TSC_IOSCR_G3_IO4 TSC_IOSCR_G3_IO4_Msk

#define	TSC_IOSCR_G4_IO1_Pos (12U)

#define	TSC_IOSCR_G4_IO1_Msk (0x1UL << TSC_IOSCR_G4_IO1_Pos)

#define	TSC_IOSCR_G4_IO1 TSC_IOSCR_G4_IO1_Msk

#define	TSC_IOSCR_G4_IO2_Pos (13U)

#define	TSC_IOSCR_G4_IO2_Msk (0x1UL << TSC_IOSCR_G4_IO2_Pos)

#define	TSC_IOSCR_G4_IO2 TSC_IOSCR_G4_IO2_Msk

#define	TSC_IOSCR_G4_IO3_Pos (14U)

#define	TSC_IOSCR_G4_IO3_Msk (0x1UL << TSC_IOSCR_G4_IO3_Pos)

#define	TSC_IOSCR_G4_IO3 TSC_IOSCR_G4_IO3_Msk

#define	TSC_IOSCR_G4_IO4_Pos (15U)

#define	TSC_IOSCR_G4_IO4_Msk (0x1UL << TSC_IOSCR_G4_IO4_Pos)

#define	TSC_IOSCR_G4_IO4 TSC_IOSCR_G4_IO4_Msk

#define	TSC_IOSCR_G5_IO1_Pos (16U)

#define	TSC_IOSCR_G5_IO1_Msk (0x1UL << TSC_IOSCR_G5_IO1_Pos)

#define	TSC_IOSCR_G5_IO1 TSC_IOSCR_G5_IO1_Msk

#define	TSC_IOSCR_G5_IO2_Pos (17U)

#define	TSC_IOSCR_G5_IO2_Msk (0x1UL << TSC_IOSCR_G5_IO2_Pos)

#define	TSC_IOSCR_G5_IO2 TSC_IOSCR_G5_IO2_Msk

#define	TSC_IOSCR_G5_IO3_Pos (18U)

#define	TSC_IOSCR_G5_IO3_Msk (0x1UL << TSC_IOSCR_G5_IO3_Pos)

#define	TSC_IOSCR_G5_IO3 TSC_IOSCR_G5_IO3_Msk

#define	TSC_IOSCR_G5_IO4_Pos (19U)

#define	TSC_IOSCR_G5_IO4_Msk (0x1UL << TSC_IOSCR_G5_IO4_Pos)

#define	TSC_IOSCR_G5_IO4 TSC_IOSCR_G5_IO4_Msk

#define	TSC_IOSCR_G6_IO1_Pos (20U)

#define	TSC_IOSCR_G6_IO1_Msk (0x1UL << TSC_IOSCR_G6_IO1_Pos)

#define	TSC_IOSCR_G6_IO1 TSC_IOSCR_G6_IO1_Msk

#define	TSC_IOSCR_G6_IO2_Pos (21U)

#define	TSC_IOSCR_G6_IO2_Msk (0x1UL << TSC_IOSCR_G6_IO2_Pos)

#define	TSC_IOSCR_G6_IO2 TSC_IOSCR_G6_IO2_Msk

#define	TSC_IOSCR_G6_IO3_Pos (22U)

#define	TSC_IOSCR_G6_IO3_Msk (0x1UL << TSC_IOSCR_G6_IO3_Pos)

#define	TSC_IOSCR_G6_IO3 TSC_IOSCR_G6_IO3_Msk

#define	TSC_IOSCR_G6_IO4_Pos (23U)

#define	TSC_IOSCR_G6_IO4_Msk (0x1UL << TSC_IOSCR_G6_IO4_Pos)

#define	TSC_IOSCR_G6_IO4 TSC_IOSCR_G6_IO4_Msk

#define	TSC_IOSCR_G7_IO1_Pos (24U)

#define	TSC_IOSCR_G7_IO1_Msk (0x1UL << TSC_IOSCR_G7_IO1_Pos)

#define	TSC_IOSCR_G7_IO1 TSC_IOSCR_G7_IO1_Msk

#define	TSC_IOSCR_G7_IO2_Pos (25U)

#define	TSC_IOSCR_G7_IO2_Msk (0x1UL << TSC_IOSCR_G7_IO2_Pos)

#define	TSC_IOSCR_G7_IO2 TSC_IOSCR_G7_IO2_Msk

#define	TSC_IOSCR_G7_IO3_Pos (26U)

#define	TSC_IOSCR_G7_IO3_Msk (0x1UL << TSC_IOSCR_G7_IO3_Pos)

#define	TSC_IOSCR_G7_IO3 TSC_IOSCR_G7_IO3_Msk

#define	TSC_IOSCR_G7_IO4_Pos (27U)

#define	TSC_IOSCR_G7_IO4_Msk (0x1UL << TSC_IOSCR_G7_IO4_Pos)

#define	TSC_IOSCR_G7_IO4 TSC_IOSCR_G7_IO4_Msk

#define	TSC_IOSCR_G8_IO1_Pos (28U)

#define	TSC_IOSCR_G8_IO1_Msk (0x1UL << TSC_IOSCR_G8_IO1_Pos)

#define	TSC_IOSCR_G8_IO1 TSC_IOSCR_G8_IO1_Msk

#define	TSC_IOSCR_G8_IO2_Pos (29U)

#define	TSC_IOSCR_G8_IO2_Msk (0x1UL << TSC_IOSCR_G8_IO2_Pos)

#define	TSC_IOSCR_G8_IO2 TSC_IOSCR_G8_IO2_Msk

#define	TSC_IOSCR_G8_IO3_Pos (30U)

#define	TSC_IOSCR_G8_IO3_Msk (0x1UL << TSC_IOSCR_G8_IO3_Pos)

#define	TSC_IOSCR_G8_IO3 TSC_IOSCR_G8_IO3_Msk

#define	TSC_IOSCR_G8_IO4_Pos (31U)

#define	TSC_IOSCR_G8_IO4_Msk (0x1UL << TSC_IOSCR_G8_IO4_Pos)

#define	TSC_IOSCR_G8_IO4 TSC_IOSCR_G8_IO4_Msk

#define	TSC_IOCCR_G1_IO1_Pos (0U)

#define	TSC_IOCCR_G1_IO1_Msk (0x1UL << TSC_IOCCR_G1_IO1_Pos)

#define	TSC_IOCCR_G1_IO1 TSC_IOCCR_G1_IO1_Msk

#define	TSC_IOCCR_G1_IO2_Pos (1U)

#define	TSC_IOCCR_G1_IO2_Msk (0x1UL << TSC_IOCCR_G1_IO2_Pos)

#define	TSC_IOCCR_G1_IO2 TSC_IOCCR_G1_IO2_Msk

#define	TSC_IOCCR_G1_IO3_Pos (2U)

#define	TSC_IOCCR_G1_IO3_Msk (0x1UL << TSC_IOCCR_G1_IO3_Pos)

#define	TSC_IOCCR_G1_IO3 TSC_IOCCR_G1_IO3_Msk

#define	TSC_IOCCR_G1_IO4_Pos (3U)

#define	TSC_IOCCR_G1_IO4_Msk (0x1UL << TSC_IOCCR_G1_IO4_Pos)

#define	TSC_IOCCR_G1_IO4 TSC_IOCCR_G1_IO4_Msk

#define	TSC_IOCCR_G2_IO1_Pos (4U)

#define	TSC_IOCCR_G2_IO1_Msk (0x1UL << TSC_IOCCR_G2_IO1_Pos)

#define	TSC_IOCCR_G2_IO1 TSC_IOCCR_G2_IO1_Msk

#define	TSC_IOCCR_G2_IO2_Pos (5U)

#define	TSC_IOCCR_G2_IO2_Msk (0x1UL << TSC_IOCCR_G2_IO2_Pos)

#define	TSC_IOCCR_G2_IO2 TSC_IOCCR_G2_IO2_Msk

#define	TSC_IOCCR_G2_IO3_Pos (6U)

#define	TSC_IOCCR_G2_IO3_Msk (0x1UL << TSC_IOCCR_G2_IO3_Pos)

#define	TSC_IOCCR_G2_IO3 TSC_IOCCR_G2_IO3_Msk

#define	TSC_IOCCR_G2_IO4_Pos (7U)

#define	TSC_IOCCR_G2_IO4_Msk (0x1UL << TSC_IOCCR_G2_IO4_Pos)

#define	TSC_IOCCR_G2_IO4 TSC_IOCCR_G2_IO4_Msk

#define	TSC_IOCCR_G3_IO1_Pos (8U)

#define	TSC_IOCCR_G3_IO1_Msk (0x1UL << TSC_IOCCR_G3_IO1_Pos)

#define	TSC_IOCCR_G3_IO1 TSC_IOCCR_G3_IO1_Msk

#define	TSC_IOCCR_G3_IO2_Pos (9U)

#define	TSC_IOCCR_G3_IO2_Msk (0x1UL << TSC_IOCCR_G3_IO2_Pos)

#define	TSC_IOCCR_G3_IO2 TSC_IOCCR_G3_IO2_Msk

#define	TSC_IOCCR_G3_IO3_Pos (10U)

#define	TSC_IOCCR_G3_IO3_Msk (0x1UL << TSC_IOCCR_G3_IO3_Pos)

#define	TSC_IOCCR_G3_IO3 TSC_IOCCR_G3_IO3_Msk

#define	TSC_IOCCR_G3_IO4_Pos (11U)

#define	TSC_IOCCR_G3_IO4_Msk (0x1UL << TSC_IOCCR_G3_IO4_Pos)

#define	TSC_IOCCR_G3_IO4 TSC_IOCCR_G3_IO4_Msk

#define	TSC_IOCCR_G4_IO1_Pos (12U)

#define	TSC_IOCCR_G4_IO1_Msk (0x1UL << TSC_IOCCR_G4_IO1_Pos)

#define	TSC_IOCCR_G4_IO1 TSC_IOCCR_G4_IO1_Msk

#define	TSC_IOCCR_G4_IO2_Pos (13U)

#define	TSC_IOCCR_G4_IO2_Msk (0x1UL << TSC_IOCCR_G4_IO2_Pos)

#define	TSC_IOCCR_G4_IO2 TSC_IOCCR_G4_IO2_Msk

#define	TSC_IOCCR_G4_IO3_Pos (14U)

#define	TSC_IOCCR_G4_IO3_Msk (0x1UL << TSC_IOCCR_G4_IO3_Pos)

#define	TSC_IOCCR_G4_IO3 TSC_IOCCR_G4_IO3_Msk

#define	TSC_IOCCR_G4_IO4_Pos (15U)

#define	TSC_IOCCR_G4_IO4_Msk (0x1UL << TSC_IOCCR_G4_IO4_Pos)

#define	TSC_IOCCR_G4_IO4 TSC_IOCCR_G4_IO4_Msk

#define	TSC_IOCCR_G5_IO1_Pos (16U)

#define	TSC_IOCCR_G5_IO1_Msk (0x1UL << TSC_IOCCR_G5_IO1_Pos)

#define	TSC_IOCCR_G5_IO1 TSC_IOCCR_G5_IO1_Msk

#define	TSC_IOCCR_G5_IO2_Pos (17U)

#define	TSC_IOCCR_G5_IO2_Msk (0x1UL << TSC_IOCCR_G5_IO2_Pos)

#define	TSC_IOCCR_G5_IO2 TSC_IOCCR_G5_IO2_Msk

#define	TSC_IOCCR_G5_IO3_Pos (18U)

#define	TSC_IOCCR_G5_IO3_Msk (0x1UL << TSC_IOCCR_G5_IO3_Pos)

#define	TSC_IOCCR_G5_IO3 TSC_IOCCR_G5_IO3_Msk

#define	TSC_IOCCR_G5_IO4_Pos (19U)

#define	TSC_IOCCR_G5_IO4_Msk (0x1UL << TSC_IOCCR_G5_IO4_Pos)

#define	TSC_IOCCR_G5_IO4 TSC_IOCCR_G5_IO4_Msk

#define	TSC_IOCCR_G6_IO1_Pos (20U)

#define	TSC_IOCCR_G6_IO1_Msk (0x1UL << TSC_IOCCR_G6_IO1_Pos)

#define	TSC_IOCCR_G6_IO1 TSC_IOCCR_G6_IO1_Msk

#define	TSC_IOCCR_G6_IO2_Pos (21U)

#define	TSC_IOCCR_G6_IO2_Msk (0x1UL << TSC_IOCCR_G6_IO2_Pos)

#define	TSC_IOCCR_G6_IO2 TSC_IOCCR_G6_IO2_Msk

#define	TSC_IOCCR_G6_IO3_Pos (22U)

#define	TSC_IOCCR_G6_IO3_Msk (0x1UL << TSC_IOCCR_G6_IO3_Pos)

#define	TSC_IOCCR_G6_IO3 TSC_IOCCR_G6_IO3_Msk

#define	TSC_IOCCR_G6_IO4_Pos (23U)

#define	TSC_IOCCR_G6_IO4_Msk (0x1UL << TSC_IOCCR_G6_IO4_Pos)

#define	TSC_IOCCR_G6_IO4 TSC_IOCCR_G6_IO4_Msk

#define	TSC_IOCCR_G7_IO1_Pos (24U)

#define	TSC_IOCCR_G7_IO1_Msk (0x1UL << TSC_IOCCR_G7_IO1_Pos)

#define	TSC_IOCCR_G7_IO1 TSC_IOCCR_G7_IO1_Msk

#define	TSC_IOCCR_G7_IO2_Pos (25U)

#define	TSC_IOCCR_G7_IO2_Msk (0x1UL << TSC_IOCCR_G7_IO2_Pos)

#define	TSC_IOCCR_G7_IO2 TSC_IOCCR_G7_IO2_Msk

#define	TSC_IOCCR_G7_IO3_Pos (26U)

#define	TSC_IOCCR_G7_IO3_Msk (0x1UL << TSC_IOCCR_G7_IO3_Pos)

#define	TSC_IOCCR_G7_IO3 TSC_IOCCR_G7_IO3_Msk

#define	TSC_IOCCR_G7_IO4_Pos (27U)

#define	TSC_IOCCR_G7_IO4_Msk (0x1UL << TSC_IOCCR_G7_IO4_Pos)

#define	TSC_IOCCR_G7_IO4 TSC_IOCCR_G7_IO4_Msk

#define	TSC_IOCCR_G8_IO1_Pos (28U)

#define	TSC_IOCCR_G8_IO1_Msk (0x1UL << TSC_IOCCR_G8_IO1_Pos)

#define	TSC_IOCCR_G8_IO1 TSC_IOCCR_G8_IO1_Msk

#define	TSC_IOCCR_G8_IO2_Pos (29U)

#define	TSC_IOCCR_G8_IO2_Msk (0x1UL << TSC_IOCCR_G8_IO2_Pos)

#define	TSC_IOCCR_G8_IO2 TSC_IOCCR_G8_IO2_Msk

#define	TSC_IOCCR_G8_IO3_Pos (30U)

#define	TSC_IOCCR_G8_IO3_Msk (0x1UL << TSC_IOCCR_G8_IO3_Pos)

#define	TSC_IOCCR_G8_IO3 TSC_IOCCR_G8_IO3_Msk

#define	TSC_IOCCR_G8_IO4_Pos (31U)

#define	TSC_IOCCR_G8_IO4_Msk (0x1UL << TSC_IOCCR_G8_IO4_Pos)

#define	TSC_IOCCR_G8_IO4 TSC_IOCCR_G8_IO4_Msk

#define	TSC_IOGCSR_G1E_Pos (0U)

#define	TSC_IOGCSR_G1E_Msk (0x1UL << TSC_IOGCSR_G1E_Pos)

#define	TSC_IOGCSR_G1E TSC_IOGCSR_G1E_Msk

#define	TSC_IOGCSR_G2E_Pos (1U)

#define	TSC_IOGCSR_G2E_Msk (0x1UL << TSC_IOGCSR_G2E_Pos)

#define	TSC_IOGCSR_G2E TSC_IOGCSR_G2E_Msk

#define	TSC_IOGCSR_G3E_Pos (2U)

#define	TSC_IOGCSR_G3E_Msk (0x1UL << TSC_IOGCSR_G3E_Pos)

#define	TSC_IOGCSR_G3E TSC_IOGCSR_G3E_Msk

#define	TSC_IOGCSR_G4E_Pos (3U)

#define	TSC_IOGCSR_G4E_Msk (0x1UL << TSC_IOGCSR_G4E_Pos)

#define	TSC_IOGCSR_G4E TSC_IOGCSR_G4E_Msk

#define	TSC_IOGCSR_G5E_Pos (4U)

#define	TSC_IOGCSR_G5E_Msk (0x1UL << TSC_IOGCSR_G5E_Pos)

#define	TSC_IOGCSR_G5E TSC_IOGCSR_G5E_Msk

#define	TSC_IOGCSR_G6E_Pos (5U)

#define	TSC_IOGCSR_G6E_Msk (0x1UL << TSC_IOGCSR_G6E_Pos)

#define	TSC_IOGCSR_G6E TSC_IOGCSR_G6E_Msk

#define	TSC_IOGCSR_G7E_Pos (6U)

#define	TSC_IOGCSR_G7E_Msk (0x1UL << TSC_IOGCSR_G7E_Pos)

#define	TSC_IOGCSR_G7E TSC_IOGCSR_G7E_Msk

#define	TSC_IOGCSR_G8E_Pos (7U)

#define	TSC_IOGCSR_G8E_Msk (0x1UL << TSC_IOGCSR_G8E_Pos)

#define	TSC_IOGCSR_G8E TSC_IOGCSR_G8E_Msk

#define	TSC_IOGCSR_G1S_Pos (16U)

#define	TSC_IOGCSR_G1S_Msk (0x1UL << TSC_IOGCSR_G1S_Pos)

#define	TSC_IOGCSR_G1S TSC_IOGCSR_G1S_Msk

#define	TSC_IOGCSR_G2S_Pos (17U)

#define	TSC_IOGCSR_G2S_Msk (0x1UL << TSC_IOGCSR_G2S_Pos)

#define	TSC_IOGCSR_G2S TSC_IOGCSR_G2S_Msk

#define	TSC_IOGCSR_G3S_Pos (18U)

#define	TSC_IOGCSR_G3S_Msk (0x1UL << TSC_IOGCSR_G3S_Pos)

#define	TSC_IOGCSR_G3S TSC_IOGCSR_G3S_Msk

#define	TSC_IOGCSR_G4S_Pos (19U)

#define	TSC_IOGCSR_G4S_Msk (0x1UL << TSC_IOGCSR_G4S_Pos)

#define	TSC_IOGCSR_G4S TSC_IOGCSR_G4S_Msk

#define	TSC_IOGCSR_G5S_Pos (20U)

#define	TSC_IOGCSR_G5S_Msk (0x1UL << TSC_IOGCSR_G5S_Pos)

#define	TSC_IOGCSR_G5S TSC_IOGCSR_G5S_Msk

#define	TSC_IOGCSR_G6S_Pos (21U)

#define	TSC_IOGCSR_G6S_Msk (0x1UL << TSC_IOGCSR_G6S_Pos)

#define	TSC_IOGCSR_G6S TSC_IOGCSR_G6S_Msk

#define	TSC_IOGCSR_G7S_Pos (22U)

#define	TSC_IOGCSR_G7S_Msk (0x1UL << TSC_IOGCSR_G7S_Pos)

#define	TSC_IOGCSR_G7S TSC_IOGCSR_G7S_Msk

#define	TSC_IOGCSR_G8S_Pos (23U)

#define	TSC_IOGCSR_G8S_Msk (0x1UL << TSC_IOGCSR_G8S_Pos)

#define	TSC_IOGCSR_G8S TSC_IOGCSR_G8S_Msk

#define	TSC_IOGXCR_CNT_Pos (0U)

#define	TSC_IOGXCR_CNT_Msk (0x3FFFUL << TSC_IOGXCR_CNT_Pos)

#define	TSC_IOGXCR_CNT TSC_IOGXCR_CNT_Msk

#define	USART_7BITS_SUPPORT

#define	USART_CR1_UE_Pos (0U)

#define	USART_CR1_UE_Msk (0x1UL << USART_CR1_UE_Pos)

#define	USART_CR1_UE USART_CR1_UE_Msk

#define	USART_CR1_UESM_Pos (1U)

#define	USART_CR1_UESM_Msk (0x1UL << USART_CR1_UESM_Pos)

#define	USART_CR1_UESM USART_CR1_UESM_Msk

#define	USART_CR1_RE_Pos (2U)

#define	USART_CR1_RE_Msk (0x1UL << USART_CR1_RE_Pos)

#define	USART_CR1_RE USART_CR1_RE_Msk

#define	USART_CR1_TE_Pos (3U)

#define	USART_CR1_TE_Msk (0x1UL << USART_CR1_TE_Pos)

#define	USART_CR1_TE USART_CR1_TE_Msk

#define	USART_CR1_IDLEIE_Pos (4U)

#define	USART_CR1_IDLEIE_Msk (0x1UL << USART_CR1_IDLEIE_Pos)

#define	USART_CR1_IDLEIE USART_CR1_IDLEIE_Msk

#define	USART_CR1_RXNEIE_Pos (5U)

#define	USART_CR1_RXNEIE_Msk (0x1UL << USART_CR1_RXNEIE_Pos)

#define	USART_CR1_RXNEIE USART_CR1_RXNEIE_Msk

#define	USART_CR1_TCIE_Pos (6U)

#define	USART_CR1_TCIE_Msk (0x1UL << USART_CR1_TCIE_Pos)

#define	USART_CR1_TCIE USART_CR1_TCIE_Msk

#define	USART_CR1_TXEIE_Pos (7U)

#define	USART_CR1_TXEIE_Msk (0x1UL << USART_CR1_TXEIE_Pos)

#define	USART_CR1_TXEIE USART_CR1_TXEIE_Msk

#define	USART_CR1_PEIE_Pos (8U)

#define	USART_CR1_PEIE_Msk (0x1UL << USART_CR1_PEIE_Pos)

#define	USART_CR1_PEIE USART_CR1_PEIE_Msk

#define	USART_CR1_PS_Pos (9U)

#define	USART_CR1_PS_Msk (0x1UL << USART_CR1_PS_Pos)

#define	USART_CR1_PS USART_CR1_PS_Msk

#define	USART_CR1_PCE_Pos (10U)

#define	USART_CR1_PCE_Msk (0x1UL << USART_CR1_PCE_Pos)

#define	USART_CR1_PCE USART_CR1_PCE_Msk

#define	USART_CR1_WAKE_Pos (11U)

#define	USART_CR1_WAKE_Msk (0x1UL << USART_CR1_WAKE_Pos)

#define	USART_CR1_WAKE USART_CR1_WAKE_Msk

#define	USART_CR1_M0_Pos (12U)

#define	USART_CR1_M0_Msk (0x1UL << USART_CR1_M0_Pos)

#define	USART_CR1_M0 USART_CR1_M0_Msk

#define	USART_CR1_MME_Pos (13U)

#define	USART_CR1_MME_Msk (0x1UL << USART_CR1_MME_Pos)

#define	USART_CR1_MME USART_CR1_MME_Msk

#define	USART_CR1_CMIE_Pos (14U)

#define	USART_CR1_CMIE_Msk (0x1UL << USART_CR1_CMIE_Pos)

#define	USART_CR1_CMIE USART_CR1_CMIE_Msk

#define	USART_CR1_OVER8_Pos (15U)

#define	USART_CR1_OVER8_Msk (0x1UL << USART_CR1_OVER8_Pos)

#define	USART_CR1_OVER8 USART_CR1_OVER8_Msk

#define	USART_CR1_DEDT_Pos (16U)

#define	USART_CR1_DEDT_Msk (0x1FUL << USART_CR1_DEDT_Pos)

#define	USART_CR1_DEDT USART_CR1_DEDT_Msk

#define	USART_CR1_DEDT_0 (0x01UL << USART_CR1_DEDT_Pos)

#define	USART_CR1_DEDT_1 (0x02UL << USART_CR1_DEDT_Pos)

#define	USART_CR1_DEDT_2 (0x04UL << USART_CR1_DEDT_Pos)

#define	USART_CR1_DEDT_3 (0x08UL << USART_CR1_DEDT_Pos)

#define	USART_CR1_DEDT_4 (0x10UL << USART_CR1_DEDT_Pos)

#define	USART_CR1_DEAT_Pos (21U)

#define	USART_CR1_DEAT_Msk (0x1FUL << USART_CR1_DEAT_Pos)

#define	USART_CR1_DEAT USART_CR1_DEAT_Msk

#define	USART_CR1_DEAT_0 (0x01UL << USART_CR1_DEAT_Pos)

#define	USART_CR1_DEAT_1 (0x02UL << USART_CR1_DEAT_Pos)

#define	USART_CR1_DEAT_2 (0x04UL << USART_CR1_DEAT_Pos)

#define	USART_CR1_DEAT_3 (0x08UL << USART_CR1_DEAT_Pos)

#define	USART_CR1_DEAT_4 (0x10UL << USART_CR1_DEAT_Pos)

#define	USART_CR1_RTOIE_Pos (26U)

#define	USART_CR1_RTOIE_Msk (0x1UL << USART_CR1_RTOIE_Pos)

#define	USART_CR1_RTOIE USART_CR1_RTOIE_Msk

#define	USART_CR1_EOBIE_Pos (27U)

#define	USART_CR1_EOBIE_Msk (0x1UL << USART_CR1_EOBIE_Pos)

#define	USART_CR1_EOBIE USART_CR1_EOBIE_Msk

#define	USART_CR1_M1_Pos (28U)

#define	USART_CR1_M1_Msk (0x1UL << USART_CR1_M1_Pos)

#define	USART_CR1_M1 USART_CR1_M1_Msk

#define	USART_CR1_M_Pos (12U)

#define	USART_CR1_M_Msk (0x10001UL << USART_CR1_M_Pos)

#define	USART_CR1_M USART_CR1_M_Msk

#define	USART_CR2_ADDM7_Pos (4U)

#define	USART_CR2_ADDM7_Msk (0x1UL << USART_CR2_ADDM7_Pos)

#define	USART_CR2_ADDM7 USART_CR2_ADDM7_Msk

#define	USART_CR2_LBDL_Pos (5U)

#define	USART_CR2_LBDL_Msk (0x1UL << USART_CR2_LBDL_Pos)

#define	USART_CR2_LBDL USART_CR2_LBDL_Msk

#define	USART_CR2_LBDIE_Pos (6U)

#define	USART_CR2_LBDIE_Msk (0x1UL << USART_CR2_LBDIE_Pos)

#define	USART_CR2_LBDIE USART_CR2_LBDIE_Msk

#define	USART_CR2_LBCL_Pos (8U)

#define	USART_CR2_LBCL_Msk (0x1UL << USART_CR2_LBCL_Pos)

#define	USART_CR2_LBCL USART_CR2_LBCL_Msk

#define	USART_CR2_CPHA_Pos (9U)

#define	USART_CR2_CPHA_Msk (0x1UL << USART_CR2_CPHA_Pos)

#define	USART_CR2_CPHA USART_CR2_CPHA_Msk

#define	USART_CR2_CPOL_Pos (10U)

#define	USART_CR2_CPOL_Msk (0x1UL << USART_CR2_CPOL_Pos)

#define	USART_CR2_CPOL USART_CR2_CPOL_Msk

#define	USART_CR2_CLKEN_Pos (11U)

#define	USART_CR2_CLKEN_Msk (0x1UL << USART_CR2_CLKEN_Pos)

#define	USART_CR2_CLKEN USART_CR2_CLKEN_Msk

#define	USART_CR2_STOP_Pos (12U)

#define	USART_CR2_STOP_Msk (0x3UL << USART_CR2_STOP_Pos)

#define	USART_CR2_STOP USART_CR2_STOP_Msk

#define	USART_CR2_STOP_0 (0x1UL << USART_CR2_STOP_Pos)

#define	USART_CR2_STOP_1 (0x2UL << USART_CR2_STOP_Pos)

#define	USART_CR2_LINEN_Pos (14U)

#define	USART_CR2_LINEN_Msk (0x1UL << USART_CR2_LINEN_Pos)

#define	USART_CR2_LINEN USART_CR2_LINEN_Msk

#define	USART_CR2_SWAP_Pos (15U)

#define	USART_CR2_SWAP_Msk (0x1UL << USART_CR2_SWAP_Pos)

#define	USART_CR2_SWAP USART_CR2_SWAP_Msk

#define	USART_CR2_RXINV_Pos (16U)

#define	USART_CR2_RXINV_Msk (0x1UL << USART_CR2_RXINV_Pos)

#define	USART_CR2_RXINV USART_CR2_RXINV_Msk

#define	USART_CR2_TXINV_Pos (17U)

#define	USART_CR2_TXINV_Msk (0x1UL << USART_CR2_TXINV_Pos)

#define	USART_CR2_TXINV USART_CR2_TXINV_Msk

#define	USART_CR2_DATAINV_Pos (18U)

#define	USART_CR2_DATAINV_Msk (0x1UL << USART_CR2_DATAINV_Pos)

#define	USART_CR2_DATAINV USART_CR2_DATAINV_Msk

#define	USART_CR2_MSBFIRST_Pos (19U)

#define	USART_CR2_MSBFIRST_Msk (0x1UL << USART_CR2_MSBFIRST_Pos)

#define	USART_CR2_MSBFIRST USART_CR2_MSBFIRST_Msk

#define	USART_CR2_ABREN_Pos (20U)

#define	USART_CR2_ABREN_Msk (0x1UL << USART_CR2_ABREN_Pos)

#define	USART_CR2_ABREN USART_CR2_ABREN_Msk

#define	USART_CR2_ABRMODE_Pos (21U)

#define	USART_CR2_ABRMODE_Msk (0x3UL << USART_CR2_ABRMODE_Pos)

#define	USART_CR2_ABRMODE USART_CR2_ABRMODE_Msk

#define	USART_CR2_ABRMODE_0 (0x1UL << USART_CR2_ABRMODE_Pos)

#define	USART_CR2_ABRMODE_1 (0x2UL << USART_CR2_ABRMODE_Pos)

#define	USART_CR2_RTOEN_Pos (23U)

#define	USART_CR2_RTOEN_Msk (0x1UL << USART_CR2_RTOEN_Pos)

#define	USART_CR2_RTOEN USART_CR2_RTOEN_Msk

#define	USART_CR2_ADD_Pos (24U)

#define	USART_CR2_ADD_Msk (0xFFUL << USART_CR2_ADD_Pos)

#define	USART_CR2_ADD USART_CR2_ADD_Msk

#define	USART_CR3_EIE_Pos (0U)

#define	USART_CR3_EIE_Msk (0x1UL << USART_CR3_EIE_Pos)

#define	USART_CR3_EIE USART_CR3_EIE_Msk

#define	USART_CR3_IREN_Pos (1U)

#define	USART_CR3_IREN_Msk (0x1UL << USART_CR3_IREN_Pos)

#define	USART_CR3_IREN USART_CR3_IREN_Msk

#define	USART_CR3_IRLP_Pos (2U)

#define	USART_CR3_IRLP_Msk (0x1UL << USART_CR3_IRLP_Pos)

#define	USART_CR3_IRLP USART_CR3_IRLP_Msk

#define	USART_CR3_HDSEL_Pos (3U)

#define	USART_CR3_HDSEL_Msk (0x1UL << USART_CR3_HDSEL_Pos)

#define	USART_CR3_HDSEL USART_CR3_HDSEL_Msk

#define	USART_CR3_NACK_Pos (4U)

#define	USART_CR3_NACK_Msk (0x1UL << USART_CR3_NACK_Pos)

#define	USART_CR3_NACK USART_CR3_NACK_Msk

#define	USART_CR3_SCEN_Pos (5U)

#define	USART_CR3_SCEN_Msk (0x1UL << USART_CR3_SCEN_Pos)

#define	USART_CR3_SCEN USART_CR3_SCEN_Msk

#define	USART_CR3_DMAR_Pos (6U)

#define	USART_CR3_DMAR_Msk (0x1UL << USART_CR3_DMAR_Pos)

#define	USART_CR3_DMAR USART_CR3_DMAR_Msk

#define	USART_CR3_DMAT_Pos (7U)

#define	USART_CR3_DMAT_Msk (0x1UL << USART_CR3_DMAT_Pos)

#define	USART_CR3_DMAT USART_CR3_DMAT_Msk

#define	USART_CR3_RTSE_Pos (8U)

#define	USART_CR3_RTSE_Msk (0x1UL << USART_CR3_RTSE_Pos)

#define	USART_CR3_RTSE USART_CR3_RTSE_Msk

#define	USART_CR3_CTSE_Pos (9U)

#define	USART_CR3_CTSE_Msk (0x1UL << USART_CR3_CTSE_Pos)

#define	USART_CR3_CTSE USART_CR3_CTSE_Msk

#define	USART_CR3_CTSIE_Pos (10U)

#define	USART_CR3_CTSIE_Msk (0x1UL << USART_CR3_CTSIE_Pos)

#define	USART_CR3_CTSIE USART_CR3_CTSIE_Msk

#define	USART_CR3_ONEBIT_Pos (11U)

#define	USART_CR3_ONEBIT_Msk (0x1UL << USART_CR3_ONEBIT_Pos)

#define	USART_CR3_ONEBIT USART_CR3_ONEBIT_Msk

#define	USART_CR3_OVRDIS_Pos (12U)

#define	USART_CR3_OVRDIS_Msk (0x1UL << USART_CR3_OVRDIS_Pos)

#define	USART_CR3_OVRDIS USART_CR3_OVRDIS_Msk

#define	USART_CR3_DDRE_Pos (13U)

#define	USART_CR3_DDRE_Msk (0x1UL << USART_CR3_DDRE_Pos)

#define	USART_CR3_DDRE USART_CR3_DDRE_Msk

#define	USART_CR3_DEM_Pos (14U)

#define	USART_CR3_DEM_Msk (0x1UL << USART_CR3_DEM_Pos)

#define	USART_CR3_DEM USART_CR3_DEM_Msk

#define	USART_CR3_DEP_Pos (15U)

#define	USART_CR3_DEP_Msk (0x1UL << USART_CR3_DEP_Pos)

#define	USART_CR3_DEP USART_CR3_DEP_Msk

#define	USART_CR3_SCARCNT_Pos (17U)

#define	USART_CR3_SCARCNT_Msk (0x7UL << USART_CR3_SCARCNT_Pos)

#define	USART_CR3_SCARCNT USART_CR3_SCARCNT_Msk

#define	USART_CR3_SCARCNT_0 (0x1UL << USART_CR3_SCARCNT_Pos)

#define	USART_CR3_SCARCNT_1 (0x2UL << USART_CR3_SCARCNT_Pos)

#define	USART_CR3_SCARCNT_2 (0x4UL << USART_CR3_SCARCNT_Pos)

#define	USART_CR3_WUS_Pos (20U)

#define	USART_CR3_WUS_Msk (0x3UL << USART_CR3_WUS_Pos)

#define	USART_CR3_WUS USART_CR3_WUS_Msk

#define	USART_CR3_WUS_0 (0x1UL << USART_CR3_WUS_Pos)

#define	USART_CR3_WUS_1 (0x2UL << USART_CR3_WUS_Pos)

#define	USART_CR3_WUFIE_Pos (22U)

#define	USART_CR3_WUFIE_Msk (0x1UL << USART_CR3_WUFIE_Pos)

#define	USART_CR3_WUFIE USART_CR3_WUFIE_Msk

#define	USART_BRR_DIV_FRACTION_Pos (0U)

#define	USART_BRR_DIV_FRACTION_Msk (0xFUL << USART_BRR_DIV_FRACTION_Pos)

#define	USART_BRR_DIV_FRACTION USART_BRR_DIV_FRACTION_Msk

#define	USART_BRR_DIV_MANTISSA_Pos (4U)

#define	USART_BRR_DIV_MANTISSA_Msk (0xFFFUL << USART_BRR_DIV_MANTISSA_Pos)

#define	USART_BRR_DIV_MANTISSA USART_BRR_DIV_MANTISSA_Msk

#define	USART_GTPR_PSC_Pos (0U)

#define	USART_GTPR_PSC_Msk (0xFFUL << USART_GTPR_PSC_Pos)

#define	USART_GTPR_PSC USART_GTPR_PSC_Msk

#define	USART_GTPR_GT_Pos (8U)

#define	USART_GTPR_GT_Msk (0xFFUL << USART_GTPR_GT_Pos)

#define	USART_GTPR_GT USART_GTPR_GT_Msk

#define	USART_RTOR_RTO_Pos (0U)

#define	USART_RTOR_RTO_Msk (0xFFFFFFUL << USART_RTOR_RTO_Pos)

#define	USART_RTOR_RTO USART_RTOR_RTO_Msk

#define	USART_RTOR_BLEN_Pos (24U)

#define	USART_RTOR_BLEN_Msk (0xFFUL << USART_RTOR_BLEN_Pos)

#define	USART_RTOR_BLEN USART_RTOR_BLEN_Msk

#define	USART_RQR_ABRRQ_Pos (0U)

#define	USART_RQR_ABRRQ_Msk (0x1UL << USART_RQR_ABRRQ_Pos)

#define	USART_RQR_ABRRQ USART_RQR_ABRRQ_Msk

#define	USART_RQR_SBKRQ_Pos (1U)

#define	USART_RQR_SBKRQ_Msk (0x1UL << USART_RQR_SBKRQ_Pos)

#define	USART_RQR_SBKRQ USART_RQR_SBKRQ_Msk

#define	USART_RQR_MMRQ_Pos (2U)

#define	USART_RQR_MMRQ_Msk (0x1UL << USART_RQR_MMRQ_Pos)

#define	USART_RQR_MMRQ USART_RQR_MMRQ_Msk

#define	USART_RQR_RXFRQ_Pos (3U)

#define	USART_RQR_RXFRQ_Msk (0x1UL << USART_RQR_RXFRQ_Pos)

#define	USART_RQR_RXFRQ USART_RQR_RXFRQ_Msk

#define	USART_RQR_TXFRQ_Pos (4U)

#define	USART_RQR_TXFRQ_Msk (0x1UL << USART_RQR_TXFRQ_Pos)

#define	USART_RQR_TXFRQ USART_RQR_TXFRQ_Msk

#define	USART_ISR_PE_Pos (0U)

#define	USART_ISR_PE_Msk (0x1UL << USART_ISR_PE_Pos)

#define	USART_ISR_PE USART_ISR_PE_Msk

#define	USART_ISR_FE_Pos (1U)

#define	USART_ISR_FE_Msk (0x1UL << USART_ISR_FE_Pos)

#define	USART_ISR_FE USART_ISR_FE_Msk

#define	USART_ISR_NE_Pos (2U)

#define	USART_ISR_NE_Msk (0x1UL << USART_ISR_NE_Pos)

#define	USART_ISR_NE USART_ISR_NE_Msk

#define	USART_ISR_ORE_Pos (3U)

#define	USART_ISR_ORE_Msk (0x1UL << USART_ISR_ORE_Pos)

#define	USART_ISR_ORE USART_ISR_ORE_Msk

#define	USART_ISR_IDLE_Pos (4U)

#define	USART_ISR_IDLE_Msk (0x1UL << USART_ISR_IDLE_Pos)

#define	USART_ISR_IDLE USART_ISR_IDLE_Msk

#define	USART_ISR_RXNE_Pos (5U)

#define	USART_ISR_RXNE_Msk (0x1UL << USART_ISR_RXNE_Pos)

#define	USART_ISR_RXNE USART_ISR_RXNE_Msk

#define	USART_ISR_TC_Pos (6U)

#define	USART_ISR_TC_Msk (0x1UL << USART_ISR_TC_Pos)

#define	USART_ISR_TC USART_ISR_TC_Msk

#define	USART_ISR_TXE_Pos (7U)

#define	USART_ISR_TXE_Msk (0x1UL << USART_ISR_TXE_Pos)

#define	USART_ISR_TXE USART_ISR_TXE_Msk

#define	USART_ISR_LBDF_Pos (8U)

#define	USART_ISR_LBDF_Msk (0x1UL << USART_ISR_LBDF_Pos)

#define	USART_ISR_LBDF USART_ISR_LBDF_Msk

#define	USART_ISR_CTSIF_Pos (9U)

#define	USART_ISR_CTSIF_Msk (0x1UL << USART_ISR_CTSIF_Pos)

#define	USART_ISR_CTSIF USART_ISR_CTSIF_Msk

#define	USART_ISR_CTS_Pos (10U)

#define	USART_ISR_CTS_Msk (0x1UL << USART_ISR_CTS_Pos)

#define	USART_ISR_CTS USART_ISR_CTS_Msk

#define	USART_ISR_RTOF_Pos (11U)

#define	USART_ISR_RTOF_Msk (0x1UL << USART_ISR_RTOF_Pos)

#define	USART_ISR_RTOF USART_ISR_RTOF_Msk

#define	USART_ISR_EOBF_Pos (12U)

#define	USART_ISR_EOBF_Msk (0x1UL << USART_ISR_EOBF_Pos)

#define	USART_ISR_EOBF USART_ISR_EOBF_Msk

#define	USART_ISR_ABRE_Pos (14U)

#define	USART_ISR_ABRE_Msk (0x1UL << USART_ISR_ABRE_Pos)

#define	USART_ISR_ABRE USART_ISR_ABRE_Msk

#define	USART_ISR_ABRF_Pos (15U)

#define	USART_ISR_ABRF_Msk (0x1UL << USART_ISR_ABRF_Pos)

#define	USART_ISR_ABRF USART_ISR_ABRF_Msk

#define	USART_ISR_BUSY_Pos (16U)

#define	USART_ISR_BUSY_Msk (0x1UL << USART_ISR_BUSY_Pos)

#define	USART_ISR_BUSY USART_ISR_BUSY_Msk

#define	USART_ISR_CMF_Pos (17U)

#define	USART_ISR_CMF_Msk (0x1UL << USART_ISR_CMF_Pos)

#define	USART_ISR_CMF USART_ISR_CMF_Msk

#define	USART_ISR_SBKF_Pos (18U)

#define	USART_ISR_SBKF_Msk (0x1UL << USART_ISR_SBKF_Pos)

#define	USART_ISR_SBKF USART_ISR_SBKF_Msk

#define	USART_ISR_RWU_Pos (19U)

#define	USART_ISR_RWU_Msk (0x1UL << USART_ISR_RWU_Pos)

#define	USART_ISR_RWU USART_ISR_RWU_Msk

#define	USART_ISR_WUF_Pos (20U)

#define	USART_ISR_WUF_Msk (0x1UL << USART_ISR_WUF_Pos)

#define	USART_ISR_WUF USART_ISR_WUF_Msk

#define	USART_ISR_TEACK_Pos (21U)

#define	USART_ISR_TEACK_Msk (0x1UL << USART_ISR_TEACK_Pos)

#define	USART_ISR_TEACK USART_ISR_TEACK_Msk

#define	USART_ISR_REACK_Pos (22U)

#define	USART_ISR_REACK_Msk (0x1UL << USART_ISR_REACK_Pos)

#define	USART_ISR_REACK USART_ISR_REACK_Msk

#define	USART_ICR_PECF_Pos (0U)

#define	USART_ICR_PECF_Msk (0x1UL << USART_ICR_PECF_Pos)

#define	USART_ICR_PECF USART_ICR_PECF_Msk

#define	USART_ICR_FECF_Pos (1U)

#define	USART_ICR_FECF_Msk (0x1UL << USART_ICR_FECF_Pos)

#define	USART_ICR_FECF USART_ICR_FECF_Msk

#define	USART_ICR_NCF_Pos (2U)

#define	USART_ICR_NCF_Msk (0x1UL << USART_ICR_NCF_Pos)

#define	USART_ICR_NCF USART_ICR_NCF_Msk

#define	USART_ICR_ORECF_Pos (3U)

#define	USART_ICR_ORECF_Msk (0x1UL << USART_ICR_ORECF_Pos)

#define	USART_ICR_ORECF USART_ICR_ORECF_Msk

#define	USART_ICR_IDLECF_Pos (4U)

#define	USART_ICR_IDLECF_Msk (0x1UL << USART_ICR_IDLECF_Pos)

#define	USART_ICR_IDLECF USART_ICR_IDLECF_Msk

#define	USART_ICR_TCCF_Pos (6U)

#define	USART_ICR_TCCF_Msk (0x1UL << USART_ICR_TCCF_Pos)

#define	USART_ICR_TCCF USART_ICR_TCCF_Msk

#define	USART_ICR_LBDCF_Pos (8U)

#define	USART_ICR_LBDCF_Msk (0x1UL << USART_ICR_LBDCF_Pos)

#define	USART_ICR_LBDCF USART_ICR_LBDCF_Msk

#define	USART_ICR_CTSCF_Pos (9U)

#define	USART_ICR_CTSCF_Msk (0x1UL << USART_ICR_CTSCF_Pos)

#define	USART_ICR_CTSCF USART_ICR_CTSCF_Msk

#define	USART_ICR_RTOCF_Pos (11U)

#define	USART_ICR_RTOCF_Msk (0x1UL << USART_ICR_RTOCF_Pos)

#define	USART_ICR_RTOCF USART_ICR_RTOCF_Msk

#define	USART_ICR_EOBCF_Pos (12U)

#define	USART_ICR_EOBCF_Msk (0x1UL << USART_ICR_EOBCF_Pos)

#define	USART_ICR_EOBCF USART_ICR_EOBCF_Msk

#define	USART_ICR_CMCF_Pos (17U)

#define	USART_ICR_CMCF_Msk (0x1UL << USART_ICR_CMCF_Pos)

#define	USART_ICR_CMCF USART_ICR_CMCF_Msk

#define	USART_ICR_WUCF_Pos (20U)

#define	USART_ICR_WUCF_Msk (0x1UL << USART_ICR_WUCF_Pos)

#define	USART_ICR_WUCF USART_ICR_WUCF_Msk

#define	USART_RDR_RDR_Pos (0U)

#define	USART_RDR_RDR_Msk (0x1FFUL << USART_RDR_RDR_Pos)

#define	USART_RDR_RDR USART_RDR_RDR_Msk

#define	USART_TDR_TDR_Pos (0U)

#define	USART_TDR_TDR_Msk (0x1FFUL << USART_TDR_TDR_Pos)

#define	USART_TDR_TDR USART_TDR_TDR_Msk

#define	USB_CNTR (USB_BASE + 0x40U)

#define	USB_ISTR (USB_BASE + 0x44U)

#define	USB_FNR (USB_BASE + 0x48U)

#define	USB_DADDR (USB_BASE + 0x4CU)

#define	USB_BTABLE (USB_BASE + 0x50U)

#define	USB_LPMCSR (USB_BASE + 0x54U)

#define	USB_ISTR_CTR ((uint16_t)0x8000U)

#define	USB_ISTR_PMAOVR ((uint16_t)0x4000U)

#define	USB_ISTR_ERR ((uint16_t)0x2000U)

#define	USB_ISTR_WKUP ((uint16_t)0x1000U)

#define	USB_ISTR_SUSP ((uint16_t)0x0800U)

#define	USB_ISTR_RESET ((uint16_t)0x0400U)

#define	USB_ISTR_SOF ((uint16_t)0x0200U)

#define	USB_ISTR_ESOF ((uint16_t)0x0100U)

#define	USB_ISTR_L1REQ ((uint16_t)0x0080U)

#define	USB_ISTR_DIR ((uint16_t)0x0010U)

#define	USB_ISTR_EP_ID ((uint16_t)0x000FU)

#define	USB_ISTR_PMAOVRM USB_ISTR_PMAOVR

#define	USB_CLR_CTR (~USB_ISTR_CTR)

#define	USB_CLR_PMAOVR (~USB_ISTR_PMAOVR)

#define	USB_CLR_ERR (~USB_ISTR_ERR)

#define	USB_CLR_WKUP (~USB_ISTR_WKUP)

#define	USB_CLR_SUSP (~USB_ISTR_SUSP)

#define	USB_CLR_RESET (~USB_ISTR_RESET)

#define	USB_CLR_SOF (~USB_ISTR_SOF)

#define	USB_CLR_ESOF (~USB_ISTR_ESOF)

#define	USB_CLR_L1REQ (~USB_ISTR_L1REQ)

#define	USB_CLR_PMAOVRM USB_CLR_PMAOVR

#define	USB_CNTR_CTRM ((uint16_t)0x8000U)

#define	USB_CNTR_PMAOVR ((uint16_t)0x4000U)

#define	USB_CNTR_ERRM ((uint16_t)0x2000U)

#define	USB_CNTR_WKUPM ((uint16_t)0x1000U)

#define	USB_CNTR_SUSPM ((uint16_t)0x0800U)

#define	USB_CNTR_RESETM ((uint16_t)0x0400U)

#define	USB_CNTR_SOFM ((uint16_t)0x0200U)

#define	USB_CNTR_ESOFM ((uint16_t)0x0100U)

#define	USB_CNTR_L1REQM ((uint16_t)0x0080U)

#define	USB_CNTR_L1RESUME ((uint16_t)0x0020U)

#define	USB_CNTR_RESUME ((uint16_t)0x0010U)

#define	USB_CNTR_FSUSP ((uint16_t)0x0008U)

#define	USB_CNTR_LPMODE ((uint16_t)0x0004U)

#define	USB_CNTR_PDWN ((uint16_t)0x0002U)

#define	USB_CNTR_FRES ((uint16_t)0x0001U)

#define	USB_CNTR_PMAOVRM USB_CNTR_PMAOVR

#define	USB_CNTR_LP_MODE USB_CNTR_LPMODE

#define	USB_LPMCSR_BESL ((uint16_t)0x00F0U)

#define	USB_LPMCSR_REMWAKE ((uint16_t)0x0008U)

#define	USB_LPMCSR_LPMACK ((uint16_t)0x0002U)

#define	USB_LPMCSR_LMPEN ((uint16_t)0x0001U)

#define	USB_FNR_RXDP ((uint16_t)0x8000U)

#define	USB_FNR_RXDM ((uint16_t)0x4000U)

#define	USB_FNR_LCK ((uint16_t)0x2000U)

#define	USB_FNR_LSOF ((uint16_t)0x1800U)

#define	USB_FNR_FN ((uint16_t)0x07FFU)

#define	USB_DADDR_EF ((uint8_t)0x80U)

#define	USB_DADDR_ADD ((uint8_t)0x7FU)

#define	USB_EP0R USB_BASE

#define	USB_EP1R (USB_BASE + 0x04U)

#define	USB_EP2R (USB_BASE + 0x08U)

#define	USB_EP3R (USB_BASE + 0x0CU)

#define	USB_EP4R (USB_BASE + 0x10U)

#define	USB_EP5R (USB_BASE + 0x14U)

#define	USB_EP6R (USB_BASE + 0x18U)

#define	USB_EP7R (USB_BASE + 0x1CU)

#define	USB_EP_CTR_RX ((uint16_t)0x8000U)

#define	USB_EP_DTOG_RX ((uint16_t)0x4000U)

#define	USB_EPRX_STAT ((uint16_t)0x3000U)

#define	USB_EP_SETUP ((uint16_t)0x0800U)

#define	USB_EP_T_FIELD ((uint16_t)0x0600U)

#define	USB_EP_KIND ((uint16_t)0x0100U)

#define	USB_EP_CTR_TX ((uint16_t)0x0080U)

#define	USB_EP_DTOG_TX ((uint16_t)0x0040U)

#define	USB_EPTX_STAT ((uint16_t)0x0030U)

#define	USB_EPADDR_FIELD ((uint16_t)0x000FU)

#define	USB_EPREG_MASK (USB_EP_CTR_RX\|USB_EP_SETUP\|USB_EP_T_FIELD\|USB_EP_KIND\|USB_EP_CTR_TX\|USB_EPADDR_FIELD)

#define	USB_EP_TYPE_MASK ((uint16_t)0x0600U)

#define	USB_EP_BULK ((uint16_t)0x0000U)

#define	USB_EP_CONTROL ((uint16_t)0x0200U)

#define	USB_EP_ISOCHRONOUS ((uint16_t)0x0400U)

#define	USB_EP_INTERRUPT ((uint16_t)0x0600U)

#define	USB_EP_T_MASK ((uint16_t) ~USB_EP_T_FIELD & USB_EPREG_MASK)

#define	USB_EPKIND_MASK ((uint16_t) ~USB_EP_KIND & USB_EPREG_MASK)

#define	USB_EP_TX_DIS ((uint16_t)0x0000U)

#define	USB_EP_TX_STALL ((uint16_t)0x0010U)

#define	USB_EP_TX_NAK ((uint16_t)0x0020U)

#define	USB_EP_TX_VALID ((uint16_t)0x0030U)

#define	USB_EPTX_DTOG1 ((uint16_t)0x0010U)

#define	USB_EPTX_DTOG2 ((uint16_t)0x0020U)

#define	USB_EPTX_DTOGMASK (USB_EPTX_STAT\|USB_EPREG_MASK)

#define	USB_EP_RX_DIS ((uint16_t)0x0000U)

#define	USB_EP_RX_STALL ((uint16_t)0x1000U)

#define	USB_EP_RX_NAK ((uint16_t)0x2000U)

#define	USB_EP_RX_VALID ((uint16_t)0x3000U)

#define	USB_EPRX_DTOG1 ((uint16_t)0x1000U)

#define	USB_EPRX_DTOG2 ((uint16_t)0x2000U)

#define	USB_EPRX_DTOGMASK (USB_EPRX_STAT\|USB_EPREG_MASK)

#define	WWDG_CR_T_Pos (0U)

#define	WWDG_CR_T_Msk (0x7FUL << WWDG_CR_T_Pos)

#define	WWDG_CR_T WWDG_CR_T_Msk

#define	WWDG_CR_T_0 (0x01UL << WWDG_CR_T_Pos)

#define	WWDG_CR_T_1 (0x02UL << WWDG_CR_T_Pos)

#define	WWDG_CR_T_2 (0x04UL << WWDG_CR_T_Pos)

#define	WWDG_CR_T_3 (0x08UL << WWDG_CR_T_Pos)

#define	WWDG_CR_T_4 (0x10UL << WWDG_CR_T_Pos)

#define	WWDG_CR_T_5 (0x20UL << WWDG_CR_T_Pos)

#define	WWDG_CR_T_6 (0x40UL << WWDG_CR_T_Pos)

#define	WWDG_CR_T0 WWDG_CR_T_0

#define	WWDG_CR_T1 WWDG_CR_T_1

#define	WWDG_CR_T2 WWDG_CR_T_2

#define	WWDG_CR_T3 WWDG_CR_T_3

#define	WWDG_CR_T4 WWDG_CR_T_4

#define	WWDG_CR_T5 WWDG_CR_T_5

#define	WWDG_CR_T6 WWDG_CR_T_6

#define	WWDG_CR_WDGA_Pos (7U)

#define	WWDG_CR_WDGA_Msk (0x1UL << WWDG_CR_WDGA_Pos)

#define	WWDG_CR_WDGA WWDG_CR_WDGA_Msk

#define	WWDG_CFR_W_Pos (0U)

#define	WWDG_CFR_W_Msk (0x7FUL << WWDG_CFR_W_Pos)

#define	WWDG_CFR_W WWDG_CFR_W_Msk

#define	WWDG_CFR_W_0 (0x01UL << WWDG_CFR_W_Pos)

#define	WWDG_CFR_W_1 (0x02UL << WWDG_CFR_W_Pos)

#define	WWDG_CFR_W_2 (0x04UL << WWDG_CFR_W_Pos)

#define	WWDG_CFR_W_3 (0x08UL << WWDG_CFR_W_Pos)

#define	WWDG_CFR_W_4 (0x10UL << WWDG_CFR_W_Pos)

#define	WWDG_CFR_W_5 (0x20UL << WWDG_CFR_W_Pos)

#define	WWDG_CFR_W_6 (0x40UL << WWDG_CFR_W_Pos)

#define	WWDG_CFR_W0 WWDG_CFR_W_0

#define	WWDG_CFR_W1 WWDG_CFR_W_1

#define	WWDG_CFR_W2 WWDG_CFR_W_2

#define	WWDG_CFR_W3 WWDG_CFR_W_3

#define	WWDG_CFR_W4 WWDG_CFR_W_4

#define	WWDG_CFR_W5 WWDG_CFR_W_5

#define	WWDG_CFR_W6 WWDG_CFR_W_6

#define	WWDG_CFR_WDGTB_Pos (7U)

#define	WWDG_CFR_WDGTB_Msk (0x3UL << WWDG_CFR_WDGTB_Pos)

#define	WWDG_CFR_WDGTB WWDG_CFR_WDGTB_Msk

#define	WWDG_CFR_WDGTB_0 (0x1UL << WWDG_CFR_WDGTB_Pos)

#define	WWDG_CFR_WDGTB_1 (0x2UL << WWDG_CFR_WDGTB_Pos)

#define	WWDG_CFR_WDGTB0 WWDG_CFR_WDGTB_0

#define	WWDG_CFR_WDGTB1 WWDG_CFR_WDGTB_1

#define	WWDG_CFR_EWI_Pos (9U)

#define	WWDG_CFR_EWI_Msk (0x1UL << WWDG_CFR_EWI_Pos)

#define	WWDG_CFR_EWI WWDG_CFR_EWI_Msk

#define	WWDG_SR_EWIF_Pos (0U)

#define	WWDG_SR_EWIF_Msk (0x1UL << WWDG_SR_EWIF_Pos)

#define	WWDG_SR_EWIF WWDG_SR_EWIF_Msk

Detailed Description

Macro Definition Documentation

◆ ADC12_CCR_CKMODE

#define ADC12_CCR_CKMODE ADC12_CCR_CKMODE_Msk

ADC clock mode

◆ ADC12_CCR_CKMODE_0

#define ADC12_CCR_CKMODE_0 (0x1UL << ADC12_CCR_CKMODE_Pos)

0x00010000

◆ ADC12_CCR_CKMODE_1

#define ADC12_CCR_CKMODE_1 (0x2UL << ADC12_CCR_CKMODE_Pos)

0x00020000

◆ ADC12_CCR_CKMODE_Msk

#define ADC12_CCR_CKMODE_Msk (0x3UL << ADC12_CCR_CKMODE_Pos)

0x00030000

◆ ADC12_CCR_CKMODE_Pos

#define ADC12_CCR_CKMODE_Pos (16U)

◆ ADC12_CCR_DELAY

#define ADC12_CCR_DELAY ADC12_CCR_DELAY_Msk

Delay between 2 sampling phases

◆ ADC12_CCR_DELAY_0

#define ADC12_CCR_DELAY_0 (0x1UL << ADC12_CCR_DELAY_Pos)

0x00000100

◆ ADC12_CCR_DELAY_1

#define ADC12_CCR_DELAY_1 (0x2UL << ADC12_CCR_DELAY_Pos)

0x00000200

◆ ADC12_CCR_DELAY_2

#define ADC12_CCR_DELAY_2 (0x4UL << ADC12_CCR_DELAY_Pos)

0x00000400

◆ ADC12_CCR_DELAY_3

#define ADC12_CCR_DELAY_3 (0x8UL << ADC12_CCR_DELAY_Pos)

0x00000800

◆ ADC12_CCR_DELAY_Msk

#define ADC12_CCR_DELAY_Msk (0xFUL << ADC12_CCR_DELAY_Pos)

0x00000F00

◆ ADC12_CCR_DELAY_Pos

#define ADC12_CCR_DELAY_Pos (8U)

◆ ADC12_CCR_DMACFG

#define ADC12_CCR_DMACFG ADC12_CCR_DMACFG_Msk

DMA configuration for multi-ADC mode

◆ ADC12_CCR_DMACFG_Msk

#define ADC12_CCR_DMACFG_Msk (0x1UL << ADC12_CCR_DMACFG_Pos)

0x00002000

◆ ADC12_CCR_DMACFG_Pos

#define ADC12_CCR_DMACFG_Pos (13U)

◆ ADC12_CCR_MDMA

#define ADC12_CCR_MDMA ADC12_CCR_MDMA_Msk

DMA mode for multi-ADC mode

◆ ADC12_CCR_MDMA_0

#define ADC12_CCR_MDMA_0 (0x1UL << ADC12_CCR_MDMA_Pos)

0x00004000

◆ ADC12_CCR_MDMA_1

#define ADC12_CCR_MDMA_1 (0x2UL << ADC12_CCR_MDMA_Pos)

0x00008000

◆ ADC12_CCR_MDMA_Msk

#define ADC12_CCR_MDMA_Msk (0x3UL << ADC12_CCR_MDMA_Pos)

0x0000C000

◆ ADC12_CCR_MDMA_Pos

#define ADC12_CCR_MDMA_Pos (14U)

◆ ADC12_CCR_MULTI

#define ADC12_CCR_MULTI ADC12_CCR_MULTI_Msk

Multi ADC mode selection

◆ ADC12_CCR_MULTI_0

#define ADC12_CCR_MULTI_0 (0x01UL << ADC12_CCR_MULTI_Pos)

0x00000001

◆ ADC12_CCR_MULTI_1

#define ADC12_CCR_MULTI_1 (0x02UL << ADC12_CCR_MULTI_Pos)

0x00000002

◆ ADC12_CCR_MULTI_2

#define ADC12_CCR_MULTI_2 (0x04UL << ADC12_CCR_MULTI_Pos)

0x00000004

◆ ADC12_CCR_MULTI_3

#define ADC12_CCR_MULTI_3 (0x08UL << ADC12_CCR_MULTI_Pos)

0x00000008

◆ ADC12_CCR_MULTI_4

#define ADC12_CCR_MULTI_4 (0x10UL << ADC12_CCR_MULTI_Pos)

0x00000010

◆ ADC12_CCR_MULTI_Msk

#define ADC12_CCR_MULTI_Msk (0x1FUL << ADC12_CCR_MULTI_Pos)

0x0000001F

◆ ADC12_CCR_MULTI_Pos

#define ADC12_CCR_MULTI_Pos (0U)

◆ ADC12_CCR_TSEN

#define ADC12_CCR_TSEN ADC12_CCR_TSEN_Msk

Temperature sensor enable

◆ ADC12_CCR_TSEN_Msk

#define ADC12_CCR_TSEN_Msk (0x1UL << ADC12_CCR_TSEN_Pos)

0x00800000

◆ ADC12_CCR_TSEN_Pos

#define ADC12_CCR_TSEN_Pos (23U)

◆ ADC12_CCR_VBATEN

#define ADC12_CCR_VBATEN ADC12_CCR_VBATEN_Msk

VBAT enable

◆ ADC12_CCR_VBATEN_Msk

#define ADC12_CCR_VBATEN_Msk (0x1UL << ADC12_CCR_VBATEN_Pos)

0x01000000

◆ ADC12_CCR_VBATEN_Pos

#define ADC12_CCR_VBATEN_Pos (24U)

◆ ADC12_CCR_VREFEN

#define ADC12_CCR_VREFEN ADC12_CCR_VREFEN_Msk

VREFINT enable

◆ ADC12_CCR_VREFEN_Msk

#define ADC12_CCR_VREFEN_Msk (0x1UL << ADC12_CCR_VREFEN_Pos)

0x00400000

◆ ADC12_CCR_VREFEN_Pos

#define ADC12_CCR_VREFEN_Pos (22U)

◆ ADC12_CDR_RDATA_MST

#define ADC12_CDR_RDATA_MST ADC12_CDR_RDATA_MST_Msk

Regular Data of the master ADC

◆ ADC12_CDR_RDATA_MST_0

#define ADC12_CDR_RDATA_MST_0 (0x0001UL << ADC12_CDR_RDATA_MST_Pos)

0x00000001

◆ ADC12_CDR_RDATA_MST_1

#define ADC12_CDR_RDATA_MST_1 (0x0002UL << ADC12_CDR_RDATA_MST_Pos)

0x00000002

◆ ADC12_CDR_RDATA_MST_10

#define ADC12_CDR_RDATA_MST_10 (0x0400UL << ADC12_CDR_RDATA_MST_Pos)

0x00000400

◆ ADC12_CDR_RDATA_MST_11

#define ADC12_CDR_RDATA_MST_11 (0x0800UL << ADC12_CDR_RDATA_MST_Pos)

0x00000800

◆ ADC12_CDR_RDATA_MST_12

#define ADC12_CDR_RDATA_MST_12 (0x1000UL << ADC12_CDR_RDATA_MST_Pos)

0x00001000

◆ ADC12_CDR_RDATA_MST_13

#define ADC12_CDR_RDATA_MST_13 (0x2000UL << ADC12_CDR_RDATA_MST_Pos)

0x00002000

◆ ADC12_CDR_RDATA_MST_14

#define ADC12_CDR_RDATA_MST_14 (0x4000UL << ADC12_CDR_RDATA_MST_Pos)

0x00004000

◆ ADC12_CDR_RDATA_MST_15

#define ADC12_CDR_RDATA_MST_15 (0x8000UL << ADC12_CDR_RDATA_MST_Pos)

0x00008000

◆ ADC12_CDR_RDATA_MST_2

#define ADC12_CDR_RDATA_MST_2 (0x0004UL << ADC12_CDR_RDATA_MST_Pos)

0x00000004

◆ ADC12_CDR_RDATA_MST_3

#define ADC12_CDR_RDATA_MST_3 (0x0008UL << ADC12_CDR_RDATA_MST_Pos)

0x00000008

◆ ADC12_CDR_RDATA_MST_4

#define ADC12_CDR_RDATA_MST_4 (0x0010UL << ADC12_CDR_RDATA_MST_Pos)

0x00000010

◆ ADC12_CDR_RDATA_MST_5

#define ADC12_CDR_RDATA_MST_5 (0x0020UL << ADC12_CDR_RDATA_MST_Pos)

0x00000020

◆ ADC12_CDR_RDATA_MST_6

#define ADC12_CDR_RDATA_MST_6 (0x0040UL << ADC12_CDR_RDATA_MST_Pos)

0x00000040

◆ ADC12_CDR_RDATA_MST_7

#define ADC12_CDR_RDATA_MST_7 (0x0080UL << ADC12_CDR_RDATA_MST_Pos)

0x00000080

◆ ADC12_CDR_RDATA_MST_8

#define ADC12_CDR_RDATA_MST_8 (0x0100UL << ADC12_CDR_RDATA_MST_Pos)

0x00000100

◆ ADC12_CDR_RDATA_MST_9

#define ADC12_CDR_RDATA_MST_9 (0x0200UL << ADC12_CDR_RDATA_MST_Pos)

0x00000200

◆ ADC12_CDR_RDATA_MST_Msk

#define ADC12_CDR_RDATA_MST_Msk (0xFFFFUL << ADC12_CDR_RDATA_MST_Pos)

0x0000FFFF

◆ ADC12_CDR_RDATA_MST_Pos

#define ADC12_CDR_RDATA_MST_Pos (0U)

◆ ADC12_CDR_RDATA_SLV

#define ADC12_CDR_RDATA_SLV ADC12_CDR_RDATA_SLV_Msk

Regular Data of the master ADC

◆ ADC12_CDR_RDATA_SLV_0

#define ADC12_CDR_RDATA_SLV_0 (0x0001UL << ADC12_CDR_RDATA_SLV_Pos)

0x00010000

◆ ADC12_CDR_RDATA_SLV_1

#define ADC12_CDR_RDATA_SLV_1 (0x0002UL << ADC12_CDR_RDATA_SLV_Pos)

0x00020000

◆ ADC12_CDR_RDATA_SLV_10

#define ADC12_CDR_RDATA_SLV_10 (0x0400UL << ADC12_CDR_RDATA_SLV_Pos)

0x04000000

◆ ADC12_CDR_RDATA_SLV_11

#define ADC12_CDR_RDATA_SLV_11 (0x0800UL << ADC12_CDR_RDATA_SLV_Pos)

0x08000000

◆ ADC12_CDR_RDATA_SLV_12

#define ADC12_CDR_RDATA_SLV_12 (0x1000UL << ADC12_CDR_RDATA_SLV_Pos)

0x10000000

◆ ADC12_CDR_RDATA_SLV_13

#define ADC12_CDR_RDATA_SLV_13 (0x2000UL << ADC12_CDR_RDATA_SLV_Pos)

0x20000000

◆ ADC12_CDR_RDATA_SLV_14

#define ADC12_CDR_RDATA_SLV_14 (0x4000UL << ADC12_CDR_RDATA_SLV_Pos)

0x40000000

◆ ADC12_CDR_RDATA_SLV_15

#define ADC12_CDR_RDATA_SLV_15 (0x8000UL << ADC12_CDR_RDATA_SLV_Pos)

0x80000000

◆ ADC12_CDR_RDATA_SLV_2

#define ADC12_CDR_RDATA_SLV_2 (0x0004UL << ADC12_CDR_RDATA_SLV_Pos)

0x00040000

◆ ADC12_CDR_RDATA_SLV_3

#define ADC12_CDR_RDATA_SLV_3 (0x0008UL << ADC12_CDR_RDATA_SLV_Pos)

0x00080000

◆ ADC12_CDR_RDATA_SLV_4

#define ADC12_CDR_RDATA_SLV_4 (0x0010UL << ADC12_CDR_RDATA_SLV_Pos)

0x00100000

◆ ADC12_CDR_RDATA_SLV_5

#define ADC12_CDR_RDATA_SLV_5 (0x0020UL << ADC12_CDR_RDATA_SLV_Pos)

0x00200000

◆ ADC12_CDR_RDATA_SLV_6

#define ADC12_CDR_RDATA_SLV_6 (0x0040UL << ADC12_CDR_RDATA_SLV_Pos)

0x00400000

◆ ADC12_CDR_RDATA_SLV_7

#define ADC12_CDR_RDATA_SLV_7 (0x0080UL << ADC12_CDR_RDATA_SLV_Pos)

0x00800000

◆ ADC12_CDR_RDATA_SLV_8

#define ADC12_CDR_RDATA_SLV_8 (0x0100UL << ADC12_CDR_RDATA_SLV_Pos)

0x01000000

◆ ADC12_CDR_RDATA_SLV_9

#define ADC12_CDR_RDATA_SLV_9 (0x0200UL << ADC12_CDR_RDATA_SLV_Pos)

0x02000000

◆ ADC12_CDR_RDATA_SLV_Msk

#define ADC12_CDR_RDATA_SLV_Msk (0xFFFFUL << ADC12_CDR_RDATA_SLV_Pos)

0xFFFF0000

◆ ADC12_CDR_RDATA_SLV_Pos

#define ADC12_CDR_RDATA_SLV_Pos (16U)

◆ ADC12_CSR_ADRDY_EOC_MST

#define ADC12_CSR_ADRDY_EOC_MST ADC12_CSR_ADRDY_EOC_MST_Msk

End of regular conversion of the master ADC

◆ ADC12_CSR_ADRDY_EOC_MST_Msk

#define ADC12_CSR_ADRDY_EOC_MST_Msk (0x1UL << ADC12_CSR_ADRDY_EOC_MST_Pos)

0x00000004

◆ ADC12_CSR_ADRDY_EOC_MST_Pos

#define ADC12_CSR_ADRDY_EOC_MST_Pos (2U)

◆ ADC12_CSR_ADRDY_EOC_SLV

#define ADC12_CSR_ADRDY_EOC_SLV ADC12_CSR_ADRDY_EOC_SLV_Msk

End of regular conversion of the slave ADC

◆ ADC12_CSR_ADRDY_EOC_SLV_Msk

#define ADC12_CSR_ADRDY_EOC_SLV_Msk (0x1UL << ADC12_CSR_ADRDY_EOC_SLV_Pos)

0x00040000

◆ ADC12_CSR_ADRDY_EOC_SLV_Pos

#define ADC12_CSR_ADRDY_EOC_SLV_Pos (18U)

◆ ADC12_CSR_ADRDY_EOS_MST

#define ADC12_CSR_ADRDY_EOS_MST ADC12_CSR_ADRDY_EOS_MST_Msk

End of regular sequence flag of the master ADC

◆ ADC12_CSR_ADRDY_EOS_MST_Msk

#define ADC12_CSR_ADRDY_EOS_MST_Msk (0x1UL << ADC12_CSR_ADRDY_EOS_MST_Pos)

0x00000008

◆ ADC12_CSR_ADRDY_EOS_MST_Pos

#define ADC12_CSR_ADRDY_EOS_MST_Pos (3U)

◆ ADC12_CSR_ADRDY_EOS_SLV

#define ADC12_CSR_ADRDY_EOS_SLV ADC12_CSR_ADRDY_EOS_SLV_Msk

End of regular sequence flag of the slave ADC

◆ ADC12_CSR_ADRDY_EOS_SLV_Msk

#define ADC12_CSR_ADRDY_EOS_SLV_Msk (0x1UL << ADC12_CSR_ADRDY_EOS_SLV_Pos)

0x00080000

◆ ADC12_CSR_ADRDY_EOS_SLV_Pos

#define ADC12_CSR_ADRDY_EOS_SLV_Pos (19U)

◆ ADC12_CSR_ADRDY_EOSMP_MST

#define ADC12_CSR_ADRDY_EOSMP_MST ADC12_CSR_ADRDY_EOSMP_MST_Msk

End of sampling phase flag of the master ADC

◆ ADC12_CSR_ADRDY_EOSMP_MST_Msk

#define ADC12_CSR_ADRDY_EOSMP_MST_Msk (0x1UL << ADC12_CSR_ADRDY_EOSMP_MST_Pos)

0x00000002

◆ ADC12_CSR_ADRDY_EOSMP_MST_Pos

#define ADC12_CSR_ADRDY_EOSMP_MST_Pos (1U)

◆ ADC12_CSR_ADRDY_EOSMP_SLV

#define ADC12_CSR_ADRDY_EOSMP_SLV ADC12_CSR_ADRDY_EOSMP_SLV_Msk

End of sampling phase flag of the slave ADC

◆ ADC12_CSR_ADRDY_EOSMP_SLV_Msk

#define ADC12_CSR_ADRDY_EOSMP_SLV_Msk (0x1UL << ADC12_CSR_ADRDY_EOSMP_SLV_Pos)

0x00020000

◆ ADC12_CSR_ADRDY_EOSMP_SLV_Pos

#define ADC12_CSR_ADRDY_EOSMP_SLV_Pos (17U)

◆ ADC12_CSR_ADRDY_JEOC_MST

#define ADC12_CSR_ADRDY_JEOC_MST ADC12_CSR_ADRDY_JEOC_MST_Msk

End of injected conversion of the master ADC

◆ ADC12_CSR_ADRDY_JEOC_MST_Msk

#define ADC12_CSR_ADRDY_JEOC_MST_Msk (0x1UL << ADC12_CSR_ADRDY_JEOC_MST_Pos)

0x00000020

◆ ADC12_CSR_ADRDY_JEOC_MST_Pos

#define ADC12_CSR_ADRDY_JEOC_MST_Pos (5U)

◆ ADC12_CSR_ADRDY_JEOC_SLV

#define ADC12_CSR_ADRDY_JEOC_SLV ADC12_CSR_ADRDY_JEOC_SLV_Msk

End of injected conversion of the slave ADC

◆ ADC12_CSR_ADRDY_JEOC_SLV_Msk

#define ADC12_CSR_ADRDY_JEOC_SLV_Msk (0x1UL << ADC12_CSR_ADRDY_JEOC_SLV_Pos)

0x00200000

◆ ADC12_CSR_ADRDY_JEOC_SLV_Pos

#define ADC12_CSR_ADRDY_JEOC_SLV_Pos (21U)

◆ ADC12_CSR_ADRDY_JEOS_MST

#define ADC12_CSR_ADRDY_JEOS_MST ADC12_CSR_ADRDY_JEOS_MST_Msk

End of injected sequence flag of the master ADC

◆ ADC12_CSR_ADRDY_JEOS_MST_Msk

#define ADC12_CSR_ADRDY_JEOS_MST_Msk (0x1UL << ADC12_CSR_ADRDY_JEOS_MST_Pos)

0x00000040

◆ ADC12_CSR_ADRDY_JEOS_MST_Pos

#define ADC12_CSR_ADRDY_JEOS_MST_Pos (6U)

◆ ADC12_CSR_ADRDY_JEOS_SLV

#define ADC12_CSR_ADRDY_JEOS_SLV ADC12_CSR_ADRDY_JEOS_SLV_Msk

End of injected sequence flag of the slave ADC

◆ ADC12_CSR_ADRDY_JEOS_SLV_Msk

#define ADC12_CSR_ADRDY_JEOS_SLV_Msk (0x1UL << ADC12_CSR_ADRDY_JEOS_SLV_Pos)

0x00400000

◆ ADC12_CSR_ADRDY_JEOS_SLV_Pos

#define ADC12_CSR_ADRDY_JEOS_SLV_Pos (22U)

◆ ADC12_CSR_ADRDY_MST

#define ADC12_CSR_ADRDY_MST ADC12_CSR_ADRDY_MST_Msk

Master ADC ready

◆ ADC12_CSR_ADRDY_MST_Msk

#define ADC12_CSR_ADRDY_MST_Msk (0x1UL << ADC12_CSR_ADRDY_MST_Pos)

0x00000001

◆ ADC12_CSR_ADRDY_MST_Pos

#define ADC12_CSR_ADRDY_MST_Pos (0U)

◆ ADC12_CSR_ADRDY_OVR_MST

#define ADC12_CSR_ADRDY_OVR_MST ADC12_CSR_ADRDY_OVR_MST_Msk

Overrun flag of the master ADC

◆ ADC12_CSR_ADRDY_OVR_MST_Msk

#define ADC12_CSR_ADRDY_OVR_MST_Msk (0x1UL << ADC12_CSR_ADRDY_OVR_MST_Pos)

0x00000010

◆ ADC12_CSR_ADRDY_OVR_MST_Pos

#define ADC12_CSR_ADRDY_OVR_MST_Pos (4U)

◆ ADC12_CSR_ADRDY_OVR_SLV [1/2]

#define ADC12_CSR_ADRDY_OVR_SLV ADC12_CSR_ADRDY_OVR_SLV_Msk

Overrun flag of the slave ADC

◆ ADC12_CSR_ADRDY_OVR_SLV [2/2]

#define ADC12_CSR_ADRDY_OVR_SLV ADC12_CSR_ADRDY_OVR_SLV_Msk

Overrun flag of the slave ADC

◆ ADC12_CSR_ADRDY_OVR_SLV_Msk [1/2]

#define ADC12_CSR_ADRDY_OVR_SLV_Msk (0x1UL << ADC12_CSR_ADRDY_OVR_SLV_Pos)

0x00100000

◆ ADC12_CSR_ADRDY_OVR_SLV_Msk [2/2]

#define ADC12_CSR_ADRDY_OVR_SLV_Msk (0x1UL << ADC12_CSR_ADRDY_OVR_SLV_Pos)

0x00100000

◆ ADC12_CSR_ADRDY_OVR_SLV_Pos [1/2]

#define ADC12_CSR_ADRDY_OVR_SLV_Pos (20U)

◆ ADC12_CSR_ADRDY_OVR_SLV_Pos [2/2]

#define ADC12_CSR_ADRDY_OVR_SLV_Pos (20U)

◆ ADC12_CSR_ADRDY_SLV

#define ADC12_CSR_ADRDY_SLV ADC12_CSR_ADRDY_SLV_Msk

Slave ADC ready

◆ ADC12_CSR_ADRDY_SLV_Msk

#define ADC12_CSR_ADRDY_SLV_Msk (0x1UL << ADC12_CSR_ADRDY_SLV_Pos)

0x00010000

◆ ADC12_CSR_ADRDY_SLV_Pos

#define ADC12_CSR_ADRDY_SLV_Pos (16U)

◆ ADC12_CSR_AWD1_MST

#define ADC12_CSR_AWD1_MST ADC12_CSR_AWD1_MST_Msk

Analog watchdog 1 flag of the master ADC

◆ ADC12_CSR_AWD1_MST_Msk

#define ADC12_CSR_AWD1_MST_Msk (0x1UL << ADC12_CSR_AWD1_MST_Pos)

0x00000080

◆ ADC12_CSR_AWD1_MST_Pos

#define ADC12_CSR_AWD1_MST_Pos (7U)

◆ ADC12_CSR_AWD1_SLV

#define ADC12_CSR_AWD1_SLV ADC12_CSR_AWD1_SLV_Msk

Analog watchdog 1 flag of the slave ADC

◆ ADC12_CSR_AWD1_SLV_Msk

#define ADC12_CSR_AWD1_SLV_Msk (0x1UL << ADC12_CSR_AWD1_SLV_Pos)

0x00800000

◆ ADC12_CSR_AWD1_SLV_Pos

#define ADC12_CSR_AWD1_SLV_Pos (23U)

◆ ADC12_CSR_AWD2_MST

#define ADC12_CSR_AWD2_MST ADC12_CSR_AWD2_MST_Msk

Analog watchdog 2 flag of the master ADC

◆ ADC12_CSR_AWD2_MST_Msk

#define ADC12_CSR_AWD2_MST_Msk (0x1UL << ADC12_CSR_AWD2_MST_Pos)

0x00000100

◆ ADC12_CSR_AWD2_MST_Pos

#define ADC12_CSR_AWD2_MST_Pos (8U)

◆ ADC12_CSR_AWD2_SLV

#define ADC12_CSR_AWD2_SLV ADC12_CSR_AWD2_SLV_Msk

Analog watchdog 2 flag of the slave ADC

◆ ADC12_CSR_AWD2_SLV_Msk

#define ADC12_CSR_AWD2_SLV_Msk (0x1UL << ADC12_CSR_AWD2_SLV_Pos)

0x01000000

◆ ADC12_CSR_AWD2_SLV_Pos

#define ADC12_CSR_AWD2_SLV_Pos (24U)

◆ ADC12_CSR_AWD3_MST

#define ADC12_CSR_AWD3_MST ADC12_CSR_AWD3_MST_Msk

Analog watchdog 3 flag of the master ADC

◆ ADC12_CSR_AWD3_MST_Msk

#define ADC12_CSR_AWD3_MST_Msk (0x1UL << ADC12_CSR_AWD3_MST_Pos)

0x00000200

◆ ADC12_CSR_AWD3_MST_Pos

#define ADC12_CSR_AWD3_MST_Pos (9U)

◆ ADC12_CSR_AWD3_SLV

#define ADC12_CSR_AWD3_SLV ADC12_CSR_AWD3_SLV_Msk

Analog watchdog 3 flag of the slave ADC

◆ ADC12_CSR_AWD3_SLV_Msk

#define ADC12_CSR_AWD3_SLV_Msk (0x1UL << ADC12_CSR_AWD3_SLV_Pos)

0x02000000

◆ ADC12_CSR_AWD3_SLV_Pos

#define ADC12_CSR_AWD3_SLV_Pos (25U)

◆ ADC12_CSR_JQOVF_MST

#define ADC12_CSR_JQOVF_MST ADC12_CSR_JQOVF_MST_Msk

Injected context queue overflow flag of the master ADC

◆ ADC12_CSR_JQOVF_MST_Msk

#define ADC12_CSR_JQOVF_MST_Msk (0x1UL << ADC12_CSR_JQOVF_MST_Pos)

0x00000400

◆ ADC12_CSR_JQOVF_MST_Pos

#define ADC12_CSR_JQOVF_MST_Pos (10U)

◆ ADC12_CSR_JQOVF_SLV

#define ADC12_CSR_JQOVF_SLV ADC12_CSR_JQOVF_SLV_Msk

Injected context queue overflow flag of the slave ADC

◆ ADC12_CSR_JQOVF_SLV_Msk

#define ADC12_CSR_JQOVF_SLV_Msk (0x1UL << ADC12_CSR_JQOVF_SLV_Pos)

0x04000000

◆ ADC12_CSR_JQOVF_SLV_Pos

#define ADC12_CSR_JQOVF_SLV_Pos (26U)

◆ ADC34_CCR_CKMODE

#define ADC34_CCR_CKMODE ADC34_CCR_CKMODE_Msk

ADC clock mode

◆ ADC34_CCR_CKMODE_0

#define ADC34_CCR_CKMODE_0 (0x1UL << ADC34_CCR_CKMODE_Pos)

0x00010000

◆ ADC34_CCR_CKMODE_1

#define ADC34_CCR_CKMODE_1 (0x2UL << ADC34_CCR_CKMODE_Pos)

0x00020000

◆ ADC34_CCR_CKMODE_Msk

#define ADC34_CCR_CKMODE_Msk (0x3UL << ADC34_CCR_CKMODE_Pos)

0x00030000

◆ ADC34_CCR_CKMODE_Pos

#define ADC34_CCR_CKMODE_Pos (16U)

◆ ADC34_CCR_DELAY

#define ADC34_CCR_DELAY ADC34_CCR_DELAY_Msk

Delay between 2 sampling phases

◆ ADC34_CCR_DELAY_0

#define ADC34_CCR_DELAY_0 (0x1UL << ADC34_CCR_DELAY_Pos)

0x00000100

◆ ADC34_CCR_DELAY_1

#define ADC34_CCR_DELAY_1 (0x2UL << ADC34_CCR_DELAY_Pos)

0x00000200

◆ ADC34_CCR_DELAY_2

#define ADC34_CCR_DELAY_2 (0x4UL << ADC34_CCR_DELAY_Pos)

0x00000400

◆ ADC34_CCR_DELAY_3

#define ADC34_CCR_DELAY_3 (0x8UL << ADC34_CCR_DELAY_Pos)

0x00000800

◆ ADC34_CCR_DELAY_Msk

#define ADC34_CCR_DELAY_Msk (0xFUL << ADC34_CCR_DELAY_Pos)

0x00000F00

◆ ADC34_CCR_DELAY_Pos

#define ADC34_CCR_DELAY_Pos (8U)

◆ ADC34_CCR_DMACFG

#define ADC34_CCR_DMACFG ADC34_CCR_DMACFG_Msk

DMA configuration for multi-ADC mode

◆ ADC34_CCR_DMACFG_Msk

#define ADC34_CCR_DMACFG_Msk (0x1UL << ADC34_CCR_DMACFG_Pos)

0x00002000

◆ ADC34_CCR_DMACFG_Pos

#define ADC34_CCR_DMACFG_Pos (13U)

◆ ADC34_CCR_MDMA

#define ADC34_CCR_MDMA ADC34_CCR_MDMA_Msk

DMA mode for multi-ADC mode

◆ ADC34_CCR_MDMA_0

#define ADC34_CCR_MDMA_0 (0x1UL << ADC34_CCR_MDMA_Pos)

0x00004000

◆ ADC34_CCR_MDMA_1

#define ADC34_CCR_MDMA_1 (0x2UL << ADC34_CCR_MDMA_Pos)

0x00008000

◆ ADC34_CCR_MDMA_Msk

#define ADC34_CCR_MDMA_Msk (0x3UL << ADC34_CCR_MDMA_Pos)

0x0000C000

◆ ADC34_CCR_MDMA_Pos

#define ADC34_CCR_MDMA_Pos (14U)

◆ ADC34_CCR_MULTI

#define ADC34_CCR_MULTI ADC34_CCR_MULTI_Msk

Multi ADC mode selection

◆ ADC34_CCR_MULTI_0

#define ADC34_CCR_MULTI_0 (0x01UL << ADC34_CCR_MULTI_Pos)

0x00000001

◆ ADC34_CCR_MULTI_1

#define ADC34_CCR_MULTI_1 (0x02UL << ADC34_CCR_MULTI_Pos)

0x00000002

◆ ADC34_CCR_MULTI_2

#define ADC34_CCR_MULTI_2 (0x04UL << ADC34_CCR_MULTI_Pos)

0x00000004

◆ ADC34_CCR_MULTI_3

#define ADC34_CCR_MULTI_3 (0x08UL << ADC34_CCR_MULTI_Pos)

0x00000008

◆ ADC34_CCR_MULTI_4

#define ADC34_CCR_MULTI_4 (0x10UL << ADC34_CCR_MULTI_Pos)

0x00000010

◆ ADC34_CCR_MULTI_Msk

#define ADC34_CCR_MULTI_Msk (0x1FUL << ADC34_CCR_MULTI_Pos)

0x0000001F

◆ ADC34_CCR_MULTI_Pos

#define ADC34_CCR_MULTI_Pos (0U)

◆ ADC34_CCR_TSEN

#define ADC34_CCR_TSEN ADC34_CCR_TSEN_Msk

Temperature sensor enable

◆ ADC34_CCR_TSEN_Msk

#define ADC34_CCR_TSEN_Msk (0x1UL << ADC34_CCR_TSEN_Pos)

0x00800000

◆ ADC34_CCR_TSEN_Pos

#define ADC34_CCR_TSEN_Pos (23U)

◆ ADC34_CCR_VBATEN

#define ADC34_CCR_VBATEN ADC34_CCR_VBATEN_Msk

VBAT enable

◆ ADC34_CCR_VBATEN_Msk

#define ADC34_CCR_VBATEN_Msk (0x1UL << ADC34_CCR_VBATEN_Pos)

0x01000000

◆ ADC34_CCR_VBATEN_Pos

#define ADC34_CCR_VBATEN_Pos (24U)

◆ ADC34_CCR_VREFEN

#define ADC34_CCR_VREFEN ADC34_CCR_VREFEN_Msk

VREFINT enable

◆ ADC34_CCR_VREFEN_Msk

#define ADC34_CCR_VREFEN_Msk (0x1UL << ADC34_CCR_VREFEN_Pos)

0x00400000

◆ ADC34_CCR_VREFEN_Pos

#define ADC34_CCR_VREFEN_Pos (22U)

◆ ADC34_CDR_RDATA_MST

#define ADC34_CDR_RDATA_MST ADC34_CDR_RDATA_MST_Msk

Regular Data of the master ADC

◆ ADC34_CDR_RDATA_MST_0

#define ADC34_CDR_RDATA_MST_0 (0x0001UL << ADC34_CDR_RDATA_MST_Pos)

0x00000001

◆ ADC34_CDR_RDATA_MST_1

#define ADC34_CDR_RDATA_MST_1 (0x0002UL << ADC34_CDR_RDATA_MST_Pos)

0x00000002

◆ ADC34_CDR_RDATA_MST_10

#define ADC34_CDR_RDATA_MST_10 (0x0400UL << ADC34_CDR_RDATA_MST_Pos)

0x00000400

◆ ADC34_CDR_RDATA_MST_11

#define ADC34_CDR_RDATA_MST_11 (0x0800UL << ADC34_CDR_RDATA_MST_Pos)

0x00000800

◆ ADC34_CDR_RDATA_MST_12

#define ADC34_CDR_RDATA_MST_12 (0x1000UL << ADC34_CDR_RDATA_MST_Pos)

0x00001000

◆ ADC34_CDR_RDATA_MST_13

#define ADC34_CDR_RDATA_MST_13 (0x2000UL << ADC34_CDR_RDATA_MST_Pos)

0x00002000

◆ ADC34_CDR_RDATA_MST_14

#define ADC34_CDR_RDATA_MST_14 (0x4000UL << ADC34_CDR_RDATA_MST_Pos)

0x00004000

◆ ADC34_CDR_RDATA_MST_15

#define ADC34_CDR_RDATA_MST_15 (0x8000UL << ADC34_CDR_RDATA_MST_Pos)

0x00008000

◆ ADC34_CDR_RDATA_MST_2

#define ADC34_CDR_RDATA_MST_2 (0x0004UL << ADC34_CDR_RDATA_MST_Pos)

0x00000004

◆ ADC34_CDR_RDATA_MST_3

#define ADC34_CDR_RDATA_MST_3 (0x0008UL << ADC34_CDR_RDATA_MST_Pos)

0x00000008

◆ ADC34_CDR_RDATA_MST_4

#define ADC34_CDR_RDATA_MST_4 (0x0010UL << ADC34_CDR_RDATA_MST_Pos)

0x00000010

◆ ADC34_CDR_RDATA_MST_5

#define ADC34_CDR_RDATA_MST_5 (0x0020UL << ADC34_CDR_RDATA_MST_Pos)

0x00000020

◆ ADC34_CDR_RDATA_MST_6

#define ADC34_CDR_RDATA_MST_6 (0x0040UL << ADC34_CDR_RDATA_MST_Pos)

0x00000040

◆ ADC34_CDR_RDATA_MST_7

#define ADC34_CDR_RDATA_MST_7 (0x0080UL << ADC34_CDR_RDATA_MST_Pos)

0x00000080

◆ ADC34_CDR_RDATA_MST_8

#define ADC34_CDR_RDATA_MST_8 (0x0100UL << ADC34_CDR_RDATA_MST_Pos)

0x00000100

◆ ADC34_CDR_RDATA_MST_9

#define ADC34_CDR_RDATA_MST_9 (0x0200UL << ADC34_CDR_RDATA_MST_Pos)

0x00000200

◆ ADC34_CDR_RDATA_MST_Msk

#define ADC34_CDR_RDATA_MST_Msk (0xFFFFUL << ADC34_CDR_RDATA_MST_Pos)

0x0000FFFF

◆ ADC34_CDR_RDATA_MST_Pos

#define ADC34_CDR_RDATA_MST_Pos (0U)

◆ ADC34_CDR_RDATA_SLV

#define ADC34_CDR_RDATA_SLV ADC34_CDR_RDATA_SLV_Msk

Regular Data of the master ADC

◆ ADC34_CDR_RDATA_SLV_0

#define ADC34_CDR_RDATA_SLV_0 (0x0001UL << ADC34_CDR_RDATA_SLV_Pos)

0x00010000

◆ ADC34_CDR_RDATA_SLV_1

#define ADC34_CDR_RDATA_SLV_1 (0x0002UL << ADC34_CDR_RDATA_SLV_Pos)

0x00020000

◆ ADC34_CDR_RDATA_SLV_10

#define ADC34_CDR_RDATA_SLV_10 (0x0400UL << ADC34_CDR_RDATA_SLV_Pos)

0x04000000

◆ ADC34_CDR_RDATA_SLV_11

#define ADC34_CDR_RDATA_SLV_11 (0x0800UL << ADC34_CDR_RDATA_SLV_Pos)

0x08000000

◆ ADC34_CDR_RDATA_SLV_12

#define ADC34_CDR_RDATA_SLV_12 (0x1000UL << ADC34_CDR_RDATA_SLV_Pos)

0x10000000

◆ ADC34_CDR_RDATA_SLV_13

#define ADC34_CDR_RDATA_SLV_13 (0x2000UL << ADC34_CDR_RDATA_SLV_Pos)

0x20000000

◆ ADC34_CDR_RDATA_SLV_14

#define ADC34_CDR_RDATA_SLV_14 (0x4000UL << ADC34_CDR_RDATA_SLV_Pos)

0x40000000

◆ ADC34_CDR_RDATA_SLV_15

#define ADC34_CDR_RDATA_SLV_15 (0x8000UL << ADC34_CDR_RDATA_SLV_Pos)

0x80000000

◆ ADC34_CDR_RDATA_SLV_2

#define ADC34_CDR_RDATA_SLV_2 (0x0004UL << ADC34_CDR_RDATA_SLV_Pos)

0x00040000

◆ ADC34_CDR_RDATA_SLV_3

#define ADC34_CDR_RDATA_SLV_3 (0x0008UL << ADC34_CDR_RDATA_SLV_Pos)

0x00080000

◆ ADC34_CDR_RDATA_SLV_4

#define ADC34_CDR_RDATA_SLV_4 (0x0010UL << ADC34_CDR_RDATA_SLV_Pos)

0x00100000

◆ ADC34_CDR_RDATA_SLV_5

#define ADC34_CDR_RDATA_SLV_5 (0x0020UL << ADC34_CDR_RDATA_SLV_Pos)

0x00200000

◆ ADC34_CDR_RDATA_SLV_6

#define ADC34_CDR_RDATA_SLV_6 (0x0040UL << ADC34_CDR_RDATA_SLV_Pos)

0x00400000

◆ ADC34_CDR_RDATA_SLV_7

#define ADC34_CDR_RDATA_SLV_7 (0x0080UL << ADC34_CDR_RDATA_SLV_Pos)

0x00800000

◆ ADC34_CDR_RDATA_SLV_8

#define ADC34_CDR_RDATA_SLV_8 (0x0100UL << ADC34_CDR_RDATA_SLV_Pos)

0x01000000

◆ ADC34_CDR_RDATA_SLV_9

#define ADC34_CDR_RDATA_SLV_9 (0x0200UL << ADC34_CDR_RDATA_SLV_Pos)

0x02000000

◆ ADC34_CDR_RDATA_SLV_Msk

#define ADC34_CDR_RDATA_SLV_Msk (0xFFFFUL << ADC34_CDR_RDATA_SLV_Pos)

0xFFFF0000

◆ ADC34_CDR_RDATA_SLV_Pos

#define ADC34_CDR_RDATA_SLV_Pos (16U)

◆ ADC34_CSR_ADRDY_EOC_MST

#define ADC34_CSR_ADRDY_EOC_MST ADC34_CSR_ADRDY_EOC_MST_Msk

End of regular conversion of the master ADC

◆ ADC34_CSR_ADRDY_EOC_MST_Msk

#define ADC34_CSR_ADRDY_EOC_MST_Msk (0x1UL << ADC34_CSR_ADRDY_EOC_MST_Pos)

0x00000004

◆ ADC34_CSR_ADRDY_EOC_MST_Pos

#define ADC34_CSR_ADRDY_EOC_MST_Pos (2U)

◆ ADC34_CSR_ADRDY_EOC_SLV

#define ADC34_CSR_ADRDY_EOC_SLV ADC34_CSR_ADRDY_EOC_SLV_Msk

End of regular conversion of the slave ADC

◆ ADC34_CSR_ADRDY_EOC_SLV_Msk

#define ADC34_CSR_ADRDY_EOC_SLV_Msk (0x1UL << ADC34_CSR_ADRDY_EOC_SLV_Pos)

0x00040000

◆ ADC34_CSR_ADRDY_EOC_SLV_Pos

#define ADC34_CSR_ADRDY_EOC_SLV_Pos (18U)

◆ ADC34_CSR_ADRDY_EOS_MST

#define ADC34_CSR_ADRDY_EOS_MST ADC34_CSR_ADRDY_EOS_MST_Msk

End of regular sequence flag of the master ADC

◆ ADC34_CSR_ADRDY_EOS_MST_Msk

#define ADC34_CSR_ADRDY_EOS_MST_Msk (0x1UL << ADC34_CSR_ADRDY_EOS_MST_Pos)

0x00000008

◆ ADC34_CSR_ADRDY_EOS_MST_Pos

#define ADC34_CSR_ADRDY_EOS_MST_Pos (3U)

◆ ADC34_CSR_ADRDY_EOS_SLV

#define ADC34_CSR_ADRDY_EOS_SLV ADC34_CSR_ADRDY_EOS_SLV_Msk

End of regular sequence flag of the slave ADC

◆ ADC34_CSR_ADRDY_EOS_SLV_Msk

#define ADC34_CSR_ADRDY_EOS_SLV_Msk (0x1UL << ADC34_CSR_ADRDY_EOS_SLV_Pos)

0x00080000

◆ ADC34_CSR_ADRDY_EOS_SLV_Pos

#define ADC34_CSR_ADRDY_EOS_SLV_Pos (19U)

◆ ADC34_CSR_ADRDY_EOSMP_MST

#define ADC34_CSR_ADRDY_EOSMP_MST ADC34_CSR_ADRDY_EOSMP_MST_Msk

End of sampling phase flag of the master ADC

◆ ADC34_CSR_ADRDY_EOSMP_MST_Msk

#define ADC34_CSR_ADRDY_EOSMP_MST_Msk (0x1UL << ADC34_CSR_ADRDY_EOSMP_MST_Pos)

0x00000002

◆ ADC34_CSR_ADRDY_EOSMP_MST_Pos

#define ADC34_CSR_ADRDY_EOSMP_MST_Pos (1U)

◆ ADC34_CSR_ADRDY_EOSMP_SLV

#define ADC34_CSR_ADRDY_EOSMP_SLV ADC34_CSR_ADRDY_EOSMP_SLV_Msk

End of sampling phase flag of the slave ADC

◆ ADC34_CSR_ADRDY_EOSMP_SLV_Msk

#define ADC34_CSR_ADRDY_EOSMP_SLV_Msk (0x1UL << ADC34_CSR_ADRDY_EOSMP_SLV_Pos)

0x00020000

◆ ADC34_CSR_ADRDY_EOSMP_SLV_Pos

#define ADC34_CSR_ADRDY_EOSMP_SLV_Pos (17U)

◆ ADC34_CSR_ADRDY_JEOC_MST

#define ADC34_CSR_ADRDY_JEOC_MST ADC34_CSR_ADRDY_JEOC_MST_Msk

End of injected conversion of the master ADC

◆ ADC34_CSR_ADRDY_JEOC_MST_Msk

#define ADC34_CSR_ADRDY_JEOC_MST_Msk (0x1UL << ADC34_CSR_ADRDY_JEOC_MST_Pos)

0x00000020

◆ ADC34_CSR_ADRDY_JEOC_MST_Pos

#define ADC34_CSR_ADRDY_JEOC_MST_Pos (5U)

◆ ADC34_CSR_ADRDY_JEOC_SLV

#define ADC34_CSR_ADRDY_JEOC_SLV ADC34_CSR_ADRDY_JEOC_SLV_Msk

End of injected conversion of the slave ADC

◆ ADC34_CSR_ADRDY_JEOC_SLV_Msk

#define ADC34_CSR_ADRDY_JEOC_SLV_Msk (0x1UL << ADC34_CSR_ADRDY_JEOC_SLV_Pos)

0x00200000

◆ ADC34_CSR_ADRDY_JEOC_SLV_Pos

#define ADC34_CSR_ADRDY_JEOC_SLV_Pos (21U)

◆ ADC34_CSR_ADRDY_JEOS_MST

#define ADC34_CSR_ADRDY_JEOS_MST ADC34_CSR_ADRDY_JEOS_MST_Msk

End of injected sequence flag of the master ADC

◆ ADC34_CSR_ADRDY_JEOS_MST_Msk

#define ADC34_CSR_ADRDY_JEOS_MST_Msk (0x1UL << ADC34_CSR_ADRDY_JEOS_MST_Pos)

0x00000040

◆ ADC34_CSR_ADRDY_JEOS_MST_Pos

#define ADC34_CSR_ADRDY_JEOS_MST_Pos (6U)

◆ ADC34_CSR_ADRDY_JEOS_SLV

#define ADC34_CSR_ADRDY_JEOS_SLV ADC34_CSR_ADRDY_JEOS_SLV_Msk

End of injected sequence flag of the slave ADC

◆ ADC34_CSR_ADRDY_JEOS_SLV_Msk

#define ADC34_CSR_ADRDY_JEOS_SLV_Msk (0x1UL << ADC34_CSR_ADRDY_JEOS_SLV_Pos)

0x00400000

◆ ADC34_CSR_ADRDY_JEOS_SLV_Pos

#define ADC34_CSR_ADRDY_JEOS_SLV_Pos (22U)

◆ ADC34_CSR_ADRDY_MST

#define ADC34_CSR_ADRDY_MST ADC34_CSR_ADRDY_MST_Msk

Master ADC ready

◆ ADC34_CSR_ADRDY_MST_Msk

#define ADC34_CSR_ADRDY_MST_Msk (0x1UL << ADC34_CSR_ADRDY_MST_Pos)

0x00000001

◆ ADC34_CSR_ADRDY_MST_Pos

#define ADC34_CSR_ADRDY_MST_Pos (0U)

◆ ADC34_CSR_ADRDY_OVR_MST

#define ADC34_CSR_ADRDY_OVR_MST ADC34_CSR_ADRDY_OVR_MST_Msk

Overrun flag of the master ADC

◆ ADC34_CSR_ADRDY_OVR_MST_Msk

#define ADC34_CSR_ADRDY_OVR_MST_Msk (0x1UL << ADC34_CSR_ADRDY_OVR_MST_Pos)

0x00000010

◆ ADC34_CSR_ADRDY_OVR_MST_Pos

#define ADC34_CSR_ADRDY_OVR_MST_Pos (4U)

◆ ADC34_CSR_ADRDY_SLV

#define ADC34_CSR_ADRDY_SLV ADC34_CSR_ADRDY_SLV_Msk

Slave ADC ready

◆ ADC34_CSR_ADRDY_SLV_Msk

#define ADC34_CSR_ADRDY_SLV_Msk (0x1UL << ADC34_CSR_ADRDY_SLV_Pos)

0x00010000

◆ ADC34_CSR_ADRDY_SLV_Pos

#define ADC34_CSR_ADRDY_SLV_Pos (16U)

◆ ADC34_CSR_AWD1_MST

#define ADC34_CSR_AWD1_MST ADC34_CSR_AWD1_MST_Msk

Analog watchdog 1 flag of the master ADC

◆ ADC34_CSR_AWD1_MST_Msk

#define ADC34_CSR_AWD1_MST_Msk (0x1UL << ADC34_CSR_AWD1_MST_Pos)

0x00000080

◆ ADC34_CSR_AWD1_MST_Pos

#define ADC34_CSR_AWD1_MST_Pos (7U)

◆ ADC34_CSR_AWD1_SLV

#define ADC34_CSR_AWD1_SLV ADC34_CSR_AWD1_SLV_Msk

Analog watchdog 1 flag of the slave ADC

◆ ADC34_CSR_AWD1_SLV_Msk

#define ADC34_CSR_AWD1_SLV_Msk (0x1UL << ADC34_CSR_AWD1_SLV_Pos)

0x00800000

◆ ADC34_CSR_AWD1_SLV_Pos

#define ADC34_CSR_AWD1_SLV_Pos (23U)

◆ ADC34_CSR_AWD2_MST

#define ADC34_CSR_AWD2_MST ADC34_CSR_AWD2_MST_Msk

Analog watchdog 2 flag of the master ADC

◆ ADC34_CSR_AWD2_MST_Msk

#define ADC34_CSR_AWD2_MST_Msk (0x1UL << ADC34_CSR_AWD2_MST_Pos)

0x00000100

◆ ADC34_CSR_AWD2_MST_Pos

#define ADC34_CSR_AWD2_MST_Pos (8U)

◆ ADC34_CSR_AWD2_SLV

#define ADC34_CSR_AWD2_SLV ADC34_CSR_AWD2_SLV_Msk

Analog watchdog 2 flag of the slave ADC

◆ ADC34_CSR_AWD2_SLV_Msk

#define ADC34_CSR_AWD2_SLV_Msk (0x1UL << ADC34_CSR_AWD2_SLV_Pos)

0x01000000

◆ ADC34_CSR_AWD2_SLV_Pos

#define ADC34_CSR_AWD2_SLV_Pos (24U)

◆ ADC34_CSR_AWD3_MST

#define ADC34_CSR_AWD3_MST ADC34_CSR_AWD3_MST_Msk

Analog watchdog 3 flag of the master ADC

◆ ADC34_CSR_AWD3_MST_Msk

#define ADC34_CSR_AWD3_MST_Msk (0x1UL << ADC34_CSR_AWD3_MST_Pos)

0x00000200

◆ ADC34_CSR_AWD3_MST_Pos

#define ADC34_CSR_AWD3_MST_Pos (9U)

◆ ADC34_CSR_AWD3_SLV

#define ADC34_CSR_AWD3_SLV ADC34_CSR_AWD3_SLV_Msk

Analog watchdog 3 flag of the slave ADC

◆ ADC34_CSR_AWD3_SLV_Msk

#define ADC34_CSR_AWD3_SLV_Msk (0x1UL << ADC34_CSR_AWD3_SLV_Pos)

0x02000000

◆ ADC34_CSR_AWD3_SLV_Pos

#define ADC34_CSR_AWD3_SLV_Pos (25U)

◆ ADC34_CSR_JQOVF_MST

#define ADC34_CSR_JQOVF_MST ADC34_CSR_JQOVF_MST_Msk

Injected context queue overflow flag of the master ADC

◆ ADC34_CSR_JQOVF_MST_Msk

#define ADC34_CSR_JQOVF_MST_Msk (0x1UL << ADC34_CSR_JQOVF_MST_Pos)

0x00000400

◆ ADC34_CSR_JQOVF_MST_Pos

#define ADC34_CSR_JQOVF_MST_Pos (10U)

◆ ADC34_CSR_JQOVF_SLV

#define ADC34_CSR_JQOVF_SLV ADC34_CSR_JQOVF_SLV_Msk

Injected context queue overflow flag of the slave ADC

◆ ADC34_CSR_JQOVF_SLV_Msk

#define ADC34_CSR_JQOVF_SLV_Msk (0x1UL << ADC34_CSR_JQOVF_SLV_Pos)

0x04000000

◆ ADC34_CSR_JQOVF_SLV_Pos

#define ADC34_CSR_JQOVF_SLV_Pos (26U)

◆ ADC5_V1_1

#define ADC5_V1_1

ADC IP version

◆ ADC_AWD2CR_AWD2CH

#define ADC_AWD2CR_AWD2CH ADC_AWD2CR_AWD2CH_Msk

ADC analog watchdog 2 monitored channel selection

◆ ADC_AWD2CR_AWD2CH_0

#define ADC_AWD2CR_AWD2CH_0 (0x00001UL << ADC_AWD2CR_AWD2CH_Pos)

0x00000001

◆ ADC_AWD2CR_AWD2CH_1

#define ADC_AWD2CR_AWD2CH_1 (0x00002UL << ADC_AWD2CR_AWD2CH_Pos)

0x00000002

◆ ADC_AWD2CR_AWD2CH_10

#define ADC_AWD2CR_AWD2CH_10 (0x00400UL << ADC_AWD2CR_AWD2CH_Pos)

0x00000400

◆ ADC_AWD2CR_AWD2CH_11

#define ADC_AWD2CR_AWD2CH_11 (0x00800UL << ADC_AWD2CR_AWD2CH_Pos)

0x00000800

◆ ADC_AWD2CR_AWD2CH_12

#define ADC_AWD2CR_AWD2CH_12 (0x01000UL << ADC_AWD2CR_AWD2CH_Pos)

0x00001000

◆ ADC_AWD2CR_AWD2CH_13

#define ADC_AWD2CR_AWD2CH_13 (0x02000UL << ADC_AWD2CR_AWD2CH_Pos)

0x00002000

◆ ADC_AWD2CR_AWD2CH_14

#define ADC_AWD2CR_AWD2CH_14 (0x04000UL << ADC_AWD2CR_AWD2CH_Pos)

0x00004000

◆ ADC_AWD2CR_AWD2CH_15

#define ADC_AWD2CR_AWD2CH_15 (0x08000UL << ADC_AWD2CR_AWD2CH_Pos)

0x00008000

◆ ADC_AWD2CR_AWD2CH_16

#define ADC_AWD2CR_AWD2CH_16 (0x10000UL << ADC_AWD2CR_AWD2CH_Pos)

0x00010000

◆ ADC_AWD2CR_AWD2CH_17

#define ADC_AWD2CR_AWD2CH_17 (0x20000UL << ADC_AWD2CR_AWD2CH_Pos)

0x00020000

◆ ADC_AWD2CR_AWD2CH_2

#define ADC_AWD2CR_AWD2CH_2 (0x00004UL << ADC_AWD2CR_AWD2CH_Pos)

0x00000004

◆ ADC_AWD2CR_AWD2CH_3

#define ADC_AWD2CR_AWD2CH_3 (0x00008UL << ADC_AWD2CR_AWD2CH_Pos)

0x00000008

◆ ADC_AWD2CR_AWD2CH_4

#define ADC_AWD2CR_AWD2CH_4 (0x00010UL << ADC_AWD2CR_AWD2CH_Pos)

0x00000010

◆ ADC_AWD2CR_AWD2CH_5

#define ADC_AWD2CR_AWD2CH_5 (0x00020UL << ADC_AWD2CR_AWD2CH_Pos)

0x00000020

◆ ADC_AWD2CR_AWD2CH_6

#define ADC_AWD2CR_AWD2CH_6 (0x00040UL << ADC_AWD2CR_AWD2CH_Pos)

0x00000040

◆ ADC_AWD2CR_AWD2CH_7

#define ADC_AWD2CR_AWD2CH_7 (0x00080UL << ADC_AWD2CR_AWD2CH_Pos)

0x00000080

◆ ADC_AWD2CR_AWD2CH_8

#define ADC_AWD2CR_AWD2CH_8 (0x00100UL << ADC_AWD2CR_AWD2CH_Pos)

0x00000100

◆ ADC_AWD2CR_AWD2CH_9

#define ADC_AWD2CR_AWD2CH_9 (0x00200UL << ADC_AWD2CR_AWD2CH_Pos)

0x00000200

◆ ADC_AWD2CR_AWD2CH_Msk

#define ADC_AWD2CR_AWD2CH_Msk (0x3FFFFUL << ADC_AWD2CR_AWD2CH_Pos)

0x0003FFFF

◆ ADC_AWD2CR_AWD2CH_Pos

#define ADC_AWD2CR_AWD2CH_Pos (1U)

◆ ADC_AWD3CR_AWD3CH

#define ADC_AWD3CR_AWD3CH ADC_AWD3CR_AWD3CH_Msk

ADC analog watchdog 3 monitored channel selection

◆ ADC_AWD3CR_AWD3CH_0

#define ADC_AWD3CR_AWD3CH_0 (0x00001UL << ADC_AWD3CR_AWD3CH_Pos)

0x00000001

◆ ADC_AWD3CR_AWD3CH_1

#define ADC_AWD3CR_AWD3CH_1 (0x00002UL << ADC_AWD3CR_AWD3CH_Pos)

0x00000002

◆ ADC_AWD3CR_AWD3CH_10

#define ADC_AWD3CR_AWD3CH_10 (0x00400UL << ADC_AWD3CR_AWD3CH_Pos)

0x00000400

◆ ADC_AWD3CR_AWD3CH_11

#define ADC_AWD3CR_AWD3CH_11 (0x00800UL << ADC_AWD3CR_AWD3CH_Pos)

0x00000800

◆ ADC_AWD3CR_AWD3CH_12

#define ADC_AWD3CR_AWD3CH_12 (0x01000UL << ADC_AWD3CR_AWD3CH_Pos)

0x00001000

◆ ADC_AWD3CR_AWD3CH_13

#define ADC_AWD3CR_AWD3CH_13 (0x02000UL << ADC_AWD3CR_AWD3CH_Pos)

0x00002000

◆ ADC_AWD3CR_AWD3CH_14

#define ADC_AWD3CR_AWD3CH_14 (0x04000UL << ADC_AWD3CR_AWD3CH_Pos)

0x00004000

◆ ADC_AWD3CR_AWD3CH_15

#define ADC_AWD3CR_AWD3CH_15 (0x08000UL << ADC_AWD3CR_AWD3CH_Pos)

0x00008000

◆ ADC_AWD3CR_AWD3CH_16

#define ADC_AWD3CR_AWD3CH_16 (0x10000UL << ADC_AWD3CR_AWD3CH_Pos)

0x00010000

◆ ADC_AWD3CR_AWD3CH_17

#define ADC_AWD3CR_AWD3CH_17 (0x20000UL << ADC_AWD3CR_AWD3CH_Pos)

0x00020000

◆ ADC_AWD3CR_AWD3CH_2

#define ADC_AWD3CR_AWD3CH_2 (0x00004UL << ADC_AWD3CR_AWD3CH_Pos)

0x00000004

◆ ADC_AWD3CR_AWD3CH_3

#define ADC_AWD3CR_AWD3CH_3 (0x00008UL << ADC_AWD3CR_AWD3CH_Pos)

0x00000008

◆ ADC_AWD3CR_AWD3CH_4

#define ADC_AWD3CR_AWD3CH_4 (0x00010UL << ADC_AWD3CR_AWD3CH_Pos)

0x00000010

◆ ADC_AWD3CR_AWD3CH_5

#define ADC_AWD3CR_AWD3CH_5 (0x00020UL << ADC_AWD3CR_AWD3CH_Pos)

0x00000020

◆ ADC_AWD3CR_AWD3CH_6

#define ADC_AWD3CR_AWD3CH_6 (0x00040UL << ADC_AWD3CR_AWD3CH_Pos)

0x00000040

◆ ADC_AWD3CR_AWD3CH_7

#define ADC_AWD3CR_AWD3CH_7 (0x00080UL << ADC_AWD3CR_AWD3CH_Pos)

0x00000080

◆ ADC_AWD3CR_AWD3CH_8

#define ADC_AWD3CR_AWD3CH_8 (0x00100UL << ADC_AWD3CR_AWD3CH_Pos)

0x00000100

◆ ADC_AWD3CR_AWD3CH_9

#define ADC_AWD3CR_AWD3CH_9 (0x00200UL << ADC_AWD3CR_AWD3CH_Pos)

0x00000200

◆ ADC_AWD3CR_AWD3CH_Msk

#define ADC_AWD3CR_AWD3CH_Msk (0x3FFFFUL << ADC_AWD3CR_AWD3CH_Pos)

0x0003FFFF

◆ ADC_AWD3CR_AWD3CH_Pos

#define ADC_AWD3CR_AWD3CH_Pos (1U)

◆ ADC_CALFACT_CALFACT_D

#define ADC_CALFACT_CALFACT_D ADC_CALFACT_CALFACT_D_Msk

ADC calibration factor in differential mode

◆ ADC_CALFACT_CALFACT_D_0

#define ADC_CALFACT_CALFACT_D_0 (0x01UL << ADC_CALFACT_CALFACT_D_Pos)

0x00010000

◆ ADC_CALFACT_CALFACT_D_1

#define ADC_CALFACT_CALFACT_D_1 (0x02UL << ADC_CALFACT_CALFACT_D_Pos)

0x00020000

◆ ADC_CALFACT_CALFACT_D_2

#define ADC_CALFACT_CALFACT_D_2 (0x04UL << ADC_CALFACT_CALFACT_D_Pos)

0x00040000

◆ ADC_CALFACT_CALFACT_D_3

#define ADC_CALFACT_CALFACT_D_3 (0x08UL << ADC_CALFACT_CALFACT_D_Pos)

0x00080000

◆ ADC_CALFACT_CALFACT_D_4

#define ADC_CALFACT_CALFACT_D_4 (0x10UL << ADC_CALFACT_CALFACT_D_Pos)

0x00100000

◆ ADC_CALFACT_CALFACT_D_5

#define ADC_CALFACT_CALFACT_D_5 (0x20UL << ADC_CALFACT_CALFACT_D_Pos)

0x00200000

◆ ADC_CALFACT_CALFACT_D_6

#define ADC_CALFACT_CALFACT_D_6 (0x40UL << ADC_CALFACT_CALFACT_D_Pos)

0x00400000

◆ ADC_CALFACT_CALFACT_D_Msk

#define ADC_CALFACT_CALFACT_D_Msk (0x7FUL << ADC_CALFACT_CALFACT_D_Pos)

0x007F0000

◆ ADC_CALFACT_CALFACT_D_Pos

#define ADC_CALFACT_CALFACT_D_Pos (16U)

◆ ADC_CALFACT_CALFACT_S

#define ADC_CALFACT_CALFACT_S ADC_CALFACT_CALFACT_S_Msk

ADC calibration factor in single-ended mode

◆ ADC_CALFACT_CALFACT_S_0

#define ADC_CALFACT_CALFACT_S_0 (0x01UL << ADC_CALFACT_CALFACT_S_Pos)

0x00000001

◆ ADC_CALFACT_CALFACT_S_1

#define ADC_CALFACT_CALFACT_S_1 (0x02UL << ADC_CALFACT_CALFACT_S_Pos)

0x00000002

◆ ADC_CALFACT_CALFACT_S_2

#define ADC_CALFACT_CALFACT_S_2 (0x04UL << ADC_CALFACT_CALFACT_S_Pos)

0x00000004

◆ ADC_CALFACT_CALFACT_S_3

#define ADC_CALFACT_CALFACT_S_3 (0x08UL << ADC_CALFACT_CALFACT_S_Pos)

0x00000008

◆ ADC_CALFACT_CALFACT_S_4

#define ADC_CALFACT_CALFACT_S_4 (0x10UL << ADC_CALFACT_CALFACT_S_Pos)

0x00000010

◆ ADC_CALFACT_CALFACT_S_5

#define ADC_CALFACT_CALFACT_S_5 (0x20UL << ADC_CALFACT_CALFACT_S_Pos)

0x00000020

◆ ADC_CALFACT_CALFACT_S_6

#define ADC_CALFACT_CALFACT_S_6 (0x40UL << ADC_CALFACT_CALFACT_S_Pos)

0x00000040

◆ ADC_CALFACT_CALFACT_S_Msk

#define ADC_CALFACT_CALFACT_S_Msk (0x7FUL << ADC_CALFACT_CALFACT_S_Pos)

0x0000007F

◆ ADC_CALFACT_CALFACT_S_Pos

#define ADC_CALFACT_CALFACT_S_Pos (0U)

◆ ADC_CCR_CKMODE

#define ADC_CCR_CKMODE ADC_CCR_CKMODE_Msk

ADC common clock source and prescaler (prescaler only for clock source synchronous)

◆ ADC_CCR_CKMODE_0

#define ADC_CCR_CKMODE_0 (0x1UL << ADC_CCR_CKMODE_Pos)

0x00010000

◆ ADC_CCR_CKMODE_1

#define ADC_CCR_CKMODE_1 (0x2UL << ADC_CCR_CKMODE_Pos)

0x00020000

◆ ADC_CCR_CKMODE_Msk

#define ADC_CCR_CKMODE_Msk (0x3UL << ADC_CCR_CKMODE_Pos)

0x00030000

◆ ADC_CCR_CKMODE_Pos

#define ADC_CCR_CKMODE_Pos (16U)

◆ ADC_CCR_DELAY

#define ADC_CCR_DELAY ADC_CCR_DELAY_Msk

ADC multimode delay between 2 sampling phases

◆ ADC_CCR_DELAY_0

#define ADC_CCR_DELAY_0 (0x1UL << ADC_CCR_DELAY_Pos)

0x00000100

◆ ADC_CCR_DELAY_1

#define ADC_CCR_DELAY_1 (0x2UL << ADC_CCR_DELAY_Pos)

0x00000200

◆ ADC_CCR_DELAY_2

#define ADC_CCR_DELAY_2 (0x4UL << ADC_CCR_DELAY_Pos)

0x00000400

◆ ADC_CCR_DELAY_3

#define ADC_CCR_DELAY_3 (0x8UL << ADC_CCR_DELAY_Pos)

0x00000800

◆ ADC_CCR_DELAY_Msk

#define ADC_CCR_DELAY_Msk (0xFUL << ADC_CCR_DELAY_Pos)

0x00000F00

◆ ADC_CCR_DELAY_Pos

#define ADC_CCR_DELAY_Pos (8U)

◆ ADC_CCR_DMACFG

#define ADC_CCR_DMACFG ADC_CCR_DMACFG_Msk

ADC multimode DMA transfer configuration

◆ ADC_CCR_DMACFG_Msk

#define ADC_CCR_DMACFG_Msk (0x1UL << ADC_CCR_DMACFG_Pos)

0x00002000

◆ ADC_CCR_DMACFG_Pos

#define ADC_CCR_DMACFG_Pos (13U)

◆ ADC_CCR_DUAL

#define ADC_CCR_DUAL ADC_CCR_DUAL_Msk

ADC multimode mode selection

◆ ADC_CCR_DUAL_0

#define ADC_CCR_DUAL_0 (0x01UL << ADC_CCR_DUAL_Pos)

0x00000001

◆ ADC_CCR_DUAL_1

#define ADC_CCR_DUAL_1 (0x02UL << ADC_CCR_DUAL_Pos)

0x00000002

◆ ADC_CCR_DUAL_2

#define ADC_CCR_DUAL_2 (0x04UL << ADC_CCR_DUAL_Pos)

0x00000004

◆ ADC_CCR_DUAL_3

#define ADC_CCR_DUAL_3 (0x08UL << ADC_CCR_DUAL_Pos)

0x00000008

◆ ADC_CCR_DUAL_4

#define ADC_CCR_DUAL_4 (0x10UL << ADC_CCR_DUAL_Pos)

0x00000010

◆ ADC_CCR_DUAL_Msk

#define ADC_CCR_DUAL_Msk (0x1FUL << ADC_CCR_DUAL_Pos)

0x0000001F

◆ ADC_CCR_DUAL_Pos

#define ADC_CCR_DUAL_Pos (0U)

◆ ADC_CCR_MDMA

#define ADC_CCR_MDMA ADC_CCR_MDMA_Msk

ADC multimode DMA transfer enable

◆ ADC_CCR_MDMA_0

#define ADC_CCR_MDMA_0 (0x1UL << ADC_CCR_MDMA_Pos)

0x00004000

◆ ADC_CCR_MDMA_1

#define ADC_CCR_MDMA_1 (0x2UL << ADC_CCR_MDMA_Pos)

0x00008000

◆ ADC_CCR_MDMA_Msk

#define ADC_CCR_MDMA_Msk (0x3UL << ADC_CCR_MDMA_Pos)

0x0000C000

◆ ADC_CCR_MDMA_Pos

#define ADC_CCR_MDMA_Pos (14U)

◆ ADC_CCR_MULTI

#define ADC_CCR_MULTI (ADC_CCR_DUAL)

◆ ADC_CCR_MULTI_0

#define ADC_CCR_MULTI_0 (ADC_CCR_DUAL_0)

◆ ADC_CCR_MULTI_1

#define ADC_CCR_MULTI_1 (ADC_CCR_DUAL_1)

◆ ADC_CCR_MULTI_2

#define ADC_CCR_MULTI_2 (ADC_CCR_DUAL_2)

◆ ADC_CCR_MULTI_3

#define ADC_CCR_MULTI_3 (ADC_CCR_DUAL_3)

◆ ADC_CCR_MULTI_4

#define ADC_CCR_MULTI_4 (ADC_CCR_DUAL_4)

◆ ADC_CCR_TSEN

#define ADC_CCR_TSEN ADC_CCR_TSEN_Msk

ADC internal path to temperature sensor enable

◆ ADC_CCR_TSEN_Msk

#define ADC_CCR_TSEN_Msk (0x1UL << ADC_CCR_TSEN_Pos)

0x00800000

◆ ADC_CCR_TSEN_Pos

#define ADC_CCR_TSEN_Pos (23U)

◆ ADC_CCR_VBATEN

#define ADC_CCR_VBATEN ADC_CCR_VBATEN_Msk

ADC internal path to battery voltage enable

◆ ADC_CCR_VBATEN_Msk

#define ADC_CCR_VBATEN_Msk (0x1UL << ADC_CCR_VBATEN_Pos)

0x01000000

◆ ADC_CCR_VBATEN_Pos

#define ADC_CCR_VBATEN_Pos (24U)

◆ ADC_CCR_VREFEN

#define ADC_CCR_VREFEN ADC_CCR_VREFEN_Msk

ADC internal path to VrefInt enable

◆ ADC_CCR_VREFEN_Msk

#define ADC_CCR_VREFEN_Msk (0x1UL << ADC_CCR_VREFEN_Pos)

0x00400000

◆ ADC_CCR_VREFEN_Pos

#define ADC_CCR_VREFEN_Pos (22U)

◆ ADC_CDR_RDATA_MST

#define ADC_CDR_RDATA_MST ADC_CDR_RDATA_MST_Msk

ADC multimode master group regular conversion data

◆ ADC_CDR_RDATA_MST_0

#define ADC_CDR_RDATA_MST_0 (0x0001UL << ADC_CDR_RDATA_MST_Pos)

0x00000001

◆ ADC_CDR_RDATA_MST_1

#define ADC_CDR_RDATA_MST_1 (0x0002UL << ADC_CDR_RDATA_MST_Pos)

0x00000002

◆ ADC_CDR_RDATA_MST_10

#define ADC_CDR_RDATA_MST_10 (0x0400UL << ADC_CDR_RDATA_MST_Pos)

0x00000400

◆ ADC_CDR_RDATA_MST_11

#define ADC_CDR_RDATA_MST_11 (0x0800UL << ADC_CDR_RDATA_MST_Pos)

0x00000800

◆ ADC_CDR_RDATA_MST_12

#define ADC_CDR_RDATA_MST_12 (0x1000UL << ADC_CDR_RDATA_MST_Pos)

0x00001000

◆ ADC_CDR_RDATA_MST_13

#define ADC_CDR_RDATA_MST_13 (0x2000UL << ADC_CDR_RDATA_MST_Pos)

0x00002000

◆ ADC_CDR_RDATA_MST_14

#define ADC_CDR_RDATA_MST_14 (0x4000UL << ADC_CDR_RDATA_MST_Pos)

0x00004000

◆ ADC_CDR_RDATA_MST_15

#define ADC_CDR_RDATA_MST_15 (0x8000UL << ADC_CDR_RDATA_MST_Pos)

0x00008000

◆ ADC_CDR_RDATA_MST_2

#define ADC_CDR_RDATA_MST_2 (0x0004UL << ADC_CDR_RDATA_MST_Pos)

0x00000004

◆ ADC_CDR_RDATA_MST_3

#define ADC_CDR_RDATA_MST_3 (0x0008UL << ADC_CDR_RDATA_MST_Pos)

0x00000008

◆ ADC_CDR_RDATA_MST_4

#define ADC_CDR_RDATA_MST_4 (0x0010UL << ADC_CDR_RDATA_MST_Pos)

0x00000010

◆ ADC_CDR_RDATA_MST_5

#define ADC_CDR_RDATA_MST_5 (0x0020UL << ADC_CDR_RDATA_MST_Pos)

0x00000020

◆ ADC_CDR_RDATA_MST_6

#define ADC_CDR_RDATA_MST_6 (0x0040UL << ADC_CDR_RDATA_MST_Pos)

0x00000040

◆ ADC_CDR_RDATA_MST_7

#define ADC_CDR_RDATA_MST_7 (0x0080UL << ADC_CDR_RDATA_MST_Pos)

0x00000080

◆ ADC_CDR_RDATA_MST_8

#define ADC_CDR_RDATA_MST_8 (0x0100UL << ADC_CDR_RDATA_MST_Pos)

0x00000100

◆ ADC_CDR_RDATA_MST_9

#define ADC_CDR_RDATA_MST_9 (0x0200UL << ADC_CDR_RDATA_MST_Pos)

0x00000200

◆ ADC_CDR_RDATA_MST_Msk

#define ADC_CDR_RDATA_MST_Msk (0xFFFFUL << ADC_CDR_RDATA_MST_Pos)

0x0000FFFF

◆ ADC_CDR_RDATA_MST_Pos

#define ADC_CDR_RDATA_MST_Pos (0U)

◆ ADC_CDR_RDATA_SLV

#define ADC_CDR_RDATA_SLV ADC_CDR_RDATA_SLV_Msk

ADC multimode slave group regular conversion data

◆ ADC_CDR_RDATA_SLV_0

#define ADC_CDR_RDATA_SLV_0 (0x0001UL << ADC_CDR_RDATA_SLV_Pos)

0x00010000

◆ ADC_CDR_RDATA_SLV_1

#define ADC_CDR_RDATA_SLV_1 (0x0002UL << ADC_CDR_RDATA_SLV_Pos)

0x00020000

◆ ADC_CDR_RDATA_SLV_10

#define ADC_CDR_RDATA_SLV_10 (0x0400UL << ADC_CDR_RDATA_SLV_Pos)

0x04000000

◆ ADC_CDR_RDATA_SLV_11

#define ADC_CDR_RDATA_SLV_11 (0x0800UL << ADC_CDR_RDATA_SLV_Pos)

0x08000000

◆ ADC_CDR_RDATA_SLV_12

#define ADC_CDR_RDATA_SLV_12 (0x1000UL << ADC_CDR_RDATA_SLV_Pos)

0x10000000

◆ ADC_CDR_RDATA_SLV_13

#define ADC_CDR_RDATA_SLV_13 (0x2000UL << ADC_CDR_RDATA_SLV_Pos)

0x20000000

◆ ADC_CDR_RDATA_SLV_14

#define ADC_CDR_RDATA_SLV_14 (0x4000UL << ADC_CDR_RDATA_SLV_Pos)

0x40000000

◆ ADC_CDR_RDATA_SLV_15

#define ADC_CDR_RDATA_SLV_15 (0x8000UL << ADC_CDR_RDATA_SLV_Pos)

0x80000000

◆ ADC_CDR_RDATA_SLV_2

#define ADC_CDR_RDATA_SLV_2 (0x0004UL << ADC_CDR_RDATA_SLV_Pos)

0x00040000

◆ ADC_CDR_RDATA_SLV_3

#define ADC_CDR_RDATA_SLV_3 (0x0008UL << ADC_CDR_RDATA_SLV_Pos)

0x00080000

◆ ADC_CDR_RDATA_SLV_4

#define ADC_CDR_RDATA_SLV_4 (0x0010UL << ADC_CDR_RDATA_SLV_Pos)

0x00100000

◆ ADC_CDR_RDATA_SLV_5

#define ADC_CDR_RDATA_SLV_5 (0x0020UL << ADC_CDR_RDATA_SLV_Pos)

0x00200000

◆ ADC_CDR_RDATA_SLV_6

#define ADC_CDR_RDATA_SLV_6 (0x0040UL << ADC_CDR_RDATA_SLV_Pos)

0x00400000

◆ ADC_CDR_RDATA_SLV_7

#define ADC_CDR_RDATA_SLV_7 (0x0080UL << ADC_CDR_RDATA_SLV_Pos)

0x00800000

◆ ADC_CDR_RDATA_SLV_8

#define ADC_CDR_RDATA_SLV_8 (0x0100UL << ADC_CDR_RDATA_SLV_Pos)

0x01000000

◆ ADC_CDR_RDATA_SLV_9

#define ADC_CDR_RDATA_SLV_9 (0x0200UL << ADC_CDR_RDATA_SLV_Pos)

0x02000000

◆ ADC_CDR_RDATA_SLV_Msk

#define ADC_CDR_RDATA_SLV_Msk (0xFFFFUL << ADC_CDR_RDATA_SLV_Pos)

0xFFFF0000

◆ ADC_CDR_RDATA_SLV_Pos

#define ADC_CDR_RDATA_SLV_Pos (16U)

◆ ADC_CFGR_ALIGN

#define ADC_CFGR_ALIGN ADC_CFGR_ALIGN_Msk

ADC data alignment

◆ ADC_CFGR_ALIGN_Msk

#define ADC_CFGR_ALIGN_Msk (0x1UL << ADC_CFGR_ALIGN_Pos)

0x00000020

◆ ADC_CFGR_ALIGN_Pos

#define ADC_CFGR_ALIGN_Pos (5U)

◆ ADC_CFGR_AUTDLY

#define ADC_CFGR_AUTDLY ADC_CFGR_AUTDLY_Msk

ADC low power auto wait

◆ ADC_CFGR_AUTDLY_Msk

#define ADC_CFGR_AUTDLY_Msk (0x1UL << ADC_CFGR_AUTDLY_Pos)

0x00004000

◆ ADC_CFGR_AUTDLY_Pos

#define ADC_CFGR_AUTDLY_Pos (14U)

◆ ADC_CFGR_AUTOFF

#define ADC_CFGR_AUTOFF ADC_CFGR_AUTOFF_Msk

ADC low power auto power off

◆ ADC_CFGR_AUTOFF_Msk

#define ADC_CFGR_AUTOFF_Msk (0x1UL << ADC_CFGR_AUTOFF_Pos)

0x00008000

◆ ADC_CFGR_AUTOFF_Pos

#define ADC_CFGR_AUTOFF_Pos (15U)

◆ ADC_CFGR_AWD1CH

#define ADC_CFGR_AWD1CH ADC_CFGR_AWD1CH_Msk

ADC analog watchdog 1 monitored channel selection

◆ ADC_CFGR_AWD1CH_0

#define ADC_CFGR_AWD1CH_0 (0x01UL << ADC_CFGR_AWD1CH_Pos)

0x04000000

◆ ADC_CFGR_AWD1CH_1

#define ADC_CFGR_AWD1CH_1 (0x02UL << ADC_CFGR_AWD1CH_Pos)

0x08000000

◆ ADC_CFGR_AWD1CH_2

#define ADC_CFGR_AWD1CH_2 (0x04UL << ADC_CFGR_AWD1CH_Pos)

0x10000000

◆ ADC_CFGR_AWD1CH_3

#define ADC_CFGR_AWD1CH_3 (0x08UL << ADC_CFGR_AWD1CH_Pos)

0x20000000

◆ ADC_CFGR_AWD1CH_4

#define ADC_CFGR_AWD1CH_4 (0x10UL << ADC_CFGR_AWD1CH_Pos)

0x40000000

◆ ADC_CFGR_AWD1CH_Msk

#define ADC_CFGR_AWD1CH_Msk (0x1FUL << ADC_CFGR_AWD1CH_Pos)

0x7C000000

◆ ADC_CFGR_AWD1CH_Pos

#define ADC_CFGR_AWD1CH_Pos (26U)

◆ ADC_CFGR_AWD1EN

#define ADC_CFGR_AWD1EN ADC_CFGR_AWD1EN_Msk

ADC analog watchdog 1 enable on scope ADC group regular

◆ ADC_CFGR_AWD1EN_Msk

#define ADC_CFGR_AWD1EN_Msk (0x1UL << ADC_CFGR_AWD1EN_Pos)

0x00800000

◆ ADC_CFGR_AWD1EN_Pos

#define ADC_CFGR_AWD1EN_Pos (23U)

◆ ADC_CFGR_AWD1SGL

#define ADC_CFGR_AWD1SGL ADC_CFGR_AWD1SGL_Msk

ADC analog watchdog 1 monitoring a single channel or all channels

◆ ADC_CFGR_AWD1SGL_Msk

#define ADC_CFGR_AWD1SGL_Msk (0x1UL << ADC_CFGR_AWD1SGL_Pos)

0x00400000

◆ ADC_CFGR_AWD1SGL_Pos

#define ADC_CFGR_AWD1SGL_Pos (22U)

◆ ADC_CFGR_CONT

#define ADC_CFGR_CONT ADC_CFGR_CONT_Msk

ADC group regular continuous conversion mode

◆ ADC_CFGR_CONT_Msk

#define ADC_CFGR_CONT_Msk (0x1UL << ADC_CFGR_CONT_Pos)

0x00002000

◆ ADC_CFGR_CONT_Pos

#define ADC_CFGR_CONT_Pos (13U)

◆ ADC_CFGR_DISCEN

#define ADC_CFGR_DISCEN ADC_CFGR_DISCEN_Msk

ADC group regular sequencer discontinuous mode

◆ ADC_CFGR_DISCEN_Msk

#define ADC_CFGR_DISCEN_Msk (0x1UL << ADC_CFGR_DISCEN_Pos)

0x00010000

◆ ADC_CFGR_DISCEN_Pos

#define ADC_CFGR_DISCEN_Pos (16U)

◆ ADC_CFGR_DISCNUM

#define ADC_CFGR_DISCNUM ADC_CFGR_DISCNUM_Msk

ADC Discontinuous mode channel count

◆ ADC_CFGR_DISCNUM_0

#define ADC_CFGR_DISCNUM_0 (0x1UL << ADC_CFGR_DISCNUM_Pos)

0x00020000

◆ ADC_CFGR_DISCNUM_1

#define ADC_CFGR_DISCNUM_1 (0x2UL << ADC_CFGR_DISCNUM_Pos)

0x00040000

◆ ADC_CFGR_DISCNUM_2

#define ADC_CFGR_DISCNUM_2 (0x4UL << ADC_CFGR_DISCNUM_Pos)

0x00080000

◆ ADC_CFGR_DISCNUM_Msk

#define ADC_CFGR_DISCNUM_Msk (0x7UL << ADC_CFGR_DISCNUM_Pos)

0x000E0000

◆ ADC_CFGR_DISCNUM_Pos

#define ADC_CFGR_DISCNUM_Pos (17U)

◆ ADC_CFGR_DMACFG

#define ADC_CFGR_DMACFG ADC_CFGR_DMACFG_Msk

ADC DMA configuration

◆ ADC_CFGR_DMACFG_Msk

#define ADC_CFGR_DMACFG_Msk (0x1UL << ADC_CFGR_DMACFG_Pos)

0x00000002

◆ ADC_CFGR_DMACFG_Pos

#define ADC_CFGR_DMACFG_Pos (1U)

◆ ADC_CFGR_DMAEN

#define ADC_CFGR_DMAEN ADC_CFGR_DMAEN_Msk

ADC DMA enable

◆ ADC_CFGR_DMAEN_Msk

#define ADC_CFGR_DMAEN_Msk (0x1UL << ADC_CFGR_DMAEN_Pos)

0x00000001

◆ ADC_CFGR_DMAEN_Pos

#define ADC_CFGR_DMAEN_Pos (0U)

◆ ADC_CFGR_EXTEN

#define ADC_CFGR_EXTEN ADC_CFGR_EXTEN_Msk

ADC group regular external trigger polarity

◆ ADC_CFGR_EXTEN_0

#define ADC_CFGR_EXTEN_0 (0x1UL << ADC_CFGR_EXTEN_Pos)

0x00000400

◆ ADC_CFGR_EXTEN_1

#define ADC_CFGR_EXTEN_1 (0x2UL << ADC_CFGR_EXTEN_Pos)

0x00000800

◆ ADC_CFGR_EXTEN_Msk

#define ADC_CFGR_EXTEN_Msk (0x3UL << ADC_CFGR_EXTEN_Pos)

0x00000C00

◆ ADC_CFGR_EXTEN_Pos

#define ADC_CFGR_EXTEN_Pos (10U)

◆ ADC_CFGR_EXTSEL

#define ADC_CFGR_EXTSEL ADC_CFGR_EXTSEL_Msk

ADC group regular external trigger source

◆ ADC_CFGR_EXTSEL_0

#define ADC_CFGR_EXTSEL_0 (0x1UL << ADC_CFGR_EXTSEL_Pos)

0x00000040

◆ ADC_CFGR_EXTSEL_1

#define ADC_CFGR_EXTSEL_1 (0x2UL << ADC_CFGR_EXTSEL_Pos)

0x00000080

◆ ADC_CFGR_EXTSEL_2

#define ADC_CFGR_EXTSEL_2 (0x4UL << ADC_CFGR_EXTSEL_Pos)

0x00000100

◆ ADC_CFGR_EXTSEL_3

#define ADC_CFGR_EXTSEL_3 (0x8UL << ADC_CFGR_EXTSEL_Pos)

0x00000200

◆ ADC_CFGR_EXTSEL_Msk

#define ADC_CFGR_EXTSEL_Msk (0xFUL << ADC_CFGR_EXTSEL_Pos)

0x000003C0

◆ ADC_CFGR_EXTSEL_Pos

#define ADC_CFGR_EXTSEL_Pos (6U)

◆ ADC_CFGR_JAUTO

#define ADC_CFGR_JAUTO ADC_CFGR_JAUTO_Msk

ADC group injected automatic trigger mode

◆ ADC_CFGR_JAUTO_Msk

#define ADC_CFGR_JAUTO_Msk (0x1UL << ADC_CFGR_JAUTO_Pos)

0x02000000

◆ ADC_CFGR_JAUTO_Pos

#define ADC_CFGR_JAUTO_Pos (25U)

◆ ADC_CFGR_JAWD1EN

#define ADC_CFGR_JAWD1EN ADC_CFGR_JAWD1EN_Msk

ADC analog watchdog 1 enable on scope ADC group injected

◆ ADC_CFGR_JAWD1EN_Msk

#define ADC_CFGR_JAWD1EN_Msk (0x1UL << ADC_CFGR_JAWD1EN_Pos)

0x01000000

◆ ADC_CFGR_JAWD1EN_Pos

#define ADC_CFGR_JAWD1EN_Pos (24U)

◆ ADC_CFGR_JDISCEN

#define ADC_CFGR_JDISCEN ADC_CFGR_JDISCEN_Msk

ADC Discontinuous mode on injected channels

◆ ADC_CFGR_JDISCEN_Msk

#define ADC_CFGR_JDISCEN_Msk (0x1UL << ADC_CFGR_JDISCEN_Pos)

0x00100000

◆ ADC_CFGR_JDISCEN_Pos

#define ADC_CFGR_JDISCEN_Pos (20U)

◆ ADC_CFGR_JQM

#define ADC_CFGR_JQM ADC_CFGR_JQM_Msk

ADC group injected contexts queue mode

◆ ADC_CFGR_JQM_Msk

#define ADC_CFGR_JQM_Msk (0x1UL << ADC_CFGR_JQM_Pos)

0x00200000

◆ ADC_CFGR_JQM_Pos

#define ADC_CFGR_JQM_Pos (21U)

◆ ADC_CFGR_OVRMOD

#define ADC_CFGR_OVRMOD ADC_CFGR_OVRMOD_Msk

ADC group regular overrun configuration

◆ ADC_CFGR_OVRMOD_Msk

#define ADC_CFGR_OVRMOD_Msk (0x1UL << ADC_CFGR_OVRMOD_Pos)

0x00001000

◆ ADC_CFGR_OVRMOD_Pos

#define ADC_CFGR_OVRMOD_Pos (12U)

◆ ADC_CFGR_RES

#define ADC_CFGR_RES ADC_CFGR_RES_Msk

ADC data resolution

◆ ADC_CFGR_RES_0

#define ADC_CFGR_RES_0 (0x1UL << ADC_CFGR_RES_Pos)

0x00000008

◆ ADC_CFGR_RES_1

#define ADC_CFGR_RES_1 (0x2UL << ADC_CFGR_RES_Pos)

0x00000010

◆ ADC_CFGR_RES_Msk

#define ADC_CFGR_RES_Msk (0x3UL << ADC_CFGR_RES_Pos)

0x00000018

◆ ADC_CFGR_RES_Pos

#define ADC_CFGR_RES_Pos (3U)

◆ ADC_CR_ADCAL

#define ADC_CR_ADCAL ADC_CR_ADCAL_Msk

ADC calibration

◆ ADC_CR_ADCAL_Msk

#define ADC_CR_ADCAL_Msk (0x1UL << ADC_CR_ADCAL_Pos)

0x80000000

◆ ADC_CR_ADCAL_Pos

#define ADC_CR_ADCAL_Pos (31U)

◆ ADC_CR_ADCALDIF

#define ADC_CR_ADCALDIF ADC_CR_ADCALDIF_Msk

ADC differential mode for calibration

◆ ADC_CR_ADCALDIF_Msk

#define ADC_CR_ADCALDIF_Msk (0x1UL << ADC_CR_ADCALDIF_Pos)

0x40000000

◆ ADC_CR_ADCALDIF_Pos

#define ADC_CR_ADCALDIF_Pos (30U)

◆ ADC_CR_ADDIS

#define ADC_CR_ADDIS ADC_CR_ADDIS_Msk

ADC disable

◆ ADC_CR_ADDIS_Msk

#define ADC_CR_ADDIS_Msk (0x1UL << ADC_CR_ADDIS_Pos)

0x00000002

◆ ADC_CR_ADDIS_Pos

#define ADC_CR_ADDIS_Pos (1U)

◆ ADC_CR_ADEN

#define ADC_CR_ADEN ADC_CR_ADEN_Msk

ADC enable

◆ ADC_CR_ADEN_Msk

#define ADC_CR_ADEN_Msk (0x1UL << ADC_CR_ADEN_Pos)

0x00000001

◆ ADC_CR_ADEN_Pos

#define ADC_CR_ADEN_Pos (0U)

◆ ADC_CR_ADSTART

#define ADC_CR_ADSTART ADC_CR_ADSTART_Msk

ADC group regular conversion start

◆ ADC_CR_ADSTART_Msk

#define ADC_CR_ADSTART_Msk (0x1UL << ADC_CR_ADSTART_Pos)

0x00000004

◆ ADC_CR_ADSTART_Pos

#define ADC_CR_ADSTART_Pos (2U)

◆ ADC_CR_ADSTP

#define ADC_CR_ADSTP ADC_CR_ADSTP_Msk

ADC group regular conversion stop

◆ ADC_CR_ADSTP_Msk

#define ADC_CR_ADSTP_Msk (0x1UL << ADC_CR_ADSTP_Pos)

0x00000010

◆ ADC_CR_ADSTP_Pos

#define ADC_CR_ADSTP_Pos (4U)

◆ ADC_CR_ADVREGEN

#define ADC_CR_ADVREGEN ADC_CR_ADVREGEN_Msk

ADC voltage regulator enable

◆ ADC_CR_ADVREGEN_0

#define ADC_CR_ADVREGEN_0 (0x1UL << ADC_CR_ADVREGEN_Pos)

0x10000000

◆ ADC_CR_ADVREGEN_1

#define ADC_CR_ADVREGEN_1 (0x2UL << ADC_CR_ADVREGEN_Pos)

0x20000000

◆ ADC_CR_ADVREGEN_Msk

#define ADC_CR_ADVREGEN_Msk (0x3UL << ADC_CR_ADVREGEN_Pos)

0x30000000

◆ ADC_CR_ADVREGEN_Pos

#define ADC_CR_ADVREGEN_Pos (28U)

◆ ADC_CR_JADSTART

#define ADC_CR_JADSTART ADC_CR_JADSTART_Msk

ADC group injected conversion start

◆ ADC_CR_JADSTART_Msk

#define ADC_CR_JADSTART_Msk (0x1UL << ADC_CR_JADSTART_Pos)

0x00000008

◆ ADC_CR_JADSTART_Pos

#define ADC_CR_JADSTART_Pos (3U)

◆ ADC_CR_JADSTP

#define ADC_CR_JADSTP ADC_CR_JADSTP_Msk

ADC group injected conversion stop

◆ ADC_CR_JADSTP_Msk

#define ADC_CR_JADSTP_Msk (0x1UL << ADC_CR_JADSTP_Pos)

0x00000020

◆ ADC_CR_JADSTP_Pos

#define ADC_CR_JADSTP_Pos (5U)

◆ ADC_CSR_ADRDY_EOC_MST

#define ADC_CSR_ADRDY_EOC_MST ADC_CSR_EOC_MST

◆ ADC_CSR_ADRDY_EOC_SLV

#define ADC_CSR_ADRDY_EOC_SLV ADC_CSR_EOC_SLV

◆ ADC_CSR_ADRDY_EOS_MST

#define ADC_CSR_ADRDY_EOS_MST ADC_CSR_EOS_MST

◆ ADC_CSR_ADRDY_EOS_SLV

#define ADC_CSR_ADRDY_EOS_SLV ADC_CSR_EOS_SLV

◆ ADC_CSR_ADRDY_EOSMP_MST

#define ADC_CSR_ADRDY_EOSMP_MST ADC_CSR_EOSMP_MST

◆ ADC_CSR_ADRDY_EOSMP_SLV

#define ADC_CSR_ADRDY_EOSMP_SLV ADC_CSR_EOSMP_SLV

◆ ADC_CSR_ADRDY_JEOC_MST

#define ADC_CSR_ADRDY_JEOC_MST ADC_CSR_JEOC_MST

◆ ADC_CSR_ADRDY_JEOC_SLV

#define ADC_CSR_ADRDY_JEOC_SLV ADC_CSR_JEOC_SLV

◆ ADC_CSR_ADRDY_JEOS_MST

#define ADC_CSR_ADRDY_JEOS_MST ADC_CSR_JEOS_MST

◆ ADC_CSR_ADRDY_JEOS_SLV

#define ADC_CSR_ADRDY_JEOS_SLV ADC_CSR_JEOS_SLV

◆ ADC_CSR_ADRDY_MST

#define ADC_CSR_ADRDY_MST ADC_CSR_ADRDY_MST_Msk

ADC multimode master ready flag

◆ ADC_CSR_ADRDY_MST_Msk

#define ADC_CSR_ADRDY_MST_Msk (0x1UL << ADC_CSR_ADRDY_MST_Pos)

0x00000001

◆ ADC_CSR_ADRDY_MST_Pos

#define ADC_CSR_ADRDY_MST_Pos (0U)

◆ ADC_CSR_ADRDY_OVR_MST

#define ADC_CSR_ADRDY_OVR_MST ADC_CSR_OVR_MST

◆ ADC_CSR_ADRDY_OVR_SLV

#define ADC_CSR_ADRDY_OVR_SLV ADC_CSR_OVR_SLV

◆ ADC_CSR_ADRDY_SLV

#define ADC_CSR_ADRDY_SLV ADC_CSR_ADRDY_SLV_Msk

ADC multimode slave ready flag

◆ ADC_CSR_ADRDY_SLV_Msk

#define ADC_CSR_ADRDY_SLV_Msk (0x1UL << ADC_CSR_ADRDY_SLV_Pos)

0x00010000

◆ ADC_CSR_ADRDY_SLV_Pos

#define ADC_CSR_ADRDY_SLV_Pos (16U)

◆ ADC_CSR_AWD1_MST

#define ADC_CSR_AWD1_MST ADC_CSR_AWD1_MST_Msk

ADC multimode master analog watchdog 1 flag

◆ ADC_CSR_AWD1_MST_Msk

#define ADC_CSR_AWD1_MST_Msk (0x1UL << ADC_CSR_AWD1_MST_Pos)

0x00000080

◆ ADC_CSR_AWD1_MST_Pos

#define ADC_CSR_AWD1_MST_Pos (7U)

◆ ADC_CSR_AWD1_SLV

#define ADC_CSR_AWD1_SLV ADC_CSR_AWD1_SLV_Msk

ADC multimode slave analog watchdog 1 flag

◆ ADC_CSR_AWD1_SLV_Msk

#define ADC_CSR_AWD1_SLV_Msk (0x1UL << ADC_CSR_AWD1_SLV_Pos)

0x00800000

◆ ADC_CSR_AWD1_SLV_Pos

#define ADC_CSR_AWD1_SLV_Pos (23U)

◆ ADC_CSR_AWD2_MST

#define ADC_CSR_AWD2_MST ADC_CSR_AWD2_MST_Msk

ADC multimode master analog watchdog 2 flag

◆ ADC_CSR_AWD2_MST_Msk

#define ADC_CSR_AWD2_MST_Msk (0x1UL << ADC_CSR_AWD2_MST_Pos)

0x00000100

◆ ADC_CSR_AWD2_MST_Pos

#define ADC_CSR_AWD2_MST_Pos (8U)

◆ ADC_CSR_AWD2_SLV

#define ADC_CSR_AWD2_SLV ADC_CSR_AWD2_SLV_Msk

ADC multimode slave analog watchdog 2 flag

◆ ADC_CSR_AWD2_SLV_Msk

#define ADC_CSR_AWD2_SLV_Msk (0x1UL << ADC_CSR_AWD2_SLV_Pos)

0x01000000

◆ ADC_CSR_AWD2_SLV_Pos

#define ADC_CSR_AWD2_SLV_Pos (24U)

◆ ADC_CSR_AWD3_MST

#define ADC_CSR_AWD3_MST ADC_CSR_AWD3_MST_Msk

ADC multimode master analog watchdog 3 flag

◆ ADC_CSR_AWD3_MST_Msk

#define ADC_CSR_AWD3_MST_Msk (0x1UL << ADC_CSR_AWD3_MST_Pos)

0x00000200

◆ ADC_CSR_AWD3_MST_Pos

#define ADC_CSR_AWD3_MST_Pos (9U)

◆ ADC_CSR_AWD3_SLV

#define ADC_CSR_AWD3_SLV ADC_CSR_AWD3_SLV_Msk

ADC multimode slave analog watchdog 3 flag

◆ ADC_CSR_AWD3_SLV_Msk

#define ADC_CSR_AWD3_SLV_Msk (0x1UL << ADC_CSR_AWD3_SLV_Pos)

0x02000000

◆ ADC_CSR_AWD3_SLV_Pos

#define ADC_CSR_AWD3_SLV_Pos (25U)

◆ ADC_CSR_EOC_MST

#define ADC_CSR_EOC_MST ADC_CSR_EOC_MST_Msk

ADC multimode master group regular end of unitary conversion flag

◆ ADC_CSR_EOC_MST_Msk

#define ADC_CSR_EOC_MST_Msk (0x1UL << ADC_CSR_EOC_MST_Pos)

0x00000004

◆ ADC_CSR_EOC_MST_Pos

#define ADC_CSR_EOC_MST_Pos (2U)

◆ ADC_CSR_EOC_SLV

#define ADC_CSR_EOC_SLV ADC_CSR_EOC_SLV_Msk

ADC multimode slave group regular end of unitary conversion flag

◆ ADC_CSR_EOC_SLV_Msk

#define ADC_CSR_EOC_SLV_Msk (0x1UL << ADC_CSR_EOC_SLV_Pos)

0x00040000

◆ ADC_CSR_EOC_SLV_Pos

#define ADC_CSR_EOC_SLV_Pos (18U)

◆ ADC_CSR_EOS_MST

#define ADC_CSR_EOS_MST ADC_CSR_EOS_MST_Msk

ADC multimode master group regular end of sequence conversions flag

◆ ADC_CSR_EOS_MST_Msk

#define ADC_CSR_EOS_MST_Msk (0x1UL << ADC_CSR_EOS_MST_Pos)

0x00000008

◆ ADC_CSR_EOS_MST_Pos

#define ADC_CSR_EOS_MST_Pos (3U)

◆ ADC_CSR_EOS_SLV

#define ADC_CSR_EOS_SLV ADC_CSR_EOS_SLV_Msk

ADC multimode slave group regular end of sequence conversions flag

◆ ADC_CSR_EOS_SLV_Msk

#define ADC_CSR_EOS_SLV_Msk (0x1UL << ADC_CSR_EOS_SLV_Pos)

0x00080000

◆ ADC_CSR_EOS_SLV_Pos

#define ADC_CSR_EOS_SLV_Pos (19U)

◆ ADC_CSR_EOSMP_MST

#define ADC_CSR_EOSMP_MST ADC_CSR_EOSMP_MST_Msk

ADC multimode master group regular end of sampling flag

◆ ADC_CSR_EOSMP_MST_Msk

#define ADC_CSR_EOSMP_MST_Msk (0x1UL << ADC_CSR_EOSMP_MST_Pos)

0x00000002

◆ ADC_CSR_EOSMP_MST_Pos

#define ADC_CSR_EOSMP_MST_Pos (1U)

◆ ADC_CSR_EOSMP_SLV

#define ADC_CSR_EOSMP_SLV ADC_CSR_EOSMP_SLV_Msk

ADC multimode slave group regular end of sampling flag

◆ ADC_CSR_EOSMP_SLV_Msk

#define ADC_CSR_EOSMP_SLV_Msk (0x1UL << ADC_CSR_EOSMP_SLV_Pos)

0x00020000

◆ ADC_CSR_EOSMP_SLV_Pos

#define ADC_CSR_EOSMP_SLV_Pos (17U)

◆ ADC_CSR_JEOC_MST

#define ADC_CSR_JEOC_MST ADC_CSR_JEOC_MST_Msk

ADC multimode master group injected end of unitary conversion flag

◆ ADC_CSR_JEOC_MST_Msk

#define ADC_CSR_JEOC_MST_Msk (0x1UL << ADC_CSR_JEOC_MST_Pos)

0x00000020

◆ ADC_CSR_JEOC_MST_Pos

#define ADC_CSR_JEOC_MST_Pos (5U)

◆ ADC_CSR_JEOC_SLV

#define ADC_CSR_JEOC_SLV ADC_CSR_JEOC_SLV_Msk

ADC multimode slave group injected end of unitary conversion flag

◆ ADC_CSR_JEOC_SLV_Msk

#define ADC_CSR_JEOC_SLV_Msk (0x1UL << ADC_CSR_JEOC_SLV_Pos)

0x00200000

◆ ADC_CSR_JEOC_SLV_Pos

#define ADC_CSR_JEOC_SLV_Pos (21U)

◆ ADC_CSR_JEOS_MST

#define ADC_CSR_JEOS_MST ADC_CSR_JEOS_MST_Msk

ADC multimode master group injected end of sequence conversions flag

◆ ADC_CSR_JEOS_MST_Msk

#define ADC_CSR_JEOS_MST_Msk (0x1UL << ADC_CSR_JEOS_MST_Pos)

0x00000040

◆ ADC_CSR_JEOS_MST_Pos

#define ADC_CSR_JEOS_MST_Pos (6U)

◆ ADC_CSR_JEOS_SLV

#define ADC_CSR_JEOS_SLV ADC_CSR_JEOS_SLV_Msk

ADC multimode slave group injected end of sequence conversions flag

◆ ADC_CSR_JEOS_SLV_Msk

#define ADC_CSR_JEOS_SLV_Msk (0x1UL << ADC_CSR_JEOS_SLV_Pos)

0x00400000

◆ ADC_CSR_JEOS_SLV_Pos

#define ADC_CSR_JEOS_SLV_Pos (22U)

◆ ADC_CSR_JQOVF_MST

#define ADC_CSR_JQOVF_MST ADC_CSR_JQOVF_MST_Msk

ADC multimode master group injected contexts queue overflow flag

◆ ADC_CSR_JQOVF_MST_Msk

#define ADC_CSR_JQOVF_MST_Msk (0x1UL << ADC_CSR_JQOVF_MST_Pos)

0x00000400

◆ ADC_CSR_JQOVF_MST_Pos

#define ADC_CSR_JQOVF_MST_Pos (10U)

◆ ADC_CSR_JQOVF_SLV

#define ADC_CSR_JQOVF_SLV ADC_CSR_JQOVF_SLV_Msk

ADC multimode slave group injected contexts queue overflow flag

◆ ADC_CSR_JQOVF_SLV_Msk

#define ADC_CSR_JQOVF_SLV_Msk (0x1UL << ADC_CSR_JQOVF_SLV_Pos)

0x04000000

◆ ADC_CSR_JQOVF_SLV_Pos

#define ADC_CSR_JQOVF_SLV_Pos (26U)

◆ ADC_CSR_OVR_MST

#define ADC_CSR_OVR_MST ADC_CSR_OVR_MST_Msk

ADC multimode master group regular overrun flag

◆ ADC_CSR_OVR_MST_Msk

#define ADC_CSR_OVR_MST_Msk (0x1UL << ADC_CSR_OVR_MST_Pos)

0x00000010

◆ ADC_CSR_OVR_MST_Pos

#define ADC_CSR_OVR_MST_Pos (4U)

◆ ADC_CSR_OVR_SLV

#define ADC_CSR_OVR_SLV ADC_CSR_OVR_SLV_Msk

ADC multimode slave group regular overrun flag

◆ ADC_CSR_OVR_SLV_Msk

#define ADC_CSR_OVR_SLV_Msk (0x1UL << ADC_CSR_OVR_SLV_Pos)

0x00100000

◆ ADC_CSR_OVR_SLV_Pos

#define ADC_CSR_OVR_SLV_Pos (20U)

◆ ADC_DIFSEL_DIFSEL

#define ADC_DIFSEL_DIFSEL ADC_DIFSEL_DIFSEL_Msk

ADC channel differential or single-ended mode

◆ ADC_DIFSEL_DIFSEL_0

#define ADC_DIFSEL_DIFSEL_0 (0x00001UL << ADC_DIFSEL_DIFSEL_Pos)

0x00000001

◆ ADC_DIFSEL_DIFSEL_1

#define ADC_DIFSEL_DIFSEL_1 (0x00002UL << ADC_DIFSEL_DIFSEL_Pos)

0x00000002

◆ ADC_DIFSEL_DIFSEL_10

#define ADC_DIFSEL_DIFSEL_10 (0x00400UL << ADC_DIFSEL_DIFSEL_Pos)

0x00000400

◆ ADC_DIFSEL_DIFSEL_11

#define ADC_DIFSEL_DIFSEL_11 (0x00800UL << ADC_DIFSEL_DIFSEL_Pos)

0x00000800

◆ ADC_DIFSEL_DIFSEL_12

#define ADC_DIFSEL_DIFSEL_12 (0x01000UL << ADC_DIFSEL_DIFSEL_Pos)

0x00001000

◆ ADC_DIFSEL_DIFSEL_13

#define ADC_DIFSEL_DIFSEL_13 (0x02000UL << ADC_DIFSEL_DIFSEL_Pos)

0x00002000

◆ ADC_DIFSEL_DIFSEL_14

#define ADC_DIFSEL_DIFSEL_14 (0x04000UL << ADC_DIFSEL_DIFSEL_Pos)

0x00004000

◆ ADC_DIFSEL_DIFSEL_15

#define ADC_DIFSEL_DIFSEL_15 (0x08000UL << ADC_DIFSEL_DIFSEL_Pos)

0x00008000

◆ ADC_DIFSEL_DIFSEL_16

#define ADC_DIFSEL_DIFSEL_16 (0x10000UL << ADC_DIFSEL_DIFSEL_Pos)

0x00010000

◆ ADC_DIFSEL_DIFSEL_17

#define ADC_DIFSEL_DIFSEL_17 (0x20000UL << ADC_DIFSEL_DIFSEL_Pos)

0x00020000

◆ ADC_DIFSEL_DIFSEL_2

#define ADC_DIFSEL_DIFSEL_2 (0x00004UL << ADC_DIFSEL_DIFSEL_Pos)

0x00000004

◆ ADC_DIFSEL_DIFSEL_3

#define ADC_DIFSEL_DIFSEL_3 (0x00008UL << ADC_DIFSEL_DIFSEL_Pos)

0x00000008

◆ ADC_DIFSEL_DIFSEL_4

#define ADC_DIFSEL_DIFSEL_4 (0x00010UL << ADC_DIFSEL_DIFSEL_Pos)

0x00000010

◆ ADC_DIFSEL_DIFSEL_5

#define ADC_DIFSEL_DIFSEL_5 (0x00020UL << ADC_DIFSEL_DIFSEL_Pos)

0x00000020

◆ ADC_DIFSEL_DIFSEL_6

#define ADC_DIFSEL_DIFSEL_6 (0x00040UL << ADC_DIFSEL_DIFSEL_Pos)

0x00000040

◆ ADC_DIFSEL_DIFSEL_7

#define ADC_DIFSEL_DIFSEL_7 (0x00080UL << ADC_DIFSEL_DIFSEL_Pos)

0x00000080

◆ ADC_DIFSEL_DIFSEL_8

#define ADC_DIFSEL_DIFSEL_8 (0x00100UL << ADC_DIFSEL_DIFSEL_Pos)

0x00000100

◆ ADC_DIFSEL_DIFSEL_9

#define ADC_DIFSEL_DIFSEL_9 (0x00200UL << ADC_DIFSEL_DIFSEL_Pos)

0x00000200

◆ ADC_DIFSEL_DIFSEL_Msk

#define ADC_DIFSEL_DIFSEL_Msk (0x3FFFFUL << ADC_DIFSEL_DIFSEL_Pos)

0x0003FFFF

◆ ADC_DIFSEL_DIFSEL_Pos

#define ADC_DIFSEL_DIFSEL_Pos (1U)

◆ ADC_DR_RDATA

#define ADC_DR_RDATA ADC_DR_RDATA_Msk

ADC group regular conversion data

◆ ADC_DR_RDATA_0

#define ADC_DR_RDATA_0 (0x0001UL << ADC_DR_RDATA_Pos)

0x00000001

◆ ADC_DR_RDATA_1

#define ADC_DR_RDATA_1 (0x0002UL << ADC_DR_RDATA_Pos)

0x00000002

◆ ADC_DR_RDATA_10

#define ADC_DR_RDATA_10 (0x0400UL << ADC_DR_RDATA_Pos)

0x00000400

◆ ADC_DR_RDATA_11

#define ADC_DR_RDATA_11 (0x0800UL << ADC_DR_RDATA_Pos)

0x00000800

◆ ADC_DR_RDATA_12

#define ADC_DR_RDATA_12 (0x1000UL << ADC_DR_RDATA_Pos)

0x00001000

◆ ADC_DR_RDATA_13

#define ADC_DR_RDATA_13 (0x2000UL << ADC_DR_RDATA_Pos)

0x00002000

◆ ADC_DR_RDATA_14

#define ADC_DR_RDATA_14 (0x4000UL << ADC_DR_RDATA_Pos)

0x00004000

◆ ADC_DR_RDATA_15

#define ADC_DR_RDATA_15 (0x8000UL << ADC_DR_RDATA_Pos)

0x00008000

◆ ADC_DR_RDATA_2

#define ADC_DR_RDATA_2 (0x0004UL << ADC_DR_RDATA_Pos)

0x00000004

◆ ADC_DR_RDATA_3

#define ADC_DR_RDATA_3 (0x0008UL << ADC_DR_RDATA_Pos)

0x00000008

◆ ADC_DR_RDATA_4

#define ADC_DR_RDATA_4 (0x0010UL << ADC_DR_RDATA_Pos)

0x00000010

◆ ADC_DR_RDATA_5

#define ADC_DR_RDATA_5 (0x0020UL << ADC_DR_RDATA_Pos)

0x00000020

◆ ADC_DR_RDATA_6

#define ADC_DR_RDATA_6 (0x0040UL << ADC_DR_RDATA_Pos)

0x00000040

◆ ADC_DR_RDATA_7

#define ADC_DR_RDATA_7 (0x0080UL << ADC_DR_RDATA_Pos)

0x00000080

◆ ADC_DR_RDATA_8

#define ADC_DR_RDATA_8 (0x0100UL << ADC_DR_RDATA_Pos)

0x00000100

◆ ADC_DR_RDATA_9

#define ADC_DR_RDATA_9 (0x0200UL << ADC_DR_RDATA_Pos)

0x00000200

◆ ADC_DR_RDATA_Msk

#define ADC_DR_RDATA_Msk (0xFFFFUL << ADC_DR_RDATA_Pos)

0x0000FFFF

◆ ADC_DR_RDATA_Pos

#define ADC_DR_RDATA_Pos (0U)

◆ ADC_IER_ADRDYIE

#define ADC_IER_ADRDYIE ADC_IER_ADRDYIE_Msk

ADC ready interrupt

◆ ADC_IER_ADRDYIE_Msk

#define ADC_IER_ADRDYIE_Msk (0x1UL << ADC_IER_ADRDYIE_Pos)

0x00000001

◆ ADC_IER_ADRDYIE_Pos

#define ADC_IER_ADRDYIE_Pos (0U)

◆ ADC_IER_AWD1

#define ADC_IER_AWD1 (ADC_IER_AWD1IE)

◆ ADC_IER_AWD1IE

#define ADC_IER_AWD1IE ADC_IER_AWD1IE_Msk

ADC analog watchdog 1 interrupt

◆ ADC_IER_AWD1IE_Msk

#define ADC_IER_AWD1IE_Msk (0x1UL << ADC_IER_AWD1IE_Pos)

0x00000080

◆ ADC_IER_AWD1IE_Pos

#define ADC_IER_AWD1IE_Pos (7U)

◆ ADC_IER_AWD2

#define ADC_IER_AWD2 (ADC_IER_AWD2IE)

◆ ADC_IER_AWD2IE

#define ADC_IER_AWD2IE ADC_IER_AWD2IE_Msk

ADC analog watchdog 2 interrupt

◆ ADC_IER_AWD2IE_Msk

#define ADC_IER_AWD2IE_Msk (0x1UL << ADC_IER_AWD2IE_Pos)

0x00000100

◆ ADC_IER_AWD2IE_Pos

#define ADC_IER_AWD2IE_Pos (8U)

◆ ADC_IER_AWD3

#define ADC_IER_AWD3 (ADC_IER_AWD3IE)

◆ ADC_IER_AWD3IE

#define ADC_IER_AWD3IE ADC_IER_AWD3IE_Msk

ADC analog watchdog 3 interrupt

◆ ADC_IER_AWD3IE_Msk

#define ADC_IER_AWD3IE_Msk (0x1UL << ADC_IER_AWD3IE_Pos)

0x00000200

◆ ADC_IER_AWD3IE_Pos

#define ADC_IER_AWD3IE_Pos (9U)

◆ ADC_IER_EOC

#define ADC_IER_EOC (ADC_IER_EOCIE)

◆ ADC_IER_EOCIE

#define ADC_IER_EOCIE ADC_IER_EOCIE_Msk

ADC group regular end of unitary conversion interrupt

◆ ADC_IER_EOCIE_Msk

#define ADC_IER_EOCIE_Msk (0x1UL << ADC_IER_EOCIE_Pos)

0x00000004

◆ ADC_IER_EOCIE_Pos

#define ADC_IER_EOCIE_Pos (2U)

◆ ADC_IER_EOS

#define ADC_IER_EOS (ADC_IER_EOSIE)

◆ ADC_IER_EOSIE

#define ADC_IER_EOSIE ADC_IER_EOSIE_Msk

ADC group regular end of sequence conversions interrupt

◆ ADC_IER_EOSIE_Msk

#define ADC_IER_EOSIE_Msk (0x1UL << ADC_IER_EOSIE_Pos)

0x00000008

◆ ADC_IER_EOSIE_Pos

#define ADC_IER_EOSIE_Pos (3U)

◆ ADC_IER_EOSMP

#define ADC_IER_EOSMP (ADC_IER_EOSMPIE)

◆ ADC_IER_EOSMPIE

#define ADC_IER_EOSMPIE ADC_IER_EOSMPIE_Msk

ADC group regular end of sampling interrupt

◆ ADC_IER_EOSMPIE_Msk

#define ADC_IER_EOSMPIE_Msk (0x1UL << ADC_IER_EOSMPIE_Pos)

0x00000002

◆ ADC_IER_EOSMPIE_Pos

#define ADC_IER_EOSMPIE_Pos (1U)

◆ ADC_IER_JEOC

#define ADC_IER_JEOC (ADC_IER_JEOCIE)

◆ ADC_IER_JEOCIE

#define ADC_IER_JEOCIE ADC_IER_JEOCIE_Msk

ADC group injected end of unitary conversion interrupt

◆ ADC_IER_JEOCIE_Msk

#define ADC_IER_JEOCIE_Msk (0x1UL << ADC_IER_JEOCIE_Pos)

0x00000020

◆ ADC_IER_JEOCIE_Pos

#define ADC_IER_JEOCIE_Pos (5U)

◆ ADC_IER_JEOS

#define ADC_IER_JEOS (ADC_IER_JEOSIE)

◆ ADC_IER_JEOSIE

#define ADC_IER_JEOSIE ADC_IER_JEOSIE_Msk

ADC group injected end of sequence conversions interrupt

◆ ADC_IER_JEOSIE_Msk

#define ADC_IER_JEOSIE_Msk (0x1UL << ADC_IER_JEOSIE_Pos)

0x00000040

◆ ADC_IER_JEOSIE_Pos

#define ADC_IER_JEOSIE_Pos (6U)

◆ ADC_IER_JQOVF

#define ADC_IER_JQOVF (ADC_IER_JQOVFIE)

◆ ADC_IER_JQOVFIE

#define ADC_IER_JQOVFIE ADC_IER_JQOVFIE_Msk

ADC group injected contexts queue overflow interrupt

◆ ADC_IER_JQOVFIE_Msk

#define ADC_IER_JQOVFIE_Msk (0x1UL << ADC_IER_JQOVFIE_Pos)

0x00000400

◆ ADC_IER_JQOVFIE_Pos

#define ADC_IER_JQOVFIE_Pos (10U)

◆ ADC_IER_OVR

#define ADC_IER_OVR (ADC_IER_OVRIE)

◆ ADC_IER_OVRIE

#define ADC_IER_OVRIE ADC_IER_OVRIE_Msk

ADC group regular overrun interrupt

◆ ADC_IER_OVRIE_Msk

#define ADC_IER_OVRIE_Msk (0x1UL << ADC_IER_OVRIE_Pos)

0x00000010

◆ ADC_IER_OVRIE_Pos

#define ADC_IER_OVRIE_Pos (4U)

◆ ADC_IER_RDY

#define ADC_IER_RDY (ADC_IER_ADRDYIE)

◆ ADC_ISR_ADRD

#define ADC_ISR_ADRD (ADC_ISR_ADRDY)

◆ ADC_ISR_ADRDY

#define ADC_ISR_ADRDY ADC_ISR_ADRDY_Msk

ADC ready flag

◆ ADC_ISR_ADRDY_Msk

#define ADC_ISR_ADRDY_Msk (0x1UL << ADC_ISR_ADRDY_Pos)

0x00000001

◆ ADC_ISR_ADRDY_Pos

#define ADC_ISR_ADRDY_Pos (0U)

◆ ADC_ISR_AWD1

#define ADC_ISR_AWD1 ADC_ISR_AWD1_Msk

ADC analog watchdog 1 flag

◆ ADC_ISR_AWD1_Msk

#define ADC_ISR_AWD1_Msk (0x1UL << ADC_ISR_AWD1_Pos)

0x00000080

◆ ADC_ISR_AWD1_Pos

#define ADC_ISR_AWD1_Pos (7U)

◆ ADC_ISR_AWD2

#define ADC_ISR_AWD2 ADC_ISR_AWD2_Msk

ADC analog watchdog 2 flag

◆ ADC_ISR_AWD2_Msk

#define ADC_ISR_AWD2_Msk (0x1UL << ADC_ISR_AWD2_Pos)

0x00000100

◆ ADC_ISR_AWD2_Pos

#define ADC_ISR_AWD2_Pos (8U)

◆ ADC_ISR_AWD3

#define ADC_ISR_AWD3 ADC_ISR_AWD3_Msk

ADC analog watchdog 3 flag

◆ ADC_ISR_AWD3_Msk

#define ADC_ISR_AWD3_Msk (0x1UL << ADC_ISR_AWD3_Pos)

0x00000200

◆ ADC_ISR_AWD3_Pos

#define ADC_ISR_AWD3_Pos (9U)

◆ ADC_ISR_EOC

#define ADC_ISR_EOC ADC_ISR_EOC_Msk

ADC group regular end of unitary conversion flag

◆ ADC_ISR_EOC_Msk

#define ADC_ISR_EOC_Msk (0x1UL << ADC_ISR_EOC_Pos)

0x00000004

◆ ADC_ISR_EOC_Pos

#define ADC_ISR_EOC_Pos (2U)

◆ ADC_ISR_EOS

#define ADC_ISR_EOS ADC_ISR_EOS_Msk

ADC group regular end of sequence conversions flag

◆ ADC_ISR_EOS_Msk

#define ADC_ISR_EOS_Msk (0x1UL << ADC_ISR_EOS_Pos)

0x00000008

◆ ADC_ISR_EOS_Pos

#define ADC_ISR_EOS_Pos (3U)

◆ ADC_ISR_EOSMP

#define ADC_ISR_EOSMP ADC_ISR_EOSMP_Msk

ADC group regular end of sampling flag

◆ ADC_ISR_EOSMP_Msk

#define ADC_ISR_EOSMP_Msk (0x1UL << ADC_ISR_EOSMP_Pos)

0x00000002

◆ ADC_ISR_EOSMP_Pos

#define ADC_ISR_EOSMP_Pos (1U)

◆ ADC_ISR_JEOC

#define ADC_ISR_JEOC ADC_ISR_JEOC_Msk

ADC group injected end of unitary conversion flag

◆ ADC_ISR_JEOC_Msk

#define ADC_ISR_JEOC_Msk (0x1UL << ADC_ISR_JEOC_Pos)

0x00000020

◆ ADC_ISR_JEOC_Pos

#define ADC_ISR_JEOC_Pos (5U)

◆ ADC_ISR_JEOS

#define ADC_ISR_JEOS ADC_ISR_JEOS_Msk

ADC group injected end of sequence conversions flag

◆ ADC_ISR_JEOS_Msk

#define ADC_ISR_JEOS_Msk (0x1UL << ADC_ISR_JEOS_Pos)

0x00000040

◆ ADC_ISR_JEOS_Pos

#define ADC_ISR_JEOS_Pos (6U)

◆ ADC_ISR_JQOVF

#define ADC_ISR_JQOVF ADC_ISR_JQOVF_Msk

ADC group injected contexts queue overflow flag

◆ ADC_ISR_JQOVF_Msk

#define ADC_ISR_JQOVF_Msk (0x1UL << ADC_ISR_JQOVF_Pos)

0x00000400

◆ ADC_ISR_JQOVF_Pos

#define ADC_ISR_JQOVF_Pos (10U)

◆ ADC_ISR_OVR

#define ADC_ISR_OVR ADC_ISR_OVR_Msk

ADC group regular overrun flag

◆ ADC_ISR_OVR_Msk

#define ADC_ISR_OVR_Msk (0x1UL << ADC_ISR_OVR_Pos)

0x00000010

◆ ADC_ISR_OVR_Pos

#define ADC_ISR_OVR_Pos (4U)

◆ ADC_JDR1_JDATA

#define ADC_JDR1_JDATA ADC_JDR1_JDATA_Msk

ADC group injected sequencer rank 1 conversion data

◆ ADC_JDR1_JDATA_0

#define ADC_JDR1_JDATA_0 (0x0001UL << ADC_JDR1_JDATA_Pos)

0x00000001

◆ ADC_JDR1_JDATA_1

#define ADC_JDR1_JDATA_1 (0x0002UL << ADC_JDR1_JDATA_Pos)

0x00000002

◆ ADC_JDR1_JDATA_10

#define ADC_JDR1_JDATA_10 (0x0400UL << ADC_JDR1_JDATA_Pos)

0x00000400

◆ ADC_JDR1_JDATA_11

#define ADC_JDR1_JDATA_11 (0x0800UL << ADC_JDR1_JDATA_Pos)

0x00000800

◆ ADC_JDR1_JDATA_12

#define ADC_JDR1_JDATA_12 (0x1000UL << ADC_JDR1_JDATA_Pos)

0x00001000

◆ ADC_JDR1_JDATA_13

#define ADC_JDR1_JDATA_13 (0x2000UL << ADC_JDR1_JDATA_Pos)

0x00002000

◆ ADC_JDR1_JDATA_14

#define ADC_JDR1_JDATA_14 (0x4000UL << ADC_JDR1_JDATA_Pos)

0x00004000

◆ ADC_JDR1_JDATA_15

#define ADC_JDR1_JDATA_15 (0x8000UL << ADC_JDR1_JDATA_Pos)

0x00008000

◆ ADC_JDR1_JDATA_2

#define ADC_JDR1_JDATA_2 (0x0004UL << ADC_JDR1_JDATA_Pos)

0x00000004

◆ ADC_JDR1_JDATA_3

#define ADC_JDR1_JDATA_3 (0x0008UL << ADC_JDR1_JDATA_Pos)

0x00000008

◆ ADC_JDR1_JDATA_4

#define ADC_JDR1_JDATA_4 (0x0010UL << ADC_JDR1_JDATA_Pos)

0x00000010

◆ ADC_JDR1_JDATA_5

#define ADC_JDR1_JDATA_5 (0x0020UL << ADC_JDR1_JDATA_Pos)

0x00000020

◆ ADC_JDR1_JDATA_6

#define ADC_JDR1_JDATA_6 (0x0040UL << ADC_JDR1_JDATA_Pos)

0x00000040

◆ ADC_JDR1_JDATA_7

#define ADC_JDR1_JDATA_7 (0x0080UL << ADC_JDR1_JDATA_Pos)

0x00000080

◆ ADC_JDR1_JDATA_8

#define ADC_JDR1_JDATA_8 (0x0100UL << ADC_JDR1_JDATA_Pos)

0x00000100

◆ ADC_JDR1_JDATA_9

#define ADC_JDR1_JDATA_9 (0x0200UL << ADC_JDR1_JDATA_Pos)

0x00000200

◆ ADC_JDR1_JDATA_Msk

#define ADC_JDR1_JDATA_Msk (0xFFFFUL << ADC_JDR1_JDATA_Pos)

0x0000FFFF

◆ ADC_JDR1_JDATA_Pos

#define ADC_JDR1_JDATA_Pos (0U)

◆ ADC_JDR2_JDATA

#define ADC_JDR2_JDATA ADC_JDR2_JDATA_Msk

ADC group injected sequencer rank 2 conversion data

◆ ADC_JDR2_JDATA_0

#define ADC_JDR2_JDATA_0 (0x0001UL << ADC_JDR2_JDATA_Pos)

0x00000001

◆ ADC_JDR2_JDATA_1

#define ADC_JDR2_JDATA_1 (0x0002UL << ADC_JDR2_JDATA_Pos)

0x00000002

◆ ADC_JDR2_JDATA_10

#define ADC_JDR2_JDATA_10 (0x0400UL << ADC_JDR2_JDATA_Pos)

0x00000400

◆ ADC_JDR2_JDATA_11

#define ADC_JDR2_JDATA_11 (0x0800UL << ADC_JDR2_JDATA_Pos)

0x00000800

◆ ADC_JDR2_JDATA_12

#define ADC_JDR2_JDATA_12 (0x1000UL << ADC_JDR2_JDATA_Pos)

0x00001000

◆ ADC_JDR2_JDATA_13

#define ADC_JDR2_JDATA_13 (0x2000UL << ADC_JDR2_JDATA_Pos)

0x00002000

◆ ADC_JDR2_JDATA_14

#define ADC_JDR2_JDATA_14 (0x4000UL << ADC_JDR2_JDATA_Pos)

0x00004000

◆ ADC_JDR2_JDATA_15

#define ADC_JDR2_JDATA_15 (0x8000UL << ADC_JDR2_JDATA_Pos)

0x00008000

◆ ADC_JDR2_JDATA_2

#define ADC_JDR2_JDATA_2 (0x0004UL << ADC_JDR2_JDATA_Pos)

0x00000004

◆ ADC_JDR2_JDATA_3

#define ADC_JDR2_JDATA_3 (0x0008UL << ADC_JDR2_JDATA_Pos)

0x00000008

◆ ADC_JDR2_JDATA_4

#define ADC_JDR2_JDATA_4 (0x0010UL << ADC_JDR2_JDATA_Pos)

0x00000010

◆ ADC_JDR2_JDATA_5

#define ADC_JDR2_JDATA_5 (0x0020UL << ADC_JDR2_JDATA_Pos)

0x00000020

◆ ADC_JDR2_JDATA_6

#define ADC_JDR2_JDATA_6 (0x0040UL << ADC_JDR2_JDATA_Pos)

0x00000040

◆ ADC_JDR2_JDATA_7

#define ADC_JDR2_JDATA_7 (0x0080UL << ADC_JDR2_JDATA_Pos)

0x00000080

◆ ADC_JDR2_JDATA_8

#define ADC_JDR2_JDATA_8 (0x0100UL << ADC_JDR2_JDATA_Pos)

0x00000100

◆ ADC_JDR2_JDATA_9

#define ADC_JDR2_JDATA_9 (0x0200UL << ADC_JDR2_JDATA_Pos)

0x00000200

◆ ADC_JDR2_JDATA_Msk

#define ADC_JDR2_JDATA_Msk (0xFFFFUL << ADC_JDR2_JDATA_Pos)

0x0000FFFF

◆ ADC_JDR2_JDATA_Pos

#define ADC_JDR2_JDATA_Pos (0U)

◆ ADC_JDR3_JDATA

#define ADC_JDR3_JDATA ADC_JDR3_JDATA_Msk

ADC group injected sequencer rank 3 conversion data

◆ ADC_JDR3_JDATA_0

#define ADC_JDR3_JDATA_0 (0x0001UL << ADC_JDR3_JDATA_Pos)

0x00000001

◆ ADC_JDR3_JDATA_1

#define ADC_JDR3_JDATA_1 (0x0002UL << ADC_JDR3_JDATA_Pos)

0x00000002

◆ ADC_JDR3_JDATA_10

#define ADC_JDR3_JDATA_10 (0x0400UL << ADC_JDR3_JDATA_Pos)

0x00000400

◆ ADC_JDR3_JDATA_11

#define ADC_JDR3_JDATA_11 (0x0800UL << ADC_JDR3_JDATA_Pos)

0x00000800

◆ ADC_JDR3_JDATA_12

#define ADC_JDR3_JDATA_12 (0x1000UL << ADC_JDR3_JDATA_Pos)

0x00001000

◆ ADC_JDR3_JDATA_13

#define ADC_JDR3_JDATA_13 (0x2000UL << ADC_JDR3_JDATA_Pos)

0x00002000

◆ ADC_JDR3_JDATA_14

#define ADC_JDR3_JDATA_14 (0x4000UL << ADC_JDR3_JDATA_Pos)

0x00004000

◆ ADC_JDR3_JDATA_15

#define ADC_JDR3_JDATA_15 (0x8000UL << ADC_JDR3_JDATA_Pos)

0x00008000

◆ ADC_JDR3_JDATA_2

#define ADC_JDR3_JDATA_2 (0x0004UL << ADC_JDR3_JDATA_Pos)

0x00000004

◆ ADC_JDR3_JDATA_3

#define ADC_JDR3_JDATA_3 (0x0008UL << ADC_JDR3_JDATA_Pos)

0x00000008

◆ ADC_JDR3_JDATA_4

#define ADC_JDR3_JDATA_4 (0x0010UL << ADC_JDR3_JDATA_Pos)

0x00000010

◆ ADC_JDR3_JDATA_5

#define ADC_JDR3_JDATA_5 (0x0020UL << ADC_JDR3_JDATA_Pos)

0x00000020

◆ ADC_JDR3_JDATA_6

#define ADC_JDR3_JDATA_6 (0x0040UL << ADC_JDR3_JDATA_Pos)

0x00000040

◆ ADC_JDR3_JDATA_7

#define ADC_JDR3_JDATA_7 (0x0080UL << ADC_JDR3_JDATA_Pos)

0x00000080

◆ ADC_JDR3_JDATA_8

#define ADC_JDR3_JDATA_8 (0x0100UL << ADC_JDR3_JDATA_Pos)

0x00000100

◆ ADC_JDR3_JDATA_9

#define ADC_JDR3_JDATA_9 (0x0200UL << ADC_JDR3_JDATA_Pos)

0x00000200

◆ ADC_JDR3_JDATA_Msk

#define ADC_JDR3_JDATA_Msk (0xFFFFUL << ADC_JDR3_JDATA_Pos)

0x0000FFFF

◆ ADC_JDR3_JDATA_Pos

#define ADC_JDR3_JDATA_Pos (0U)

◆ ADC_JDR4_JDATA

#define ADC_JDR4_JDATA ADC_JDR4_JDATA_Msk

ADC group injected sequencer rank 4 conversion data

◆ ADC_JDR4_JDATA_0

#define ADC_JDR4_JDATA_0 (0x0001UL << ADC_JDR4_JDATA_Pos)

0x00000001

◆ ADC_JDR4_JDATA_1

#define ADC_JDR4_JDATA_1 (0x0002UL << ADC_JDR4_JDATA_Pos)

0x00000002

◆ ADC_JDR4_JDATA_10

#define ADC_JDR4_JDATA_10 (0x0400UL << ADC_JDR4_JDATA_Pos)

0x00000400

◆ ADC_JDR4_JDATA_11

#define ADC_JDR4_JDATA_11 (0x0800UL << ADC_JDR4_JDATA_Pos)

0x00000800

◆ ADC_JDR4_JDATA_12

#define ADC_JDR4_JDATA_12 (0x1000UL << ADC_JDR4_JDATA_Pos)

0x00001000

◆ ADC_JDR4_JDATA_13

#define ADC_JDR4_JDATA_13 (0x2000UL << ADC_JDR4_JDATA_Pos)

0x00002000

◆ ADC_JDR4_JDATA_14

#define ADC_JDR4_JDATA_14 (0x4000UL << ADC_JDR4_JDATA_Pos)

0x00004000

◆ ADC_JDR4_JDATA_15

#define ADC_JDR4_JDATA_15 (0x8000UL << ADC_JDR4_JDATA_Pos)

0x00008000

◆ ADC_JDR4_JDATA_2

#define ADC_JDR4_JDATA_2 (0x0004UL << ADC_JDR4_JDATA_Pos)

0x00000004

◆ ADC_JDR4_JDATA_3

#define ADC_JDR4_JDATA_3 (0x0008UL << ADC_JDR4_JDATA_Pos)

0x00000008

◆ ADC_JDR4_JDATA_4

#define ADC_JDR4_JDATA_4 (0x0010UL << ADC_JDR4_JDATA_Pos)

0x00000010

◆ ADC_JDR4_JDATA_5

#define ADC_JDR4_JDATA_5 (0x0020UL << ADC_JDR4_JDATA_Pos)

0x00000020

◆ ADC_JDR4_JDATA_6

#define ADC_JDR4_JDATA_6 (0x0040UL << ADC_JDR4_JDATA_Pos)

0x00000040

◆ ADC_JDR4_JDATA_7

#define ADC_JDR4_JDATA_7 (0x0080UL << ADC_JDR4_JDATA_Pos)

0x00000080

◆ ADC_JDR4_JDATA_8

#define ADC_JDR4_JDATA_8 (0x0100UL << ADC_JDR4_JDATA_Pos)

0x00000100

◆ ADC_JDR4_JDATA_9

#define ADC_JDR4_JDATA_9 (0x0200UL << ADC_JDR4_JDATA_Pos)

0x00000200

◆ ADC_JDR4_JDATA_Msk

#define ADC_JDR4_JDATA_Msk (0xFFFFUL << ADC_JDR4_JDATA_Pos)

0x0000FFFF

◆ ADC_JDR4_JDATA_Pos

#define ADC_JDR4_JDATA_Pos (0U)

◆ ADC_JSQR_JEXTEN

#define ADC_JSQR_JEXTEN ADC_JSQR_JEXTEN_Msk

ADC group injected external trigger polarity

◆ ADC_JSQR_JEXTEN_0

#define ADC_JSQR_JEXTEN_0 (0x1UL << ADC_JSQR_JEXTEN_Pos)

0x00000040

◆ ADC_JSQR_JEXTEN_1

#define ADC_JSQR_JEXTEN_1 (0x2UL << ADC_JSQR_JEXTEN_Pos)

0x00000080

◆ ADC_JSQR_JEXTEN_Msk

#define ADC_JSQR_JEXTEN_Msk (0x3UL << ADC_JSQR_JEXTEN_Pos)

0x000000C0

◆ ADC_JSQR_JEXTEN_Pos

#define ADC_JSQR_JEXTEN_Pos (6U)

◆ ADC_JSQR_JEXTSEL

#define ADC_JSQR_JEXTSEL ADC_JSQR_JEXTSEL_Msk

ADC group injected external trigger source

◆ ADC_JSQR_JEXTSEL_0

#define ADC_JSQR_JEXTSEL_0 (0x1UL << ADC_JSQR_JEXTSEL_Pos)

0x00000004

◆ ADC_JSQR_JEXTSEL_1

#define ADC_JSQR_JEXTSEL_1 (0x2UL << ADC_JSQR_JEXTSEL_Pos)

0x00000008

◆ ADC_JSQR_JEXTSEL_2

#define ADC_JSQR_JEXTSEL_2 (0x4UL << ADC_JSQR_JEXTSEL_Pos)

0x00000010

◆ ADC_JSQR_JEXTSEL_3

#define ADC_JSQR_JEXTSEL_3 (0x8UL << ADC_JSQR_JEXTSEL_Pos)

0x00000020

◆ ADC_JSQR_JEXTSEL_Msk

#define ADC_JSQR_JEXTSEL_Msk (0xFUL << ADC_JSQR_JEXTSEL_Pos)

0x0000003C

◆ ADC_JSQR_JEXTSEL_Pos

#define ADC_JSQR_JEXTSEL_Pos (2U)

◆ ADC_JSQR_JL

#define ADC_JSQR_JL ADC_JSQR_JL_Msk

ADC group injected sequencer scan length

◆ ADC_JSQR_JL_0

#define ADC_JSQR_JL_0 (0x1UL << ADC_JSQR_JL_Pos)

0x00000001

◆ ADC_JSQR_JL_1

#define ADC_JSQR_JL_1 (0x2UL << ADC_JSQR_JL_Pos)

0x00000002

◆ ADC_JSQR_JL_Msk

#define ADC_JSQR_JL_Msk (0x3UL << ADC_JSQR_JL_Pos)

0x00000003

◆ ADC_JSQR_JL_Pos

#define ADC_JSQR_JL_Pos (0U)

◆ ADC_JSQR_JSQ1

#define ADC_JSQR_JSQ1 ADC_JSQR_JSQ1_Msk

ADC group injected sequencer rank 1

◆ ADC_JSQR_JSQ1_0

#define ADC_JSQR_JSQ1_0 (0x01UL << ADC_JSQR_JSQ1_Pos)

0x00000100

◆ ADC_JSQR_JSQ1_1

#define ADC_JSQR_JSQ1_1 (0x02UL << ADC_JSQR_JSQ1_Pos)

0x00000200

◆ ADC_JSQR_JSQ1_2

#define ADC_JSQR_JSQ1_2 (0x04UL << ADC_JSQR_JSQ1_Pos)

0x00000400

◆ ADC_JSQR_JSQ1_3

#define ADC_JSQR_JSQ1_3 (0x08UL << ADC_JSQR_JSQ1_Pos)

0x00000800

◆ ADC_JSQR_JSQ1_4

#define ADC_JSQR_JSQ1_4 (0x10UL << ADC_JSQR_JSQ1_Pos)

0x00001000

◆ ADC_JSQR_JSQ1_Msk

#define ADC_JSQR_JSQ1_Msk (0x1FUL << ADC_JSQR_JSQ1_Pos)

0x00001F00

◆ ADC_JSQR_JSQ1_Pos

#define ADC_JSQR_JSQ1_Pos (8U)

◆ ADC_JSQR_JSQ2

#define ADC_JSQR_JSQ2 ADC_JSQR_JSQ2_Msk

ADC group injected sequencer rank 2

◆ ADC_JSQR_JSQ2_0

#define ADC_JSQR_JSQ2_0 (0x01UL << ADC_JSQR_JSQ2_Pos)

0x00004000

◆ ADC_JSQR_JSQ2_1

#define ADC_JSQR_JSQ2_1 (0x02UL << ADC_JSQR_JSQ2_Pos)

0x00008000

◆ ADC_JSQR_JSQ2_2

#define ADC_JSQR_JSQ2_2 (0x04UL << ADC_JSQR_JSQ2_Pos)

0x00010000

◆ ADC_JSQR_JSQ2_3

#define ADC_JSQR_JSQ2_3 (0x08UL << ADC_JSQR_JSQ2_Pos)

0x00020000

◆ ADC_JSQR_JSQ2_4

#define ADC_JSQR_JSQ2_4 (0x10UL << ADC_JSQR_JSQ2_Pos)

0x00040000

◆ ADC_JSQR_JSQ2_Msk

#define ADC_JSQR_JSQ2_Msk (0x1FUL << ADC_JSQR_JSQ2_Pos)

0x0007C000

◆ ADC_JSQR_JSQ2_Pos

#define ADC_JSQR_JSQ2_Pos (14U)

◆ ADC_JSQR_JSQ3

#define ADC_JSQR_JSQ3 ADC_JSQR_JSQ3_Msk

ADC group injected sequencer rank 3

◆ ADC_JSQR_JSQ3_0

#define ADC_JSQR_JSQ3_0 (0x01UL << ADC_JSQR_JSQ3_Pos)

0x00100000

◆ ADC_JSQR_JSQ3_1

#define ADC_JSQR_JSQ3_1 (0x02UL << ADC_JSQR_JSQ3_Pos)

0x00200000

◆ ADC_JSQR_JSQ3_2

#define ADC_JSQR_JSQ3_2 (0x04UL << ADC_JSQR_JSQ3_Pos)

0x00400000

◆ ADC_JSQR_JSQ3_3

#define ADC_JSQR_JSQ3_3 (0x08UL << ADC_JSQR_JSQ3_Pos)

0x00800000

◆ ADC_JSQR_JSQ3_4

#define ADC_JSQR_JSQ3_4 (0x10UL << ADC_JSQR_JSQ3_Pos)

0x01000000

◆ ADC_JSQR_JSQ3_Msk

#define ADC_JSQR_JSQ3_Msk (0x1FUL << ADC_JSQR_JSQ3_Pos)

0x01F00000

◆ ADC_JSQR_JSQ3_Pos

#define ADC_JSQR_JSQ3_Pos (20U)

◆ ADC_JSQR_JSQ4

#define ADC_JSQR_JSQ4 ADC_JSQR_JSQ4_Msk

ADC group injected sequencer rank 4

◆ ADC_JSQR_JSQ4_0

#define ADC_JSQR_JSQ4_0 (0x01UL << ADC_JSQR_JSQ4_Pos)

0x04000000

◆ ADC_JSQR_JSQ4_1

#define ADC_JSQR_JSQ4_1 (0x02UL << ADC_JSQR_JSQ4_Pos)

0x08000000

◆ ADC_JSQR_JSQ4_2

#define ADC_JSQR_JSQ4_2 (0x04UL << ADC_JSQR_JSQ4_Pos)

0x10000000

◆ ADC_JSQR_JSQ4_3

#define ADC_JSQR_JSQ4_3 (0x08UL << ADC_JSQR_JSQ4_Pos)

0x20000000

◆ ADC_JSQR_JSQ4_4

#define ADC_JSQR_JSQ4_4 (0x10UL << ADC_JSQR_JSQ4_Pos)

0x40000000

◆ ADC_JSQR_JSQ4_Msk

#define ADC_JSQR_JSQ4_Msk (0x1FUL << ADC_JSQR_JSQ4_Pos)

0x7C000000

◆ ADC_JSQR_JSQ4_Pos

#define ADC_JSQR_JSQ4_Pos (26U)

◆ ADC_MULTIMODE_SUPPORT

#define ADC_MULTIMODE_SUPPORT

ADC feature available only on specific devices: multimode available on devices with several ADC instances

◆ ADC_OFR1_OFFSET1

#define ADC_OFR1_OFFSET1 ADC_OFR1_OFFSET1_Msk

ADC offset number 1 offset level

◆ ADC_OFR1_OFFSET1_0

#define ADC_OFR1_OFFSET1_0 (0x001UL << ADC_OFR1_OFFSET1_Pos)

0x00000001

◆ ADC_OFR1_OFFSET1_1

#define ADC_OFR1_OFFSET1_1 (0x002UL << ADC_OFR1_OFFSET1_Pos)

0x00000002

◆ ADC_OFR1_OFFSET1_10

#define ADC_OFR1_OFFSET1_10 (0x400UL << ADC_OFR1_OFFSET1_Pos)

0x00000400

◆ ADC_OFR1_OFFSET1_11

#define ADC_OFR1_OFFSET1_11 (0x800UL << ADC_OFR1_OFFSET1_Pos)

0x00000800

◆ ADC_OFR1_OFFSET1_2

#define ADC_OFR1_OFFSET1_2 (0x004UL << ADC_OFR1_OFFSET1_Pos)

0x00000004

◆ ADC_OFR1_OFFSET1_3

#define ADC_OFR1_OFFSET1_3 (0x008UL << ADC_OFR1_OFFSET1_Pos)

0x00000008

◆ ADC_OFR1_OFFSET1_4

#define ADC_OFR1_OFFSET1_4 (0x010UL << ADC_OFR1_OFFSET1_Pos)

0x00000010

◆ ADC_OFR1_OFFSET1_5

#define ADC_OFR1_OFFSET1_5 (0x020UL << ADC_OFR1_OFFSET1_Pos)

0x00000020

◆ ADC_OFR1_OFFSET1_6

#define ADC_OFR1_OFFSET1_6 (0x040UL << ADC_OFR1_OFFSET1_Pos)

0x00000040

◆ ADC_OFR1_OFFSET1_7

#define ADC_OFR1_OFFSET1_7 (0x080UL << ADC_OFR1_OFFSET1_Pos)

0x00000080

◆ ADC_OFR1_OFFSET1_8

#define ADC_OFR1_OFFSET1_8 (0x100UL << ADC_OFR1_OFFSET1_Pos)

0x00000100

◆ ADC_OFR1_OFFSET1_9

#define ADC_OFR1_OFFSET1_9 (0x200UL << ADC_OFR1_OFFSET1_Pos)

0x00000200

◆ ADC_OFR1_OFFSET1_CH

#define ADC_OFR1_OFFSET1_CH ADC_OFR1_OFFSET1_CH_Msk

ADC offset number 1 channel selection

◆ ADC_OFR1_OFFSET1_CH_0

#define ADC_OFR1_OFFSET1_CH_0 (0x01UL << ADC_OFR1_OFFSET1_CH_Pos)

0x04000000

◆ ADC_OFR1_OFFSET1_CH_1

#define ADC_OFR1_OFFSET1_CH_1 (0x02UL << ADC_OFR1_OFFSET1_CH_Pos)

0x08000000

◆ ADC_OFR1_OFFSET1_CH_2

#define ADC_OFR1_OFFSET1_CH_2 (0x04UL << ADC_OFR1_OFFSET1_CH_Pos)

0x10000000

◆ ADC_OFR1_OFFSET1_CH_3

#define ADC_OFR1_OFFSET1_CH_3 (0x08UL << ADC_OFR1_OFFSET1_CH_Pos)

0x20000000

◆ ADC_OFR1_OFFSET1_CH_4

#define ADC_OFR1_OFFSET1_CH_4 (0x10UL << ADC_OFR1_OFFSET1_CH_Pos)

0x40000000

◆ ADC_OFR1_OFFSET1_CH_Msk

#define ADC_OFR1_OFFSET1_CH_Msk (0x1FUL << ADC_OFR1_OFFSET1_CH_Pos)

0x7C000000

◆ ADC_OFR1_OFFSET1_CH_Pos

#define ADC_OFR1_OFFSET1_CH_Pos (26U)

◆ ADC_OFR1_OFFSET1_EN

#define ADC_OFR1_OFFSET1_EN ADC_OFR1_OFFSET1_EN_Msk

ADC offset number 1 enable

◆ ADC_OFR1_OFFSET1_EN_Msk

#define ADC_OFR1_OFFSET1_EN_Msk (0x1UL << ADC_OFR1_OFFSET1_EN_Pos)

0x80000000

◆ ADC_OFR1_OFFSET1_EN_Pos

#define ADC_OFR1_OFFSET1_EN_Pos (31U)

◆ ADC_OFR1_OFFSET1_Msk

#define ADC_OFR1_OFFSET1_Msk (0xFFFUL << ADC_OFR1_OFFSET1_Pos)

0x00000FFF

◆ ADC_OFR1_OFFSET1_Pos

#define ADC_OFR1_OFFSET1_Pos (0U)

◆ ADC_OFR2_OFFSET2

#define ADC_OFR2_OFFSET2 ADC_OFR2_OFFSET2_Msk

ADC offset number 2 offset level

◆ ADC_OFR2_OFFSET2_0

#define ADC_OFR2_OFFSET2_0 (0x001UL << ADC_OFR2_OFFSET2_Pos)

0x00000001

◆ ADC_OFR2_OFFSET2_1

#define ADC_OFR2_OFFSET2_1 (0x002UL << ADC_OFR2_OFFSET2_Pos)

0x00000002

◆ ADC_OFR2_OFFSET2_10

#define ADC_OFR2_OFFSET2_10 (0x400UL << ADC_OFR2_OFFSET2_Pos)

0x00000400

◆ ADC_OFR2_OFFSET2_11

#define ADC_OFR2_OFFSET2_11 (0x800UL << ADC_OFR2_OFFSET2_Pos)

0x00000800

◆ ADC_OFR2_OFFSET2_2

#define ADC_OFR2_OFFSET2_2 (0x004UL << ADC_OFR2_OFFSET2_Pos)

0x00000004

◆ ADC_OFR2_OFFSET2_3

#define ADC_OFR2_OFFSET2_3 (0x008UL << ADC_OFR2_OFFSET2_Pos)

0x00000008

◆ ADC_OFR2_OFFSET2_4

#define ADC_OFR2_OFFSET2_4 (0x010UL << ADC_OFR2_OFFSET2_Pos)

0x00000010

◆ ADC_OFR2_OFFSET2_5

#define ADC_OFR2_OFFSET2_5 (0x020UL << ADC_OFR2_OFFSET2_Pos)

0x00000020

◆ ADC_OFR2_OFFSET2_6

#define ADC_OFR2_OFFSET2_6 (0x040UL << ADC_OFR2_OFFSET2_Pos)

0x00000040

◆ ADC_OFR2_OFFSET2_7

#define ADC_OFR2_OFFSET2_7 (0x080UL << ADC_OFR2_OFFSET2_Pos)

0x00000080

◆ ADC_OFR2_OFFSET2_8

#define ADC_OFR2_OFFSET2_8 (0x100UL << ADC_OFR2_OFFSET2_Pos)

0x00000100

◆ ADC_OFR2_OFFSET2_9

#define ADC_OFR2_OFFSET2_9 (0x200UL << ADC_OFR2_OFFSET2_Pos)

0x00000200

◆ ADC_OFR2_OFFSET2_CH

#define ADC_OFR2_OFFSET2_CH ADC_OFR2_OFFSET2_CH_Msk

ADC offset number 2 channel selection

◆ ADC_OFR2_OFFSET2_CH_0

#define ADC_OFR2_OFFSET2_CH_0 (0x01UL << ADC_OFR2_OFFSET2_CH_Pos)

0x04000000

◆ ADC_OFR2_OFFSET2_CH_1

#define ADC_OFR2_OFFSET2_CH_1 (0x02UL << ADC_OFR2_OFFSET2_CH_Pos)

0x08000000

◆ ADC_OFR2_OFFSET2_CH_2

#define ADC_OFR2_OFFSET2_CH_2 (0x04UL << ADC_OFR2_OFFSET2_CH_Pos)

0x10000000

◆ ADC_OFR2_OFFSET2_CH_3

#define ADC_OFR2_OFFSET2_CH_3 (0x08UL << ADC_OFR2_OFFSET2_CH_Pos)

0x20000000

◆ ADC_OFR2_OFFSET2_CH_4

#define ADC_OFR2_OFFSET2_CH_4 (0x10UL << ADC_OFR2_OFFSET2_CH_Pos)

0x40000000

◆ ADC_OFR2_OFFSET2_CH_Msk

#define ADC_OFR2_OFFSET2_CH_Msk (0x1FUL << ADC_OFR2_OFFSET2_CH_Pos)

0x7C000000

◆ ADC_OFR2_OFFSET2_CH_Pos

#define ADC_OFR2_OFFSET2_CH_Pos (26U)

◆ ADC_OFR2_OFFSET2_EN

#define ADC_OFR2_OFFSET2_EN ADC_OFR2_OFFSET2_EN_Msk

ADC offset number 2 enable

◆ ADC_OFR2_OFFSET2_EN_Msk

#define ADC_OFR2_OFFSET2_EN_Msk (0x1UL << ADC_OFR2_OFFSET2_EN_Pos)

0x80000000

◆ ADC_OFR2_OFFSET2_EN_Pos

#define ADC_OFR2_OFFSET2_EN_Pos (31U)

◆ ADC_OFR2_OFFSET2_Msk

#define ADC_OFR2_OFFSET2_Msk (0xFFFUL << ADC_OFR2_OFFSET2_Pos)

0x00000FFF

◆ ADC_OFR2_OFFSET2_Pos

#define ADC_OFR2_OFFSET2_Pos (0U)

◆ ADC_OFR3_OFFSET3

#define ADC_OFR3_OFFSET3 ADC_OFR3_OFFSET3_Msk

ADC offset number 3 offset level

◆ ADC_OFR3_OFFSET3_0

#define ADC_OFR3_OFFSET3_0 (0x001UL << ADC_OFR3_OFFSET3_Pos)

0x00000001

◆ ADC_OFR3_OFFSET3_1

#define ADC_OFR3_OFFSET3_1 (0x002UL << ADC_OFR3_OFFSET3_Pos)

0x00000002

◆ ADC_OFR3_OFFSET3_10

#define ADC_OFR3_OFFSET3_10 (0x400UL << ADC_OFR3_OFFSET3_Pos)

0x00000400

◆ ADC_OFR3_OFFSET3_11

#define ADC_OFR3_OFFSET3_11 (0x800UL << ADC_OFR3_OFFSET3_Pos)

0x00000800

◆ ADC_OFR3_OFFSET3_2

#define ADC_OFR3_OFFSET3_2 (0x004UL << ADC_OFR3_OFFSET3_Pos)

0x00000004

◆ ADC_OFR3_OFFSET3_3

#define ADC_OFR3_OFFSET3_3 (0x008UL << ADC_OFR3_OFFSET3_Pos)

0x00000008

◆ ADC_OFR3_OFFSET3_4

#define ADC_OFR3_OFFSET3_4 (0x010UL << ADC_OFR3_OFFSET3_Pos)

0x00000010

◆ ADC_OFR3_OFFSET3_5

#define ADC_OFR3_OFFSET3_5 (0x020UL << ADC_OFR3_OFFSET3_Pos)

0x00000020

◆ ADC_OFR3_OFFSET3_6

#define ADC_OFR3_OFFSET3_6 (0x040UL << ADC_OFR3_OFFSET3_Pos)

0x00000040

◆ ADC_OFR3_OFFSET3_7

#define ADC_OFR3_OFFSET3_7 (0x080UL << ADC_OFR3_OFFSET3_Pos)

0x00000080

◆ ADC_OFR3_OFFSET3_8

#define ADC_OFR3_OFFSET3_8 (0x100UL << ADC_OFR3_OFFSET3_Pos)

0x00000100

◆ ADC_OFR3_OFFSET3_9

#define ADC_OFR3_OFFSET3_9 (0x200UL << ADC_OFR3_OFFSET3_Pos)

0x00000200

◆ ADC_OFR3_OFFSET3_CH

#define ADC_OFR3_OFFSET3_CH ADC_OFR3_OFFSET3_CH_Msk

ADC offset number 3 channel selection

◆ ADC_OFR3_OFFSET3_CH_0

#define ADC_OFR3_OFFSET3_CH_0 (0x01UL << ADC_OFR3_OFFSET3_CH_Pos)

0x04000000

◆ ADC_OFR3_OFFSET3_CH_1

#define ADC_OFR3_OFFSET3_CH_1 (0x02UL << ADC_OFR3_OFFSET3_CH_Pos)

0x08000000

◆ ADC_OFR3_OFFSET3_CH_2

#define ADC_OFR3_OFFSET3_CH_2 (0x04UL << ADC_OFR3_OFFSET3_CH_Pos)

0x10000000

◆ ADC_OFR3_OFFSET3_CH_3

#define ADC_OFR3_OFFSET3_CH_3 (0x08UL << ADC_OFR3_OFFSET3_CH_Pos)

0x20000000

◆ ADC_OFR3_OFFSET3_CH_4

#define ADC_OFR3_OFFSET3_CH_4 (0x10UL << ADC_OFR3_OFFSET3_CH_Pos)

0x40000000

◆ ADC_OFR3_OFFSET3_CH_Msk

#define ADC_OFR3_OFFSET3_CH_Msk (0x1FUL << ADC_OFR3_OFFSET3_CH_Pos)

0x7C000000

◆ ADC_OFR3_OFFSET3_CH_Pos

#define ADC_OFR3_OFFSET3_CH_Pos (26U)

◆ ADC_OFR3_OFFSET3_EN

#define ADC_OFR3_OFFSET3_EN ADC_OFR3_OFFSET3_EN_Msk

ADC offset number 3 enable

◆ ADC_OFR3_OFFSET3_EN_Msk

#define ADC_OFR3_OFFSET3_EN_Msk (0x1UL << ADC_OFR3_OFFSET3_EN_Pos)

0x80000000

◆ ADC_OFR3_OFFSET3_EN_Pos

#define ADC_OFR3_OFFSET3_EN_Pos (31U)

◆ ADC_OFR3_OFFSET3_Msk

#define ADC_OFR3_OFFSET3_Msk (0xFFFUL << ADC_OFR3_OFFSET3_Pos)

0x00000FFF

◆ ADC_OFR3_OFFSET3_Pos

#define ADC_OFR3_OFFSET3_Pos (0U)

◆ ADC_OFR4_OFFSET4

#define ADC_OFR4_OFFSET4 ADC_OFR4_OFFSET4_Msk

ADC offset number 4 offset level

◆ ADC_OFR4_OFFSET4_0

#define ADC_OFR4_OFFSET4_0 (0x001UL << ADC_OFR4_OFFSET4_Pos)

0x00000001

◆ ADC_OFR4_OFFSET4_1

#define ADC_OFR4_OFFSET4_1 (0x002UL << ADC_OFR4_OFFSET4_Pos)

0x00000002

◆ ADC_OFR4_OFFSET4_10

#define ADC_OFR4_OFFSET4_10 (0x400UL << ADC_OFR4_OFFSET4_Pos)

0x00000400

◆ ADC_OFR4_OFFSET4_11

#define ADC_OFR4_OFFSET4_11 (0x800UL << ADC_OFR4_OFFSET4_Pos)

0x00000800

◆ ADC_OFR4_OFFSET4_2

#define ADC_OFR4_OFFSET4_2 (0x004UL << ADC_OFR4_OFFSET4_Pos)

0x00000004

◆ ADC_OFR4_OFFSET4_3

#define ADC_OFR4_OFFSET4_3 (0x008UL << ADC_OFR4_OFFSET4_Pos)

0x00000008

◆ ADC_OFR4_OFFSET4_4

#define ADC_OFR4_OFFSET4_4 (0x010UL << ADC_OFR4_OFFSET4_Pos)

0x00000010

◆ ADC_OFR4_OFFSET4_5

#define ADC_OFR4_OFFSET4_5 (0x020UL << ADC_OFR4_OFFSET4_Pos)

0x00000020

◆ ADC_OFR4_OFFSET4_6

#define ADC_OFR4_OFFSET4_6 (0x040UL << ADC_OFR4_OFFSET4_Pos)

0x00000040

◆ ADC_OFR4_OFFSET4_7

#define ADC_OFR4_OFFSET4_7 (0x080UL << ADC_OFR4_OFFSET4_Pos)

0x00000080

◆ ADC_OFR4_OFFSET4_8

#define ADC_OFR4_OFFSET4_8 (0x100UL << ADC_OFR4_OFFSET4_Pos)

0x00000100

◆ ADC_OFR4_OFFSET4_9

#define ADC_OFR4_OFFSET4_9 (0x200UL << ADC_OFR4_OFFSET4_Pos)

0x00000200

◆ ADC_OFR4_OFFSET4_CH

#define ADC_OFR4_OFFSET4_CH ADC_OFR4_OFFSET4_CH_Msk

ADC offset number 4 channel selection

◆ ADC_OFR4_OFFSET4_CH_0

#define ADC_OFR4_OFFSET4_CH_0 (0x01UL << ADC_OFR4_OFFSET4_CH_Pos)

0x04000000

◆ ADC_OFR4_OFFSET4_CH_1

#define ADC_OFR4_OFFSET4_CH_1 (0x02UL << ADC_OFR4_OFFSET4_CH_Pos)

0x08000000

◆ ADC_OFR4_OFFSET4_CH_2

#define ADC_OFR4_OFFSET4_CH_2 (0x04UL << ADC_OFR4_OFFSET4_CH_Pos)

0x10000000

◆ ADC_OFR4_OFFSET4_CH_3

#define ADC_OFR4_OFFSET4_CH_3 (0x08UL << ADC_OFR4_OFFSET4_CH_Pos)

0x20000000

◆ ADC_OFR4_OFFSET4_CH_4

#define ADC_OFR4_OFFSET4_CH_4 (0x10UL << ADC_OFR4_OFFSET4_CH_Pos)

0x40000000

◆ ADC_OFR4_OFFSET4_CH_Msk

#define ADC_OFR4_OFFSET4_CH_Msk (0x1FUL << ADC_OFR4_OFFSET4_CH_Pos)

0x7C000000

◆ ADC_OFR4_OFFSET4_CH_Pos

#define ADC_OFR4_OFFSET4_CH_Pos (26U)

◆ ADC_OFR4_OFFSET4_EN

#define ADC_OFR4_OFFSET4_EN ADC_OFR4_OFFSET4_EN_Msk

ADC offset number 4 enable

◆ ADC_OFR4_OFFSET4_EN_Msk

#define ADC_OFR4_OFFSET4_EN_Msk (0x1UL << ADC_OFR4_OFFSET4_EN_Pos)

0x80000000

◆ ADC_OFR4_OFFSET4_EN_Pos

#define ADC_OFR4_OFFSET4_EN_Pos (31U)

◆ ADC_OFR4_OFFSET4_Msk

#define ADC_OFR4_OFFSET4_Msk (0xFFFUL << ADC_OFR4_OFFSET4_Pos)

0x00000FFF

◆ ADC_OFR4_OFFSET4_Pos

#define ADC_OFR4_OFFSET4_Pos (0U)

◆ ADC_SMPR1_SMP0

#define ADC_SMPR1_SMP0 ADC_SMPR1_SMP0_Msk

ADC channel 0 sampling time selection

◆ ADC_SMPR1_SMP0_0

#define ADC_SMPR1_SMP0_0 (0x1UL << ADC_SMPR1_SMP0_Pos)

0x00000001

◆ ADC_SMPR1_SMP0_1

#define ADC_SMPR1_SMP0_1 (0x2UL << ADC_SMPR1_SMP0_Pos)

0x00000002

◆ ADC_SMPR1_SMP0_2

#define ADC_SMPR1_SMP0_2 (0x4UL << ADC_SMPR1_SMP0_Pos)

0x00000004

◆ ADC_SMPR1_SMP0_Msk

#define ADC_SMPR1_SMP0_Msk (0x7UL << ADC_SMPR1_SMP0_Pos)

0x00000007

◆ ADC_SMPR1_SMP0_Pos

#define ADC_SMPR1_SMP0_Pos (0U)

◆ ADC_SMPR1_SMP1

#define ADC_SMPR1_SMP1 ADC_SMPR1_SMP1_Msk

ADC channel 1 sampling time selection

◆ ADC_SMPR1_SMP1_0

#define ADC_SMPR1_SMP1_0 (0x1UL << ADC_SMPR1_SMP1_Pos)

0x00000008

◆ ADC_SMPR1_SMP1_1

#define ADC_SMPR1_SMP1_1 (0x2UL << ADC_SMPR1_SMP1_Pos)

0x00000010

◆ ADC_SMPR1_SMP1_2

#define ADC_SMPR1_SMP1_2 (0x4UL << ADC_SMPR1_SMP1_Pos)

0x00000020

◆ ADC_SMPR1_SMP1_Msk

#define ADC_SMPR1_SMP1_Msk (0x7UL << ADC_SMPR1_SMP1_Pos)

0x00000038

◆ ADC_SMPR1_SMP1_Pos

#define ADC_SMPR1_SMP1_Pos (3U)

◆ ADC_SMPR1_SMP2

#define ADC_SMPR1_SMP2 ADC_SMPR1_SMP2_Msk

ADC channel 2 sampling time selection

◆ ADC_SMPR1_SMP2_0

#define ADC_SMPR1_SMP2_0 (0x1UL << ADC_SMPR1_SMP2_Pos)

0x00000040

◆ ADC_SMPR1_SMP2_1

#define ADC_SMPR1_SMP2_1 (0x2UL << ADC_SMPR1_SMP2_Pos)

0x00000080

◆ ADC_SMPR1_SMP2_2

#define ADC_SMPR1_SMP2_2 (0x4UL << ADC_SMPR1_SMP2_Pos)

0x00000100

◆ ADC_SMPR1_SMP2_Msk

#define ADC_SMPR1_SMP2_Msk (0x7UL << ADC_SMPR1_SMP2_Pos)

0x000001C0

◆ ADC_SMPR1_SMP2_Pos

#define ADC_SMPR1_SMP2_Pos (6U)

◆ ADC_SMPR1_SMP3

#define ADC_SMPR1_SMP3 ADC_SMPR1_SMP3_Msk

ADC channel 3 sampling time selection

◆ ADC_SMPR1_SMP3_0

#define ADC_SMPR1_SMP3_0 (0x1UL << ADC_SMPR1_SMP3_Pos)

0x00000200

◆ ADC_SMPR1_SMP3_1

#define ADC_SMPR1_SMP3_1 (0x2UL << ADC_SMPR1_SMP3_Pos)

0x00000400

◆ ADC_SMPR1_SMP3_2

#define ADC_SMPR1_SMP3_2 (0x4UL << ADC_SMPR1_SMP3_Pos)

0x00000800

◆ ADC_SMPR1_SMP3_Msk

#define ADC_SMPR1_SMP3_Msk (0x7UL << ADC_SMPR1_SMP3_Pos)

0x00000E00

◆ ADC_SMPR1_SMP3_Pos

#define ADC_SMPR1_SMP3_Pos (9U)

◆ ADC_SMPR1_SMP4

#define ADC_SMPR1_SMP4 ADC_SMPR1_SMP4_Msk

ADC channel 4 sampling time selection

◆ ADC_SMPR1_SMP4_0

#define ADC_SMPR1_SMP4_0 (0x1UL << ADC_SMPR1_SMP4_Pos)

0x00001000

◆ ADC_SMPR1_SMP4_1

#define ADC_SMPR1_SMP4_1 (0x2UL << ADC_SMPR1_SMP4_Pos)

0x00002000

◆ ADC_SMPR1_SMP4_2

#define ADC_SMPR1_SMP4_2 (0x4UL << ADC_SMPR1_SMP4_Pos)

0x00004000

◆ ADC_SMPR1_SMP4_Msk

#define ADC_SMPR1_SMP4_Msk (0x7UL << ADC_SMPR1_SMP4_Pos)

0x00007000

◆ ADC_SMPR1_SMP4_Pos

#define ADC_SMPR1_SMP4_Pos (12U)

◆ ADC_SMPR1_SMP5

#define ADC_SMPR1_SMP5 ADC_SMPR1_SMP5_Msk

ADC channel 5 sampling time selection

◆ ADC_SMPR1_SMP5_0

#define ADC_SMPR1_SMP5_0 (0x1UL << ADC_SMPR1_SMP5_Pos)

0x00008000

◆ ADC_SMPR1_SMP5_1

#define ADC_SMPR1_SMP5_1 (0x2UL << ADC_SMPR1_SMP5_Pos)

0x00010000

◆ ADC_SMPR1_SMP5_2

#define ADC_SMPR1_SMP5_2 (0x4UL << ADC_SMPR1_SMP5_Pos)

0x00020000

◆ ADC_SMPR1_SMP5_Msk

#define ADC_SMPR1_SMP5_Msk (0x7UL << ADC_SMPR1_SMP5_Pos)

0x00038000

◆ ADC_SMPR1_SMP5_Pos

#define ADC_SMPR1_SMP5_Pos (15U)

◆ ADC_SMPR1_SMP6

#define ADC_SMPR1_SMP6 ADC_SMPR1_SMP6_Msk

ADC channel 6 sampling time selection

◆ ADC_SMPR1_SMP6_0

#define ADC_SMPR1_SMP6_0 (0x1UL << ADC_SMPR1_SMP6_Pos)

0x00040000

◆ ADC_SMPR1_SMP6_1

#define ADC_SMPR1_SMP6_1 (0x2UL << ADC_SMPR1_SMP6_Pos)

0x00080000

◆ ADC_SMPR1_SMP6_2

#define ADC_SMPR1_SMP6_2 (0x4UL << ADC_SMPR1_SMP6_Pos)

0x00100000

◆ ADC_SMPR1_SMP6_Msk

#define ADC_SMPR1_SMP6_Msk (0x7UL << ADC_SMPR1_SMP6_Pos)

0x001C0000

◆ ADC_SMPR1_SMP6_Pos

#define ADC_SMPR1_SMP6_Pos (18U)

◆ ADC_SMPR1_SMP7

#define ADC_SMPR1_SMP7 ADC_SMPR1_SMP7_Msk

ADC channel 7 sampling time selection

◆ ADC_SMPR1_SMP7_0

#define ADC_SMPR1_SMP7_0 (0x1UL << ADC_SMPR1_SMP7_Pos)

0x00200000

◆ ADC_SMPR1_SMP7_1

#define ADC_SMPR1_SMP7_1 (0x2UL << ADC_SMPR1_SMP7_Pos)

0x00400000

◆ ADC_SMPR1_SMP7_2

#define ADC_SMPR1_SMP7_2 (0x4UL << ADC_SMPR1_SMP7_Pos)

0x00800000

◆ ADC_SMPR1_SMP7_Msk

#define ADC_SMPR1_SMP7_Msk (0x7UL << ADC_SMPR1_SMP7_Pos)

0x00E00000

◆ ADC_SMPR1_SMP7_Pos

#define ADC_SMPR1_SMP7_Pos (21U)

◆ ADC_SMPR1_SMP8

#define ADC_SMPR1_SMP8 ADC_SMPR1_SMP8_Msk

ADC channel 8 sampling time selection

◆ ADC_SMPR1_SMP8_0

#define ADC_SMPR1_SMP8_0 (0x1UL << ADC_SMPR1_SMP8_Pos)

0x01000000

◆ ADC_SMPR1_SMP8_1

#define ADC_SMPR1_SMP8_1 (0x2UL << ADC_SMPR1_SMP8_Pos)

0x02000000

◆ ADC_SMPR1_SMP8_2

#define ADC_SMPR1_SMP8_2 (0x4UL << ADC_SMPR1_SMP8_Pos)

0x04000000

◆ ADC_SMPR1_SMP8_Msk

#define ADC_SMPR1_SMP8_Msk (0x7UL << ADC_SMPR1_SMP8_Pos)

0x07000000

◆ ADC_SMPR1_SMP8_Pos

#define ADC_SMPR1_SMP8_Pos (24U)

◆ ADC_SMPR1_SMP9

#define ADC_SMPR1_SMP9 ADC_SMPR1_SMP9_Msk

ADC channel 9 sampling time selection

◆ ADC_SMPR1_SMP9_0

#define ADC_SMPR1_SMP9_0 (0x1UL << ADC_SMPR1_SMP9_Pos)

0x08000000

◆ ADC_SMPR1_SMP9_1

#define ADC_SMPR1_SMP9_1 (0x2UL << ADC_SMPR1_SMP9_Pos)

0x10000000

◆ ADC_SMPR1_SMP9_2

#define ADC_SMPR1_SMP9_2 (0x4UL << ADC_SMPR1_SMP9_Pos)

0x20000000

◆ ADC_SMPR1_SMP9_Msk

#define ADC_SMPR1_SMP9_Msk (0x7UL << ADC_SMPR1_SMP9_Pos)

0x38000000

◆ ADC_SMPR1_SMP9_Pos

#define ADC_SMPR1_SMP9_Pos (27U)

◆ ADC_SMPR2_SMP10

#define ADC_SMPR2_SMP10 ADC_SMPR2_SMP10_Msk

ADC channel 10 sampling time selection

◆ ADC_SMPR2_SMP10_0

#define ADC_SMPR2_SMP10_0 (0x1UL << ADC_SMPR2_SMP10_Pos)

0x00000001

◆ ADC_SMPR2_SMP10_1

#define ADC_SMPR2_SMP10_1 (0x2UL << ADC_SMPR2_SMP10_Pos)

0x00000002

◆ ADC_SMPR2_SMP10_2

#define ADC_SMPR2_SMP10_2 (0x4UL << ADC_SMPR2_SMP10_Pos)

0x00000004

◆ ADC_SMPR2_SMP10_Msk

#define ADC_SMPR2_SMP10_Msk (0x7UL << ADC_SMPR2_SMP10_Pos)

0x00000007

◆ ADC_SMPR2_SMP10_Pos

#define ADC_SMPR2_SMP10_Pos (0U)

◆ ADC_SMPR2_SMP11

#define ADC_SMPR2_SMP11 ADC_SMPR2_SMP11_Msk

ADC channel 11 sampling time selection

◆ ADC_SMPR2_SMP11_0

#define ADC_SMPR2_SMP11_0 (0x1UL << ADC_SMPR2_SMP11_Pos)

0x00000008

◆ ADC_SMPR2_SMP11_1

#define ADC_SMPR2_SMP11_1 (0x2UL << ADC_SMPR2_SMP11_Pos)

0x00000010

◆ ADC_SMPR2_SMP11_2

#define ADC_SMPR2_SMP11_2 (0x4UL << ADC_SMPR2_SMP11_Pos)

0x00000020

◆ ADC_SMPR2_SMP11_Msk

#define ADC_SMPR2_SMP11_Msk (0x7UL << ADC_SMPR2_SMP11_Pos)

0x00000038

◆ ADC_SMPR2_SMP11_Pos

#define ADC_SMPR2_SMP11_Pos (3U)

◆ ADC_SMPR2_SMP12

#define ADC_SMPR2_SMP12 ADC_SMPR2_SMP12_Msk

ADC channel 12 sampling time selection

◆ ADC_SMPR2_SMP12_0

#define ADC_SMPR2_SMP12_0 (0x1UL << ADC_SMPR2_SMP12_Pos)

0x00000040

◆ ADC_SMPR2_SMP12_1

#define ADC_SMPR2_SMP12_1 (0x2UL << ADC_SMPR2_SMP12_Pos)

0x00000080

◆ ADC_SMPR2_SMP12_2

#define ADC_SMPR2_SMP12_2 (0x4UL << ADC_SMPR2_SMP12_Pos)

0x00000100

◆ ADC_SMPR2_SMP12_Msk

#define ADC_SMPR2_SMP12_Msk (0x7UL << ADC_SMPR2_SMP12_Pos)

0x000001C0

◆ ADC_SMPR2_SMP12_Pos

#define ADC_SMPR2_SMP12_Pos (6U)

◆ ADC_SMPR2_SMP13

#define ADC_SMPR2_SMP13 ADC_SMPR2_SMP13_Msk

ADC channel 13 sampling time selection

◆ ADC_SMPR2_SMP13_0

#define ADC_SMPR2_SMP13_0 (0x1UL << ADC_SMPR2_SMP13_Pos)

0x00000200

◆ ADC_SMPR2_SMP13_1

#define ADC_SMPR2_SMP13_1 (0x2UL << ADC_SMPR2_SMP13_Pos)

0x00000400

◆ ADC_SMPR2_SMP13_2

#define ADC_SMPR2_SMP13_2 (0x4UL << ADC_SMPR2_SMP13_Pos)

0x00000800

◆ ADC_SMPR2_SMP13_Msk

#define ADC_SMPR2_SMP13_Msk (0x7UL << ADC_SMPR2_SMP13_Pos)

0x00000E00

◆ ADC_SMPR2_SMP13_Pos

#define ADC_SMPR2_SMP13_Pos (9U)

◆ ADC_SMPR2_SMP14

#define ADC_SMPR2_SMP14 ADC_SMPR2_SMP14_Msk

ADC channel 14 sampling time selection

◆ ADC_SMPR2_SMP14_0

#define ADC_SMPR2_SMP14_0 (0x1UL << ADC_SMPR2_SMP14_Pos)

0x00001000

◆ ADC_SMPR2_SMP14_1

#define ADC_SMPR2_SMP14_1 (0x2UL << ADC_SMPR2_SMP14_Pos)

0x00002000

◆ ADC_SMPR2_SMP14_2

#define ADC_SMPR2_SMP14_2 (0x4UL << ADC_SMPR2_SMP14_Pos)

0x00004000

◆ ADC_SMPR2_SMP14_Msk

#define ADC_SMPR2_SMP14_Msk (0x7UL << ADC_SMPR2_SMP14_Pos)

0x00007000

◆ ADC_SMPR2_SMP14_Pos

#define ADC_SMPR2_SMP14_Pos (12U)

◆ ADC_SMPR2_SMP15

#define ADC_SMPR2_SMP15 ADC_SMPR2_SMP15_Msk

ADC channel 15 sampling time selection

◆ ADC_SMPR2_SMP15_0

#define ADC_SMPR2_SMP15_0 (0x1UL << ADC_SMPR2_SMP15_Pos)

0x00008000

◆ ADC_SMPR2_SMP15_1

#define ADC_SMPR2_SMP15_1 (0x2UL << ADC_SMPR2_SMP15_Pos)

0x00010000

◆ ADC_SMPR2_SMP15_2

#define ADC_SMPR2_SMP15_2 (0x4UL << ADC_SMPR2_SMP15_Pos)

0x00020000

◆ ADC_SMPR2_SMP15_Msk

#define ADC_SMPR2_SMP15_Msk (0x7UL << ADC_SMPR2_SMP15_Pos)

0x00038000

◆ ADC_SMPR2_SMP15_Pos

#define ADC_SMPR2_SMP15_Pos (15U)

◆ ADC_SMPR2_SMP16

#define ADC_SMPR2_SMP16 ADC_SMPR2_SMP16_Msk

ADC channel 16 sampling time selection

◆ ADC_SMPR2_SMP16_0

#define ADC_SMPR2_SMP16_0 (0x1UL << ADC_SMPR2_SMP16_Pos)

0x00040000

◆ ADC_SMPR2_SMP16_1

#define ADC_SMPR2_SMP16_1 (0x2UL << ADC_SMPR2_SMP16_Pos)

0x00080000

◆ ADC_SMPR2_SMP16_2

#define ADC_SMPR2_SMP16_2 (0x4UL << ADC_SMPR2_SMP16_Pos)

0x00100000

◆ ADC_SMPR2_SMP16_Msk

#define ADC_SMPR2_SMP16_Msk (0x7UL << ADC_SMPR2_SMP16_Pos)

0x001C0000

◆ ADC_SMPR2_SMP16_Pos

#define ADC_SMPR2_SMP16_Pos (18U)

◆ ADC_SMPR2_SMP17

#define ADC_SMPR2_SMP17 ADC_SMPR2_SMP17_Msk

ADC channel 17 sampling time selection

◆ ADC_SMPR2_SMP17_0

#define ADC_SMPR2_SMP17_0 (0x1UL << ADC_SMPR2_SMP17_Pos)

0x00200000

◆ ADC_SMPR2_SMP17_1

#define ADC_SMPR2_SMP17_1 (0x2UL << ADC_SMPR2_SMP17_Pos)

0x00400000

◆ ADC_SMPR2_SMP17_2

#define ADC_SMPR2_SMP17_2 (0x4UL << ADC_SMPR2_SMP17_Pos)

0x00800000

◆ ADC_SMPR2_SMP17_Msk

#define ADC_SMPR2_SMP17_Msk (0x7UL << ADC_SMPR2_SMP17_Pos)

0x00E00000

◆ ADC_SMPR2_SMP17_Pos

#define ADC_SMPR2_SMP17_Pos (21U)

◆ ADC_SMPR2_SMP18

#define ADC_SMPR2_SMP18 ADC_SMPR2_SMP18_Msk

ADC channel 18 sampling time selection

◆ ADC_SMPR2_SMP18_0

#define ADC_SMPR2_SMP18_0 (0x1UL << ADC_SMPR2_SMP18_Pos)

0x01000000

◆ ADC_SMPR2_SMP18_1

#define ADC_SMPR2_SMP18_1 (0x2UL << ADC_SMPR2_SMP18_Pos)

0x02000000

◆ ADC_SMPR2_SMP18_2

#define ADC_SMPR2_SMP18_2 (0x4UL << ADC_SMPR2_SMP18_Pos)

0x04000000

◆ ADC_SMPR2_SMP18_Msk

#define ADC_SMPR2_SMP18_Msk (0x7UL << ADC_SMPR2_SMP18_Pos)

0x07000000

◆ ADC_SMPR2_SMP18_Pos

#define ADC_SMPR2_SMP18_Pos (24U)

◆ ADC_SQR1_L

#define ADC_SQR1_L ADC_SQR1_L_Msk

ADC group regular sequencer scan length

◆ ADC_SQR1_L_0

#define ADC_SQR1_L_0 (0x1UL << ADC_SQR1_L_Pos)

0x00000001

◆ ADC_SQR1_L_1

#define ADC_SQR1_L_1 (0x2UL << ADC_SQR1_L_Pos)

0x00000002

◆ ADC_SQR1_L_2

#define ADC_SQR1_L_2 (0x4UL << ADC_SQR1_L_Pos)

0x00000004

◆ ADC_SQR1_L_3

#define ADC_SQR1_L_3 (0x8UL << ADC_SQR1_L_Pos)

0x00000008

◆ ADC_SQR1_L_Msk

#define ADC_SQR1_L_Msk (0xFUL << ADC_SQR1_L_Pos)

0x0000000F

◆ ADC_SQR1_L_Pos

#define ADC_SQR1_L_Pos (0U)

◆ ADC_SQR1_SQ1

#define ADC_SQR1_SQ1 ADC_SQR1_SQ1_Msk

ADC group regular sequencer rank 1

◆ ADC_SQR1_SQ1_0

#define ADC_SQR1_SQ1_0 (0x01UL << ADC_SQR1_SQ1_Pos)

0x00000040

◆ ADC_SQR1_SQ1_1

#define ADC_SQR1_SQ1_1 (0x02UL << ADC_SQR1_SQ1_Pos)

0x00000080

◆ ADC_SQR1_SQ1_2

#define ADC_SQR1_SQ1_2 (0x04UL << ADC_SQR1_SQ1_Pos)

0x00000100

◆ ADC_SQR1_SQ1_3

#define ADC_SQR1_SQ1_3 (0x08UL << ADC_SQR1_SQ1_Pos)

0x00000200

◆ ADC_SQR1_SQ1_4

#define ADC_SQR1_SQ1_4 (0x10UL << ADC_SQR1_SQ1_Pos)

0x00000400

◆ ADC_SQR1_SQ1_Msk

#define ADC_SQR1_SQ1_Msk (0x1FUL << ADC_SQR1_SQ1_Pos)

0x000007C0

◆ ADC_SQR1_SQ1_Pos

#define ADC_SQR1_SQ1_Pos (6U)

◆ ADC_SQR1_SQ2

#define ADC_SQR1_SQ2 ADC_SQR1_SQ2_Msk

ADC group regular sequencer rank 2

◆ ADC_SQR1_SQ2_0

#define ADC_SQR1_SQ2_0 (0x01UL << ADC_SQR1_SQ2_Pos)

0x00001000

◆ ADC_SQR1_SQ2_1

#define ADC_SQR1_SQ2_1 (0x02UL << ADC_SQR1_SQ2_Pos)

0x00002000

◆ ADC_SQR1_SQ2_2

#define ADC_SQR1_SQ2_2 (0x04UL << ADC_SQR1_SQ2_Pos)

0x00004000

◆ ADC_SQR1_SQ2_3

#define ADC_SQR1_SQ2_3 (0x08UL << ADC_SQR1_SQ2_Pos)

0x00008000

◆ ADC_SQR1_SQ2_4

#define ADC_SQR1_SQ2_4 (0x10UL << ADC_SQR1_SQ2_Pos)

0x00010000

◆ ADC_SQR1_SQ2_Msk

#define ADC_SQR1_SQ2_Msk (0x1FUL << ADC_SQR1_SQ2_Pos)

0x0001F000

◆ ADC_SQR1_SQ2_Pos

#define ADC_SQR1_SQ2_Pos (12U)

◆ ADC_SQR1_SQ3

#define ADC_SQR1_SQ3 ADC_SQR1_SQ3_Msk

ADC group regular sequencer rank 3

◆ ADC_SQR1_SQ3_0

#define ADC_SQR1_SQ3_0 (0x01UL << ADC_SQR1_SQ3_Pos)

0x00040000

◆ ADC_SQR1_SQ3_1

#define ADC_SQR1_SQ3_1 (0x02UL << ADC_SQR1_SQ3_Pos)

0x00080000

◆ ADC_SQR1_SQ3_2

#define ADC_SQR1_SQ3_2 (0x04UL << ADC_SQR1_SQ3_Pos)

0x00100000

◆ ADC_SQR1_SQ3_3

#define ADC_SQR1_SQ3_3 (0x08UL << ADC_SQR1_SQ3_Pos)

0x00200000

◆ ADC_SQR1_SQ3_4

#define ADC_SQR1_SQ3_4 (0x10UL << ADC_SQR1_SQ3_Pos)

0x00400000

◆ ADC_SQR1_SQ3_Msk

#define ADC_SQR1_SQ3_Msk (0x1FUL << ADC_SQR1_SQ3_Pos)

0x007C0000

◆ ADC_SQR1_SQ3_Pos

#define ADC_SQR1_SQ3_Pos (18U)

◆ ADC_SQR1_SQ4

#define ADC_SQR1_SQ4 ADC_SQR1_SQ4_Msk

ADC group regular sequencer rank 4

◆ ADC_SQR1_SQ4_0

#define ADC_SQR1_SQ4_0 (0x01UL << ADC_SQR1_SQ4_Pos)

0x01000000

◆ ADC_SQR1_SQ4_1

#define ADC_SQR1_SQ4_1 (0x02UL << ADC_SQR1_SQ4_Pos)

0x02000000

◆ ADC_SQR1_SQ4_2

#define ADC_SQR1_SQ4_2 (0x04UL << ADC_SQR1_SQ4_Pos)

0x04000000

◆ ADC_SQR1_SQ4_3

#define ADC_SQR1_SQ4_3 (0x08UL << ADC_SQR1_SQ4_Pos)

0x08000000

◆ ADC_SQR1_SQ4_4

#define ADC_SQR1_SQ4_4 (0x10UL << ADC_SQR1_SQ4_Pos)

0x10000000

◆ ADC_SQR1_SQ4_Msk

#define ADC_SQR1_SQ4_Msk (0x1FUL << ADC_SQR1_SQ4_Pos)

0x1F000000

◆ ADC_SQR1_SQ4_Pos

#define ADC_SQR1_SQ4_Pos (24U)

◆ ADC_SQR2_SQ5

#define ADC_SQR2_SQ5 ADC_SQR2_SQ5_Msk

ADC group regular sequencer rank 5

◆ ADC_SQR2_SQ5_0

#define ADC_SQR2_SQ5_0 (0x01UL << ADC_SQR2_SQ5_Pos)

0x00000001

◆ ADC_SQR2_SQ5_1

#define ADC_SQR2_SQ5_1 (0x02UL << ADC_SQR2_SQ5_Pos)

0x00000002

◆ ADC_SQR2_SQ5_2

#define ADC_SQR2_SQ5_2 (0x04UL << ADC_SQR2_SQ5_Pos)

0x00000004

◆ ADC_SQR2_SQ5_3

#define ADC_SQR2_SQ5_3 (0x08UL << ADC_SQR2_SQ5_Pos)

0x00000008

◆ ADC_SQR2_SQ5_4

#define ADC_SQR2_SQ5_4 (0x10UL << ADC_SQR2_SQ5_Pos)

0x00000010

◆ ADC_SQR2_SQ5_Msk

#define ADC_SQR2_SQ5_Msk (0x1FUL << ADC_SQR2_SQ5_Pos)

0x0000001F

◆ ADC_SQR2_SQ5_Pos

#define ADC_SQR2_SQ5_Pos (0U)

◆ ADC_SQR2_SQ6

#define ADC_SQR2_SQ6 ADC_SQR2_SQ6_Msk

ADC group regular sequencer rank 6

◆ ADC_SQR2_SQ6_0

#define ADC_SQR2_SQ6_0 (0x01UL << ADC_SQR2_SQ6_Pos)

0x00000040

◆ ADC_SQR2_SQ6_1

#define ADC_SQR2_SQ6_1 (0x02UL << ADC_SQR2_SQ6_Pos)

0x00000080

◆ ADC_SQR2_SQ6_2

#define ADC_SQR2_SQ6_2 (0x04UL << ADC_SQR2_SQ6_Pos)

0x00000100

◆ ADC_SQR2_SQ6_3

#define ADC_SQR2_SQ6_3 (0x08UL << ADC_SQR2_SQ6_Pos)

0x00000200

◆ ADC_SQR2_SQ6_4

#define ADC_SQR2_SQ6_4 (0x10UL << ADC_SQR2_SQ6_Pos)

0x00000400

◆ ADC_SQR2_SQ6_Msk

#define ADC_SQR2_SQ6_Msk (0x1FUL << ADC_SQR2_SQ6_Pos)

0x000007C0

◆ ADC_SQR2_SQ6_Pos

#define ADC_SQR2_SQ6_Pos (6U)

◆ ADC_SQR2_SQ7

#define ADC_SQR2_SQ7 ADC_SQR2_SQ7_Msk

ADC group regular sequencer rank 7

◆ ADC_SQR2_SQ7_0

#define ADC_SQR2_SQ7_0 (0x01UL << ADC_SQR2_SQ7_Pos)

0x00001000

◆ ADC_SQR2_SQ7_1

#define ADC_SQR2_SQ7_1 (0x02UL << ADC_SQR2_SQ7_Pos)

0x00002000

◆ ADC_SQR2_SQ7_2

#define ADC_SQR2_SQ7_2 (0x04UL << ADC_SQR2_SQ7_Pos)

0x00004000

◆ ADC_SQR2_SQ7_3

#define ADC_SQR2_SQ7_3 (0x08UL << ADC_SQR2_SQ7_Pos)

0x00008000

◆ ADC_SQR2_SQ7_4

#define ADC_SQR2_SQ7_4 (0x10UL << ADC_SQR2_SQ7_Pos)

0x00010000

◆ ADC_SQR2_SQ7_Msk

#define ADC_SQR2_SQ7_Msk (0x1FUL << ADC_SQR2_SQ7_Pos)

0x0001F000

◆ ADC_SQR2_SQ7_Pos

#define ADC_SQR2_SQ7_Pos (12U)

◆ ADC_SQR2_SQ8

#define ADC_SQR2_SQ8 ADC_SQR2_SQ8_Msk

ADC group regular sequencer rank 8

◆ ADC_SQR2_SQ8_0

#define ADC_SQR2_SQ8_0 (0x01UL << ADC_SQR2_SQ8_Pos)

0x00040000

◆ ADC_SQR2_SQ8_1

#define ADC_SQR2_SQ8_1 (0x02UL << ADC_SQR2_SQ8_Pos)

0x00080000

◆ ADC_SQR2_SQ8_2

#define ADC_SQR2_SQ8_2 (0x04UL << ADC_SQR2_SQ8_Pos)

0x00100000

◆ ADC_SQR2_SQ8_3

#define ADC_SQR2_SQ8_3 (0x08UL << ADC_SQR2_SQ8_Pos)

0x00200000

◆ ADC_SQR2_SQ8_4

#define ADC_SQR2_SQ8_4 (0x10UL << ADC_SQR2_SQ8_Pos)

0x00400000

◆ ADC_SQR2_SQ8_Msk

#define ADC_SQR2_SQ8_Msk (0x1FUL << ADC_SQR2_SQ8_Pos)

0x007C0000

◆ ADC_SQR2_SQ8_Pos

#define ADC_SQR2_SQ8_Pos (18U)

◆ ADC_SQR2_SQ9

#define ADC_SQR2_SQ9 ADC_SQR2_SQ9_Msk

ADC group regular sequencer rank 9

◆ ADC_SQR2_SQ9_0

#define ADC_SQR2_SQ9_0 (0x01UL << ADC_SQR2_SQ9_Pos)

0x01000000

◆ ADC_SQR2_SQ9_1

#define ADC_SQR2_SQ9_1 (0x02UL << ADC_SQR2_SQ9_Pos)

0x02000000

◆ ADC_SQR2_SQ9_2

#define ADC_SQR2_SQ9_2 (0x04UL << ADC_SQR2_SQ9_Pos)

0x04000000

◆ ADC_SQR2_SQ9_3

#define ADC_SQR2_SQ9_3 (0x08UL << ADC_SQR2_SQ9_Pos)

0x08000000

◆ ADC_SQR2_SQ9_4

#define ADC_SQR2_SQ9_4 (0x10UL << ADC_SQR2_SQ9_Pos)

0x10000000

◆ ADC_SQR2_SQ9_Msk

#define ADC_SQR2_SQ9_Msk (0x1FUL << ADC_SQR2_SQ9_Pos)

0x1F000000

◆ ADC_SQR2_SQ9_Pos

#define ADC_SQR2_SQ9_Pos (24U)

◆ ADC_SQR3_SQ10

#define ADC_SQR3_SQ10 ADC_SQR3_SQ10_Msk

ADC group regular sequencer rank 10

◆ ADC_SQR3_SQ10_0

#define ADC_SQR3_SQ10_0 (0x01UL << ADC_SQR3_SQ10_Pos)

0x00000001

◆ ADC_SQR3_SQ10_1

#define ADC_SQR3_SQ10_1 (0x02UL << ADC_SQR3_SQ10_Pos)

0x00000002

◆ ADC_SQR3_SQ10_2

#define ADC_SQR3_SQ10_2 (0x04UL << ADC_SQR3_SQ10_Pos)

0x00000004

◆ ADC_SQR3_SQ10_3

#define ADC_SQR3_SQ10_3 (0x08UL << ADC_SQR3_SQ10_Pos)

0x00000008

◆ ADC_SQR3_SQ10_4

#define ADC_SQR3_SQ10_4 (0x10UL << ADC_SQR3_SQ10_Pos)

0x00000010

◆ ADC_SQR3_SQ10_Msk

#define ADC_SQR3_SQ10_Msk (0x1FUL << ADC_SQR3_SQ10_Pos)

0x0000001F

◆ ADC_SQR3_SQ10_Pos

#define ADC_SQR3_SQ10_Pos (0U)

◆ ADC_SQR3_SQ11

#define ADC_SQR3_SQ11 ADC_SQR3_SQ11_Msk

ADC group regular sequencer rank 11

◆ ADC_SQR3_SQ11_0

#define ADC_SQR3_SQ11_0 (0x01UL << ADC_SQR3_SQ11_Pos)

0x00000040

◆ ADC_SQR3_SQ11_1

#define ADC_SQR3_SQ11_1 (0x02UL << ADC_SQR3_SQ11_Pos)

0x00000080

◆ ADC_SQR3_SQ11_2

#define ADC_SQR3_SQ11_2 (0x04UL << ADC_SQR3_SQ11_Pos)

0x00000100

◆ ADC_SQR3_SQ11_3

#define ADC_SQR3_SQ11_3 (0x08UL << ADC_SQR3_SQ11_Pos)

0x00000200

◆ ADC_SQR3_SQ11_4

#define ADC_SQR3_SQ11_4 (0x10UL << ADC_SQR3_SQ11_Pos)

0x00000400

◆ ADC_SQR3_SQ11_Msk

#define ADC_SQR3_SQ11_Msk (0x1FUL << ADC_SQR3_SQ11_Pos)

0x000007C0

◆ ADC_SQR3_SQ11_Pos

#define ADC_SQR3_SQ11_Pos (6U)

◆ ADC_SQR3_SQ12

#define ADC_SQR3_SQ12 ADC_SQR3_SQ12_Msk

ADC group regular sequencer rank 12

◆ ADC_SQR3_SQ12_0

#define ADC_SQR3_SQ12_0 (0x01UL << ADC_SQR3_SQ12_Pos)

0x00001000

◆ ADC_SQR3_SQ12_1

#define ADC_SQR3_SQ12_1 (0x02UL << ADC_SQR3_SQ12_Pos)

0x00002000

◆ ADC_SQR3_SQ12_2

#define ADC_SQR3_SQ12_2 (0x04UL << ADC_SQR3_SQ12_Pos)

0x00004000

◆ ADC_SQR3_SQ12_3

#define ADC_SQR3_SQ12_3 (0x08UL << ADC_SQR3_SQ12_Pos)

0x00008000

◆ ADC_SQR3_SQ12_4

#define ADC_SQR3_SQ12_4 (0x10UL << ADC_SQR3_SQ12_Pos)

0x00010000

◆ ADC_SQR3_SQ12_Msk

#define ADC_SQR3_SQ12_Msk (0x1FUL << ADC_SQR3_SQ12_Pos)

0x0001F000

◆ ADC_SQR3_SQ12_Pos

#define ADC_SQR3_SQ12_Pos (12U)

◆ ADC_SQR3_SQ13

#define ADC_SQR3_SQ13 ADC_SQR3_SQ13_Msk

ADC group regular sequencer rank 13

◆ ADC_SQR3_SQ13_0

#define ADC_SQR3_SQ13_0 (0x01UL << ADC_SQR3_SQ13_Pos)

0x00040000

◆ ADC_SQR3_SQ13_1

#define ADC_SQR3_SQ13_1 (0x02UL << ADC_SQR3_SQ13_Pos)

0x00080000

◆ ADC_SQR3_SQ13_2

#define ADC_SQR3_SQ13_2 (0x04UL << ADC_SQR3_SQ13_Pos)

0x00100000

◆ ADC_SQR3_SQ13_3

#define ADC_SQR3_SQ13_3 (0x08UL << ADC_SQR3_SQ13_Pos)

0x00200000

◆ ADC_SQR3_SQ13_4

#define ADC_SQR3_SQ13_4 (0x10UL << ADC_SQR3_SQ13_Pos)

0x00400000

◆ ADC_SQR3_SQ13_Msk

#define ADC_SQR3_SQ13_Msk (0x1FUL << ADC_SQR3_SQ13_Pos)

0x007C0000

◆ ADC_SQR3_SQ13_Pos

#define ADC_SQR3_SQ13_Pos (18U)

◆ ADC_SQR3_SQ14

#define ADC_SQR3_SQ14 ADC_SQR3_SQ14_Msk

ADC group regular sequencer rank 14

◆ ADC_SQR3_SQ14_0

#define ADC_SQR3_SQ14_0 (0x01UL << ADC_SQR3_SQ14_Pos)

0x01000000

◆ ADC_SQR3_SQ14_1

#define ADC_SQR3_SQ14_1 (0x02UL << ADC_SQR3_SQ14_Pos)

0x02000000

◆ ADC_SQR3_SQ14_2

#define ADC_SQR3_SQ14_2 (0x04UL << ADC_SQR3_SQ14_Pos)

0x04000000

◆ ADC_SQR3_SQ14_3

#define ADC_SQR3_SQ14_3 (0x08UL << ADC_SQR3_SQ14_Pos)

0x08000000

◆ ADC_SQR3_SQ14_4

#define ADC_SQR3_SQ14_4 (0x10UL << ADC_SQR3_SQ14_Pos)

0x10000000

◆ ADC_SQR3_SQ14_Msk

#define ADC_SQR3_SQ14_Msk (0x1FUL << ADC_SQR3_SQ14_Pos)

0x1F000000

◆ ADC_SQR3_SQ14_Pos

#define ADC_SQR3_SQ14_Pos (24U)

◆ ADC_SQR4_SQ15

#define ADC_SQR4_SQ15 ADC_SQR4_SQ15_Msk

ADC group regular sequencer rank 15

◆ ADC_SQR4_SQ15_0

#define ADC_SQR4_SQ15_0 (0x01UL << ADC_SQR4_SQ15_Pos)

0x00000001

◆ ADC_SQR4_SQ15_1

#define ADC_SQR4_SQ15_1 (0x02UL << ADC_SQR4_SQ15_Pos)

0x00000002

◆ ADC_SQR4_SQ15_2

#define ADC_SQR4_SQ15_2 (0x04UL << ADC_SQR4_SQ15_Pos)

0x00000004

◆ ADC_SQR4_SQ15_3

#define ADC_SQR4_SQ15_3 (0x08UL << ADC_SQR4_SQ15_Pos)

0x00000008

◆ ADC_SQR4_SQ15_4

#define ADC_SQR4_SQ15_4 (0x10UL << ADC_SQR4_SQ15_Pos)

0x00000010

◆ ADC_SQR4_SQ15_Msk

#define ADC_SQR4_SQ15_Msk (0x1FUL << ADC_SQR4_SQ15_Pos)

0x0000001F

◆ ADC_SQR4_SQ15_Pos

#define ADC_SQR4_SQ15_Pos (0U)

◆ ADC_SQR4_SQ16

#define ADC_SQR4_SQ16 ADC_SQR4_SQ16_Msk

ADC group regular sequencer rank 16

◆ ADC_SQR4_SQ16_0

#define ADC_SQR4_SQ16_0 (0x01UL << ADC_SQR4_SQ16_Pos)

0x00000040

◆ ADC_SQR4_SQ16_1

#define ADC_SQR4_SQ16_1 (0x02UL << ADC_SQR4_SQ16_Pos)

0x00000080

◆ ADC_SQR4_SQ16_2

#define ADC_SQR4_SQ16_2 (0x04UL << ADC_SQR4_SQ16_Pos)

0x00000100

◆ ADC_SQR4_SQ16_3

#define ADC_SQR4_SQ16_3 (0x08UL << ADC_SQR4_SQ16_Pos)

0x00000200

◆ ADC_SQR4_SQ16_4

#define ADC_SQR4_SQ16_4 (0x10UL << ADC_SQR4_SQ16_Pos)

0x00000400

◆ ADC_SQR4_SQ16_Msk

#define ADC_SQR4_SQ16_Msk (0x1FUL << ADC_SQR4_SQ16_Pos)

0x000007C0

◆ ADC_SQR4_SQ16_Pos

#define ADC_SQR4_SQ16_Pos (6U)

◆ ADC_TR1_HT1

#define ADC_TR1_HT1 ADC_TR1_HT1_Msk

ADC Analog watchdog 1 threshold high

◆ ADC_TR1_HT1_0

#define ADC_TR1_HT1_0 (0x001UL << ADC_TR1_HT1_Pos)

0x00010000

◆ ADC_TR1_HT1_1

#define ADC_TR1_HT1_1 (0x002UL << ADC_TR1_HT1_Pos)

0x00020000

◆ ADC_TR1_HT1_10

#define ADC_TR1_HT1_10 (0x400UL << ADC_TR1_HT1_Pos)

0x04000000

◆ ADC_TR1_HT1_11

#define ADC_TR1_HT1_11 (0x800UL << ADC_TR1_HT1_Pos)

0x08000000

◆ ADC_TR1_HT1_2

#define ADC_TR1_HT1_2 (0x004UL << ADC_TR1_HT1_Pos)

0x00040000

◆ ADC_TR1_HT1_3

#define ADC_TR1_HT1_3 (0x008UL << ADC_TR1_HT1_Pos)

0x00080000

◆ ADC_TR1_HT1_4

#define ADC_TR1_HT1_4 (0x010UL << ADC_TR1_HT1_Pos)

0x00100000

◆ ADC_TR1_HT1_5

#define ADC_TR1_HT1_5 (0x020UL << ADC_TR1_HT1_Pos)

0x00200000

◆ ADC_TR1_HT1_6

#define ADC_TR1_HT1_6 (0x040UL << ADC_TR1_HT1_Pos)

0x00400000

◆ ADC_TR1_HT1_7

#define ADC_TR1_HT1_7 (0x080UL << ADC_TR1_HT1_Pos)

0x00800000

◆ ADC_TR1_HT1_8

#define ADC_TR1_HT1_8 (0x100UL << ADC_TR1_HT1_Pos)

0x01000000

◆ ADC_TR1_HT1_9

#define ADC_TR1_HT1_9 (0x200UL << ADC_TR1_HT1_Pos)

0x02000000

◆ ADC_TR1_HT1_Msk

#define ADC_TR1_HT1_Msk (0xFFFUL << ADC_TR1_HT1_Pos)

0x0FFF0000

◆ ADC_TR1_HT1_Pos

#define ADC_TR1_HT1_Pos (16U)

◆ ADC_TR1_LT1

#define ADC_TR1_LT1 ADC_TR1_LT1_Msk

ADC analog watchdog 1 threshold low

◆ ADC_TR1_LT1_0

#define ADC_TR1_LT1_0 (0x001UL << ADC_TR1_LT1_Pos)

0x00000001

◆ ADC_TR1_LT1_1

#define ADC_TR1_LT1_1 (0x002UL << ADC_TR1_LT1_Pos)

0x00000002

◆ ADC_TR1_LT1_10

#define ADC_TR1_LT1_10 (0x400UL << ADC_TR1_LT1_Pos)

0x00000400

◆ ADC_TR1_LT1_11

#define ADC_TR1_LT1_11 (0x800UL << ADC_TR1_LT1_Pos)

0x00000800

◆ ADC_TR1_LT1_2

#define ADC_TR1_LT1_2 (0x004UL << ADC_TR1_LT1_Pos)

0x00000004

◆ ADC_TR1_LT1_3

#define ADC_TR1_LT1_3 (0x008UL << ADC_TR1_LT1_Pos)

0x00000008

◆ ADC_TR1_LT1_4

#define ADC_TR1_LT1_4 (0x010UL << ADC_TR1_LT1_Pos)

0x00000010

◆ ADC_TR1_LT1_5

#define ADC_TR1_LT1_5 (0x020UL << ADC_TR1_LT1_Pos)

0x00000020

◆ ADC_TR1_LT1_6

#define ADC_TR1_LT1_6 (0x040UL << ADC_TR1_LT1_Pos)

0x00000040

◆ ADC_TR1_LT1_7

#define ADC_TR1_LT1_7 (0x080UL << ADC_TR1_LT1_Pos)

0x00000080

◆ ADC_TR1_LT1_8

#define ADC_TR1_LT1_8 (0x100UL << ADC_TR1_LT1_Pos)

0x00000100

◆ ADC_TR1_LT1_9

#define ADC_TR1_LT1_9 (0x200UL << ADC_TR1_LT1_Pos)

0x00000200

◆ ADC_TR1_LT1_Msk

#define ADC_TR1_LT1_Msk (0xFFFUL << ADC_TR1_LT1_Pos)

0x00000FFF

◆ ADC_TR1_LT1_Pos

#define ADC_TR1_LT1_Pos (0U)

◆ ADC_TR2_HT2

#define ADC_TR2_HT2 ADC_TR2_HT2_Msk

ADC analog watchdog 2 threshold high

◆ ADC_TR2_HT2_0

#define ADC_TR2_HT2_0 (0x01UL << ADC_TR2_HT2_Pos)

0x00010000

◆ ADC_TR2_HT2_1

#define ADC_TR2_HT2_1 (0x02UL << ADC_TR2_HT2_Pos)

0x00020000

◆ ADC_TR2_HT2_2

#define ADC_TR2_HT2_2 (0x04UL << ADC_TR2_HT2_Pos)

0x00040000

◆ ADC_TR2_HT2_3

#define ADC_TR2_HT2_3 (0x08UL << ADC_TR2_HT2_Pos)

0x00080000

◆ ADC_TR2_HT2_4

#define ADC_TR2_HT2_4 (0x10UL << ADC_TR2_HT2_Pos)

0x00100000

◆ ADC_TR2_HT2_5

#define ADC_TR2_HT2_5 (0x20UL << ADC_TR2_HT2_Pos)

0x00200000

◆ ADC_TR2_HT2_6

#define ADC_TR2_HT2_6 (0x40UL << ADC_TR2_HT2_Pos)

0x00400000

◆ ADC_TR2_HT2_7

#define ADC_TR2_HT2_7 (0x80UL << ADC_TR2_HT2_Pos)

0x00800000

◆ ADC_TR2_HT2_Msk

#define ADC_TR2_HT2_Msk (0xFFUL << ADC_TR2_HT2_Pos)

0x00FF0000

◆ ADC_TR2_HT2_Pos

#define ADC_TR2_HT2_Pos (16U)

◆ ADC_TR2_LT2

#define ADC_TR2_LT2 ADC_TR2_LT2_Msk

ADC analog watchdog 2 threshold low

◆ ADC_TR2_LT2_0

#define ADC_TR2_LT2_0 (0x01UL << ADC_TR2_LT2_Pos)

0x00000001

◆ ADC_TR2_LT2_1

#define ADC_TR2_LT2_1 (0x02UL << ADC_TR2_LT2_Pos)

0x00000002

◆ ADC_TR2_LT2_2

#define ADC_TR2_LT2_2 (0x04UL << ADC_TR2_LT2_Pos)

0x00000004

◆ ADC_TR2_LT2_3

#define ADC_TR2_LT2_3 (0x08UL << ADC_TR2_LT2_Pos)

0x00000008

◆ ADC_TR2_LT2_4

#define ADC_TR2_LT2_4 (0x10UL << ADC_TR2_LT2_Pos)

0x00000010

◆ ADC_TR2_LT2_5

#define ADC_TR2_LT2_5 (0x20UL << ADC_TR2_LT2_Pos)

0x00000020

◆ ADC_TR2_LT2_6

#define ADC_TR2_LT2_6 (0x40UL << ADC_TR2_LT2_Pos)

0x00000040

◆ ADC_TR2_LT2_7

#define ADC_TR2_LT2_7 (0x80UL << ADC_TR2_LT2_Pos)

0x00000080

◆ ADC_TR2_LT2_Msk

#define ADC_TR2_LT2_Msk (0xFFUL << ADC_TR2_LT2_Pos)

0x000000FF

◆ ADC_TR2_LT2_Pos

#define ADC_TR2_LT2_Pos (0U)

◆ ADC_TR3_HT3

#define ADC_TR3_HT3 ADC_TR3_HT3_Msk

ADC analog watchdog 3 threshold high

◆ ADC_TR3_HT3_0

#define ADC_TR3_HT3_0 (0x01UL << ADC_TR3_HT3_Pos)

0x00010000

◆ ADC_TR3_HT3_1

#define ADC_TR3_HT3_1 (0x02UL << ADC_TR3_HT3_Pos)

0x00020000

◆ ADC_TR3_HT3_2

#define ADC_TR3_HT3_2 (0x04UL << ADC_TR3_HT3_Pos)

0x00040000

◆ ADC_TR3_HT3_3

#define ADC_TR3_HT3_3 (0x08UL << ADC_TR3_HT3_Pos)

0x00080000

◆ ADC_TR3_HT3_4

#define ADC_TR3_HT3_4 (0x10UL << ADC_TR3_HT3_Pos)

0x00100000

◆ ADC_TR3_HT3_5

#define ADC_TR3_HT3_5 (0x20UL << ADC_TR3_HT3_Pos)

0x00200000

◆ ADC_TR3_HT3_6

#define ADC_TR3_HT3_6 (0x40UL << ADC_TR3_HT3_Pos)

0x00400000

◆ ADC_TR3_HT3_7

#define ADC_TR3_HT3_7 (0x80UL << ADC_TR3_HT3_Pos)

0x00800000

◆ ADC_TR3_HT3_Msk

#define ADC_TR3_HT3_Msk (0xFFUL << ADC_TR3_HT3_Pos)

0x00FF0000

◆ ADC_TR3_HT3_Pos

#define ADC_TR3_HT3_Pos (16U)

◆ ADC_TR3_LT3

#define ADC_TR3_LT3 ADC_TR3_LT3_Msk

ADC analog watchdog 3 threshold low

◆ ADC_TR3_LT3_0

#define ADC_TR3_LT3_0 (0x01UL << ADC_TR3_LT3_Pos)

0x00000001

◆ ADC_TR3_LT3_1

#define ADC_TR3_LT3_1 (0x02UL << ADC_TR3_LT3_Pos)

0x00000002

◆ ADC_TR3_LT3_2

#define ADC_TR3_LT3_2 (0x04UL << ADC_TR3_LT3_Pos)

0x00000004

◆ ADC_TR3_LT3_3

#define ADC_TR3_LT3_3 (0x08UL << ADC_TR3_LT3_Pos)

0x00000008

◆ ADC_TR3_LT3_4

#define ADC_TR3_LT3_4 (0x10UL << ADC_TR3_LT3_Pos)

0x00000010

◆ ADC_TR3_LT3_5

#define ADC_TR3_LT3_5 (0x20UL << ADC_TR3_LT3_Pos)

0x00000020

◆ ADC_TR3_LT3_6

#define ADC_TR3_LT3_6 (0x40UL << ADC_TR3_LT3_Pos)

0x00000040

◆ ADC_TR3_LT3_7

#define ADC_TR3_LT3_7 (0x80UL << ADC_TR3_LT3_Pos)

0x00000080

◆ ADC_TR3_LT3_Msk

#define ADC_TR3_LT3_Msk (0xFFUL << ADC_TR3_LT3_Pos)

0x000000FF

◆ ADC_TR3_LT3_Pos

#define ADC_TR3_LT3_Pos (0U)

◆ CAN_BTR_BRP

#define CAN_BTR_BRP CAN_BTR_BRP_Msk

Baud Rate Prescaler

◆ CAN_BTR_BRP_Msk

#define CAN_BTR_BRP_Msk (0x3FFUL << CAN_BTR_BRP_Pos)

0x000003FF

◆ CAN_BTR_BRP_Pos

#define CAN_BTR_BRP_Pos (0U)

◆ CAN_BTR_LBKM

#define CAN_BTR_LBKM CAN_BTR_LBKM_Msk

Loop Back Mode (Debug)

◆ CAN_BTR_LBKM_Msk

#define CAN_BTR_LBKM_Msk (0x1UL << CAN_BTR_LBKM_Pos)

0x40000000

◆ CAN_BTR_LBKM_Pos

#define CAN_BTR_LBKM_Pos (30U)

◆ CAN_BTR_SILM

#define CAN_BTR_SILM CAN_BTR_SILM_Msk

Silent Mode Mailbox registers

◆ CAN_BTR_SILM_Msk

#define CAN_BTR_SILM_Msk (0x1UL << CAN_BTR_SILM_Pos)

0x80000000

◆ CAN_BTR_SILM_Pos

#define CAN_BTR_SILM_Pos (31U)

◆ CAN_BTR_SJW

#define CAN_BTR_SJW CAN_BTR_SJW_Msk

Resynchronization Jump Width

◆ CAN_BTR_SJW_0

#define CAN_BTR_SJW_0 (0x1UL << CAN_BTR_SJW_Pos)

0x01000000

◆ CAN_BTR_SJW_1

#define CAN_BTR_SJW_1 (0x2UL << CAN_BTR_SJW_Pos)

0x02000000

◆ CAN_BTR_SJW_Msk

#define CAN_BTR_SJW_Msk (0x3UL << CAN_BTR_SJW_Pos)

0x03000000

◆ CAN_BTR_SJW_Pos

#define CAN_BTR_SJW_Pos (24U)

◆ CAN_BTR_TS1

#define CAN_BTR_TS1 CAN_BTR_TS1_Msk

Time Segment 1

◆ CAN_BTR_TS1_0

#define CAN_BTR_TS1_0 (0x1UL << CAN_BTR_TS1_Pos)

0x00010000

◆ CAN_BTR_TS1_1

#define CAN_BTR_TS1_1 (0x2UL << CAN_BTR_TS1_Pos)

0x00020000

◆ CAN_BTR_TS1_2

#define CAN_BTR_TS1_2 (0x4UL << CAN_BTR_TS1_Pos)

0x00040000

◆ CAN_BTR_TS1_3

#define CAN_BTR_TS1_3 (0x8UL << CAN_BTR_TS1_Pos)

0x00080000

◆ CAN_BTR_TS1_Msk

#define CAN_BTR_TS1_Msk (0xFUL << CAN_BTR_TS1_Pos)

0x000F0000

◆ CAN_BTR_TS1_Pos

#define CAN_BTR_TS1_Pos (16U)

◆ CAN_BTR_TS2

#define CAN_BTR_TS2 CAN_BTR_TS2_Msk

Time Segment 2

◆ CAN_BTR_TS2_0

#define CAN_BTR_TS2_0 (0x1UL << CAN_BTR_TS2_Pos)

0x00100000

◆ CAN_BTR_TS2_1

#define CAN_BTR_TS2_1 (0x2UL << CAN_BTR_TS2_Pos)

0x00200000

◆ CAN_BTR_TS2_2

#define CAN_BTR_TS2_2 (0x4UL << CAN_BTR_TS2_Pos)

0x00400000

◆ CAN_BTR_TS2_Msk

#define CAN_BTR_TS2_Msk (0x7UL << CAN_BTR_TS2_Pos)

0x00700000

◆ CAN_BTR_TS2_Pos

#define CAN_BTR_TS2_Pos (20U)

◆ CAN_ESR_BOFF

#define CAN_ESR_BOFF CAN_ESR_BOFF_Msk

Bus-Off Flag

◆ CAN_ESR_BOFF_Msk

#define CAN_ESR_BOFF_Msk (0x1UL << CAN_ESR_BOFF_Pos)

0x00000004

◆ CAN_ESR_BOFF_Pos

#define CAN_ESR_BOFF_Pos (2U)

◆ CAN_ESR_EPVF

#define CAN_ESR_EPVF CAN_ESR_EPVF_Msk

Error Passive Flag

◆ CAN_ESR_EPVF_Msk

#define CAN_ESR_EPVF_Msk (0x1UL << CAN_ESR_EPVF_Pos)

0x00000002

◆ CAN_ESR_EPVF_Pos

#define CAN_ESR_EPVF_Pos (1U)

◆ CAN_ESR_EWGF

#define CAN_ESR_EWGF CAN_ESR_EWGF_Msk

Error Warning Flag

◆ CAN_ESR_EWGF_Msk

#define CAN_ESR_EWGF_Msk (0x1UL << CAN_ESR_EWGF_Pos)

0x00000001

◆ CAN_ESR_EWGF_Pos

#define CAN_ESR_EWGF_Pos (0U)

◆ CAN_ESR_LEC

#define CAN_ESR_LEC CAN_ESR_LEC_Msk

LEC[2:0] bits (Last Error Code)

◆ CAN_ESR_LEC_0

#define CAN_ESR_LEC_0 (0x1UL << CAN_ESR_LEC_Pos)

0x00000010

◆ CAN_ESR_LEC_1

#define CAN_ESR_LEC_1 (0x2UL << CAN_ESR_LEC_Pos)

0x00000020

◆ CAN_ESR_LEC_2

#define CAN_ESR_LEC_2 (0x4UL << CAN_ESR_LEC_Pos)

0x00000040

◆ CAN_ESR_LEC_Msk

#define CAN_ESR_LEC_Msk (0x7UL << CAN_ESR_LEC_Pos)

0x00000070

◆ CAN_ESR_LEC_Pos

#define CAN_ESR_LEC_Pos (4U)

◆ CAN_ESR_REC

#define CAN_ESR_REC CAN_ESR_REC_Msk

Receive Error Counter

◆ CAN_ESR_REC_Msk

#define CAN_ESR_REC_Msk (0xFFUL << CAN_ESR_REC_Pos)

0xFF000000

◆ CAN_ESR_REC_Pos

#define CAN_ESR_REC_Pos (24U)

◆ CAN_ESR_TEC

#define CAN_ESR_TEC CAN_ESR_TEC_Msk

Least significant byte of the 9-bit Transmit Error Counter

◆ CAN_ESR_TEC_Msk

#define CAN_ESR_TEC_Msk (0xFFUL << CAN_ESR_TEC_Pos)

0x00FF0000

◆ CAN_ESR_TEC_Pos

#define CAN_ESR_TEC_Pos (16U)

◆ CAN_F0R1_FB0

#define CAN_F0R1_FB0 CAN_F0R1_FB0_Msk

Filter bit 0

◆ CAN_F0R1_FB0_Msk

#define CAN_F0R1_FB0_Msk (0x1UL << CAN_F0R1_FB0_Pos)

0x00000001

◆ CAN_F0R1_FB0_Pos

#define CAN_F0R1_FB0_Pos (0U)

◆ CAN_F0R1_FB1

#define CAN_F0R1_FB1 CAN_F0R1_FB1_Msk

Filter bit 1

◆ CAN_F0R1_FB10

#define CAN_F0R1_FB10 CAN_F0R1_FB10_Msk

Filter bit 10

◆ CAN_F0R1_FB10_Msk

#define CAN_F0R1_FB10_Msk (0x1UL << CAN_F0R1_FB10_Pos)

0x00000400

◆ CAN_F0R1_FB10_Pos

#define CAN_F0R1_FB10_Pos (10U)

◆ CAN_F0R1_FB11

#define CAN_F0R1_FB11 CAN_F0R1_FB11_Msk

Filter bit 11

◆ CAN_F0R1_FB11_Msk

#define CAN_F0R1_FB11_Msk (0x1UL << CAN_F0R1_FB11_Pos)

0x00000800

◆ CAN_F0R1_FB11_Pos

#define CAN_F0R1_FB11_Pos (11U)

◆ CAN_F0R1_FB12

#define CAN_F0R1_FB12 CAN_F0R1_FB12_Msk

Filter bit 12

◆ CAN_F0R1_FB12_Msk

#define CAN_F0R1_FB12_Msk (0x1UL << CAN_F0R1_FB12_Pos)

0x00001000

◆ CAN_F0R1_FB12_Pos

#define CAN_F0R1_FB12_Pos (12U)

◆ CAN_F0R1_FB13

#define CAN_F0R1_FB13 CAN_F0R1_FB13_Msk

Filter bit 13

◆ CAN_F0R1_FB13_Msk

#define CAN_F0R1_FB13_Msk (0x1UL << CAN_F0R1_FB13_Pos)

0x00002000

◆ CAN_F0R1_FB13_Pos

#define CAN_F0R1_FB13_Pos (13U)

◆ CAN_F0R1_FB14

#define CAN_F0R1_FB14 CAN_F0R1_FB14_Msk

Filter bit 14

◆ CAN_F0R1_FB14_Msk

#define CAN_F0R1_FB14_Msk (0x1UL << CAN_F0R1_FB14_Pos)

0x00004000

◆ CAN_F0R1_FB14_Pos

#define CAN_F0R1_FB14_Pos (14U)

◆ CAN_F0R1_FB15

#define CAN_F0R1_FB15 CAN_F0R1_FB15_Msk

Filter bit 15

◆ CAN_F0R1_FB15_Msk

#define CAN_F0R1_FB15_Msk (0x1UL << CAN_F0R1_FB15_Pos)

0x00008000

◆ CAN_F0R1_FB15_Pos

#define CAN_F0R1_FB15_Pos (15U)

◆ CAN_F0R1_FB16

#define CAN_F0R1_FB16 CAN_F0R1_FB16_Msk

Filter bit 16

◆ CAN_F0R1_FB16_Msk

#define CAN_F0R1_FB16_Msk (0x1UL << CAN_F0R1_FB16_Pos)

0x00010000

◆ CAN_F0R1_FB16_Pos

#define CAN_F0R1_FB16_Pos (16U)

◆ CAN_F0R1_FB17

#define CAN_F0R1_FB17 CAN_F0R1_FB17_Msk

Filter bit 17

◆ CAN_F0R1_FB17_Msk

#define CAN_F0R1_FB17_Msk (0x1UL << CAN_F0R1_FB17_Pos)

0x00020000

◆ CAN_F0R1_FB17_Pos

#define CAN_F0R1_FB17_Pos (17U)

◆ CAN_F0R1_FB18

#define CAN_F0R1_FB18 CAN_F0R1_FB18_Msk

Filter bit 18

◆ CAN_F0R1_FB18_Msk

#define CAN_F0R1_FB18_Msk (0x1UL << CAN_F0R1_FB18_Pos)

0x00040000

◆ CAN_F0R1_FB18_Pos

#define CAN_F0R1_FB18_Pos (18U)

◆ CAN_F0R1_FB19

#define CAN_F0R1_FB19 CAN_F0R1_FB19_Msk

Filter bit 19

◆ CAN_F0R1_FB19_Msk

#define CAN_F0R1_FB19_Msk (0x1UL << CAN_F0R1_FB19_Pos)

0x00080000

◆ CAN_F0R1_FB19_Pos

#define CAN_F0R1_FB19_Pos (19U)

◆ CAN_F0R1_FB1_Msk

#define CAN_F0R1_FB1_Msk (0x1UL << CAN_F0R1_FB1_Pos)

0x00000002

◆ CAN_F0R1_FB1_Pos

#define CAN_F0R1_FB1_Pos (1U)

◆ CAN_F0R1_FB2

#define CAN_F0R1_FB2 CAN_F0R1_FB2_Msk

Filter bit 2

◆ CAN_F0R1_FB20

#define CAN_F0R1_FB20 CAN_F0R1_FB20_Msk

Filter bit 20

◆ CAN_F0R1_FB20_Msk

#define CAN_F0R1_FB20_Msk (0x1UL << CAN_F0R1_FB20_Pos)

0x00100000

◆ CAN_F0R1_FB20_Pos

#define CAN_F0R1_FB20_Pos (20U)

◆ CAN_F0R1_FB21

#define CAN_F0R1_FB21 CAN_F0R1_FB21_Msk

Filter bit 21

◆ CAN_F0R1_FB21_Msk

#define CAN_F0R1_FB21_Msk (0x1UL << CAN_F0R1_FB21_Pos)

0x00200000

◆ CAN_F0R1_FB21_Pos

#define CAN_F0R1_FB21_Pos (21U)

◆ CAN_F0R1_FB22

#define CAN_F0R1_FB22 CAN_F0R1_FB22_Msk

Filter bit 22

◆ CAN_F0R1_FB22_Msk

#define CAN_F0R1_FB22_Msk (0x1UL << CAN_F0R1_FB22_Pos)

0x00400000

◆ CAN_F0R1_FB22_Pos

#define CAN_F0R1_FB22_Pos (22U)

◆ CAN_F0R1_FB23

#define CAN_F0R1_FB23 CAN_F0R1_FB23_Msk

Filter bit 23

◆ CAN_F0R1_FB23_Msk

#define CAN_F0R1_FB23_Msk (0x1UL << CAN_F0R1_FB23_Pos)

0x00800000

◆ CAN_F0R1_FB23_Pos

#define CAN_F0R1_FB23_Pos (23U)

◆ CAN_F0R1_FB24

#define CAN_F0R1_FB24 CAN_F0R1_FB24_Msk

Filter bit 24

◆ CAN_F0R1_FB24_Msk

#define CAN_F0R1_FB24_Msk (0x1UL << CAN_F0R1_FB24_Pos)

0x01000000

◆ CAN_F0R1_FB24_Pos

#define CAN_F0R1_FB24_Pos (24U)

◆ CAN_F0R1_FB25

#define CAN_F0R1_FB25 CAN_F0R1_FB25_Msk

Filter bit 25

◆ CAN_F0R1_FB25_Msk

#define CAN_F0R1_FB25_Msk (0x1UL << CAN_F0R1_FB25_Pos)

0x02000000

◆ CAN_F0R1_FB25_Pos

#define CAN_F0R1_FB25_Pos (25U)

◆ CAN_F0R1_FB26

#define CAN_F0R1_FB26 CAN_F0R1_FB26_Msk

Filter bit 26

◆ CAN_F0R1_FB26_Msk

#define CAN_F0R1_FB26_Msk (0x1UL << CAN_F0R1_FB26_Pos)

0x04000000

◆ CAN_F0R1_FB26_Pos

#define CAN_F0R1_FB26_Pos (26U)

◆ CAN_F0R1_FB27

#define CAN_F0R1_FB27 CAN_F0R1_FB27_Msk

Filter bit 27

◆ CAN_F0R1_FB27_Msk

#define CAN_F0R1_FB27_Msk (0x1UL << CAN_F0R1_FB27_Pos)

0x08000000

◆ CAN_F0R1_FB27_Pos

#define CAN_F0R1_FB27_Pos (27U)

◆ CAN_F0R1_FB28

#define CAN_F0R1_FB28 CAN_F0R1_FB28_Msk

Filter bit 28

◆ CAN_F0R1_FB28_Msk

#define CAN_F0R1_FB28_Msk (0x1UL << CAN_F0R1_FB28_Pos)

0x10000000

◆ CAN_F0R1_FB28_Pos

#define CAN_F0R1_FB28_Pos (28U)

◆ CAN_F0R1_FB29

#define CAN_F0R1_FB29 CAN_F0R1_FB29_Msk

Filter bit 29

◆ CAN_F0R1_FB29_Msk

#define CAN_F0R1_FB29_Msk (0x1UL << CAN_F0R1_FB29_Pos)

0x20000000

◆ CAN_F0R1_FB29_Pos

#define CAN_F0R1_FB29_Pos (29U)

◆ CAN_F0R1_FB2_Msk

#define CAN_F0R1_FB2_Msk (0x1UL << CAN_F0R1_FB2_Pos)

0x00000004

◆ CAN_F0R1_FB2_Pos

#define CAN_F0R1_FB2_Pos (2U)

◆ CAN_F0R1_FB3

#define CAN_F0R1_FB3 CAN_F0R1_FB3_Msk

Filter bit 3

◆ CAN_F0R1_FB30

#define CAN_F0R1_FB30 CAN_F0R1_FB30_Msk

Filter bit 30

◆ CAN_F0R1_FB30_Msk

#define CAN_F0R1_FB30_Msk (0x1UL << CAN_F0R1_FB30_Pos)

0x40000000

◆ CAN_F0R1_FB30_Pos

#define CAN_F0R1_FB30_Pos (30U)

◆ CAN_F0R1_FB31

#define CAN_F0R1_FB31 CAN_F0R1_FB31_Msk

Filter bit 31

◆ CAN_F0R1_FB31_Msk

#define CAN_F0R1_FB31_Msk (0x1UL << CAN_F0R1_FB31_Pos)

0x80000000

◆ CAN_F0R1_FB31_Pos

#define CAN_F0R1_FB31_Pos (31U)

◆ CAN_F0R1_FB3_Msk

#define CAN_F0R1_FB3_Msk (0x1UL << CAN_F0R1_FB3_Pos)

0x00000008

◆ CAN_F0R1_FB3_Pos

#define CAN_F0R1_FB3_Pos (3U)

◆ CAN_F0R1_FB4

#define CAN_F0R1_FB4 CAN_F0R1_FB4_Msk

Filter bit 4

◆ CAN_F0R1_FB4_Msk

#define CAN_F0R1_FB4_Msk (0x1UL << CAN_F0R1_FB4_Pos)

0x00000010

◆ CAN_F0R1_FB4_Pos

#define CAN_F0R1_FB4_Pos (4U)

◆ CAN_F0R1_FB5

#define CAN_F0R1_FB5 CAN_F0R1_FB5_Msk

Filter bit 5

◆ CAN_F0R1_FB5_Msk

#define CAN_F0R1_FB5_Msk (0x1UL << CAN_F0R1_FB5_Pos)

0x00000020

◆ CAN_F0R1_FB5_Pos

#define CAN_F0R1_FB5_Pos (5U)

◆ CAN_F0R1_FB6

#define CAN_F0R1_FB6 CAN_F0R1_FB6_Msk

Filter bit 6

◆ CAN_F0R1_FB6_Msk

#define CAN_F0R1_FB6_Msk (0x1UL << CAN_F0R1_FB6_Pos)

0x00000040

◆ CAN_F0R1_FB6_Pos

#define CAN_F0R1_FB6_Pos (6U)

◆ CAN_F0R1_FB7

#define CAN_F0R1_FB7 CAN_F0R1_FB7_Msk

Filter bit 7

◆ CAN_F0R1_FB7_Msk

#define CAN_F0R1_FB7_Msk (0x1UL << CAN_F0R1_FB7_Pos)

0x00000080

◆ CAN_F0R1_FB7_Pos

#define CAN_F0R1_FB7_Pos (7U)

◆ CAN_F0R1_FB8

#define CAN_F0R1_FB8 CAN_F0R1_FB8_Msk

Filter bit 8

◆ CAN_F0R1_FB8_Msk

#define CAN_F0R1_FB8_Msk (0x1UL << CAN_F0R1_FB8_Pos)

0x00000100

◆ CAN_F0R1_FB8_Pos

#define CAN_F0R1_FB8_Pos (8U)

◆ CAN_F0R1_FB9

#define CAN_F0R1_FB9 CAN_F0R1_FB9_Msk

Filter bit 9

◆ CAN_F0R1_FB9_Msk

#define CAN_F0R1_FB9_Msk (0x1UL << CAN_F0R1_FB9_Pos)

0x00000200

◆ CAN_F0R1_FB9_Pos

#define CAN_F0R1_FB9_Pos (9U)

◆ CAN_F0R2_FB0

#define CAN_F0R2_FB0 CAN_F0R2_FB0_Msk

Filter bit 0

◆ CAN_F0R2_FB0_Msk

#define CAN_F0R2_FB0_Msk (0x1UL << CAN_F0R2_FB0_Pos)

0x00000001

◆ CAN_F0R2_FB0_Pos

#define CAN_F0R2_FB0_Pos (0U)

◆ CAN_F0R2_FB1

#define CAN_F0R2_FB1 CAN_F0R2_FB1_Msk

Filter bit 1

◆ CAN_F0R2_FB10

#define CAN_F0R2_FB10 CAN_F0R2_FB10_Msk

Filter bit 10

◆ CAN_F0R2_FB10_Msk

#define CAN_F0R2_FB10_Msk (0x1UL << CAN_F0R2_FB10_Pos)

0x00000400

◆ CAN_F0R2_FB10_Pos

#define CAN_F0R2_FB10_Pos (10U)

◆ CAN_F0R2_FB11

#define CAN_F0R2_FB11 CAN_F0R2_FB11_Msk

Filter bit 11

◆ CAN_F0R2_FB11_Msk

#define CAN_F0R2_FB11_Msk (0x1UL << CAN_F0R2_FB11_Pos)

0x00000800

◆ CAN_F0R2_FB11_Pos

#define CAN_F0R2_FB11_Pos (11U)

◆ CAN_F0R2_FB12

#define CAN_F0R2_FB12 CAN_F0R2_FB12_Msk

Filter bit 12

◆ CAN_F0R2_FB12_Msk

#define CAN_F0R2_FB12_Msk (0x1UL << CAN_F0R2_FB12_Pos)

0x00001000

◆ CAN_F0R2_FB12_Pos

#define CAN_F0R2_FB12_Pos (12U)

◆ CAN_F0R2_FB13

#define CAN_F0R2_FB13 CAN_F0R2_FB13_Msk

Filter bit 13

◆ CAN_F0R2_FB13_Msk

#define CAN_F0R2_FB13_Msk (0x1UL << CAN_F0R2_FB13_Pos)

0x00002000

◆ CAN_F0R2_FB13_Pos

#define CAN_F0R2_FB13_Pos (13U)

◆ CAN_F0R2_FB14

#define CAN_F0R2_FB14 CAN_F0R2_FB14_Msk

Filter bit 14

◆ CAN_F0R2_FB14_Msk

#define CAN_F0R2_FB14_Msk (0x1UL << CAN_F0R2_FB14_Pos)

0x00004000

◆ CAN_F0R2_FB14_Pos

#define CAN_F0R2_FB14_Pos (14U)

◆ CAN_F0R2_FB15

#define CAN_F0R2_FB15 CAN_F0R2_FB15_Msk

Filter bit 15

◆ CAN_F0R2_FB15_Msk

#define CAN_F0R2_FB15_Msk (0x1UL << CAN_F0R2_FB15_Pos)

0x00008000

◆ CAN_F0R2_FB15_Pos

#define CAN_F0R2_FB15_Pos (15U)

◆ CAN_F0R2_FB16

#define CAN_F0R2_FB16 CAN_F0R2_FB16_Msk

Filter bit 16

◆ CAN_F0R2_FB16_Msk

#define CAN_F0R2_FB16_Msk (0x1UL << CAN_F0R2_FB16_Pos)

0x00010000

◆ CAN_F0R2_FB16_Pos

#define CAN_F0R2_FB16_Pos (16U)

◆ CAN_F0R2_FB17

#define CAN_F0R2_FB17 CAN_F0R2_FB17_Msk

Filter bit 17

◆ CAN_F0R2_FB17_Msk

#define CAN_F0R2_FB17_Msk (0x1UL << CAN_F0R2_FB17_Pos)

0x00020000

◆ CAN_F0R2_FB17_Pos

#define CAN_F0R2_FB17_Pos (17U)

◆ CAN_F0R2_FB18

#define CAN_F0R2_FB18 CAN_F0R2_FB18_Msk

Filter bit 18

◆ CAN_F0R2_FB18_Msk

#define CAN_F0R2_FB18_Msk (0x1UL << CAN_F0R2_FB18_Pos)

0x00040000

◆ CAN_F0R2_FB18_Pos

#define CAN_F0R2_FB18_Pos (18U)

◆ CAN_F0R2_FB19

#define CAN_F0R2_FB19 CAN_F0R2_FB19_Msk

Filter bit 19

◆ CAN_F0R2_FB19_Msk

#define CAN_F0R2_FB19_Msk (0x1UL << CAN_F0R2_FB19_Pos)

0x00080000

◆ CAN_F0R2_FB19_Pos

#define CAN_F0R2_FB19_Pos (19U)

◆ CAN_F0R2_FB1_Msk

#define CAN_F0R2_FB1_Msk (0x1UL << CAN_F0R2_FB1_Pos)

0x00000002

◆ CAN_F0R2_FB1_Pos

#define CAN_F0R2_FB1_Pos (1U)

◆ CAN_F0R2_FB2

#define CAN_F0R2_FB2 CAN_F0R2_FB2_Msk

Filter bit 2

◆ CAN_F0R2_FB20

#define CAN_F0R2_FB20 CAN_F0R2_FB20_Msk

Filter bit 20

◆ CAN_F0R2_FB20_Msk

#define CAN_F0R2_FB20_Msk (0x1UL << CAN_F0R2_FB20_Pos)

0x00100000

◆ CAN_F0R2_FB20_Pos

#define CAN_F0R2_FB20_Pos (20U)

◆ CAN_F0R2_FB21

#define CAN_F0R2_FB21 CAN_F0R2_FB21_Msk

Filter bit 21

◆ CAN_F0R2_FB21_Msk

#define CAN_F0R2_FB21_Msk (0x1UL << CAN_F0R2_FB21_Pos)

0x00200000

◆ CAN_F0R2_FB21_Pos

#define CAN_F0R2_FB21_Pos (21U)

◆ CAN_F0R2_FB22

#define CAN_F0R2_FB22 CAN_F0R2_FB22_Msk

Filter bit 22

◆ CAN_F0R2_FB22_Msk

#define CAN_F0R2_FB22_Msk (0x1UL << CAN_F0R2_FB22_Pos)

0x00400000

◆ CAN_F0R2_FB22_Pos

#define CAN_F0R2_FB22_Pos (22U)

◆ CAN_F0R2_FB23

#define CAN_F0R2_FB23 CAN_F0R2_FB23_Msk

Filter bit 23

◆ CAN_F0R2_FB23_Msk

#define CAN_F0R2_FB23_Msk (0x1UL << CAN_F0R2_FB23_Pos)

0x00800000

◆ CAN_F0R2_FB23_Pos

#define CAN_F0R2_FB23_Pos (23U)

◆ CAN_F0R2_FB24

#define CAN_F0R2_FB24 CAN_F0R2_FB24_Msk

Filter bit 24

◆ CAN_F0R2_FB24_Msk

#define CAN_F0R2_FB24_Msk (0x1UL << CAN_F0R2_FB24_Pos)

0x01000000

◆ CAN_F0R2_FB24_Pos

#define CAN_F0R2_FB24_Pos (24U)

◆ CAN_F0R2_FB25

#define CAN_F0R2_FB25 CAN_F0R2_FB25_Msk

Filter bit 25

◆ CAN_F0R2_FB25_Msk

#define CAN_F0R2_FB25_Msk (0x1UL << CAN_F0R2_FB25_Pos)

0x02000000

◆ CAN_F0R2_FB25_Pos

#define CAN_F0R2_FB25_Pos (25U)

◆ CAN_F0R2_FB26

#define CAN_F0R2_FB26 CAN_F0R2_FB26_Msk

Filter bit 26

◆ CAN_F0R2_FB26_Msk

#define CAN_F0R2_FB26_Msk (0x1UL << CAN_F0R2_FB26_Pos)

0x04000000

◆ CAN_F0R2_FB26_Pos

#define CAN_F0R2_FB26_Pos (26U)

◆ CAN_F0R2_FB27

#define CAN_F0R2_FB27 CAN_F0R2_FB27_Msk

Filter bit 27

◆ CAN_F0R2_FB27_Msk

#define CAN_F0R2_FB27_Msk (0x1UL << CAN_F0R2_FB27_Pos)

0x08000000

◆ CAN_F0R2_FB27_Pos

#define CAN_F0R2_FB27_Pos (27U)

◆ CAN_F0R2_FB28

#define CAN_F0R2_FB28 CAN_F0R2_FB28_Msk

Filter bit 28

◆ CAN_F0R2_FB28_Msk

#define CAN_F0R2_FB28_Msk (0x1UL << CAN_F0R2_FB28_Pos)

0x10000000

◆ CAN_F0R2_FB28_Pos

#define CAN_F0R2_FB28_Pos (28U)

◆ CAN_F0R2_FB29

#define CAN_F0R2_FB29 CAN_F0R2_FB29_Msk

Filter bit 29

◆ CAN_F0R2_FB29_Msk

#define CAN_F0R2_FB29_Msk (0x1UL << CAN_F0R2_FB29_Pos)

0x20000000

◆ CAN_F0R2_FB29_Pos

#define CAN_F0R2_FB29_Pos (29U)

◆ CAN_F0R2_FB2_Msk

#define CAN_F0R2_FB2_Msk (0x1UL << CAN_F0R2_FB2_Pos)

0x00000004

◆ CAN_F0R2_FB2_Pos

#define CAN_F0R2_FB2_Pos (2U)

◆ CAN_F0R2_FB3

#define CAN_F0R2_FB3 CAN_F0R2_FB3_Msk

Filter bit 3

◆ CAN_F0R2_FB30

#define CAN_F0R2_FB30 CAN_F0R2_FB30_Msk

Filter bit 30

◆ CAN_F0R2_FB30_Msk

#define CAN_F0R2_FB30_Msk (0x1UL << CAN_F0R2_FB30_Pos)

0x40000000

◆ CAN_F0R2_FB30_Pos

#define CAN_F0R2_FB30_Pos (30U)

◆ CAN_F0R2_FB31

#define CAN_F0R2_FB31 CAN_F0R2_FB31_Msk

Filter bit 31

◆ CAN_F0R2_FB31_Msk

#define CAN_F0R2_FB31_Msk (0x1UL << CAN_F0R2_FB31_Pos)

0x80000000

◆ CAN_F0R2_FB31_Pos

#define CAN_F0R2_FB31_Pos (31U)

◆ CAN_F0R2_FB3_Msk

#define CAN_F0R2_FB3_Msk (0x1UL << CAN_F0R2_FB3_Pos)

0x00000008

◆ CAN_F0R2_FB3_Pos

#define CAN_F0R2_FB3_Pos (3U)

◆ CAN_F0R2_FB4

#define CAN_F0R2_FB4 CAN_F0R2_FB4_Msk

Filter bit 4

◆ CAN_F0R2_FB4_Msk

#define CAN_F0R2_FB4_Msk (0x1UL << CAN_F0R2_FB4_Pos)

0x00000010

◆ CAN_F0R2_FB4_Pos

#define CAN_F0R2_FB4_Pos (4U)

◆ CAN_F0R2_FB5

#define CAN_F0R2_FB5 CAN_F0R2_FB5_Msk

Filter bit 5

◆ CAN_F0R2_FB5_Msk

#define CAN_F0R2_FB5_Msk (0x1UL << CAN_F0R2_FB5_Pos)

0x00000020

◆ CAN_F0R2_FB5_Pos

#define CAN_F0R2_FB5_Pos (5U)

◆ CAN_F0R2_FB6

#define CAN_F0R2_FB6 CAN_F0R2_FB6_Msk

Filter bit 6

◆ CAN_F0R2_FB6_Msk

#define CAN_F0R2_FB6_Msk (0x1UL << CAN_F0R2_FB6_Pos)

0x00000040

◆ CAN_F0R2_FB6_Pos

#define CAN_F0R2_FB6_Pos (6U)

◆ CAN_F0R2_FB7

#define CAN_F0R2_FB7 CAN_F0R2_FB7_Msk

Filter bit 7

◆ CAN_F0R2_FB7_Msk

#define CAN_F0R2_FB7_Msk (0x1UL << CAN_F0R2_FB7_Pos)

0x00000080

◆ CAN_F0R2_FB7_Pos

#define CAN_F0R2_FB7_Pos (7U)

◆ CAN_F0R2_FB8

#define CAN_F0R2_FB8 CAN_F0R2_FB8_Msk

Filter bit 8

◆ CAN_F0R2_FB8_Msk

#define CAN_F0R2_FB8_Msk (0x1UL << CAN_F0R2_FB8_Pos)

0x00000100

◆ CAN_F0R2_FB8_Pos

#define CAN_F0R2_FB8_Pos (8U)

◆ CAN_F0R2_FB9

#define CAN_F0R2_FB9 CAN_F0R2_FB9_Msk

Filter bit 9

◆ CAN_F0R2_FB9_Msk

#define CAN_F0R2_FB9_Msk (0x1UL << CAN_F0R2_FB9_Pos)

0x00000200

◆ CAN_F0R2_FB9_Pos

#define CAN_F0R2_FB9_Pos (9U)

◆ CAN_F10R1_FB0

#define CAN_F10R1_FB0 CAN_F10R1_FB0_Msk

Filter bit 0

◆ CAN_F10R1_FB0_Msk

#define CAN_F10R1_FB0_Msk (0x1UL << CAN_F10R1_FB0_Pos)

0x00000001

◆ CAN_F10R1_FB0_Pos

#define CAN_F10R1_FB0_Pos (0U)

◆ CAN_F10R1_FB1

#define CAN_F10R1_FB1 CAN_F10R1_FB1_Msk

Filter bit 1

◆ CAN_F10R1_FB10

#define CAN_F10R1_FB10 CAN_F10R1_FB10_Msk

Filter bit 10

◆ CAN_F10R1_FB10_Msk

#define CAN_F10R1_FB10_Msk (0x1UL << CAN_F10R1_FB10_Pos)

0x00000400

◆ CAN_F10R1_FB10_Pos

#define CAN_F10R1_FB10_Pos (10U)

◆ CAN_F10R1_FB11

#define CAN_F10R1_FB11 CAN_F10R1_FB11_Msk

Filter bit 11

◆ CAN_F10R1_FB11_Msk

#define CAN_F10R1_FB11_Msk (0x1UL << CAN_F10R1_FB11_Pos)

0x00000800

◆ CAN_F10R1_FB11_Pos

#define CAN_F10R1_FB11_Pos (11U)

◆ CAN_F10R1_FB12

#define CAN_F10R1_FB12 CAN_F10R1_FB12_Msk

Filter bit 12

◆ CAN_F10R1_FB12_Msk

#define CAN_F10R1_FB12_Msk (0x1UL << CAN_F10R1_FB12_Pos)

0x00001000

◆ CAN_F10R1_FB12_Pos

#define CAN_F10R1_FB12_Pos (12U)

◆ CAN_F10R1_FB13

#define CAN_F10R1_FB13 CAN_F10R1_FB13_Msk

Filter bit 13

◆ CAN_F10R1_FB13_Msk

#define CAN_F10R1_FB13_Msk (0x1UL << CAN_F10R1_FB13_Pos)

0x00002000

◆ CAN_F10R1_FB13_Pos

#define CAN_F10R1_FB13_Pos (13U)

◆ CAN_F10R1_FB14

#define CAN_F10R1_FB14 CAN_F10R1_FB14_Msk

Filter bit 14

◆ CAN_F10R1_FB14_Msk

#define CAN_F10R1_FB14_Msk (0x1UL << CAN_F10R1_FB14_Pos)

0x00004000

◆ CAN_F10R1_FB14_Pos

#define CAN_F10R1_FB14_Pos (14U)

◆ CAN_F10R1_FB15

#define CAN_F10R1_FB15 CAN_F10R1_FB15_Msk

Filter bit 15

◆ CAN_F10R1_FB15_Msk

#define CAN_F10R1_FB15_Msk (0x1UL << CAN_F10R1_FB15_Pos)

0x00008000

◆ CAN_F10R1_FB15_Pos

#define CAN_F10R1_FB15_Pos (15U)

◆ CAN_F10R1_FB16

#define CAN_F10R1_FB16 CAN_F10R1_FB16_Msk

Filter bit 16

◆ CAN_F10R1_FB16_Msk

#define CAN_F10R1_FB16_Msk (0x1UL << CAN_F10R1_FB16_Pos)

0x00010000

◆ CAN_F10R1_FB16_Pos

#define CAN_F10R1_FB16_Pos (16U)

◆ CAN_F10R1_FB17

#define CAN_F10R1_FB17 CAN_F10R1_FB17_Msk

Filter bit 17

◆ CAN_F10R1_FB17_Msk

#define CAN_F10R1_FB17_Msk (0x1UL << CAN_F10R1_FB17_Pos)

0x00020000

◆ CAN_F10R1_FB17_Pos

#define CAN_F10R1_FB17_Pos (17U)

◆ CAN_F10R1_FB18

#define CAN_F10R1_FB18 CAN_F10R1_FB18_Msk

Filter bit 18

◆ CAN_F10R1_FB18_Msk

#define CAN_F10R1_FB18_Msk (0x1UL << CAN_F10R1_FB18_Pos)

0x00040000

◆ CAN_F10R1_FB18_Pos

#define CAN_F10R1_FB18_Pos (18U)

◆ CAN_F10R1_FB19

#define CAN_F10R1_FB19 CAN_F10R1_FB19_Msk

Filter bit 19

◆ CAN_F10R1_FB19_Msk

#define CAN_F10R1_FB19_Msk (0x1UL << CAN_F10R1_FB19_Pos)

0x00080000

◆ CAN_F10R1_FB19_Pos

#define CAN_F10R1_FB19_Pos (19U)

◆ CAN_F10R1_FB1_Msk

#define CAN_F10R1_FB1_Msk (0x1UL << CAN_F10R1_FB1_Pos)

0x00000002

◆ CAN_F10R1_FB1_Pos

#define CAN_F10R1_FB1_Pos (1U)

◆ CAN_F10R1_FB2

#define CAN_F10R1_FB2 CAN_F10R1_FB2_Msk

Filter bit 2

◆ CAN_F10R1_FB20

#define CAN_F10R1_FB20 CAN_F10R1_FB20_Msk

Filter bit 20

◆ CAN_F10R1_FB20_Msk

#define CAN_F10R1_FB20_Msk (0x1UL << CAN_F10R1_FB20_Pos)

0x00100000

◆ CAN_F10R1_FB20_Pos

#define CAN_F10R1_FB20_Pos (20U)

◆ CAN_F10R1_FB21

#define CAN_F10R1_FB21 CAN_F10R1_FB21_Msk

Filter bit 21

◆ CAN_F10R1_FB21_Msk

#define CAN_F10R1_FB21_Msk (0x1UL << CAN_F10R1_FB21_Pos)

0x00200000

◆ CAN_F10R1_FB21_Pos

#define CAN_F10R1_FB21_Pos (21U)

◆ CAN_F10R1_FB22

#define CAN_F10R1_FB22 CAN_F10R1_FB22_Msk

Filter bit 22

◆ CAN_F10R1_FB22_Msk

#define CAN_F10R1_FB22_Msk (0x1UL << CAN_F10R1_FB22_Pos)

0x00400000

◆ CAN_F10R1_FB22_Pos

#define CAN_F10R1_FB22_Pos (22U)

◆ CAN_F10R1_FB23

#define CAN_F10R1_FB23 CAN_F10R1_FB23_Msk

Filter bit 23

◆ CAN_F10R1_FB23_Msk

#define CAN_F10R1_FB23_Msk (0x1UL << CAN_F10R1_FB23_Pos)

0x00800000

◆ CAN_F10R1_FB23_Pos

#define CAN_F10R1_FB23_Pos (23U)

◆ CAN_F10R1_FB24

#define CAN_F10R1_FB24 CAN_F10R1_FB24_Msk

Filter bit 24

◆ CAN_F10R1_FB24_Msk

#define CAN_F10R1_FB24_Msk (0x1UL << CAN_F10R1_FB24_Pos)

0x01000000

◆ CAN_F10R1_FB24_Pos

#define CAN_F10R1_FB24_Pos (24U)

◆ CAN_F10R1_FB25

#define CAN_F10R1_FB25 CAN_F10R1_FB25_Msk

Filter bit 25

◆ CAN_F10R1_FB25_Msk

#define CAN_F10R1_FB25_Msk (0x1UL << CAN_F10R1_FB25_Pos)

0x02000000

◆ CAN_F10R1_FB25_Pos

#define CAN_F10R1_FB25_Pos (25U)

◆ CAN_F10R1_FB26

#define CAN_F10R1_FB26 CAN_F10R1_FB26_Msk

Filter bit 26

◆ CAN_F10R1_FB26_Msk

#define CAN_F10R1_FB26_Msk (0x1UL << CAN_F10R1_FB26_Pos)

0x04000000

◆ CAN_F10R1_FB26_Pos

#define CAN_F10R1_FB26_Pos (26U)

◆ CAN_F10R1_FB27

#define CAN_F10R1_FB27 CAN_F10R1_FB27_Msk

Filter bit 27

◆ CAN_F10R1_FB27_Msk

#define CAN_F10R1_FB27_Msk (0x1UL << CAN_F10R1_FB27_Pos)

0x08000000

◆ CAN_F10R1_FB27_Pos

#define CAN_F10R1_FB27_Pos (27U)

◆ CAN_F10R1_FB28

#define CAN_F10R1_FB28 CAN_F10R1_FB28_Msk

Filter bit 28

◆ CAN_F10R1_FB28_Msk

#define CAN_F10R1_FB28_Msk (0x1UL << CAN_F10R1_FB28_Pos)

0x10000000

◆ CAN_F10R1_FB28_Pos

#define CAN_F10R1_FB28_Pos (28U)

◆ CAN_F10R1_FB29

#define CAN_F10R1_FB29 CAN_F10R1_FB29_Msk

Filter bit 29

◆ CAN_F10R1_FB29_Msk

#define CAN_F10R1_FB29_Msk (0x1UL << CAN_F10R1_FB29_Pos)

0x20000000

◆ CAN_F10R1_FB29_Pos

#define CAN_F10R1_FB29_Pos (29U)

◆ CAN_F10R1_FB2_Msk

#define CAN_F10R1_FB2_Msk (0x1UL << CAN_F10R1_FB2_Pos)

0x00000004

◆ CAN_F10R1_FB2_Pos

#define CAN_F10R1_FB2_Pos (2U)

◆ CAN_F10R1_FB3

#define CAN_F10R1_FB3 CAN_F10R1_FB3_Msk

Filter bit 3

◆ CAN_F10R1_FB30

#define CAN_F10R1_FB30 CAN_F10R1_FB30_Msk

Filter bit 30

◆ CAN_F10R1_FB30_Msk

#define CAN_F10R1_FB30_Msk (0x1UL << CAN_F10R1_FB30_Pos)

0x40000000

◆ CAN_F10R1_FB30_Pos

#define CAN_F10R1_FB30_Pos (30U)

◆ CAN_F10R1_FB31

#define CAN_F10R1_FB31 CAN_F10R1_FB31_Msk

Filter bit 31

◆ CAN_F10R1_FB31_Msk

#define CAN_F10R1_FB31_Msk (0x1UL << CAN_F10R1_FB31_Pos)

0x80000000

◆ CAN_F10R1_FB31_Pos

#define CAN_F10R1_FB31_Pos (31U)

◆ CAN_F10R1_FB3_Msk

#define CAN_F10R1_FB3_Msk (0x1UL << CAN_F10R1_FB3_Pos)

0x00000008

◆ CAN_F10R1_FB3_Pos

#define CAN_F10R1_FB3_Pos (3U)

◆ CAN_F10R1_FB4

#define CAN_F10R1_FB4 CAN_F10R1_FB4_Msk

Filter bit 4

◆ CAN_F10R1_FB4_Msk

#define CAN_F10R1_FB4_Msk (0x1UL << CAN_F10R1_FB4_Pos)

0x00000010

◆ CAN_F10R1_FB4_Pos

#define CAN_F10R1_FB4_Pos (4U)

◆ CAN_F10R1_FB5

#define CAN_F10R1_FB5 CAN_F10R1_FB5_Msk

Filter bit 5

◆ CAN_F10R1_FB5_Msk

#define CAN_F10R1_FB5_Msk (0x1UL << CAN_F10R1_FB5_Pos)

0x00000020

◆ CAN_F10R1_FB5_Pos

#define CAN_F10R1_FB5_Pos (5U)

◆ CAN_F10R1_FB6

#define CAN_F10R1_FB6 CAN_F10R1_FB6_Msk

Filter bit 6

◆ CAN_F10R1_FB6_Msk

#define CAN_F10R1_FB6_Msk (0x1UL << CAN_F10R1_FB6_Pos)

0x00000040

◆ CAN_F10R1_FB6_Pos

#define CAN_F10R1_FB6_Pos (6U)

◆ CAN_F10R1_FB7

#define CAN_F10R1_FB7 CAN_F10R1_FB7_Msk

Filter bit 7

◆ CAN_F10R1_FB7_Msk

#define CAN_F10R1_FB7_Msk (0x1UL << CAN_F10R1_FB7_Pos)

0x00000080

◆ CAN_F10R1_FB7_Pos

#define CAN_F10R1_FB7_Pos (7U)

◆ CAN_F10R1_FB8

#define CAN_F10R1_FB8 CAN_F10R1_FB8_Msk

Filter bit 8

◆ CAN_F10R1_FB8_Msk

#define CAN_F10R1_FB8_Msk (0x1UL << CAN_F10R1_FB8_Pos)

0x00000100

◆ CAN_F10R1_FB8_Pos

#define CAN_F10R1_FB8_Pos (8U)

◆ CAN_F10R1_FB9

#define CAN_F10R1_FB9 CAN_F10R1_FB9_Msk

Filter bit 9

◆ CAN_F10R1_FB9_Msk

#define CAN_F10R1_FB9_Msk (0x1UL << CAN_F10R1_FB9_Pos)

0x00000200

◆ CAN_F10R1_FB9_Pos

#define CAN_F10R1_FB9_Pos (9U)

◆ CAN_F10R2_FB0

#define CAN_F10R2_FB0 CAN_F10R2_FB0_Msk

Filter bit 0

◆ CAN_F10R2_FB0_Msk

#define CAN_F10R2_FB0_Msk (0x1UL << CAN_F10R2_FB0_Pos)

0x00000001

◆ CAN_F10R2_FB0_Pos

#define CAN_F10R2_FB0_Pos (0U)

◆ CAN_F10R2_FB1

#define CAN_F10R2_FB1 CAN_F10R2_FB1_Msk

Filter bit 1

◆ CAN_F10R2_FB10

#define CAN_F10R2_FB10 CAN_F10R2_FB10_Msk

Filter bit 10

◆ CAN_F10R2_FB10_Msk

#define CAN_F10R2_FB10_Msk (0x1UL << CAN_F10R2_FB10_Pos)

0x00000400

◆ CAN_F10R2_FB10_Pos

#define CAN_F10R2_FB10_Pos (10U)

◆ CAN_F10R2_FB11

#define CAN_F10R2_FB11 CAN_F10R2_FB11_Msk

Filter bit 11

◆ CAN_F10R2_FB11_Msk

#define CAN_F10R2_FB11_Msk (0x1UL << CAN_F10R2_FB11_Pos)

0x00000800

◆ CAN_F10R2_FB11_Pos

#define CAN_F10R2_FB11_Pos (11U)

◆ CAN_F10R2_FB12

#define CAN_F10R2_FB12 CAN_F10R2_FB12_Msk

Filter bit 12

◆ CAN_F10R2_FB12_Msk

#define CAN_F10R2_FB12_Msk (0x1UL << CAN_F10R2_FB12_Pos)

0x00001000

◆ CAN_F10R2_FB12_Pos

#define CAN_F10R2_FB12_Pos (12U)

◆ CAN_F10R2_FB13

#define CAN_F10R2_FB13 CAN_F10R2_FB13_Msk

Filter bit 13

◆ CAN_F10R2_FB13_Msk

#define CAN_F10R2_FB13_Msk (0x1UL << CAN_F10R2_FB13_Pos)

0x00002000

◆ CAN_F10R2_FB13_Pos

#define CAN_F10R2_FB13_Pos (13U)

◆ CAN_F10R2_FB14

#define CAN_F10R2_FB14 CAN_F10R2_FB14_Msk

Filter bit 14

◆ CAN_F10R2_FB14_Msk

#define CAN_F10R2_FB14_Msk (0x1UL << CAN_F10R2_FB14_Pos)

0x00004000

◆ CAN_F10R2_FB14_Pos

#define CAN_F10R2_FB14_Pos (14U)

◆ CAN_F10R2_FB15

#define CAN_F10R2_FB15 CAN_F10R2_FB15_Msk

Filter bit 15

◆ CAN_F10R2_FB15_Msk

#define CAN_F10R2_FB15_Msk (0x1UL << CAN_F10R2_FB15_Pos)

0x00008000

◆ CAN_F10R2_FB15_Pos

#define CAN_F10R2_FB15_Pos (15U)

◆ CAN_F10R2_FB16

#define CAN_F10R2_FB16 CAN_F10R2_FB16_Msk

Filter bit 16

◆ CAN_F10R2_FB16_Msk

#define CAN_F10R2_FB16_Msk (0x1UL << CAN_F10R2_FB16_Pos)

0x00010000

◆ CAN_F10R2_FB16_Pos

#define CAN_F10R2_FB16_Pos (16U)

◆ CAN_F10R2_FB17

#define CAN_F10R2_FB17 CAN_F10R2_FB17_Msk

Filter bit 17

◆ CAN_F10R2_FB17_Msk

#define CAN_F10R2_FB17_Msk (0x1UL << CAN_F10R2_FB17_Pos)

0x00020000

◆ CAN_F10R2_FB17_Pos

#define CAN_F10R2_FB17_Pos (17U)

◆ CAN_F10R2_FB18

#define CAN_F10R2_FB18 CAN_F10R2_FB18_Msk

Filter bit 18

◆ CAN_F10R2_FB18_Msk

#define CAN_F10R2_FB18_Msk (0x1UL << CAN_F10R2_FB18_Pos)

0x00040000

◆ CAN_F10R2_FB18_Pos

#define CAN_F10R2_FB18_Pos (18U)

◆ CAN_F10R2_FB19

#define CAN_F10R2_FB19 CAN_F10R2_FB19_Msk

Filter bit 19

◆ CAN_F10R2_FB19_Msk

#define CAN_F10R2_FB19_Msk (0x1UL << CAN_F10R2_FB19_Pos)

0x00080000

◆ CAN_F10R2_FB19_Pos

#define CAN_F10R2_FB19_Pos (19U)

◆ CAN_F10R2_FB1_Msk

#define CAN_F10R2_FB1_Msk (0x1UL << CAN_F10R2_FB1_Pos)

0x00000002

◆ CAN_F10R2_FB1_Pos

#define CAN_F10R2_FB1_Pos (1U)

◆ CAN_F10R2_FB2

#define CAN_F10R2_FB2 CAN_F10R2_FB2_Msk

Filter bit 2

◆ CAN_F10R2_FB20

#define CAN_F10R2_FB20 CAN_F10R2_FB20_Msk

Filter bit 20

◆ CAN_F10R2_FB20_Msk

#define CAN_F10R2_FB20_Msk (0x1UL << CAN_F10R2_FB20_Pos)

0x00100000

◆ CAN_F10R2_FB20_Pos

#define CAN_F10R2_FB20_Pos (20U)

◆ CAN_F10R2_FB21

#define CAN_F10R2_FB21 CAN_F10R2_FB21_Msk

Filter bit 21

◆ CAN_F10R2_FB21_Msk

#define CAN_F10R2_FB21_Msk (0x1UL << CAN_F10R2_FB21_Pos)

0x00200000

◆ CAN_F10R2_FB21_Pos

#define CAN_F10R2_FB21_Pos (21U)

◆ CAN_F10R2_FB22

#define CAN_F10R2_FB22 CAN_F10R2_FB22_Msk

Filter bit 22

◆ CAN_F10R2_FB22_Msk

#define CAN_F10R2_FB22_Msk (0x1UL << CAN_F10R2_FB22_Pos)

0x00400000

◆ CAN_F10R2_FB22_Pos

#define CAN_F10R2_FB22_Pos (22U)

◆ CAN_F10R2_FB23

#define CAN_F10R2_FB23 CAN_F10R2_FB23_Msk

Filter bit 23

◆ CAN_F10R2_FB23_Msk

#define CAN_F10R2_FB23_Msk (0x1UL << CAN_F10R2_FB23_Pos)

0x00800000

◆ CAN_F10R2_FB23_Pos

#define CAN_F10R2_FB23_Pos (23U)

◆ CAN_F10R2_FB24

#define CAN_F10R2_FB24 CAN_F10R2_FB24_Msk

Filter bit 24

◆ CAN_F10R2_FB24_Msk

#define CAN_F10R2_FB24_Msk (0x1UL << CAN_F10R2_FB24_Pos)

0x01000000

◆ CAN_F10R2_FB24_Pos

#define CAN_F10R2_FB24_Pos (24U)

◆ CAN_F10R2_FB25

#define CAN_F10R2_FB25 CAN_F10R2_FB25_Msk

Filter bit 25

◆ CAN_F10R2_FB25_Msk

#define CAN_F10R2_FB25_Msk (0x1UL << CAN_F10R2_FB25_Pos)

0x02000000

◆ CAN_F10R2_FB25_Pos

#define CAN_F10R2_FB25_Pos (25U)

◆ CAN_F10R2_FB26

#define CAN_F10R2_FB26 CAN_F10R2_FB26_Msk

Filter bit 26

◆ CAN_F10R2_FB26_Msk

#define CAN_F10R2_FB26_Msk (0x1UL << CAN_F10R2_FB26_Pos)

0x04000000

◆ CAN_F10R2_FB26_Pos

#define CAN_F10R2_FB26_Pos (26U)

◆ CAN_F10R2_FB27

#define CAN_F10R2_FB27 CAN_F10R2_FB27_Msk

Filter bit 27

◆ CAN_F10R2_FB27_Msk

#define CAN_F10R2_FB27_Msk (0x1UL << CAN_F10R2_FB27_Pos)

0x08000000

◆ CAN_F10R2_FB27_Pos

#define CAN_F10R2_FB27_Pos (27U)

◆ CAN_F10R2_FB28

#define CAN_F10R2_FB28 CAN_F10R2_FB28_Msk

Filter bit 28

◆ CAN_F10R2_FB28_Msk

#define CAN_F10R2_FB28_Msk (0x1UL << CAN_F10R2_FB28_Pos)

0x10000000

◆ CAN_F10R2_FB28_Pos

#define CAN_F10R2_FB28_Pos (28U)

◆ CAN_F10R2_FB29

#define CAN_F10R2_FB29 CAN_F10R2_FB29_Msk

Filter bit 29

◆ CAN_F10R2_FB29_Msk

#define CAN_F10R2_FB29_Msk (0x1UL << CAN_F10R2_FB29_Pos)

0x20000000

◆ CAN_F10R2_FB29_Pos

#define CAN_F10R2_FB29_Pos (29U)

◆ CAN_F10R2_FB2_Msk

#define CAN_F10R2_FB2_Msk (0x1UL << CAN_F10R2_FB2_Pos)

0x00000004

◆ CAN_F10R2_FB2_Pos

#define CAN_F10R2_FB2_Pos (2U)

◆ CAN_F10R2_FB3

#define CAN_F10R2_FB3 CAN_F10R2_FB3_Msk

Filter bit 3

◆ CAN_F10R2_FB30

#define CAN_F10R2_FB30 CAN_F10R2_FB30_Msk

Filter bit 30

◆ CAN_F10R2_FB30_Msk

#define CAN_F10R2_FB30_Msk (0x1UL << CAN_F10R2_FB30_Pos)

0x40000000

◆ CAN_F10R2_FB30_Pos

#define CAN_F10R2_FB30_Pos (30U)

◆ CAN_F10R2_FB31

#define CAN_F10R2_FB31 CAN_F10R2_FB31_Msk

Filter bit 31

◆ CAN_F10R2_FB31_Msk

#define CAN_F10R2_FB31_Msk (0x1UL << CAN_F10R2_FB31_Pos)

0x80000000

◆ CAN_F10R2_FB31_Pos

#define CAN_F10R2_FB31_Pos (31U)

◆ CAN_F10R2_FB3_Msk

#define CAN_F10R2_FB3_Msk (0x1UL << CAN_F10R2_FB3_Pos)

0x00000008

◆ CAN_F10R2_FB3_Pos

#define CAN_F10R2_FB3_Pos (3U)

◆ CAN_F10R2_FB4

#define CAN_F10R2_FB4 CAN_F10R2_FB4_Msk

Filter bit 4

◆ CAN_F10R2_FB4_Msk

#define CAN_F10R2_FB4_Msk (0x1UL << CAN_F10R2_FB4_Pos)

0x00000010

◆ CAN_F10R2_FB4_Pos

#define CAN_F10R2_FB4_Pos (4U)

◆ CAN_F10R2_FB5

#define CAN_F10R2_FB5 CAN_F10R2_FB5_Msk

Filter bit 5

◆ CAN_F10R2_FB5_Msk

#define CAN_F10R2_FB5_Msk (0x1UL << CAN_F10R2_FB5_Pos)

0x00000020

◆ CAN_F10R2_FB5_Pos

#define CAN_F10R2_FB5_Pos (5U)

◆ CAN_F10R2_FB6

#define CAN_F10R2_FB6 CAN_F10R2_FB6_Msk

Filter bit 6

◆ CAN_F10R2_FB6_Msk

#define CAN_F10R2_FB6_Msk (0x1UL << CAN_F10R2_FB6_Pos)

0x00000040

◆ CAN_F10R2_FB6_Pos

#define CAN_F10R2_FB6_Pos (6U)

◆ CAN_F10R2_FB7

#define CAN_F10R2_FB7 CAN_F10R2_FB7_Msk

Filter bit 7

◆ CAN_F10R2_FB7_Msk

#define CAN_F10R2_FB7_Msk (0x1UL << CAN_F10R2_FB7_Pos)

0x00000080

◆ CAN_F10R2_FB7_Pos

#define CAN_F10R2_FB7_Pos (7U)

◆ CAN_F10R2_FB8

#define CAN_F10R2_FB8 CAN_F10R2_FB8_Msk

Filter bit 8

◆ CAN_F10R2_FB8_Msk

#define CAN_F10R2_FB8_Msk (0x1UL << CAN_F10R2_FB8_Pos)

0x00000100

◆ CAN_F10R2_FB8_Pos

#define CAN_F10R2_FB8_Pos (8U)

◆ CAN_F10R2_FB9

#define CAN_F10R2_FB9 CAN_F10R2_FB9_Msk

Filter bit 9

◆ CAN_F10R2_FB9_Msk

#define CAN_F10R2_FB9_Msk (0x1UL << CAN_F10R2_FB9_Pos)

0x00000200

◆ CAN_F10R2_FB9_Pos

#define CAN_F10R2_FB9_Pos (9U)

◆ CAN_F11R1_FB0

#define CAN_F11R1_FB0 CAN_F11R1_FB0_Msk

Filter bit 0

◆ CAN_F11R1_FB0_Msk

#define CAN_F11R1_FB0_Msk (0x1UL << CAN_F11R1_FB0_Pos)

0x00000001

◆ CAN_F11R1_FB0_Pos

#define CAN_F11R1_FB0_Pos (0U)

◆ CAN_F11R1_FB1

#define CAN_F11R1_FB1 CAN_F11R1_FB1_Msk

Filter bit 1

◆ CAN_F11R1_FB10

#define CAN_F11R1_FB10 CAN_F11R1_FB10_Msk

Filter bit 10

◆ CAN_F11R1_FB10_Msk

#define CAN_F11R1_FB10_Msk (0x1UL << CAN_F11R1_FB10_Pos)

0x00000400

◆ CAN_F11R1_FB10_Pos

#define CAN_F11R1_FB10_Pos (10U)

◆ CAN_F11R1_FB11

#define CAN_F11R1_FB11 CAN_F11R1_FB11_Msk

Filter bit 11

◆ CAN_F11R1_FB11_Msk

#define CAN_F11R1_FB11_Msk (0x1UL << CAN_F11R1_FB11_Pos)

0x00000800

◆ CAN_F11R1_FB11_Pos

#define CAN_F11R1_FB11_Pos (11U)

◆ CAN_F11R1_FB12

#define CAN_F11R1_FB12 CAN_F11R1_FB12_Msk

Filter bit 12

◆ CAN_F11R1_FB12_Msk

#define CAN_F11R1_FB12_Msk (0x1UL << CAN_F11R1_FB12_Pos)

0x00001000

◆ CAN_F11R1_FB12_Pos

#define CAN_F11R1_FB12_Pos (12U)

◆ CAN_F11R1_FB13

#define CAN_F11R1_FB13 CAN_F11R1_FB13_Msk

Filter bit 13

◆ CAN_F11R1_FB13_Msk

#define CAN_F11R1_FB13_Msk (0x1UL << CAN_F11R1_FB13_Pos)

0x00002000

◆ CAN_F11R1_FB13_Pos

#define CAN_F11R1_FB13_Pos (13U)

◆ CAN_F11R1_FB14

#define CAN_F11R1_FB14 CAN_F11R1_FB14_Msk

Filter bit 14

◆ CAN_F11R1_FB14_Msk

#define CAN_F11R1_FB14_Msk (0x1UL << CAN_F11R1_FB14_Pos)

0x00004000

◆ CAN_F11R1_FB14_Pos

#define CAN_F11R1_FB14_Pos (14U)

◆ CAN_F11R1_FB15

#define CAN_F11R1_FB15 CAN_F11R1_FB15_Msk

Filter bit 15

◆ CAN_F11R1_FB15_Msk

#define CAN_F11R1_FB15_Msk (0x1UL << CAN_F11R1_FB15_Pos)

0x00008000

◆ CAN_F11R1_FB15_Pos

#define CAN_F11R1_FB15_Pos (15U)

◆ CAN_F11R1_FB16

#define CAN_F11R1_FB16 CAN_F11R1_FB16_Msk

Filter bit 16

◆ CAN_F11R1_FB16_Msk

#define CAN_F11R1_FB16_Msk (0x1UL << CAN_F11R1_FB16_Pos)

0x00010000

◆ CAN_F11R1_FB16_Pos

#define CAN_F11R1_FB16_Pos (16U)

◆ CAN_F11R1_FB17

#define CAN_F11R1_FB17 CAN_F11R1_FB17_Msk

Filter bit 17

◆ CAN_F11R1_FB17_Msk

#define CAN_F11R1_FB17_Msk (0x1UL << CAN_F11R1_FB17_Pos)

0x00020000

◆ CAN_F11R1_FB17_Pos

#define CAN_F11R1_FB17_Pos (17U)

◆ CAN_F11R1_FB18

#define CAN_F11R1_FB18 CAN_F11R1_FB18_Msk

Filter bit 18

◆ CAN_F11R1_FB18_Msk

#define CAN_F11R1_FB18_Msk (0x1UL << CAN_F11R1_FB18_Pos)

0x00040000

◆ CAN_F11R1_FB18_Pos

#define CAN_F11R1_FB18_Pos (18U)

◆ CAN_F11R1_FB19

#define CAN_F11R1_FB19 CAN_F11R1_FB19_Msk

Filter bit 19

◆ CAN_F11R1_FB19_Msk

#define CAN_F11R1_FB19_Msk (0x1UL << CAN_F11R1_FB19_Pos)

0x00080000

◆ CAN_F11R1_FB19_Pos

#define CAN_F11R1_FB19_Pos (19U)

◆ CAN_F11R1_FB1_Msk

#define CAN_F11R1_FB1_Msk (0x1UL << CAN_F11R1_FB1_Pos)

0x00000002

◆ CAN_F11R1_FB1_Pos

#define CAN_F11R1_FB1_Pos (1U)

◆ CAN_F11R1_FB2

#define CAN_F11R1_FB2 CAN_F11R1_FB2_Msk

Filter bit 2

◆ CAN_F11R1_FB20

#define CAN_F11R1_FB20 CAN_F11R1_FB20_Msk

Filter bit 20

◆ CAN_F11R1_FB20_Msk

#define CAN_F11R1_FB20_Msk (0x1UL << CAN_F11R1_FB20_Pos)

0x00100000

◆ CAN_F11R1_FB20_Pos

#define CAN_F11R1_FB20_Pos (20U)

◆ CAN_F11R1_FB21

#define CAN_F11R1_FB21 CAN_F11R1_FB21_Msk

Filter bit 21

◆ CAN_F11R1_FB21_Msk

#define CAN_F11R1_FB21_Msk (0x1UL << CAN_F11R1_FB21_Pos)

0x00200000

◆ CAN_F11R1_FB21_Pos

#define CAN_F11R1_FB21_Pos (21U)

◆ CAN_F11R1_FB22

#define CAN_F11R1_FB22 CAN_F11R1_FB22_Msk

Filter bit 22

◆ CAN_F11R1_FB22_Msk

#define CAN_F11R1_FB22_Msk (0x1UL << CAN_F11R1_FB22_Pos)

0x00400000

◆ CAN_F11R1_FB22_Pos

#define CAN_F11R1_FB22_Pos (22U)

◆ CAN_F11R1_FB23

#define CAN_F11R1_FB23 CAN_F11R1_FB23_Msk

Filter bit 23

◆ CAN_F11R1_FB23_Msk

#define CAN_F11R1_FB23_Msk (0x1UL << CAN_F11R1_FB23_Pos)

0x00800000

◆ CAN_F11R1_FB23_Pos

#define CAN_F11R1_FB23_Pos (23U)

◆ CAN_F11R1_FB24

#define CAN_F11R1_FB24 CAN_F11R1_FB24_Msk

Filter bit 24

◆ CAN_F11R1_FB24_Msk

#define CAN_F11R1_FB24_Msk (0x1UL << CAN_F11R1_FB24_Pos)

0x01000000

◆ CAN_F11R1_FB24_Pos

#define CAN_F11R1_FB24_Pos (24U)

◆ CAN_F11R1_FB25

#define CAN_F11R1_FB25 CAN_F11R1_FB25_Msk

Filter bit 25

◆ CAN_F11R1_FB25_Msk

#define CAN_F11R1_FB25_Msk (0x1UL << CAN_F11R1_FB25_Pos)

0x02000000

◆ CAN_F11R1_FB25_Pos

#define CAN_F11R1_FB25_Pos (25U)

◆ CAN_F11R1_FB26

#define CAN_F11R1_FB26 CAN_F11R1_FB26_Msk

Filter bit 26

◆ CAN_F11R1_FB26_Msk

#define CAN_F11R1_FB26_Msk (0x1UL << CAN_F11R1_FB26_Pos)

0x04000000

◆ CAN_F11R1_FB26_Pos

#define CAN_F11R1_FB26_Pos (26U)

◆ CAN_F11R1_FB27

#define CAN_F11R1_FB27 CAN_F11R1_FB27_Msk

Filter bit 27

◆ CAN_F11R1_FB27_Msk

#define CAN_F11R1_FB27_Msk (0x1UL << CAN_F11R1_FB27_Pos)

0x08000000

◆ CAN_F11R1_FB27_Pos

#define CAN_F11R1_FB27_Pos (27U)

◆ CAN_F11R1_FB28

#define CAN_F11R1_FB28 CAN_F11R1_FB28_Msk

Filter bit 28

◆ CAN_F11R1_FB28_Msk

#define CAN_F11R1_FB28_Msk (0x1UL << CAN_F11R1_FB28_Pos)

0x10000000

◆ CAN_F11R1_FB28_Pos

#define CAN_F11R1_FB28_Pos (28U)

◆ CAN_F11R1_FB29

#define CAN_F11R1_FB29 CAN_F11R1_FB29_Msk

Filter bit 29

◆ CAN_F11R1_FB29_Msk

#define CAN_F11R1_FB29_Msk (0x1UL << CAN_F11R1_FB29_Pos)

0x20000000

◆ CAN_F11R1_FB29_Pos

#define CAN_F11R1_FB29_Pos (29U)

◆ CAN_F11R1_FB2_Msk

#define CAN_F11R1_FB2_Msk (0x1UL << CAN_F11R1_FB2_Pos)

0x00000004

◆ CAN_F11R1_FB2_Pos

#define CAN_F11R1_FB2_Pos (2U)

◆ CAN_F11R1_FB3

#define CAN_F11R1_FB3 CAN_F11R1_FB3_Msk

Filter bit 3

◆ CAN_F11R1_FB30

#define CAN_F11R1_FB30 CAN_F11R1_FB30_Msk

Filter bit 30

◆ CAN_F11R1_FB30_Msk

#define CAN_F11R1_FB30_Msk (0x1UL << CAN_F11R1_FB30_Pos)

0x40000000

◆ CAN_F11R1_FB30_Pos

#define CAN_F11R1_FB30_Pos (30U)

◆ CAN_F11R1_FB31

#define CAN_F11R1_FB31 CAN_F11R1_FB31_Msk

Filter bit 31

◆ CAN_F11R1_FB31_Msk

#define CAN_F11R1_FB31_Msk (0x1UL << CAN_F11R1_FB31_Pos)

0x80000000

◆ CAN_F11R1_FB31_Pos

#define CAN_F11R1_FB31_Pos (31U)

◆ CAN_F11R1_FB3_Msk

#define CAN_F11R1_FB3_Msk (0x1UL << CAN_F11R1_FB3_Pos)

0x00000008

◆ CAN_F11R1_FB3_Pos

#define CAN_F11R1_FB3_Pos (3U)

◆ CAN_F11R1_FB4

#define CAN_F11R1_FB4 CAN_F11R1_FB4_Msk

Filter bit 4

◆ CAN_F11R1_FB4_Msk

#define CAN_F11R1_FB4_Msk (0x1UL << CAN_F11R1_FB4_Pos)

0x00000010

◆ CAN_F11R1_FB4_Pos

#define CAN_F11R1_FB4_Pos (4U)

◆ CAN_F11R1_FB5

#define CAN_F11R1_FB5 CAN_F11R1_FB5_Msk

Filter bit 5

◆ CAN_F11R1_FB5_Msk

#define CAN_F11R1_FB5_Msk (0x1UL << CAN_F11R1_FB5_Pos)

0x00000020

◆ CAN_F11R1_FB5_Pos

#define CAN_F11R1_FB5_Pos (5U)

◆ CAN_F11R1_FB6

#define CAN_F11R1_FB6 CAN_F11R1_FB6_Msk

Filter bit 6

◆ CAN_F11R1_FB6_Msk

#define CAN_F11R1_FB6_Msk (0x1UL << CAN_F11R1_FB6_Pos)

0x00000040

◆ CAN_F11R1_FB6_Pos

#define CAN_F11R1_FB6_Pos (6U)

◆ CAN_F11R1_FB7

#define CAN_F11R1_FB7 CAN_F11R1_FB7_Msk

Filter bit 7

◆ CAN_F11R1_FB7_Msk

#define CAN_F11R1_FB7_Msk (0x1UL << CAN_F11R1_FB7_Pos)

0x00000080

◆ CAN_F11R1_FB7_Pos

#define CAN_F11R1_FB7_Pos (7U)

◆ CAN_F11R1_FB8

#define CAN_F11R1_FB8 CAN_F11R1_FB8_Msk

Filter bit 8

◆ CAN_F11R1_FB8_Msk

#define CAN_F11R1_FB8_Msk (0x1UL << CAN_F11R1_FB8_Pos)

0x00000100

◆ CAN_F11R1_FB8_Pos

#define CAN_F11R1_FB8_Pos (8U)

◆ CAN_F11R1_FB9

#define CAN_F11R1_FB9 CAN_F11R1_FB9_Msk

Filter bit 9

◆ CAN_F11R1_FB9_Msk

#define CAN_F11R1_FB9_Msk (0x1UL << CAN_F11R1_FB9_Pos)

0x00000200

◆ CAN_F11R1_FB9_Pos

#define CAN_F11R1_FB9_Pos (9U)

◆ CAN_F11R2_FB0

#define CAN_F11R2_FB0 CAN_F11R2_FB0_Msk

Filter bit 0

◆ CAN_F11R2_FB0_Msk

#define CAN_F11R2_FB0_Msk (0x1UL << CAN_F11R2_FB0_Pos)

0x00000001

◆ CAN_F11R2_FB0_Pos

#define CAN_F11R2_FB0_Pos (0U)

◆ CAN_F11R2_FB1

#define CAN_F11R2_FB1 CAN_F11R2_FB1_Msk

Filter bit 1

◆ CAN_F11R2_FB10

#define CAN_F11R2_FB10 CAN_F11R2_FB10_Msk

Filter bit 10

◆ CAN_F11R2_FB10_Msk

#define CAN_F11R2_FB10_Msk (0x1UL << CAN_F11R2_FB10_Pos)

0x00000400

◆ CAN_F11R2_FB10_Pos

#define CAN_F11R2_FB10_Pos (10U)

◆ CAN_F11R2_FB11

#define CAN_F11R2_FB11 CAN_F11R2_FB11_Msk

Filter bit 11

◆ CAN_F11R2_FB11_Msk

#define CAN_F11R2_FB11_Msk (0x1UL << CAN_F11R2_FB11_Pos)

0x00000800

◆ CAN_F11R2_FB11_Pos

#define CAN_F11R2_FB11_Pos (11U)

◆ CAN_F11R2_FB12

#define CAN_F11R2_FB12 CAN_F11R2_FB12_Msk

Filter bit 12

◆ CAN_F11R2_FB12_Msk

#define CAN_F11R2_FB12_Msk (0x1UL << CAN_F11R2_FB12_Pos)

0x00001000

◆ CAN_F11R2_FB12_Pos

#define CAN_F11R2_FB12_Pos (12U)

◆ CAN_F11R2_FB13

#define CAN_F11R2_FB13 CAN_F11R2_FB13_Msk

Filter bit 13

◆ CAN_F11R2_FB13_Msk

#define CAN_F11R2_FB13_Msk (0x1UL << CAN_F11R2_FB13_Pos)

0x00002000

◆ CAN_F11R2_FB13_Pos

#define CAN_F11R2_FB13_Pos (13U)

◆ CAN_F11R2_FB14

#define CAN_F11R2_FB14 CAN_F11R2_FB14_Msk

Filter bit 14

◆ CAN_F11R2_FB14_Msk

#define CAN_F11R2_FB14_Msk (0x1UL << CAN_F11R2_FB14_Pos)

0x00004000

◆ CAN_F11R2_FB14_Pos

#define CAN_F11R2_FB14_Pos (14U)

◆ CAN_F11R2_FB15

#define CAN_F11R2_FB15 CAN_F11R2_FB15_Msk

Filter bit 15

◆ CAN_F11R2_FB15_Msk

#define CAN_F11R2_FB15_Msk (0x1UL << CAN_F11R2_FB15_Pos)

0x00008000

◆ CAN_F11R2_FB15_Pos

#define CAN_F11R2_FB15_Pos (15U)

◆ CAN_F11R2_FB16

#define CAN_F11R2_FB16 CAN_F11R2_FB16_Msk

Filter bit 16

◆ CAN_F11R2_FB16_Msk

#define CAN_F11R2_FB16_Msk (0x1UL << CAN_F11R2_FB16_Pos)

0x00010000

◆ CAN_F11R2_FB16_Pos

#define CAN_F11R2_FB16_Pos (16U)

◆ CAN_F11R2_FB17

#define CAN_F11R2_FB17 CAN_F11R2_FB17_Msk

Filter bit 17

◆ CAN_F11R2_FB17_Msk

#define CAN_F11R2_FB17_Msk (0x1UL << CAN_F11R2_FB17_Pos)

0x00020000

◆ CAN_F11R2_FB17_Pos

#define CAN_F11R2_FB17_Pos (17U)

◆ CAN_F11R2_FB18

#define CAN_F11R2_FB18 CAN_F11R2_FB18_Msk

Filter bit 18

◆ CAN_F11R2_FB18_Msk

#define CAN_F11R2_FB18_Msk (0x1UL << CAN_F11R2_FB18_Pos)

0x00040000

◆ CAN_F11R2_FB18_Pos

#define CAN_F11R2_FB18_Pos (18U)

◆ CAN_F11R2_FB19

#define CAN_F11R2_FB19 CAN_F11R2_FB19_Msk

Filter bit 19

◆ CAN_F11R2_FB19_Msk

#define CAN_F11R2_FB19_Msk (0x1UL << CAN_F11R2_FB19_Pos)

0x00080000

◆ CAN_F11R2_FB19_Pos

#define CAN_F11R2_FB19_Pos (19U)

◆ CAN_F11R2_FB1_Msk

#define CAN_F11R2_FB1_Msk (0x1UL << CAN_F11R2_FB1_Pos)

0x00000002

◆ CAN_F11R2_FB1_Pos

#define CAN_F11R2_FB1_Pos (1U)

◆ CAN_F11R2_FB2

#define CAN_F11R2_FB2 CAN_F11R2_FB2_Msk

Filter bit 2

◆ CAN_F11R2_FB20

#define CAN_F11R2_FB20 CAN_F11R2_FB20_Msk

Filter bit 20

◆ CAN_F11R2_FB20_Msk

#define CAN_F11R2_FB20_Msk (0x1UL << CAN_F11R2_FB20_Pos)

0x00100000

◆ CAN_F11R2_FB20_Pos

#define CAN_F11R2_FB20_Pos (20U)

◆ CAN_F11R2_FB21

#define CAN_F11R2_FB21 CAN_F11R2_FB21_Msk

Filter bit 21

◆ CAN_F11R2_FB21_Msk

#define CAN_F11R2_FB21_Msk (0x1UL << CAN_F11R2_FB21_Pos)

0x00200000

◆ CAN_F11R2_FB21_Pos

#define CAN_F11R2_FB21_Pos (21U)

◆ CAN_F11R2_FB22

#define CAN_F11R2_FB22 CAN_F11R2_FB22_Msk

Filter bit 22

◆ CAN_F11R2_FB22_Msk

#define CAN_F11R2_FB22_Msk (0x1UL << CAN_F11R2_FB22_Pos)

0x00400000

◆ CAN_F11R2_FB22_Pos

#define CAN_F11R2_FB22_Pos (22U)

◆ CAN_F11R2_FB23

#define CAN_F11R2_FB23 CAN_F11R2_FB23_Msk

Filter bit 23

◆ CAN_F11R2_FB23_Msk

#define CAN_F11R2_FB23_Msk (0x1UL << CAN_F11R2_FB23_Pos)

0x00800000

◆ CAN_F11R2_FB23_Pos

#define CAN_F11R2_FB23_Pos (23U)

◆ CAN_F11R2_FB24

#define CAN_F11R2_FB24 CAN_F11R2_FB24_Msk

Filter bit 24

◆ CAN_F11R2_FB24_Msk

#define CAN_F11R2_FB24_Msk (0x1UL << CAN_F11R2_FB24_Pos)

0x01000000

◆ CAN_F11R2_FB24_Pos

#define CAN_F11R2_FB24_Pos (24U)

◆ CAN_F11R2_FB25

#define CAN_F11R2_FB25 CAN_F11R2_FB25_Msk

Filter bit 25

◆ CAN_F11R2_FB25_Msk

#define CAN_F11R2_FB25_Msk (0x1UL << CAN_F11R2_FB25_Pos)

0x02000000

◆ CAN_F11R2_FB25_Pos

#define CAN_F11R2_FB25_Pos (25U)

◆ CAN_F11R2_FB26

#define CAN_F11R2_FB26 CAN_F11R2_FB26_Msk

Filter bit 26

◆ CAN_F11R2_FB26_Msk

#define CAN_F11R2_FB26_Msk (0x1UL << CAN_F11R2_FB26_Pos)

0x04000000

◆ CAN_F11R2_FB26_Pos

#define CAN_F11R2_FB26_Pos (26U)

◆ CAN_F11R2_FB27

#define CAN_F11R2_FB27 CAN_F11R2_FB27_Msk

Filter bit 27

◆ CAN_F11R2_FB27_Msk

#define CAN_F11R2_FB27_Msk (0x1UL << CAN_F11R2_FB27_Pos)

0x08000000

◆ CAN_F11R2_FB27_Pos

#define CAN_F11R2_FB27_Pos (27U)

◆ CAN_F11R2_FB28

#define CAN_F11R2_FB28 CAN_F11R2_FB28_Msk

Filter bit 28

◆ CAN_F11R2_FB28_Msk

#define CAN_F11R2_FB28_Msk (0x1UL << CAN_F11R2_FB28_Pos)

0x10000000

◆ CAN_F11R2_FB28_Pos

#define CAN_F11R2_FB28_Pos (28U)

◆ CAN_F11R2_FB29

#define CAN_F11R2_FB29 CAN_F11R2_FB29_Msk

Filter bit 29

◆ CAN_F11R2_FB29_Msk

#define CAN_F11R2_FB29_Msk (0x1UL << CAN_F11R2_FB29_Pos)

0x20000000

◆ CAN_F11R2_FB29_Pos

#define CAN_F11R2_FB29_Pos (29U)

◆ CAN_F11R2_FB2_Msk

#define CAN_F11R2_FB2_Msk (0x1UL << CAN_F11R2_FB2_Pos)

0x00000004

◆ CAN_F11R2_FB2_Pos

#define CAN_F11R2_FB2_Pos (2U)

◆ CAN_F11R2_FB3

#define CAN_F11R2_FB3 CAN_F11R2_FB3_Msk

Filter bit 3

◆ CAN_F11R2_FB30

#define CAN_F11R2_FB30 CAN_F11R2_FB30_Msk

Filter bit 30

◆ CAN_F11R2_FB30_Msk

#define CAN_F11R2_FB30_Msk (0x1UL << CAN_F11R2_FB30_Pos)

0x40000000

◆ CAN_F11R2_FB30_Pos

#define CAN_F11R2_FB30_Pos (30U)

◆ CAN_F11R2_FB31

#define CAN_F11R2_FB31 CAN_F11R2_FB31_Msk

Filter bit 31

◆ CAN_F11R2_FB31_Msk

#define CAN_F11R2_FB31_Msk (0x1UL << CAN_F11R2_FB31_Pos)

0x80000000

◆ CAN_F11R2_FB31_Pos

#define CAN_F11R2_FB31_Pos (31U)

◆ CAN_F11R2_FB3_Msk

#define CAN_F11R2_FB3_Msk (0x1UL << CAN_F11R2_FB3_Pos)

0x00000008

◆ CAN_F11R2_FB3_Pos

#define CAN_F11R2_FB3_Pos (3U)

◆ CAN_F11R2_FB4

#define CAN_F11R2_FB4 CAN_F11R2_FB4_Msk

Filter bit 4

◆ CAN_F11R2_FB4_Msk

#define CAN_F11R2_FB4_Msk (0x1UL << CAN_F11R2_FB4_Pos)

0x00000010

◆ CAN_F11R2_FB4_Pos

#define CAN_F11R2_FB4_Pos (4U)

◆ CAN_F11R2_FB5

#define CAN_F11R2_FB5 CAN_F11R2_FB5_Msk

Filter bit 5

◆ CAN_F11R2_FB5_Msk

#define CAN_F11R2_FB5_Msk (0x1UL << CAN_F11R2_FB5_Pos)

0x00000020

◆ CAN_F11R2_FB5_Pos

#define CAN_F11R2_FB5_Pos (5U)

◆ CAN_F11R2_FB6

#define CAN_F11R2_FB6 CAN_F11R2_FB6_Msk

Filter bit 6

◆ CAN_F11R2_FB6_Msk

#define CAN_F11R2_FB6_Msk (0x1UL << CAN_F11R2_FB6_Pos)

0x00000040

◆ CAN_F11R2_FB6_Pos

#define CAN_F11R2_FB6_Pos (6U)

◆ CAN_F11R2_FB7

#define CAN_F11R2_FB7 CAN_F11R2_FB7_Msk

Filter bit 7

◆ CAN_F11R2_FB7_Msk

#define CAN_F11R2_FB7_Msk (0x1UL << CAN_F11R2_FB7_Pos)

0x00000080

◆ CAN_F11R2_FB7_Pos

#define CAN_F11R2_FB7_Pos (7U)

◆ CAN_F11R2_FB8

#define CAN_F11R2_FB8 CAN_F11R2_FB8_Msk

Filter bit 8

◆ CAN_F11R2_FB8_Msk

#define CAN_F11R2_FB8_Msk (0x1UL << CAN_F11R2_FB8_Pos)

0x00000100

◆ CAN_F11R2_FB8_Pos

#define CAN_F11R2_FB8_Pos (8U)

◆ CAN_F11R2_FB9

#define CAN_F11R2_FB9 CAN_F11R2_FB9_Msk

Filter bit 9

◆ CAN_F11R2_FB9_Msk

#define CAN_F11R2_FB9_Msk (0x1UL << CAN_F11R2_FB9_Pos)

0x00000200

◆ CAN_F11R2_FB9_Pos

#define CAN_F11R2_FB9_Pos (9U)

◆ CAN_F12R1_FB0

#define CAN_F12R1_FB0 CAN_F12R1_FB0_Msk

Filter bit 0

◆ CAN_F12R1_FB0_Msk

#define CAN_F12R1_FB0_Msk (0x1UL << CAN_F12R1_FB0_Pos)

0x00000001

◆ CAN_F12R1_FB0_Pos

#define CAN_F12R1_FB0_Pos (0U)

◆ CAN_F12R1_FB1

#define CAN_F12R1_FB1 CAN_F12R1_FB1_Msk

Filter bit 1

◆ CAN_F12R1_FB10

#define CAN_F12R1_FB10 CAN_F12R1_FB10_Msk

Filter bit 10

◆ CAN_F12R1_FB10_Msk

#define CAN_F12R1_FB10_Msk (0x1UL << CAN_F12R1_FB10_Pos)

0x00000400

◆ CAN_F12R1_FB10_Pos

#define CAN_F12R1_FB10_Pos (10U)

◆ CAN_F12R1_FB11

#define CAN_F12R1_FB11 CAN_F12R1_FB11_Msk

Filter bit 11

◆ CAN_F12R1_FB11_Msk

#define CAN_F12R1_FB11_Msk (0x1UL << CAN_F12R1_FB11_Pos)

0x00000800

◆ CAN_F12R1_FB11_Pos

#define CAN_F12R1_FB11_Pos (11U)

◆ CAN_F12R1_FB12

#define CAN_F12R1_FB12 CAN_F12R1_FB12_Msk

Filter bit 12

◆ CAN_F12R1_FB12_Msk

#define CAN_F12R1_FB12_Msk (0x1UL << CAN_F12R1_FB12_Pos)

0x00001000

◆ CAN_F12R1_FB12_Pos

#define CAN_F12R1_FB12_Pos (12U)

◆ CAN_F12R1_FB13

#define CAN_F12R1_FB13 CAN_F12R1_FB13_Msk

Filter bit 13

◆ CAN_F12R1_FB13_Msk

#define CAN_F12R1_FB13_Msk (0x1UL << CAN_F12R1_FB13_Pos)

0x00002000

◆ CAN_F12R1_FB13_Pos

#define CAN_F12R1_FB13_Pos (13U)

◆ CAN_F12R1_FB14

#define CAN_F12R1_FB14 CAN_F12R1_FB14_Msk

Filter bit 14

◆ CAN_F12R1_FB14_Msk

#define CAN_F12R1_FB14_Msk (0x1UL << CAN_F12R1_FB14_Pos)

0x00004000

◆ CAN_F12R1_FB14_Pos

#define CAN_F12R1_FB14_Pos (14U)

◆ CAN_F12R1_FB15

#define CAN_F12R1_FB15 CAN_F12R1_FB15_Msk

Filter bit 15

◆ CAN_F12R1_FB15_Msk

#define CAN_F12R1_FB15_Msk (0x1UL << CAN_F12R1_FB15_Pos)

0x00008000

◆ CAN_F12R1_FB15_Pos

#define CAN_F12R1_FB15_Pos (15U)

◆ CAN_F12R1_FB16

#define CAN_F12R1_FB16 CAN_F12R1_FB16_Msk

Filter bit 16

◆ CAN_F12R1_FB16_Msk

#define CAN_F12R1_FB16_Msk (0x1UL << CAN_F12R1_FB16_Pos)

0x00010000

◆ CAN_F12R1_FB16_Pos

#define CAN_F12R1_FB16_Pos (16U)

◆ CAN_F12R1_FB17

#define CAN_F12R1_FB17 CAN_F12R1_FB17_Msk

Filter bit 17

◆ CAN_F12R1_FB17_Msk

#define CAN_F12R1_FB17_Msk (0x1UL << CAN_F12R1_FB17_Pos)

0x00020000

◆ CAN_F12R1_FB17_Pos

#define CAN_F12R1_FB17_Pos (17U)

◆ CAN_F12R1_FB18

#define CAN_F12R1_FB18 CAN_F12R1_FB18_Msk

Filter bit 18

◆ CAN_F12R1_FB18_Msk

#define CAN_F12R1_FB18_Msk (0x1UL << CAN_F12R1_FB18_Pos)

0x00040000

◆ CAN_F12R1_FB18_Pos

#define CAN_F12R1_FB18_Pos (18U)

◆ CAN_F12R1_FB19

#define CAN_F12R1_FB19 CAN_F12R1_FB19_Msk

Filter bit 19

◆ CAN_F12R1_FB19_Msk

#define CAN_F12R1_FB19_Msk (0x1UL << CAN_F12R1_FB19_Pos)

0x00080000

◆ CAN_F12R1_FB19_Pos

#define CAN_F12R1_FB19_Pos (19U)

◆ CAN_F12R1_FB1_Msk

#define CAN_F12R1_FB1_Msk (0x1UL << CAN_F12R1_FB1_Pos)

0x00000002

◆ CAN_F12R1_FB1_Pos

#define CAN_F12R1_FB1_Pos (1U)

◆ CAN_F12R1_FB2

#define CAN_F12R1_FB2 CAN_F12R1_FB2_Msk

Filter bit 2

◆ CAN_F12R1_FB20

#define CAN_F12R1_FB20 CAN_F12R1_FB20_Msk

Filter bit 20

◆ CAN_F12R1_FB20_Msk

#define CAN_F12R1_FB20_Msk (0x1UL << CAN_F12R1_FB20_Pos)

0x00100000

◆ CAN_F12R1_FB20_Pos

#define CAN_F12R1_FB20_Pos (20U)

◆ CAN_F12R1_FB21

#define CAN_F12R1_FB21 CAN_F12R1_FB21_Msk

Filter bit 21

◆ CAN_F12R1_FB21_Msk

#define CAN_F12R1_FB21_Msk (0x1UL << CAN_F12R1_FB21_Pos)

0x00200000

◆ CAN_F12R1_FB21_Pos

#define CAN_F12R1_FB21_Pos (21U)

◆ CAN_F12R1_FB22

#define CAN_F12R1_FB22 CAN_F12R1_FB22_Msk

Filter bit 22

◆ CAN_F12R1_FB22_Msk

#define CAN_F12R1_FB22_Msk (0x1UL << CAN_F12R1_FB22_Pos)

0x00400000

◆ CAN_F12R1_FB22_Pos

#define CAN_F12R1_FB22_Pos (22U)

◆ CAN_F12R1_FB23

#define CAN_F12R1_FB23 CAN_F12R1_FB23_Msk

Filter bit 23

◆ CAN_F12R1_FB23_Msk

#define CAN_F12R1_FB23_Msk (0x1UL << CAN_F12R1_FB23_Pos)

0x00800000

◆ CAN_F12R1_FB23_Pos

#define CAN_F12R1_FB23_Pos (23U)

◆ CAN_F12R1_FB24

#define CAN_F12R1_FB24 CAN_F12R1_FB24_Msk

Filter bit 24

◆ CAN_F12R1_FB24_Msk

#define CAN_F12R1_FB24_Msk (0x1UL << CAN_F12R1_FB24_Pos)

0x01000000

◆ CAN_F12R1_FB24_Pos

#define CAN_F12R1_FB24_Pos (24U)

◆ CAN_F12R1_FB25

#define CAN_F12R1_FB25 CAN_F12R1_FB25_Msk

Filter bit 25

◆ CAN_F12R1_FB25_Msk

#define CAN_F12R1_FB25_Msk (0x1UL << CAN_F12R1_FB25_Pos)

0x02000000

◆ CAN_F12R1_FB25_Pos

#define CAN_F12R1_FB25_Pos (25U)

◆ CAN_F12R1_FB26

#define CAN_F12R1_FB26 CAN_F12R1_FB26_Msk

Filter bit 26

◆ CAN_F12R1_FB26_Msk

#define CAN_F12R1_FB26_Msk (0x1UL << CAN_F12R1_FB26_Pos)

0x04000000

◆ CAN_F12R1_FB26_Pos

#define CAN_F12R1_FB26_Pos (26U)

◆ CAN_F12R1_FB27

#define CAN_F12R1_FB27 CAN_F12R1_FB27_Msk

Filter bit 27

◆ CAN_F12R1_FB27_Msk

#define CAN_F12R1_FB27_Msk (0x1UL << CAN_F12R1_FB27_Pos)

0x08000000

◆ CAN_F12R1_FB27_Pos

#define CAN_F12R1_FB27_Pos (27U)

◆ CAN_F12R1_FB28

#define CAN_F12R1_FB28 CAN_F12R1_FB28_Msk

Filter bit 28

◆ CAN_F12R1_FB28_Msk

#define CAN_F12R1_FB28_Msk (0x1UL << CAN_F12R1_FB28_Pos)

0x10000000

◆ CAN_F12R1_FB28_Pos

#define CAN_F12R1_FB28_Pos (28U)

◆ CAN_F12R1_FB29

#define CAN_F12R1_FB29 CAN_F12R1_FB29_Msk

Filter bit 29

◆ CAN_F12R1_FB29_Msk

#define CAN_F12R1_FB29_Msk (0x1UL << CAN_F12R1_FB29_Pos)

0x20000000

◆ CAN_F12R1_FB29_Pos

#define CAN_F12R1_FB29_Pos (29U)

◆ CAN_F12R1_FB2_Msk

#define CAN_F12R1_FB2_Msk (0x1UL << CAN_F12R1_FB2_Pos)

0x00000004

◆ CAN_F12R1_FB2_Pos

#define CAN_F12R1_FB2_Pos (2U)

◆ CAN_F12R1_FB3

#define CAN_F12R1_FB3 CAN_F12R1_FB3_Msk

Filter bit 3

◆ CAN_F12R1_FB30

#define CAN_F12R1_FB30 CAN_F12R1_FB30_Msk

Filter bit 30

◆ CAN_F12R1_FB30_Msk

#define CAN_F12R1_FB30_Msk (0x1UL << CAN_F12R1_FB30_Pos)

0x40000000

◆ CAN_F12R1_FB30_Pos

#define CAN_F12R1_FB30_Pos (30U)

◆ CAN_F12R1_FB31

#define CAN_F12R1_FB31 CAN_F12R1_FB31_Msk

Filter bit 31

◆ CAN_F12R1_FB31_Msk

#define CAN_F12R1_FB31_Msk (0x1UL << CAN_F12R1_FB31_Pos)

0x80000000

◆ CAN_F12R1_FB31_Pos

#define CAN_F12R1_FB31_Pos (31U)

◆ CAN_F12R1_FB3_Msk

#define CAN_F12R1_FB3_Msk (0x1UL << CAN_F12R1_FB3_Pos)

0x00000008

◆ CAN_F12R1_FB3_Pos

#define CAN_F12R1_FB3_Pos (3U)

◆ CAN_F12R1_FB4

#define CAN_F12R1_FB4 CAN_F12R1_FB4_Msk

Filter bit 4

◆ CAN_F12R1_FB4_Msk

#define CAN_F12R1_FB4_Msk (0x1UL << CAN_F12R1_FB4_Pos)

0x00000010

◆ CAN_F12R1_FB4_Pos

#define CAN_F12R1_FB4_Pos (4U)

◆ CAN_F12R1_FB5

#define CAN_F12R1_FB5 CAN_F12R1_FB5_Msk

Filter bit 5

◆ CAN_F12R1_FB5_Msk

#define CAN_F12R1_FB5_Msk (0x1UL << CAN_F12R1_FB5_Pos)

0x00000020

◆ CAN_F12R1_FB5_Pos

#define CAN_F12R1_FB5_Pos (5U)

◆ CAN_F12R1_FB6

#define CAN_F12R1_FB6 CAN_F12R1_FB6_Msk

Filter bit 6

◆ CAN_F12R1_FB6_Msk

#define CAN_F12R1_FB6_Msk (0x1UL << CAN_F12R1_FB6_Pos)

0x00000040

◆ CAN_F12R1_FB6_Pos

#define CAN_F12R1_FB6_Pos (6U)

◆ CAN_F12R1_FB7

#define CAN_F12R1_FB7 CAN_F12R1_FB7_Msk

Filter bit 7

◆ CAN_F12R1_FB7_Msk

#define CAN_F12R1_FB7_Msk (0x1UL << CAN_F12R1_FB7_Pos)

0x00000080

◆ CAN_F12R1_FB7_Pos

#define CAN_F12R1_FB7_Pos (7U)

◆ CAN_F12R1_FB8

#define CAN_F12R1_FB8 CAN_F12R1_FB8_Msk

Filter bit 8

◆ CAN_F12R1_FB8_Msk

#define CAN_F12R1_FB8_Msk (0x1UL << CAN_F12R1_FB8_Pos)

0x00000100

◆ CAN_F12R1_FB8_Pos

#define CAN_F12R1_FB8_Pos (8U)

◆ CAN_F12R1_FB9

#define CAN_F12R1_FB9 CAN_F12R1_FB9_Msk

Filter bit 9

◆ CAN_F12R1_FB9_Msk

#define CAN_F12R1_FB9_Msk (0x1UL << CAN_F12R1_FB9_Pos)

0x00000200

◆ CAN_F12R1_FB9_Pos

#define CAN_F12R1_FB9_Pos (9U)

◆ CAN_F12R2_FB0

#define CAN_F12R2_FB0 CAN_F12R2_FB0_Msk

Filter bit 0

◆ CAN_F12R2_FB0_Msk

#define CAN_F12R2_FB0_Msk (0x1UL << CAN_F12R2_FB0_Pos)

0x00000001

◆ CAN_F12R2_FB0_Pos

#define CAN_F12R2_FB0_Pos (0U)

◆ CAN_F12R2_FB1

#define CAN_F12R2_FB1 CAN_F12R2_FB1_Msk

Filter bit 1

◆ CAN_F12R2_FB10

#define CAN_F12R2_FB10 CAN_F12R2_FB10_Msk

Filter bit 10

◆ CAN_F12R2_FB10_Msk

#define CAN_F12R2_FB10_Msk (0x1UL << CAN_F12R2_FB10_Pos)

0x00000400

◆ CAN_F12R2_FB10_Pos

#define CAN_F12R2_FB10_Pos (10U)

◆ CAN_F12R2_FB11

#define CAN_F12R2_FB11 CAN_F12R2_FB11_Msk

Filter bit 11

◆ CAN_F12R2_FB11_Msk

#define CAN_F12R2_FB11_Msk (0x1UL << CAN_F12R2_FB11_Pos)

0x00000800

◆ CAN_F12R2_FB11_Pos

#define CAN_F12R2_FB11_Pos (11U)

◆ CAN_F12R2_FB12

#define CAN_F12R2_FB12 CAN_F12R2_FB12_Msk

Filter bit 12

◆ CAN_F12R2_FB12_Msk

#define CAN_F12R2_FB12_Msk (0x1UL << CAN_F12R2_FB12_Pos)

0x00001000

◆ CAN_F12R2_FB12_Pos

#define CAN_F12R2_FB12_Pos (12U)

◆ CAN_F12R2_FB13

#define CAN_F12R2_FB13 CAN_F12R2_FB13_Msk

Filter bit 13

◆ CAN_F12R2_FB13_Msk

#define CAN_F12R2_FB13_Msk (0x1UL << CAN_F12R2_FB13_Pos)

0x00002000

◆ CAN_F12R2_FB13_Pos

#define CAN_F12R2_FB13_Pos (13U)

◆ CAN_F12R2_FB14

#define CAN_F12R2_FB14 CAN_F12R2_FB14_Msk

Filter bit 14

◆ CAN_F12R2_FB14_Msk

#define CAN_F12R2_FB14_Msk (0x1UL << CAN_F12R2_FB14_Pos)

0x00004000

◆ CAN_F12R2_FB14_Pos

#define CAN_F12R2_FB14_Pos (14U)

◆ CAN_F12R2_FB15

#define CAN_F12R2_FB15 CAN_F12R2_FB15_Msk

Filter bit 15

◆ CAN_F12R2_FB15_Msk

#define CAN_F12R2_FB15_Msk (0x1UL << CAN_F12R2_FB15_Pos)

0x00008000

◆ CAN_F12R2_FB15_Pos

#define CAN_F12R2_FB15_Pos (15U)

◆ CAN_F12R2_FB16

#define CAN_F12R2_FB16 CAN_F12R2_FB16_Msk

Filter bit 16

◆ CAN_F12R2_FB16_Msk

#define CAN_F12R2_FB16_Msk (0x1UL << CAN_F12R2_FB16_Pos)

0x00010000

◆ CAN_F12R2_FB16_Pos

#define CAN_F12R2_FB16_Pos (16U)

◆ CAN_F12R2_FB17

#define CAN_F12R2_FB17 CAN_F12R2_FB17_Msk

Filter bit 17

◆ CAN_F12R2_FB17_Msk

#define CAN_F12R2_FB17_Msk (0x1UL << CAN_F12R2_FB17_Pos)

0x00020000

◆ CAN_F12R2_FB17_Pos

#define CAN_F12R2_FB17_Pos (17U)

◆ CAN_F12R2_FB18

#define CAN_F12R2_FB18 CAN_F12R2_FB18_Msk

Filter bit 18

◆ CAN_F12R2_FB18_Msk

#define CAN_F12R2_FB18_Msk (0x1UL << CAN_F12R2_FB18_Pos)

0x00040000

◆ CAN_F12R2_FB18_Pos

#define CAN_F12R2_FB18_Pos (18U)

◆ CAN_F12R2_FB19

#define CAN_F12R2_FB19 CAN_F12R2_FB19_Msk

Filter bit 19

◆ CAN_F12R2_FB19_Msk

#define CAN_F12R2_FB19_Msk (0x1UL << CAN_F12R2_FB19_Pos)

0x00080000

◆ CAN_F12R2_FB19_Pos

#define CAN_F12R2_FB19_Pos (19U)

◆ CAN_F12R2_FB1_Msk

#define CAN_F12R2_FB1_Msk (0x1UL << CAN_F12R2_FB1_Pos)

0x00000002

◆ CAN_F12R2_FB1_Pos

#define CAN_F12R2_FB1_Pos (1U)

◆ CAN_F12R2_FB2

#define CAN_F12R2_FB2 CAN_F12R2_FB2_Msk

Filter bit 2

◆ CAN_F12R2_FB20

#define CAN_F12R2_FB20 CAN_F12R2_FB20_Msk

Filter bit 20

◆ CAN_F12R2_FB20_Msk

#define CAN_F12R2_FB20_Msk (0x1UL << CAN_F12R2_FB20_Pos)

0x00100000

◆ CAN_F12R2_FB20_Pos

#define CAN_F12R2_FB20_Pos (20U)

◆ CAN_F12R2_FB21

#define CAN_F12R2_FB21 CAN_F12R2_FB21_Msk

Filter bit 21

◆ CAN_F12R2_FB21_Msk

#define CAN_F12R2_FB21_Msk (0x1UL << CAN_F12R2_FB21_Pos)

0x00200000

◆ CAN_F12R2_FB21_Pos

#define CAN_F12R2_FB21_Pos (21U)

◆ CAN_F12R2_FB22

#define CAN_F12R2_FB22 CAN_F12R2_FB22_Msk

Filter bit 22

◆ CAN_F12R2_FB22_Msk

#define CAN_F12R2_FB22_Msk (0x1UL << CAN_F12R2_FB22_Pos)

0x00400000

◆ CAN_F12R2_FB22_Pos

#define CAN_F12R2_FB22_Pos (22U)

◆ CAN_F12R2_FB23

#define CAN_F12R2_FB23 CAN_F12R2_FB23_Msk

Filter bit 23

◆ CAN_F12R2_FB23_Msk

#define CAN_F12R2_FB23_Msk (0x1UL << CAN_F12R2_FB23_Pos)

0x00800000

◆ CAN_F12R2_FB23_Pos

#define CAN_F12R2_FB23_Pos (23U)

◆ CAN_F12R2_FB24

#define CAN_F12R2_FB24 CAN_F12R2_FB24_Msk

Filter bit 24

◆ CAN_F12R2_FB24_Msk

#define CAN_F12R2_FB24_Msk (0x1UL << CAN_F12R2_FB24_Pos)

0x01000000

◆ CAN_F12R2_FB24_Pos

#define CAN_F12R2_FB24_Pos (24U)

◆ CAN_F12R2_FB25

#define CAN_F12R2_FB25 CAN_F12R2_FB25_Msk

Filter bit 25

◆ CAN_F12R2_FB25_Msk

#define CAN_F12R2_FB25_Msk (0x1UL << CAN_F12R2_FB25_Pos)

0x02000000

◆ CAN_F12R2_FB25_Pos

#define CAN_F12R2_FB25_Pos (25U)

◆ CAN_F12R2_FB26

#define CAN_F12R2_FB26 CAN_F12R2_FB26_Msk

Filter bit 26

◆ CAN_F12R2_FB26_Msk

#define CAN_F12R2_FB26_Msk (0x1UL << CAN_F12R2_FB26_Pos)

0x04000000

◆ CAN_F12R2_FB26_Pos

#define CAN_F12R2_FB26_Pos (26U)

◆ CAN_F12R2_FB27

#define CAN_F12R2_FB27 CAN_F12R2_FB27_Msk

Filter bit 27

◆ CAN_F12R2_FB27_Msk

#define CAN_F12R2_FB27_Msk (0x1UL << CAN_F12R2_FB27_Pos)

0x08000000

◆ CAN_F12R2_FB27_Pos

#define CAN_F12R2_FB27_Pos (27U)

◆ CAN_F12R2_FB28

#define CAN_F12R2_FB28 CAN_F12R2_FB28_Msk

Filter bit 28

◆ CAN_F12R2_FB28_Msk

#define CAN_F12R2_FB28_Msk (0x1UL << CAN_F12R2_FB28_Pos)

0x10000000

◆ CAN_F12R2_FB28_Pos

#define CAN_F12R2_FB28_Pos (28U)

◆ CAN_F12R2_FB29

#define CAN_F12R2_FB29 CAN_F12R2_FB29_Msk

Filter bit 29

◆ CAN_F12R2_FB29_Msk

#define CAN_F12R2_FB29_Msk (0x1UL << CAN_F12R2_FB29_Pos)

0x20000000

◆ CAN_F12R2_FB29_Pos

#define CAN_F12R2_FB29_Pos (29U)

◆ CAN_F12R2_FB2_Msk

#define CAN_F12R2_FB2_Msk (0x1UL << CAN_F12R2_FB2_Pos)

0x00000004

◆ CAN_F12R2_FB2_Pos

#define CAN_F12R2_FB2_Pos (2U)

◆ CAN_F12R2_FB3

#define CAN_F12R2_FB3 CAN_F12R2_FB3_Msk

Filter bit 3

◆ CAN_F12R2_FB30

#define CAN_F12R2_FB30 CAN_F12R2_FB30_Msk

Filter bit 30

◆ CAN_F12R2_FB30_Msk

#define CAN_F12R2_FB30_Msk (0x1UL << CAN_F12R2_FB30_Pos)

0x40000000

◆ CAN_F12R2_FB30_Pos

#define CAN_F12R2_FB30_Pos (30U)

◆ CAN_F12R2_FB31

#define CAN_F12R2_FB31 CAN_F12R2_FB31_Msk

Filter bit 31

◆ CAN_F12R2_FB31_Msk

#define CAN_F12R2_FB31_Msk (0x1UL << CAN_F12R2_FB31_Pos)

0x80000000

◆ CAN_F12R2_FB31_Pos

#define CAN_F12R2_FB31_Pos (31U)

◆ CAN_F12R2_FB3_Msk

#define CAN_F12R2_FB3_Msk (0x1UL << CAN_F12R2_FB3_Pos)

0x00000008

◆ CAN_F12R2_FB3_Pos

#define CAN_F12R2_FB3_Pos (3U)

◆ CAN_F12R2_FB4

#define CAN_F12R2_FB4 CAN_F12R2_FB4_Msk

Filter bit 4

◆ CAN_F12R2_FB4_Msk

#define CAN_F12R2_FB4_Msk (0x1UL << CAN_F12R2_FB4_Pos)

0x00000010

◆ CAN_F12R2_FB4_Pos

#define CAN_F12R2_FB4_Pos (4U)

◆ CAN_F12R2_FB5

#define CAN_F12R2_FB5 CAN_F12R2_FB5_Msk

Filter bit 5

◆ CAN_F12R2_FB5_Msk

#define CAN_F12R2_FB5_Msk (0x1UL << CAN_F12R2_FB5_Pos)

0x00000020

◆ CAN_F12R2_FB5_Pos

#define CAN_F12R2_FB5_Pos (5U)

◆ CAN_F12R2_FB6

#define CAN_F12R2_FB6 CAN_F12R2_FB6_Msk

Filter bit 6

◆ CAN_F12R2_FB6_Msk

#define CAN_F12R2_FB6_Msk (0x1UL << CAN_F12R2_FB6_Pos)

0x00000040

◆ CAN_F12R2_FB6_Pos

#define CAN_F12R2_FB6_Pos (6U)

◆ CAN_F12R2_FB7

#define CAN_F12R2_FB7 CAN_F12R2_FB7_Msk

Filter bit 7

◆ CAN_F12R2_FB7_Msk

#define CAN_F12R2_FB7_Msk (0x1UL << CAN_F12R2_FB7_Pos)

0x00000080

◆ CAN_F12R2_FB7_Pos

#define CAN_F12R2_FB7_Pos (7U)

◆ CAN_F12R2_FB8

#define CAN_F12R2_FB8 CAN_F12R2_FB8_Msk

Filter bit 8

◆ CAN_F12R2_FB8_Msk

#define CAN_F12R2_FB8_Msk (0x1UL << CAN_F12R2_FB8_Pos)

0x00000100

◆ CAN_F12R2_FB8_Pos

#define CAN_F12R2_FB8_Pos (8U)

◆ CAN_F12R2_FB9

#define CAN_F12R2_FB9 CAN_F12R2_FB9_Msk

Filter bit 9

◆ CAN_F12R2_FB9_Msk

#define CAN_F12R2_FB9_Msk (0x1UL << CAN_F12R2_FB9_Pos)

0x00000200

◆ CAN_F12R2_FB9_Pos

#define CAN_F12R2_FB9_Pos (9U)

◆ CAN_F13R1_FB0

#define CAN_F13R1_FB0 CAN_F13R1_FB0_Msk

Filter bit 0

◆ CAN_F13R1_FB0_Msk

#define CAN_F13R1_FB0_Msk (0x1UL << CAN_F13R1_FB0_Pos)

0x00000001

◆ CAN_F13R1_FB0_Pos

#define CAN_F13R1_FB0_Pos (0U)

◆ CAN_F13R1_FB1

#define CAN_F13R1_FB1 CAN_F13R1_FB1_Msk

Filter bit 1

◆ CAN_F13R1_FB10

#define CAN_F13R1_FB10 CAN_F13R1_FB10_Msk

Filter bit 10

◆ CAN_F13R1_FB10_Msk

#define CAN_F13R1_FB10_Msk (0x1UL << CAN_F13R1_FB10_Pos)

0x00000400

◆ CAN_F13R1_FB10_Pos

#define CAN_F13R1_FB10_Pos (10U)

◆ CAN_F13R1_FB11

#define CAN_F13R1_FB11 CAN_F13R1_FB11_Msk

Filter bit 11

◆ CAN_F13R1_FB11_Msk

#define CAN_F13R1_FB11_Msk (0x1UL << CAN_F13R1_FB11_Pos)

0x00000800

◆ CAN_F13R1_FB11_Pos

#define CAN_F13R1_FB11_Pos (11U)

◆ CAN_F13R1_FB12

#define CAN_F13R1_FB12 CAN_F13R1_FB12_Msk

Filter bit 12

◆ CAN_F13R1_FB12_Msk

#define CAN_F13R1_FB12_Msk (0x1UL << CAN_F13R1_FB12_Pos)

0x00001000

◆ CAN_F13R1_FB12_Pos

#define CAN_F13R1_FB12_Pos (12U)

◆ CAN_F13R1_FB13

#define CAN_F13R1_FB13 CAN_F13R1_FB13_Msk

Filter bit 13

◆ CAN_F13R1_FB13_Msk

#define CAN_F13R1_FB13_Msk (0x1UL << CAN_F13R1_FB13_Pos)

0x00002000

◆ CAN_F13R1_FB13_Pos

#define CAN_F13R1_FB13_Pos (13U)

◆ CAN_F13R1_FB14

#define CAN_F13R1_FB14 CAN_F13R1_FB14_Msk

Filter bit 14

◆ CAN_F13R1_FB14_Msk

#define CAN_F13R1_FB14_Msk (0x1UL << CAN_F13R1_FB14_Pos)

0x00004000

◆ CAN_F13R1_FB14_Pos

#define CAN_F13R1_FB14_Pos (14U)

◆ CAN_F13R1_FB15

#define CAN_F13R1_FB15 CAN_F13R1_FB15_Msk

Filter bit 15

◆ CAN_F13R1_FB15_Msk

#define CAN_F13R1_FB15_Msk (0x1UL << CAN_F13R1_FB15_Pos)

0x00008000

◆ CAN_F13R1_FB15_Pos

#define CAN_F13R1_FB15_Pos (15U)

◆ CAN_F13R1_FB16

#define CAN_F13R1_FB16 CAN_F13R1_FB16_Msk

Filter bit 16

◆ CAN_F13R1_FB16_Msk

#define CAN_F13R1_FB16_Msk (0x1UL << CAN_F13R1_FB16_Pos)

0x00010000

◆ CAN_F13R1_FB16_Pos

#define CAN_F13R1_FB16_Pos (16U)

◆ CAN_F13R1_FB17

#define CAN_F13R1_FB17 CAN_F13R1_FB17_Msk

Filter bit 17

◆ CAN_F13R1_FB17_Msk

#define CAN_F13R1_FB17_Msk (0x1UL << CAN_F13R1_FB17_Pos)

0x00020000

◆ CAN_F13R1_FB17_Pos

#define CAN_F13R1_FB17_Pos (17U)

◆ CAN_F13R1_FB18

#define CAN_F13R1_FB18 CAN_F13R1_FB18_Msk

Filter bit 18

◆ CAN_F13R1_FB18_Msk

#define CAN_F13R1_FB18_Msk (0x1UL << CAN_F13R1_FB18_Pos)

0x00040000

◆ CAN_F13R1_FB18_Pos

#define CAN_F13R1_FB18_Pos (18U)

◆ CAN_F13R1_FB19

#define CAN_F13R1_FB19 CAN_F13R1_FB19_Msk

Filter bit 19

◆ CAN_F13R1_FB19_Msk

#define CAN_F13R1_FB19_Msk (0x1UL << CAN_F13R1_FB19_Pos)

0x00080000

◆ CAN_F13R1_FB19_Pos

#define CAN_F13R1_FB19_Pos (19U)

◆ CAN_F13R1_FB1_Msk

#define CAN_F13R1_FB1_Msk (0x1UL << CAN_F13R1_FB1_Pos)

0x00000002

◆ CAN_F13R1_FB1_Pos

#define CAN_F13R1_FB1_Pos (1U)

◆ CAN_F13R1_FB2

#define CAN_F13R1_FB2 CAN_F13R1_FB2_Msk

Filter bit 2

◆ CAN_F13R1_FB20

#define CAN_F13R1_FB20 CAN_F13R1_FB20_Msk

Filter bit 20

◆ CAN_F13R1_FB20_Msk

#define CAN_F13R1_FB20_Msk (0x1UL << CAN_F13R1_FB20_Pos)

0x00100000

◆ CAN_F13R1_FB20_Pos

#define CAN_F13R1_FB20_Pos (20U)

◆ CAN_F13R1_FB21

#define CAN_F13R1_FB21 CAN_F13R1_FB21_Msk

Filter bit 21

◆ CAN_F13R1_FB21_Msk

#define CAN_F13R1_FB21_Msk (0x1UL << CAN_F13R1_FB21_Pos)

0x00200000

◆ CAN_F13R1_FB21_Pos

#define CAN_F13R1_FB21_Pos (21U)

◆ CAN_F13R1_FB22

#define CAN_F13R1_FB22 CAN_F13R1_FB22_Msk

Filter bit 22

◆ CAN_F13R1_FB22_Msk

#define CAN_F13R1_FB22_Msk (0x1UL << CAN_F13R1_FB22_Pos)

0x00400000

◆ CAN_F13R1_FB22_Pos

#define CAN_F13R1_FB22_Pos (22U)

◆ CAN_F13R1_FB23

#define CAN_F13R1_FB23 CAN_F13R1_FB23_Msk

Filter bit 23

◆ CAN_F13R1_FB23_Msk

#define CAN_F13R1_FB23_Msk (0x1UL << CAN_F13R1_FB23_Pos)

0x00800000

◆ CAN_F13R1_FB23_Pos

#define CAN_F13R1_FB23_Pos (23U)

◆ CAN_F13R1_FB24

#define CAN_F13R1_FB24 CAN_F13R1_FB24_Msk

Filter bit 24

◆ CAN_F13R1_FB24_Msk

#define CAN_F13R1_FB24_Msk (0x1UL << CAN_F13R1_FB24_Pos)

0x01000000

◆ CAN_F13R1_FB24_Pos

#define CAN_F13R1_FB24_Pos (24U)

◆ CAN_F13R1_FB25

#define CAN_F13R1_FB25 CAN_F13R1_FB25_Msk

Filter bit 25

◆ CAN_F13R1_FB25_Msk

#define CAN_F13R1_FB25_Msk (0x1UL << CAN_F13R1_FB25_Pos)

0x02000000

◆ CAN_F13R1_FB25_Pos

#define CAN_F13R1_FB25_Pos (25U)

◆ CAN_F13R1_FB26

#define CAN_F13R1_FB26 CAN_F13R1_FB26_Msk

Filter bit 26

◆ CAN_F13R1_FB26_Msk

#define CAN_F13R1_FB26_Msk (0x1UL << CAN_F13R1_FB26_Pos)

0x04000000

◆ CAN_F13R1_FB26_Pos

#define CAN_F13R1_FB26_Pos (26U)

◆ CAN_F13R1_FB27

#define CAN_F13R1_FB27 CAN_F13R1_FB27_Msk

Filter bit 27

◆ CAN_F13R1_FB27_Msk

#define CAN_F13R1_FB27_Msk (0x1UL << CAN_F13R1_FB27_Pos)

0x08000000

◆ CAN_F13R1_FB27_Pos

#define CAN_F13R1_FB27_Pos (27U)

◆ CAN_F13R1_FB28

#define CAN_F13R1_FB28 CAN_F13R1_FB28_Msk

Filter bit 28

◆ CAN_F13R1_FB28_Msk

#define CAN_F13R1_FB28_Msk (0x1UL << CAN_F13R1_FB28_Pos)

0x10000000

◆ CAN_F13R1_FB28_Pos

#define CAN_F13R1_FB28_Pos (28U)

◆ CAN_F13R1_FB29

#define CAN_F13R1_FB29 CAN_F13R1_FB29_Msk

Filter bit 29

◆ CAN_F13R1_FB29_Msk

#define CAN_F13R1_FB29_Msk (0x1UL << CAN_F13R1_FB29_Pos)

0x20000000

◆ CAN_F13R1_FB29_Pos

#define CAN_F13R1_FB29_Pos (29U)

◆ CAN_F13R1_FB2_Msk

#define CAN_F13R1_FB2_Msk (0x1UL << CAN_F13R1_FB2_Pos)

0x00000004

◆ CAN_F13R1_FB2_Pos

#define CAN_F13R1_FB2_Pos (2U)

◆ CAN_F13R1_FB3

#define CAN_F13R1_FB3 CAN_F13R1_FB3_Msk

Filter bit 3

◆ CAN_F13R1_FB30

#define CAN_F13R1_FB30 CAN_F13R1_FB30_Msk

Filter bit 30

◆ CAN_F13R1_FB30_Msk

#define CAN_F13R1_FB30_Msk (0x1UL << CAN_F13R1_FB30_Pos)

0x40000000

◆ CAN_F13R1_FB30_Pos

#define CAN_F13R1_FB30_Pos (30U)

◆ CAN_F13R1_FB31

#define CAN_F13R1_FB31 CAN_F13R1_FB31_Msk

Filter bit 31

◆ CAN_F13R1_FB31_Msk

#define CAN_F13R1_FB31_Msk (0x1UL << CAN_F13R1_FB31_Pos)

0x80000000

◆ CAN_F13R1_FB31_Pos

#define CAN_F13R1_FB31_Pos (31U)

◆ CAN_F13R1_FB3_Msk

#define CAN_F13R1_FB3_Msk (0x1UL << CAN_F13R1_FB3_Pos)

0x00000008

◆ CAN_F13R1_FB3_Pos

#define CAN_F13R1_FB3_Pos (3U)

◆ CAN_F13R1_FB4

#define CAN_F13R1_FB4 CAN_F13R1_FB4_Msk

Filter bit 4

◆ CAN_F13R1_FB4_Msk

#define CAN_F13R1_FB4_Msk (0x1UL << CAN_F13R1_FB4_Pos)

0x00000010

◆ CAN_F13R1_FB4_Pos

#define CAN_F13R1_FB4_Pos (4U)

◆ CAN_F13R1_FB5

#define CAN_F13R1_FB5 CAN_F13R1_FB5_Msk

Filter bit 5

◆ CAN_F13R1_FB5_Msk

#define CAN_F13R1_FB5_Msk (0x1UL << CAN_F13R1_FB5_Pos)

0x00000020

◆ CAN_F13R1_FB5_Pos

#define CAN_F13R1_FB5_Pos (5U)

◆ CAN_F13R1_FB6

#define CAN_F13R1_FB6 CAN_F13R1_FB6_Msk

Filter bit 6

◆ CAN_F13R1_FB6_Msk

#define CAN_F13R1_FB6_Msk (0x1UL << CAN_F13R1_FB6_Pos)

0x00000040

◆ CAN_F13R1_FB6_Pos

#define CAN_F13R1_FB6_Pos (6U)

◆ CAN_F13R1_FB7

#define CAN_F13R1_FB7 CAN_F13R1_FB7_Msk

Filter bit 7

◆ CAN_F13R1_FB7_Msk

#define CAN_F13R1_FB7_Msk (0x1UL << CAN_F13R1_FB7_Pos)

0x00000080

◆ CAN_F13R1_FB7_Pos

#define CAN_F13R1_FB7_Pos (7U)

◆ CAN_F13R1_FB8

#define CAN_F13R1_FB8 CAN_F13R1_FB8_Msk

Filter bit 8

◆ CAN_F13R1_FB8_Msk

#define CAN_F13R1_FB8_Msk (0x1UL << CAN_F13R1_FB8_Pos)

0x00000100

◆ CAN_F13R1_FB8_Pos

#define CAN_F13R1_FB8_Pos (8U)

◆ CAN_F13R1_FB9

#define CAN_F13R1_FB9 CAN_F13R1_FB9_Msk

Filter bit 9

◆ CAN_F13R1_FB9_Msk

#define CAN_F13R1_FB9_Msk (0x1UL << CAN_F13R1_FB9_Pos)

0x00000200

◆ CAN_F13R1_FB9_Pos

#define CAN_F13R1_FB9_Pos (9U)

◆ CAN_F13R2_FB0

#define CAN_F13R2_FB0 CAN_F13R2_FB0_Msk

Filter bit 0

◆ CAN_F13R2_FB0_Msk

#define CAN_F13R2_FB0_Msk (0x1UL << CAN_F13R2_FB0_Pos)

0x00000001

◆ CAN_F13R2_FB0_Pos

#define CAN_F13R2_FB0_Pos (0U)

◆ CAN_F13R2_FB1

#define CAN_F13R2_FB1 CAN_F13R2_FB1_Msk

Filter bit 1

◆ CAN_F13R2_FB10

#define CAN_F13R2_FB10 CAN_F13R2_FB10_Msk

Filter bit 10

◆ CAN_F13R2_FB10_Msk

#define CAN_F13R2_FB10_Msk (0x1UL << CAN_F13R2_FB10_Pos)

0x00000400

◆ CAN_F13R2_FB10_Pos

#define CAN_F13R2_FB10_Pos (10U)

◆ CAN_F13R2_FB11

#define CAN_F13R2_FB11 CAN_F13R2_FB11_Msk

Filter bit 11

◆ CAN_F13R2_FB11_Msk

#define CAN_F13R2_FB11_Msk (0x1UL << CAN_F13R2_FB11_Pos)

0x00000800

◆ CAN_F13R2_FB11_Pos

#define CAN_F13R2_FB11_Pos (11U)

◆ CAN_F13R2_FB12

#define CAN_F13R2_FB12 CAN_F13R2_FB12_Msk

Filter bit 12

◆ CAN_F13R2_FB12_Msk

#define CAN_F13R2_FB12_Msk (0x1UL << CAN_F13R2_FB12_Pos)

0x00001000

◆ CAN_F13R2_FB12_Pos

#define CAN_F13R2_FB12_Pos (12U)

◆ CAN_F13R2_FB13

#define CAN_F13R2_FB13 CAN_F13R2_FB13_Msk

Filter bit 13

◆ CAN_F13R2_FB13_Msk

#define CAN_F13R2_FB13_Msk (0x1UL << CAN_F13R2_FB13_Pos)

0x00002000

◆ CAN_F13R2_FB13_Pos

#define CAN_F13R2_FB13_Pos (13U)

◆ CAN_F13R2_FB14

#define CAN_F13R2_FB14 CAN_F13R2_FB14_Msk

Filter bit 14

◆ CAN_F13R2_FB14_Msk

#define CAN_F13R2_FB14_Msk (0x1UL << CAN_F13R2_FB14_Pos)

0x00004000

◆ CAN_F13R2_FB14_Pos

#define CAN_F13R2_FB14_Pos (14U)

◆ CAN_F13R2_FB15

#define CAN_F13R2_FB15 CAN_F13R2_FB15_Msk

Filter bit 15

◆ CAN_F13R2_FB15_Msk

#define CAN_F13R2_FB15_Msk (0x1UL << CAN_F13R2_FB15_Pos)

0x00008000

◆ CAN_F13R2_FB15_Pos

#define CAN_F13R2_FB15_Pos (15U)

◆ CAN_F13R2_FB16

#define CAN_F13R2_FB16 CAN_F13R2_FB16_Msk

Filter bit 16

◆ CAN_F13R2_FB16_Msk

#define CAN_F13R2_FB16_Msk (0x1UL << CAN_F13R2_FB16_Pos)

0x00010000

◆ CAN_F13R2_FB16_Pos

#define CAN_F13R2_FB16_Pos (16U)

◆ CAN_F13R2_FB17

#define CAN_F13R2_FB17 CAN_F13R2_FB17_Msk

Filter bit 17

◆ CAN_F13R2_FB17_Msk

#define CAN_F13R2_FB17_Msk (0x1UL << CAN_F13R2_FB17_Pos)

0x00020000

◆ CAN_F13R2_FB17_Pos

#define CAN_F13R2_FB17_Pos (17U)

◆ CAN_F13R2_FB18

#define CAN_F13R2_FB18 CAN_F13R2_FB18_Msk

Filter bit 18

◆ CAN_F13R2_FB18_Msk

#define CAN_F13R2_FB18_Msk (0x1UL << CAN_F13R2_FB18_Pos)

0x00040000

◆ CAN_F13R2_FB18_Pos

#define CAN_F13R2_FB18_Pos (18U)

◆ CAN_F13R2_FB19

#define CAN_F13R2_FB19 CAN_F13R2_FB19_Msk

Filter bit 19

◆ CAN_F13R2_FB19_Msk

#define CAN_F13R2_FB19_Msk (0x1UL << CAN_F13R2_FB19_Pos)

0x00080000

◆ CAN_F13R2_FB19_Pos

#define CAN_F13R2_FB19_Pos (19U)

◆ CAN_F13R2_FB1_Msk

#define CAN_F13R2_FB1_Msk (0x1UL << CAN_F13R2_FB1_Pos)

0x00000002

◆ CAN_F13R2_FB1_Pos

#define CAN_F13R2_FB1_Pos (1U)

◆ CAN_F13R2_FB2

#define CAN_F13R2_FB2 CAN_F13R2_FB2_Msk

Filter bit 2

◆ CAN_F13R2_FB20

#define CAN_F13R2_FB20 CAN_F13R2_FB20_Msk

Filter bit 20

◆ CAN_F13R2_FB20_Msk

#define CAN_F13R2_FB20_Msk (0x1UL << CAN_F13R2_FB20_Pos)

0x00100000

◆ CAN_F13R2_FB20_Pos

#define CAN_F13R2_FB20_Pos (20U)

◆ CAN_F13R2_FB21

#define CAN_F13R2_FB21 CAN_F13R2_FB21_Msk

Filter bit 21

◆ CAN_F13R2_FB21_Msk

#define CAN_F13R2_FB21_Msk (0x1UL << CAN_F13R2_FB21_Pos)

0x00200000

◆ CAN_F13R2_FB21_Pos

#define CAN_F13R2_FB21_Pos (21U)

◆ CAN_F13R2_FB22

#define CAN_F13R2_FB22 CAN_F13R2_FB22_Msk

Filter bit 22

◆ CAN_F13R2_FB22_Msk

#define CAN_F13R2_FB22_Msk (0x1UL << CAN_F13R2_FB22_Pos)

0x00400000

◆ CAN_F13R2_FB22_Pos

#define CAN_F13R2_FB22_Pos (22U)

◆ CAN_F13R2_FB23

#define CAN_F13R2_FB23 CAN_F13R2_FB23_Msk

Filter bit 23

◆ CAN_F13R2_FB23_Msk

#define CAN_F13R2_FB23_Msk (0x1UL << CAN_F13R2_FB23_Pos)

0x00800000

◆ CAN_F13R2_FB23_Pos

#define CAN_F13R2_FB23_Pos (23U)

◆ CAN_F13R2_FB24

#define CAN_F13R2_FB24 CAN_F13R2_FB24_Msk

Filter bit 24

◆ CAN_F13R2_FB24_Msk

#define CAN_F13R2_FB24_Msk (0x1UL << CAN_F13R2_FB24_Pos)

0x01000000

◆ CAN_F13R2_FB24_Pos

#define CAN_F13R2_FB24_Pos (24U)

◆ CAN_F13R2_FB25

#define CAN_F13R2_FB25 CAN_F13R2_FB25_Msk

Filter bit 25

◆ CAN_F13R2_FB25_Msk

#define CAN_F13R2_FB25_Msk (0x1UL << CAN_F13R2_FB25_Pos)

0x02000000

◆ CAN_F13R2_FB25_Pos

#define CAN_F13R2_FB25_Pos (25U)

◆ CAN_F13R2_FB26

#define CAN_F13R2_FB26 CAN_F13R2_FB26_Msk

Filter bit 26

◆ CAN_F13R2_FB26_Msk

#define CAN_F13R2_FB26_Msk (0x1UL << CAN_F13R2_FB26_Pos)

0x04000000

◆ CAN_F13R2_FB26_Pos

#define CAN_F13R2_FB26_Pos (26U)

◆ CAN_F13R2_FB27

#define CAN_F13R2_FB27 CAN_F13R2_FB27_Msk

Filter bit 27

◆ CAN_F13R2_FB27_Msk

#define CAN_F13R2_FB27_Msk (0x1UL << CAN_F13R2_FB27_Pos)

0x08000000

◆ CAN_F13R2_FB27_Pos

#define CAN_F13R2_FB27_Pos (27U)

◆ CAN_F13R2_FB28

#define CAN_F13R2_FB28 CAN_F13R2_FB28_Msk

Filter bit 28

◆ CAN_F13R2_FB28_Msk

#define CAN_F13R2_FB28_Msk (0x1UL << CAN_F13R2_FB28_Pos)

0x10000000

◆ CAN_F13R2_FB28_Pos

#define CAN_F13R2_FB28_Pos (28U)

◆ CAN_F13R2_FB29

#define CAN_F13R2_FB29 CAN_F13R2_FB29_Msk

Filter bit 29

◆ CAN_F13R2_FB29_Msk

#define CAN_F13R2_FB29_Msk (0x1UL << CAN_F13R2_FB29_Pos)

0x20000000

◆ CAN_F13R2_FB29_Pos

#define CAN_F13R2_FB29_Pos (29U)

◆ CAN_F13R2_FB2_Msk

#define CAN_F13R2_FB2_Msk (0x1UL << CAN_F13R2_FB2_Pos)

0x00000004

◆ CAN_F13R2_FB2_Pos

#define CAN_F13R2_FB2_Pos (2U)

◆ CAN_F13R2_FB3

#define CAN_F13R2_FB3 CAN_F13R2_FB3_Msk

Filter bit 3

◆ CAN_F13R2_FB30

#define CAN_F13R2_FB30 CAN_F13R2_FB30_Msk

Filter bit 30

◆ CAN_F13R2_FB30_Msk

#define CAN_F13R2_FB30_Msk (0x1UL << CAN_F13R2_FB30_Pos)

0x40000000

◆ CAN_F13R2_FB30_Pos

#define CAN_F13R2_FB30_Pos (30U)

◆ CAN_F13R2_FB31

#define CAN_F13R2_FB31 CAN_F13R2_FB31_Msk

Filter bit 31

◆ CAN_F13R2_FB31_Msk

#define CAN_F13R2_FB31_Msk (0x1UL << CAN_F13R2_FB31_Pos)

0x80000000

◆ CAN_F13R2_FB31_Pos

#define CAN_F13R2_FB31_Pos (31U)

◆ CAN_F13R2_FB3_Msk

#define CAN_F13R2_FB3_Msk (0x1UL << CAN_F13R2_FB3_Pos)

0x00000008

◆ CAN_F13R2_FB3_Pos

#define CAN_F13R2_FB3_Pos (3U)

◆ CAN_F13R2_FB4

#define CAN_F13R2_FB4 CAN_F13R2_FB4_Msk

Filter bit 4

◆ CAN_F13R2_FB4_Msk

#define CAN_F13R2_FB4_Msk (0x1UL << CAN_F13R2_FB4_Pos)

0x00000010

◆ CAN_F13R2_FB4_Pos

#define CAN_F13R2_FB4_Pos (4U)

◆ CAN_F13R2_FB5

#define CAN_F13R2_FB5 CAN_F13R2_FB5_Msk

Filter bit 5

◆ CAN_F13R2_FB5_Msk

#define CAN_F13R2_FB5_Msk (0x1UL << CAN_F13R2_FB5_Pos)

0x00000020

◆ CAN_F13R2_FB5_Pos

#define CAN_F13R2_FB5_Pos (5U)

◆ CAN_F13R2_FB6

#define CAN_F13R2_FB6 CAN_F13R2_FB6_Msk

Filter bit 6

◆ CAN_F13R2_FB6_Msk

#define CAN_F13R2_FB6_Msk (0x1UL << CAN_F13R2_FB6_Pos)

0x00000040

◆ CAN_F13R2_FB6_Pos

#define CAN_F13R2_FB6_Pos (6U)

◆ CAN_F13R2_FB7

#define CAN_F13R2_FB7 CAN_F13R2_FB7_Msk

Filter bit 7

◆ CAN_F13R2_FB7_Msk

#define CAN_F13R2_FB7_Msk (0x1UL << CAN_F13R2_FB7_Pos)

0x00000080

◆ CAN_F13R2_FB7_Pos

#define CAN_F13R2_FB7_Pos (7U)

◆ CAN_F13R2_FB8

#define CAN_F13R2_FB8 CAN_F13R2_FB8_Msk

Filter bit 8

◆ CAN_F13R2_FB8_Msk

#define CAN_F13R2_FB8_Msk (0x1UL << CAN_F13R2_FB8_Pos)

0x00000100

◆ CAN_F13R2_FB8_Pos

#define CAN_F13R2_FB8_Pos (8U)

◆ CAN_F13R2_FB9

#define CAN_F13R2_FB9 CAN_F13R2_FB9_Msk

Filter bit 9

◆ CAN_F13R2_FB9_Msk

#define CAN_F13R2_FB9_Msk (0x1UL << CAN_F13R2_FB9_Pos)

0x00000200

◆ CAN_F13R2_FB9_Pos

#define CAN_F13R2_FB9_Pos (9U)

◆ CAN_F1R1_FB0

#define CAN_F1R1_FB0 CAN_F1R1_FB0_Msk

Filter bit 0

◆ CAN_F1R1_FB0_Msk

#define CAN_F1R1_FB0_Msk (0x1UL << CAN_F1R1_FB0_Pos)

0x00000001

◆ CAN_F1R1_FB0_Pos

#define CAN_F1R1_FB0_Pos (0U)

◆ CAN_F1R1_FB1

#define CAN_F1R1_FB1 CAN_F1R1_FB1_Msk

Filter bit 1

◆ CAN_F1R1_FB10

#define CAN_F1R1_FB10 CAN_F1R1_FB10_Msk

Filter bit 10

◆ CAN_F1R1_FB10_Msk

#define CAN_F1R1_FB10_Msk (0x1UL << CAN_F1R1_FB10_Pos)

0x00000400

◆ CAN_F1R1_FB10_Pos

#define CAN_F1R1_FB10_Pos (10U)

◆ CAN_F1R1_FB11

#define CAN_F1R1_FB11 CAN_F1R1_FB11_Msk

Filter bit 11

◆ CAN_F1R1_FB11_Msk

#define CAN_F1R1_FB11_Msk (0x1UL << CAN_F1R1_FB11_Pos)

0x00000800

◆ CAN_F1R1_FB11_Pos

#define CAN_F1R1_FB11_Pos (11U)

◆ CAN_F1R1_FB12

#define CAN_F1R1_FB12 CAN_F1R1_FB12_Msk

Filter bit 12

◆ CAN_F1R1_FB12_Msk

#define CAN_F1R1_FB12_Msk (0x1UL << CAN_F1R1_FB12_Pos)

0x00001000

◆ CAN_F1R1_FB12_Pos

#define CAN_F1R1_FB12_Pos (12U)

◆ CAN_F1R1_FB13

#define CAN_F1R1_FB13 CAN_F1R1_FB13_Msk

Filter bit 13

◆ CAN_F1R1_FB13_Msk

#define CAN_F1R1_FB13_Msk (0x1UL << CAN_F1R1_FB13_Pos)

0x00002000

◆ CAN_F1R1_FB13_Pos

#define CAN_F1R1_FB13_Pos (13U)

◆ CAN_F1R1_FB14

#define CAN_F1R1_FB14 CAN_F1R1_FB14_Msk

Filter bit 14

◆ CAN_F1R1_FB14_Msk

#define CAN_F1R1_FB14_Msk (0x1UL << CAN_F1R1_FB14_Pos)

0x00004000

◆ CAN_F1R1_FB14_Pos

#define CAN_F1R1_FB14_Pos (14U)

◆ CAN_F1R1_FB15

#define CAN_F1R1_FB15 CAN_F1R1_FB15_Msk

Filter bit 15

◆ CAN_F1R1_FB15_Msk

#define CAN_F1R1_FB15_Msk (0x1UL << CAN_F1R1_FB15_Pos)

0x00008000

◆ CAN_F1R1_FB15_Pos

#define CAN_F1R1_FB15_Pos (15U)

◆ CAN_F1R1_FB16

#define CAN_F1R1_FB16 CAN_F1R1_FB16_Msk

Filter bit 16

◆ CAN_F1R1_FB16_Msk

#define CAN_F1R1_FB16_Msk (0x1UL << CAN_F1R1_FB16_Pos)

0x00010000

◆ CAN_F1R1_FB16_Pos

#define CAN_F1R1_FB16_Pos (16U)

◆ CAN_F1R1_FB17

#define CAN_F1R1_FB17 CAN_F1R1_FB17_Msk

Filter bit 17

◆ CAN_F1R1_FB17_Msk

#define CAN_F1R1_FB17_Msk (0x1UL << CAN_F1R1_FB17_Pos)

0x00020000

◆ CAN_F1R1_FB17_Pos

#define CAN_F1R1_FB17_Pos (17U)

◆ CAN_F1R1_FB18

#define CAN_F1R1_FB18 CAN_F1R1_FB18_Msk

Filter bit 18

◆ CAN_F1R1_FB18_Msk

#define CAN_F1R1_FB18_Msk (0x1UL << CAN_F1R1_FB18_Pos)

0x00040000

◆ CAN_F1R1_FB18_Pos

#define CAN_F1R1_FB18_Pos (18U)

◆ CAN_F1R1_FB19

#define CAN_F1R1_FB19 CAN_F1R1_FB19_Msk

Filter bit 19

◆ CAN_F1R1_FB19_Msk

#define CAN_F1R1_FB19_Msk (0x1UL << CAN_F1R1_FB19_Pos)

0x00080000

◆ CAN_F1R1_FB19_Pos

#define CAN_F1R1_FB19_Pos (19U)

◆ CAN_F1R1_FB1_Msk

#define CAN_F1R1_FB1_Msk (0x1UL << CAN_F1R1_FB1_Pos)

0x00000002

◆ CAN_F1R1_FB1_Pos

#define CAN_F1R1_FB1_Pos (1U)

◆ CAN_F1R1_FB2

#define CAN_F1R1_FB2 CAN_F1R1_FB2_Msk

Filter bit 2

◆ CAN_F1R1_FB20

#define CAN_F1R1_FB20 CAN_F1R1_FB20_Msk

Filter bit 20

◆ CAN_F1R1_FB20_Msk

#define CAN_F1R1_FB20_Msk (0x1UL << CAN_F1R1_FB20_Pos)

0x00100000

◆ CAN_F1R1_FB20_Pos

#define CAN_F1R1_FB20_Pos (20U)

◆ CAN_F1R1_FB21

#define CAN_F1R1_FB21 CAN_F1R1_FB21_Msk

Filter bit 21

◆ CAN_F1R1_FB21_Msk

#define CAN_F1R1_FB21_Msk (0x1UL << CAN_F1R1_FB21_Pos)

0x00200000

◆ CAN_F1R1_FB21_Pos

#define CAN_F1R1_FB21_Pos (21U)

◆ CAN_F1R1_FB22

#define CAN_F1R1_FB22 CAN_F1R1_FB22_Msk

Filter bit 22

◆ CAN_F1R1_FB22_Msk

#define CAN_F1R1_FB22_Msk (0x1UL << CAN_F1R1_FB22_Pos)

0x00400000

◆ CAN_F1R1_FB22_Pos

#define CAN_F1R1_FB22_Pos (22U)

◆ CAN_F1R1_FB23

#define CAN_F1R1_FB23 CAN_F1R1_FB23_Msk

Filter bit 23

◆ CAN_F1R1_FB23_Msk

#define CAN_F1R1_FB23_Msk (0x1UL << CAN_F1R1_FB23_Pos)

0x00800000

◆ CAN_F1R1_FB23_Pos

#define CAN_F1R1_FB23_Pos (23U)

◆ CAN_F1R1_FB24

#define CAN_F1R1_FB24 CAN_F1R1_FB24_Msk

Filter bit 24

◆ CAN_F1R1_FB24_Msk

#define CAN_F1R1_FB24_Msk (0x1UL << CAN_F1R1_FB24_Pos)

0x01000000

◆ CAN_F1R1_FB24_Pos

#define CAN_F1R1_FB24_Pos (24U)

◆ CAN_F1R1_FB25

#define CAN_F1R1_FB25 CAN_F1R1_FB25_Msk

Filter bit 25

◆ CAN_F1R1_FB25_Msk

#define CAN_F1R1_FB25_Msk (0x1UL << CAN_F1R1_FB25_Pos)

0x02000000

◆ CAN_F1R1_FB25_Pos

#define CAN_F1R1_FB25_Pos (25U)

◆ CAN_F1R1_FB26

#define CAN_F1R1_FB26 CAN_F1R1_FB26_Msk

Filter bit 26

◆ CAN_F1R1_FB26_Msk

#define CAN_F1R1_FB26_Msk (0x1UL << CAN_F1R1_FB26_Pos)

0x04000000

◆ CAN_F1R1_FB26_Pos

#define CAN_F1R1_FB26_Pos (26U)

◆ CAN_F1R1_FB27

#define CAN_F1R1_FB27 CAN_F1R1_FB27_Msk

Filter bit 27

◆ CAN_F1R1_FB27_Msk

#define CAN_F1R1_FB27_Msk (0x1UL << CAN_F1R1_FB27_Pos)

0x08000000

◆ CAN_F1R1_FB27_Pos

#define CAN_F1R1_FB27_Pos (27U)

◆ CAN_F1R1_FB28

#define CAN_F1R1_FB28 CAN_F1R1_FB28_Msk

Filter bit 28

◆ CAN_F1R1_FB28_Msk

#define CAN_F1R1_FB28_Msk (0x1UL << CAN_F1R1_FB28_Pos)

0x10000000

◆ CAN_F1R1_FB28_Pos

#define CAN_F1R1_FB28_Pos (28U)

◆ CAN_F1R1_FB29

#define CAN_F1R1_FB29 CAN_F1R1_FB29_Msk

Filter bit 29

◆ CAN_F1R1_FB29_Msk

#define CAN_F1R1_FB29_Msk (0x1UL << CAN_F1R1_FB29_Pos)

0x20000000

◆ CAN_F1R1_FB29_Pos

#define CAN_F1R1_FB29_Pos (29U)

◆ CAN_F1R1_FB2_Msk

#define CAN_F1R1_FB2_Msk (0x1UL << CAN_F1R1_FB2_Pos)

0x00000004

◆ CAN_F1R1_FB2_Pos

#define CAN_F1R1_FB2_Pos (2U)

◆ CAN_F1R1_FB3

#define CAN_F1R1_FB3 CAN_F1R1_FB3_Msk

Filter bit 3

◆ CAN_F1R1_FB30

#define CAN_F1R1_FB30 CAN_F1R1_FB30_Msk

Filter bit 30

◆ CAN_F1R1_FB30_Msk

#define CAN_F1R1_FB30_Msk (0x1UL << CAN_F1R1_FB30_Pos)

0x40000000

◆ CAN_F1R1_FB30_Pos

#define CAN_F1R1_FB30_Pos (30U)

◆ CAN_F1R1_FB31

#define CAN_F1R1_FB31 CAN_F1R1_FB31_Msk

Filter bit 31

◆ CAN_F1R1_FB31_Msk

#define CAN_F1R1_FB31_Msk (0x1UL << CAN_F1R1_FB31_Pos)

0x80000000

◆ CAN_F1R1_FB31_Pos

#define CAN_F1R1_FB31_Pos (31U)

◆ CAN_F1R1_FB3_Msk

#define CAN_F1R1_FB3_Msk (0x1UL << CAN_F1R1_FB3_Pos)

0x00000008

◆ CAN_F1R1_FB3_Pos

#define CAN_F1R1_FB3_Pos (3U)

◆ CAN_F1R1_FB4

#define CAN_F1R1_FB4 CAN_F1R1_FB4_Msk

Filter bit 4

◆ CAN_F1R1_FB4_Msk

#define CAN_F1R1_FB4_Msk (0x1UL << CAN_F1R1_FB4_Pos)

0x00000010

◆ CAN_F1R1_FB4_Pos

#define CAN_F1R1_FB4_Pos (4U)

◆ CAN_F1R1_FB5

#define CAN_F1R1_FB5 CAN_F1R1_FB5_Msk

Filter bit 5

◆ CAN_F1R1_FB5_Msk

#define CAN_F1R1_FB5_Msk (0x1UL << CAN_F1R1_FB5_Pos)

0x00000020

◆ CAN_F1R1_FB5_Pos

#define CAN_F1R1_FB5_Pos (5U)

◆ CAN_F1R1_FB6

#define CAN_F1R1_FB6 CAN_F1R1_FB6_Msk

Filter bit 6

◆ CAN_F1R1_FB6_Msk

#define CAN_F1R1_FB6_Msk (0x1UL << CAN_F1R1_FB6_Pos)

0x00000040

◆ CAN_F1R1_FB6_Pos

#define CAN_F1R1_FB6_Pos (6U)

◆ CAN_F1R1_FB7

#define CAN_F1R1_FB7 CAN_F1R1_FB7_Msk

Filter bit 7

◆ CAN_F1R1_FB7_Msk

#define CAN_F1R1_FB7_Msk (0x1UL << CAN_F1R1_FB7_Pos)

0x00000080

◆ CAN_F1R1_FB7_Pos

#define CAN_F1R1_FB7_Pos (7U)

◆ CAN_F1R1_FB8

#define CAN_F1R1_FB8 CAN_F1R1_FB8_Msk

Filter bit 8

◆ CAN_F1R1_FB8_Msk

#define CAN_F1R1_FB8_Msk (0x1UL << CAN_F1R1_FB8_Pos)

0x00000100

◆ CAN_F1R1_FB8_Pos

#define CAN_F1R1_FB8_Pos (8U)

◆ CAN_F1R1_FB9

#define CAN_F1R1_FB9 CAN_F1R1_FB9_Msk

Filter bit 9

◆ CAN_F1R1_FB9_Msk

#define CAN_F1R1_FB9_Msk (0x1UL << CAN_F1R1_FB9_Pos)

0x00000200

◆ CAN_F1R1_FB9_Pos

#define CAN_F1R1_FB9_Pos (9U)

◆ CAN_F1R2_FB0

#define CAN_F1R2_FB0 CAN_F1R2_FB0_Msk

Filter bit 0

◆ CAN_F1R2_FB0_Msk

#define CAN_F1R2_FB0_Msk (0x1UL << CAN_F1R2_FB0_Pos)

0x00000001

◆ CAN_F1R2_FB0_Pos

#define CAN_F1R2_FB0_Pos (0U)

◆ CAN_F1R2_FB1

#define CAN_F1R2_FB1 CAN_F1R2_FB1_Msk

Filter bit 1

◆ CAN_F1R2_FB10

#define CAN_F1R2_FB10 CAN_F1R2_FB10_Msk

Filter bit 10

◆ CAN_F1R2_FB10_Msk

#define CAN_F1R2_FB10_Msk (0x1UL << CAN_F1R2_FB10_Pos)

0x00000400

◆ CAN_F1R2_FB10_Pos

#define CAN_F1R2_FB10_Pos (10U)

◆ CAN_F1R2_FB11

#define CAN_F1R2_FB11 CAN_F1R2_FB11_Msk

Filter bit 11

◆ CAN_F1R2_FB11_Msk

#define CAN_F1R2_FB11_Msk (0x1UL << CAN_F1R2_FB11_Pos)

0x00000800

◆ CAN_F1R2_FB11_Pos

#define CAN_F1R2_FB11_Pos (11U)

◆ CAN_F1R2_FB12

#define CAN_F1R2_FB12 CAN_F1R2_FB12_Msk

Filter bit 12

◆ CAN_F1R2_FB12_Msk

#define CAN_F1R2_FB12_Msk (0x1UL << CAN_F1R2_FB12_Pos)

0x00001000

◆ CAN_F1R2_FB12_Pos

#define CAN_F1R2_FB12_Pos (12U)

◆ CAN_F1R2_FB13

#define CAN_F1R2_FB13 CAN_F1R2_FB13_Msk

Filter bit 13

◆ CAN_F1R2_FB13_Msk

#define CAN_F1R2_FB13_Msk (0x1UL << CAN_F1R2_FB13_Pos)

0x00002000

◆ CAN_F1R2_FB13_Pos

#define CAN_F1R2_FB13_Pos (13U)

◆ CAN_F1R2_FB14

#define CAN_F1R2_FB14 CAN_F1R2_FB14_Msk

Filter bit 14

◆ CAN_F1R2_FB14_Msk

#define CAN_F1R2_FB14_Msk (0x1UL << CAN_F1R2_FB14_Pos)

0x00004000

◆ CAN_F1R2_FB14_Pos

#define CAN_F1R2_FB14_Pos (14U)

◆ CAN_F1R2_FB15

#define CAN_F1R2_FB15 CAN_F1R2_FB15_Msk

Filter bit 15

◆ CAN_F1R2_FB15_Msk

#define CAN_F1R2_FB15_Msk (0x1UL << CAN_F1R2_FB15_Pos)

0x00008000

◆ CAN_F1R2_FB15_Pos

#define CAN_F1R2_FB15_Pos (15U)

◆ CAN_F1R2_FB16

#define CAN_F1R2_FB16 CAN_F1R2_FB16_Msk

Filter bit 16

◆ CAN_F1R2_FB16_Msk

#define CAN_F1R2_FB16_Msk (0x1UL << CAN_F1R2_FB16_Pos)

0x00010000

◆ CAN_F1R2_FB16_Pos

#define CAN_F1R2_FB16_Pos (16U)

◆ CAN_F1R2_FB17

#define CAN_F1R2_FB17 CAN_F1R2_FB17_Msk

Filter bit 17

◆ CAN_F1R2_FB17_Msk

#define CAN_F1R2_FB17_Msk (0x1UL << CAN_F1R2_FB17_Pos)

0x00020000

◆ CAN_F1R2_FB17_Pos

#define CAN_F1R2_FB17_Pos (17U)

◆ CAN_F1R2_FB18

#define CAN_F1R2_FB18 CAN_F1R2_FB18_Msk

Filter bit 18

◆ CAN_F1R2_FB18_Msk

#define CAN_F1R2_FB18_Msk (0x1UL << CAN_F1R2_FB18_Pos)

0x00040000

◆ CAN_F1R2_FB18_Pos

#define CAN_F1R2_FB18_Pos (18U)

◆ CAN_F1R2_FB19

#define CAN_F1R2_FB19 CAN_F1R2_FB19_Msk

Filter bit 19

◆ CAN_F1R2_FB19_Msk

#define CAN_F1R2_FB19_Msk (0x1UL << CAN_F1R2_FB19_Pos)

0x00080000

◆ CAN_F1R2_FB19_Pos

#define CAN_F1R2_FB19_Pos (19U)

◆ CAN_F1R2_FB1_Msk

#define CAN_F1R2_FB1_Msk (0x1UL << CAN_F1R2_FB1_Pos)

0x00000002

◆ CAN_F1R2_FB1_Pos

#define CAN_F1R2_FB1_Pos (1U)

◆ CAN_F1R2_FB2

#define CAN_F1R2_FB2 CAN_F1R2_FB2_Msk

Filter bit 2

◆ CAN_F1R2_FB20

#define CAN_F1R2_FB20 CAN_F1R2_FB20_Msk

Filter bit 20

◆ CAN_F1R2_FB20_Msk

#define CAN_F1R2_FB20_Msk (0x1UL << CAN_F1R2_FB20_Pos)

0x00100000

◆ CAN_F1R2_FB20_Pos

#define CAN_F1R2_FB20_Pos (20U)

◆ CAN_F1R2_FB21

#define CAN_F1R2_FB21 CAN_F1R2_FB21_Msk

Filter bit 21

◆ CAN_F1R2_FB21_Msk

#define CAN_F1R2_FB21_Msk (0x1UL << CAN_F1R2_FB21_Pos)

0x00200000

◆ CAN_F1R2_FB21_Pos

#define CAN_F1R2_FB21_Pos (21U)

◆ CAN_F1R2_FB22

#define CAN_F1R2_FB22 CAN_F1R2_FB22_Msk

Filter bit 22

◆ CAN_F1R2_FB22_Msk

#define CAN_F1R2_FB22_Msk (0x1UL << CAN_F1R2_FB22_Pos)

0x00400000

◆ CAN_F1R2_FB22_Pos

#define CAN_F1R2_FB22_Pos (22U)

◆ CAN_F1R2_FB23

#define CAN_F1R2_FB23 CAN_F1R2_FB23_Msk

Filter bit 23

◆ CAN_F1R2_FB23_Msk

#define CAN_F1R2_FB23_Msk (0x1UL << CAN_F1R2_FB23_Pos)

0x00800000

◆ CAN_F1R2_FB23_Pos

#define CAN_F1R2_FB23_Pos (23U)

◆ CAN_F1R2_FB24

#define CAN_F1R2_FB24 CAN_F1R2_FB24_Msk

Filter bit 24

◆ CAN_F1R2_FB24_Msk

#define CAN_F1R2_FB24_Msk (0x1UL << CAN_F1R2_FB24_Pos)

0x01000000

◆ CAN_F1R2_FB24_Pos

#define CAN_F1R2_FB24_Pos (24U)

◆ CAN_F1R2_FB25

#define CAN_F1R2_FB25 CAN_F1R2_FB25_Msk

Filter bit 25

◆ CAN_F1R2_FB25_Msk

#define CAN_F1R2_FB25_Msk (0x1UL << CAN_F1R2_FB25_Pos)

0x02000000

◆ CAN_F1R2_FB25_Pos

#define CAN_F1R2_FB25_Pos (25U)

◆ CAN_F1R2_FB26

#define CAN_F1R2_FB26 CAN_F1R2_FB26_Msk

Filter bit 26

◆ CAN_F1R2_FB26_Msk

#define CAN_F1R2_FB26_Msk (0x1UL << CAN_F1R2_FB26_Pos)

0x04000000

◆ CAN_F1R2_FB26_Pos

#define CAN_F1R2_FB26_Pos (26U)

◆ CAN_F1R2_FB27

#define CAN_F1R2_FB27 CAN_F1R2_FB27_Msk

Filter bit 27

◆ CAN_F1R2_FB27_Msk

#define CAN_F1R2_FB27_Msk (0x1UL << CAN_F1R2_FB27_Pos)

0x08000000

◆ CAN_F1R2_FB27_Pos

#define CAN_F1R2_FB27_Pos (27U)

◆ CAN_F1R2_FB28

#define CAN_F1R2_FB28 CAN_F1R2_FB28_Msk

Filter bit 28

◆ CAN_F1R2_FB28_Msk

#define CAN_F1R2_FB28_Msk (0x1UL << CAN_F1R2_FB28_Pos)

0x10000000

◆ CAN_F1R2_FB28_Pos

#define CAN_F1R2_FB28_Pos (28U)

◆ CAN_F1R2_FB29

#define CAN_F1R2_FB29 CAN_F1R2_FB29_Msk

Filter bit 29

◆ CAN_F1R2_FB29_Msk

#define CAN_F1R2_FB29_Msk (0x1UL << CAN_F1R2_FB29_Pos)

0x20000000

◆ CAN_F1R2_FB29_Pos

#define CAN_F1R2_FB29_Pos (29U)

◆ CAN_F1R2_FB2_Msk

#define CAN_F1R2_FB2_Msk (0x1UL << CAN_F1R2_FB2_Pos)

0x00000004

◆ CAN_F1R2_FB2_Pos

#define CAN_F1R2_FB2_Pos (2U)

◆ CAN_F1R2_FB3

#define CAN_F1R2_FB3 CAN_F1R2_FB3_Msk

Filter bit 3

◆ CAN_F1R2_FB30

#define CAN_F1R2_FB30 CAN_F1R2_FB30_Msk

Filter bit 30

◆ CAN_F1R2_FB30_Msk

#define CAN_F1R2_FB30_Msk (0x1UL << CAN_F1R2_FB30_Pos)

0x40000000

◆ CAN_F1R2_FB30_Pos

#define CAN_F1R2_FB30_Pos (30U)

◆ CAN_F1R2_FB31

#define CAN_F1R2_FB31 CAN_F1R2_FB31_Msk

Filter bit 31

◆ CAN_F1R2_FB31_Msk

#define CAN_F1R2_FB31_Msk (0x1UL << CAN_F1R2_FB31_Pos)

0x80000000

◆ CAN_F1R2_FB31_Pos

#define CAN_F1R2_FB31_Pos (31U)

◆ CAN_F1R2_FB3_Msk

#define CAN_F1R2_FB3_Msk (0x1UL << CAN_F1R2_FB3_Pos)

0x00000008

◆ CAN_F1R2_FB3_Pos

#define CAN_F1R2_FB3_Pos (3U)

◆ CAN_F1R2_FB4

#define CAN_F1R2_FB4 CAN_F1R2_FB4_Msk

Filter bit 4

◆ CAN_F1R2_FB4_Msk

#define CAN_F1R2_FB4_Msk (0x1UL << CAN_F1R2_FB4_Pos)

0x00000010

◆ CAN_F1R2_FB4_Pos

#define CAN_F1R2_FB4_Pos (4U)

◆ CAN_F1R2_FB5

#define CAN_F1R2_FB5 CAN_F1R2_FB5_Msk

Filter bit 5

◆ CAN_F1R2_FB5_Msk

#define CAN_F1R2_FB5_Msk (0x1UL << CAN_F1R2_FB5_Pos)

0x00000020

◆ CAN_F1R2_FB5_Pos

#define CAN_F1R2_FB5_Pos (5U)

◆ CAN_F1R2_FB6

#define CAN_F1R2_FB6 CAN_F1R2_FB6_Msk

Filter bit 6

◆ CAN_F1R2_FB6_Msk

#define CAN_F1R2_FB6_Msk (0x1UL << CAN_F1R2_FB6_Pos)

0x00000040

◆ CAN_F1R2_FB6_Pos

#define CAN_F1R2_FB6_Pos (6U)

◆ CAN_F1R2_FB7

#define CAN_F1R2_FB7 CAN_F1R2_FB7_Msk

Filter bit 7

◆ CAN_F1R2_FB7_Msk

#define CAN_F1R2_FB7_Msk (0x1UL << CAN_F1R2_FB7_Pos)

0x00000080

◆ CAN_F1R2_FB7_Pos

#define CAN_F1R2_FB7_Pos (7U)

◆ CAN_F1R2_FB8

#define CAN_F1R2_FB8 CAN_F1R2_FB8_Msk

Filter bit 8

◆ CAN_F1R2_FB8_Msk

#define CAN_F1R2_FB8_Msk (0x1UL << CAN_F1R2_FB8_Pos)

0x00000100

◆ CAN_F1R2_FB8_Pos

#define CAN_F1R2_FB8_Pos (8U)

◆ CAN_F1R2_FB9

#define CAN_F1R2_FB9 CAN_F1R2_FB9_Msk

Filter bit 9

◆ CAN_F1R2_FB9_Msk

#define CAN_F1R2_FB9_Msk (0x1UL << CAN_F1R2_FB9_Pos)

0x00000200

◆ CAN_F1R2_FB9_Pos

#define CAN_F1R2_FB9_Pos (9U)

◆ CAN_F2R1_FB0

#define CAN_F2R1_FB0 CAN_F2R1_FB0_Msk

Filter bit 0

◆ CAN_F2R1_FB0_Msk

#define CAN_F2R1_FB0_Msk (0x1UL << CAN_F2R1_FB0_Pos)

0x00000001

◆ CAN_F2R1_FB0_Pos

#define CAN_F2R1_FB0_Pos (0U)

◆ CAN_F2R1_FB1

#define CAN_F2R1_FB1 CAN_F2R1_FB1_Msk

Filter bit 1

◆ CAN_F2R1_FB10

#define CAN_F2R1_FB10 CAN_F2R1_FB10_Msk

Filter bit 10

◆ CAN_F2R1_FB10_Msk

#define CAN_F2R1_FB10_Msk (0x1UL << CAN_F2R1_FB10_Pos)

0x00000400

◆ CAN_F2R1_FB10_Pos

#define CAN_F2R1_FB10_Pos (10U)

◆ CAN_F2R1_FB11

#define CAN_F2R1_FB11 CAN_F2R1_FB11_Msk

Filter bit 11

◆ CAN_F2R1_FB11_Msk

#define CAN_F2R1_FB11_Msk (0x1UL << CAN_F2R1_FB11_Pos)

0x00000800

◆ CAN_F2R1_FB11_Pos

#define CAN_F2R1_FB11_Pos (11U)

◆ CAN_F2R1_FB12

#define CAN_F2R1_FB12 CAN_F2R1_FB12_Msk

Filter bit 12

◆ CAN_F2R1_FB12_Msk

#define CAN_F2R1_FB12_Msk (0x1UL << CAN_F2R1_FB12_Pos)

0x00001000

◆ CAN_F2R1_FB12_Pos

#define CAN_F2R1_FB12_Pos (12U)

◆ CAN_F2R1_FB13

#define CAN_F2R1_FB13 CAN_F2R1_FB13_Msk

Filter bit 13

◆ CAN_F2R1_FB13_Msk

#define CAN_F2R1_FB13_Msk (0x1UL << CAN_F2R1_FB13_Pos)

0x00002000

◆ CAN_F2R1_FB13_Pos

#define CAN_F2R1_FB13_Pos (13U)

◆ CAN_F2R1_FB14

#define CAN_F2R1_FB14 CAN_F2R1_FB14_Msk

Filter bit 14

◆ CAN_F2R1_FB14_Msk

#define CAN_F2R1_FB14_Msk (0x1UL << CAN_F2R1_FB14_Pos)

0x00004000

◆ CAN_F2R1_FB14_Pos

#define CAN_F2R1_FB14_Pos (14U)

◆ CAN_F2R1_FB15

#define CAN_F2R1_FB15 CAN_F2R1_FB15_Msk

Filter bit 15

◆ CAN_F2R1_FB15_Msk

#define CAN_F2R1_FB15_Msk (0x1UL << CAN_F2R1_FB15_Pos)

0x00008000

◆ CAN_F2R1_FB15_Pos

#define CAN_F2R1_FB15_Pos (15U)

◆ CAN_F2R1_FB16

#define CAN_F2R1_FB16 CAN_F2R1_FB16_Msk

Filter bit 16

◆ CAN_F2R1_FB16_Msk

#define CAN_F2R1_FB16_Msk (0x1UL << CAN_F2R1_FB16_Pos)

0x00010000

◆ CAN_F2R1_FB16_Pos

#define CAN_F2R1_FB16_Pos (16U)

◆ CAN_F2R1_FB17

#define CAN_F2R1_FB17 CAN_F2R1_FB17_Msk

Filter bit 17

◆ CAN_F2R1_FB17_Msk

#define CAN_F2R1_FB17_Msk (0x1UL << CAN_F2R1_FB17_Pos)

0x00020000

◆ CAN_F2R1_FB17_Pos

#define CAN_F2R1_FB17_Pos (17U)

◆ CAN_F2R1_FB18

#define CAN_F2R1_FB18 CAN_F2R1_FB18_Msk

Filter bit 18

◆ CAN_F2R1_FB18_Msk

#define CAN_F2R1_FB18_Msk (0x1UL << CAN_F2R1_FB18_Pos)

0x00040000

◆ CAN_F2R1_FB18_Pos

#define CAN_F2R1_FB18_Pos (18U)

◆ CAN_F2R1_FB19

#define CAN_F2R1_FB19 CAN_F2R1_FB19_Msk

Filter bit 19

◆ CAN_F2R1_FB19_Msk

#define CAN_F2R1_FB19_Msk (0x1UL << CAN_F2R1_FB19_Pos)

0x00080000

◆ CAN_F2R1_FB19_Pos

#define CAN_F2R1_FB19_Pos (19U)

◆ CAN_F2R1_FB1_Msk

#define CAN_F2R1_FB1_Msk (0x1UL << CAN_F2R1_FB1_Pos)

0x00000002

◆ CAN_F2R1_FB1_Pos

#define CAN_F2R1_FB1_Pos (1U)

◆ CAN_F2R1_FB2

#define CAN_F2R1_FB2 CAN_F2R1_FB2_Msk

Filter bit 2

◆ CAN_F2R1_FB20

#define CAN_F2R1_FB20 CAN_F2R1_FB20_Msk

Filter bit 20

◆ CAN_F2R1_FB20_Msk

#define CAN_F2R1_FB20_Msk (0x1UL << CAN_F2R1_FB20_Pos)

0x00100000

◆ CAN_F2R1_FB20_Pos

#define CAN_F2R1_FB20_Pos (20U)

◆ CAN_F2R1_FB21

#define CAN_F2R1_FB21 CAN_F2R1_FB21_Msk

Filter bit 21

◆ CAN_F2R1_FB21_Msk

#define CAN_F2R1_FB21_Msk (0x1UL << CAN_F2R1_FB21_Pos)

0x00200000

◆ CAN_F2R1_FB21_Pos

#define CAN_F2R1_FB21_Pos (21U)

◆ CAN_F2R1_FB22

#define CAN_F2R1_FB22 CAN_F2R1_FB22_Msk

Filter bit 22

◆ CAN_F2R1_FB22_Msk

#define CAN_F2R1_FB22_Msk (0x1UL << CAN_F2R1_FB22_Pos)

0x00400000

◆ CAN_F2R1_FB22_Pos

#define CAN_F2R1_FB22_Pos (22U)

◆ CAN_F2R1_FB23

#define CAN_F2R1_FB23 CAN_F2R1_FB23_Msk

Filter bit 23

◆ CAN_F2R1_FB23_Msk

#define CAN_F2R1_FB23_Msk (0x1UL << CAN_F2R1_FB23_Pos)

0x00800000

◆ CAN_F2R1_FB23_Pos

#define CAN_F2R1_FB23_Pos (23U)

◆ CAN_F2R1_FB24

#define CAN_F2R1_FB24 CAN_F2R1_FB24_Msk

Filter bit 24

◆ CAN_F2R1_FB24_Msk

#define CAN_F2R1_FB24_Msk (0x1UL << CAN_F2R1_FB24_Pos)

0x01000000

◆ CAN_F2R1_FB24_Pos

#define CAN_F2R1_FB24_Pos (24U)

◆ CAN_F2R1_FB25

#define CAN_F2R1_FB25 CAN_F2R1_FB25_Msk

Filter bit 25

◆ CAN_F2R1_FB25_Msk

#define CAN_F2R1_FB25_Msk (0x1UL << CAN_F2R1_FB25_Pos)

0x02000000

◆ CAN_F2R1_FB25_Pos

#define CAN_F2R1_FB25_Pos (25U)

◆ CAN_F2R1_FB26

#define CAN_F2R1_FB26 CAN_F2R1_FB26_Msk

Filter bit 26

◆ CAN_F2R1_FB26_Msk

#define CAN_F2R1_FB26_Msk (0x1UL << CAN_F2R1_FB26_Pos)

0x04000000

◆ CAN_F2R1_FB26_Pos

#define CAN_F2R1_FB26_Pos (26U)

◆ CAN_F2R1_FB27

#define CAN_F2R1_FB27 CAN_F2R1_FB27_Msk

Filter bit 27

◆ CAN_F2R1_FB27_Msk

#define CAN_F2R1_FB27_Msk (0x1UL << CAN_F2R1_FB27_Pos)

0x08000000

◆ CAN_F2R1_FB27_Pos

#define CAN_F2R1_FB27_Pos (27U)

◆ CAN_F2R1_FB28

#define CAN_F2R1_FB28 CAN_F2R1_FB28_Msk

Filter bit 28

◆ CAN_F2R1_FB28_Msk

#define CAN_F2R1_FB28_Msk (0x1UL << CAN_F2R1_FB28_Pos)

0x10000000

◆ CAN_F2R1_FB28_Pos

#define CAN_F2R1_FB28_Pos (28U)

◆ CAN_F2R1_FB29

#define CAN_F2R1_FB29 CAN_F2R1_FB29_Msk

Filter bit 29

◆ CAN_F2R1_FB29_Msk

#define CAN_F2R1_FB29_Msk (0x1UL << CAN_F2R1_FB29_Pos)

0x20000000

◆ CAN_F2R1_FB29_Pos

#define CAN_F2R1_FB29_Pos (29U)

◆ CAN_F2R1_FB2_Msk

#define CAN_F2R1_FB2_Msk (0x1UL << CAN_F2R1_FB2_Pos)

0x00000004

◆ CAN_F2R1_FB2_Pos

#define CAN_F2R1_FB2_Pos (2U)

◆ CAN_F2R1_FB3

#define CAN_F2R1_FB3 CAN_F2R1_FB3_Msk

Filter bit 3

◆ CAN_F2R1_FB30

#define CAN_F2R1_FB30 CAN_F2R1_FB30_Msk

Filter bit 30

◆ CAN_F2R1_FB30_Msk

#define CAN_F2R1_FB30_Msk (0x1UL << CAN_F2R1_FB30_Pos)

0x40000000

◆ CAN_F2R1_FB30_Pos

#define CAN_F2R1_FB30_Pos (30U)

◆ CAN_F2R1_FB31

#define CAN_F2R1_FB31 CAN_F2R1_FB31_Msk

Filter bit 31

◆ CAN_F2R1_FB31_Msk

#define CAN_F2R1_FB31_Msk (0x1UL << CAN_F2R1_FB31_Pos)

0x80000000

◆ CAN_F2R1_FB31_Pos

#define CAN_F2R1_FB31_Pos (31U)

◆ CAN_F2R1_FB3_Msk

#define CAN_F2R1_FB3_Msk (0x1UL << CAN_F2R1_FB3_Pos)

0x00000008

◆ CAN_F2R1_FB3_Pos

#define CAN_F2R1_FB3_Pos (3U)

◆ CAN_F2R1_FB4

#define CAN_F2R1_FB4 CAN_F2R1_FB4_Msk

Filter bit 4

◆ CAN_F2R1_FB4_Msk

#define CAN_F2R1_FB4_Msk (0x1UL << CAN_F2R1_FB4_Pos)

0x00000010

◆ CAN_F2R1_FB4_Pos

#define CAN_F2R1_FB4_Pos (4U)

◆ CAN_F2R1_FB5

#define CAN_F2R1_FB5 CAN_F2R1_FB5_Msk

Filter bit 5

◆ CAN_F2R1_FB5_Msk

#define CAN_F2R1_FB5_Msk (0x1UL << CAN_F2R1_FB5_Pos)

0x00000020

◆ CAN_F2R1_FB5_Pos

#define CAN_F2R1_FB5_Pos (5U)

◆ CAN_F2R1_FB6

#define CAN_F2R1_FB6 CAN_F2R1_FB6_Msk

Filter bit 6

◆ CAN_F2R1_FB6_Msk

#define CAN_F2R1_FB6_Msk (0x1UL << CAN_F2R1_FB6_Pos)

0x00000040

◆ CAN_F2R1_FB6_Pos

#define CAN_F2R1_FB6_Pos (6U)

◆ CAN_F2R1_FB7

#define CAN_F2R1_FB7 CAN_F2R1_FB7_Msk

Filter bit 7

◆ CAN_F2R1_FB7_Msk

#define CAN_F2R1_FB7_Msk (0x1UL << CAN_F2R1_FB7_Pos)

0x00000080

◆ CAN_F2R1_FB7_Pos

#define CAN_F2R1_FB7_Pos (7U)

◆ CAN_F2R1_FB8

#define CAN_F2R1_FB8 CAN_F2R1_FB8_Msk

Filter bit 8

◆ CAN_F2R1_FB8_Msk

#define CAN_F2R1_FB8_Msk (0x1UL << CAN_F2R1_FB8_Pos)

0x00000100

◆ CAN_F2R1_FB8_Pos

#define CAN_F2R1_FB8_Pos (8U)

◆ CAN_F2R1_FB9

#define CAN_F2R1_FB9 CAN_F2R1_FB9_Msk

Filter bit 9

◆ CAN_F2R1_FB9_Msk

#define CAN_F2R1_FB9_Msk (0x1UL << CAN_F2R1_FB9_Pos)

0x00000200

◆ CAN_F2R1_FB9_Pos

#define CAN_F2R1_FB9_Pos (9U)

◆ CAN_F2R2_FB0

#define CAN_F2R2_FB0 CAN_F2R2_FB0_Msk

Filter bit 0

◆ CAN_F2R2_FB0_Msk

#define CAN_F2R2_FB0_Msk (0x1UL << CAN_F2R2_FB0_Pos)

0x00000001

◆ CAN_F2R2_FB0_Pos

#define CAN_F2R2_FB0_Pos (0U)

◆ CAN_F2R2_FB1

#define CAN_F2R2_FB1 CAN_F2R2_FB1_Msk

Filter bit 1

◆ CAN_F2R2_FB10

#define CAN_F2R2_FB10 CAN_F2R2_FB10_Msk

Filter bit 10

◆ CAN_F2R2_FB10_Msk

#define CAN_F2R2_FB10_Msk (0x1UL << CAN_F2R2_FB10_Pos)

0x00000400

◆ CAN_F2R2_FB10_Pos

#define CAN_F2R2_FB10_Pos (10U)

◆ CAN_F2R2_FB11

#define CAN_F2R2_FB11 CAN_F2R2_FB11_Msk

Filter bit 11

◆ CAN_F2R2_FB11_Msk

#define CAN_F2R2_FB11_Msk (0x1UL << CAN_F2R2_FB11_Pos)

0x00000800

◆ CAN_F2R2_FB11_Pos

#define CAN_F2R2_FB11_Pos (11U)

◆ CAN_F2R2_FB12

#define CAN_F2R2_FB12 CAN_F2R2_FB12_Msk

Filter bit 12

◆ CAN_F2R2_FB12_Msk

#define CAN_F2R2_FB12_Msk (0x1UL << CAN_F2R2_FB12_Pos)

0x00001000

◆ CAN_F2R2_FB12_Pos

#define CAN_F2R2_FB12_Pos (12U)

◆ CAN_F2R2_FB13

#define CAN_F2R2_FB13 CAN_F2R2_FB13_Msk

Filter bit 13

◆ CAN_F2R2_FB13_Msk

#define CAN_F2R2_FB13_Msk (0x1UL << CAN_F2R2_FB13_Pos)

0x00002000

◆ CAN_F2R2_FB13_Pos

#define CAN_F2R2_FB13_Pos (13U)

◆ CAN_F2R2_FB14

#define CAN_F2R2_FB14 CAN_F2R2_FB14_Msk

Filter bit 14

◆ CAN_F2R2_FB14_Msk

#define CAN_F2R2_FB14_Msk (0x1UL << CAN_F2R2_FB14_Pos)

0x00004000

◆ CAN_F2R2_FB14_Pos

#define CAN_F2R2_FB14_Pos (14U)

◆ CAN_F2R2_FB15

#define CAN_F2R2_FB15 CAN_F2R2_FB15_Msk

Filter bit 15

◆ CAN_F2R2_FB15_Msk

#define CAN_F2R2_FB15_Msk (0x1UL << CAN_F2R2_FB15_Pos)

0x00008000

◆ CAN_F2R2_FB15_Pos

#define CAN_F2R2_FB15_Pos (15U)

◆ CAN_F2R2_FB16

#define CAN_F2R2_FB16 CAN_F2R2_FB16_Msk

Filter bit 16

◆ CAN_F2R2_FB16_Msk

#define CAN_F2R2_FB16_Msk (0x1UL << CAN_F2R2_FB16_Pos)

0x00010000

◆ CAN_F2R2_FB16_Pos

#define CAN_F2R2_FB16_Pos (16U)

◆ CAN_F2R2_FB17

#define CAN_F2R2_FB17 CAN_F2R2_FB17_Msk

Filter bit 17

◆ CAN_F2R2_FB17_Msk

#define CAN_F2R2_FB17_Msk (0x1UL << CAN_F2R2_FB17_Pos)

0x00020000

◆ CAN_F2R2_FB17_Pos

#define CAN_F2R2_FB17_Pos (17U)

◆ CAN_F2R2_FB18

#define CAN_F2R2_FB18 CAN_F2R2_FB18_Msk

Filter bit 18

◆ CAN_F2R2_FB18_Msk

#define CAN_F2R2_FB18_Msk (0x1UL << CAN_F2R2_FB18_Pos)

0x00040000

◆ CAN_F2R2_FB18_Pos

#define CAN_F2R2_FB18_Pos (18U)

◆ CAN_F2R2_FB19

#define CAN_F2R2_FB19 CAN_F2R2_FB19_Msk

Filter bit 19

◆ CAN_F2R2_FB19_Msk

#define CAN_F2R2_FB19_Msk (0x1UL << CAN_F2R2_FB19_Pos)

0x00080000

◆ CAN_F2R2_FB19_Pos

#define CAN_F2R2_FB19_Pos (19U)

◆ CAN_F2R2_FB1_Msk

#define CAN_F2R2_FB1_Msk (0x1UL << CAN_F2R2_FB1_Pos)

0x00000002

◆ CAN_F2R2_FB1_Pos

#define CAN_F2R2_FB1_Pos (1U)

◆ CAN_F2R2_FB2

#define CAN_F2R2_FB2 CAN_F2R2_FB2_Msk

Filter bit 2

◆ CAN_F2R2_FB20

#define CAN_F2R2_FB20 CAN_F2R2_FB20_Msk

Filter bit 20

◆ CAN_F2R2_FB20_Msk

#define CAN_F2R2_FB20_Msk (0x1UL << CAN_F2R2_FB20_Pos)

0x00100000

◆ CAN_F2R2_FB20_Pos

#define CAN_F2R2_FB20_Pos (20U)

◆ CAN_F2R2_FB21

#define CAN_F2R2_FB21 CAN_F2R2_FB21_Msk

Filter bit 21

◆ CAN_F2R2_FB21_Msk

#define CAN_F2R2_FB21_Msk (0x1UL << CAN_F2R2_FB21_Pos)

0x00200000

◆ CAN_F2R2_FB21_Pos

#define CAN_F2R2_FB21_Pos (21U)

◆ CAN_F2R2_FB22

#define CAN_F2R2_FB22 CAN_F2R2_FB22_Msk

Filter bit 22

◆ CAN_F2R2_FB22_Msk

#define CAN_F2R2_FB22_Msk (0x1UL << CAN_F2R2_FB22_Pos)

0x00400000

◆ CAN_F2R2_FB22_Pos

#define CAN_F2R2_FB22_Pos (22U)

◆ CAN_F2R2_FB23

#define CAN_F2R2_FB23 CAN_F2R2_FB23_Msk

Filter bit 23

◆ CAN_F2R2_FB23_Msk

#define CAN_F2R2_FB23_Msk (0x1UL << CAN_F2R2_FB23_Pos)

0x00800000

◆ CAN_F2R2_FB23_Pos

#define CAN_F2R2_FB23_Pos (23U)

◆ CAN_F2R2_FB24

#define CAN_F2R2_FB24 CAN_F2R2_FB24_Msk

Filter bit 24

◆ CAN_F2R2_FB24_Msk

#define CAN_F2R2_FB24_Msk (0x1UL << CAN_F2R2_FB24_Pos)

0x01000000

◆ CAN_F2R2_FB24_Pos

#define CAN_F2R2_FB24_Pos (24U)

◆ CAN_F2R2_FB25

#define CAN_F2R2_FB25 CAN_F2R2_FB25_Msk

Filter bit 25

◆ CAN_F2R2_FB25_Msk

#define CAN_F2R2_FB25_Msk (0x1UL << CAN_F2R2_FB25_Pos)

0x02000000

◆ CAN_F2R2_FB25_Pos

#define CAN_F2R2_FB25_Pos (25U)

◆ CAN_F2R2_FB26

#define CAN_F2R2_FB26 CAN_F2R2_FB26_Msk

Filter bit 26

◆ CAN_F2R2_FB26_Msk

#define CAN_F2R2_FB26_Msk (0x1UL << CAN_F2R2_FB26_Pos)

0x04000000

◆ CAN_F2R2_FB26_Pos

#define CAN_F2R2_FB26_Pos (26U)

◆ CAN_F2R2_FB27

#define CAN_F2R2_FB27 CAN_F2R2_FB27_Msk

Filter bit 27

◆ CAN_F2R2_FB27_Msk

#define CAN_F2R2_FB27_Msk (0x1UL << CAN_F2R2_FB27_Pos)

0x08000000

◆ CAN_F2R2_FB27_Pos

#define CAN_F2R2_FB27_Pos (27U)

◆ CAN_F2R2_FB28

#define CAN_F2R2_FB28 CAN_F2R2_FB28_Msk

Filter bit 28

◆ CAN_F2R2_FB28_Msk

#define CAN_F2R2_FB28_Msk (0x1UL << CAN_F2R2_FB28_Pos)

0x10000000

◆ CAN_F2R2_FB28_Pos

#define CAN_F2R2_FB28_Pos (28U)

◆ CAN_F2R2_FB29

#define CAN_F2R2_FB29 CAN_F2R2_FB29_Msk

Filter bit 29

◆ CAN_F2R2_FB29_Msk

#define CAN_F2R2_FB29_Msk (0x1UL << CAN_F2R2_FB29_Pos)

0x20000000

◆ CAN_F2R2_FB29_Pos

#define CAN_F2R2_FB29_Pos (29U)

◆ CAN_F2R2_FB2_Msk

#define CAN_F2R2_FB2_Msk (0x1UL << CAN_F2R2_FB2_Pos)

0x00000004

◆ CAN_F2R2_FB2_Pos

#define CAN_F2R2_FB2_Pos (2U)

◆ CAN_F2R2_FB3

#define CAN_F2R2_FB3 CAN_F2R2_FB3_Msk

Filter bit 3

◆ CAN_F2R2_FB30

#define CAN_F2R2_FB30 CAN_F2R2_FB30_Msk

Filter bit 30

◆ CAN_F2R2_FB30_Msk

#define CAN_F2R2_FB30_Msk (0x1UL << CAN_F2R2_FB30_Pos)

0x40000000

◆ CAN_F2R2_FB30_Pos

#define CAN_F2R2_FB30_Pos (30U)

◆ CAN_F2R2_FB31

#define CAN_F2R2_FB31 CAN_F2R2_FB31_Msk

Filter bit 31

◆ CAN_F2R2_FB31_Msk

#define CAN_F2R2_FB31_Msk (0x1UL << CAN_F2R2_FB31_Pos)

0x80000000

◆ CAN_F2R2_FB31_Pos

#define CAN_F2R2_FB31_Pos (31U)

◆ CAN_F2R2_FB3_Msk

#define CAN_F2R2_FB3_Msk (0x1UL << CAN_F2R2_FB3_Pos)

0x00000008

◆ CAN_F2R2_FB3_Pos

#define CAN_F2R2_FB3_Pos (3U)

◆ CAN_F2R2_FB4

#define CAN_F2R2_FB4 CAN_F2R2_FB4_Msk

Filter bit 4

◆ CAN_F2R2_FB4_Msk

#define CAN_F2R2_FB4_Msk (0x1UL << CAN_F2R2_FB4_Pos)

0x00000010

◆ CAN_F2R2_FB4_Pos

#define CAN_F2R2_FB4_Pos (4U)

◆ CAN_F2R2_FB5

#define CAN_F2R2_FB5 CAN_F2R2_FB5_Msk

Filter bit 5

◆ CAN_F2R2_FB5_Msk

#define CAN_F2R2_FB5_Msk (0x1UL << CAN_F2R2_FB5_Pos)

0x00000020

◆ CAN_F2R2_FB5_Pos

#define CAN_F2R2_FB5_Pos (5U)

◆ CAN_F2R2_FB6

#define CAN_F2R2_FB6 CAN_F2R2_FB6_Msk

Filter bit 6

◆ CAN_F2R2_FB6_Msk

#define CAN_F2R2_FB6_Msk (0x1UL << CAN_F2R2_FB6_Pos)

0x00000040

◆ CAN_F2R2_FB6_Pos

#define CAN_F2R2_FB6_Pos (6U)

◆ CAN_F2R2_FB7

#define CAN_F2R2_FB7 CAN_F2R2_FB7_Msk

Filter bit 7

◆ CAN_F2R2_FB7_Msk

#define CAN_F2R2_FB7_Msk (0x1UL << CAN_F2R2_FB7_Pos)

0x00000080

◆ CAN_F2R2_FB7_Pos

#define CAN_F2R2_FB7_Pos (7U)

◆ CAN_F2R2_FB8

#define CAN_F2R2_FB8 CAN_F2R2_FB8_Msk

Filter bit 8

◆ CAN_F2R2_FB8_Msk

#define CAN_F2R2_FB8_Msk (0x1UL << CAN_F2R2_FB8_Pos)

0x00000100

◆ CAN_F2R2_FB8_Pos

#define CAN_F2R2_FB8_Pos (8U)

◆ CAN_F2R2_FB9

#define CAN_F2R2_FB9 CAN_F2R2_FB9_Msk

Filter bit 9

◆ CAN_F2R2_FB9_Msk

#define CAN_F2R2_FB9_Msk (0x1UL << CAN_F2R2_FB9_Pos)

0x00000200

◆ CAN_F2R2_FB9_Pos

#define CAN_F2R2_FB9_Pos (9U)

◆ CAN_F3R1_FB0

#define CAN_F3R1_FB0 CAN_F3R1_FB0_Msk

Filter bit 0

◆ CAN_F3R1_FB0_Msk

#define CAN_F3R1_FB0_Msk (0x1UL << CAN_F3R1_FB0_Pos)

0x00000001

◆ CAN_F3R1_FB0_Pos

#define CAN_F3R1_FB0_Pos (0U)

◆ CAN_F3R1_FB1

#define CAN_F3R1_FB1 CAN_F3R1_FB1_Msk

Filter bit 1

◆ CAN_F3R1_FB10

#define CAN_F3R1_FB10 CAN_F3R1_FB10_Msk

Filter bit 10

◆ CAN_F3R1_FB10_Msk

#define CAN_F3R1_FB10_Msk (0x1UL << CAN_F3R1_FB10_Pos)

0x00000400

◆ CAN_F3R1_FB10_Pos

#define CAN_F3R1_FB10_Pos (10U)

◆ CAN_F3R1_FB11

#define CAN_F3R1_FB11 CAN_F3R1_FB11_Msk

Filter bit 11

◆ CAN_F3R1_FB11_Msk

#define CAN_F3R1_FB11_Msk (0x1UL << CAN_F3R1_FB11_Pos)

0x00000800

◆ CAN_F3R1_FB11_Pos

#define CAN_F3R1_FB11_Pos (11U)

◆ CAN_F3R1_FB12

#define CAN_F3R1_FB12 CAN_F3R1_FB12_Msk

Filter bit 12

◆ CAN_F3R1_FB12_Msk

#define CAN_F3R1_FB12_Msk (0x1UL << CAN_F3R1_FB12_Pos)

0x00001000

◆ CAN_F3R1_FB12_Pos

#define CAN_F3R1_FB12_Pos (12U)

◆ CAN_F3R1_FB13

#define CAN_F3R1_FB13 CAN_F3R1_FB13_Msk

Filter bit 13

◆ CAN_F3R1_FB13_Msk

#define CAN_F3R1_FB13_Msk (0x1UL << CAN_F3R1_FB13_Pos)

0x00002000

◆ CAN_F3R1_FB13_Pos

#define CAN_F3R1_FB13_Pos (13U)

◆ CAN_F3R1_FB14

#define CAN_F3R1_FB14 CAN_F3R1_FB14_Msk

Filter bit 14

◆ CAN_F3R1_FB14_Msk

#define CAN_F3R1_FB14_Msk (0x1UL << CAN_F3R1_FB14_Pos)

0x00004000

◆ CAN_F3R1_FB14_Pos

#define CAN_F3R1_FB14_Pos (14U)

◆ CAN_F3R1_FB15

#define CAN_F3R1_FB15 CAN_F3R1_FB15_Msk

Filter bit 15

◆ CAN_F3R1_FB15_Msk

#define CAN_F3R1_FB15_Msk (0x1UL << CAN_F3R1_FB15_Pos)

0x00008000

◆ CAN_F3R1_FB15_Pos

#define CAN_F3R1_FB15_Pos (15U)

◆ CAN_F3R1_FB16

#define CAN_F3R1_FB16 CAN_F3R1_FB16_Msk

Filter bit 16

◆ CAN_F3R1_FB16_Msk

#define CAN_F3R1_FB16_Msk (0x1UL << CAN_F3R1_FB16_Pos)

0x00010000

◆ CAN_F3R1_FB16_Pos

#define CAN_F3R1_FB16_Pos (16U)

◆ CAN_F3R1_FB17

#define CAN_F3R1_FB17 CAN_F3R1_FB17_Msk

Filter bit 17

◆ CAN_F3R1_FB17_Msk

#define CAN_F3R1_FB17_Msk (0x1UL << CAN_F3R1_FB17_Pos)

0x00020000

◆ CAN_F3R1_FB17_Pos

#define CAN_F3R1_FB17_Pos (17U)

◆ CAN_F3R1_FB18

#define CAN_F3R1_FB18 CAN_F3R1_FB18_Msk

Filter bit 18

◆ CAN_F3R1_FB18_Msk

#define CAN_F3R1_FB18_Msk (0x1UL << CAN_F3R1_FB18_Pos)

0x00040000

◆ CAN_F3R1_FB18_Pos

#define CAN_F3R1_FB18_Pos (18U)

◆ CAN_F3R1_FB19

#define CAN_F3R1_FB19 CAN_F3R1_FB19_Msk

Filter bit 19

◆ CAN_F3R1_FB19_Msk

#define CAN_F3R1_FB19_Msk (0x1UL << CAN_F3R1_FB19_Pos)

0x00080000

◆ CAN_F3R1_FB19_Pos

#define CAN_F3R1_FB19_Pos (19U)

◆ CAN_F3R1_FB1_Msk

#define CAN_F3R1_FB1_Msk (0x1UL << CAN_F3R1_FB1_Pos)

0x00000002

◆ CAN_F3R1_FB1_Pos

#define CAN_F3R1_FB1_Pos (1U)

◆ CAN_F3R1_FB2

#define CAN_F3R1_FB2 CAN_F3R1_FB2_Msk

Filter bit 2

◆ CAN_F3R1_FB20

#define CAN_F3R1_FB20 CAN_F3R1_FB20_Msk

Filter bit 20

◆ CAN_F3R1_FB20_Msk

#define CAN_F3R1_FB20_Msk (0x1UL << CAN_F3R1_FB20_Pos)

0x00100000

◆ CAN_F3R1_FB20_Pos

#define CAN_F3R1_FB20_Pos (20U)

◆ CAN_F3R1_FB21

#define CAN_F3R1_FB21 CAN_F3R1_FB21_Msk

Filter bit 21

◆ CAN_F3R1_FB21_Msk

#define CAN_F3R1_FB21_Msk (0x1UL << CAN_F3R1_FB21_Pos)

0x00200000

◆ CAN_F3R1_FB21_Pos

#define CAN_F3R1_FB21_Pos (21U)

◆ CAN_F3R1_FB22

#define CAN_F3R1_FB22 CAN_F3R1_FB22_Msk

Filter bit 22

◆ CAN_F3R1_FB22_Msk

#define CAN_F3R1_FB22_Msk (0x1UL << CAN_F3R1_FB22_Pos)

0x00400000

◆ CAN_F3R1_FB22_Pos

#define CAN_F3R1_FB22_Pos (22U)

◆ CAN_F3R1_FB23

#define CAN_F3R1_FB23 CAN_F3R1_FB23_Msk

Filter bit 23

◆ CAN_F3R1_FB23_Msk

#define CAN_F3R1_FB23_Msk (0x1UL << CAN_F3R1_FB23_Pos)

0x00800000

◆ CAN_F3R1_FB23_Pos

#define CAN_F3R1_FB23_Pos (23U)

◆ CAN_F3R1_FB24

#define CAN_F3R1_FB24 CAN_F3R1_FB24_Msk

Filter bit 24

◆ CAN_F3R1_FB24_Msk

#define CAN_F3R1_FB24_Msk (0x1UL << CAN_F3R1_FB24_Pos)

0x01000000

◆ CAN_F3R1_FB24_Pos

#define CAN_F3R1_FB24_Pos (24U)

◆ CAN_F3R1_FB25

#define CAN_F3R1_FB25 CAN_F3R1_FB25_Msk

Filter bit 25

◆ CAN_F3R1_FB25_Msk

#define CAN_F3R1_FB25_Msk (0x1UL << CAN_F3R1_FB25_Pos)

0x02000000

◆ CAN_F3R1_FB25_Pos

#define CAN_F3R1_FB25_Pos (25U)

◆ CAN_F3R1_FB26

#define CAN_F3R1_FB26 CAN_F3R1_FB26_Msk

Filter bit 26

◆ CAN_F3R1_FB26_Msk

#define CAN_F3R1_FB26_Msk (0x1UL << CAN_F3R1_FB26_Pos)

0x04000000

◆ CAN_F3R1_FB26_Pos

#define CAN_F3R1_FB26_Pos (26U)

◆ CAN_F3R1_FB27

#define CAN_F3R1_FB27 CAN_F3R1_FB27_Msk

Filter bit 27

◆ CAN_F3R1_FB27_Msk

#define CAN_F3R1_FB27_Msk (0x1UL << CAN_F3R1_FB27_Pos)

0x08000000

◆ CAN_F3R1_FB27_Pos

#define CAN_F3R1_FB27_Pos (27U)

◆ CAN_F3R1_FB28

#define CAN_F3R1_FB28 CAN_F3R1_FB28_Msk

Filter bit 28

◆ CAN_F3R1_FB28_Msk

#define CAN_F3R1_FB28_Msk (0x1UL << CAN_F3R1_FB28_Pos)

0x10000000

◆ CAN_F3R1_FB28_Pos

#define CAN_F3R1_FB28_Pos (28U)

◆ CAN_F3R1_FB29

#define CAN_F3R1_FB29 CAN_F3R1_FB29_Msk

Filter bit 29

◆ CAN_F3R1_FB29_Msk

#define CAN_F3R1_FB29_Msk (0x1UL << CAN_F3R1_FB29_Pos)

0x20000000

◆ CAN_F3R1_FB29_Pos

#define CAN_F3R1_FB29_Pos (29U)

◆ CAN_F3R1_FB2_Msk

#define CAN_F3R1_FB2_Msk (0x1UL << CAN_F3R1_FB2_Pos)

0x00000004

◆ CAN_F3R1_FB2_Pos

#define CAN_F3R1_FB2_Pos (2U)

◆ CAN_F3R1_FB3

#define CAN_F3R1_FB3 CAN_F3R1_FB3_Msk

Filter bit 3

◆ CAN_F3R1_FB30

#define CAN_F3R1_FB30 CAN_F3R1_FB30_Msk

Filter bit 30

◆ CAN_F3R1_FB30_Msk

#define CAN_F3R1_FB30_Msk (0x1UL << CAN_F3R1_FB30_Pos)

0x40000000

◆ CAN_F3R1_FB30_Pos

#define CAN_F3R1_FB30_Pos (30U)

◆ CAN_F3R1_FB31

#define CAN_F3R1_FB31 CAN_F3R1_FB31_Msk

Filter bit 31

◆ CAN_F3R1_FB31_Msk

#define CAN_F3R1_FB31_Msk (0x1UL << CAN_F3R1_FB31_Pos)

0x80000000

◆ CAN_F3R1_FB31_Pos

#define CAN_F3R1_FB31_Pos (31U)

◆ CAN_F3R1_FB3_Msk

#define CAN_F3R1_FB3_Msk (0x1UL << CAN_F3R1_FB3_Pos)

0x00000008

◆ CAN_F3R1_FB3_Pos

#define CAN_F3R1_FB3_Pos (3U)

◆ CAN_F3R1_FB4

#define CAN_F3R1_FB4 CAN_F3R1_FB4_Msk

Filter bit 4

◆ CAN_F3R1_FB4_Msk

#define CAN_F3R1_FB4_Msk (0x1UL << CAN_F3R1_FB4_Pos)

0x00000010

◆ CAN_F3R1_FB4_Pos

#define CAN_F3R1_FB4_Pos (4U)

◆ CAN_F3R1_FB5

#define CAN_F3R1_FB5 CAN_F3R1_FB5_Msk

Filter bit 5

◆ CAN_F3R1_FB5_Msk

#define CAN_F3R1_FB5_Msk (0x1UL << CAN_F3R1_FB5_Pos)

0x00000020

◆ CAN_F3R1_FB5_Pos

#define CAN_F3R1_FB5_Pos (5U)

◆ CAN_F3R1_FB6

#define CAN_F3R1_FB6 CAN_F3R1_FB6_Msk

Filter bit 6

◆ CAN_F3R1_FB6_Msk

#define CAN_F3R1_FB6_Msk (0x1UL << CAN_F3R1_FB6_Pos)

0x00000040

◆ CAN_F3R1_FB6_Pos

#define CAN_F3R1_FB6_Pos (6U)

◆ CAN_F3R1_FB7

#define CAN_F3R1_FB7 CAN_F3R1_FB7_Msk

Filter bit 7

◆ CAN_F3R1_FB7_Msk

#define CAN_F3R1_FB7_Msk (0x1UL << CAN_F3R1_FB7_Pos)

0x00000080

◆ CAN_F3R1_FB7_Pos

#define CAN_F3R1_FB7_Pos (7U)

◆ CAN_F3R1_FB8

#define CAN_F3R1_FB8 CAN_F3R1_FB8_Msk

Filter bit 8

◆ CAN_F3R1_FB8_Msk

#define CAN_F3R1_FB8_Msk (0x1UL << CAN_F3R1_FB8_Pos)

0x00000100

◆ CAN_F3R1_FB8_Pos

#define CAN_F3R1_FB8_Pos (8U)

◆ CAN_F3R1_FB9

#define CAN_F3R1_FB9 CAN_F3R1_FB9_Msk

Filter bit 9

◆ CAN_F3R1_FB9_Msk

#define CAN_F3R1_FB9_Msk (0x1UL << CAN_F3R1_FB9_Pos)

0x00000200

◆ CAN_F3R1_FB9_Pos

#define CAN_F3R1_FB9_Pos (9U)

◆ CAN_F3R2_FB0

#define CAN_F3R2_FB0 CAN_F3R2_FB0_Msk

Filter bit 0

◆ CAN_F3R2_FB0_Msk

#define CAN_F3R2_FB0_Msk (0x1UL << CAN_F3R2_FB0_Pos)

0x00000001

◆ CAN_F3R2_FB0_Pos

#define CAN_F3R2_FB0_Pos (0U)

◆ CAN_F3R2_FB1

#define CAN_F3R2_FB1 CAN_F3R2_FB1_Msk

Filter bit 1

◆ CAN_F3R2_FB10

#define CAN_F3R2_FB10 CAN_F3R2_FB10_Msk

Filter bit 10

◆ CAN_F3R2_FB10_Msk

#define CAN_F3R2_FB10_Msk (0x1UL << CAN_F3R2_FB10_Pos)

0x00000400

◆ CAN_F3R2_FB10_Pos

#define CAN_F3R2_FB10_Pos (10U)

◆ CAN_F3R2_FB11

#define CAN_F3R2_FB11 CAN_F3R2_FB11_Msk

Filter bit 11

◆ CAN_F3R2_FB11_Msk

#define CAN_F3R2_FB11_Msk (0x1UL << CAN_F3R2_FB11_Pos)

0x00000800

◆ CAN_F3R2_FB11_Pos

#define CAN_F3R2_FB11_Pos (11U)

◆ CAN_F3R2_FB12

#define CAN_F3R2_FB12 CAN_F3R2_FB12_Msk

Filter bit 12

◆ CAN_F3R2_FB12_Msk

#define CAN_F3R2_FB12_Msk (0x1UL << CAN_F3R2_FB12_Pos)

0x00001000

◆ CAN_F3R2_FB12_Pos

#define CAN_F3R2_FB12_Pos (12U)

◆ CAN_F3R2_FB13

#define CAN_F3R2_FB13 CAN_F3R2_FB13_Msk

Filter bit 13

◆ CAN_F3R2_FB13_Msk

#define CAN_F3R2_FB13_Msk (0x1UL << CAN_F3R2_FB13_Pos)

0x00002000

◆ CAN_F3R2_FB13_Pos

#define CAN_F3R2_FB13_Pos (13U)

◆ CAN_F3R2_FB14

#define CAN_F3R2_FB14 CAN_F3R2_FB14_Msk

Filter bit 14

◆ CAN_F3R2_FB14_Msk

#define CAN_F3R2_FB14_Msk (0x1UL << CAN_F3R2_FB14_Pos)

0x00004000

◆ CAN_F3R2_FB14_Pos

#define CAN_F3R2_FB14_Pos (14U)

◆ CAN_F3R2_FB15

#define CAN_F3R2_FB15 CAN_F3R2_FB15_Msk

Filter bit 15

◆ CAN_F3R2_FB15_Msk

#define CAN_F3R2_FB15_Msk (0x1UL << CAN_F3R2_FB15_Pos)

0x00008000

◆ CAN_F3R2_FB15_Pos

#define CAN_F3R2_FB15_Pos (15U)

◆ CAN_F3R2_FB16

#define CAN_F3R2_FB16 CAN_F3R2_FB16_Msk

Filter bit 16

◆ CAN_F3R2_FB16_Msk

#define CAN_F3R2_FB16_Msk (0x1UL << CAN_F3R2_FB16_Pos)

0x00010000

◆ CAN_F3R2_FB16_Pos

#define CAN_F3R2_FB16_Pos (16U)

◆ CAN_F3R2_FB17

#define CAN_F3R2_FB17 CAN_F3R2_FB17_Msk

Filter bit 17

◆ CAN_F3R2_FB17_Msk

#define CAN_F3R2_FB17_Msk (0x1UL << CAN_F3R2_FB17_Pos)

0x00020000

◆ CAN_F3R2_FB17_Pos

#define CAN_F3R2_FB17_Pos (17U)

◆ CAN_F3R2_FB18

#define CAN_F3R2_FB18 CAN_F3R2_FB18_Msk

Filter bit 18

◆ CAN_F3R2_FB18_Msk

#define CAN_F3R2_FB18_Msk (0x1UL << CAN_F3R2_FB18_Pos)

0x00040000

◆ CAN_F3R2_FB18_Pos

#define CAN_F3R2_FB18_Pos (18U)

◆ CAN_F3R2_FB19

#define CAN_F3R2_FB19 CAN_F3R2_FB19_Msk

Filter bit 19

◆ CAN_F3R2_FB19_Msk

#define CAN_F3R2_FB19_Msk (0x1UL << CAN_F3R2_FB19_Pos)

0x00080000

◆ CAN_F3R2_FB19_Pos

#define CAN_F3R2_FB19_Pos (19U)

◆ CAN_F3R2_FB1_Msk

#define CAN_F3R2_FB1_Msk (0x1UL << CAN_F3R2_FB1_Pos)

0x00000002

◆ CAN_F3R2_FB1_Pos

#define CAN_F3R2_FB1_Pos (1U)

◆ CAN_F3R2_FB2

#define CAN_F3R2_FB2 CAN_F3R2_FB2_Msk

Filter bit 2

◆ CAN_F3R2_FB20

#define CAN_F3R2_FB20 CAN_F3R2_FB20_Msk

Filter bit 20

◆ CAN_F3R2_FB20_Msk

#define CAN_F3R2_FB20_Msk (0x1UL << CAN_F3R2_FB20_Pos)

0x00100000

◆ CAN_F3R2_FB20_Pos

#define CAN_F3R2_FB20_Pos (20U)

◆ CAN_F3R2_FB21

#define CAN_F3R2_FB21 CAN_F3R2_FB21_Msk

Filter bit 21

◆ CAN_F3R2_FB21_Msk

#define CAN_F3R2_FB21_Msk (0x1UL << CAN_F3R2_FB21_Pos)

0x00200000

◆ CAN_F3R2_FB21_Pos

#define CAN_F3R2_FB21_Pos (21U)

◆ CAN_F3R2_FB22

#define CAN_F3R2_FB22 CAN_F3R2_FB22_Msk

Filter bit 22

◆ CAN_F3R2_FB22_Msk

#define CAN_F3R2_FB22_Msk (0x1UL << CAN_F3R2_FB22_Pos)

0x00400000

◆ CAN_F3R2_FB22_Pos

#define CAN_F3R2_FB22_Pos (22U)

◆ CAN_F3R2_FB23

#define CAN_F3R2_FB23 CAN_F3R2_FB23_Msk

Filter bit 23

◆ CAN_F3R2_FB23_Msk

#define CAN_F3R2_FB23_Msk (0x1UL << CAN_F3R2_FB23_Pos)

0x00800000

◆ CAN_F3R2_FB23_Pos

#define CAN_F3R2_FB23_Pos (23U)

◆ CAN_F3R2_FB24

#define CAN_F3R2_FB24 CAN_F3R2_FB24_Msk

Filter bit 24

◆ CAN_F3R2_FB24_Msk

#define CAN_F3R2_FB24_Msk (0x1UL << CAN_F3R2_FB24_Pos)

0x01000000

◆ CAN_F3R2_FB24_Pos

#define CAN_F3R2_FB24_Pos (24U)

◆ CAN_F3R2_FB25

#define CAN_F3R2_FB25 CAN_F3R2_FB25_Msk

Filter bit 25

◆ CAN_F3R2_FB25_Msk

#define CAN_F3R2_FB25_Msk (0x1UL << CAN_F3R2_FB25_Pos)

0x02000000

◆ CAN_F3R2_FB25_Pos

#define CAN_F3R2_FB25_Pos (25U)

◆ CAN_F3R2_FB26

#define CAN_F3R2_FB26 CAN_F3R2_FB26_Msk

Filter bit 26

◆ CAN_F3R2_FB26_Msk

#define CAN_F3R2_FB26_Msk (0x1UL << CAN_F3R2_FB26_Pos)

0x04000000

◆ CAN_F3R2_FB26_Pos

#define CAN_F3R2_FB26_Pos (26U)

◆ CAN_F3R2_FB27

#define CAN_F3R2_FB27 CAN_F3R2_FB27_Msk

Filter bit 27

◆ CAN_F3R2_FB27_Msk

#define CAN_F3R2_FB27_Msk (0x1UL << CAN_F3R2_FB27_Pos)

0x08000000

◆ CAN_F3R2_FB27_Pos

#define CAN_F3R2_FB27_Pos (27U)

◆ CAN_F3R2_FB28

#define CAN_F3R2_FB28 CAN_F3R2_FB28_Msk

Filter bit 28

◆ CAN_F3R2_FB28_Msk

#define CAN_F3R2_FB28_Msk (0x1UL << CAN_F3R2_FB28_Pos)

0x10000000

◆ CAN_F3R2_FB28_Pos

#define CAN_F3R2_FB28_Pos (28U)

◆ CAN_F3R2_FB29

#define CAN_F3R2_FB29 CAN_F3R2_FB29_Msk

Filter bit 29

◆ CAN_F3R2_FB29_Msk

#define CAN_F3R2_FB29_Msk (0x1UL << CAN_F3R2_FB29_Pos)

0x20000000

◆ CAN_F3R2_FB29_Pos

#define CAN_F3R2_FB29_Pos (29U)

◆ CAN_F3R2_FB2_Msk

#define CAN_F3R2_FB2_Msk (0x1UL << CAN_F3R2_FB2_Pos)

0x00000004

◆ CAN_F3R2_FB2_Pos

#define CAN_F3R2_FB2_Pos (2U)

◆ CAN_F3R2_FB3

#define CAN_F3R2_FB3 CAN_F3R2_FB3_Msk

Filter bit 3

◆ CAN_F3R2_FB30

#define CAN_F3R2_FB30 CAN_F3R2_FB30_Msk

Filter bit 30

◆ CAN_F3R2_FB30_Msk

#define CAN_F3R2_FB30_Msk (0x1UL << CAN_F3R2_FB30_Pos)

0x40000000

◆ CAN_F3R2_FB30_Pos

#define CAN_F3R2_FB30_Pos (30U)

◆ CAN_F3R2_FB31

#define CAN_F3R2_FB31 CAN_F3R2_FB31_Msk

Filter bit 31

◆ CAN_F3R2_FB31_Msk

#define CAN_F3R2_FB31_Msk (0x1UL << CAN_F3R2_FB31_Pos)

0x80000000

◆ CAN_F3R2_FB31_Pos

#define CAN_F3R2_FB31_Pos (31U)

◆ CAN_F3R2_FB3_Msk

#define CAN_F3R2_FB3_Msk (0x1UL << CAN_F3R2_FB3_Pos)

0x00000008

◆ CAN_F3R2_FB3_Pos

#define CAN_F3R2_FB3_Pos (3U)

◆ CAN_F3R2_FB4

#define CAN_F3R2_FB4 CAN_F3R2_FB4_Msk

Filter bit 4

◆ CAN_F3R2_FB4_Msk

#define CAN_F3R2_FB4_Msk (0x1UL << CAN_F3R2_FB4_Pos)

0x00000010

◆ CAN_F3R2_FB4_Pos

#define CAN_F3R2_FB4_Pos (4U)

◆ CAN_F3R2_FB5

#define CAN_F3R2_FB5 CAN_F3R2_FB5_Msk

Filter bit 5

◆ CAN_F3R2_FB5_Msk

#define CAN_F3R2_FB5_Msk (0x1UL << CAN_F3R2_FB5_Pos)

0x00000020

◆ CAN_F3R2_FB5_Pos

#define CAN_F3R2_FB5_Pos (5U)

◆ CAN_F3R2_FB6

#define CAN_F3R2_FB6 CAN_F3R2_FB6_Msk

Filter bit 6

◆ CAN_F3R2_FB6_Msk

#define CAN_F3R2_FB6_Msk (0x1UL << CAN_F3R2_FB6_Pos)

0x00000040

◆ CAN_F3R2_FB6_Pos

#define CAN_F3R2_FB6_Pos (6U)

◆ CAN_F3R2_FB7

#define CAN_F3R2_FB7 CAN_F3R2_FB7_Msk

Filter bit 7

◆ CAN_F3R2_FB7_Msk

#define CAN_F3R2_FB7_Msk (0x1UL << CAN_F3R2_FB7_Pos)

0x00000080

◆ CAN_F3R2_FB7_Pos

#define CAN_F3R2_FB7_Pos (7U)

◆ CAN_F3R2_FB8

#define CAN_F3R2_FB8 CAN_F3R2_FB8_Msk

Filter bit 8

◆ CAN_F3R2_FB8_Msk

#define CAN_F3R2_FB8_Msk (0x1UL << CAN_F3R2_FB8_Pos)

0x00000100

◆ CAN_F3R2_FB8_Pos

#define CAN_F3R2_FB8_Pos (8U)

◆ CAN_F3R2_FB9

#define CAN_F3R2_FB9 CAN_F3R2_FB9_Msk

Filter bit 9

◆ CAN_F3R2_FB9_Msk

#define CAN_F3R2_FB9_Msk (0x1UL << CAN_F3R2_FB9_Pos)

0x00000200

◆ CAN_F3R2_FB9_Pos

#define CAN_F3R2_FB9_Pos (9U)

◆ CAN_F4R1_FB0

#define CAN_F4R1_FB0 CAN_F4R1_FB0_Msk

Filter bit 0

◆ CAN_F4R1_FB0_Msk

#define CAN_F4R1_FB0_Msk (0x1UL << CAN_F4R1_FB0_Pos)

0x00000001

◆ CAN_F4R1_FB0_Pos

#define CAN_F4R1_FB0_Pos (0U)

◆ CAN_F4R1_FB1

#define CAN_F4R1_FB1 CAN_F4R1_FB1_Msk

Filter bit 1

◆ CAN_F4R1_FB10

#define CAN_F4R1_FB10 CAN_F4R1_FB10_Msk

Filter bit 10

◆ CAN_F4R1_FB10_Msk

#define CAN_F4R1_FB10_Msk (0x1UL << CAN_F4R1_FB10_Pos)

0x00000400

◆ CAN_F4R1_FB10_Pos

#define CAN_F4R1_FB10_Pos (10U)

◆ CAN_F4R1_FB11

#define CAN_F4R1_FB11 CAN_F4R1_FB11_Msk

Filter bit 11

◆ CAN_F4R1_FB11_Msk

#define CAN_F4R1_FB11_Msk (0x1UL << CAN_F4R1_FB11_Pos)

0x00000800

◆ CAN_F4R1_FB11_Pos

#define CAN_F4R1_FB11_Pos (11U)

◆ CAN_F4R1_FB12

#define CAN_F4R1_FB12 CAN_F4R1_FB12_Msk

Filter bit 12

◆ CAN_F4R1_FB12_Msk

#define CAN_F4R1_FB12_Msk (0x1UL << CAN_F4R1_FB12_Pos)

0x00001000

◆ CAN_F4R1_FB12_Pos

#define CAN_F4R1_FB12_Pos (12U)

◆ CAN_F4R1_FB13

#define CAN_F4R1_FB13 CAN_F4R1_FB13_Msk

Filter bit 13

◆ CAN_F4R1_FB13_Msk

#define CAN_F4R1_FB13_Msk (0x1UL << CAN_F4R1_FB13_Pos)

0x00002000

◆ CAN_F4R1_FB13_Pos

#define CAN_F4R1_FB13_Pos (13U)

◆ CAN_F4R1_FB14

#define CAN_F4R1_FB14 CAN_F4R1_FB14_Msk

Filter bit 14

◆ CAN_F4R1_FB14_Msk

#define CAN_F4R1_FB14_Msk (0x1UL << CAN_F4R1_FB14_Pos)

0x00004000

◆ CAN_F4R1_FB14_Pos

#define CAN_F4R1_FB14_Pos (14U)

◆ CAN_F4R1_FB15

#define CAN_F4R1_FB15 CAN_F4R1_FB15_Msk

Filter bit 15

◆ CAN_F4R1_FB15_Msk

#define CAN_F4R1_FB15_Msk (0x1UL << CAN_F4R1_FB15_Pos)

0x00008000

◆ CAN_F4R1_FB15_Pos

#define CAN_F4R1_FB15_Pos (15U)

◆ CAN_F4R1_FB16

#define CAN_F4R1_FB16 CAN_F4R1_FB16_Msk

Filter bit 16

◆ CAN_F4R1_FB16_Msk

#define CAN_F4R1_FB16_Msk (0x1UL << CAN_F4R1_FB16_Pos)

0x00010000

◆ CAN_F4R1_FB16_Pos

#define CAN_F4R1_FB16_Pos (16U)

◆ CAN_F4R1_FB17

#define CAN_F4R1_FB17 CAN_F4R1_FB17_Msk

Filter bit 17

◆ CAN_F4R1_FB17_Msk

#define CAN_F4R1_FB17_Msk (0x1UL << CAN_F4R1_FB17_Pos)

0x00020000

◆ CAN_F4R1_FB17_Pos

#define CAN_F4R1_FB17_Pos (17U)

◆ CAN_F4R1_FB18

#define CAN_F4R1_FB18 CAN_F4R1_FB18_Msk

Filter bit 18

◆ CAN_F4R1_FB18_Msk

#define CAN_F4R1_FB18_Msk (0x1UL << CAN_F4R1_FB18_Pos)

0x00040000

◆ CAN_F4R1_FB18_Pos

#define CAN_F4R1_FB18_Pos (18U)

◆ CAN_F4R1_FB19

#define CAN_F4R1_FB19 CAN_F4R1_FB19_Msk

Filter bit 19

◆ CAN_F4R1_FB19_Msk

#define CAN_F4R1_FB19_Msk (0x1UL << CAN_F4R1_FB19_Pos)

0x00080000

◆ CAN_F4R1_FB19_Pos

#define CAN_F4R1_FB19_Pos (19U)

◆ CAN_F4R1_FB1_Msk

#define CAN_F4R1_FB1_Msk (0x1UL << CAN_F4R1_FB1_Pos)

0x00000002

◆ CAN_F4R1_FB1_Pos

#define CAN_F4R1_FB1_Pos (1U)

◆ CAN_F4R1_FB2

#define CAN_F4R1_FB2 CAN_F4R1_FB2_Msk

Filter bit 2

◆ CAN_F4R1_FB20

#define CAN_F4R1_FB20 CAN_F4R1_FB20_Msk

Filter bit 20

◆ CAN_F4R1_FB20_Msk

#define CAN_F4R1_FB20_Msk (0x1UL << CAN_F4R1_FB20_Pos)

0x00100000

◆ CAN_F4R1_FB20_Pos

#define CAN_F4R1_FB20_Pos (20U)

◆ CAN_F4R1_FB21

#define CAN_F4R1_FB21 CAN_F4R1_FB21_Msk

Filter bit 21

◆ CAN_F4R1_FB21_Msk

#define CAN_F4R1_FB21_Msk (0x1UL << CAN_F4R1_FB21_Pos)

0x00200000

◆ CAN_F4R1_FB21_Pos

#define CAN_F4R1_FB21_Pos (21U)

◆ CAN_F4R1_FB22

#define CAN_F4R1_FB22 CAN_F4R1_FB22_Msk

Filter bit 22

◆ CAN_F4R1_FB22_Msk

#define CAN_F4R1_FB22_Msk (0x1UL << CAN_F4R1_FB22_Pos)

0x00400000

◆ CAN_F4R1_FB22_Pos

#define CAN_F4R1_FB22_Pos (22U)

◆ CAN_F4R1_FB23

#define CAN_F4R1_FB23 CAN_F4R1_FB23_Msk

Filter bit 23

◆ CAN_F4R1_FB23_Msk

#define CAN_F4R1_FB23_Msk (0x1UL << CAN_F4R1_FB23_Pos)

0x00800000

◆ CAN_F4R1_FB23_Pos

#define CAN_F4R1_FB23_Pos (23U)

◆ CAN_F4R1_FB24

#define CAN_F4R1_FB24 CAN_F4R1_FB24_Msk

Filter bit 24

◆ CAN_F4R1_FB24_Msk

#define CAN_F4R1_FB24_Msk (0x1UL << CAN_F4R1_FB24_Pos)

0x01000000

◆ CAN_F4R1_FB24_Pos

#define CAN_F4R1_FB24_Pos (24U)

◆ CAN_F4R1_FB25

#define CAN_F4R1_FB25 CAN_F4R1_FB25_Msk

Filter bit 25

◆ CAN_F4R1_FB25_Msk

#define CAN_F4R1_FB25_Msk (0x1UL << CAN_F4R1_FB25_Pos)

0x02000000

◆ CAN_F4R1_FB25_Pos

#define CAN_F4R1_FB25_Pos (25U)

◆ CAN_F4R1_FB26

#define CAN_F4R1_FB26 CAN_F4R1_FB26_Msk

Filter bit 26

◆ CAN_F4R1_FB26_Msk

#define CAN_F4R1_FB26_Msk (0x1UL << CAN_F4R1_FB26_Pos)

0x04000000

◆ CAN_F4R1_FB26_Pos

#define CAN_F4R1_FB26_Pos (26U)

◆ CAN_F4R1_FB27

#define CAN_F4R1_FB27 CAN_F4R1_FB27_Msk

Filter bit 27

◆ CAN_F4R1_FB27_Msk

#define CAN_F4R1_FB27_Msk (0x1UL << CAN_F4R1_FB27_Pos)

0x08000000

◆ CAN_F4R1_FB27_Pos

#define CAN_F4R1_FB27_Pos (27U)

◆ CAN_F4R1_FB28

#define CAN_F4R1_FB28 CAN_F4R1_FB28_Msk

Filter bit 28

◆ CAN_F4R1_FB28_Msk

#define CAN_F4R1_FB28_Msk (0x1UL << CAN_F4R1_FB28_Pos)

0x10000000

◆ CAN_F4R1_FB28_Pos

#define CAN_F4R1_FB28_Pos (28U)

◆ CAN_F4R1_FB29

#define CAN_F4R1_FB29 CAN_F4R1_FB29_Msk

Filter bit 29

◆ CAN_F4R1_FB29_Msk

#define CAN_F4R1_FB29_Msk (0x1UL << CAN_F4R1_FB29_Pos)

0x20000000

◆ CAN_F4R1_FB29_Pos

#define CAN_F4R1_FB29_Pos (29U)

◆ CAN_F4R1_FB2_Msk

#define CAN_F4R1_FB2_Msk (0x1UL << CAN_F4R1_FB2_Pos)

0x00000004

◆ CAN_F4R1_FB2_Pos

#define CAN_F4R1_FB2_Pos (2U)

◆ CAN_F4R1_FB3

#define CAN_F4R1_FB3 CAN_F4R1_FB3_Msk

Filter bit 3

◆ CAN_F4R1_FB30

#define CAN_F4R1_FB30 CAN_F4R1_FB30_Msk

Filter bit 30

◆ CAN_F4R1_FB30_Msk

#define CAN_F4R1_FB30_Msk (0x1UL << CAN_F4R1_FB30_Pos)

0x40000000

◆ CAN_F4R1_FB30_Pos

#define CAN_F4R1_FB30_Pos (30U)

◆ CAN_F4R1_FB31

#define CAN_F4R1_FB31 CAN_F4R1_FB31_Msk

Filter bit 31

◆ CAN_F4R1_FB31_Msk

#define CAN_F4R1_FB31_Msk (0x1UL << CAN_F4R1_FB31_Pos)

0x80000000

◆ CAN_F4R1_FB31_Pos

#define CAN_F4R1_FB31_Pos (31U)

◆ CAN_F4R1_FB3_Msk

#define CAN_F4R1_FB3_Msk (0x1UL << CAN_F4R1_FB3_Pos)

0x00000008

◆ CAN_F4R1_FB3_Pos

#define CAN_F4R1_FB3_Pos (3U)

◆ CAN_F4R1_FB4

#define CAN_F4R1_FB4 CAN_F4R1_FB4_Msk

Filter bit 4

◆ CAN_F4R1_FB4_Msk

#define CAN_F4R1_FB4_Msk (0x1UL << CAN_F4R1_FB4_Pos)

0x00000010

◆ CAN_F4R1_FB4_Pos

#define CAN_F4R1_FB4_Pos (4U)

◆ CAN_F4R1_FB5

#define CAN_F4R1_FB5 CAN_F4R1_FB5_Msk

Filter bit 5

◆ CAN_F4R1_FB5_Msk

#define CAN_F4R1_FB5_Msk (0x1UL << CAN_F4R1_FB5_Pos)

0x00000020

◆ CAN_F4R1_FB5_Pos

#define CAN_F4R1_FB5_Pos (5U)

◆ CAN_F4R1_FB6

#define CAN_F4R1_FB6 CAN_F4R1_FB6_Msk

Filter bit 6

◆ CAN_F4R1_FB6_Msk

#define CAN_F4R1_FB6_Msk (0x1UL << CAN_F4R1_FB6_Pos)

0x00000040

◆ CAN_F4R1_FB6_Pos

#define CAN_F4R1_FB6_Pos (6U)

◆ CAN_F4R1_FB7

#define CAN_F4R1_FB7 CAN_F4R1_FB7_Msk

Filter bit 7

◆ CAN_F4R1_FB7_Msk

#define CAN_F4R1_FB7_Msk (0x1UL << CAN_F4R1_FB7_Pos)

0x00000080

◆ CAN_F4R1_FB7_Pos

#define CAN_F4R1_FB7_Pos (7U)

◆ CAN_F4R1_FB8

#define CAN_F4R1_FB8 CAN_F4R1_FB8_Msk

Filter bit 8

◆ CAN_F4R1_FB8_Msk

#define CAN_F4R1_FB8_Msk (0x1UL << CAN_F4R1_FB8_Pos)

0x00000100

◆ CAN_F4R1_FB8_Pos

#define CAN_F4R1_FB8_Pos (8U)

◆ CAN_F4R1_FB9

#define CAN_F4R1_FB9 CAN_F4R1_FB9_Msk

Filter bit 9

◆ CAN_F4R1_FB9_Msk

#define CAN_F4R1_FB9_Msk (0x1UL << CAN_F4R1_FB9_Pos)

0x00000200

◆ CAN_F4R1_FB9_Pos

#define CAN_F4R1_FB9_Pos (9U)

◆ CAN_F4R2_FB0

#define CAN_F4R2_FB0 CAN_F4R2_FB0_Msk

Filter bit 0

◆ CAN_F4R2_FB0_Msk

#define CAN_F4R2_FB0_Msk (0x1UL << CAN_F4R2_FB0_Pos)

0x00000001

◆ CAN_F4R2_FB0_Pos

#define CAN_F4R2_FB0_Pos (0U)

◆ CAN_F4R2_FB1

#define CAN_F4R2_FB1 CAN_F4R2_FB1_Msk

Filter bit 1

◆ CAN_F4R2_FB10

#define CAN_F4R2_FB10 CAN_F4R2_FB10_Msk

Filter bit 10

◆ CAN_F4R2_FB10_Msk

#define CAN_F4R2_FB10_Msk (0x1UL << CAN_F4R2_FB10_Pos)

0x00000400

◆ CAN_F4R2_FB10_Pos

#define CAN_F4R2_FB10_Pos (10U)

◆ CAN_F4R2_FB11

#define CAN_F4R2_FB11 CAN_F4R2_FB11_Msk

Filter bit 11

◆ CAN_F4R2_FB11_Msk

#define CAN_F4R2_FB11_Msk (0x1UL << CAN_F4R2_FB11_Pos)

0x00000800

◆ CAN_F4R2_FB11_Pos

#define CAN_F4R2_FB11_Pos (11U)

◆ CAN_F4R2_FB12

#define CAN_F4R2_FB12 CAN_F4R2_FB12_Msk

Filter bit 12

◆ CAN_F4R2_FB12_Msk

#define CAN_F4R2_FB12_Msk (0x1UL << CAN_F4R2_FB12_Pos)

0x00001000

◆ CAN_F4R2_FB12_Pos

#define CAN_F4R2_FB12_Pos (12U)

◆ CAN_F4R2_FB13

#define CAN_F4R2_FB13 CAN_F4R2_FB13_Msk

Filter bit 13

◆ CAN_F4R2_FB13_Msk

#define CAN_F4R2_FB13_Msk (0x1UL << CAN_F4R2_FB13_Pos)

0x00002000

◆ CAN_F4R2_FB13_Pos

#define CAN_F4R2_FB13_Pos (13U)

◆ CAN_F4R2_FB14

#define CAN_F4R2_FB14 CAN_F4R2_FB14_Msk

Filter bit 14

◆ CAN_F4R2_FB14_Msk

#define CAN_F4R2_FB14_Msk (0x1UL << CAN_F4R2_FB14_Pos)

0x00004000

◆ CAN_F4R2_FB14_Pos

#define CAN_F4R2_FB14_Pos (14U)

◆ CAN_F4R2_FB15

#define CAN_F4R2_FB15 CAN_F4R2_FB15_Msk

Filter bit 15

◆ CAN_F4R2_FB15_Msk

#define CAN_F4R2_FB15_Msk (0x1UL << CAN_F4R2_FB15_Pos)

0x00008000

◆ CAN_F4R2_FB15_Pos

#define CAN_F4R2_FB15_Pos (15U)

◆ CAN_F4R2_FB16

#define CAN_F4R2_FB16 CAN_F4R2_FB16_Msk

Filter bit 16

◆ CAN_F4R2_FB16_Msk

#define CAN_F4R2_FB16_Msk (0x1UL << CAN_F4R2_FB16_Pos)

0x00010000

◆ CAN_F4R2_FB16_Pos

#define CAN_F4R2_FB16_Pos (16U)

◆ CAN_F4R2_FB17

#define CAN_F4R2_FB17 CAN_F4R2_FB17_Msk

Filter bit 17

◆ CAN_F4R2_FB17_Msk

#define CAN_F4R2_FB17_Msk (0x1UL << CAN_F4R2_FB17_Pos)

0x00020000

◆ CAN_F4R2_FB17_Pos

#define CAN_F4R2_FB17_Pos (17U)

◆ CAN_F4R2_FB18

#define CAN_F4R2_FB18 CAN_F4R2_FB18_Msk

Filter bit 18

◆ CAN_F4R2_FB18_Msk

#define CAN_F4R2_FB18_Msk (0x1UL << CAN_F4R2_FB18_Pos)

0x00040000

◆ CAN_F4R2_FB18_Pos

#define CAN_F4R2_FB18_Pos (18U)

◆ CAN_F4R2_FB19

#define CAN_F4R2_FB19 CAN_F4R2_FB19_Msk

Filter bit 19

◆ CAN_F4R2_FB19_Msk

#define CAN_F4R2_FB19_Msk (0x1UL << CAN_F4R2_FB19_Pos)

0x00080000

◆ CAN_F4R2_FB19_Pos

#define CAN_F4R2_FB19_Pos (19U)

◆ CAN_F4R2_FB1_Msk

#define CAN_F4R2_FB1_Msk (0x1UL << CAN_F4R2_FB1_Pos)

0x00000002

◆ CAN_F4R2_FB1_Pos

#define CAN_F4R2_FB1_Pos (1U)

◆ CAN_F4R2_FB2

#define CAN_F4R2_FB2 CAN_F4R2_FB2_Msk

Filter bit 2

◆ CAN_F4R2_FB20

#define CAN_F4R2_FB20 CAN_F4R2_FB20_Msk

Filter bit 20

◆ CAN_F4R2_FB20_Msk

#define CAN_F4R2_FB20_Msk (0x1UL << CAN_F4R2_FB20_Pos)

0x00100000

◆ CAN_F4R2_FB20_Pos

#define CAN_F4R2_FB20_Pos (20U)

◆ CAN_F4R2_FB21

#define CAN_F4R2_FB21 CAN_F4R2_FB21_Msk

Filter bit 21

◆ CAN_F4R2_FB21_Msk

#define CAN_F4R2_FB21_Msk (0x1UL << CAN_F4R2_FB21_Pos)

0x00200000

◆ CAN_F4R2_FB21_Pos

#define CAN_F4R2_FB21_Pos (21U)

◆ CAN_F4R2_FB22

#define CAN_F4R2_FB22 CAN_F4R2_FB22_Msk

Filter bit 22

◆ CAN_F4R2_FB22_Msk

#define CAN_F4R2_FB22_Msk (0x1UL << CAN_F4R2_FB22_Pos)

0x00400000

◆ CAN_F4R2_FB22_Pos

#define CAN_F4R2_FB22_Pos (22U)

◆ CAN_F4R2_FB23

#define CAN_F4R2_FB23 CAN_F4R2_FB23_Msk

Filter bit 23

◆ CAN_F4R2_FB23_Msk

#define CAN_F4R2_FB23_Msk (0x1UL << CAN_F4R2_FB23_Pos)

0x00800000

◆ CAN_F4R2_FB23_Pos

#define CAN_F4R2_FB23_Pos (23U)

◆ CAN_F4R2_FB24

#define CAN_F4R2_FB24 CAN_F4R2_FB24_Msk

Filter bit 24

◆ CAN_F4R2_FB24_Msk

#define CAN_F4R2_FB24_Msk (0x1UL << CAN_F4R2_FB24_Pos)

0x01000000

◆ CAN_F4R2_FB24_Pos

#define CAN_F4R2_FB24_Pos (24U)

◆ CAN_F4R2_FB25

#define CAN_F4R2_FB25 CAN_F4R2_FB25_Msk

Filter bit 25

◆ CAN_F4R2_FB25_Msk

#define CAN_F4R2_FB25_Msk (0x1UL << CAN_F4R2_FB25_Pos)

0x02000000

◆ CAN_F4R2_FB25_Pos

#define CAN_F4R2_FB25_Pos (25U)

◆ CAN_F4R2_FB26

#define CAN_F4R2_FB26 CAN_F4R2_FB26_Msk

Filter bit 26

◆ CAN_F4R2_FB26_Msk

#define CAN_F4R2_FB26_Msk (0x1UL << CAN_F4R2_FB26_Pos)

0x04000000

◆ CAN_F4R2_FB26_Pos

#define CAN_F4R2_FB26_Pos (26U)

◆ CAN_F4R2_FB27

#define CAN_F4R2_FB27 CAN_F4R2_FB27_Msk

Filter bit 27

◆ CAN_F4R2_FB27_Msk

#define CAN_F4R2_FB27_Msk (0x1UL << CAN_F4R2_FB27_Pos)

0x08000000

◆ CAN_F4R2_FB27_Pos

#define CAN_F4R2_FB27_Pos (27U)

◆ CAN_F4R2_FB28

#define CAN_F4R2_FB28 CAN_F4R2_FB28_Msk

Filter bit 28

◆ CAN_F4R2_FB28_Msk

#define CAN_F4R2_FB28_Msk (0x1UL << CAN_F4R2_FB28_Pos)

0x10000000

◆ CAN_F4R2_FB28_Pos

#define CAN_F4R2_FB28_Pos (28U)

◆ CAN_F4R2_FB29

#define CAN_F4R2_FB29 CAN_F4R2_FB29_Msk

Filter bit 29

◆ CAN_F4R2_FB29_Msk

#define CAN_F4R2_FB29_Msk (0x1UL << CAN_F4R2_FB29_Pos)

0x20000000

◆ CAN_F4R2_FB29_Pos

#define CAN_F4R2_FB29_Pos (29U)

◆ CAN_F4R2_FB2_Msk

#define CAN_F4R2_FB2_Msk (0x1UL << CAN_F4R2_FB2_Pos)

0x00000004

◆ CAN_F4R2_FB2_Pos

#define CAN_F4R2_FB2_Pos (2U)

◆ CAN_F4R2_FB3

#define CAN_F4R2_FB3 CAN_F4R2_FB3_Msk

Filter bit 3

◆ CAN_F4R2_FB30

#define CAN_F4R2_FB30 CAN_F4R2_FB30_Msk

Filter bit 30

◆ CAN_F4R2_FB30_Msk

#define CAN_F4R2_FB30_Msk (0x1UL << CAN_F4R2_FB30_Pos)

0x40000000

◆ CAN_F4R2_FB30_Pos

#define CAN_F4R2_FB30_Pos (30U)

◆ CAN_F4R2_FB31

#define CAN_F4R2_FB31 CAN_F4R2_FB31_Msk

Filter bit 31

◆ CAN_F4R2_FB31_Msk

#define CAN_F4R2_FB31_Msk (0x1UL << CAN_F4R2_FB31_Pos)

0x80000000

◆ CAN_F4R2_FB31_Pos

#define CAN_F4R2_FB31_Pos (31U)

◆ CAN_F4R2_FB3_Msk

#define CAN_F4R2_FB3_Msk (0x1UL << CAN_F4R2_FB3_Pos)

0x00000008

◆ CAN_F4R2_FB3_Pos

#define CAN_F4R2_FB3_Pos (3U)

◆ CAN_F4R2_FB4

#define CAN_F4R2_FB4 CAN_F4R2_FB4_Msk

Filter bit 4

◆ CAN_F4R2_FB4_Msk

#define CAN_F4R2_FB4_Msk (0x1UL << CAN_F4R2_FB4_Pos)

0x00000010

◆ CAN_F4R2_FB4_Pos

#define CAN_F4R2_FB4_Pos (4U)

◆ CAN_F4R2_FB5

#define CAN_F4R2_FB5 CAN_F4R2_FB5_Msk

Filter bit 5

◆ CAN_F4R2_FB5_Msk

#define CAN_F4R2_FB5_Msk (0x1UL << CAN_F4R2_FB5_Pos)

0x00000020

◆ CAN_F4R2_FB5_Pos

#define CAN_F4R2_FB5_Pos (5U)

◆ CAN_F4R2_FB6

#define CAN_F4R2_FB6 CAN_F4R2_FB6_Msk

Filter bit 6

◆ CAN_F4R2_FB6_Msk

#define CAN_F4R2_FB6_Msk (0x1UL << CAN_F4R2_FB6_Pos)

0x00000040

◆ CAN_F4R2_FB6_Pos

#define CAN_F4R2_FB6_Pos (6U)

◆ CAN_F4R2_FB7

#define CAN_F4R2_FB7 CAN_F4R2_FB7_Msk

Filter bit 7

◆ CAN_F4R2_FB7_Msk

#define CAN_F4R2_FB7_Msk (0x1UL << CAN_F4R2_FB7_Pos)

0x00000080

◆ CAN_F4R2_FB7_Pos

#define CAN_F4R2_FB7_Pos (7U)

◆ CAN_F4R2_FB8

#define CAN_F4R2_FB8 CAN_F4R2_FB8_Msk

Filter bit 8

◆ CAN_F4R2_FB8_Msk

#define CAN_F4R2_FB8_Msk (0x1UL << CAN_F4R2_FB8_Pos)

0x00000100

◆ CAN_F4R2_FB8_Pos

#define CAN_F4R2_FB8_Pos (8U)

◆ CAN_F4R2_FB9

#define CAN_F4R2_FB9 CAN_F4R2_FB9_Msk

Filter bit 9

◆ CAN_F4R2_FB9_Msk

#define CAN_F4R2_FB9_Msk (0x1UL << CAN_F4R2_FB9_Pos)

0x00000200

◆ CAN_F4R2_FB9_Pos

#define CAN_F4R2_FB9_Pos (9U)

◆ CAN_F5R1_FB0

#define CAN_F5R1_FB0 CAN_F5R1_FB0_Msk

Filter bit 0

◆ CAN_F5R1_FB0_Msk

#define CAN_F5R1_FB0_Msk (0x1UL << CAN_F5R1_FB0_Pos)

0x00000001

◆ CAN_F5R1_FB0_Pos

#define CAN_F5R1_FB0_Pos (0U)

◆ CAN_F5R1_FB1

#define CAN_F5R1_FB1 CAN_F5R1_FB1_Msk

Filter bit 1

◆ CAN_F5R1_FB10

#define CAN_F5R1_FB10 CAN_F5R1_FB10_Msk

Filter bit 10

◆ CAN_F5R1_FB10_Msk

#define CAN_F5R1_FB10_Msk (0x1UL << CAN_F5R1_FB10_Pos)

0x00000400

◆ CAN_F5R1_FB10_Pos

#define CAN_F5R1_FB10_Pos (10U)

◆ CAN_F5R1_FB11

#define CAN_F5R1_FB11 CAN_F5R1_FB11_Msk

Filter bit 11

◆ CAN_F5R1_FB11_Msk

#define CAN_F5R1_FB11_Msk (0x1UL << CAN_F5R1_FB11_Pos)

0x00000800

◆ CAN_F5R1_FB11_Pos

#define CAN_F5R1_FB11_Pos (11U)

◆ CAN_F5R1_FB12

#define CAN_F5R1_FB12 CAN_F5R1_FB12_Msk

Filter bit 12

◆ CAN_F5R1_FB12_Msk

#define CAN_F5R1_FB12_Msk (0x1UL << CAN_F5R1_FB12_Pos)

0x00001000

◆ CAN_F5R1_FB12_Pos

#define CAN_F5R1_FB12_Pos (12U)

◆ CAN_F5R1_FB13

#define CAN_F5R1_FB13 CAN_F5R1_FB13_Msk

Filter bit 13

◆ CAN_F5R1_FB13_Msk

#define CAN_F5R1_FB13_Msk (0x1UL << CAN_F5R1_FB13_Pos)

0x00002000

◆ CAN_F5R1_FB13_Pos

#define CAN_F5R1_FB13_Pos (13U)

◆ CAN_F5R1_FB14

#define CAN_F5R1_FB14 CAN_F5R1_FB14_Msk

Filter bit 14

◆ CAN_F5R1_FB14_Msk

#define CAN_F5R1_FB14_Msk (0x1UL << CAN_F5R1_FB14_Pos)

0x00004000

◆ CAN_F5R1_FB14_Pos

#define CAN_F5R1_FB14_Pos (14U)

◆ CAN_F5R1_FB15

#define CAN_F5R1_FB15 CAN_F5R1_FB15_Msk

Filter bit 15

◆ CAN_F5R1_FB15_Msk

#define CAN_F5R1_FB15_Msk (0x1UL << CAN_F5R1_FB15_Pos)

0x00008000

◆ CAN_F5R1_FB15_Pos

#define CAN_F5R1_FB15_Pos (15U)

◆ CAN_F5R1_FB16

#define CAN_F5R1_FB16 CAN_F5R1_FB16_Msk

Filter bit 16

◆ CAN_F5R1_FB16_Msk

#define CAN_F5R1_FB16_Msk (0x1UL << CAN_F5R1_FB16_Pos)

0x00010000

◆ CAN_F5R1_FB16_Pos

#define CAN_F5R1_FB16_Pos (16U)

◆ CAN_F5R1_FB17

#define CAN_F5R1_FB17 CAN_F5R1_FB17_Msk

Filter bit 17

◆ CAN_F5R1_FB17_Msk

#define CAN_F5R1_FB17_Msk (0x1UL << CAN_F5R1_FB17_Pos)

0x00020000

◆ CAN_F5R1_FB17_Pos

#define CAN_F5R1_FB17_Pos (17U)

◆ CAN_F5R1_FB18

#define CAN_F5R1_FB18 CAN_F5R1_FB18_Msk

Filter bit 18

◆ CAN_F5R1_FB18_Msk

#define CAN_F5R1_FB18_Msk (0x1UL << CAN_F5R1_FB18_Pos)

0x00040000

◆ CAN_F5R1_FB18_Pos

#define CAN_F5R1_FB18_Pos (18U)

◆ CAN_F5R1_FB19

#define CAN_F5R1_FB19 CAN_F5R1_FB19_Msk

Filter bit 19

◆ CAN_F5R1_FB19_Msk

#define CAN_F5R1_FB19_Msk (0x1UL << CAN_F5R1_FB19_Pos)

0x00080000

◆ CAN_F5R1_FB19_Pos

#define CAN_F5R1_FB19_Pos (19U)

◆ CAN_F5R1_FB1_Msk

#define CAN_F5R1_FB1_Msk (0x1UL << CAN_F5R1_FB1_Pos)

0x00000002

◆ CAN_F5R1_FB1_Pos

#define CAN_F5R1_FB1_Pos (1U)

◆ CAN_F5R1_FB2

#define CAN_F5R1_FB2 CAN_F5R1_FB2_Msk

Filter bit 2

◆ CAN_F5R1_FB20

#define CAN_F5R1_FB20 CAN_F5R1_FB20_Msk

Filter bit 20

◆ CAN_F5R1_FB20_Msk

#define CAN_F5R1_FB20_Msk (0x1UL << CAN_F5R1_FB20_Pos)

0x00100000

◆ CAN_F5R1_FB20_Pos

#define CAN_F5R1_FB20_Pos (20U)

◆ CAN_F5R1_FB21

#define CAN_F5R1_FB21 CAN_F5R1_FB21_Msk

Filter bit 21

◆ CAN_F5R1_FB21_Msk

#define CAN_F5R1_FB21_Msk (0x1UL << CAN_F5R1_FB21_Pos)

0x00200000

◆ CAN_F5R1_FB21_Pos

#define CAN_F5R1_FB21_Pos (21U)

◆ CAN_F5R1_FB22

#define CAN_F5R1_FB22 CAN_F5R1_FB22_Msk

Filter bit 22

◆ CAN_F5R1_FB22_Msk

#define CAN_F5R1_FB22_Msk (0x1UL << CAN_F5R1_FB22_Pos)

0x00400000

◆ CAN_F5R1_FB22_Pos

#define CAN_F5R1_FB22_Pos (22U)

◆ CAN_F5R1_FB23

#define CAN_F5R1_FB23 CAN_F5R1_FB23_Msk

Filter bit 23

◆ CAN_F5R1_FB23_Msk

#define CAN_F5R1_FB23_Msk (0x1UL << CAN_F5R1_FB23_Pos)

0x00800000

◆ CAN_F5R1_FB23_Pos

#define CAN_F5R1_FB23_Pos (23U)

◆ CAN_F5R1_FB24

#define CAN_F5R1_FB24 CAN_F5R1_FB24_Msk

Filter bit 24

◆ CAN_F5R1_FB24_Msk

#define CAN_F5R1_FB24_Msk (0x1UL << CAN_F5R1_FB24_Pos)

0x01000000

◆ CAN_F5R1_FB24_Pos

#define CAN_F5R1_FB24_Pos (24U)

◆ CAN_F5R1_FB25

#define CAN_F5R1_FB25 CAN_F5R1_FB25_Msk

Filter bit 25

◆ CAN_F5R1_FB25_Msk

#define CAN_F5R1_FB25_Msk (0x1UL << CAN_F5R1_FB25_Pos)

0x02000000

◆ CAN_F5R1_FB25_Pos

#define CAN_F5R1_FB25_Pos (25U)

◆ CAN_F5R1_FB26

#define CAN_F5R1_FB26 CAN_F5R1_FB26_Msk

Filter bit 26

◆ CAN_F5R1_FB26_Msk

#define CAN_F5R1_FB26_Msk (0x1UL << CAN_F5R1_FB26_Pos)

0x04000000

◆ CAN_F5R1_FB26_Pos

#define CAN_F5R1_FB26_Pos (26U)

◆ CAN_F5R1_FB27

#define CAN_F5R1_FB27 CAN_F5R1_FB27_Msk

Filter bit 27

◆ CAN_F5R1_FB27_Msk

#define CAN_F5R1_FB27_Msk (0x1UL << CAN_F5R1_FB27_Pos)

0x08000000

◆ CAN_F5R1_FB27_Pos

#define CAN_F5R1_FB27_Pos (27U)

◆ CAN_F5R1_FB28

#define CAN_F5R1_FB28 CAN_F5R1_FB28_Msk

Filter bit 28

◆ CAN_F5R1_FB28_Msk

#define CAN_F5R1_FB28_Msk (0x1UL << CAN_F5R1_FB28_Pos)

0x10000000

◆ CAN_F5R1_FB28_Pos

#define CAN_F5R1_FB28_Pos (28U)

◆ CAN_F5R1_FB29

#define CAN_F5R1_FB29 CAN_F5R1_FB29_Msk

Filter bit 29

◆ CAN_F5R1_FB29_Msk

#define CAN_F5R1_FB29_Msk (0x1UL << CAN_F5R1_FB29_Pos)

0x20000000

◆ CAN_F5R1_FB29_Pos

#define CAN_F5R1_FB29_Pos (29U)

◆ CAN_F5R1_FB2_Msk

#define CAN_F5R1_FB2_Msk (0x1UL << CAN_F5R1_FB2_Pos)

0x00000004

◆ CAN_F5R1_FB2_Pos

#define CAN_F5R1_FB2_Pos (2U)

◆ CAN_F5R1_FB3

#define CAN_F5R1_FB3 CAN_F5R1_FB3_Msk

Filter bit 3

◆ CAN_F5R1_FB30

#define CAN_F5R1_FB30 CAN_F5R1_FB30_Msk

Filter bit 30

◆ CAN_F5R1_FB30_Msk

#define CAN_F5R1_FB30_Msk (0x1UL << CAN_F5R1_FB30_Pos)

0x40000000

◆ CAN_F5R1_FB30_Pos

#define CAN_F5R1_FB30_Pos (30U)

◆ CAN_F5R1_FB31

#define CAN_F5R1_FB31 CAN_F5R1_FB31_Msk

Filter bit 31

◆ CAN_F5R1_FB31_Msk

#define CAN_F5R1_FB31_Msk (0x1UL << CAN_F5R1_FB31_Pos)

0x80000000

◆ CAN_F5R1_FB31_Pos

#define CAN_F5R1_FB31_Pos (31U)

◆ CAN_F5R1_FB3_Msk

#define CAN_F5R1_FB3_Msk (0x1UL << CAN_F5R1_FB3_Pos)

0x00000008

◆ CAN_F5R1_FB3_Pos

#define CAN_F5R1_FB3_Pos (3U)

◆ CAN_F5R1_FB4

#define CAN_F5R1_FB4 CAN_F5R1_FB4_Msk

Filter bit 4

◆ CAN_F5R1_FB4_Msk

#define CAN_F5R1_FB4_Msk (0x1UL << CAN_F5R1_FB4_Pos)

0x00000010

◆ CAN_F5R1_FB4_Pos

#define CAN_F5R1_FB4_Pos (4U)

◆ CAN_F5R1_FB5

#define CAN_F5R1_FB5 CAN_F5R1_FB5_Msk

Filter bit 5

◆ CAN_F5R1_FB5_Msk

#define CAN_F5R1_FB5_Msk (0x1UL << CAN_F5R1_FB5_Pos)

0x00000020

◆ CAN_F5R1_FB5_Pos

#define CAN_F5R1_FB5_Pos (5U)

◆ CAN_F5R1_FB6

#define CAN_F5R1_FB6 CAN_F5R1_FB6_Msk

Filter bit 6

◆ CAN_F5R1_FB6_Msk

#define CAN_F5R1_FB6_Msk (0x1UL << CAN_F5R1_FB6_Pos)

0x00000040

◆ CAN_F5R1_FB6_Pos

#define CAN_F5R1_FB6_Pos (6U)

◆ CAN_F5R1_FB7

#define CAN_F5R1_FB7 CAN_F5R1_FB7_Msk

Filter bit 7

◆ CAN_F5R1_FB7_Msk

#define CAN_F5R1_FB7_Msk (0x1UL << CAN_F5R1_FB7_Pos)

0x00000080

◆ CAN_F5R1_FB7_Pos

#define CAN_F5R1_FB7_Pos (7U)

◆ CAN_F5R1_FB8

#define CAN_F5R1_FB8 CAN_F5R1_FB8_Msk

Filter bit 8

◆ CAN_F5R1_FB8_Msk

#define CAN_F5R1_FB8_Msk (0x1UL << CAN_F5R1_FB8_Pos)

0x00000100

◆ CAN_F5R1_FB8_Pos

#define CAN_F5R1_FB8_Pos (8U)

◆ CAN_F5R1_FB9

#define CAN_F5R1_FB9 CAN_F5R1_FB9_Msk

Filter bit 9

◆ CAN_F5R1_FB9_Msk

#define CAN_F5R1_FB9_Msk (0x1UL << CAN_F5R1_FB9_Pos)

0x00000200

◆ CAN_F5R1_FB9_Pos

#define CAN_F5R1_FB9_Pos (9U)

◆ CAN_F5R2_FB0

#define CAN_F5R2_FB0 CAN_F5R2_FB0_Msk

Filter bit 0

◆ CAN_F5R2_FB0_Msk

#define CAN_F5R2_FB0_Msk (0x1UL << CAN_F5R2_FB0_Pos)

0x00000001

◆ CAN_F5R2_FB0_Pos

#define CAN_F5R2_FB0_Pos (0U)

◆ CAN_F5R2_FB1

#define CAN_F5R2_FB1 CAN_F5R2_FB1_Msk

Filter bit 1

◆ CAN_F5R2_FB10

#define CAN_F5R2_FB10 CAN_F5R2_FB10_Msk

Filter bit 10

◆ CAN_F5R2_FB10_Msk

#define CAN_F5R2_FB10_Msk (0x1UL << CAN_F5R2_FB10_Pos)

0x00000400

◆ CAN_F5R2_FB10_Pos

#define CAN_F5R2_FB10_Pos (10U)

◆ CAN_F5R2_FB11

#define CAN_F5R2_FB11 CAN_F5R2_FB11_Msk

Filter bit 11

◆ CAN_F5R2_FB11_Msk

#define CAN_F5R2_FB11_Msk (0x1UL << CAN_F5R2_FB11_Pos)

0x00000800

◆ CAN_F5R2_FB11_Pos

#define CAN_F5R2_FB11_Pos (11U)

◆ CAN_F5R2_FB12

#define CAN_F5R2_FB12 CAN_F5R2_FB12_Msk

Filter bit 12

◆ CAN_F5R2_FB12_Msk

#define CAN_F5R2_FB12_Msk (0x1UL << CAN_F5R2_FB12_Pos)

0x00001000

◆ CAN_F5R2_FB12_Pos

#define CAN_F5R2_FB12_Pos (12U)

◆ CAN_F5R2_FB13

#define CAN_F5R2_FB13 CAN_F5R2_FB13_Msk

Filter bit 13

◆ CAN_F5R2_FB13_Msk

#define CAN_F5R2_FB13_Msk (0x1UL << CAN_F5R2_FB13_Pos)

0x00002000

◆ CAN_F5R2_FB13_Pos

#define CAN_F5R2_FB13_Pos (13U)

◆ CAN_F5R2_FB14

#define CAN_F5R2_FB14 CAN_F5R2_FB14_Msk

Filter bit 14

◆ CAN_F5R2_FB14_Msk

#define CAN_F5R2_FB14_Msk (0x1UL << CAN_F5R2_FB14_Pos)

0x00004000

◆ CAN_F5R2_FB14_Pos

#define CAN_F5R2_FB14_Pos (14U)

◆ CAN_F5R2_FB15

#define CAN_F5R2_FB15 CAN_F5R2_FB15_Msk

Filter bit 15

◆ CAN_F5R2_FB15_Msk

#define CAN_F5R2_FB15_Msk (0x1UL << CAN_F5R2_FB15_Pos)

0x00008000

◆ CAN_F5R2_FB15_Pos

#define CAN_F5R2_FB15_Pos (15U)

◆ CAN_F5R2_FB16

#define CAN_F5R2_FB16 CAN_F5R2_FB16_Msk

Filter bit 16

◆ CAN_F5R2_FB16_Msk

#define CAN_F5R2_FB16_Msk (0x1UL << CAN_F5R2_FB16_Pos)

0x00010000

◆ CAN_F5R2_FB16_Pos

#define CAN_F5R2_FB16_Pos (16U)

◆ CAN_F5R2_FB17

#define CAN_F5R2_FB17 CAN_F5R2_FB17_Msk

Filter bit 17

◆ CAN_F5R2_FB17_Msk

#define CAN_F5R2_FB17_Msk (0x1UL << CAN_F5R2_FB17_Pos)

0x00020000

◆ CAN_F5R2_FB17_Pos

#define CAN_F5R2_FB17_Pos (17U)

◆ CAN_F5R2_FB18

#define CAN_F5R2_FB18 CAN_F5R2_FB18_Msk

Filter bit 18

◆ CAN_F5R2_FB18_Msk

#define CAN_F5R2_FB18_Msk (0x1UL << CAN_F5R2_FB18_Pos)

0x00040000

◆ CAN_F5R2_FB18_Pos

#define CAN_F5R2_FB18_Pos (18U)

◆ CAN_F5R2_FB19

#define CAN_F5R2_FB19 CAN_F5R2_FB19_Msk

Filter bit 19

◆ CAN_F5R2_FB19_Msk

#define CAN_F5R2_FB19_Msk (0x1UL << CAN_F5R2_FB19_Pos)

0x00080000

◆ CAN_F5R2_FB19_Pos

#define CAN_F5R2_FB19_Pos (19U)

◆ CAN_F5R2_FB1_Msk

#define CAN_F5R2_FB1_Msk (0x1UL << CAN_F5R2_FB1_Pos)

0x00000002

◆ CAN_F5R2_FB1_Pos

#define CAN_F5R2_FB1_Pos (1U)

◆ CAN_F5R2_FB2

#define CAN_F5R2_FB2 CAN_F5R2_FB2_Msk

Filter bit 2

◆ CAN_F5R2_FB20

#define CAN_F5R2_FB20 CAN_F5R2_FB20_Msk

Filter bit 20

◆ CAN_F5R2_FB20_Msk

#define CAN_F5R2_FB20_Msk (0x1UL << CAN_F5R2_FB20_Pos)

0x00100000

◆ CAN_F5R2_FB20_Pos

#define CAN_F5R2_FB20_Pos (20U)

◆ CAN_F5R2_FB21

#define CAN_F5R2_FB21 CAN_F5R2_FB21_Msk

Filter bit 21

◆ CAN_F5R2_FB21_Msk

#define CAN_F5R2_FB21_Msk (0x1UL << CAN_F5R2_FB21_Pos)

0x00200000

◆ CAN_F5R2_FB21_Pos

#define CAN_F5R2_FB21_Pos (21U)

◆ CAN_F5R2_FB22

#define CAN_F5R2_FB22 CAN_F5R2_FB22_Msk

Filter bit 22

◆ CAN_F5R2_FB22_Msk

#define CAN_F5R2_FB22_Msk (0x1UL << CAN_F5R2_FB22_Pos)

0x00400000

◆ CAN_F5R2_FB22_Pos

#define CAN_F5R2_FB22_Pos (22U)

◆ CAN_F5R2_FB23

#define CAN_F5R2_FB23 CAN_F5R2_FB23_Msk

Filter bit 23

◆ CAN_F5R2_FB23_Msk

#define CAN_F5R2_FB23_Msk (0x1UL << CAN_F5R2_FB23_Pos)

0x00800000

◆ CAN_F5R2_FB23_Pos

#define CAN_F5R2_FB23_Pos (23U)

◆ CAN_F5R2_FB24

#define CAN_F5R2_FB24 CAN_F5R2_FB24_Msk

Filter bit 24

◆ CAN_F5R2_FB24_Msk

#define CAN_F5R2_FB24_Msk (0x1UL << CAN_F5R2_FB24_Pos)

0x01000000

◆ CAN_F5R2_FB24_Pos

#define CAN_F5R2_FB24_Pos (24U)

◆ CAN_F5R2_FB25

#define CAN_F5R2_FB25 CAN_F5R2_FB25_Msk

Filter bit 25

◆ CAN_F5R2_FB25_Msk

#define CAN_F5R2_FB25_Msk (0x1UL << CAN_F5R2_FB25_Pos)

0x02000000

◆ CAN_F5R2_FB25_Pos

#define CAN_F5R2_FB25_Pos (25U)

◆ CAN_F5R2_FB26

#define CAN_F5R2_FB26 CAN_F5R2_FB26_Msk

Filter bit 26

◆ CAN_F5R2_FB26_Msk

#define CAN_F5R2_FB26_Msk (0x1UL << CAN_F5R2_FB26_Pos)

0x04000000

◆ CAN_F5R2_FB26_Pos

#define CAN_F5R2_FB26_Pos (26U)

◆ CAN_F5R2_FB27

#define CAN_F5R2_FB27 CAN_F5R2_FB27_Msk

Filter bit 27

◆ CAN_F5R2_FB27_Msk

#define CAN_F5R2_FB27_Msk (0x1UL << CAN_F5R2_FB27_Pos)

0x08000000

◆ CAN_F5R2_FB27_Pos

#define CAN_F5R2_FB27_Pos (27U)

◆ CAN_F5R2_FB28

#define CAN_F5R2_FB28 CAN_F5R2_FB28_Msk

Filter bit 28

◆ CAN_F5R2_FB28_Msk

#define CAN_F5R2_FB28_Msk (0x1UL << CAN_F5R2_FB28_Pos)

0x10000000

◆ CAN_F5R2_FB28_Pos

#define CAN_F5R2_FB28_Pos (28U)

◆ CAN_F5R2_FB29

#define CAN_F5R2_FB29 CAN_F5R2_FB29_Msk

Filter bit 29

◆ CAN_F5R2_FB29_Msk

#define CAN_F5R2_FB29_Msk (0x1UL << CAN_F5R2_FB29_Pos)

0x20000000

◆ CAN_F5R2_FB29_Pos

#define CAN_F5R2_FB29_Pos (29U)

◆ CAN_F5R2_FB2_Msk

#define CAN_F5R2_FB2_Msk (0x1UL << CAN_F5R2_FB2_Pos)

0x00000004

◆ CAN_F5R2_FB2_Pos

#define CAN_F5R2_FB2_Pos (2U)

◆ CAN_F5R2_FB3

#define CAN_F5R2_FB3 CAN_F5R2_FB3_Msk

Filter bit 3

◆ CAN_F5R2_FB30

#define CAN_F5R2_FB30 CAN_F5R2_FB30_Msk

Filter bit 30

◆ CAN_F5R2_FB30_Msk

#define CAN_F5R2_FB30_Msk (0x1UL << CAN_F5R2_FB30_Pos)

0x40000000

◆ CAN_F5R2_FB30_Pos

#define CAN_F5R2_FB30_Pos (30U)

◆ CAN_F5R2_FB31

#define CAN_F5R2_FB31 CAN_F5R2_FB31_Msk

Filter bit 31

◆ CAN_F5R2_FB31_Msk

#define CAN_F5R2_FB31_Msk (0x1UL << CAN_F5R2_FB31_Pos)

0x80000000

◆ CAN_F5R2_FB31_Pos

#define CAN_F5R2_FB31_Pos (31U)

◆ CAN_F5R2_FB3_Msk

#define CAN_F5R2_FB3_Msk (0x1UL << CAN_F5R2_FB3_Pos)

0x00000008

◆ CAN_F5R2_FB3_Pos

#define CAN_F5R2_FB3_Pos (3U)

◆ CAN_F5R2_FB4

#define CAN_F5R2_FB4 CAN_F5R2_FB4_Msk

Filter bit 4

◆ CAN_F5R2_FB4_Msk

#define CAN_F5R2_FB4_Msk (0x1UL << CAN_F5R2_FB4_Pos)

0x00000010

◆ CAN_F5R2_FB4_Pos

#define CAN_F5R2_FB4_Pos (4U)

◆ CAN_F5R2_FB5

#define CAN_F5R2_FB5 CAN_F5R2_FB5_Msk

Filter bit 5

◆ CAN_F5R2_FB5_Msk

#define CAN_F5R2_FB5_Msk (0x1UL << CAN_F5R2_FB5_Pos)

0x00000020

◆ CAN_F5R2_FB5_Pos

#define CAN_F5R2_FB5_Pos (5U)

◆ CAN_F5R2_FB6

#define CAN_F5R2_FB6 CAN_F5R2_FB6_Msk

Filter bit 6

◆ CAN_F5R2_FB6_Msk

#define CAN_F5R2_FB6_Msk (0x1UL << CAN_F5R2_FB6_Pos)

0x00000040

◆ CAN_F5R2_FB6_Pos

#define CAN_F5R2_FB6_Pos (6U)

◆ CAN_F5R2_FB7

#define CAN_F5R2_FB7 CAN_F5R2_FB7_Msk

Filter bit 7

◆ CAN_F5R2_FB7_Msk

#define CAN_F5R2_FB7_Msk (0x1UL << CAN_F5R2_FB7_Pos)

0x00000080

◆ CAN_F5R2_FB7_Pos

#define CAN_F5R2_FB7_Pos (7U)

◆ CAN_F5R2_FB8

#define CAN_F5R2_FB8 CAN_F5R2_FB8_Msk

Filter bit 8

◆ CAN_F5R2_FB8_Msk

#define CAN_F5R2_FB8_Msk (0x1UL << CAN_F5R2_FB8_Pos)

0x00000100

◆ CAN_F5R2_FB8_Pos

#define CAN_F5R2_FB8_Pos (8U)

◆ CAN_F5R2_FB9

#define CAN_F5R2_FB9 CAN_F5R2_FB9_Msk

Filter bit 9

◆ CAN_F5R2_FB9_Msk

#define CAN_F5R2_FB9_Msk (0x1UL << CAN_F5R2_FB9_Pos)

0x00000200

◆ CAN_F5R2_FB9_Pos

#define CAN_F5R2_FB9_Pos (9U)

◆ CAN_F6R1_FB0

#define CAN_F6R1_FB0 CAN_F6R1_FB0_Msk

Filter bit 0

◆ CAN_F6R1_FB0_Msk

#define CAN_F6R1_FB0_Msk (0x1UL << CAN_F6R1_FB0_Pos)

0x00000001

◆ CAN_F6R1_FB0_Pos

#define CAN_F6R1_FB0_Pos (0U)

◆ CAN_F6R1_FB1

#define CAN_F6R1_FB1 CAN_F6R1_FB1_Msk

Filter bit 1

◆ CAN_F6R1_FB10

#define CAN_F6R1_FB10 CAN_F6R1_FB10_Msk

Filter bit 10

◆ CAN_F6R1_FB10_Msk

#define CAN_F6R1_FB10_Msk (0x1UL << CAN_F6R1_FB10_Pos)

0x00000400

◆ CAN_F6R1_FB10_Pos

#define CAN_F6R1_FB10_Pos (10U)

◆ CAN_F6R1_FB11

#define CAN_F6R1_FB11 CAN_F6R1_FB11_Msk

Filter bit 11

◆ CAN_F6R1_FB11_Msk

#define CAN_F6R1_FB11_Msk (0x1UL << CAN_F6R1_FB11_Pos)

0x00000800

◆ CAN_F6R1_FB11_Pos

#define CAN_F6R1_FB11_Pos (11U)

◆ CAN_F6R1_FB12

#define CAN_F6R1_FB12 CAN_F6R1_FB12_Msk

Filter bit 12

◆ CAN_F6R1_FB12_Msk

#define CAN_F6R1_FB12_Msk (0x1UL << CAN_F6R1_FB12_Pos)

0x00001000

◆ CAN_F6R1_FB12_Pos

#define CAN_F6R1_FB12_Pos (12U)

◆ CAN_F6R1_FB13

#define CAN_F6R1_FB13 CAN_F6R1_FB13_Msk

Filter bit 13

◆ CAN_F6R1_FB13_Msk

#define CAN_F6R1_FB13_Msk (0x1UL << CAN_F6R1_FB13_Pos)

0x00002000

◆ CAN_F6R1_FB13_Pos

#define CAN_F6R1_FB13_Pos (13U)

◆ CAN_F6R1_FB14

#define CAN_F6R1_FB14 CAN_F6R1_FB14_Msk

Filter bit 14

◆ CAN_F6R1_FB14_Msk

#define CAN_F6R1_FB14_Msk (0x1UL << CAN_F6R1_FB14_Pos)

0x00004000

◆ CAN_F6R1_FB14_Pos

#define CAN_F6R1_FB14_Pos (14U)

◆ CAN_F6R1_FB15

#define CAN_F6R1_FB15 CAN_F6R1_FB15_Msk

Filter bit 15

◆ CAN_F6R1_FB15_Msk

#define CAN_F6R1_FB15_Msk (0x1UL << CAN_F6R1_FB15_Pos)

0x00008000

◆ CAN_F6R1_FB15_Pos

#define CAN_F6R1_FB15_Pos (15U)

◆ CAN_F6R1_FB16

#define CAN_F6R1_FB16 CAN_F6R1_FB16_Msk

Filter bit 16

◆ CAN_F6R1_FB16_Msk

#define CAN_F6R1_FB16_Msk (0x1UL << CAN_F6R1_FB16_Pos)

0x00010000

◆ CAN_F6R1_FB16_Pos

#define CAN_F6R1_FB16_Pos (16U)

◆ CAN_F6R1_FB17

#define CAN_F6R1_FB17 CAN_F6R1_FB17_Msk

Filter bit 17

◆ CAN_F6R1_FB17_Msk

#define CAN_F6R1_FB17_Msk (0x1UL << CAN_F6R1_FB17_Pos)

0x00020000

◆ CAN_F6R1_FB17_Pos

#define CAN_F6R1_FB17_Pos (17U)

◆ CAN_F6R1_FB18

#define CAN_F6R1_FB18 CAN_F6R1_FB18_Msk

Filter bit 18

◆ CAN_F6R1_FB18_Msk

#define CAN_F6R1_FB18_Msk (0x1UL << CAN_F6R1_FB18_Pos)

0x00040000

◆ CAN_F6R1_FB18_Pos

#define CAN_F6R1_FB18_Pos (18U)

◆ CAN_F6R1_FB19

#define CAN_F6R1_FB19 CAN_F6R1_FB19_Msk

Filter bit 19

◆ CAN_F6R1_FB19_Msk

#define CAN_F6R1_FB19_Msk (0x1UL << CAN_F6R1_FB19_Pos)

0x00080000

◆ CAN_F6R1_FB19_Pos

#define CAN_F6R1_FB19_Pos (19U)

◆ CAN_F6R1_FB1_Msk

#define CAN_F6R1_FB1_Msk (0x1UL << CAN_F6R1_FB1_Pos)

0x00000002

◆ CAN_F6R1_FB1_Pos

#define CAN_F6R1_FB1_Pos (1U)

◆ CAN_F6R1_FB2

#define CAN_F6R1_FB2 CAN_F6R1_FB2_Msk

Filter bit 2

◆ CAN_F6R1_FB20

#define CAN_F6R1_FB20 CAN_F6R1_FB20_Msk

Filter bit 20

◆ CAN_F6R1_FB20_Msk

#define CAN_F6R1_FB20_Msk (0x1UL << CAN_F6R1_FB20_Pos)

0x00100000

◆ CAN_F6R1_FB20_Pos

#define CAN_F6R1_FB20_Pos (20U)

◆ CAN_F6R1_FB21

#define CAN_F6R1_FB21 CAN_F6R1_FB21_Msk

Filter bit 21

◆ CAN_F6R1_FB21_Msk

#define CAN_F6R1_FB21_Msk (0x1UL << CAN_F6R1_FB21_Pos)

0x00200000

◆ CAN_F6R1_FB21_Pos

#define CAN_F6R1_FB21_Pos (21U)

◆ CAN_F6R1_FB22

#define CAN_F6R1_FB22 CAN_F6R1_FB22_Msk

Filter bit 22

◆ CAN_F6R1_FB22_Msk

#define CAN_F6R1_FB22_Msk (0x1UL << CAN_F6R1_FB22_Pos)

0x00400000

◆ CAN_F6R1_FB22_Pos

#define CAN_F6R1_FB22_Pos (22U)

◆ CAN_F6R1_FB23

#define CAN_F6R1_FB23 CAN_F6R1_FB23_Msk

Filter bit 23

◆ CAN_F6R1_FB23_Msk

#define CAN_F6R1_FB23_Msk (0x1UL << CAN_F6R1_FB23_Pos)

0x00800000

◆ CAN_F6R1_FB23_Pos

#define CAN_F6R1_FB23_Pos (23U)

◆ CAN_F6R1_FB24

#define CAN_F6R1_FB24 CAN_F6R1_FB24_Msk

Filter bit 24

◆ CAN_F6R1_FB24_Msk

#define CAN_F6R1_FB24_Msk (0x1UL << CAN_F6R1_FB24_Pos)

0x01000000

◆ CAN_F6R1_FB24_Pos

#define CAN_F6R1_FB24_Pos (24U)

◆ CAN_F6R1_FB25

#define CAN_F6R1_FB25 CAN_F6R1_FB25_Msk

Filter bit 25

◆ CAN_F6R1_FB25_Msk

#define CAN_F6R1_FB25_Msk (0x1UL << CAN_F6R1_FB25_Pos)

0x02000000

◆ CAN_F6R1_FB25_Pos

#define CAN_F6R1_FB25_Pos (25U)

◆ CAN_F6R1_FB26

#define CAN_F6R1_FB26 CAN_F6R1_FB26_Msk

Filter bit 26

◆ CAN_F6R1_FB26_Msk

#define CAN_F6R1_FB26_Msk (0x1UL << CAN_F6R1_FB26_Pos)

0x04000000

◆ CAN_F6R1_FB26_Pos

#define CAN_F6R1_FB26_Pos (26U)

◆ CAN_F6R1_FB27

#define CAN_F6R1_FB27 CAN_F6R1_FB27_Msk

Filter bit 27

◆ CAN_F6R1_FB27_Msk

#define CAN_F6R1_FB27_Msk (0x1UL << CAN_F6R1_FB27_Pos)

0x08000000

◆ CAN_F6R1_FB27_Pos

#define CAN_F6R1_FB27_Pos (27U)

◆ CAN_F6R1_FB28

#define CAN_F6R1_FB28 CAN_F6R1_FB28_Msk

Filter bit 28

◆ CAN_F6R1_FB28_Msk

#define CAN_F6R1_FB28_Msk (0x1UL << CAN_F6R1_FB28_Pos)

0x10000000

◆ CAN_F6R1_FB28_Pos

#define CAN_F6R1_FB28_Pos (28U)

◆ CAN_F6R1_FB29

#define CAN_F6R1_FB29 CAN_F6R1_FB29_Msk

Filter bit 29

◆ CAN_F6R1_FB29_Msk

#define CAN_F6R1_FB29_Msk (0x1UL << CAN_F6R1_FB29_Pos)

0x20000000

◆ CAN_F6R1_FB29_Pos

#define CAN_F6R1_FB29_Pos (29U)

◆ CAN_F6R1_FB2_Msk

#define CAN_F6R1_FB2_Msk (0x1UL << CAN_F6R1_FB2_Pos)

0x00000004

◆ CAN_F6R1_FB2_Pos

#define CAN_F6R1_FB2_Pos (2U)

◆ CAN_F6R1_FB3

#define CAN_F6R1_FB3 CAN_F6R1_FB3_Msk

Filter bit 3

◆ CAN_F6R1_FB30

#define CAN_F6R1_FB30 CAN_F6R1_FB30_Msk

Filter bit 30

◆ CAN_F6R1_FB30_Msk

#define CAN_F6R1_FB30_Msk (0x1UL << CAN_F6R1_FB30_Pos)

0x40000000

◆ CAN_F6R1_FB30_Pos

#define CAN_F6R1_FB30_Pos (30U)

◆ CAN_F6R1_FB31

#define CAN_F6R1_FB31 CAN_F6R1_FB31_Msk

Filter bit 31

◆ CAN_F6R1_FB31_Msk

#define CAN_F6R1_FB31_Msk (0x1UL << CAN_F6R1_FB31_Pos)

0x80000000

◆ CAN_F6R1_FB31_Pos

#define CAN_F6R1_FB31_Pos (31U)

◆ CAN_F6R1_FB3_Msk

#define CAN_F6R1_FB3_Msk (0x1UL << CAN_F6R1_FB3_Pos)

0x00000008

◆ CAN_F6R1_FB3_Pos

#define CAN_F6R1_FB3_Pos (3U)

◆ CAN_F6R1_FB4

#define CAN_F6R1_FB4 CAN_F6R1_FB4_Msk

Filter bit 4

◆ CAN_F6R1_FB4_Msk

#define CAN_F6R1_FB4_Msk (0x1UL << CAN_F6R1_FB4_Pos)

0x00000010

◆ CAN_F6R1_FB4_Pos

#define CAN_F6R1_FB4_Pos (4U)

◆ CAN_F6R1_FB5

#define CAN_F6R1_FB5 CAN_F6R1_FB5_Msk

Filter bit 5

◆ CAN_F6R1_FB5_Msk

#define CAN_F6R1_FB5_Msk (0x1UL << CAN_F6R1_FB5_Pos)

0x00000020

◆ CAN_F6R1_FB5_Pos

#define CAN_F6R1_FB5_Pos (5U)

◆ CAN_F6R1_FB6

#define CAN_F6R1_FB6 CAN_F6R1_FB6_Msk

Filter bit 6

◆ CAN_F6R1_FB6_Msk

#define CAN_F6R1_FB6_Msk (0x1UL << CAN_F6R1_FB6_Pos)

0x00000040

◆ CAN_F6R1_FB6_Pos

#define CAN_F6R1_FB6_Pos (6U)

◆ CAN_F6R1_FB7

#define CAN_F6R1_FB7 CAN_F6R1_FB7_Msk

Filter bit 7

◆ CAN_F6R1_FB7_Msk

#define CAN_F6R1_FB7_Msk (0x1UL << CAN_F6R1_FB7_Pos)

0x00000080

◆ CAN_F6R1_FB7_Pos

#define CAN_F6R1_FB7_Pos (7U)

◆ CAN_F6R1_FB8

#define CAN_F6R1_FB8 CAN_F6R1_FB8_Msk

Filter bit 8

◆ CAN_F6R1_FB8_Msk

#define CAN_F6R1_FB8_Msk (0x1UL << CAN_F6R1_FB8_Pos)

0x00000100

◆ CAN_F6R1_FB8_Pos

#define CAN_F6R1_FB8_Pos (8U)

◆ CAN_F6R1_FB9

#define CAN_F6R1_FB9 CAN_F6R1_FB9_Msk

Filter bit 9

◆ CAN_F6R1_FB9_Msk

#define CAN_F6R1_FB9_Msk (0x1UL << CAN_F6R1_FB9_Pos)

0x00000200

◆ CAN_F6R1_FB9_Pos

#define CAN_F6R1_FB9_Pos (9U)

◆ CAN_F6R2_FB0

#define CAN_F6R2_FB0 CAN_F6R2_FB0_Msk

Filter bit 0

◆ CAN_F6R2_FB0_Msk

#define CAN_F6R2_FB0_Msk (0x1UL << CAN_F6R2_FB0_Pos)

0x00000001

◆ CAN_F6R2_FB0_Pos

#define CAN_F6R2_FB0_Pos (0U)

◆ CAN_F6R2_FB1

#define CAN_F6R2_FB1 CAN_F6R2_FB1_Msk

Filter bit 1

◆ CAN_F6R2_FB10

#define CAN_F6R2_FB10 CAN_F6R2_FB10_Msk

Filter bit 10

◆ CAN_F6R2_FB10_Msk

#define CAN_F6R2_FB10_Msk (0x1UL << CAN_F6R2_FB10_Pos)

0x00000400

◆ CAN_F6R2_FB10_Pos

#define CAN_F6R2_FB10_Pos (10U)

◆ CAN_F6R2_FB11

#define CAN_F6R2_FB11 CAN_F6R2_FB11_Msk

Filter bit 11

◆ CAN_F6R2_FB11_Msk

#define CAN_F6R2_FB11_Msk (0x1UL << CAN_F6R2_FB11_Pos)

0x00000800

◆ CAN_F6R2_FB11_Pos

#define CAN_F6R2_FB11_Pos (11U)

◆ CAN_F6R2_FB12

#define CAN_F6R2_FB12 CAN_F6R2_FB12_Msk

Filter bit 12

◆ CAN_F6R2_FB12_Msk

#define CAN_F6R2_FB12_Msk (0x1UL << CAN_F6R2_FB12_Pos)

0x00001000

◆ CAN_F6R2_FB12_Pos

#define CAN_F6R2_FB12_Pos (12U)

◆ CAN_F6R2_FB13

#define CAN_F6R2_FB13 CAN_F6R2_FB13_Msk

Filter bit 13

◆ CAN_F6R2_FB13_Msk

#define CAN_F6R2_FB13_Msk (0x1UL << CAN_F6R2_FB13_Pos)

0x00002000

◆ CAN_F6R2_FB13_Pos

#define CAN_F6R2_FB13_Pos (13U)

◆ CAN_F6R2_FB14

#define CAN_F6R2_FB14 CAN_F6R2_FB14_Msk

Filter bit 14

◆ CAN_F6R2_FB14_Msk

#define CAN_F6R2_FB14_Msk (0x1UL << CAN_F6R2_FB14_Pos)

0x00004000

◆ CAN_F6R2_FB14_Pos

#define CAN_F6R2_FB14_Pos (14U)

◆ CAN_F6R2_FB15

#define CAN_F6R2_FB15 CAN_F6R2_FB15_Msk

Filter bit 15

◆ CAN_F6R2_FB15_Msk

#define CAN_F6R2_FB15_Msk (0x1UL << CAN_F6R2_FB15_Pos)

0x00008000

◆ CAN_F6R2_FB15_Pos

#define CAN_F6R2_FB15_Pos (15U)

◆ CAN_F6R2_FB16

#define CAN_F6R2_FB16 CAN_F6R2_FB16_Msk

Filter bit 16

◆ CAN_F6R2_FB16_Msk

#define CAN_F6R2_FB16_Msk (0x1UL << CAN_F6R2_FB16_Pos)

0x00010000

◆ CAN_F6R2_FB16_Pos

#define CAN_F6R2_FB16_Pos (16U)

◆ CAN_F6R2_FB17

#define CAN_F6R2_FB17 CAN_F6R2_FB17_Msk

Filter bit 17

◆ CAN_F6R2_FB17_Msk

#define CAN_F6R2_FB17_Msk (0x1UL << CAN_F6R2_FB17_Pos)

0x00020000

◆ CAN_F6R2_FB17_Pos

#define CAN_F6R2_FB17_Pos (17U)

◆ CAN_F6R2_FB18

#define CAN_F6R2_FB18 CAN_F6R2_FB18_Msk

Filter bit 18

◆ CAN_F6R2_FB18_Msk

#define CAN_F6R2_FB18_Msk (0x1UL << CAN_F6R2_FB18_Pos)

0x00040000

◆ CAN_F6R2_FB18_Pos

#define CAN_F6R2_FB18_Pos (18U)

◆ CAN_F6R2_FB19

#define CAN_F6R2_FB19 CAN_F6R2_FB19_Msk

Filter bit 19

◆ CAN_F6R2_FB19_Msk

#define CAN_F6R2_FB19_Msk (0x1UL << CAN_F6R2_FB19_Pos)

0x00080000

◆ CAN_F6R2_FB19_Pos

#define CAN_F6R2_FB19_Pos (19U)

◆ CAN_F6R2_FB1_Msk

#define CAN_F6R2_FB1_Msk (0x1UL << CAN_F6R2_FB1_Pos)

0x00000002

◆ CAN_F6R2_FB1_Pos

#define CAN_F6R2_FB1_Pos (1U)

◆ CAN_F6R2_FB2

#define CAN_F6R2_FB2 CAN_F6R2_FB2_Msk

Filter bit 2

◆ CAN_F6R2_FB20

#define CAN_F6R2_FB20 CAN_F6R2_FB20_Msk

Filter bit 20

◆ CAN_F6R2_FB20_Msk

#define CAN_F6R2_FB20_Msk (0x1UL << CAN_F6R2_FB20_Pos)

0x00100000

◆ CAN_F6R2_FB20_Pos

#define CAN_F6R2_FB20_Pos (20U)

◆ CAN_F6R2_FB21

#define CAN_F6R2_FB21 CAN_F6R2_FB21_Msk

Filter bit 21

◆ CAN_F6R2_FB21_Msk

#define CAN_F6R2_FB21_Msk (0x1UL << CAN_F6R2_FB21_Pos)

0x00200000

◆ CAN_F6R2_FB21_Pos

#define CAN_F6R2_FB21_Pos (21U)

◆ CAN_F6R2_FB22

#define CAN_F6R2_FB22 CAN_F6R2_FB22_Msk

Filter bit 22

◆ CAN_F6R2_FB22_Msk

#define CAN_F6R2_FB22_Msk (0x1UL << CAN_F6R2_FB22_Pos)

0x00400000

◆ CAN_F6R2_FB22_Pos

#define CAN_F6R2_FB22_Pos (22U)

◆ CAN_F6R2_FB23

#define CAN_F6R2_FB23 CAN_F6R2_FB23_Msk

Filter bit 23

◆ CAN_F6R2_FB23_Msk

#define CAN_F6R2_FB23_Msk (0x1UL << CAN_F6R2_FB23_Pos)

0x00800000

◆ CAN_F6R2_FB23_Pos

#define CAN_F6R2_FB23_Pos (23U)

◆ CAN_F6R2_FB24

#define CAN_F6R2_FB24 CAN_F6R2_FB24_Msk

Filter bit 24

◆ CAN_F6R2_FB24_Msk

#define CAN_F6R2_FB24_Msk (0x1UL << CAN_F6R2_FB24_Pos)

0x01000000

◆ CAN_F6R2_FB24_Pos

#define CAN_F6R2_FB24_Pos (24U)

◆ CAN_F6R2_FB25

#define CAN_F6R2_FB25 CAN_F6R2_FB25_Msk

Filter bit 25

◆ CAN_F6R2_FB25_Msk

#define CAN_F6R2_FB25_Msk (0x1UL << CAN_F6R2_FB25_Pos)

0x02000000

◆ CAN_F6R2_FB25_Pos

#define CAN_F6R2_FB25_Pos (25U)

◆ CAN_F6R2_FB26

#define CAN_F6R2_FB26 CAN_F6R2_FB26_Msk

Filter bit 26

◆ CAN_F6R2_FB26_Msk

#define CAN_F6R2_FB26_Msk (0x1UL << CAN_F6R2_FB26_Pos)

0x04000000

◆ CAN_F6R2_FB26_Pos

#define CAN_F6R2_FB26_Pos (26U)

◆ CAN_F6R2_FB27

#define CAN_F6R2_FB27 CAN_F6R2_FB27_Msk

Filter bit 27

◆ CAN_F6R2_FB27_Msk

#define CAN_F6R2_FB27_Msk (0x1UL << CAN_F6R2_FB27_Pos)

0x08000000

◆ CAN_F6R2_FB27_Pos

#define CAN_F6R2_FB27_Pos (27U)

◆ CAN_F6R2_FB28

#define CAN_F6R2_FB28 CAN_F6R2_FB28_Msk

Filter bit 28

◆ CAN_F6R2_FB28_Msk

#define CAN_F6R2_FB28_Msk (0x1UL << CAN_F6R2_FB28_Pos)

0x10000000

◆ CAN_F6R2_FB28_Pos

#define CAN_F6R2_FB28_Pos (28U)

◆ CAN_F6R2_FB29

#define CAN_F6R2_FB29 CAN_F6R2_FB29_Msk

Filter bit 29

◆ CAN_F6R2_FB29_Msk

#define CAN_F6R2_FB29_Msk (0x1UL << CAN_F6R2_FB29_Pos)

0x20000000

◆ CAN_F6R2_FB29_Pos

#define CAN_F6R2_FB29_Pos (29U)

◆ CAN_F6R2_FB2_Msk

#define CAN_F6R2_FB2_Msk (0x1UL << CAN_F6R2_FB2_Pos)

0x00000004

◆ CAN_F6R2_FB2_Pos

#define CAN_F6R2_FB2_Pos (2U)

◆ CAN_F6R2_FB3

#define CAN_F6R2_FB3 CAN_F6R2_FB3_Msk

Filter bit 3

◆ CAN_F6R2_FB30

#define CAN_F6R2_FB30 CAN_F6R2_FB30_Msk

Filter bit 30

◆ CAN_F6R2_FB30_Msk

#define CAN_F6R2_FB30_Msk (0x1UL << CAN_F6R2_FB30_Pos)

0x40000000

◆ CAN_F6R2_FB30_Pos

#define CAN_F6R2_FB30_Pos (30U)

◆ CAN_F6R2_FB31

#define CAN_F6R2_FB31 CAN_F6R2_FB31_Msk

Filter bit 31

◆ CAN_F6R2_FB31_Msk

#define CAN_F6R2_FB31_Msk (0x1UL << CAN_F6R2_FB31_Pos)

0x80000000

◆ CAN_F6R2_FB31_Pos

#define CAN_F6R2_FB31_Pos (31U)

◆ CAN_F6R2_FB3_Msk

#define CAN_F6R2_FB3_Msk (0x1UL << CAN_F6R2_FB3_Pos)

0x00000008

◆ CAN_F6R2_FB3_Pos

#define CAN_F6R2_FB3_Pos (3U)

◆ CAN_F6R2_FB4

#define CAN_F6R2_FB4 CAN_F6R2_FB4_Msk

Filter bit 4

◆ CAN_F6R2_FB4_Msk

#define CAN_F6R2_FB4_Msk (0x1UL << CAN_F6R2_FB4_Pos)

0x00000010

◆ CAN_F6R2_FB4_Pos

#define CAN_F6R2_FB4_Pos (4U)

◆ CAN_F6R2_FB5

#define CAN_F6R2_FB5 CAN_F6R2_FB5_Msk

Filter bit 5

◆ CAN_F6R2_FB5_Msk

#define CAN_F6R2_FB5_Msk (0x1UL << CAN_F6R2_FB5_Pos)

0x00000020

◆ CAN_F6R2_FB5_Pos

#define CAN_F6R2_FB5_Pos (5U)

◆ CAN_F6R2_FB6

#define CAN_F6R2_FB6 CAN_F6R2_FB6_Msk

Filter bit 6

◆ CAN_F6R2_FB6_Msk

#define CAN_F6R2_FB6_Msk (0x1UL << CAN_F6R2_FB6_Pos)

0x00000040

◆ CAN_F6R2_FB6_Pos

#define CAN_F6R2_FB6_Pos (6U)

◆ CAN_F6R2_FB7

#define CAN_F6R2_FB7 CAN_F6R2_FB7_Msk

Filter bit 7

◆ CAN_F6R2_FB7_Msk

#define CAN_F6R2_FB7_Msk (0x1UL << CAN_F6R2_FB7_Pos)

0x00000080

◆ CAN_F6R2_FB7_Pos

#define CAN_F6R2_FB7_Pos (7U)

◆ CAN_F6R2_FB8

#define CAN_F6R2_FB8 CAN_F6R2_FB8_Msk

Filter bit 8

◆ CAN_F6R2_FB8_Msk

#define CAN_F6R2_FB8_Msk (0x1UL << CAN_F6R2_FB8_Pos)

0x00000100

◆ CAN_F6R2_FB8_Pos

#define CAN_F6R2_FB8_Pos (8U)

◆ CAN_F6R2_FB9

#define CAN_F6R2_FB9 CAN_F6R2_FB9_Msk

Filter bit 9

◆ CAN_F6R2_FB9_Msk

#define CAN_F6R2_FB9_Msk (0x1UL << CAN_F6R2_FB9_Pos)

0x00000200

◆ CAN_F6R2_FB9_Pos

#define CAN_F6R2_FB9_Pos (9U)

◆ CAN_F7R1_FB0

#define CAN_F7R1_FB0 CAN_F7R1_FB0_Msk

Filter bit 0

◆ CAN_F7R1_FB0_Msk

#define CAN_F7R1_FB0_Msk (0x1UL << CAN_F7R1_FB0_Pos)

0x00000001

◆ CAN_F7R1_FB0_Pos

#define CAN_F7R1_FB0_Pos (0U)

◆ CAN_F7R1_FB1

#define CAN_F7R1_FB1 CAN_F7R1_FB1_Msk

Filter bit 1

◆ CAN_F7R1_FB10

#define CAN_F7R1_FB10 CAN_F7R1_FB10_Msk

Filter bit 10

◆ CAN_F7R1_FB10_Msk

#define CAN_F7R1_FB10_Msk (0x1UL << CAN_F7R1_FB10_Pos)

0x00000400

◆ CAN_F7R1_FB10_Pos

#define CAN_F7R1_FB10_Pos (10U)

◆ CAN_F7R1_FB11

#define CAN_F7R1_FB11 CAN_F7R1_FB11_Msk

Filter bit 11

◆ CAN_F7R1_FB11_Msk

#define CAN_F7R1_FB11_Msk (0x1UL << CAN_F7R1_FB11_Pos)

0x00000800

◆ CAN_F7R1_FB11_Pos

#define CAN_F7R1_FB11_Pos (11U)

◆ CAN_F7R1_FB12

#define CAN_F7R1_FB12 CAN_F7R1_FB12_Msk

Filter bit 12

◆ CAN_F7R1_FB12_Msk

#define CAN_F7R1_FB12_Msk (0x1UL << CAN_F7R1_FB12_Pos)

0x00001000

◆ CAN_F7R1_FB12_Pos

#define CAN_F7R1_FB12_Pos (12U)

◆ CAN_F7R1_FB13

#define CAN_F7R1_FB13 CAN_F7R1_FB13_Msk

Filter bit 13

◆ CAN_F7R1_FB13_Msk

#define CAN_F7R1_FB13_Msk (0x1UL << CAN_F7R1_FB13_Pos)

0x00002000

◆ CAN_F7R1_FB13_Pos

#define CAN_F7R1_FB13_Pos (13U)

◆ CAN_F7R1_FB14

#define CAN_F7R1_FB14 CAN_F7R1_FB14_Msk

Filter bit 14

◆ CAN_F7R1_FB14_Msk

#define CAN_F7R1_FB14_Msk (0x1UL << CAN_F7R1_FB14_Pos)

0x00004000

◆ CAN_F7R1_FB14_Pos

#define CAN_F7R1_FB14_Pos (14U)

◆ CAN_F7R1_FB15

#define CAN_F7R1_FB15 CAN_F7R1_FB15_Msk

Filter bit 15

◆ CAN_F7R1_FB15_Msk

#define CAN_F7R1_FB15_Msk (0x1UL << CAN_F7R1_FB15_Pos)

0x00008000

◆ CAN_F7R1_FB15_Pos

#define CAN_F7R1_FB15_Pos (15U)

◆ CAN_F7R1_FB16

#define CAN_F7R1_FB16 CAN_F7R1_FB16_Msk

Filter bit 16

◆ CAN_F7R1_FB16_Msk

#define CAN_F7R1_FB16_Msk (0x1UL << CAN_F7R1_FB16_Pos)

0x00010000

◆ CAN_F7R1_FB16_Pos

#define CAN_F7R1_FB16_Pos (16U)

◆ CAN_F7R1_FB17

#define CAN_F7R1_FB17 CAN_F7R1_FB17_Msk

Filter bit 17

◆ CAN_F7R1_FB17_Msk

#define CAN_F7R1_FB17_Msk (0x1UL << CAN_F7R1_FB17_Pos)

0x00020000

◆ CAN_F7R1_FB17_Pos

#define CAN_F7R1_FB17_Pos (17U)

◆ CAN_F7R1_FB18

#define CAN_F7R1_FB18 CAN_F7R1_FB18_Msk

Filter bit 18

◆ CAN_F7R1_FB18_Msk

#define CAN_F7R1_FB18_Msk (0x1UL << CAN_F7R1_FB18_Pos)

0x00040000

◆ CAN_F7R1_FB18_Pos

#define CAN_F7R1_FB18_Pos (18U)

◆ CAN_F7R1_FB19

#define CAN_F7R1_FB19 CAN_F7R1_FB19_Msk

Filter bit 19

◆ CAN_F7R1_FB19_Msk

#define CAN_F7R1_FB19_Msk (0x1UL << CAN_F7R1_FB19_Pos)

0x00080000

◆ CAN_F7R1_FB19_Pos

#define CAN_F7R1_FB19_Pos (19U)

◆ CAN_F7R1_FB1_Msk

#define CAN_F7R1_FB1_Msk (0x1UL << CAN_F7R1_FB1_Pos)

0x00000002

◆ CAN_F7R1_FB1_Pos

#define CAN_F7R1_FB1_Pos (1U)

◆ CAN_F7R1_FB2

#define CAN_F7R1_FB2 CAN_F7R1_FB2_Msk

Filter bit 2

◆ CAN_F7R1_FB20

#define CAN_F7R1_FB20 CAN_F7R1_FB20_Msk

Filter bit 20

◆ CAN_F7R1_FB20_Msk

#define CAN_F7R1_FB20_Msk (0x1UL << CAN_F7R1_FB20_Pos)

0x00100000

◆ CAN_F7R1_FB20_Pos

#define CAN_F7R1_FB20_Pos (20U)

◆ CAN_F7R1_FB21

#define CAN_F7R1_FB21 CAN_F7R1_FB21_Msk

Filter bit 21

◆ CAN_F7R1_FB21_Msk

#define CAN_F7R1_FB21_Msk (0x1UL << CAN_F7R1_FB21_Pos)

0x00200000

◆ CAN_F7R1_FB21_Pos

#define CAN_F7R1_FB21_Pos (21U)

◆ CAN_F7R1_FB22

#define CAN_F7R1_FB22 CAN_F7R1_FB22_Msk

Filter bit 22

◆ CAN_F7R1_FB22_Msk

#define CAN_F7R1_FB22_Msk (0x1UL << CAN_F7R1_FB22_Pos)

0x00400000

◆ CAN_F7R1_FB22_Pos

#define CAN_F7R1_FB22_Pos (22U)

◆ CAN_F7R1_FB23

#define CAN_F7R1_FB23 CAN_F7R1_FB23_Msk

Filter bit 23

◆ CAN_F7R1_FB23_Msk

#define CAN_F7R1_FB23_Msk (0x1UL << CAN_F7R1_FB23_Pos)

0x00800000

◆ CAN_F7R1_FB23_Pos

#define CAN_F7R1_FB23_Pos (23U)

◆ CAN_F7R1_FB24

#define CAN_F7R1_FB24 CAN_F7R1_FB24_Msk

Filter bit 24

◆ CAN_F7R1_FB24_Msk

#define CAN_F7R1_FB24_Msk (0x1UL << CAN_F7R1_FB24_Pos)

0x01000000

◆ CAN_F7R1_FB24_Pos

#define CAN_F7R1_FB24_Pos (24U)

◆ CAN_F7R1_FB25

#define CAN_F7R1_FB25 CAN_F7R1_FB25_Msk

Filter bit 25

◆ CAN_F7R1_FB25_Msk

#define CAN_F7R1_FB25_Msk (0x1UL << CAN_F7R1_FB25_Pos)

0x02000000

◆ CAN_F7R1_FB25_Pos

#define CAN_F7R1_FB25_Pos (25U)

◆ CAN_F7R1_FB26

#define CAN_F7R1_FB26 CAN_F7R1_FB26_Msk

Filter bit 26

◆ CAN_F7R1_FB26_Msk

#define CAN_F7R1_FB26_Msk (0x1UL << CAN_F7R1_FB26_Pos)

0x04000000

◆ CAN_F7R1_FB26_Pos

#define CAN_F7R1_FB26_Pos (26U)

◆ CAN_F7R1_FB27

#define CAN_F7R1_FB27 CAN_F7R1_FB27_Msk

Filter bit 27

◆ CAN_F7R1_FB27_Msk

#define CAN_F7R1_FB27_Msk (0x1UL << CAN_F7R1_FB27_Pos)

0x08000000

◆ CAN_F7R1_FB27_Pos

#define CAN_F7R1_FB27_Pos (27U)

◆ CAN_F7R1_FB28

#define CAN_F7R1_FB28 CAN_F7R1_FB28_Msk

Filter bit 28

◆ CAN_F7R1_FB28_Msk

#define CAN_F7R1_FB28_Msk (0x1UL << CAN_F7R1_FB28_Pos)

0x10000000

◆ CAN_F7R1_FB28_Pos

#define CAN_F7R1_FB28_Pos (28U)

◆ CAN_F7R1_FB29

#define CAN_F7R1_FB29 CAN_F7R1_FB29_Msk

Filter bit 29

◆ CAN_F7R1_FB29_Msk

#define CAN_F7R1_FB29_Msk (0x1UL << CAN_F7R1_FB29_Pos)

0x20000000

◆ CAN_F7R1_FB29_Pos

#define CAN_F7R1_FB29_Pos (29U)

◆ CAN_F7R1_FB2_Msk

#define CAN_F7R1_FB2_Msk (0x1UL << CAN_F7R1_FB2_Pos)

0x00000004

◆ CAN_F7R1_FB2_Pos

#define CAN_F7R1_FB2_Pos (2U)

◆ CAN_F7R1_FB3

#define CAN_F7R1_FB3 CAN_F7R1_FB3_Msk

Filter bit 3

◆ CAN_F7R1_FB30

#define CAN_F7R1_FB30 CAN_F7R1_FB30_Msk

Filter bit 30

◆ CAN_F7R1_FB30_Msk

#define CAN_F7R1_FB30_Msk (0x1UL << CAN_F7R1_FB30_Pos)

0x40000000

◆ CAN_F7R1_FB30_Pos

#define CAN_F7R1_FB30_Pos (30U)

◆ CAN_F7R1_FB31

#define CAN_F7R1_FB31 CAN_F7R1_FB31_Msk

Filter bit 31

◆ CAN_F7R1_FB31_Msk

#define CAN_F7R1_FB31_Msk (0x1UL << CAN_F7R1_FB31_Pos)

0x80000000

◆ CAN_F7R1_FB31_Pos

#define CAN_F7R1_FB31_Pos (31U)

◆ CAN_F7R1_FB3_Msk

#define CAN_F7R1_FB3_Msk (0x1UL << CAN_F7R1_FB3_Pos)

0x00000008

◆ CAN_F7R1_FB3_Pos

#define CAN_F7R1_FB3_Pos (3U)

◆ CAN_F7R1_FB4

#define CAN_F7R1_FB4 CAN_F7R1_FB4_Msk

Filter bit 4

◆ CAN_F7R1_FB4_Msk

#define CAN_F7R1_FB4_Msk (0x1UL << CAN_F7R1_FB4_Pos)

0x00000010

◆ CAN_F7R1_FB4_Pos

#define CAN_F7R1_FB4_Pos (4U)

◆ CAN_F7R1_FB5

#define CAN_F7R1_FB5 CAN_F7R1_FB5_Msk

Filter bit 5

◆ CAN_F7R1_FB5_Msk

#define CAN_F7R1_FB5_Msk (0x1UL << CAN_F7R1_FB5_Pos)

0x00000020

◆ CAN_F7R1_FB5_Pos

#define CAN_F7R1_FB5_Pos (5U)

◆ CAN_F7R1_FB6

#define CAN_F7R1_FB6 CAN_F7R1_FB6_Msk

Filter bit 6

◆ CAN_F7R1_FB6_Msk

#define CAN_F7R1_FB6_Msk (0x1UL << CAN_F7R1_FB6_Pos)

0x00000040

◆ CAN_F7R1_FB6_Pos

#define CAN_F7R1_FB6_Pos (6U)

◆ CAN_F7R1_FB7

#define CAN_F7R1_FB7 CAN_F7R1_FB7_Msk

Filter bit 7

◆ CAN_F7R1_FB7_Msk

#define CAN_F7R1_FB7_Msk (0x1UL << CAN_F7R1_FB7_Pos)

0x00000080

◆ CAN_F7R1_FB7_Pos

#define CAN_F7R1_FB7_Pos (7U)

◆ CAN_F7R1_FB8

#define CAN_F7R1_FB8 CAN_F7R1_FB8_Msk

Filter bit 8

◆ CAN_F7R1_FB8_Msk

#define CAN_F7R1_FB8_Msk (0x1UL << CAN_F7R1_FB8_Pos)

0x00000100

◆ CAN_F7R1_FB8_Pos

#define CAN_F7R1_FB8_Pos (8U)

◆ CAN_F7R1_FB9

#define CAN_F7R1_FB9 CAN_F7R1_FB9_Msk

Filter bit 9

◆ CAN_F7R1_FB9_Msk

#define CAN_F7R1_FB9_Msk (0x1UL << CAN_F7R1_FB9_Pos)

0x00000200

◆ CAN_F7R1_FB9_Pos

#define CAN_F7R1_FB9_Pos (9U)

◆ CAN_F7R2_FB0

#define CAN_F7R2_FB0 CAN_F7R2_FB0_Msk

Filter bit 0

◆ CAN_F7R2_FB0_Msk

#define CAN_F7R2_FB0_Msk (0x1UL << CAN_F7R2_FB0_Pos)

0x00000001

◆ CAN_F7R2_FB0_Pos

#define CAN_F7R2_FB0_Pos (0U)

◆ CAN_F7R2_FB1

#define CAN_F7R2_FB1 CAN_F7R2_FB1_Msk

Filter bit 1

◆ CAN_F7R2_FB10

#define CAN_F7R2_FB10 CAN_F7R2_FB10_Msk

Filter bit 10

◆ CAN_F7R2_FB10_Msk

#define CAN_F7R2_FB10_Msk (0x1UL << CAN_F7R2_FB10_Pos)

0x00000400

◆ CAN_F7R2_FB10_Pos

#define CAN_F7R2_FB10_Pos (10U)

◆ CAN_F7R2_FB11

#define CAN_F7R2_FB11 CAN_F7R2_FB11_Msk

Filter bit 11

◆ CAN_F7R2_FB11_Msk

#define CAN_F7R2_FB11_Msk (0x1UL << CAN_F7R2_FB11_Pos)

0x00000800

◆ CAN_F7R2_FB11_Pos

#define CAN_F7R2_FB11_Pos (11U)

◆ CAN_F7R2_FB12

#define CAN_F7R2_FB12 CAN_F7R2_FB12_Msk

Filter bit 12

◆ CAN_F7R2_FB12_Msk

#define CAN_F7R2_FB12_Msk (0x1UL << CAN_F7R2_FB12_Pos)

0x00001000

◆ CAN_F7R2_FB12_Pos

#define CAN_F7R2_FB12_Pos (12U)

◆ CAN_F7R2_FB13

#define CAN_F7R2_FB13 CAN_F7R2_FB13_Msk

Filter bit 13

◆ CAN_F7R2_FB13_Msk

#define CAN_F7R2_FB13_Msk (0x1UL << CAN_F7R2_FB13_Pos)

0x00002000

◆ CAN_F7R2_FB13_Pos

#define CAN_F7R2_FB13_Pos (13U)

◆ CAN_F7R2_FB14

#define CAN_F7R2_FB14 CAN_F7R2_FB14_Msk

Filter bit 14

◆ CAN_F7R2_FB14_Msk

#define CAN_F7R2_FB14_Msk (0x1UL << CAN_F7R2_FB14_Pos)

0x00004000

◆ CAN_F7R2_FB14_Pos

#define CAN_F7R2_FB14_Pos (14U)

◆ CAN_F7R2_FB15

#define CAN_F7R2_FB15 CAN_F7R2_FB15_Msk

Filter bit 15

◆ CAN_F7R2_FB15_Msk

#define CAN_F7R2_FB15_Msk (0x1UL << CAN_F7R2_FB15_Pos)

0x00008000

◆ CAN_F7R2_FB15_Pos

#define CAN_F7R2_FB15_Pos (15U)

◆ CAN_F7R2_FB16

#define CAN_F7R2_FB16 CAN_F7R2_FB16_Msk

Filter bit 16

◆ CAN_F7R2_FB16_Msk

#define CAN_F7R2_FB16_Msk (0x1UL << CAN_F7R2_FB16_Pos)

0x00010000

◆ CAN_F7R2_FB16_Pos

#define CAN_F7R2_FB16_Pos (16U)

◆ CAN_F7R2_FB17

#define CAN_F7R2_FB17 CAN_F7R2_FB17_Msk

Filter bit 17

◆ CAN_F7R2_FB17_Msk

#define CAN_F7R2_FB17_Msk (0x1UL << CAN_F7R2_FB17_Pos)

0x00020000

◆ CAN_F7R2_FB17_Pos

#define CAN_F7R2_FB17_Pos (17U)

◆ CAN_F7R2_FB18

#define CAN_F7R2_FB18 CAN_F7R2_FB18_Msk

Filter bit 18

◆ CAN_F7R2_FB18_Msk

#define CAN_F7R2_FB18_Msk (0x1UL << CAN_F7R2_FB18_Pos)

0x00040000

◆ CAN_F7R2_FB18_Pos

#define CAN_F7R2_FB18_Pos (18U)

◆ CAN_F7R2_FB19

#define CAN_F7R2_FB19 CAN_F7R2_FB19_Msk

Filter bit 19

◆ CAN_F7R2_FB19_Msk

#define CAN_F7R2_FB19_Msk (0x1UL << CAN_F7R2_FB19_Pos)

0x00080000

◆ CAN_F7R2_FB19_Pos

#define CAN_F7R2_FB19_Pos (19U)

◆ CAN_F7R2_FB1_Msk

#define CAN_F7R2_FB1_Msk (0x1UL << CAN_F7R2_FB1_Pos)

0x00000002

◆ CAN_F7R2_FB1_Pos

#define CAN_F7R2_FB1_Pos (1U)

◆ CAN_F7R2_FB2

#define CAN_F7R2_FB2 CAN_F7R2_FB2_Msk

Filter bit 2

◆ CAN_F7R2_FB20

#define CAN_F7R2_FB20 CAN_F7R2_FB20_Msk

Filter bit 20

◆ CAN_F7R2_FB20_Msk

#define CAN_F7R2_FB20_Msk (0x1UL << CAN_F7R2_FB20_Pos)

0x00100000

◆ CAN_F7R2_FB20_Pos

#define CAN_F7R2_FB20_Pos (20U)

◆ CAN_F7R2_FB21

#define CAN_F7R2_FB21 CAN_F7R2_FB21_Msk

Filter bit 21

◆ CAN_F7R2_FB21_Msk

#define CAN_F7R2_FB21_Msk (0x1UL << CAN_F7R2_FB21_Pos)

0x00200000

◆ CAN_F7R2_FB21_Pos

#define CAN_F7R2_FB21_Pos (21U)

◆ CAN_F7R2_FB22

#define CAN_F7R2_FB22 CAN_F7R2_FB22_Msk

Filter bit 22

◆ CAN_F7R2_FB22_Msk

#define CAN_F7R2_FB22_Msk (0x1UL << CAN_F7R2_FB22_Pos)

0x00400000

◆ CAN_F7R2_FB22_Pos

#define CAN_F7R2_FB22_Pos (22U)

◆ CAN_F7R2_FB23

#define CAN_F7R2_FB23 CAN_F7R2_FB23_Msk

Filter bit 23

◆ CAN_F7R2_FB23_Msk

#define CAN_F7R2_FB23_Msk (0x1UL << CAN_F7R2_FB23_Pos)

0x00800000

◆ CAN_F7R2_FB23_Pos

#define CAN_F7R2_FB23_Pos (23U)

◆ CAN_F7R2_FB24

#define CAN_F7R2_FB24 CAN_F7R2_FB24_Msk

Filter bit 24

◆ CAN_F7R2_FB24_Msk

#define CAN_F7R2_FB24_Msk (0x1UL << CAN_F7R2_FB24_Pos)

0x01000000

◆ CAN_F7R2_FB24_Pos

#define CAN_F7R2_FB24_Pos (24U)

◆ CAN_F7R2_FB25

#define CAN_F7R2_FB25 CAN_F7R2_FB25_Msk

Filter bit 25

◆ CAN_F7R2_FB25_Msk

#define CAN_F7R2_FB25_Msk (0x1UL << CAN_F7R2_FB25_Pos)

0x02000000

◆ CAN_F7R2_FB25_Pos

#define CAN_F7R2_FB25_Pos (25U)

◆ CAN_F7R2_FB26

#define CAN_F7R2_FB26 CAN_F7R2_FB26_Msk

Filter bit 26

◆ CAN_F7R2_FB26_Msk

#define CAN_F7R2_FB26_Msk (0x1UL << CAN_F7R2_FB26_Pos)

0x04000000

◆ CAN_F7R2_FB26_Pos

#define CAN_F7R2_FB26_Pos (26U)

◆ CAN_F7R2_FB27

#define CAN_F7R2_FB27 CAN_F7R2_FB27_Msk

Filter bit 27

◆ CAN_F7R2_FB27_Msk

#define CAN_F7R2_FB27_Msk (0x1UL << CAN_F7R2_FB27_Pos)

0x08000000

◆ CAN_F7R2_FB27_Pos

#define CAN_F7R2_FB27_Pos (27U)

◆ CAN_F7R2_FB28

#define CAN_F7R2_FB28 CAN_F7R2_FB28_Msk

Filter bit 28

◆ CAN_F7R2_FB28_Msk

#define CAN_F7R2_FB28_Msk (0x1UL << CAN_F7R2_FB28_Pos)

0x10000000

◆ CAN_F7R2_FB28_Pos

#define CAN_F7R2_FB28_Pos (28U)

◆ CAN_F7R2_FB29

#define CAN_F7R2_FB29 CAN_F7R2_FB29_Msk

Filter bit 29

◆ CAN_F7R2_FB29_Msk

#define CAN_F7R2_FB29_Msk (0x1UL << CAN_F7R2_FB29_Pos)

0x20000000

◆ CAN_F7R2_FB29_Pos

#define CAN_F7R2_FB29_Pos (29U)

◆ CAN_F7R2_FB2_Msk

#define CAN_F7R2_FB2_Msk (0x1UL << CAN_F7R2_FB2_Pos)

0x00000004

◆ CAN_F7R2_FB2_Pos

#define CAN_F7R2_FB2_Pos (2U)

◆ CAN_F7R2_FB3

#define CAN_F7R2_FB3 CAN_F7R2_FB3_Msk

Filter bit 3

◆ CAN_F7R2_FB30

#define CAN_F7R2_FB30 CAN_F7R2_FB30_Msk

Filter bit 30

◆ CAN_F7R2_FB30_Msk

#define CAN_F7R2_FB30_Msk (0x1UL << CAN_F7R2_FB30_Pos)

0x40000000

◆ CAN_F7R2_FB30_Pos

#define CAN_F7R2_FB30_Pos (30U)

◆ CAN_F7R2_FB31

#define CAN_F7R2_FB31 CAN_F7R2_FB31_Msk

Filter bit 31

◆ CAN_F7R2_FB31_Msk

#define CAN_F7R2_FB31_Msk (0x1UL << CAN_F7R2_FB31_Pos)

0x80000000

◆ CAN_F7R2_FB31_Pos

#define CAN_F7R2_FB31_Pos (31U)

◆ CAN_F7R2_FB3_Msk

#define CAN_F7R2_FB3_Msk (0x1UL << CAN_F7R2_FB3_Pos)

0x00000008

◆ CAN_F7R2_FB3_Pos

#define CAN_F7R2_FB3_Pos (3U)

◆ CAN_F7R2_FB4

#define CAN_F7R2_FB4 CAN_F7R2_FB4_Msk

Filter bit 4

◆ CAN_F7R2_FB4_Msk

#define CAN_F7R2_FB4_Msk (0x1UL << CAN_F7R2_FB4_Pos)

0x00000010

◆ CAN_F7R2_FB4_Pos

#define CAN_F7R2_FB4_Pos (4U)

◆ CAN_F7R2_FB5

#define CAN_F7R2_FB5 CAN_F7R2_FB5_Msk

Filter bit 5

◆ CAN_F7R2_FB5_Msk

#define CAN_F7R2_FB5_Msk (0x1UL << CAN_F7R2_FB5_Pos)

0x00000020

◆ CAN_F7R2_FB5_Pos

#define CAN_F7R2_FB5_Pos (5U)

◆ CAN_F7R2_FB6

#define CAN_F7R2_FB6 CAN_F7R2_FB6_Msk

Filter bit 6

◆ CAN_F7R2_FB6_Msk

#define CAN_F7R2_FB6_Msk (0x1UL << CAN_F7R2_FB6_Pos)

0x00000040

◆ CAN_F7R2_FB6_Pos

#define CAN_F7R2_FB6_Pos (6U)

◆ CAN_F7R2_FB7

#define CAN_F7R2_FB7 CAN_F7R2_FB7_Msk

Filter bit 7

◆ CAN_F7R2_FB7_Msk

#define CAN_F7R2_FB7_Msk (0x1UL << CAN_F7R2_FB7_Pos)

0x00000080

◆ CAN_F7R2_FB7_Pos

#define CAN_F7R2_FB7_Pos (7U)

◆ CAN_F7R2_FB8

#define CAN_F7R2_FB8 CAN_F7R2_FB8_Msk

Filter bit 8

◆ CAN_F7R2_FB8_Msk

#define CAN_F7R2_FB8_Msk (0x1UL << CAN_F7R2_FB8_Pos)

0x00000100

◆ CAN_F7R2_FB8_Pos

#define CAN_F7R2_FB8_Pos (8U)

◆ CAN_F7R2_FB9

#define CAN_F7R2_FB9 CAN_F7R2_FB9_Msk

Filter bit 9

◆ CAN_F7R2_FB9_Msk

#define CAN_F7R2_FB9_Msk (0x1UL << CAN_F7R2_FB9_Pos)

0x00000200

◆ CAN_F7R2_FB9_Pos

#define CAN_F7R2_FB9_Pos (9U)

◆ CAN_F8R1_FB0

#define CAN_F8R1_FB0 CAN_F8R1_FB0_Msk

Filter bit 0

◆ CAN_F8R1_FB0_Msk

#define CAN_F8R1_FB0_Msk (0x1UL << CAN_F8R1_FB0_Pos)

0x00000001

◆ CAN_F8R1_FB0_Pos

#define CAN_F8R1_FB0_Pos (0U)

◆ CAN_F8R1_FB1

#define CAN_F8R1_FB1 CAN_F8R1_FB1_Msk

Filter bit 1

◆ CAN_F8R1_FB10

#define CAN_F8R1_FB10 CAN_F8R1_FB10_Msk

Filter bit 10

◆ CAN_F8R1_FB10_Msk

#define CAN_F8R1_FB10_Msk (0x1UL << CAN_F8R1_FB10_Pos)

0x00000400

◆ CAN_F8R1_FB10_Pos

#define CAN_F8R1_FB10_Pos (10U)

◆ CAN_F8R1_FB11

#define CAN_F8R1_FB11 CAN_F8R1_FB11_Msk

Filter bit 11

◆ CAN_F8R1_FB11_Msk

#define CAN_F8R1_FB11_Msk (0x1UL << CAN_F8R1_FB11_Pos)

0x00000800

◆ CAN_F8R1_FB11_Pos

#define CAN_F8R1_FB11_Pos (11U)

◆ CAN_F8R1_FB12

#define CAN_F8R1_FB12 CAN_F8R1_FB12_Msk

Filter bit 12

◆ CAN_F8R1_FB12_Msk

#define CAN_F8R1_FB12_Msk (0x1UL << CAN_F8R1_FB12_Pos)

0x00001000

◆ CAN_F8R1_FB12_Pos

#define CAN_F8R1_FB12_Pos (12U)

◆ CAN_F8R1_FB13

#define CAN_F8R1_FB13 CAN_F8R1_FB13_Msk

Filter bit 13

◆ CAN_F8R1_FB13_Msk

#define CAN_F8R1_FB13_Msk (0x1UL << CAN_F8R1_FB13_Pos)

0x00002000

◆ CAN_F8R1_FB13_Pos

#define CAN_F8R1_FB13_Pos (13U)

◆ CAN_F8R1_FB14

#define CAN_F8R1_FB14 CAN_F8R1_FB14_Msk

Filter bit 14

◆ CAN_F8R1_FB14_Msk

#define CAN_F8R1_FB14_Msk (0x1UL << CAN_F8R1_FB14_Pos)

0x00004000

◆ CAN_F8R1_FB14_Pos

#define CAN_F8R1_FB14_Pos (14U)

◆ CAN_F8R1_FB15

#define CAN_F8R1_FB15 CAN_F8R1_FB15_Msk

Filter bit 15

◆ CAN_F8R1_FB15_Msk

#define CAN_F8R1_FB15_Msk (0x1UL << CAN_F8R1_FB15_Pos)

0x00008000

◆ CAN_F8R1_FB15_Pos

#define CAN_F8R1_FB15_Pos (15U)

◆ CAN_F8R1_FB16

#define CAN_F8R1_FB16 CAN_F8R1_FB16_Msk

Filter bit 16

◆ CAN_F8R1_FB16_Msk

#define CAN_F8R1_FB16_Msk (0x1UL << CAN_F8R1_FB16_Pos)

0x00010000

◆ CAN_F8R1_FB16_Pos

#define CAN_F8R1_FB16_Pos (16U)

◆ CAN_F8R1_FB17

#define CAN_F8R1_FB17 CAN_F8R1_FB17_Msk

Filter bit 17

◆ CAN_F8R1_FB17_Msk

#define CAN_F8R1_FB17_Msk (0x1UL << CAN_F8R1_FB17_Pos)

0x00020000

◆ CAN_F8R1_FB17_Pos

#define CAN_F8R1_FB17_Pos (17U)

◆ CAN_F8R1_FB18

#define CAN_F8R1_FB18 CAN_F8R1_FB18_Msk

Filter bit 18

◆ CAN_F8R1_FB18_Msk

#define CAN_F8R1_FB18_Msk (0x1UL << CAN_F8R1_FB18_Pos)

0x00040000

◆ CAN_F8R1_FB18_Pos

#define CAN_F8R1_FB18_Pos (18U)

◆ CAN_F8R1_FB19

#define CAN_F8R1_FB19 CAN_F8R1_FB19_Msk

Filter bit 19

◆ CAN_F8R1_FB19_Msk

#define CAN_F8R1_FB19_Msk (0x1UL << CAN_F8R1_FB19_Pos)

0x00080000

◆ CAN_F8R1_FB19_Pos

#define CAN_F8R1_FB19_Pos (19U)

◆ CAN_F8R1_FB1_Msk

#define CAN_F8R1_FB1_Msk (0x1UL << CAN_F8R1_FB1_Pos)

0x00000002

◆ CAN_F8R1_FB1_Pos

#define CAN_F8R1_FB1_Pos (1U)

◆ CAN_F8R1_FB2

#define CAN_F8R1_FB2 CAN_F8R1_FB2_Msk

Filter bit 2

◆ CAN_F8R1_FB20

#define CAN_F8R1_FB20 CAN_F8R1_FB20_Msk

Filter bit 20

◆ CAN_F8R1_FB20_Msk

#define CAN_F8R1_FB20_Msk (0x1UL << CAN_F8R1_FB20_Pos)

0x00100000

◆ CAN_F8R1_FB20_Pos

#define CAN_F8R1_FB20_Pos (20U)

◆ CAN_F8R1_FB21

#define CAN_F8R1_FB21 CAN_F8R1_FB21_Msk

Filter bit 21

◆ CAN_F8R1_FB21_Msk

#define CAN_F8R1_FB21_Msk (0x1UL << CAN_F8R1_FB21_Pos)

0x00200000

◆ CAN_F8R1_FB21_Pos

#define CAN_F8R1_FB21_Pos (21U)

◆ CAN_F8R1_FB22

#define CAN_F8R1_FB22 CAN_F8R1_FB22_Msk

Filter bit 22

◆ CAN_F8R1_FB22_Msk

#define CAN_F8R1_FB22_Msk (0x1UL << CAN_F8R1_FB22_Pos)

0x00400000

◆ CAN_F8R1_FB22_Pos

#define CAN_F8R1_FB22_Pos (22U)

◆ CAN_F8R1_FB23

#define CAN_F8R1_FB23 CAN_F8R1_FB23_Msk

Filter bit 23

◆ CAN_F8R1_FB23_Msk

#define CAN_F8R1_FB23_Msk (0x1UL << CAN_F8R1_FB23_Pos)

0x00800000

◆ CAN_F8R1_FB23_Pos

#define CAN_F8R1_FB23_Pos (23U)

◆ CAN_F8R1_FB24

#define CAN_F8R1_FB24 CAN_F8R1_FB24_Msk

Filter bit 24

◆ CAN_F8R1_FB24_Msk

#define CAN_F8R1_FB24_Msk (0x1UL << CAN_F8R1_FB24_Pos)

0x01000000

◆ CAN_F8R1_FB24_Pos

#define CAN_F8R1_FB24_Pos (24U)

◆ CAN_F8R1_FB25

#define CAN_F8R1_FB25 CAN_F8R1_FB25_Msk

Filter bit 25

◆ CAN_F8R1_FB25_Msk

#define CAN_F8R1_FB25_Msk (0x1UL << CAN_F8R1_FB25_Pos)

0x02000000

◆ CAN_F8R1_FB25_Pos

#define CAN_F8R1_FB25_Pos (25U)

◆ CAN_F8R1_FB26

#define CAN_F8R1_FB26 CAN_F8R1_FB26_Msk

Filter bit 26

◆ CAN_F8R1_FB26_Msk

#define CAN_F8R1_FB26_Msk (0x1UL << CAN_F8R1_FB26_Pos)

0x04000000

◆ CAN_F8R1_FB26_Pos

#define CAN_F8R1_FB26_Pos (26U)

◆ CAN_F8R1_FB27

#define CAN_F8R1_FB27 CAN_F8R1_FB27_Msk

Filter bit 27

◆ CAN_F8R1_FB27_Msk

#define CAN_F8R1_FB27_Msk (0x1UL << CAN_F8R1_FB27_Pos)

0x08000000

◆ CAN_F8R1_FB27_Pos

#define CAN_F8R1_FB27_Pos (27U)

◆ CAN_F8R1_FB28

#define CAN_F8R1_FB28 CAN_F8R1_FB28_Msk

Filter bit 28

◆ CAN_F8R1_FB28_Msk

#define CAN_F8R1_FB28_Msk (0x1UL << CAN_F8R1_FB28_Pos)

0x10000000

◆ CAN_F8R1_FB28_Pos

#define CAN_F8R1_FB28_Pos (28U)

◆ CAN_F8R1_FB29

#define CAN_F8R1_FB29 CAN_F8R1_FB29_Msk

Filter bit 29

◆ CAN_F8R1_FB29_Msk

#define CAN_F8R1_FB29_Msk (0x1UL << CAN_F8R1_FB29_Pos)

0x20000000

◆ CAN_F8R1_FB29_Pos

#define CAN_F8R1_FB29_Pos (29U)

◆ CAN_F8R1_FB2_Msk

#define CAN_F8R1_FB2_Msk (0x1UL << CAN_F8R1_FB2_Pos)

0x00000004

◆ CAN_F8R1_FB2_Pos

#define CAN_F8R1_FB2_Pos (2U)

◆ CAN_F8R1_FB3

#define CAN_F8R1_FB3 CAN_F8R1_FB3_Msk

Filter bit 3

◆ CAN_F8R1_FB30

#define CAN_F8R1_FB30 CAN_F8R1_FB30_Msk

Filter bit 30

◆ CAN_F8R1_FB30_Msk

#define CAN_F8R1_FB30_Msk (0x1UL << CAN_F8R1_FB30_Pos)

0x40000000

◆ CAN_F8R1_FB30_Pos

#define CAN_F8R1_FB30_Pos (30U)

◆ CAN_F8R1_FB31

#define CAN_F8R1_FB31 CAN_F8R1_FB31_Msk

Filter bit 31

◆ CAN_F8R1_FB31_Msk

#define CAN_F8R1_FB31_Msk (0x1UL << CAN_F8R1_FB31_Pos)

0x80000000

◆ CAN_F8R1_FB31_Pos

#define CAN_F8R1_FB31_Pos (31U)

◆ CAN_F8R1_FB3_Msk

#define CAN_F8R1_FB3_Msk (0x1UL << CAN_F8R1_FB3_Pos)

0x00000008

◆ CAN_F8R1_FB3_Pos

#define CAN_F8R1_FB3_Pos (3U)

◆ CAN_F8R1_FB4

#define CAN_F8R1_FB4 CAN_F8R1_FB4_Msk

Filter bit 4

◆ CAN_F8R1_FB4_Msk

#define CAN_F8R1_FB4_Msk (0x1UL << CAN_F8R1_FB4_Pos)

0x00000010

◆ CAN_F8R1_FB4_Pos

#define CAN_F8R1_FB4_Pos (4U)

◆ CAN_F8R1_FB5

#define CAN_F8R1_FB5 CAN_F8R1_FB5_Msk

Filter bit 5

◆ CAN_F8R1_FB5_Msk

#define CAN_F8R1_FB5_Msk (0x1UL << CAN_F8R1_FB5_Pos)

0x00000020

◆ CAN_F8R1_FB5_Pos

#define CAN_F8R1_FB5_Pos (5U)

◆ CAN_F8R1_FB6

#define CAN_F8R1_FB6 CAN_F8R1_FB6_Msk

Filter bit 6

◆ CAN_F8R1_FB6_Msk

#define CAN_F8R1_FB6_Msk (0x1UL << CAN_F8R1_FB6_Pos)

0x00000040

◆ CAN_F8R1_FB6_Pos

#define CAN_F8R1_FB6_Pos (6U)

◆ CAN_F8R1_FB7

#define CAN_F8R1_FB7 CAN_F8R1_FB7_Msk

Filter bit 7

◆ CAN_F8R1_FB7_Msk

#define CAN_F8R1_FB7_Msk (0x1UL << CAN_F8R1_FB7_Pos)

0x00000080

◆ CAN_F8R1_FB7_Pos

#define CAN_F8R1_FB7_Pos (7U)

◆ CAN_F8R1_FB8

#define CAN_F8R1_FB8 CAN_F8R1_FB8_Msk

Filter bit 8

◆ CAN_F8R1_FB8_Msk

#define CAN_F8R1_FB8_Msk (0x1UL << CAN_F8R1_FB8_Pos)

0x00000100

◆ CAN_F8R1_FB8_Pos

#define CAN_F8R1_FB8_Pos (8U)

◆ CAN_F8R1_FB9

#define CAN_F8R1_FB9 CAN_F8R1_FB9_Msk

Filter bit 9

◆ CAN_F8R1_FB9_Msk

#define CAN_F8R1_FB9_Msk (0x1UL << CAN_F8R1_FB9_Pos)

0x00000200

◆ CAN_F8R1_FB9_Pos

#define CAN_F8R1_FB9_Pos (9U)

◆ CAN_F8R2_FB0

#define CAN_F8R2_FB0 CAN_F8R2_FB0_Msk

Filter bit 0

◆ CAN_F8R2_FB0_Msk

#define CAN_F8R2_FB0_Msk (0x1UL << CAN_F8R2_FB0_Pos)

0x00000001

◆ CAN_F8R2_FB0_Pos

#define CAN_F8R2_FB0_Pos (0U)

◆ CAN_F8R2_FB1

#define CAN_F8R2_FB1 CAN_F8R2_FB1_Msk

Filter bit 1

◆ CAN_F8R2_FB10

#define CAN_F8R2_FB10 CAN_F8R2_FB10_Msk

Filter bit 10

◆ CAN_F8R2_FB10_Msk

#define CAN_F8R2_FB10_Msk (0x1UL << CAN_F8R2_FB10_Pos)

0x00000400

◆ CAN_F8R2_FB10_Pos

#define CAN_F8R2_FB10_Pos (10U)

◆ CAN_F8R2_FB11

#define CAN_F8R2_FB11 CAN_F8R2_FB11_Msk

Filter bit 11

◆ CAN_F8R2_FB11_Msk

#define CAN_F8R2_FB11_Msk (0x1UL << CAN_F8R2_FB11_Pos)

0x00000800

◆ CAN_F8R2_FB11_Pos

#define CAN_F8R2_FB11_Pos (11U)

◆ CAN_F8R2_FB12

#define CAN_F8R2_FB12 CAN_F8R2_FB12_Msk

Filter bit 12

◆ CAN_F8R2_FB12_Msk

#define CAN_F8R2_FB12_Msk (0x1UL << CAN_F8R2_FB12_Pos)

0x00001000

◆ CAN_F8R2_FB12_Pos

#define CAN_F8R2_FB12_Pos (12U)

◆ CAN_F8R2_FB13

#define CAN_F8R2_FB13 CAN_F8R2_FB13_Msk

Filter bit 13

◆ CAN_F8R2_FB13_Msk

#define CAN_F8R2_FB13_Msk (0x1UL << CAN_F8R2_FB13_Pos)

0x00002000

◆ CAN_F8R2_FB13_Pos

#define CAN_F8R2_FB13_Pos (13U)

◆ CAN_F8R2_FB14

#define CAN_F8R2_FB14 CAN_F8R2_FB14_Msk

Filter bit 14

◆ CAN_F8R2_FB14_Msk

#define CAN_F8R2_FB14_Msk (0x1UL << CAN_F8R2_FB14_Pos)

0x00004000

◆ CAN_F8R2_FB14_Pos

#define CAN_F8R2_FB14_Pos (14U)

◆ CAN_F8R2_FB15

#define CAN_F8R2_FB15 CAN_F8R2_FB15_Msk

Filter bit 15

◆ CAN_F8R2_FB15_Msk

#define CAN_F8R2_FB15_Msk (0x1UL << CAN_F8R2_FB15_Pos)

0x00008000

◆ CAN_F8R2_FB15_Pos

#define CAN_F8R2_FB15_Pos (15U)

◆ CAN_F8R2_FB16

#define CAN_F8R2_FB16 CAN_F8R2_FB16_Msk

Filter bit 16

◆ CAN_F8R2_FB16_Msk

#define CAN_F8R2_FB16_Msk (0x1UL << CAN_F8R2_FB16_Pos)

0x00010000

◆ CAN_F8R2_FB16_Pos

#define CAN_F8R2_FB16_Pos (16U)

◆ CAN_F8R2_FB17

#define CAN_F8R2_FB17 CAN_F8R2_FB17_Msk

Filter bit 17

◆ CAN_F8R2_FB17_Msk

#define CAN_F8R2_FB17_Msk (0x1UL << CAN_F8R2_FB17_Pos)

0x00020000

◆ CAN_F8R2_FB17_Pos

#define CAN_F8R2_FB17_Pos (17U)

◆ CAN_F8R2_FB18

#define CAN_F8R2_FB18 CAN_F8R2_FB18_Msk

Filter bit 18

◆ CAN_F8R2_FB18_Msk

#define CAN_F8R2_FB18_Msk (0x1UL << CAN_F8R2_FB18_Pos)

0x00040000

◆ CAN_F8R2_FB18_Pos

#define CAN_F8R2_FB18_Pos (18U)

◆ CAN_F8R2_FB19

#define CAN_F8R2_FB19 CAN_F8R2_FB19_Msk

Filter bit 19

◆ CAN_F8R2_FB19_Msk

#define CAN_F8R2_FB19_Msk (0x1UL << CAN_F8R2_FB19_Pos)

0x00080000

◆ CAN_F8R2_FB19_Pos

#define CAN_F8R2_FB19_Pos (19U)

◆ CAN_F8R2_FB1_Msk

#define CAN_F8R2_FB1_Msk (0x1UL << CAN_F8R2_FB1_Pos)

0x00000002

◆ CAN_F8R2_FB1_Pos

#define CAN_F8R2_FB1_Pos (1U)

◆ CAN_F8R2_FB2

#define CAN_F8R2_FB2 CAN_F8R2_FB2_Msk

Filter bit 2

◆ CAN_F8R2_FB20

#define CAN_F8R2_FB20 CAN_F8R2_FB20_Msk

Filter bit 20

◆ CAN_F8R2_FB20_Msk

#define CAN_F8R2_FB20_Msk (0x1UL << CAN_F8R2_FB20_Pos)

0x00100000

◆ CAN_F8R2_FB20_Pos

#define CAN_F8R2_FB20_Pos (20U)

◆ CAN_F8R2_FB21

#define CAN_F8R2_FB21 CAN_F8R2_FB21_Msk

Filter bit 21

◆ CAN_F8R2_FB21_Msk

#define CAN_F8R2_FB21_Msk (0x1UL << CAN_F8R2_FB21_Pos)

0x00200000

◆ CAN_F8R2_FB21_Pos

#define CAN_F8R2_FB21_Pos (21U)

◆ CAN_F8R2_FB22

#define CAN_F8R2_FB22 CAN_F8R2_FB22_Msk

Filter bit 22

◆ CAN_F8R2_FB22_Msk

#define CAN_F8R2_FB22_Msk (0x1UL << CAN_F8R2_FB22_Pos)

0x00400000

◆ CAN_F8R2_FB22_Pos

#define CAN_F8R2_FB22_Pos (22U)

◆ CAN_F8R2_FB23

#define CAN_F8R2_FB23 CAN_F8R2_FB23_Msk

Filter bit 23

◆ CAN_F8R2_FB23_Msk

#define CAN_F8R2_FB23_Msk (0x1UL << CAN_F8R2_FB23_Pos)

0x00800000

◆ CAN_F8R2_FB23_Pos

#define CAN_F8R2_FB23_Pos (23U)

◆ CAN_F8R2_FB24

#define CAN_F8R2_FB24 CAN_F8R2_FB24_Msk

Filter bit 24

◆ CAN_F8R2_FB24_Msk

#define CAN_F8R2_FB24_Msk (0x1UL << CAN_F8R2_FB24_Pos)

0x01000000

◆ CAN_F8R2_FB24_Pos

#define CAN_F8R2_FB24_Pos (24U)

◆ CAN_F8R2_FB25

#define CAN_F8R2_FB25 CAN_F8R2_FB25_Msk

Filter bit 25

◆ CAN_F8R2_FB25_Msk

#define CAN_F8R2_FB25_Msk (0x1UL << CAN_F8R2_FB25_Pos)

0x02000000

◆ CAN_F8R2_FB25_Pos

#define CAN_F8R2_FB25_Pos (25U)

◆ CAN_F8R2_FB26

#define CAN_F8R2_FB26 CAN_F8R2_FB26_Msk

Filter bit 26

◆ CAN_F8R2_FB26_Msk

#define CAN_F8R2_FB26_Msk (0x1UL << CAN_F8R2_FB26_Pos)

0x04000000

◆ CAN_F8R2_FB26_Pos

#define CAN_F8R2_FB26_Pos (26U)

◆ CAN_F8R2_FB27

#define CAN_F8R2_FB27 CAN_F8R2_FB27_Msk

Filter bit 27

◆ CAN_F8R2_FB27_Msk

#define CAN_F8R2_FB27_Msk (0x1UL << CAN_F8R2_FB27_Pos)

0x08000000

◆ CAN_F8R2_FB27_Pos

#define CAN_F8R2_FB27_Pos (27U)

◆ CAN_F8R2_FB28

#define CAN_F8R2_FB28 CAN_F8R2_FB28_Msk

Filter bit 28

◆ CAN_F8R2_FB28_Msk

#define CAN_F8R2_FB28_Msk (0x1UL << CAN_F8R2_FB28_Pos)

0x10000000

◆ CAN_F8R2_FB28_Pos

#define CAN_F8R2_FB28_Pos (28U)

◆ CAN_F8R2_FB29

#define CAN_F8R2_FB29 CAN_F8R2_FB29_Msk

Filter bit 29

◆ CAN_F8R2_FB29_Msk

#define CAN_F8R2_FB29_Msk (0x1UL << CAN_F8R2_FB29_Pos)

0x20000000

◆ CAN_F8R2_FB29_Pos

#define CAN_F8R2_FB29_Pos (29U)

◆ CAN_F8R2_FB2_Msk

#define CAN_F8R2_FB2_Msk (0x1UL << CAN_F8R2_FB2_Pos)

0x00000004

◆ CAN_F8R2_FB2_Pos

#define CAN_F8R2_FB2_Pos (2U)

◆ CAN_F8R2_FB3

#define CAN_F8R2_FB3 CAN_F8R2_FB3_Msk

Filter bit 3

◆ CAN_F8R2_FB30

#define CAN_F8R2_FB30 CAN_F8R2_FB30_Msk

Filter bit 30

◆ CAN_F8R2_FB30_Msk

#define CAN_F8R2_FB30_Msk (0x1UL << CAN_F8R2_FB30_Pos)

0x40000000

◆ CAN_F8R2_FB30_Pos

#define CAN_F8R2_FB30_Pos (30U)

◆ CAN_F8R2_FB31

#define CAN_F8R2_FB31 CAN_F8R2_FB31_Msk

Filter bit 31

◆ CAN_F8R2_FB31_Msk

#define CAN_F8R2_FB31_Msk (0x1UL << CAN_F8R2_FB31_Pos)

0x80000000

◆ CAN_F8R2_FB31_Pos

#define CAN_F8R2_FB31_Pos (31U)

◆ CAN_F8R2_FB3_Msk

#define CAN_F8R2_FB3_Msk (0x1UL << CAN_F8R2_FB3_Pos)

0x00000008

◆ CAN_F8R2_FB3_Pos

#define CAN_F8R2_FB3_Pos (3U)

◆ CAN_F8R2_FB4

#define CAN_F8R2_FB4 CAN_F8R2_FB4_Msk

Filter bit 4

◆ CAN_F8R2_FB4_Msk

#define CAN_F8R2_FB4_Msk (0x1UL << CAN_F8R2_FB4_Pos)

0x00000010

◆ CAN_F8R2_FB4_Pos

#define CAN_F8R2_FB4_Pos (4U)

◆ CAN_F8R2_FB5

#define CAN_F8R2_FB5 CAN_F8R2_FB5_Msk

Filter bit 5

◆ CAN_F8R2_FB5_Msk

#define CAN_F8R2_FB5_Msk (0x1UL << CAN_F8R2_FB5_Pos)

0x00000020

◆ CAN_F8R2_FB5_Pos

#define CAN_F8R2_FB5_Pos (5U)

◆ CAN_F8R2_FB6

#define CAN_F8R2_FB6 CAN_F8R2_FB6_Msk

Filter bit 6

◆ CAN_F8R2_FB6_Msk

#define CAN_F8R2_FB6_Msk (0x1UL << CAN_F8R2_FB6_Pos)

0x00000040

◆ CAN_F8R2_FB6_Pos

#define CAN_F8R2_FB6_Pos (6U)

◆ CAN_F8R2_FB7

#define CAN_F8R2_FB7 CAN_F8R2_FB7_Msk

Filter bit 7

◆ CAN_F8R2_FB7_Msk

#define CAN_F8R2_FB7_Msk (0x1UL << CAN_F8R2_FB7_Pos)

0x00000080

◆ CAN_F8R2_FB7_Pos

#define CAN_F8R2_FB7_Pos (7U)

◆ CAN_F8R2_FB8

#define CAN_F8R2_FB8 CAN_F8R2_FB8_Msk

Filter bit 8

◆ CAN_F8R2_FB8_Msk

#define CAN_F8R2_FB8_Msk (0x1UL << CAN_F8R2_FB8_Pos)

0x00000100

◆ CAN_F8R2_FB8_Pos

#define CAN_F8R2_FB8_Pos (8U)

◆ CAN_F8R2_FB9

#define CAN_F8R2_FB9 CAN_F8R2_FB9_Msk

Filter bit 9

◆ CAN_F8R2_FB9_Msk

#define CAN_F8R2_FB9_Msk (0x1UL << CAN_F8R2_FB9_Pos)

0x00000200

◆ CAN_F8R2_FB9_Pos

#define CAN_F8R2_FB9_Pos (9U)

◆ CAN_F9R1_FB0

#define CAN_F9R1_FB0 CAN_F9R1_FB0_Msk

Filter bit 0

◆ CAN_F9R1_FB0_Msk

#define CAN_F9R1_FB0_Msk (0x1UL << CAN_F9R1_FB0_Pos)

0x00000001

◆ CAN_F9R1_FB0_Pos

#define CAN_F9R1_FB0_Pos (0U)

◆ CAN_F9R1_FB1

#define CAN_F9R1_FB1 CAN_F9R1_FB1_Msk

Filter bit 1

◆ CAN_F9R1_FB10

#define CAN_F9R1_FB10 CAN_F9R1_FB10_Msk

Filter bit 10

◆ CAN_F9R1_FB10_Msk

#define CAN_F9R1_FB10_Msk (0x1UL << CAN_F9R1_FB10_Pos)

0x00000400

◆ CAN_F9R1_FB10_Pos

#define CAN_F9R1_FB10_Pos (10U)

◆ CAN_F9R1_FB11

#define CAN_F9R1_FB11 CAN_F9R1_FB11_Msk

Filter bit 11

◆ CAN_F9R1_FB11_Msk

#define CAN_F9R1_FB11_Msk (0x1UL << CAN_F9R1_FB11_Pos)

0x00000800

◆ CAN_F9R1_FB11_Pos

#define CAN_F9R1_FB11_Pos (11U)

◆ CAN_F9R1_FB12

#define CAN_F9R1_FB12 CAN_F9R1_FB12_Msk

Filter bit 12

◆ CAN_F9R1_FB12_Msk

#define CAN_F9R1_FB12_Msk (0x1UL << CAN_F9R1_FB12_Pos)

0x00001000

◆ CAN_F9R1_FB12_Pos

#define CAN_F9R1_FB12_Pos (12U)

◆ CAN_F9R1_FB13

#define CAN_F9R1_FB13 CAN_F9R1_FB13_Msk

Filter bit 13

◆ CAN_F9R1_FB13_Msk

#define CAN_F9R1_FB13_Msk (0x1UL << CAN_F9R1_FB13_Pos)

0x00002000

◆ CAN_F9R1_FB13_Pos

#define CAN_F9R1_FB13_Pos (13U)

◆ CAN_F9R1_FB14

#define CAN_F9R1_FB14 CAN_F9R1_FB14_Msk

Filter bit 14

◆ CAN_F9R1_FB14_Msk

#define CAN_F9R1_FB14_Msk (0x1UL << CAN_F9R1_FB14_Pos)

0x00004000

◆ CAN_F9R1_FB14_Pos

#define CAN_F9R1_FB14_Pos (14U)

◆ CAN_F9R1_FB15

#define CAN_F9R1_FB15 CAN_F9R1_FB15_Msk

Filter bit 15

◆ CAN_F9R1_FB15_Msk

#define CAN_F9R1_FB15_Msk (0x1UL << CAN_F9R1_FB15_Pos)

0x00008000

◆ CAN_F9R1_FB15_Pos

#define CAN_F9R1_FB15_Pos (15U)

◆ CAN_F9R1_FB16

#define CAN_F9R1_FB16 CAN_F9R1_FB16_Msk

Filter bit 16

◆ CAN_F9R1_FB16_Msk

#define CAN_F9R1_FB16_Msk (0x1UL << CAN_F9R1_FB16_Pos)

0x00010000

◆ CAN_F9R1_FB16_Pos

#define CAN_F9R1_FB16_Pos (16U)

◆ CAN_F9R1_FB17

#define CAN_F9R1_FB17 CAN_F9R1_FB17_Msk

Filter bit 17

◆ CAN_F9R1_FB17_Msk

#define CAN_F9R1_FB17_Msk (0x1UL << CAN_F9R1_FB17_Pos)

0x00020000

◆ CAN_F9R1_FB17_Pos

#define CAN_F9R1_FB17_Pos (17U)

◆ CAN_F9R1_FB18

#define CAN_F9R1_FB18 CAN_F9R1_FB18_Msk

Filter bit 18

◆ CAN_F9R1_FB18_Msk

#define CAN_F9R1_FB18_Msk (0x1UL << CAN_F9R1_FB18_Pos)

0x00040000

◆ CAN_F9R1_FB18_Pos

#define CAN_F9R1_FB18_Pos (18U)

◆ CAN_F9R1_FB19

#define CAN_F9R1_FB19 CAN_F9R1_FB19_Msk

Filter bit 19

◆ CAN_F9R1_FB19_Msk

#define CAN_F9R1_FB19_Msk (0x1UL << CAN_F9R1_FB19_Pos)

0x00080000

◆ CAN_F9R1_FB19_Pos

#define CAN_F9R1_FB19_Pos (19U)

◆ CAN_F9R1_FB1_Msk

#define CAN_F9R1_FB1_Msk (0x1UL << CAN_F9R1_FB1_Pos)

0x00000002

◆ CAN_F9R1_FB1_Pos

#define CAN_F9R1_FB1_Pos (1U)

◆ CAN_F9R1_FB2

#define CAN_F9R1_FB2 CAN_F9R1_FB2_Msk

Filter bit 2

◆ CAN_F9R1_FB20

#define CAN_F9R1_FB20 CAN_F9R1_FB20_Msk

Filter bit 20

◆ CAN_F9R1_FB20_Msk

#define CAN_F9R1_FB20_Msk (0x1UL << CAN_F9R1_FB20_Pos)

0x00100000

◆ CAN_F9R1_FB20_Pos

#define CAN_F9R1_FB20_Pos (20U)

◆ CAN_F9R1_FB21

#define CAN_F9R1_FB21 CAN_F9R1_FB21_Msk

Filter bit 21

◆ CAN_F9R1_FB21_Msk

#define CAN_F9R1_FB21_Msk (0x1UL << CAN_F9R1_FB21_Pos)

0x00200000

◆ CAN_F9R1_FB21_Pos

#define CAN_F9R1_FB21_Pos (21U)

◆ CAN_F9R1_FB22

#define CAN_F9R1_FB22 CAN_F9R1_FB22_Msk

Filter bit 22

◆ CAN_F9R1_FB22_Msk

#define CAN_F9R1_FB22_Msk (0x1UL << CAN_F9R1_FB22_Pos)

0x00400000

◆ CAN_F9R1_FB22_Pos

#define CAN_F9R1_FB22_Pos (22U)

◆ CAN_F9R1_FB23

#define CAN_F9R1_FB23 CAN_F9R1_FB23_Msk

Filter bit 23

◆ CAN_F9R1_FB23_Msk

#define CAN_F9R1_FB23_Msk (0x1UL << CAN_F9R1_FB23_Pos)

0x00800000

◆ CAN_F9R1_FB23_Pos

#define CAN_F9R1_FB23_Pos (23U)

◆ CAN_F9R1_FB24

#define CAN_F9R1_FB24 CAN_F9R1_FB24_Msk

Filter bit 24

◆ CAN_F9R1_FB24_Msk

#define CAN_F9R1_FB24_Msk (0x1UL << CAN_F9R1_FB24_Pos)

0x01000000

◆ CAN_F9R1_FB24_Pos

#define CAN_F9R1_FB24_Pos (24U)

◆ CAN_F9R1_FB25

#define CAN_F9R1_FB25 CAN_F9R1_FB25_Msk

Filter bit 25

◆ CAN_F9R1_FB25_Msk

#define CAN_F9R1_FB25_Msk (0x1UL << CAN_F9R1_FB25_Pos)

0x02000000

◆ CAN_F9R1_FB25_Pos

#define CAN_F9R1_FB25_Pos (25U)

◆ CAN_F9R1_FB26

#define CAN_F9R1_FB26 CAN_F9R1_FB26_Msk

Filter bit 26

◆ CAN_F9R1_FB26_Msk

#define CAN_F9R1_FB26_Msk (0x1UL << CAN_F9R1_FB26_Pos)

0x04000000

◆ CAN_F9R1_FB26_Pos

#define CAN_F9R1_FB26_Pos (26U)

◆ CAN_F9R1_FB27

#define CAN_F9R1_FB27 CAN_F9R1_FB27_Msk

Filter bit 27

◆ CAN_F9R1_FB27_Msk

#define CAN_F9R1_FB27_Msk (0x1UL << CAN_F9R1_FB27_Pos)

0x08000000

◆ CAN_F9R1_FB27_Pos

#define CAN_F9R1_FB27_Pos (27U)

◆ CAN_F9R1_FB28

#define CAN_F9R1_FB28 CAN_F9R1_FB28_Msk

Filter bit 28

◆ CAN_F9R1_FB28_Msk

#define CAN_F9R1_FB28_Msk (0x1UL << CAN_F9R1_FB28_Pos)

0x10000000

◆ CAN_F9R1_FB28_Pos

#define CAN_F9R1_FB28_Pos (28U)

◆ CAN_F9R1_FB29

#define CAN_F9R1_FB29 CAN_F9R1_FB29_Msk

Filter bit 29

◆ CAN_F9R1_FB29_Msk

#define CAN_F9R1_FB29_Msk (0x1UL << CAN_F9R1_FB29_Pos)

0x20000000

◆ CAN_F9R1_FB29_Pos

#define CAN_F9R1_FB29_Pos (29U)

◆ CAN_F9R1_FB2_Msk

#define CAN_F9R1_FB2_Msk (0x1UL << CAN_F9R1_FB2_Pos)

0x00000004

◆ CAN_F9R1_FB2_Pos

#define CAN_F9R1_FB2_Pos (2U)

◆ CAN_F9R1_FB3

#define CAN_F9R1_FB3 CAN_F9R1_FB3_Msk

Filter bit 3

◆ CAN_F9R1_FB30

#define CAN_F9R1_FB30 CAN_F9R1_FB30_Msk

Filter bit 30

◆ CAN_F9R1_FB30_Msk

#define CAN_F9R1_FB30_Msk (0x1UL << CAN_F9R1_FB30_Pos)

0x40000000

◆ CAN_F9R1_FB30_Pos

#define CAN_F9R1_FB30_Pos (30U)

◆ CAN_F9R1_FB31

#define CAN_F9R1_FB31 CAN_F9R1_FB31_Msk

Filter bit 31

◆ CAN_F9R1_FB31_Msk

#define CAN_F9R1_FB31_Msk (0x1UL << CAN_F9R1_FB31_Pos)

0x80000000

◆ CAN_F9R1_FB31_Pos

#define CAN_F9R1_FB31_Pos (31U)

◆ CAN_F9R1_FB3_Msk

#define CAN_F9R1_FB3_Msk (0x1UL << CAN_F9R1_FB3_Pos)

0x00000008

◆ CAN_F9R1_FB3_Pos

#define CAN_F9R1_FB3_Pos (3U)

◆ CAN_F9R1_FB4

#define CAN_F9R1_FB4 CAN_F9R1_FB4_Msk

Filter bit 4

◆ CAN_F9R1_FB4_Msk

#define CAN_F9R1_FB4_Msk (0x1UL << CAN_F9R1_FB4_Pos)

0x00000010

◆ CAN_F9R1_FB4_Pos

#define CAN_F9R1_FB4_Pos (4U)

◆ CAN_F9R1_FB5

#define CAN_F9R1_FB5 CAN_F9R1_FB5_Msk

Filter bit 5

◆ CAN_F9R1_FB5_Msk

#define CAN_F9R1_FB5_Msk (0x1UL << CAN_F9R1_FB5_Pos)

0x00000020

◆ CAN_F9R1_FB5_Pos

#define CAN_F9R1_FB5_Pos (5U)

◆ CAN_F9R1_FB6

#define CAN_F9R1_FB6 CAN_F9R1_FB6_Msk

Filter bit 6

◆ CAN_F9R1_FB6_Msk

#define CAN_F9R1_FB6_Msk (0x1UL << CAN_F9R1_FB6_Pos)

0x00000040

◆ CAN_F9R1_FB6_Pos

#define CAN_F9R1_FB6_Pos (6U)

◆ CAN_F9R1_FB7

#define CAN_F9R1_FB7 CAN_F9R1_FB7_Msk

Filter bit 7

◆ CAN_F9R1_FB7_Msk

#define CAN_F9R1_FB7_Msk (0x1UL << CAN_F9R1_FB7_Pos)

0x00000080

◆ CAN_F9R1_FB7_Pos

#define CAN_F9R1_FB7_Pos (7U)

◆ CAN_F9R1_FB8

#define CAN_F9R1_FB8 CAN_F9R1_FB8_Msk

Filter bit 8

◆ CAN_F9R1_FB8_Msk

#define CAN_F9R1_FB8_Msk (0x1UL << CAN_F9R1_FB8_Pos)

0x00000100

◆ CAN_F9R1_FB8_Pos

#define CAN_F9R1_FB8_Pos (8U)

◆ CAN_F9R1_FB9

#define CAN_F9R1_FB9 CAN_F9R1_FB9_Msk

Filter bit 9

◆ CAN_F9R1_FB9_Msk

#define CAN_F9R1_FB9_Msk (0x1UL << CAN_F9R1_FB9_Pos)

0x00000200

◆ CAN_F9R1_FB9_Pos

#define CAN_F9R1_FB9_Pos (9U)

◆ CAN_F9R2_FB0

#define CAN_F9R2_FB0 CAN_F9R2_FB0_Msk

Filter bit 0

◆ CAN_F9R2_FB0_Msk

#define CAN_F9R2_FB0_Msk (0x1UL << CAN_F9R2_FB0_Pos)

0x00000001

◆ CAN_F9R2_FB0_Pos

#define CAN_F9R2_FB0_Pos (0U)

◆ CAN_F9R2_FB1

#define CAN_F9R2_FB1 CAN_F9R2_FB1_Msk

Filter bit 1

◆ CAN_F9R2_FB10

#define CAN_F9R2_FB10 CAN_F9R2_FB10_Msk

Filter bit 10

◆ CAN_F9R2_FB10_Msk

#define CAN_F9R2_FB10_Msk (0x1UL << CAN_F9R2_FB10_Pos)

0x00000400

◆ CAN_F9R2_FB10_Pos

#define CAN_F9R2_FB10_Pos (10U)

◆ CAN_F9R2_FB11

#define CAN_F9R2_FB11 CAN_F9R2_FB11_Msk

Filter bit 11

◆ CAN_F9R2_FB11_Msk

#define CAN_F9R2_FB11_Msk (0x1UL << CAN_F9R2_FB11_Pos)

0x00000800

◆ CAN_F9R2_FB11_Pos

#define CAN_F9R2_FB11_Pos (11U)

◆ CAN_F9R2_FB12

#define CAN_F9R2_FB12 CAN_F9R2_FB12_Msk

Filter bit 12

◆ CAN_F9R2_FB12_Msk

#define CAN_F9R2_FB12_Msk (0x1UL << CAN_F9R2_FB12_Pos)

0x00001000

◆ CAN_F9R2_FB12_Pos

#define CAN_F9R2_FB12_Pos (12U)

◆ CAN_F9R2_FB13

#define CAN_F9R2_FB13 CAN_F9R2_FB13_Msk

Filter bit 13

◆ CAN_F9R2_FB13_Msk

#define CAN_F9R2_FB13_Msk (0x1UL << CAN_F9R2_FB13_Pos)

0x00002000

◆ CAN_F9R2_FB13_Pos

#define CAN_F9R2_FB13_Pos (13U)

◆ CAN_F9R2_FB14

#define CAN_F9R2_FB14 CAN_F9R2_FB14_Msk

Filter bit 14

◆ CAN_F9R2_FB14_Msk

#define CAN_F9R2_FB14_Msk (0x1UL << CAN_F9R2_FB14_Pos)

0x00004000

◆ CAN_F9R2_FB14_Pos

#define CAN_F9R2_FB14_Pos (14U)

◆ CAN_F9R2_FB15

#define CAN_F9R2_FB15 CAN_F9R2_FB15_Msk

Filter bit 15

◆ CAN_F9R2_FB15_Msk

#define CAN_F9R2_FB15_Msk (0x1UL << CAN_F9R2_FB15_Pos)

0x00008000

◆ CAN_F9R2_FB15_Pos

#define CAN_F9R2_FB15_Pos (15U)

◆ CAN_F9R2_FB16

#define CAN_F9R2_FB16 CAN_F9R2_FB16_Msk

Filter bit 16

◆ CAN_F9R2_FB16_Msk

#define CAN_F9R2_FB16_Msk (0x1UL << CAN_F9R2_FB16_Pos)

0x00010000

◆ CAN_F9R2_FB16_Pos

#define CAN_F9R2_FB16_Pos (16U)

◆ CAN_F9R2_FB17

#define CAN_F9R2_FB17 CAN_F9R2_FB17_Msk

Filter bit 17

◆ CAN_F9R2_FB17_Msk

#define CAN_F9R2_FB17_Msk (0x1UL << CAN_F9R2_FB17_Pos)

0x00020000

◆ CAN_F9R2_FB17_Pos

#define CAN_F9R2_FB17_Pos (17U)

◆ CAN_F9R2_FB18

#define CAN_F9R2_FB18 CAN_F9R2_FB18_Msk

Filter bit 18

◆ CAN_F9R2_FB18_Msk

#define CAN_F9R2_FB18_Msk (0x1UL << CAN_F9R2_FB18_Pos)

0x00040000

◆ CAN_F9R2_FB18_Pos

#define CAN_F9R2_FB18_Pos (18U)

◆ CAN_F9R2_FB19

#define CAN_F9R2_FB19 CAN_F9R2_FB19_Msk

Filter bit 19

◆ CAN_F9R2_FB19_Msk

#define CAN_F9R2_FB19_Msk (0x1UL << CAN_F9R2_FB19_Pos)

0x00080000

◆ CAN_F9R2_FB19_Pos

#define CAN_F9R2_FB19_Pos (19U)

◆ CAN_F9R2_FB1_Msk

#define CAN_F9R2_FB1_Msk (0x1UL << CAN_F9R2_FB1_Pos)

0x00000002

◆ CAN_F9R2_FB1_Pos

#define CAN_F9R2_FB1_Pos (1U)

◆ CAN_F9R2_FB2

#define CAN_F9R2_FB2 CAN_F9R2_FB2_Msk

Filter bit 2

◆ CAN_F9R2_FB20

#define CAN_F9R2_FB20 CAN_F9R2_FB20_Msk

Filter bit 20

◆ CAN_F9R2_FB20_Msk

#define CAN_F9R2_FB20_Msk (0x1UL << CAN_F9R2_FB20_Pos)

0x00100000

◆ CAN_F9R2_FB20_Pos

#define CAN_F9R2_FB20_Pos (20U)

◆ CAN_F9R2_FB21

#define CAN_F9R2_FB21 CAN_F9R2_FB21_Msk

Filter bit 21

◆ CAN_F9R2_FB21_Msk

#define CAN_F9R2_FB21_Msk (0x1UL << CAN_F9R2_FB21_Pos)

0x00200000

◆ CAN_F9R2_FB21_Pos

#define CAN_F9R2_FB21_Pos (21U)

◆ CAN_F9R2_FB22

#define CAN_F9R2_FB22 CAN_F9R2_FB22_Msk

Filter bit 22

◆ CAN_F9R2_FB22_Msk

#define CAN_F9R2_FB22_Msk (0x1UL << CAN_F9R2_FB22_Pos)

0x00400000

◆ CAN_F9R2_FB22_Pos

#define CAN_F9R2_FB22_Pos (22U)

◆ CAN_F9R2_FB23

#define CAN_F9R2_FB23 CAN_F9R2_FB23_Msk

Filter bit 23

◆ CAN_F9R2_FB23_Msk

#define CAN_F9R2_FB23_Msk (0x1UL << CAN_F9R2_FB23_Pos)

0x00800000

◆ CAN_F9R2_FB23_Pos

#define CAN_F9R2_FB23_Pos (23U)

◆ CAN_F9R2_FB24

#define CAN_F9R2_FB24 CAN_F9R2_FB24_Msk

Filter bit 24

◆ CAN_F9R2_FB24_Msk

#define CAN_F9R2_FB24_Msk (0x1UL << CAN_F9R2_FB24_Pos)

0x01000000

◆ CAN_F9R2_FB24_Pos

#define CAN_F9R2_FB24_Pos (24U)

◆ CAN_F9R2_FB25

#define CAN_F9R2_FB25 CAN_F9R2_FB25_Msk

Filter bit 25

◆ CAN_F9R2_FB25_Msk

#define CAN_F9R2_FB25_Msk (0x1UL << CAN_F9R2_FB25_Pos)

0x02000000

◆ CAN_F9R2_FB25_Pos

#define CAN_F9R2_FB25_Pos (25U)

◆ CAN_F9R2_FB26

#define CAN_F9R2_FB26 CAN_F9R2_FB26_Msk

Filter bit 26

◆ CAN_F9R2_FB26_Msk

#define CAN_F9R2_FB26_Msk (0x1UL << CAN_F9R2_FB26_Pos)

0x04000000

◆ CAN_F9R2_FB26_Pos

#define CAN_F9R2_FB26_Pos (26U)

◆ CAN_F9R2_FB27

#define CAN_F9R2_FB27 CAN_F9R2_FB27_Msk

Filter bit 27

◆ CAN_F9R2_FB27_Msk

#define CAN_F9R2_FB27_Msk (0x1UL << CAN_F9R2_FB27_Pos)

0x08000000

◆ CAN_F9R2_FB27_Pos

#define CAN_F9R2_FB27_Pos (27U)

◆ CAN_F9R2_FB28

#define CAN_F9R2_FB28 CAN_F9R2_FB28_Msk

Filter bit 28

◆ CAN_F9R2_FB28_Msk

#define CAN_F9R2_FB28_Msk (0x1UL << CAN_F9R2_FB28_Pos)

0x10000000

◆ CAN_F9R2_FB28_Pos

#define CAN_F9R2_FB28_Pos (28U)

◆ CAN_F9R2_FB29

#define CAN_F9R2_FB29 CAN_F9R2_FB29_Msk

Filter bit 29

◆ CAN_F9R2_FB29_Msk

#define CAN_F9R2_FB29_Msk (0x1UL << CAN_F9R2_FB29_Pos)

0x20000000

◆ CAN_F9R2_FB29_Pos

#define CAN_F9R2_FB29_Pos (29U)

◆ CAN_F9R2_FB2_Msk

#define CAN_F9R2_FB2_Msk (0x1UL << CAN_F9R2_FB2_Pos)

0x00000004

◆ CAN_F9R2_FB2_Pos

#define CAN_F9R2_FB2_Pos (2U)

◆ CAN_F9R2_FB3

#define CAN_F9R2_FB3 CAN_F9R2_FB3_Msk

Filter bit 3

◆ CAN_F9R2_FB30

#define CAN_F9R2_FB30 CAN_F9R2_FB30_Msk

Filter bit 30

◆ CAN_F9R2_FB30_Msk

#define CAN_F9R2_FB30_Msk (0x1UL << CAN_F9R2_FB30_Pos)

0x40000000

◆ CAN_F9R2_FB30_Pos

#define CAN_F9R2_FB30_Pos (30U)

◆ CAN_F9R2_FB31

#define CAN_F9R2_FB31 CAN_F9R2_FB31_Msk

Filter bit 31

◆ CAN_F9R2_FB31_Msk

#define CAN_F9R2_FB31_Msk (0x1UL << CAN_F9R2_FB31_Pos)

0x80000000

◆ CAN_F9R2_FB31_Pos

#define CAN_F9R2_FB31_Pos (31U)

◆ CAN_F9R2_FB3_Msk

#define CAN_F9R2_FB3_Msk (0x1UL << CAN_F9R2_FB3_Pos)

0x00000008

◆ CAN_F9R2_FB3_Pos

#define CAN_F9R2_FB3_Pos (3U)

◆ CAN_F9R2_FB4

#define CAN_F9R2_FB4 CAN_F9R2_FB4_Msk

Filter bit 4

◆ CAN_F9R2_FB4_Msk

#define CAN_F9R2_FB4_Msk (0x1UL << CAN_F9R2_FB4_Pos)

0x00000010

◆ CAN_F9R2_FB4_Pos

#define CAN_F9R2_FB4_Pos (4U)

◆ CAN_F9R2_FB5

#define CAN_F9R2_FB5 CAN_F9R2_FB5_Msk

Filter bit 5

◆ CAN_F9R2_FB5_Msk

#define CAN_F9R2_FB5_Msk (0x1UL << CAN_F9R2_FB5_Pos)

0x00000020

◆ CAN_F9R2_FB5_Pos

#define CAN_F9R2_FB5_Pos (5U)

◆ CAN_F9R2_FB6

#define CAN_F9R2_FB6 CAN_F9R2_FB6_Msk

Filter bit 6

◆ CAN_F9R2_FB6_Msk

#define CAN_F9R2_FB6_Msk (0x1UL << CAN_F9R2_FB6_Pos)

0x00000040

◆ CAN_F9R2_FB6_Pos

#define CAN_F9R2_FB6_Pos (6U)

◆ CAN_F9R2_FB7

#define CAN_F9R2_FB7 CAN_F9R2_FB7_Msk

Filter bit 7

◆ CAN_F9R2_FB7_Msk

#define CAN_F9R2_FB7_Msk (0x1UL << CAN_F9R2_FB7_Pos)

0x00000080

◆ CAN_F9R2_FB7_Pos

#define CAN_F9R2_FB7_Pos (7U)

◆ CAN_F9R2_FB8

#define CAN_F9R2_FB8 CAN_F9R2_FB8_Msk

Filter bit 8

◆ CAN_F9R2_FB8_Msk

#define CAN_F9R2_FB8_Msk (0x1UL << CAN_F9R2_FB8_Pos)

0x00000100

◆ CAN_F9R2_FB8_Pos

#define CAN_F9R2_FB8_Pos (8U)

◆ CAN_F9R2_FB9

#define CAN_F9R2_FB9 CAN_F9R2_FB9_Msk

Filter bit 9

◆ CAN_F9R2_FB9_Msk

#define CAN_F9R2_FB9_Msk (0x1UL << CAN_F9R2_FB9_Pos)

0x00000200

◆ CAN_F9R2_FB9_Pos

#define CAN_F9R2_FB9_Pos (9U)

◆ CAN_FA1R_FACT

#define CAN_FA1R_FACT CAN_FA1R_FACT_Msk

Filter Active

◆ CAN_FA1R_FACT0

#define CAN_FA1R_FACT0 CAN_FA1R_FACT0_Msk

Filter 0 Active

◆ CAN_FA1R_FACT0_Msk

#define CAN_FA1R_FACT0_Msk (0x1UL << CAN_FA1R_FACT0_Pos)

0x00000001

◆ CAN_FA1R_FACT0_Pos

#define CAN_FA1R_FACT0_Pos (0U)

◆ CAN_FA1R_FACT1

#define CAN_FA1R_FACT1 CAN_FA1R_FACT1_Msk

Filter 1 Active

◆ CAN_FA1R_FACT10

#define CAN_FA1R_FACT10 CAN_FA1R_FACT10_Msk

Filter 10 Active

◆ CAN_FA1R_FACT10_Msk

#define CAN_FA1R_FACT10_Msk (0x1UL << CAN_FA1R_FACT10_Pos)

0x00000400

◆ CAN_FA1R_FACT10_Pos

#define CAN_FA1R_FACT10_Pos (10U)

◆ CAN_FA1R_FACT11

#define CAN_FA1R_FACT11 CAN_FA1R_FACT11_Msk

Filter 11 Active

◆ CAN_FA1R_FACT11_Msk

#define CAN_FA1R_FACT11_Msk (0x1UL << CAN_FA1R_FACT11_Pos)

0x00000800

◆ CAN_FA1R_FACT11_Pos

#define CAN_FA1R_FACT11_Pos (11U)

◆ CAN_FA1R_FACT12

#define CAN_FA1R_FACT12 CAN_FA1R_FACT12_Msk

Filter 12 Active

◆ CAN_FA1R_FACT12_Msk

#define CAN_FA1R_FACT12_Msk (0x1UL << CAN_FA1R_FACT12_Pos)

0x00001000

◆ CAN_FA1R_FACT12_Pos

#define CAN_FA1R_FACT12_Pos (12U)

◆ CAN_FA1R_FACT13

#define CAN_FA1R_FACT13 CAN_FA1R_FACT13_Msk

Filter 13 Active

◆ CAN_FA1R_FACT13_Msk

#define CAN_FA1R_FACT13_Msk (0x1UL << CAN_FA1R_FACT13_Pos)

0x00002000

◆ CAN_FA1R_FACT13_Pos

#define CAN_FA1R_FACT13_Pos (13U)

◆ CAN_FA1R_FACT1_Msk

#define CAN_FA1R_FACT1_Msk (0x1UL << CAN_FA1R_FACT1_Pos)

0x00000002

◆ CAN_FA1R_FACT1_Pos

#define CAN_FA1R_FACT1_Pos (1U)

◆ CAN_FA1R_FACT2

#define CAN_FA1R_FACT2 CAN_FA1R_FACT2_Msk

Filter 2 Active

◆ CAN_FA1R_FACT2_Msk

#define CAN_FA1R_FACT2_Msk (0x1UL << CAN_FA1R_FACT2_Pos)

0x00000004

◆ CAN_FA1R_FACT2_Pos

#define CAN_FA1R_FACT2_Pos (2U)

◆ CAN_FA1R_FACT3

#define CAN_FA1R_FACT3 CAN_FA1R_FACT3_Msk

Filter 3 Active

◆ CAN_FA1R_FACT3_Msk

#define CAN_FA1R_FACT3_Msk (0x1UL << CAN_FA1R_FACT3_Pos)

0x00000008

◆ CAN_FA1R_FACT3_Pos

#define CAN_FA1R_FACT3_Pos (3U)

◆ CAN_FA1R_FACT4

#define CAN_FA1R_FACT4 CAN_FA1R_FACT4_Msk

Filter 4 Active

◆ CAN_FA1R_FACT4_Msk

#define CAN_FA1R_FACT4_Msk (0x1UL << CAN_FA1R_FACT4_Pos)

0x00000010

◆ CAN_FA1R_FACT4_Pos

#define CAN_FA1R_FACT4_Pos (4U)

◆ CAN_FA1R_FACT5

#define CAN_FA1R_FACT5 CAN_FA1R_FACT5_Msk

Filter 5 Active

◆ CAN_FA1R_FACT5_Msk

#define CAN_FA1R_FACT5_Msk (0x1UL << CAN_FA1R_FACT5_Pos)

0x00000020

◆ CAN_FA1R_FACT5_Pos

#define CAN_FA1R_FACT5_Pos (5U)

◆ CAN_FA1R_FACT6

#define CAN_FA1R_FACT6 CAN_FA1R_FACT6_Msk

Filter 6 Active

◆ CAN_FA1R_FACT6_Msk

#define CAN_FA1R_FACT6_Msk (0x1UL << CAN_FA1R_FACT6_Pos)

0x00000040

◆ CAN_FA1R_FACT6_Pos

#define CAN_FA1R_FACT6_Pos (6U)

◆ CAN_FA1R_FACT7

#define CAN_FA1R_FACT7 CAN_FA1R_FACT7_Msk

Filter 7 Active

◆ CAN_FA1R_FACT7_Msk

#define CAN_FA1R_FACT7_Msk (0x1UL << CAN_FA1R_FACT7_Pos)

0x00000080

◆ CAN_FA1R_FACT7_Pos

#define CAN_FA1R_FACT7_Pos (7U)

◆ CAN_FA1R_FACT8

#define CAN_FA1R_FACT8 CAN_FA1R_FACT8_Msk

Filter 8 Active

◆ CAN_FA1R_FACT8_Msk

#define CAN_FA1R_FACT8_Msk (0x1UL << CAN_FA1R_FACT8_Pos)

0x00000100

◆ CAN_FA1R_FACT8_Pos

#define CAN_FA1R_FACT8_Pos (8U)

◆ CAN_FA1R_FACT9

#define CAN_FA1R_FACT9 CAN_FA1R_FACT9_Msk

Filter 9 Active

◆ CAN_FA1R_FACT9_Msk

#define CAN_FA1R_FACT9_Msk (0x1UL << CAN_FA1R_FACT9_Pos)

0x00000200

◆ CAN_FA1R_FACT9_Pos

#define CAN_FA1R_FACT9_Pos (9U)

◆ CAN_FA1R_FACT_Msk

#define CAN_FA1R_FACT_Msk (0x3FFFUL << CAN_FA1R_FACT_Pos)

0x00003FFF

◆ CAN_FA1R_FACT_Pos

#define CAN_FA1R_FACT_Pos (0U)

◆ CAN_FFA1R_FFA

#define CAN_FFA1R_FFA CAN_FFA1R_FFA_Msk

Filter FIFO Assignment

◆ CAN_FFA1R_FFA0

#define CAN_FFA1R_FFA0 CAN_FFA1R_FFA0_Msk

Filter FIFO Assignment for Filter 0

◆ CAN_FFA1R_FFA0_Msk

#define CAN_FFA1R_FFA0_Msk (0x1UL << CAN_FFA1R_FFA0_Pos)

0x00000001

◆ CAN_FFA1R_FFA0_Pos

#define CAN_FFA1R_FFA0_Pos (0U)

◆ CAN_FFA1R_FFA1

#define CAN_FFA1R_FFA1 CAN_FFA1R_FFA1_Msk

Filter FIFO Assignment for Filter 1

◆ CAN_FFA1R_FFA10

#define CAN_FFA1R_FFA10 CAN_FFA1R_FFA10_Msk

Filter FIFO Assignment for Filter 10

◆ CAN_FFA1R_FFA10_Msk

#define CAN_FFA1R_FFA10_Msk (0x1UL << CAN_FFA1R_FFA10_Pos)

0x00000400

◆ CAN_FFA1R_FFA10_Pos

#define CAN_FFA1R_FFA10_Pos (10U)

◆ CAN_FFA1R_FFA11

#define CAN_FFA1R_FFA11 CAN_FFA1R_FFA11_Msk

Filter FIFO Assignment for Filter 11

◆ CAN_FFA1R_FFA11_Msk

#define CAN_FFA1R_FFA11_Msk (0x1UL << CAN_FFA1R_FFA11_Pos)

0x00000800

◆ CAN_FFA1R_FFA11_Pos

#define CAN_FFA1R_FFA11_Pos (11U)

◆ CAN_FFA1R_FFA12

#define CAN_FFA1R_FFA12 CAN_FFA1R_FFA12_Msk

Filter FIFO Assignment for Filter 12

◆ CAN_FFA1R_FFA12_Msk

#define CAN_FFA1R_FFA12_Msk (0x1UL << CAN_FFA1R_FFA12_Pos)

0x00001000

◆ CAN_FFA1R_FFA12_Pos

#define CAN_FFA1R_FFA12_Pos (12U)

◆ CAN_FFA1R_FFA13

#define CAN_FFA1R_FFA13 CAN_FFA1R_FFA13_Msk

Filter FIFO Assignment for Filter 13

◆ CAN_FFA1R_FFA13_Msk

#define CAN_FFA1R_FFA13_Msk (0x1UL << CAN_FFA1R_FFA13_Pos)

0x00002000

◆ CAN_FFA1R_FFA13_Pos

#define CAN_FFA1R_FFA13_Pos (13U)

◆ CAN_FFA1R_FFA1_Msk

#define CAN_FFA1R_FFA1_Msk (0x1UL << CAN_FFA1R_FFA1_Pos)

0x00000002

◆ CAN_FFA1R_FFA1_Pos

#define CAN_FFA1R_FFA1_Pos (1U)

◆ CAN_FFA1R_FFA2

#define CAN_FFA1R_FFA2 CAN_FFA1R_FFA2_Msk

Filter FIFO Assignment for Filter 2

◆ CAN_FFA1R_FFA2_Msk

#define CAN_FFA1R_FFA2_Msk (0x1UL << CAN_FFA1R_FFA2_Pos)

0x00000004

◆ CAN_FFA1R_FFA2_Pos

#define CAN_FFA1R_FFA2_Pos (2U)

◆ CAN_FFA1R_FFA3

#define CAN_FFA1R_FFA3 CAN_FFA1R_FFA3_Msk

Filter FIFO Assignment for Filter 3

◆ CAN_FFA1R_FFA3_Msk

#define CAN_FFA1R_FFA3_Msk (0x1UL << CAN_FFA1R_FFA3_Pos)

0x00000008

◆ CAN_FFA1R_FFA3_Pos

#define CAN_FFA1R_FFA3_Pos (3U)

◆ CAN_FFA1R_FFA4

#define CAN_FFA1R_FFA4 CAN_FFA1R_FFA4_Msk

Filter FIFO Assignment for Filter 4

◆ CAN_FFA1R_FFA4_Msk

#define CAN_FFA1R_FFA4_Msk (0x1UL << CAN_FFA1R_FFA4_Pos)

0x00000010

◆ CAN_FFA1R_FFA4_Pos

#define CAN_FFA1R_FFA4_Pos (4U)

◆ CAN_FFA1R_FFA5

#define CAN_FFA1R_FFA5 CAN_FFA1R_FFA5_Msk

Filter FIFO Assignment for Filter 5

◆ CAN_FFA1R_FFA5_Msk

#define CAN_FFA1R_FFA5_Msk (0x1UL << CAN_FFA1R_FFA5_Pos)

0x00000020

◆ CAN_FFA1R_FFA5_Pos

#define CAN_FFA1R_FFA5_Pos (5U)

◆ CAN_FFA1R_FFA6

#define CAN_FFA1R_FFA6 CAN_FFA1R_FFA6_Msk

Filter FIFO Assignment for Filter 6

◆ CAN_FFA1R_FFA6_Msk

#define CAN_FFA1R_FFA6_Msk (0x1UL << CAN_FFA1R_FFA6_Pos)

0x00000040

◆ CAN_FFA1R_FFA6_Pos

#define CAN_FFA1R_FFA6_Pos (6U)

◆ CAN_FFA1R_FFA7

#define CAN_FFA1R_FFA7 CAN_FFA1R_FFA7_Msk

Filter FIFO Assignment for Filter 7

◆ CAN_FFA1R_FFA7_Msk

#define CAN_FFA1R_FFA7_Msk (0x1UL << CAN_FFA1R_FFA7_Pos)

0x00000080

◆ CAN_FFA1R_FFA7_Pos

#define CAN_FFA1R_FFA7_Pos (7U)

◆ CAN_FFA1R_FFA8

#define CAN_FFA1R_FFA8 CAN_FFA1R_FFA8_Msk

Filter FIFO Assignment for Filter 8

◆ CAN_FFA1R_FFA8_Msk

#define CAN_FFA1R_FFA8_Msk (0x1UL << CAN_FFA1R_FFA8_Pos)

0x00000100

◆ CAN_FFA1R_FFA8_Pos

#define CAN_FFA1R_FFA8_Pos (8U)

◆ CAN_FFA1R_FFA9

#define CAN_FFA1R_FFA9 CAN_FFA1R_FFA9_Msk

Filter FIFO Assignment for Filter 9

◆ CAN_FFA1R_FFA9_Msk

#define CAN_FFA1R_FFA9_Msk (0x1UL << CAN_FFA1R_FFA9_Pos)

0x00000200

◆ CAN_FFA1R_FFA9_Pos

#define CAN_FFA1R_FFA9_Pos (9U)

◆ CAN_FFA1R_FFA_Msk

#define CAN_FFA1R_FFA_Msk (0x3FFFUL << CAN_FFA1R_FFA_Pos)

0x00003FFF

◆ CAN_FFA1R_FFA_Pos

#define CAN_FFA1R_FFA_Pos (0U)

◆ CAN_FM1R_FBM

#define CAN_FM1R_FBM CAN_FM1R_FBM_Msk

Filter Mode

◆ CAN_FM1R_FBM0

#define CAN_FM1R_FBM0 CAN_FM1R_FBM0_Msk

Filter Init Mode bit 0

◆ CAN_FM1R_FBM0_Msk

#define CAN_FM1R_FBM0_Msk (0x1UL << CAN_FM1R_FBM0_Pos)

0x00000001

◆ CAN_FM1R_FBM0_Pos

#define CAN_FM1R_FBM0_Pos (0U)

◆ CAN_FM1R_FBM1

#define CAN_FM1R_FBM1 CAN_FM1R_FBM1_Msk

Filter Init Mode bit 1

◆ CAN_FM1R_FBM10

#define CAN_FM1R_FBM10 CAN_FM1R_FBM10_Msk

Filter Init Mode bit 10

◆ CAN_FM1R_FBM10_Msk

#define CAN_FM1R_FBM10_Msk (0x1UL << CAN_FM1R_FBM10_Pos)

0x00000400

◆ CAN_FM1R_FBM10_Pos

#define CAN_FM1R_FBM10_Pos (10U)

◆ CAN_FM1R_FBM11

#define CAN_FM1R_FBM11 CAN_FM1R_FBM11_Msk

Filter Init Mode bit 11

◆ CAN_FM1R_FBM11_Msk

#define CAN_FM1R_FBM11_Msk (0x1UL << CAN_FM1R_FBM11_Pos)

0x00000800

◆ CAN_FM1R_FBM11_Pos

#define CAN_FM1R_FBM11_Pos (11U)

◆ CAN_FM1R_FBM12

#define CAN_FM1R_FBM12 CAN_FM1R_FBM12_Msk

Filter Init Mode bit 12

◆ CAN_FM1R_FBM12_Msk

#define CAN_FM1R_FBM12_Msk (0x1UL << CAN_FM1R_FBM12_Pos)

0x00001000

◆ CAN_FM1R_FBM12_Pos

#define CAN_FM1R_FBM12_Pos (12U)

◆ CAN_FM1R_FBM13

#define CAN_FM1R_FBM13 CAN_FM1R_FBM13_Msk

Filter Init Mode bit 13

◆ CAN_FM1R_FBM13_Msk

#define CAN_FM1R_FBM13_Msk (0x1UL << CAN_FM1R_FBM13_Pos)

0x00002000

◆ CAN_FM1R_FBM13_Pos

#define CAN_FM1R_FBM13_Pos (13U)

◆ CAN_FM1R_FBM1_Msk

#define CAN_FM1R_FBM1_Msk (0x1UL << CAN_FM1R_FBM1_Pos)

0x00000002

◆ CAN_FM1R_FBM1_Pos

#define CAN_FM1R_FBM1_Pos (1U)

◆ CAN_FM1R_FBM2

#define CAN_FM1R_FBM2 CAN_FM1R_FBM2_Msk

Filter Init Mode bit 2

◆ CAN_FM1R_FBM2_Msk

#define CAN_FM1R_FBM2_Msk (0x1UL << CAN_FM1R_FBM2_Pos)

0x00000004

◆ CAN_FM1R_FBM2_Pos

#define CAN_FM1R_FBM2_Pos (2U)

◆ CAN_FM1R_FBM3

#define CAN_FM1R_FBM3 CAN_FM1R_FBM3_Msk

Filter Init Mode bit 3

◆ CAN_FM1R_FBM3_Msk

#define CAN_FM1R_FBM3_Msk (0x1UL << CAN_FM1R_FBM3_Pos)

0x00000008

◆ CAN_FM1R_FBM3_Pos

#define CAN_FM1R_FBM3_Pos (3U)

◆ CAN_FM1R_FBM4

#define CAN_FM1R_FBM4 CAN_FM1R_FBM4_Msk

Filter Init Mode bit 4

◆ CAN_FM1R_FBM4_Msk

#define CAN_FM1R_FBM4_Msk (0x1UL << CAN_FM1R_FBM4_Pos)

0x00000010

◆ CAN_FM1R_FBM4_Pos

#define CAN_FM1R_FBM4_Pos (4U)

◆ CAN_FM1R_FBM5

#define CAN_FM1R_FBM5 CAN_FM1R_FBM5_Msk

Filter Init Mode bit 5

◆ CAN_FM1R_FBM5_Msk

#define CAN_FM1R_FBM5_Msk (0x1UL << CAN_FM1R_FBM5_Pos)

0x00000020

◆ CAN_FM1R_FBM5_Pos

#define CAN_FM1R_FBM5_Pos (5U)

◆ CAN_FM1R_FBM6

#define CAN_FM1R_FBM6 CAN_FM1R_FBM6_Msk

Filter Init Mode bit 6

◆ CAN_FM1R_FBM6_Msk

#define CAN_FM1R_FBM6_Msk (0x1UL << CAN_FM1R_FBM6_Pos)

0x00000040

◆ CAN_FM1R_FBM6_Pos

#define CAN_FM1R_FBM6_Pos (6U)

◆ CAN_FM1R_FBM7

#define CAN_FM1R_FBM7 CAN_FM1R_FBM7_Msk

Filter Init Mode bit 7

◆ CAN_FM1R_FBM7_Msk

#define CAN_FM1R_FBM7_Msk (0x1UL << CAN_FM1R_FBM7_Pos)

0x00000080

◆ CAN_FM1R_FBM7_Pos

#define CAN_FM1R_FBM7_Pos (7U)

◆ CAN_FM1R_FBM8

#define CAN_FM1R_FBM8 CAN_FM1R_FBM8_Msk

Filter Init Mode bit 8

◆ CAN_FM1R_FBM8_Msk

#define CAN_FM1R_FBM8_Msk (0x1UL << CAN_FM1R_FBM8_Pos)

0x00000100

◆ CAN_FM1R_FBM8_Pos

#define CAN_FM1R_FBM8_Pos (8U)

◆ CAN_FM1R_FBM9

#define CAN_FM1R_FBM9 CAN_FM1R_FBM9_Msk

Filter Init Mode bit 9

◆ CAN_FM1R_FBM9_Msk

#define CAN_FM1R_FBM9_Msk (0x1UL << CAN_FM1R_FBM9_Pos)

0x00000200

◆ CAN_FM1R_FBM9_Pos

#define CAN_FM1R_FBM9_Pos (9U)

◆ CAN_FM1R_FBM_Msk

#define CAN_FM1R_FBM_Msk (0x3FFFUL << CAN_FM1R_FBM_Pos)

0x00003FFF

◆ CAN_FM1R_FBM_Pos

#define CAN_FM1R_FBM_Pos (0U)

◆ CAN_FMR_FINIT

#define CAN_FMR_FINIT CAN_FMR_FINIT_Msk

Filter Init Mode

◆ CAN_FMR_FINIT_Msk

#define CAN_FMR_FINIT_Msk (0x1UL << CAN_FMR_FINIT_Pos)

0x00000001

◆ CAN_FMR_FINIT_Pos

#define CAN_FMR_FINIT_Pos (0U)

◆ CAN_FS1R_FSC

#define CAN_FS1R_FSC CAN_FS1R_FSC_Msk

Filter Scale Configuration

◆ CAN_FS1R_FSC0

#define CAN_FS1R_FSC0 CAN_FS1R_FSC0_Msk

Filter Scale Configuration bit 0

◆ CAN_FS1R_FSC0_Msk

#define CAN_FS1R_FSC0_Msk (0x1UL << CAN_FS1R_FSC0_Pos)

0x00000001

◆ CAN_FS1R_FSC0_Pos

#define CAN_FS1R_FSC0_Pos (0U)

◆ CAN_FS1R_FSC1

#define CAN_FS1R_FSC1 CAN_FS1R_FSC1_Msk

Filter Scale Configuration bit 1

◆ CAN_FS1R_FSC10

#define CAN_FS1R_FSC10 CAN_FS1R_FSC10_Msk

Filter Scale Configuration bit 10

◆ CAN_FS1R_FSC10_Msk

#define CAN_FS1R_FSC10_Msk (0x1UL << CAN_FS1R_FSC10_Pos)

0x00000400

◆ CAN_FS1R_FSC10_Pos

#define CAN_FS1R_FSC10_Pos (10U)

◆ CAN_FS1R_FSC11

#define CAN_FS1R_FSC11 CAN_FS1R_FSC11_Msk

Filter Scale Configuration bit 11

◆ CAN_FS1R_FSC11_Msk

#define CAN_FS1R_FSC11_Msk (0x1UL << CAN_FS1R_FSC11_Pos)

0x00000800

◆ CAN_FS1R_FSC11_Pos

#define CAN_FS1R_FSC11_Pos (11U)

◆ CAN_FS1R_FSC12

#define CAN_FS1R_FSC12 CAN_FS1R_FSC12_Msk

Filter Scale Configuration bit 12

◆ CAN_FS1R_FSC12_Msk

#define CAN_FS1R_FSC12_Msk (0x1UL << CAN_FS1R_FSC12_Pos)

0x00001000

◆ CAN_FS1R_FSC12_Pos

#define CAN_FS1R_FSC12_Pos (12U)

◆ CAN_FS1R_FSC13

#define CAN_FS1R_FSC13 CAN_FS1R_FSC13_Msk

Filter Scale Configuration bit 13

◆ CAN_FS1R_FSC13_Msk

#define CAN_FS1R_FSC13_Msk (0x1UL << CAN_FS1R_FSC13_Pos)

0x00002000

◆ CAN_FS1R_FSC13_Pos

#define CAN_FS1R_FSC13_Pos (13U)

◆ CAN_FS1R_FSC1_Msk

#define CAN_FS1R_FSC1_Msk (0x1UL << CAN_FS1R_FSC1_Pos)

0x00000002

◆ CAN_FS1R_FSC1_Pos

#define CAN_FS1R_FSC1_Pos (1U)

◆ CAN_FS1R_FSC2

#define CAN_FS1R_FSC2 CAN_FS1R_FSC2_Msk

Filter Scale Configuration bit 2

◆ CAN_FS1R_FSC2_Msk

#define CAN_FS1R_FSC2_Msk (0x1UL << CAN_FS1R_FSC2_Pos)

0x00000004

◆ CAN_FS1R_FSC2_Pos

#define CAN_FS1R_FSC2_Pos (2U)

◆ CAN_FS1R_FSC3

#define CAN_FS1R_FSC3 CAN_FS1R_FSC3_Msk

Filter Scale Configuration bit 3

◆ CAN_FS1R_FSC3_Msk

#define CAN_FS1R_FSC3_Msk (0x1UL << CAN_FS1R_FSC3_Pos)

0x00000008

◆ CAN_FS1R_FSC3_Pos

#define CAN_FS1R_FSC3_Pos (3U)

◆ CAN_FS1R_FSC4

#define CAN_FS1R_FSC4 CAN_FS1R_FSC4_Msk

Filter Scale Configuration bit 4

◆ CAN_FS1R_FSC4_Msk

#define CAN_FS1R_FSC4_Msk (0x1UL << CAN_FS1R_FSC4_Pos)

0x00000010

◆ CAN_FS1R_FSC4_Pos

#define CAN_FS1R_FSC4_Pos (4U)

◆ CAN_FS1R_FSC5

#define CAN_FS1R_FSC5 CAN_FS1R_FSC5_Msk

Filter Scale Configuration bit 5

◆ CAN_FS1R_FSC5_Msk

#define CAN_FS1R_FSC5_Msk (0x1UL << CAN_FS1R_FSC5_Pos)

0x00000020

◆ CAN_FS1R_FSC5_Pos

#define CAN_FS1R_FSC5_Pos (5U)

◆ CAN_FS1R_FSC6

#define CAN_FS1R_FSC6 CAN_FS1R_FSC6_Msk

Filter Scale Configuration bit 6

◆ CAN_FS1R_FSC6_Msk

#define CAN_FS1R_FSC6_Msk (0x1UL << CAN_FS1R_FSC6_Pos)

0x00000040

◆ CAN_FS1R_FSC6_Pos

#define CAN_FS1R_FSC6_Pos (6U)

◆ CAN_FS1R_FSC7

#define CAN_FS1R_FSC7 CAN_FS1R_FSC7_Msk

Filter Scale Configuration bit 7

◆ CAN_FS1R_FSC7_Msk

#define CAN_FS1R_FSC7_Msk (0x1UL << CAN_FS1R_FSC7_Pos)

0x00000080

◆ CAN_FS1R_FSC7_Pos

#define CAN_FS1R_FSC7_Pos (7U)

◆ CAN_FS1R_FSC8

#define CAN_FS1R_FSC8 CAN_FS1R_FSC8_Msk

Filter Scale Configuration bit 8

◆ CAN_FS1R_FSC8_Msk

#define CAN_FS1R_FSC8_Msk (0x1UL << CAN_FS1R_FSC8_Pos)

0x00000100

◆ CAN_FS1R_FSC8_Pos

#define CAN_FS1R_FSC8_Pos (8U)

◆ CAN_FS1R_FSC9

#define CAN_FS1R_FSC9 CAN_FS1R_FSC9_Msk

Filter Scale Configuration bit 9

◆ CAN_FS1R_FSC9_Msk

#define CAN_FS1R_FSC9_Msk (0x1UL << CAN_FS1R_FSC9_Pos)

0x00000200

◆ CAN_FS1R_FSC9_Pos

#define CAN_FS1R_FSC9_Pos (9U)

◆ CAN_FS1R_FSC_Msk

#define CAN_FS1R_FSC_Msk (0x3FFFUL << CAN_FS1R_FSC_Pos)

0x00003FFF

◆ CAN_FS1R_FSC_Pos

#define CAN_FS1R_FSC_Pos (0U)

◆ CAN_IER_BOFIE

#define CAN_IER_BOFIE CAN_IER_BOFIE_Msk

Bus-Off Interrupt Enable

◆ CAN_IER_BOFIE_Msk

#define CAN_IER_BOFIE_Msk (0x1UL << CAN_IER_BOFIE_Pos)

0x00000400

◆ CAN_IER_BOFIE_Pos

#define CAN_IER_BOFIE_Pos (10U)

◆ CAN_IER_EPVIE

#define CAN_IER_EPVIE CAN_IER_EPVIE_Msk

Error Passive Interrupt Enable

◆ CAN_IER_EPVIE_Msk

#define CAN_IER_EPVIE_Msk (0x1UL << CAN_IER_EPVIE_Pos)

0x00000200

◆ CAN_IER_EPVIE_Pos

#define CAN_IER_EPVIE_Pos (9U)

◆ CAN_IER_ERRIE

#define CAN_IER_ERRIE CAN_IER_ERRIE_Msk

Error Interrupt Enable

◆ CAN_IER_ERRIE_Msk

#define CAN_IER_ERRIE_Msk (0x1UL << CAN_IER_ERRIE_Pos)

0x00008000

◆ CAN_IER_ERRIE_Pos

#define CAN_IER_ERRIE_Pos (15U)

◆ CAN_IER_EWGIE

#define CAN_IER_EWGIE CAN_IER_EWGIE_Msk

Error Warning Interrupt Enable

◆ CAN_IER_EWGIE_Msk

#define CAN_IER_EWGIE_Msk (0x1UL << CAN_IER_EWGIE_Pos)

0x00000100

◆ CAN_IER_EWGIE_Pos

#define CAN_IER_EWGIE_Pos (8U)

◆ CAN_IER_FFIE0

#define CAN_IER_FFIE0 CAN_IER_FFIE0_Msk

FIFO Full Interrupt Enable

◆ CAN_IER_FFIE0_Msk

#define CAN_IER_FFIE0_Msk (0x1UL << CAN_IER_FFIE0_Pos)

0x00000004

◆ CAN_IER_FFIE0_Pos

#define CAN_IER_FFIE0_Pos (2U)

◆ CAN_IER_FFIE1

#define CAN_IER_FFIE1 CAN_IER_FFIE1_Msk

FIFO Full Interrupt Enable

◆ CAN_IER_FFIE1_Msk

#define CAN_IER_FFIE1_Msk (0x1UL << CAN_IER_FFIE1_Pos)

0x00000020

◆ CAN_IER_FFIE1_Pos

#define CAN_IER_FFIE1_Pos (5U)

◆ CAN_IER_FMPIE0

#define CAN_IER_FMPIE0 CAN_IER_FMPIE0_Msk

FIFO Message Pending Interrupt Enable

◆ CAN_IER_FMPIE0_Msk

#define CAN_IER_FMPIE0_Msk (0x1UL << CAN_IER_FMPIE0_Pos)

0x00000002

◆ CAN_IER_FMPIE0_Pos

#define CAN_IER_FMPIE0_Pos (1U)

◆ CAN_IER_FMPIE1

#define CAN_IER_FMPIE1 CAN_IER_FMPIE1_Msk

FIFO Message Pending Interrupt Enable

◆ CAN_IER_FMPIE1_Msk

#define CAN_IER_FMPIE1_Msk (0x1UL << CAN_IER_FMPIE1_Pos)

0x00000010

◆ CAN_IER_FMPIE1_Pos

#define CAN_IER_FMPIE1_Pos (4U)

◆ CAN_IER_FOVIE0

#define CAN_IER_FOVIE0 CAN_IER_FOVIE0_Msk

FIFO Overrun Interrupt Enable

◆ CAN_IER_FOVIE0_Msk

#define CAN_IER_FOVIE0_Msk (0x1UL << CAN_IER_FOVIE0_Pos)

0x00000008

◆ CAN_IER_FOVIE0_Pos

#define CAN_IER_FOVIE0_Pos (3U)

◆ CAN_IER_FOVIE1

#define CAN_IER_FOVIE1 CAN_IER_FOVIE1_Msk

FIFO Overrun Interrupt Enable

◆ CAN_IER_FOVIE1_Msk

#define CAN_IER_FOVIE1_Msk (0x1UL << CAN_IER_FOVIE1_Pos)

0x00000040

◆ CAN_IER_FOVIE1_Pos

#define CAN_IER_FOVIE1_Pos (6U)

◆ CAN_IER_LECIE

#define CAN_IER_LECIE CAN_IER_LECIE_Msk

Last Error Code Interrupt Enable

◆ CAN_IER_LECIE_Msk

#define CAN_IER_LECIE_Msk (0x1UL << CAN_IER_LECIE_Pos)

0x00000800

◆ CAN_IER_LECIE_Pos

#define CAN_IER_LECIE_Pos (11U)

◆ CAN_IER_SLKIE

#define CAN_IER_SLKIE CAN_IER_SLKIE_Msk

Sleep Interrupt Enable

◆ CAN_IER_SLKIE_Msk

#define CAN_IER_SLKIE_Msk (0x1UL << CAN_IER_SLKIE_Pos)

0x00020000

◆ CAN_IER_SLKIE_Pos

#define CAN_IER_SLKIE_Pos (17U)

◆ CAN_IER_TMEIE

#define CAN_IER_TMEIE CAN_IER_TMEIE_Msk

Transmit Mailbox Empty Interrupt Enable

◆ CAN_IER_TMEIE_Msk

#define CAN_IER_TMEIE_Msk (0x1UL << CAN_IER_TMEIE_Pos)

0x00000001

◆ CAN_IER_TMEIE_Pos

#define CAN_IER_TMEIE_Pos (0U)

◆ CAN_IER_WKUIE

#define CAN_IER_WKUIE CAN_IER_WKUIE_Msk

Wakeup Interrupt Enable

◆ CAN_IER_WKUIE_Msk

#define CAN_IER_WKUIE_Msk (0x1UL << CAN_IER_WKUIE_Pos)

0x00010000

◆ CAN_IER_WKUIE_Pos

#define CAN_IER_WKUIE_Pos (16U)

◆ CAN_MCR_ABOM

#define CAN_MCR_ABOM CAN_MCR_ABOM_Msk

Automatic Bus-Off Management

◆ CAN_MCR_ABOM_Msk

#define CAN_MCR_ABOM_Msk (0x1UL << CAN_MCR_ABOM_Pos)

0x00000040

◆ CAN_MCR_ABOM_Pos

#define CAN_MCR_ABOM_Pos (6U)

◆ CAN_MCR_AWUM

#define CAN_MCR_AWUM CAN_MCR_AWUM_Msk

Automatic Wakeup Mode

◆ CAN_MCR_AWUM_Msk

#define CAN_MCR_AWUM_Msk (0x1UL << CAN_MCR_AWUM_Pos)

0x00000020

◆ CAN_MCR_AWUM_Pos

#define CAN_MCR_AWUM_Pos (5U)

◆ CAN_MCR_INRQ

#define CAN_MCR_INRQ CAN_MCR_INRQ_Msk

Initialization Request

◆ CAN_MCR_INRQ_Msk

#define CAN_MCR_INRQ_Msk (0x1UL << CAN_MCR_INRQ_Pos)

0x00000001

◆ CAN_MCR_INRQ_Pos

#define CAN_MCR_INRQ_Pos (0U)

◆ CAN_MCR_NART

#define CAN_MCR_NART CAN_MCR_NART_Msk

No Automatic Retransmission

◆ CAN_MCR_NART_Msk

#define CAN_MCR_NART_Msk (0x1UL << CAN_MCR_NART_Pos)

0x00000010

◆ CAN_MCR_NART_Pos

#define CAN_MCR_NART_Pos (4U)

◆ CAN_MCR_RESET

#define CAN_MCR_RESET CAN_MCR_RESET_Msk

bxCAN software master reset

◆ CAN_MCR_RESET_Msk

#define CAN_MCR_RESET_Msk (0x1UL << CAN_MCR_RESET_Pos)

0x00008000

◆ CAN_MCR_RESET_Pos

#define CAN_MCR_RESET_Pos (15U)

◆ CAN_MCR_RFLM

#define CAN_MCR_RFLM CAN_MCR_RFLM_Msk

Receive FIFO Locked Mode

◆ CAN_MCR_RFLM_Msk

#define CAN_MCR_RFLM_Msk (0x1UL << CAN_MCR_RFLM_Pos)

0x00000008

◆ CAN_MCR_RFLM_Pos

#define CAN_MCR_RFLM_Pos (3U)

◆ CAN_MCR_SLEEP

#define CAN_MCR_SLEEP CAN_MCR_SLEEP_Msk

Sleep Mode Request

◆ CAN_MCR_SLEEP_Msk

#define CAN_MCR_SLEEP_Msk (0x1UL << CAN_MCR_SLEEP_Pos)

0x00000002

◆ CAN_MCR_SLEEP_Pos

#define CAN_MCR_SLEEP_Pos (1U)

◆ CAN_MCR_TTCM

#define CAN_MCR_TTCM CAN_MCR_TTCM_Msk

Time Triggered Communication Mode

◆ CAN_MCR_TTCM_Msk

#define CAN_MCR_TTCM_Msk (0x1UL << CAN_MCR_TTCM_Pos)

0x00000080

◆ CAN_MCR_TTCM_Pos

#define CAN_MCR_TTCM_Pos (7U)

◆ CAN_MCR_TXFP

#define CAN_MCR_TXFP CAN_MCR_TXFP_Msk

Transmit FIFO Priority

◆ CAN_MCR_TXFP_Msk

#define CAN_MCR_TXFP_Msk (0x1UL << CAN_MCR_TXFP_Pos)

0x00000004

◆ CAN_MCR_TXFP_Pos

#define CAN_MCR_TXFP_Pos (2U)

◆ CAN_MSR_ERRI

#define CAN_MSR_ERRI CAN_MSR_ERRI_Msk

Error Interrupt

◆ CAN_MSR_ERRI_Msk

#define CAN_MSR_ERRI_Msk (0x1UL << CAN_MSR_ERRI_Pos)

0x00000004

◆ CAN_MSR_ERRI_Pos

#define CAN_MSR_ERRI_Pos (2U)

◆ CAN_MSR_INAK

#define CAN_MSR_INAK CAN_MSR_INAK_Msk

Initialization Acknowledge

◆ CAN_MSR_INAK_Msk

#define CAN_MSR_INAK_Msk (0x1UL << CAN_MSR_INAK_Pos)

0x00000001

◆ CAN_MSR_INAK_Pos

#define CAN_MSR_INAK_Pos (0U)

◆ CAN_MSR_RX

#define CAN_MSR_RX CAN_MSR_RX_Msk

CAN Rx Signal

◆ CAN_MSR_RX_Msk

#define CAN_MSR_RX_Msk (0x1UL << CAN_MSR_RX_Pos)

0x00000800

◆ CAN_MSR_RX_Pos

#define CAN_MSR_RX_Pos (11U)

◆ CAN_MSR_RXM

#define CAN_MSR_RXM CAN_MSR_RXM_Msk

Receive Mode

◆ CAN_MSR_RXM_Msk

#define CAN_MSR_RXM_Msk (0x1UL << CAN_MSR_RXM_Pos)

0x00000200

◆ CAN_MSR_RXM_Pos

#define CAN_MSR_RXM_Pos (9U)

◆ CAN_MSR_SAMP

#define CAN_MSR_SAMP CAN_MSR_SAMP_Msk

Last Sample Point

◆ CAN_MSR_SAMP_Msk

#define CAN_MSR_SAMP_Msk (0x1UL << CAN_MSR_SAMP_Pos)

0x00000400

◆ CAN_MSR_SAMP_Pos

#define CAN_MSR_SAMP_Pos (10U)

◆ CAN_MSR_SLAK

#define CAN_MSR_SLAK CAN_MSR_SLAK_Msk

Sleep Acknowledge

◆ CAN_MSR_SLAK_Msk

#define CAN_MSR_SLAK_Msk (0x1UL << CAN_MSR_SLAK_Pos)

0x00000002

◆ CAN_MSR_SLAK_Pos

#define CAN_MSR_SLAK_Pos (1U)

◆ CAN_MSR_SLAKI

#define CAN_MSR_SLAKI CAN_MSR_SLAKI_Msk

Sleep Acknowledge Interrupt

◆ CAN_MSR_SLAKI_Msk

#define CAN_MSR_SLAKI_Msk (0x1UL << CAN_MSR_SLAKI_Pos)

0x00000010

◆ CAN_MSR_SLAKI_Pos

#define CAN_MSR_SLAKI_Pos (4U)

◆ CAN_MSR_TXM

#define CAN_MSR_TXM CAN_MSR_TXM_Msk

Transmit Mode

◆ CAN_MSR_TXM_Msk

#define CAN_MSR_TXM_Msk (0x1UL << CAN_MSR_TXM_Pos)

0x00000100

◆ CAN_MSR_TXM_Pos

#define CAN_MSR_TXM_Pos (8U)

◆ CAN_MSR_WKUI

#define CAN_MSR_WKUI CAN_MSR_WKUI_Msk

Wakeup Interrupt

◆ CAN_MSR_WKUI_Msk

#define CAN_MSR_WKUI_Msk (0x1UL << CAN_MSR_WKUI_Pos)

0x00000008

◆ CAN_MSR_WKUI_Pos

#define CAN_MSR_WKUI_Pos (3U)

◆ CAN_RDH0R_DATA4

#define CAN_RDH0R_DATA4 CAN_RDH0R_DATA4_Msk

Data byte 4

◆ CAN_RDH0R_DATA4_Msk

#define CAN_RDH0R_DATA4_Msk (0xFFUL << CAN_RDH0R_DATA4_Pos)

0x000000FF

◆ CAN_RDH0R_DATA4_Pos

#define CAN_RDH0R_DATA4_Pos (0U)

◆ CAN_RDH0R_DATA5

#define CAN_RDH0R_DATA5 CAN_RDH0R_DATA5_Msk

Data byte 5

◆ CAN_RDH0R_DATA5_Msk

#define CAN_RDH0R_DATA5_Msk (0xFFUL << CAN_RDH0R_DATA5_Pos)

0x0000FF00

◆ CAN_RDH0R_DATA5_Pos

#define CAN_RDH0R_DATA5_Pos (8U)

◆ CAN_RDH0R_DATA6

#define CAN_RDH0R_DATA6 CAN_RDH0R_DATA6_Msk

Data byte 6

◆ CAN_RDH0R_DATA6_Msk

#define CAN_RDH0R_DATA6_Msk (0xFFUL << CAN_RDH0R_DATA6_Pos)

0x00FF0000

◆ CAN_RDH0R_DATA6_Pos

#define CAN_RDH0R_DATA6_Pos (16U)

◆ CAN_RDH0R_DATA7

#define CAN_RDH0R_DATA7 CAN_RDH0R_DATA7_Msk

Data byte 7

◆ CAN_RDH0R_DATA7_Msk

#define CAN_RDH0R_DATA7_Msk (0xFFUL << CAN_RDH0R_DATA7_Pos)

0xFF000000

◆ CAN_RDH0R_DATA7_Pos

#define CAN_RDH0R_DATA7_Pos (24U)

◆ CAN_RDH1R_DATA4

#define CAN_RDH1R_DATA4 CAN_RDH1R_DATA4_Msk

Data byte 4

◆ CAN_RDH1R_DATA4_Msk

#define CAN_RDH1R_DATA4_Msk (0xFFUL << CAN_RDH1R_DATA4_Pos)

0x000000FF

◆ CAN_RDH1R_DATA4_Pos

#define CAN_RDH1R_DATA4_Pos (0U)

◆ CAN_RDH1R_DATA5

#define CAN_RDH1R_DATA5 CAN_RDH1R_DATA5_Msk

Data byte 5

◆ CAN_RDH1R_DATA5_Msk

#define CAN_RDH1R_DATA5_Msk (0xFFUL << CAN_RDH1R_DATA5_Pos)

0x0000FF00

◆ CAN_RDH1R_DATA5_Pos

#define CAN_RDH1R_DATA5_Pos (8U)

◆ CAN_RDH1R_DATA6

#define CAN_RDH1R_DATA6 CAN_RDH1R_DATA6_Msk

Data byte 6

◆ CAN_RDH1R_DATA6_Msk

#define CAN_RDH1R_DATA6_Msk (0xFFUL << CAN_RDH1R_DATA6_Pos)

0x00FF0000

◆ CAN_RDH1R_DATA6_Pos

#define CAN_RDH1R_DATA6_Pos (16U)

◆ CAN_RDH1R_DATA7

#define CAN_RDH1R_DATA7 CAN_RDH1R_DATA7_Msk

Data byte 7 CAN filter registers

◆ CAN_RDH1R_DATA7_Msk

#define CAN_RDH1R_DATA7_Msk (0xFFUL << CAN_RDH1R_DATA7_Pos)

0xFF000000

◆ CAN_RDH1R_DATA7_Pos

#define CAN_RDH1R_DATA7_Pos (24U)

◆ CAN_RDL0R_DATA0

#define CAN_RDL0R_DATA0 CAN_RDL0R_DATA0_Msk

Data byte 0

◆ CAN_RDL0R_DATA0_Msk

#define CAN_RDL0R_DATA0_Msk (0xFFUL << CAN_RDL0R_DATA0_Pos)

0x000000FF

◆ CAN_RDL0R_DATA0_Pos

#define CAN_RDL0R_DATA0_Pos (0U)

◆ CAN_RDL0R_DATA1

#define CAN_RDL0R_DATA1 CAN_RDL0R_DATA1_Msk

Data byte 1

◆ CAN_RDL0R_DATA1_Msk

#define CAN_RDL0R_DATA1_Msk (0xFFUL << CAN_RDL0R_DATA1_Pos)

0x0000FF00

◆ CAN_RDL0R_DATA1_Pos

#define CAN_RDL0R_DATA1_Pos (8U)

◆ CAN_RDL0R_DATA2

#define CAN_RDL0R_DATA2 CAN_RDL0R_DATA2_Msk

Data byte 2

◆ CAN_RDL0R_DATA2_Msk

#define CAN_RDL0R_DATA2_Msk (0xFFUL << CAN_RDL0R_DATA2_Pos)

0x00FF0000

◆ CAN_RDL0R_DATA2_Pos

#define CAN_RDL0R_DATA2_Pos (16U)

◆ CAN_RDL0R_DATA3

#define CAN_RDL0R_DATA3 CAN_RDL0R_DATA3_Msk

Data byte 3

◆ CAN_RDL0R_DATA3_Msk

#define CAN_RDL0R_DATA3_Msk (0xFFUL << CAN_RDL0R_DATA3_Pos)

0xFF000000

◆ CAN_RDL0R_DATA3_Pos

#define CAN_RDL0R_DATA3_Pos (24U)

◆ CAN_RDL1R_DATA0

#define CAN_RDL1R_DATA0 CAN_RDL1R_DATA0_Msk

Data byte 0

◆ CAN_RDL1R_DATA0_Msk

#define CAN_RDL1R_DATA0_Msk (0xFFUL << CAN_RDL1R_DATA0_Pos)

0x000000FF

◆ CAN_RDL1R_DATA0_Pos

#define CAN_RDL1R_DATA0_Pos (0U)

◆ CAN_RDL1R_DATA1

#define CAN_RDL1R_DATA1 CAN_RDL1R_DATA1_Msk

Data byte 1

◆ CAN_RDL1R_DATA1_Msk

#define CAN_RDL1R_DATA1_Msk (0xFFUL << CAN_RDL1R_DATA1_Pos)

0x0000FF00

◆ CAN_RDL1R_DATA1_Pos

#define CAN_RDL1R_DATA1_Pos (8U)

◆ CAN_RDL1R_DATA2

#define CAN_RDL1R_DATA2 CAN_RDL1R_DATA2_Msk

Data byte 2

◆ CAN_RDL1R_DATA2_Msk

#define CAN_RDL1R_DATA2_Msk (0xFFUL << CAN_RDL1R_DATA2_Pos)

0x00FF0000

◆ CAN_RDL1R_DATA2_Pos

#define CAN_RDL1R_DATA2_Pos (16U)

◆ CAN_RDL1R_DATA3

#define CAN_RDL1R_DATA3 CAN_RDL1R_DATA3_Msk

Data byte 3

◆ CAN_RDL1R_DATA3_Msk

#define CAN_RDL1R_DATA3_Msk (0xFFUL << CAN_RDL1R_DATA3_Pos)

0xFF000000

◆ CAN_RDL1R_DATA3_Pos

#define CAN_RDL1R_DATA3_Pos (24U)

◆ CAN_RDT0R_DLC

#define CAN_RDT0R_DLC CAN_RDT0R_DLC_Msk

Data Length Code

◆ CAN_RDT0R_DLC_Msk

#define CAN_RDT0R_DLC_Msk (0xFUL << CAN_RDT0R_DLC_Pos)

0x0000000F

◆ CAN_RDT0R_DLC_Pos

#define CAN_RDT0R_DLC_Pos (0U)

◆ CAN_RDT0R_FMI

#define CAN_RDT0R_FMI CAN_RDT0R_FMI_Msk

Filter Match Index

◆ CAN_RDT0R_FMI_Msk

#define CAN_RDT0R_FMI_Msk (0xFFUL << CAN_RDT0R_FMI_Pos)

0x0000FF00

◆ CAN_RDT0R_FMI_Pos

#define CAN_RDT0R_FMI_Pos (8U)

◆ CAN_RDT0R_TIME

#define CAN_RDT0R_TIME CAN_RDT0R_TIME_Msk

Message Time Stamp

◆ CAN_RDT0R_TIME_Msk

#define CAN_RDT0R_TIME_Msk (0xFFFFUL << CAN_RDT0R_TIME_Pos)

0xFFFF0000

◆ CAN_RDT0R_TIME_Pos

#define CAN_RDT0R_TIME_Pos (16U)

◆ CAN_RDT1R_DLC

#define CAN_RDT1R_DLC CAN_RDT1R_DLC_Msk

Data Length Code

◆ CAN_RDT1R_DLC_Msk

#define CAN_RDT1R_DLC_Msk (0xFUL << CAN_RDT1R_DLC_Pos)

0x0000000F

◆ CAN_RDT1R_DLC_Pos

#define CAN_RDT1R_DLC_Pos (0U)

◆ CAN_RDT1R_FMI

#define CAN_RDT1R_FMI CAN_RDT1R_FMI_Msk

Filter Match Index

◆ CAN_RDT1R_FMI_Msk

#define CAN_RDT1R_FMI_Msk (0xFFUL << CAN_RDT1R_FMI_Pos)

0x0000FF00

◆ CAN_RDT1R_FMI_Pos

#define CAN_RDT1R_FMI_Pos (8U)

◆ CAN_RDT1R_TIME

#define CAN_RDT1R_TIME CAN_RDT1R_TIME_Msk

Message Time Stamp

◆ CAN_RDT1R_TIME_Msk

#define CAN_RDT1R_TIME_Msk (0xFFFFUL << CAN_RDT1R_TIME_Pos)

0xFFFF0000

◆ CAN_RDT1R_TIME_Pos

#define CAN_RDT1R_TIME_Pos (16U)

◆ CAN_RF0R_FMP0

#define CAN_RF0R_FMP0 CAN_RF0R_FMP0_Msk

FIFO 0 Message Pending

◆ CAN_RF0R_FMP0_Msk

#define CAN_RF0R_FMP0_Msk (0x3UL << CAN_RF0R_FMP0_Pos)

0x00000003

◆ CAN_RF0R_FMP0_Pos

#define CAN_RF0R_FMP0_Pos (0U)

◆ CAN_RF0R_FOVR0

#define CAN_RF0R_FOVR0 CAN_RF0R_FOVR0_Msk

FIFO 0 Overrun

◆ CAN_RF0R_FOVR0_Msk

#define CAN_RF0R_FOVR0_Msk (0x1UL << CAN_RF0R_FOVR0_Pos)

0x00000010

◆ CAN_RF0R_FOVR0_Pos

#define CAN_RF0R_FOVR0_Pos (4U)

◆ CAN_RF0R_FULL0

#define CAN_RF0R_FULL0 CAN_RF0R_FULL0_Msk

FIFO 0 Full

◆ CAN_RF0R_FULL0_Msk

#define CAN_RF0R_FULL0_Msk (0x1UL << CAN_RF0R_FULL0_Pos)

0x00000008

◆ CAN_RF0R_FULL0_Pos

#define CAN_RF0R_FULL0_Pos (3U)

◆ CAN_RF0R_RFOM0

#define CAN_RF0R_RFOM0 CAN_RF0R_RFOM0_Msk

Release FIFO 0 Output Mailbox

◆ CAN_RF0R_RFOM0_Msk

#define CAN_RF0R_RFOM0_Msk (0x1UL << CAN_RF0R_RFOM0_Pos)

0x00000020

◆ CAN_RF0R_RFOM0_Pos

#define CAN_RF0R_RFOM0_Pos (5U)

◆ CAN_RF1R_FMP1

#define CAN_RF1R_FMP1 CAN_RF1R_FMP1_Msk

FIFO 1 Message Pending

◆ CAN_RF1R_FMP1_Msk

#define CAN_RF1R_FMP1_Msk (0x3UL << CAN_RF1R_FMP1_Pos)

0x00000003

◆ CAN_RF1R_FMP1_Pos

#define CAN_RF1R_FMP1_Pos (0U)

◆ CAN_RF1R_FOVR1

#define CAN_RF1R_FOVR1 CAN_RF1R_FOVR1_Msk

FIFO 1 Overrun

◆ CAN_RF1R_FOVR1_Msk

#define CAN_RF1R_FOVR1_Msk (0x1UL << CAN_RF1R_FOVR1_Pos)

0x00000010

◆ CAN_RF1R_FOVR1_Pos

#define CAN_RF1R_FOVR1_Pos (4U)

◆ CAN_RF1R_FULL1

#define CAN_RF1R_FULL1 CAN_RF1R_FULL1_Msk

FIFO 1 Full

◆ CAN_RF1R_FULL1_Msk

#define CAN_RF1R_FULL1_Msk (0x1UL << CAN_RF1R_FULL1_Pos)

0x00000008

◆ CAN_RF1R_FULL1_Pos

#define CAN_RF1R_FULL1_Pos (3U)

◆ CAN_RF1R_RFOM1

#define CAN_RF1R_RFOM1 CAN_RF1R_RFOM1_Msk

Release FIFO 1 Output Mailbox

◆ CAN_RF1R_RFOM1_Msk

#define CAN_RF1R_RFOM1_Msk (0x1UL << CAN_RF1R_RFOM1_Pos)

0x00000020

◆ CAN_RF1R_RFOM1_Pos

#define CAN_RF1R_RFOM1_Pos (5U)

◆ CAN_RI0R_EXID

#define CAN_RI0R_EXID CAN_RI0R_EXID_Msk

Extended Identifier

◆ CAN_RI0R_EXID_Msk

#define CAN_RI0R_EXID_Msk (0x3FFFFUL << CAN_RI0R_EXID_Pos)

0x001FFFF8

◆ CAN_RI0R_EXID_Pos

#define CAN_RI0R_EXID_Pos (3U)

◆ CAN_RI0R_IDE

#define CAN_RI0R_IDE CAN_RI0R_IDE_Msk

Identifier Extension

◆ CAN_RI0R_IDE_Msk

#define CAN_RI0R_IDE_Msk (0x1UL << CAN_RI0R_IDE_Pos)

0x00000004

◆ CAN_RI0R_IDE_Pos

#define CAN_RI0R_IDE_Pos (2U)

◆ CAN_RI0R_RTR

#define CAN_RI0R_RTR CAN_RI0R_RTR_Msk

Remote Transmission Request

◆ CAN_RI0R_RTR_Msk

#define CAN_RI0R_RTR_Msk (0x1UL << CAN_RI0R_RTR_Pos)

0x00000002

◆ CAN_RI0R_RTR_Pos

#define CAN_RI0R_RTR_Pos (1U)

◆ CAN_RI0R_STID

#define CAN_RI0R_STID CAN_RI0R_STID_Msk

Standard Identifier or Extended Identifier

◆ CAN_RI0R_STID_Msk

#define CAN_RI0R_STID_Msk (0x7FFUL << CAN_RI0R_STID_Pos)

0xFFE00000

◆ CAN_RI0R_STID_Pos

#define CAN_RI0R_STID_Pos (21U)

◆ CAN_RI1R_EXID

#define CAN_RI1R_EXID CAN_RI1R_EXID_Msk

Extended identifier

◆ CAN_RI1R_EXID_Msk

#define CAN_RI1R_EXID_Msk (0x3FFFFUL << CAN_RI1R_EXID_Pos)

0x001FFFF8

◆ CAN_RI1R_EXID_Pos

#define CAN_RI1R_EXID_Pos (3U)

◆ CAN_RI1R_IDE

#define CAN_RI1R_IDE CAN_RI1R_IDE_Msk

Identifier Extension

◆ CAN_RI1R_IDE_Msk

#define CAN_RI1R_IDE_Msk (0x1UL << CAN_RI1R_IDE_Pos)

0x00000004

◆ CAN_RI1R_IDE_Pos

#define CAN_RI1R_IDE_Pos (2U)

◆ CAN_RI1R_RTR

#define CAN_RI1R_RTR CAN_RI1R_RTR_Msk

Remote Transmission Request

◆ CAN_RI1R_RTR_Msk

#define CAN_RI1R_RTR_Msk (0x1UL << CAN_RI1R_RTR_Pos)

0x00000002

◆ CAN_RI1R_RTR_Pos

#define CAN_RI1R_RTR_Pos (1U)

◆ CAN_RI1R_STID

#define CAN_RI1R_STID CAN_RI1R_STID_Msk

Standard Identifier or Extended Identifier

◆ CAN_RI1R_STID_Msk

#define CAN_RI1R_STID_Msk (0x7FFUL << CAN_RI1R_STID_Pos)

0xFFE00000

◆ CAN_RI1R_STID_Pos

#define CAN_RI1R_STID_Pos (21U)

◆ CAN_TDH0R_DATA4

#define CAN_TDH0R_DATA4 CAN_TDH0R_DATA4_Msk

Data byte 4

◆ CAN_TDH0R_DATA4_Msk

#define CAN_TDH0R_DATA4_Msk (0xFFUL << CAN_TDH0R_DATA4_Pos)

0x000000FF

◆ CAN_TDH0R_DATA4_Pos

#define CAN_TDH0R_DATA4_Pos (0U)

◆ CAN_TDH0R_DATA5

#define CAN_TDH0R_DATA5 CAN_TDH0R_DATA5_Msk

Data byte 5

◆ CAN_TDH0R_DATA5_Msk

#define CAN_TDH0R_DATA5_Msk (0xFFUL << CAN_TDH0R_DATA5_Pos)

0x0000FF00

◆ CAN_TDH0R_DATA5_Pos

#define CAN_TDH0R_DATA5_Pos (8U)

◆ CAN_TDH0R_DATA6

#define CAN_TDH0R_DATA6 CAN_TDH0R_DATA6_Msk

Data byte 6

◆ CAN_TDH0R_DATA6_Msk

#define CAN_TDH0R_DATA6_Msk (0xFFUL << CAN_TDH0R_DATA6_Pos)

0x00FF0000

◆ CAN_TDH0R_DATA6_Pos

#define CAN_TDH0R_DATA6_Pos (16U)

◆ CAN_TDH0R_DATA7

#define CAN_TDH0R_DATA7 CAN_TDH0R_DATA7_Msk

Data byte 7

◆ CAN_TDH0R_DATA7_Msk

#define CAN_TDH0R_DATA7_Msk (0xFFUL << CAN_TDH0R_DATA7_Pos)

0xFF000000

◆ CAN_TDH0R_DATA7_Pos

#define CAN_TDH0R_DATA7_Pos (24U)

◆ CAN_TDH1R_DATA4

#define CAN_TDH1R_DATA4 CAN_TDH1R_DATA4_Msk

Data byte 4

◆ CAN_TDH1R_DATA4_Msk

#define CAN_TDH1R_DATA4_Msk (0xFFUL << CAN_TDH1R_DATA4_Pos)

0x000000FF

◆ CAN_TDH1R_DATA4_Pos

#define CAN_TDH1R_DATA4_Pos (0U)

◆ CAN_TDH1R_DATA5

#define CAN_TDH1R_DATA5 CAN_TDH1R_DATA5_Msk

Data byte 5

◆ CAN_TDH1R_DATA5_Msk

#define CAN_TDH1R_DATA5_Msk (0xFFUL << CAN_TDH1R_DATA5_Pos)

0x0000FF00

◆ CAN_TDH1R_DATA5_Pos

#define CAN_TDH1R_DATA5_Pos (8U)

◆ CAN_TDH1R_DATA6

#define CAN_TDH1R_DATA6 CAN_TDH1R_DATA6_Msk

Data byte 6

◆ CAN_TDH1R_DATA6_Msk

#define CAN_TDH1R_DATA6_Msk (0xFFUL << CAN_TDH1R_DATA6_Pos)

0x00FF0000

◆ CAN_TDH1R_DATA6_Pos

#define CAN_TDH1R_DATA6_Pos (16U)

◆ CAN_TDH1R_DATA7

#define CAN_TDH1R_DATA7 CAN_TDH1R_DATA7_Msk

Data byte 7

◆ CAN_TDH1R_DATA7_Msk

#define CAN_TDH1R_DATA7_Msk (0xFFUL << CAN_TDH1R_DATA7_Pos)

0xFF000000

◆ CAN_TDH1R_DATA7_Pos

#define CAN_TDH1R_DATA7_Pos (24U)

◆ CAN_TDH2R_DATA4

#define CAN_TDH2R_DATA4 CAN_TDH2R_DATA4_Msk

Data byte 4

◆ CAN_TDH2R_DATA4_Msk

#define CAN_TDH2R_DATA4_Msk (0xFFUL << CAN_TDH2R_DATA4_Pos)

0x000000FF

◆ CAN_TDH2R_DATA4_Pos

#define CAN_TDH2R_DATA4_Pos (0U)

◆ CAN_TDH2R_DATA5

#define CAN_TDH2R_DATA5 CAN_TDH2R_DATA5_Msk

Data byte 5

◆ CAN_TDH2R_DATA5_Msk

#define CAN_TDH2R_DATA5_Msk (0xFFUL << CAN_TDH2R_DATA5_Pos)

0x0000FF00

◆ CAN_TDH2R_DATA5_Pos

#define CAN_TDH2R_DATA5_Pos (8U)

◆ CAN_TDH2R_DATA6

#define CAN_TDH2R_DATA6 CAN_TDH2R_DATA6_Msk

Data byte 6

◆ CAN_TDH2R_DATA6_Msk

#define CAN_TDH2R_DATA6_Msk (0xFFUL << CAN_TDH2R_DATA6_Pos)

0x00FF0000

◆ CAN_TDH2R_DATA6_Pos

#define CAN_TDH2R_DATA6_Pos (16U)

◆ CAN_TDH2R_DATA7

#define CAN_TDH2R_DATA7 CAN_TDH2R_DATA7_Msk

Data byte 7

◆ CAN_TDH2R_DATA7_Msk

#define CAN_TDH2R_DATA7_Msk (0xFFUL << CAN_TDH2R_DATA7_Pos)

0xFF000000

◆ CAN_TDH2R_DATA7_Pos

#define CAN_TDH2R_DATA7_Pos (24U)

◆ CAN_TDL0R_DATA0

#define CAN_TDL0R_DATA0 CAN_TDL0R_DATA0_Msk

Data byte 0

◆ CAN_TDL0R_DATA0_Msk

#define CAN_TDL0R_DATA0_Msk (0xFFUL << CAN_TDL0R_DATA0_Pos)

0x000000FF

◆ CAN_TDL0R_DATA0_Pos

#define CAN_TDL0R_DATA0_Pos (0U)

◆ CAN_TDL0R_DATA1

#define CAN_TDL0R_DATA1 CAN_TDL0R_DATA1_Msk

Data byte 1

◆ CAN_TDL0R_DATA1_Msk

#define CAN_TDL0R_DATA1_Msk (0xFFUL << CAN_TDL0R_DATA1_Pos)

0x0000FF00

◆ CAN_TDL0R_DATA1_Pos

#define CAN_TDL0R_DATA1_Pos (8U)

◆ CAN_TDL0R_DATA2

#define CAN_TDL0R_DATA2 CAN_TDL0R_DATA2_Msk

Data byte 2

◆ CAN_TDL0R_DATA2_Msk

#define CAN_TDL0R_DATA2_Msk (0xFFUL << CAN_TDL0R_DATA2_Pos)

0x00FF0000

◆ CAN_TDL0R_DATA2_Pos

#define CAN_TDL0R_DATA2_Pos (16U)

◆ CAN_TDL0R_DATA3

#define CAN_TDL0R_DATA3 CAN_TDL0R_DATA3_Msk

Data byte 3

◆ CAN_TDL0R_DATA3_Msk

#define CAN_TDL0R_DATA3_Msk (0xFFUL << CAN_TDL0R_DATA3_Pos)

0xFF000000

◆ CAN_TDL0R_DATA3_Pos

#define CAN_TDL0R_DATA3_Pos (24U)

◆ CAN_TDL1R_DATA0

#define CAN_TDL1R_DATA0 CAN_TDL1R_DATA0_Msk

Data byte 0

◆ CAN_TDL1R_DATA0_Msk

#define CAN_TDL1R_DATA0_Msk (0xFFUL << CAN_TDL1R_DATA0_Pos)

0x000000FF

◆ CAN_TDL1R_DATA0_Pos

#define CAN_TDL1R_DATA0_Pos (0U)

◆ CAN_TDL1R_DATA1

#define CAN_TDL1R_DATA1 CAN_TDL1R_DATA1_Msk

Data byte 1

◆ CAN_TDL1R_DATA1_Msk

#define CAN_TDL1R_DATA1_Msk (0xFFUL << CAN_TDL1R_DATA1_Pos)

0x0000FF00

◆ CAN_TDL1R_DATA1_Pos

#define CAN_TDL1R_DATA1_Pos (8U)

◆ CAN_TDL1R_DATA2

#define CAN_TDL1R_DATA2 CAN_TDL1R_DATA2_Msk

Data byte 2

◆ CAN_TDL1R_DATA2_Msk

#define CAN_TDL1R_DATA2_Msk (0xFFUL << CAN_TDL1R_DATA2_Pos)

0x00FF0000

◆ CAN_TDL1R_DATA2_Pos

#define CAN_TDL1R_DATA2_Pos (16U)

◆ CAN_TDL1R_DATA3

#define CAN_TDL1R_DATA3 CAN_TDL1R_DATA3_Msk

Data byte 3

◆ CAN_TDL1R_DATA3_Msk

#define CAN_TDL1R_DATA3_Msk (0xFFUL << CAN_TDL1R_DATA3_Pos)

0xFF000000

◆ CAN_TDL1R_DATA3_Pos

#define CAN_TDL1R_DATA3_Pos (24U)

◆ CAN_TDL2R_DATA0

#define CAN_TDL2R_DATA0 CAN_TDL2R_DATA0_Msk

Data byte 0

◆ CAN_TDL2R_DATA0_Msk

#define CAN_TDL2R_DATA0_Msk (0xFFUL << CAN_TDL2R_DATA0_Pos)

0x000000FF

◆ CAN_TDL2R_DATA0_Pos

#define CAN_TDL2R_DATA0_Pos (0U)

◆ CAN_TDL2R_DATA1

#define CAN_TDL2R_DATA1 CAN_TDL2R_DATA1_Msk

Data byte 1

◆ CAN_TDL2R_DATA1_Msk

#define CAN_TDL2R_DATA1_Msk (0xFFUL << CAN_TDL2R_DATA1_Pos)

0x0000FF00

◆ CAN_TDL2R_DATA1_Pos

#define CAN_TDL2R_DATA1_Pos (8U)

◆ CAN_TDL2R_DATA2

#define CAN_TDL2R_DATA2 CAN_TDL2R_DATA2_Msk

Data byte 2

◆ CAN_TDL2R_DATA2_Msk

#define CAN_TDL2R_DATA2_Msk (0xFFUL << CAN_TDL2R_DATA2_Pos)

0x00FF0000

◆ CAN_TDL2R_DATA2_Pos

#define CAN_TDL2R_DATA2_Pos (16U)

◆ CAN_TDL2R_DATA3

#define CAN_TDL2R_DATA3 CAN_TDL2R_DATA3_Msk

Data byte 3

◆ CAN_TDL2R_DATA3_Msk

#define CAN_TDL2R_DATA3_Msk (0xFFUL << CAN_TDL2R_DATA3_Pos)

0xFF000000

◆ CAN_TDL2R_DATA3_Pos

#define CAN_TDL2R_DATA3_Pos (24U)

◆ CAN_TDT0R_DLC

#define CAN_TDT0R_DLC CAN_TDT0R_DLC_Msk

Data Length Code

◆ CAN_TDT0R_DLC_Msk

#define CAN_TDT0R_DLC_Msk (0xFUL << CAN_TDT0R_DLC_Pos)

0x0000000F

◆ CAN_TDT0R_DLC_Pos

#define CAN_TDT0R_DLC_Pos (0U)

◆ CAN_TDT0R_TGT

#define CAN_TDT0R_TGT CAN_TDT0R_TGT_Msk

Transmit Global Time

◆ CAN_TDT0R_TGT_Msk

#define CAN_TDT0R_TGT_Msk (0x1UL << CAN_TDT0R_TGT_Pos)

0x00000100

◆ CAN_TDT0R_TGT_Pos

#define CAN_TDT0R_TGT_Pos (8U)

◆ CAN_TDT0R_TIME

#define CAN_TDT0R_TIME CAN_TDT0R_TIME_Msk

Message Time Stamp

◆ CAN_TDT0R_TIME_Msk

#define CAN_TDT0R_TIME_Msk (0xFFFFUL << CAN_TDT0R_TIME_Pos)

0xFFFF0000

◆ CAN_TDT0R_TIME_Pos

#define CAN_TDT0R_TIME_Pos (16U)

◆ CAN_TDT1R_DLC

#define CAN_TDT1R_DLC CAN_TDT1R_DLC_Msk

Data Length Code

◆ CAN_TDT1R_DLC_Msk

#define CAN_TDT1R_DLC_Msk (0xFUL << CAN_TDT1R_DLC_Pos)

0x0000000F

◆ CAN_TDT1R_DLC_Pos

#define CAN_TDT1R_DLC_Pos (0U)

◆ CAN_TDT1R_TGT

#define CAN_TDT1R_TGT CAN_TDT1R_TGT_Msk

Transmit Global Time

◆ CAN_TDT1R_TGT_Msk

#define CAN_TDT1R_TGT_Msk (0x1UL << CAN_TDT1R_TGT_Pos)

0x00000100

◆ CAN_TDT1R_TGT_Pos

#define CAN_TDT1R_TGT_Pos (8U)

◆ CAN_TDT1R_TIME

#define CAN_TDT1R_TIME CAN_TDT1R_TIME_Msk

Message Time Stamp

◆ CAN_TDT1R_TIME_Msk

#define CAN_TDT1R_TIME_Msk (0xFFFFUL << CAN_TDT1R_TIME_Pos)

0xFFFF0000

◆ CAN_TDT1R_TIME_Pos

#define CAN_TDT1R_TIME_Pos (16U)

◆ CAN_TDT2R_DLC

#define CAN_TDT2R_DLC CAN_TDT2R_DLC_Msk

Data Length Code

◆ CAN_TDT2R_DLC_Msk

#define CAN_TDT2R_DLC_Msk (0xFUL << CAN_TDT2R_DLC_Pos)

0x0000000F

◆ CAN_TDT2R_DLC_Pos

#define CAN_TDT2R_DLC_Pos (0U)

◆ CAN_TDT2R_TGT

#define CAN_TDT2R_TGT CAN_TDT2R_TGT_Msk

Transmit Global Time

◆ CAN_TDT2R_TGT_Msk

#define CAN_TDT2R_TGT_Msk (0x1UL << CAN_TDT2R_TGT_Pos)

0x00000100

◆ CAN_TDT2R_TGT_Pos

#define CAN_TDT2R_TGT_Pos (8U)

◆ CAN_TDT2R_TIME

#define CAN_TDT2R_TIME CAN_TDT2R_TIME_Msk

Message Time Stamp

◆ CAN_TDT2R_TIME_Msk

#define CAN_TDT2R_TIME_Msk (0xFFFFUL << CAN_TDT2R_TIME_Pos)

0xFFFF0000

◆ CAN_TDT2R_TIME_Pos

#define CAN_TDT2R_TIME_Pos (16U)

◆ CAN_TI0R_EXID

#define CAN_TI0R_EXID CAN_TI0R_EXID_Msk

Extended Identifier

◆ CAN_TI0R_EXID_Msk

#define CAN_TI0R_EXID_Msk (0x3FFFFUL << CAN_TI0R_EXID_Pos)

0x001FFFF8

◆ CAN_TI0R_EXID_Pos

#define CAN_TI0R_EXID_Pos (3U)

◆ CAN_TI0R_IDE

#define CAN_TI0R_IDE CAN_TI0R_IDE_Msk

Identifier Extension

◆ CAN_TI0R_IDE_Msk

#define CAN_TI0R_IDE_Msk (0x1UL << CAN_TI0R_IDE_Pos)

0x00000004

◆ CAN_TI0R_IDE_Pos

#define CAN_TI0R_IDE_Pos (2U)

◆ CAN_TI0R_RTR

#define CAN_TI0R_RTR CAN_TI0R_RTR_Msk

Remote Transmission Request

◆ CAN_TI0R_RTR_Msk

#define CAN_TI0R_RTR_Msk (0x1UL << CAN_TI0R_RTR_Pos)

0x00000002

◆ CAN_TI0R_RTR_Pos

#define CAN_TI0R_RTR_Pos (1U)

◆ CAN_TI0R_STID

#define CAN_TI0R_STID CAN_TI0R_STID_Msk

Standard Identifier or Extended Identifier

◆ CAN_TI0R_STID_Msk

#define CAN_TI0R_STID_Msk (0x7FFUL << CAN_TI0R_STID_Pos)

0xFFE00000

◆ CAN_TI0R_STID_Pos

#define CAN_TI0R_STID_Pos (21U)

◆ CAN_TI0R_TXRQ

#define CAN_TI0R_TXRQ CAN_TI0R_TXRQ_Msk

Transmit Mailbox Request

◆ CAN_TI0R_TXRQ_Msk

#define CAN_TI0R_TXRQ_Msk (0x1UL << CAN_TI0R_TXRQ_Pos)

0x00000001

◆ CAN_TI0R_TXRQ_Pos

#define CAN_TI0R_TXRQ_Pos (0U)

◆ CAN_TI1R_EXID

#define CAN_TI1R_EXID CAN_TI1R_EXID_Msk

Extended Identifier

◆ CAN_TI1R_EXID_Msk

#define CAN_TI1R_EXID_Msk (0x3FFFFUL << CAN_TI1R_EXID_Pos)

0x001FFFF8

◆ CAN_TI1R_EXID_Pos

#define CAN_TI1R_EXID_Pos (3U)

◆ CAN_TI1R_IDE

#define CAN_TI1R_IDE CAN_TI1R_IDE_Msk

Identifier Extension

◆ CAN_TI1R_IDE_Msk

#define CAN_TI1R_IDE_Msk (0x1UL << CAN_TI1R_IDE_Pos)

0x00000004

◆ CAN_TI1R_IDE_Pos

#define CAN_TI1R_IDE_Pos (2U)

◆ CAN_TI1R_RTR

#define CAN_TI1R_RTR CAN_TI1R_RTR_Msk

Remote Transmission Request

◆ CAN_TI1R_RTR_Msk

#define CAN_TI1R_RTR_Msk (0x1UL << CAN_TI1R_RTR_Pos)

0x00000002

◆ CAN_TI1R_RTR_Pos

#define CAN_TI1R_RTR_Pos (1U)

◆ CAN_TI1R_STID

#define CAN_TI1R_STID CAN_TI1R_STID_Msk

Standard Identifier or Extended Identifier

◆ CAN_TI1R_STID_Msk

#define CAN_TI1R_STID_Msk (0x7FFUL << CAN_TI1R_STID_Pos)

0xFFE00000

◆ CAN_TI1R_STID_Pos

#define CAN_TI1R_STID_Pos (21U)

◆ CAN_TI1R_TXRQ

#define CAN_TI1R_TXRQ CAN_TI1R_TXRQ_Msk

Transmit Mailbox Request

◆ CAN_TI1R_TXRQ_Msk

#define CAN_TI1R_TXRQ_Msk (0x1UL << CAN_TI1R_TXRQ_Pos)

0x00000001

◆ CAN_TI1R_TXRQ_Pos

#define CAN_TI1R_TXRQ_Pos (0U)

◆ CAN_TI2R_EXID

#define CAN_TI2R_EXID CAN_TI2R_EXID_Msk

Extended identifier

◆ CAN_TI2R_EXID_Msk

#define CAN_TI2R_EXID_Msk (0x3FFFFUL << CAN_TI2R_EXID_Pos)

0x001FFFF8

◆ CAN_TI2R_EXID_Pos

#define CAN_TI2R_EXID_Pos (3U)

◆ CAN_TI2R_IDE

#define CAN_TI2R_IDE CAN_TI2R_IDE_Msk

Identifier Extension

◆ CAN_TI2R_IDE_Msk

#define CAN_TI2R_IDE_Msk (0x1UL << CAN_TI2R_IDE_Pos)

0x00000004

◆ CAN_TI2R_IDE_Pos

#define CAN_TI2R_IDE_Pos (2U)

◆ CAN_TI2R_RTR

#define CAN_TI2R_RTR CAN_TI2R_RTR_Msk

Remote Transmission Request

◆ CAN_TI2R_RTR_Msk

#define CAN_TI2R_RTR_Msk (0x1UL << CAN_TI2R_RTR_Pos)

0x00000002

◆ CAN_TI2R_RTR_Pos

#define CAN_TI2R_RTR_Pos (1U)

◆ CAN_TI2R_STID

#define CAN_TI2R_STID CAN_TI2R_STID_Msk

Standard Identifier or Extended Identifier

◆ CAN_TI2R_STID_Msk

#define CAN_TI2R_STID_Msk (0x7FFUL << CAN_TI2R_STID_Pos)

0xFFE00000

◆ CAN_TI2R_STID_Pos

#define CAN_TI2R_STID_Pos (21U)

◆ CAN_TI2R_TXRQ

#define CAN_TI2R_TXRQ CAN_TI2R_TXRQ_Msk

Transmit Mailbox Request

◆ CAN_TI2R_TXRQ_Msk

#define CAN_TI2R_TXRQ_Msk (0x1UL << CAN_TI2R_TXRQ_Pos)

0x00000001

◆ CAN_TI2R_TXRQ_Pos

#define CAN_TI2R_TXRQ_Pos (0U)

◆ CAN_TSR_ABRQ0

#define CAN_TSR_ABRQ0 CAN_TSR_ABRQ0_Msk

Abort Request for Mailbox0

◆ CAN_TSR_ABRQ0_Msk

#define CAN_TSR_ABRQ0_Msk (0x1UL << CAN_TSR_ABRQ0_Pos)

0x00000080

◆ CAN_TSR_ABRQ0_Pos

#define CAN_TSR_ABRQ0_Pos (7U)

◆ CAN_TSR_ABRQ1

#define CAN_TSR_ABRQ1 CAN_TSR_ABRQ1_Msk

Abort Request for Mailbox 1

◆ CAN_TSR_ABRQ1_Msk

#define CAN_TSR_ABRQ1_Msk (0x1UL << CAN_TSR_ABRQ1_Pos)

0x00008000

◆ CAN_TSR_ABRQ1_Pos

#define CAN_TSR_ABRQ1_Pos (15U)

◆ CAN_TSR_ABRQ2

#define CAN_TSR_ABRQ2 CAN_TSR_ABRQ2_Msk

Abort Request for Mailbox 2

◆ CAN_TSR_ABRQ2_Msk

#define CAN_TSR_ABRQ2_Msk (0x1UL << CAN_TSR_ABRQ2_Pos)

0x00800000

◆ CAN_TSR_ABRQ2_Pos

#define CAN_TSR_ABRQ2_Pos (23U)

◆ CAN_TSR_ALST0

#define CAN_TSR_ALST0 CAN_TSR_ALST0_Msk

Arbitration Lost for Mailbox0

◆ CAN_TSR_ALST0_Msk

#define CAN_TSR_ALST0_Msk (0x1UL << CAN_TSR_ALST0_Pos)

0x00000004

◆ CAN_TSR_ALST0_Pos

#define CAN_TSR_ALST0_Pos (2U)

◆ CAN_TSR_ALST1

#define CAN_TSR_ALST1 CAN_TSR_ALST1_Msk

Arbitration Lost for Mailbox1

◆ CAN_TSR_ALST1_Msk

#define CAN_TSR_ALST1_Msk (0x1UL << CAN_TSR_ALST1_Pos)

0x00000400

◆ CAN_TSR_ALST1_Pos

#define CAN_TSR_ALST1_Pos (10U)

◆ CAN_TSR_ALST2

#define CAN_TSR_ALST2 CAN_TSR_ALST2_Msk

Arbitration Lost for mailbox 2

◆ CAN_TSR_ALST2_Msk

#define CAN_TSR_ALST2_Msk (0x1UL << CAN_TSR_ALST2_Pos)

0x00040000

◆ CAN_TSR_ALST2_Pos

#define CAN_TSR_ALST2_Pos (18U)

◆ CAN_TSR_CODE

#define CAN_TSR_CODE CAN_TSR_CODE_Msk

Mailbox Code

◆ CAN_TSR_CODE_Msk

#define CAN_TSR_CODE_Msk (0x3UL << CAN_TSR_CODE_Pos)

0x03000000

◆ CAN_TSR_CODE_Pos

#define CAN_TSR_CODE_Pos (24U)

◆ CAN_TSR_LOW

#define CAN_TSR_LOW CAN_TSR_LOW_Msk

LOW[2:0] bits

◆ CAN_TSR_LOW0

#define CAN_TSR_LOW0 CAN_TSR_LOW0_Msk

Lowest Priority Flag for Mailbox 0

◆ CAN_TSR_LOW0_Msk

#define CAN_TSR_LOW0_Msk (0x1UL << CAN_TSR_LOW0_Pos)

0x20000000

◆ CAN_TSR_LOW0_Pos

#define CAN_TSR_LOW0_Pos (29U)

◆ CAN_TSR_LOW1

#define CAN_TSR_LOW1 CAN_TSR_LOW1_Msk

Lowest Priority Flag for Mailbox 1

◆ CAN_TSR_LOW1_Msk

#define CAN_TSR_LOW1_Msk (0x1UL << CAN_TSR_LOW1_Pos)

0x40000000

◆ CAN_TSR_LOW1_Pos

#define CAN_TSR_LOW1_Pos (30U)

◆ CAN_TSR_LOW2

#define CAN_TSR_LOW2 CAN_TSR_LOW2_Msk

Lowest Priority Flag for Mailbox 2

◆ CAN_TSR_LOW2_Msk

#define CAN_TSR_LOW2_Msk (0x1UL << CAN_TSR_LOW2_Pos)

0x80000000

◆ CAN_TSR_LOW2_Pos

#define CAN_TSR_LOW2_Pos (31U)

◆ CAN_TSR_LOW_Msk

#define CAN_TSR_LOW_Msk (0x7UL << CAN_TSR_LOW_Pos)

0xE0000000

◆ CAN_TSR_LOW_Pos

#define CAN_TSR_LOW_Pos (29U)

◆ CAN_TSR_RQCP0

#define CAN_TSR_RQCP0 CAN_TSR_RQCP0_Msk

Request Completed Mailbox0

◆ CAN_TSR_RQCP0_Msk

#define CAN_TSR_RQCP0_Msk (0x1UL << CAN_TSR_RQCP0_Pos)

0x00000001

◆ CAN_TSR_RQCP0_Pos

#define CAN_TSR_RQCP0_Pos (0U)

◆ CAN_TSR_RQCP1

#define CAN_TSR_RQCP1 CAN_TSR_RQCP1_Msk

Request Completed Mailbox1

◆ CAN_TSR_RQCP1_Msk

#define CAN_TSR_RQCP1_Msk (0x1UL << CAN_TSR_RQCP1_Pos)

0x00000100

◆ CAN_TSR_RQCP1_Pos

#define CAN_TSR_RQCP1_Pos (8U)

◆ CAN_TSR_RQCP2

#define CAN_TSR_RQCP2 CAN_TSR_RQCP2_Msk

Request Completed Mailbox2

◆ CAN_TSR_RQCP2_Msk

#define CAN_TSR_RQCP2_Msk (0x1UL << CAN_TSR_RQCP2_Pos)

0x00010000

◆ CAN_TSR_RQCP2_Pos

#define CAN_TSR_RQCP2_Pos (16U)

◆ CAN_TSR_TERR0

#define CAN_TSR_TERR0 CAN_TSR_TERR0_Msk

Transmission Error of Mailbox0

◆ CAN_TSR_TERR0_Msk

#define CAN_TSR_TERR0_Msk (0x1UL << CAN_TSR_TERR0_Pos)

0x00000008

◆ CAN_TSR_TERR0_Pos

#define CAN_TSR_TERR0_Pos (3U)

◆ CAN_TSR_TERR1

#define CAN_TSR_TERR1 CAN_TSR_TERR1_Msk

Transmission Error of Mailbox1

◆ CAN_TSR_TERR1_Msk

#define CAN_TSR_TERR1_Msk (0x1UL << CAN_TSR_TERR1_Pos)

0x00000800

◆ CAN_TSR_TERR1_Pos

#define CAN_TSR_TERR1_Pos (11U)

◆ CAN_TSR_TERR2

#define CAN_TSR_TERR2 CAN_TSR_TERR2_Msk

Transmission Error of Mailbox 2

◆ CAN_TSR_TERR2_Msk

#define CAN_TSR_TERR2_Msk (0x1UL << CAN_TSR_TERR2_Pos)

0x00080000

◆ CAN_TSR_TERR2_Pos

#define CAN_TSR_TERR2_Pos (19U)

◆ CAN_TSR_TME

#define CAN_TSR_TME CAN_TSR_TME_Msk

TME[2:0] bits

◆ CAN_TSR_TME0

#define CAN_TSR_TME0 CAN_TSR_TME0_Msk

Transmit Mailbox 0 Empty

◆ CAN_TSR_TME0_Msk

#define CAN_TSR_TME0_Msk (0x1UL << CAN_TSR_TME0_Pos)

0x04000000

◆ CAN_TSR_TME0_Pos

#define CAN_TSR_TME0_Pos (26U)

◆ CAN_TSR_TME1

#define CAN_TSR_TME1 CAN_TSR_TME1_Msk

Transmit Mailbox 1 Empty

◆ CAN_TSR_TME1_Msk

#define CAN_TSR_TME1_Msk (0x1UL << CAN_TSR_TME1_Pos)

0x08000000

◆ CAN_TSR_TME1_Pos

#define CAN_TSR_TME1_Pos (27U)

◆ CAN_TSR_TME2

#define CAN_TSR_TME2 CAN_TSR_TME2_Msk

Transmit Mailbox 2 Empty

◆ CAN_TSR_TME2_Msk

#define CAN_TSR_TME2_Msk (0x1UL << CAN_TSR_TME2_Pos)

0x10000000

◆ CAN_TSR_TME2_Pos

#define CAN_TSR_TME2_Pos (28U)

◆ CAN_TSR_TME_Msk

#define CAN_TSR_TME_Msk (0x7UL << CAN_TSR_TME_Pos)

0x1C000000

◆ CAN_TSR_TME_Pos

#define CAN_TSR_TME_Pos (26U)

◆ CAN_TSR_TXOK0

#define CAN_TSR_TXOK0 CAN_TSR_TXOK0_Msk

Transmission OK of Mailbox0

◆ CAN_TSR_TXOK0_Msk

#define CAN_TSR_TXOK0_Msk (0x1UL << CAN_TSR_TXOK0_Pos)

0x00000002

◆ CAN_TSR_TXOK0_Pos

#define CAN_TSR_TXOK0_Pos (1U)

◆ CAN_TSR_TXOK1

#define CAN_TSR_TXOK1 CAN_TSR_TXOK1_Msk

Transmission OK of Mailbox1

◆ CAN_TSR_TXOK1_Msk

#define CAN_TSR_TXOK1_Msk (0x1UL << CAN_TSR_TXOK1_Pos)

0x00000200

◆ CAN_TSR_TXOK1_Pos

#define CAN_TSR_TXOK1_Pos (9U)

◆ CAN_TSR_TXOK2

#define CAN_TSR_TXOK2 CAN_TSR_TXOK2_Msk

Transmission OK of Mailbox 2

◆ CAN_TSR_TXOK2_Msk

#define CAN_TSR_TXOK2_Msk (0x1UL << CAN_TSR_TXOK2_Pos)

0x00020000

◆ CAN_TSR_TXOK2_Pos

#define CAN_TSR_TXOK2_Pos (17U)

◆ COMP1_CSR_COMP1BLANKING

#define COMP1_CSR_COMP1BLANKING COMP1_CSR_COMP1BLANKING_Msk

COMP1 blanking

◆ COMP1_CSR_COMP1BLANKING_0

#define COMP1_CSR_COMP1BLANKING_0 (0x1UL << COMP1_CSR_COMP1BLANKING_Pos)

0x00040000

◆ COMP1_CSR_COMP1BLANKING_1

#define COMP1_CSR_COMP1BLANKING_1 (0x2UL << COMP1_CSR_COMP1BLANKING_Pos)

0x00080000

◆ COMP1_CSR_COMP1BLANKING_2

#define COMP1_CSR_COMP1BLANKING_2 (0x4UL << COMP1_CSR_COMP1BLANKING_Pos)

0x00100000

◆ COMP1_CSR_COMP1BLANKING_Msk

#define COMP1_CSR_COMP1BLANKING_Msk (0x3UL << COMP1_CSR_COMP1BLANKING_Pos)

0x000C0000

◆ COMP1_CSR_COMP1BLANKING_Pos

#define COMP1_CSR_COMP1BLANKING_Pos (18U)

◆ COMP1_CSR_COMP1EN

#define COMP1_CSR_COMP1EN COMP1_CSR_COMP1EN_Msk

COMP1 enable

◆ COMP1_CSR_COMP1EN_Msk

#define COMP1_CSR_COMP1EN_Msk (0x1UL << COMP1_CSR_COMP1EN_Pos)

0x00000001

◆ COMP1_CSR_COMP1EN_Pos

#define COMP1_CSR_COMP1EN_Pos (0U)

◆ COMP1_CSR_COMP1INSEL

#define COMP1_CSR_COMP1INSEL COMP1_CSR_COMP1INSEL_Msk

COMP1 inverting input select

◆ COMP1_CSR_COMP1INSEL_0

#define COMP1_CSR_COMP1INSEL_0 (0x1UL << COMP1_CSR_COMP1INSEL_Pos)

0x00000010

◆ COMP1_CSR_COMP1INSEL_1

#define COMP1_CSR_COMP1INSEL_1 (0x2UL << COMP1_CSR_COMP1INSEL_Pos)

0x00000020

◆ COMP1_CSR_COMP1INSEL_2

#define COMP1_CSR_COMP1INSEL_2 (0x4UL << COMP1_CSR_COMP1INSEL_Pos)

0x00000040

◆ COMP1_CSR_COMP1INSEL_Msk

#define COMP1_CSR_COMP1INSEL_Msk (0x7UL << COMP1_CSR_COMP1INSEL_Pos)

0x00000070

◆ COMP1_CSR_COMP1INSEL_Pos

#define COMP1_CSR_COMP1INSEL_Pos (4U)

◆ COMP1_CSR_COMP1LOCK

#define COMP1_CSR_COMP1LOCK COMP1_CSR_COMP1LOCK_Msk

COMP1 lock

◆ COMP1_CSR_COMP1LOCK_Msk

#define COMP1_CSR_COMP1LOCK_Msk (0x1UL << COMP1_CSR_COMP1LOCK_Pos)

0x80000000

◆ COMP1_CSR_COMP1LOCK_Pos

#define COMP1_CSR_COMP1LOCK_Pos (31U)

◆ COMP1_CSR_COMP1OUT

#define COMP1_CSR_COMP1OUT COMP1_CSR_COMP1OUT_Msk

COMP1 output level

◆ COMP1_CSR_COMP1OUT_Msk

#define COMP1_CSR_COMP1OUT_Msk (0x1UL << COMP1_CSR_COMP1OUT_Pos)

0x40000000

◆ COMP1_CSR_COMP1OUT_Pos

#define COMP1_CSR_COMP1OUT_Pos (30U)

◆ COMP1_CSR_COMP1OUTSEL

#define COMP1_CSR_COMP1OUTSEL COMP1_CSR_COMP1OUTSEL_Msk

COMP1 output select

◆ COMP1_CSR_COMP1OUTSEL_0

#define COMP1_CSR_COMP1OUTSEL_0 (0x1UL << COMP1_CSR_COMP1OUTSEL_Pos)

0x00000400

◆ COMP1_CSR_COMP1OUTSEL_1

#define COMP1_CSR_COMP1OUTSEL_1 (0x2UL << COMP1_CSR_COMP1OUTSEL_Pos)

0x00000800

◆ COMP1_CSR_COMP1OUTSEL_2

#define COMP1_CSR_COMP1OUTSEL_2 (0x4UL << COMP1_CSR_COMP1OUTSEL_Pos)

0x00001000

◆ COMP1_CSR_COMP1OUTSEL_3

#define COMP1_CSR_COMP1OUTSEL_3 (0x8UL << COMP1_CSR_COMP1OUTSEL_Pos)

0x00002000

◆ COMP1_CSR_COMP1OUTSEL_Msk

#define COMP1_CSR_COMP1OUTSEL_Msk (0xFUL << COMP1_CSR_COMP1OUTSEL_Pos)

0x00003C00

◆ COMP1_CSR_COMP1OUTSEL_Pos

#define COMP1_CSR_COMP1OUTSEL_Pos (10U)

◆ COMP1_CSR_COMP1POL

#define COMP1_CSR_COMP1POL COMP1_CSR_COMP1POL_Msk

COMP1 output polarity

◆ COMP1_CSR_COMP1POL_Msk

#define COMP1_CSR_COMP1POL_Msk (0x1UL << COMP1_CSR_COMP1POL_Pos)

0x00008000

◆ COMP1_CSR_COMP1POL_Pos

#define COMP1_CSR_COMP1POL_Pos (15U)

◆ COMP1_CSR_COMP1SW1

#define COMP1_CSR_COMP1SW1 COMP1_CSR_COMP1SW1_Msk

COMP1 SW1 switch control

◆ COMP1_CSR_COMP1SW1_Msk

#define COMP1_CSR_COMP1SW1_Msk (0x1UL << COMP1_CSR_COMP1SW1_Pos)

0x00000002

◆ COMP1_CSR_COMP1SW1_Pos

#define COMP1_CSR_COMP1SW1_Pos (1U)

◆ COMP2_CSR_COMP2BLANKING

#define COMP2_CSR_COMP2BLANKING COMP2_CSR_COMP2BLANKING_Msk

COMP2 blanking

◆ COMP2_CSR_COMP2BLANKING_0

#define COMP2_CSR_COMP2BLANKING_0 (0x1UL << COMP2_CSR_COMP2BLANKING_Pos)

0x00040000

◆ COMP2_CSR_COMP2BLANKING_1

#define COMP2_CSR_COMP2BLANKING_1 (0x2UL << COMP2_CSR_COMP2BLANKING_Pos)

0x00080000

◆ COMP2_CSR_COMP2BLANKING_2

#define COMP2_CSR_COMP2BLANKING_2 (0x4UL << COMP2_CSR_COMP2BLANKING_Pos)

0x00100000

◆ COMP2_CSR_COMP2BLANKING_Msk

#define COMP2_CSR_COMP2BLANKING_Msk (0x3UL << COMP2_CSR_COMP2BLANKING_Pos)

0x000C0000

◆ COMP2_CSR_COMP2BLANKING_Pos

#define COMP2_CSR_COMP2BLANKING_Pos (18U)

◆ COMP2_CSR_COMP2EN

#define COMP2_CSR_COMP2EN COMP2_CSR_COMP2EN_Msk

COMP2 enable

◆ COMP2_CSR_COMP2EN_Msk

#define COMP2_CSR_COMP2EN_Msk (0x1UL << COMP2_CSR_COMP2EN_Pos)

0x00000001

◆ COMP2_CSR_COMP2EN_Pos

#define COMP2_CSR_COMP2EN_Pos (0U)

◆ COMP2_CSR_COMP2INSEL

#define COMP2_CSR_COMP2INSEL COMP2_CSR_COMP2INSEL_Msk

COMP2 inverting input select

◆ COMP2_CSR_COMP2INSEL_0

#define COMP2_CSR_COMP2INSEL_0 (0x00000010U)

COMP2 inverting input select bit 0

◆ COMP2_CSR_COMP2INSEL_1

#define COMP2_CSR_COMP2INSEL_1 (0x00000020U)

COMP2 inverting input select bit 1

◆ COMP2_CSR_COMP2INSEL_2

#define COMP2_CSR_COMP2INSEL_2 (0x00000040U)

COMP2 inverting input select bit 2

◆ COMP2_CSR_COMP2INSEL_Msk

#define COMP2_CSR_COMP2INSEL_Msk (0x7UL << COMP2_CSR_COMP2INSEL_Pos)

0x00000070

◆ COMP2_CSR_COMP2INSEL_Pos

#define COMP2_CSR_COMP2INSEL_Pos (4U)

◆ COMP2_CSR_COMP2LOCK

#define COMP2_CSR_COMP2LOCK COMP2_CSR_COMP2LOCK_Msk

COMP2 lock

◆ COMP2_CSR_COMP2LOCK_Msk

#define COMP2_CSR_COMP2LOCK_Msk (0x1UL << COMP2_CSR_COMP2LOCK_Pos)

0x80000000

◆ COMP2_CSR_COMP2LOCK_Pos

#define COMP2_CSR_COMP2LOCK_Pos (31U)

◆ COMP2_CSR_COMP2OUT

#define COMP2_CSR_COMP2OUT COMP2_CSR_COMP2OUT_Msk

COMP2 output level

◆ COMP2_CSR_COMP2OUT_Msk

#define COMP2_CSR_COMP2OUT_Msk (0x1UL << COMP2_CSR_COMP2OUT_Pos)

0x40000000

◆ COMP2_CSR_COMP2OUT_Pos

#define COMP2_CSR_COMP2OUT_Pos (30U)

◆ COMP2_CSR_COMP2OUTSEL

#define COMP2_CSR_COMP2OUTSEL COMP2_CSR_COMP2OUTSEL_Msk

COMP2 output select

◆ COMP2_CSR_COMP2OUTSEL_0

#define COMP2_CSR_COMP2OUTSEL_0 (0x1UL << COMP2_CSR_COMP2OUTSEL_Pos)

0x00000400

◆ COMP2_CSR_COMP2OUTSEL_1

#define COMP2_CSR_COMP2OUTSEL_1 (0x2UL << COMP2_CSR_COMP2OUTSEL_Pos)

0x00000800

◆ COMP2_CSR_COMP2OUTSEL_2

#define COMP2_CSR_COMP2OUTSEL_2 (0x4UL << COMP2_CSR_COMP2OUTSEL_Pos)

0x00001000

◆ COMP2_CSR_COMP2OUTSEL_3

#define COMP2_CSR_COMP2OUTSEL_3 (0x8UL << COMP2_CSR_COMP2OUTSEL_Pos)

0x00002000

◆ COMP2_CSR_COMP2OUTSEL_Msk

#define COMP2_CSR_COMP2OUTSEL_Msk (0xFUL << COMP2_CSR_COMP2OUTSEL_Pos)

0x00003C00

◆ COMP2_CSR_COMP2OUTSEL_Pos

#define COMP2_CSR_COMP2OUTSEL_Pos (10U)

◆ COMP2_CSR_COMP2POL

#define COMP2_CSR_COMP2POL COMP2_CSR_COMP2POL_Msk

COMP2 output polarity

◆ COMP2_CSR_COMP2POL_Msk

#define COMP2_CSR_COMP2POL_Msk (0x1UL << COMP2_CSR_COMP2POL_Pos)

0x00008000

◆ COMP2_CSR_COMP2POL_Pos

#define COMP2_CSR_COMP2POL_Pos (15U)

◆ COMP3_CSR_COMP3BLANKING

#define COMP3_CSR_COMP3BLANKING COMP3_CSR_COMP3BLANKING_Msk

COMP3 blanking

◆ COMP3_CSR_COMP3BLANKING_0

#define COMP3_CSR_COMP3BLANKING_0 (0x1UL << COMP3_CSR_COMP3BLANKING_Pos)

0x00040000

◆ COMP3_CSR_COMP3BLANKING_1

#define COMP3_CSR_COMP3BLANKING_1 (0x2UL << COMP3_CSR_COMP3BLANKING_Pos)

0x00080000

◆ COMP3_CSR_COMP3BLANKING_2

#define COMP3_CSR_COMP3BLANKING_2 (0x4UL << COMP3_CSR_COMP3BLANKING_Pos)

0x00100000

◆ COMP3_CSR_COMP3BLANKING_Msk

#define COMP3_CSR_COMP3BLANKING_Msk (0x3UL << COMP3_CSR_COMP3BLANKING_Pos)

0x000C0000

◆ COMP3_CSR_COMP3BLANKING_Pos

#define COMP3_CSR_COMP3BLANKING_Pos (18U)

◆ COMP3_CSR_COMP3EN

#define COMP3_CSR_COMP3EN COMP3_CSR_COMP3EN_Msk

COMP3 enable

◆ COMP3_CSR_COMP3EN_Msk

#define COMP3_CSR_COMP3EN_Msk (0x1UL << COMP3_CSR_COMP3EN_Pos)

0x00000001

◆ COMP3_CSR_COMP3EN_Pos

#define COMP3_CSR_COMP3EN_Pos (0U)

◆ COMP3_CSR_COMP3INSEL

#define COMP3_CSR_COMP3INSEL COMP3_CSR_COMP3INSEL_Msk

COMP3 inverting input select

◆ COMP3_CSR_COMP3INSEL_0

#define COMP3_CSR_COMP3INSEL_0 (0x1UL << COMP3_CSR_COMP3INSEL_Pos)

0x00000010

◆ COMP3_CSR_COMP3INSEL_1

#define COMP3_CSR_COMP3INSEL_1 (0x2UL << COMP3_CSR_COMP3INSEL_Pos)

0x00000020

◆ COMP3_CSR_COMP3INSEL_2

#define COMP3_CSR_COMP3INSEL_2 (0x4UL << COMP3_CSR_COMP3INSEL_Pos)

0x00000040

◆ COMP3_CSR_COMP3INSEL_Msk

#define COMP3_CSR_COMP3INSEL_Msk (0x7UL << COMP3_CSR_COMP3INSEL_Pos)

0x00000070

◆ COMP3_CSR_COMP3INSEL_Pos

#define COMP3_CSR_COMP3INSEL_Pos (4U)

◆ COMP3_CSR_COMP3LOCK

#define COMP3_CSR_COMP3LOCK COMP3_CSR_COMP3LOCK_Msk

COMP3 lock

◆ COMP3_CSR_COMP3LOCK_Msk

#define COMP3_CSR_COMP3LOCK_Msk (0x1UL << COMP3_CSR_COMP3LOCK_Pos)

0x80000000

◆ COMP3_CSR_COMP3LOCK_Pos

#define COMP3_CSR_COMP3LOCK_Pos (31U)

◆ COMP3_CSR_COMP3OUT

#define COMP3_CSR_COMP3OUT COMP3_CSR_COMP3OUT_Msk

COMP3 output level

◆ COMP3_CSR_COMP3OUT_Msk

#define COMP3_CSR_COMP3OUT_Msk (0x1UL << COMP3_CSR_COMP3OUT_Pos)

0x40000000

◆ COMP3_CSR_COMP3OUT_Pos

#define COMP3_CSR_COMP3OUT_Pos (30U)

◆ COMP3_CSR_COMP3OUTSEL

#define COMP3_CSR_COMP3OUTSEL COMP3_CSR_COMP3OUTSEL_Msk

COMP3 output select

◆ COMP3_CSR_COMP3OUTSEL_0

#define COMP3_CSR_COMP3OUTSEL_0 (0x1UL << COMP3_CSR_COMP3OUTSEL_Pos)

0x00000400

◆ COMP3_CSR_COMP3OUTSEL_1

#define COMP3_CSR_COMP3OUTSEL_1 (0x2UL << COMP3_CSR_COMP3OUTSEL_Pos)

0x00000800

◆ COMP3_CSR_COMP3OUTSEL_2

#define COMP3_CSR_COMP3OUTSEL_2 (0x4UL << COMP3_CSR_COMP3OUTSEL_Pos)

0x00001000

◆ COMP3_CSR_COMP3OUTSEL_3

#define COMP3_CSR_COMP3OUTSEL_3 (0x8UL << COMP3_CSR_COMP3OUTSEL_Pos)

0x00002000

◆ COMP3_CSR_COMP3OUTSEL_Msk

#define COMP3_CSR_COMP3OUTSEL_Msk (0xFUL << COMP3_CSR_COMP3OUTSEL_Pos)

0x00003C00

◆ COMP3_CSR_COMP3OUTSEL_Pos

#define COMP3_CSR_COMP3OUTSEL_Pos (10U)

◆ COMP3_CSR_COMP3POL

#define COMP3_CSR_COMP3POL COMP3_CSR_COMP3POL_Msk

COMP3 output polarity

◆ COMP3_CSR_COMP3POL_Msk

#define COMP3_CSR_COMP3POL_Msk (0x1UL << COMP3_CSR_COMP3POL_Pos)

0x00008000

◆ COMP3_CSR_COMP3POL_Pos

#define COMP3_CSR_COMP3POL_Pos (15U)

◆ COMP4_CSR_COMP4BLANKING

#define COMP4_CSR_COMP4BLANKING COMP4_CSR_COMP4BLANKING_Msk

COMP4 blanking

◆ COMP4_CSR_COMP4BLANKING_0

#define COMP4_CSR_COMP4BLANKING_0 (0x1UL << COMP4_CSR_COMP4BLANKING_Pos)

0x00040000

◆ COMP4_CSR_COMP4BLANKING_1

#define COMP4_CSR_COMP4BLANKING_1 (0x2UL << COMP4_CSR_COMP4BLANKING_Pos)

0x00080000

◆ COMP4_CSR_COMP4BLANKING_2

#define COMP4_CSR_COMP4BLANKING_2 (0x4UL << COMP4_CSR_COMP4BLANKING_Pos)

0x00100000

◆ COMP4_CSR_COMP4BLANKING_Msk

#define COMP4_CSR_COMP4BLANKING_Msk (0x3UL << COMP4_CSR_COMP4BLANKING_Pos)

0x000C0000

◆ COMP4_CSR_COMP4BLANKING_Pos

#define COMP4_CSR_COMP4BLANKING_Pos (18U)

◆ COMP4_CSR_COMP4EN

#define COMP4_CSR_COMP4EN COMP4_CSR_COMP4EN_Msk

COMP4 enable

◆ COMP4_CSR_COMP4EN_Msk

#define COMP4_CSR_COMP4EN_Msk (0x1UL << COMP4_CSR_COMP4EN_Pos)

0x00000001

◆ COMP4_CSR_COMP4EN_Pos

#define COMP4_CSR_COMP4EN_Pos (0U)

◆ COMP4_CSR_COMP4INSEL

#define COMP4_CSR_COMP4INSEL COMP4_CSR_COMP4INSEL_Msk

COMP4 inverting input select

◆ COMP4_CSR_COMP4INSEL_0

#define COMP4_CSR_COMP4INSEL_0 (0x00000010U)

COMP4 inverting input select bit 0

◆ COMP4_CSR_COMP4INSEL_1

#define COMP4_CSR_COMP4INSEL_1 (0x00000020U)

COMP4 inverting input select bit 1

◆ COMP4_CSR_COMP4INSEL_2

#define COMP4_CSR_COMP4INSEL_2 (0x00000040U)

COMP4 inverting input select bit 2

◆ COMP4_CSR_COMP4INSEL_Msk

#define COMP4_CSR_COMP4INSEL_Msk (0x7UL << COMP4_CSR_COMP4INSEL_Pos)

0x00000070

◆ COMP4_CSR_COMP4INSEL_Pos

#define COMP4_CSR_COMP4INSEL_Pos (4U)

◆ COMP4_CSR_COMP4LOCK

#define COMP4_CSR_COMP4LOCK COMP4_CSR_COMP4LOCK_Msk

COMP4 lock

◆ COMP4_CSR_COMP4LOCK_Msk

#define COMP4_CSR_COMP4LOCK_Msk (0x1UL << COMP4_CSR_COMP4LOCK_Pos)

0x80000000

◆ COMP4_CSR_COMP4LOCK_Pos

#define COMP4_CSR_COMP4LOCK_Pos (31U)

◆ COMP4_CSR_COMP4OUT

#define COMP4_CSR_COMP4OUT COMP4_CSR_COMP4OUT_Msk

COMP4 output level

◆ COMP4_CSR_COMP4OUT_Msk

#define COMP4_CSR_COMP4OUT_Msk (0x1UL << COMP4_CSR_COMP4OUT_Pos)

0x40000000

◆ COMP4_CSR_COMP4OUT_Pos

#define COMP4_CSR_COMP4OUT_Pos (30U)

◆ COMP4_CSR_COMP4OUTSEL

#define COMP4_CSR_COMP4OUTSEL COMP4_CSR_COMP4OUTSEL_Msk

COMP4 output select

◆ COMP4_CSR_COMP4OUTSEL_0

#define COMP4_CSR_COMP4OUTSEL_0 (0x1UL << COMP4_CSR_COMP4OUTSEL_Pos)

0x00000400

◆ COMP4_CSR_COMP4OUTSEL_1

#define COMP4_CSR_COMP4OUTSEL_1 (0x2UL << COMP4_CSR_COMP4OUTSEL_Pos)

0x00000800

◆ COMP4_CSR_COMP4OUTSEL_2

#define COMP4_CSR_COMP4OUTSEL_2 (0x4UL << COMP4_CSR_COMP4OUTSEL_Pos)

0x00001000

◆ COMP4_CSR_COMP4OUTSEL_3

#define COMP4_CSR_COMP4OUTSEL_3 (0x8UL << COMP4_CSR_COMP4OUTSEL_Pos)

0x00002000

◆ COMP4_CSR_COMP4OUTSEL_Msk

#define COMP4_CSR_COMP4OUTSEL_Msk (0xFUL << COMP4_CSR_COMP4OUTSEL_Pos)

0x00003C00

◆ COMP4_CSR_COMP4OUTSEL_Pos

#define COMP4_CSR_COMP4OUTSEL_Pos (10U)

◆ COMP4_CSR_COMP4POL

#define COMP4_CSR_COMP4POL COMP4_CSR_COMP4POL_Msk

COMP4 output polarity

◆ COMP4_CSR_COMP4POL_Msk

#define COMP4_CSR_COMP4POL_Msk (0x1UL << COMP4_CSR_COMP4POL_Pos)

0x00008000

◆ COMP4_CSR_COMP4POL_Pos

#define COMP4_CSR_COMP4POL_Pos (15U)

◆ COMP5_CSR_COMP5BLANKING

#define COMP5_CSR_COMP5BLANKING COMP5_CSR_COMP5BLANKING_Msk

COMP5 blanking

◆ COMP5_CSR_COMP5BLANKING_0

#define COMP5_CSR_COMP5BLANKING_0 (0x1UL << COMP5_CSR_COMP5BLANKING_Pos)

0x00040000

◆ COMP5_CSR_COMP5BLANKING_1

#define COMP5_CSR_COMP5BLANKING_1 (0x2UL << COMP5_CSR_COMP5BLANKING_Pos)

0x00080000

◆ COMP5_CSR_COMP5BLANKING_2

#define COMP5_CSR_COMP5BLANKING_2 (0x4UL << COMP5_CSR_COMP5BLANKING_Pos)

0x00100000

◆ COMP5_CSR_COMP5BLANKING_Msk

#define COMP5_CSR_COMP5BLANKING_Msk (0x3UL << COMP5_CSR_COMP5BLANKING_Pos)

0x000C0000

◆ COMP5_CSR_COMP5BLANKING_Pos

#define COMP5_CSR_COMP5BLANKING_Pos (18U)

◆ COMP5_CSR_COMP5EN

#define COMP5_CSR_COMP5EN COMP5_CSR_COMP5EN_Msk

COMP5 enable

◆ COMP5_CSR_COMP5EN_Msk

#define COMP5_CSR_COMP5EN_Msk (0x1UL << COMP5_CSR_COMP5EN_Pos)

0x00000001

◆ COMP5_CSR_COMP5EN_Pos

#define COMP5_CSR_COMP5EN_Pos (0U)

◆ COMP5_CSR_COMP5INSEL

#define COMP5_CSR_COMP5INSEL COMP5_CSR_COMP5INSEL_Msk

COMP5 inverting input select

◆ COMP5_CSR_COMP5INSEL_0

#define COMP5_CSR_COMP5INSEL_0 (0x1UL << COMP5_CSR_COMP5INSEL_Pos)

0x00000010

◆ COMP5_CSR_COMP5INSEL_1

#define COMP5_CSR_COMP5INSEL_1 (0x2UL << COMP5_CSR_COMP5INSEL_Pos)

0x00000020

◆ COMP5_CSR_COMP5INSEL_2

#define COMP5_CSR_COMP5INSEL_2 (0x4UL << COMP5_CSR_COMP5INSEL_Pos)

0x00000040

◆ COMP5_CSR_COMP5INSEL_Msk

#define COMP5_CSR_COMP5INSEL_Msk (0x7UL << COMP5_CSR_COMP5INSEL_Pos)

0x00000070

◆ COMP5_CSR_COMP5INSEL_Pos

#define COMP5_CSR_COMP5INSEL_Pos (4U)

◆ COMP5_CSR_COMP5LOCK

#define COMP5_CSR_COMP5LOCK COMP5_CSR_COMP5LOCK_Msk

COMP5 lock

◆ COMP5_CSR_COMP5LOCK_Msk

#define COMP5_CSR_COMP5LOCK_Msk (0x1UL << COMP5_CSR_COMP5LOCK_Pos)

0x80000000

◆ COMP5_CSR_COMP5LOCK_Pos

#define COMP5_CSR_COMP5LOCK_Pos (31U)

◆ COMP5_CSR_COMP5OUT

#define COMP5_CSR_COMP5OUT COMP5_CSR_COMP5OUT_Msk

COMP5 output level

◆ COMP5_CSR_COMP5OUT_Msk

#define COMP5_CSR_COMP5OUT_Msk (0x1UL << COMP5_CSR_COMP5OUT_Pos)

0x40000000

◆ COMP5_CSR_COMP5OUT_Pos

#define COMP5_CSR_COMP5OUT_Pos (30U)

◆ COMP5_CSR_COMP5OUTSEL

#define COMP5_CSR_COMP5OUTSEL COMP5_CSR_COMP5OUTSEL_Msk

COMP5 output select

◆ COMP5_CSR_COMP5OUTSEL_0

#define COMP5_CSR_COMP5OUTSEL_0 (0x1UL << COMP5_CSR_COMP5OUTSEL_Pos)

0x00000400

◆ COMP5_CSR_COMP5OUTSEL_1

#define COMP5_CSR_COMP5OUTSEL_1 (0x2UL << COMP5_CSR_COMP5OUTSEL_Pos)

0x00000800

◆ COMP5_CSR_COMP5OUTSEL_2

#define COMP5_CSR_COMP5OUTSEL_2 (0x4UL << COMP5_CSR_COMP5OUTSEL_Pos)

0x00001000

◆ COMP5_CSR_COMP5OUTSEL_3

#define COMP5_CSR_COMP5OUTSEL_3 (0x8UL << COMP5_CSR_COMP5OUTSEL_Pos)

0x00002000

◆ COMP5_CSR_COMP5OUTSEL_Msk

#define COMP5_CSR_COMP5OUTSEL_Msk (0xFUL << COMP5_CSR_COMP5OUTSEL_Pos)

0x00003C00

◆ COMP5_CSR_COMP5OUTSEL_Pos

#define COMP5_CSR_COMP5OUTSEL_Pos (10U)

◆ COMP5_CSR_COMP5POL

#define COMP5_CSR_COMP5POL COMP5_CSR_COMP5POL_Msk

COMP5 output polarity

◆ COMP5_CSR_COMP5POL_Msk

#define COMP5_CSR_COMP5POL_Msk (0x1UL << COMP5_CSR_COMP5POL_Pos)

0x00008000

◆ COMP5_CSR_COMP5POL_Pos

#define COMP5_CSR_COMP5POL_Pos (15U)

◆ COMP6_CSR_COMP6BLANKING

#define COMP6_CSR_COMP6BLANKING COMP6_CSR_COMP6BLANKING_Msk

COMP6 blanking

◆ COMP6_CSR_COMP6BLANKING_0

#define COMP6_CSR_COMP6BLANKING_0 (0x1UL << COMP6_CSR_COMP6BLANKING_Pos)

0x00040000

◆ COMP6_CSR_COMP6BLANKING_1

#define COMP6_CSR_COMP6BLANKING_1 (0x2UL << COMP6_CSR_COMP6BLANKING_Pos)

0x00080000

◆ COMP6_CSR_COMP6BLANKING_2

#define COMP6_CSR_COMP6BLANKING_2 (0x4UL << COMP6_CSR_COMP6BLANKING_Pos)

0x00100000

◆ COMP6_CSR_COMP6BLANKING_Msk

#define COMP6_CSR_COMP6BLANKING_Msk (0x3UL << COMP6_CSR_COMP6BLANKING_Pos)

0x000C0000

◆ COMP6_CSR_COMP6BLANKING_Pos

#define COMP6_CSR_COMP6BLANKING_Pos (18U)

◆ COMP6_CSR_COMP6EN

#define COMP6_CSR_COMP6EN COMP6_CSR_COMP6EN_Msk

COMP6 enable

◆ COMP6_CSR_COMP6EN_Msk

#define COMP6_CSR_COMP6EN_Msk (0x1UL << COMP6_CSR_COMP6EN_Pos)

0x00000001

◆ COMP6_CSR_COMP6EN_Pos

#define COMP6_CSR_COMP6EN_Pos (0U)

◆ COMP6_CSR_COMP6INSEL

#define COMP6_CSR_COMP6INSEL COMP6_CSR_COMP6INSEL_Msk

COMP6 inverting input select

◆ COMP6_CSR_COMP6INSEL_0

#define COMP6_CSR_COMP6INSEL_0 (0x00000010U)

COMP6 inverting input select bit 0

◆ COMP6_CSR_COMP6INSEL_1

#define COMP6_CSR_COMP6INSEL_1 (0x00000020U)

COMP6 inverting input select bit 1

◆ COMP6_CSR_COMP6INSEL_2

#define COMP6_CSR_COMP6INSEL_2 (0x00000040U)

COMP6 inverting input select bit 2

◆ COMP6_CSR_COMP6INSEL_Msk

#define COMP6_CSR_COMP6INSEL_Msk (0x7UL << COMP6_CSR_COMP6INSEL_Pos)

0x00000070

◆ COMP6_CSR_COMP6INSEL_Pos

#define COMP6_CSR_COMP6INSEL_Pos (4U)

◆ COMP6_CSR_COMP6LOCK

#define COMP6_CSR_COMP6LOCK COMP6_CSR_COMP6LOCK_Msk

COMP6 lock

◆ COMP6_CSR_COMP6LOCK_Msk

#define COMP6_CSR_COMP6LOCK_Msk (0x1UL << COMP6_CSR_COMP6LOCK_Pos)

0x80000000

◆ COMP6_CSR_COMP6LOCK_Pos

#define COMP6_CSR_COMP6LOCK_Pos (31U)

◆ COMP6_CSR_COMP6OUT

#define COMP6_CSR_COMP6OUT COMP6_CSR_COMP6OUT_Msk

COMP6 output level

◆ COMP6_CSR_COMP6OUT_Msk

#define COMP6_CSR_COMP6OUT_Msk (0x1UL << COMP6_CSR_COMP6OUT_Pos)

0x40000000

◆ COMP6_CSR_COMP6OUT_Pos

#define COMP6_CSR_COMP6OUT_Pos (30U)

◆ COMP6_CSR_COMP6OUTSEL

#define COMP6_CSR_COMP6OUTSEL COMP6_CSR_COMP6OUTSEL_Msk

COMP6 output select

◆ COMP6_CSR_COMP6OUTSEL_0

#define COMP6_CSR_COMP6OUTSEL_0 (0x1UL << COMP6_CSR_COMP6OUTSEL_Pos)

0x00000400

◆ COMP6_CSR_COMP6OUTSEL_1

#define COMP6_CSR_COMP6OUTSEL_1 (0x2UL << COMP6_CSR_COMP6OUTSEL_Pos)

0x00000800

◆ COMP6_CSR_COMP6OUTSEL_2

#define COMP6_CSR_COMP6OUTSEL_2 (0x4UL << COMP6_CSR_COMP6OUTSEL_Pos)

0x00001000

◆ COMP6_CSR_COMP6OUTSEL_3

#define COMP6_CSR_COMP6OUTSEL_3 (0x8UL << COMP6_CSR_COMP6OUTSEL_Pos)

0x00002000

◆ COMP6_CSR_COMP6OUTSEL_Msk

#define COMP6_CSR_COMP6OUTSEL_Msk (0xFUL << COMP6_CSR_COMP6OUTSEL_Pos)

0x00003C00

◆ COMP6_CSR_COMP6OUTSEL_Pos

#define COMP6_CSR_COMP6OUTSEL_Pos (10U)

◆ COMP6_CSR_COMP6POL

#define COMP6_CSR_COMP6POL COMP6_CSR_COMP6POL_Msk

COMP6 output polarity

◆ COMP6_CSR_COMP6POL_Msk

#define COMP6_CSR_COMP6POL_Msk (0x1UL << COMP6_CSR_COMP6POL_Pos)

0x00008000

◆ COMP6_CSR_COMP6POL_Pos

#define COMP6_CSR_COMP6POL_Pos (15U)

◆ COMP7_CSR_COMP7BLANKING

#define COMP7_CSR_COMP7BLANKING COMP7_CSR_COMP7BLANKING_Msk

COMP7 blanking

◆ COMP7_CSR_COMP7BLANKING_0

#define COMP7_CSR_COMP7BLANKING_0 (0x1UL << COMP7_CSR_COMP7BLANKING_Pos)

0x00040000

◆ COMP7_CSR_COMP7BLANKING_1

#define COMP7_CSR_COMP7BLANKING_1 (0x2UL << COMP7_CSR_COMP7BLANKING_Pos)

0x00080000

◆ COMP7_CSR_COMP7BLANKING_2

#define COMP7_CSR_COMP7BLANKING_2 (0x4UL << COMP7_CSR_COMP7BLANKING_Pos)

0x00100000

◆ COMP7_CSR_COMP7BLANKING_Msk

#define COMP7_CSR_COMP7BLANKING_Msk (0x3UL << COMP7_CSR_COMP7BLANKING_Pos)

0x000C0000

◆ COMP7_CSR_COMP7BLANKING_Pos

#define COMP7_CSR_COMP7BLANKING_Pos (18U)

◆ COMP7_CSR_COMP7EN

#define COMP7_CSR_COMP7EN COMP7_CSR_COMP7EN_Msk

COMP7 enable

◆ COMP7_CSR_COMP7EN_Msk

#define COMP7_CSR_COMP7EN_Msk (0x1UL << COMP7_CSR_COMP7EN_Pos)

0x00000001

◆ COMP7_CSR_COMP7EN_Pos

#define COMP7_CSR_COMP7EN_Pos (0U)

◆ COMP7_CSR_COMP7INSEL

#define COMP7_CSR_COMP7INSEL COMP7_CSR_COMP7INSEL_Msk

COMP7 inverting input select

◆ COMP7_CSR_COMP7INSEL_0

#define COMP7_CSR_COMP7INSEL_0 (0x1UL << COMP7_CSR_COMP7INSEL_Pos)

0x00000010

◆ COMP7_CSR_COMP7INSEL_1

#define COMP7_CSR_COMP7INSEL_1 (0x2UL << COMP7_CSR_COMP7INSEL_Pos)

0x00000020

◆ COMP7_CSR_COMP7INSEL_2

#define COMP7_CSR_COMP7INSEL_2 (0x4UL << COMP7_CSR_COMP7INSEL_Pos)

0x00000040

◆ COMP7_CSR_COMP7INSEL_Msk

#define COMP7_CSR_COMP7INSEL_Msk (0x7UL << COMP7_CSR_COMP7INSEL_Pos)

0x00000070

◆ COMP7_CSR_COMP7INSEL_Pos

#define COMP7_CSR_COMP7INSEL_Pos (4U)

◆ COMP7_CSR_COMP7LOCK

#define COMP7_CSR_COMP7LOCK COMP7_CSR_COMP7LOCK_Msk

COMP7 lock

◆ COMP7_CSR_COMP7LOCK_Msk

#define COMP7_CSR_COMP7LOCK_Msk (0x1UL << COMP7_CSR_COMP7LOCK_Pos)

0x80000000

◆ COMP7_CSR_COMP7LOCK_Pos

#define COMP7_CSR_COMP7LOCK_Pos (31U)

◆ COMP7_CSR_COMP7OUT

#define COMP7_CSR_COMP7OUT COMP7_CSR_COMP7OUT_Msk

COMP7 output level

◆ COMP7_CSR_COMP7OUT_Msk

#define COMP7_CSR_COMP7OUT_Msk (0x1UL << COMP7_CSR_COMP7OUT_Pos)

0x40000000

◆ COMP7_CSR_COMP7OUT_Pos

#define COMP7_CSR_COMP7OUT_Pos (30U)

◆ COMP7_CSR_COMP7OUTSEL

#define COMP7_CSR_COMP7OUTSEL COMP7_CSR_COMP7OUTSEL_Msk

COMP7 output select

◆ COMP7_CSR_COMP7OUTSEL_0

#define COMP7_CSR_COMP7OUTSEL_0 (0x1UL << COMP7_CSR_COMP7OUTSEL_Pos)

0x00000400

◆ COMP7_CSR_COMP7OUTSEL_1

#define COMP7_CSR_COMP7OUTSEL_1 (0x2UL << COMP7_CSR_COMP7OUTSEL_Pos)

0x00000800

◆ COMP7_CSR_COMP7OUTSEL_2

#define COMP7_CSR_COMP7OUTSEL_2 (0x4UL << COMP7_CSR_COMP7OUTSEL_Pos)

0x00001000

◆ COMP7_CSR_COMP7OUTSEL_3

#define COMP7_CSR_COMP7OUTSEL_3 (0x8UL << COMP7_CSR_COMP7OUTSEL_Pos)

0x00002000

◆ COMP7_CSR_COMP7OUTSEL_Msk

#define COMP7_CSR_COMP7OUTSEL_Msk (0xFUL << COMP7_CSR_COMP7OUTSEL_Pos)

0x00003C00

◆ COMP7_CSR_COMP7OUTSEL_Pos

#define COMP7_CSR_COMP7OUTSEL_Pos (10U)

◆ COMP7_CSR_COMP7POL

#define COMP7_CSR_COMP7POL COMP7_CSR_COMP7POL_Msk

COMP7 output polarity

◆ COMP7_CSR_COMP7POL_Msk

#define COMP7_CSR_COMP7POL_Msk (0x1UL << COMP7_CSR_COMP7POL_Pos)

0x00008000

◆ COMP7_CSR_COMP7POL_Pos

#define COMP7_CSR_COMP7POL_Pos (15U)

◆ COMP_CSR_COMP1SW1

#define COMP_CSR_COMP1SW1 COMP1_CSR_COMP1SW1

◆ COMP_CSR_COMPxBLANKING

#define COMP_CSR_COMPxBLANKING COMP_CSR_COMPxBLANKING_Msk

COMPx blanking

◆ COMP_CSR_COMPxBLANKING_0

#define COMP_CSR_COMPxBLANKING_0 (0x1UL << COMP_CSR_COMPxBLANKING_Pos)

0x00040000

◆ COMP_CSR_COMPxBLANKING_1

#define COMP_CSR_COMPxBLANKING_1 (0x2UL << COMP_CSR_COMPxBLANKING_Pos)

0x00080000

◆ COMP_CSR_COMPxBLANKING_2

#define COMP_CSR_COMPxBLANKING_2 (0x4UL << COMP_CSR_COMPxBLANKING_Pos)

0x00100000

◆ COMP_CSR_COMPxBLANKING_Msk

#define COMP_CSR_COMPxBLANKING_Msk (0x3UL << COMP_CSR_COMPxBLANKING_Pos)

0x000C0000

◆ COMP_CSR_COMPxBLANKING_Pos

#define COMP_CSR_COMPxBLANKING_Pos (18U)

◆ COMP_CSR_COMPxEN

#define COMP_CSR_COMPxEN COMP_CSR_COMPxEN_Msk

COMPx enable

◆ COMP_CSR_COMPxEN_Msk

#define COMP_CSR_COMPxEN_Msk (0x1UL << COMP_CSR_COMPxEN_Pos)

0x00000001

◆ COMP_CSR_COMPxEN_Pos

#define COMP_CSR_COMPxEN_Pos (0U)

◆ COMP_CSR_COMPxINSEL

#define COMP_CSR_COMPxINSEL COMP_CSR_COMPxINSEL_Msk

COMPx inverting input select

◆ COMP_CSR_COMPxINSEL_0

#define COMP_CSR_COMPxINSEL_0 (0x00000010U)

COMPx inverting input select bit 0

◆ COMP_CSR_COMPxINSEL_1

#define COMP_CSR_COMPxINSEL_1 (0x00000020U)

COMPx inverting input select bit 1

◆ COMP_CSR_COMPxINSEL_2

#define COMP_CSR_COMPxINSEL_2 (0x00000040U)

COMPx inverting input select bit 2

◆ COMP_CSR_COMPxINSEL_Msk

#define COMP_CSR_COMPxINSEL_Msk (0x7UL << COMP_CSR_COMPxINSEL_Pos)

0x00000070

◆ COMP_CSR_COMPxINSEL_Pos

#define COMP_CSR_COMPxINSEL_Pos (4U)

◆ COMP_CSR_COMPxLOCK

#define COMP_CSR_COMPxLOCK COMP_CSR_COMPxLOCK_Msk

COMPx lock

◆ COMP_CSR_COMPxLOCK_Msk

#define COMP_CSR_COMPxLOCK_Msk (0x1UL << COMP_CSR_COMPxLOCK_Pos)

0x80000000

◆ COMP_CSR_COMPxLOCK_Pos

#define COMP_CSR_COMPxLOCK_Pos (31U)

◆ COMP_CSR_COMPxOUT

#define COMP_CSR_COMPxOUT COMP_CSR_COMPxOUT_Msk

COMPx output level

◆ COMP_CSR_COMPxOUT_Msk

#define COMP_CSR_COMPxOUT_Msk (0x1UL << COMP_CSR_COMPxOUT_Pos)

0x40000000

◆ COMP_CSR_COMPxOUT_Pos

#define COMP_CSR_COMPxOUT_Pos (30U)

◆ COMP_CSR_COMPxOUTSEL

#define COMP_CSR_COMPxOUTSEL COMP_CSR_COMPxOUTSEL_Msk

COMPx output select

◆ COMP_CSR_COMPxOUTSEL_0

#define COMP_CSR_COMPxOUTSEL_0 (0x1UL << COMP_CSR_COMPxOUTSEL_Pos)

0x00000400

◆ COMP_CSR_COMPxOUTSEL_1

#define COMP_CSR_COMPxOUTSEL_1 (0x2UL << COMP_CSR_COMPxOUTSEL_Pos)

0x00000800

◆ COMP_CSR_COMPxOUTSEL_2

#define COMP_CSR_COMPxOUTSEL_2 (0x4UL << COMP_CSR_COMPxOUTSEL_Pos)

0x00001000

◆ COMP_CSR_COMPxOUTSEL_3

#define COMP_CSR_COMPxOUTSEL_3 (0x8UL << COMP_CSR_COMPxOUTSEL_Pos)

0x00002000

◆ COMP_CSR_COMPxOUTSEL_Msk

#define COMP_CSR_COMPxOUTSEL_Msk (0xFUL << COMP_CSR_COMPxOUTSEL_Pos)

0x00003C00

◆ COMP_CSR_COMPxOUTSEL_Pos

#define COMP_CSR_COMPxOUTSEL_Pos (10U)

◆ COMP_CSR_COMPxPOL

#define COMP_CSR_COMPxPOL COMP_CSR_COMPxPOL_Msk

COMPx output polarity

◆ COMP_CSR_COMPxPOL_Msk

#define COMP_CSR_COMPxPOL_Msk (0x1UL << COMP_CSR_COMPxPOL_Pos)

0x00008000

◆ COMP_CSR_COMPxPOL_Pos

#define COMP_CSR_COMPxPOL_Pos (15U)

◆ COMP_CSR_COMPxSW1

#define COMP_CSR_COMPxSW1 COMP_CSR_COMPxSW1_Msk

COMPx SW1 switch control

◆ COMP_CSR_COMPxSW1_Msk

#define COMP_CSR_COMPxSW1_Msk (0x1UL << COMP_CSR_COMPxSW1_Pos)

0x00000002

◆ COMP_CSR_COMPxSW1_Pos

#define COMP_CSR_COMPxSW1_Pos (1U)

◆ COMP_V1_3_0_0

#define COMP_V1_3_0_0

Comparator IP version

◆ CRC_CR_POLYSIZE

#define CRC_CR_POLYSIZE CRC_CR_POLYSIZE_Msk

Polynomial size bits

◆ CRC_CR_POLYSIZE_0

#define CRC_CR_POLYSIZE_0 (0x1UL << CRC_CR_POLYSIZE_Pos)

0x00000008

◆ CRC_CR_POLYSIZE_1

#define CRC_CR_POLYSIZE_1 (0x2UL << CRC_CR_POLYSIZE_Pos)

0x00000010

◆ CRC_CR_POLYSIZE_Msk

#define CRC_CR_POLYSIZE_Msk (0x3UL << CRC_CR_POLYSIZE_Pos)

0x00000018

◆ CRC_CR_POLYSIZE_Pos

#define CRC_CR_POLYSIZE_Pos (3U)

◆ CRC_CR_RESET

#define CRC_CR_RESET CRC_CR_RESET_Msk

RESET the CRC computation unit bit

◆ CRC_CR_RESET_Msk

#define CRC_CR_RESET_Msk (0x1UL << CRC_CR_RESET_Pos)

0x00000001

◆ CRC_CR_RESET_Pos

#define CRC_CR_RESET_Pos (0U)

◆ CRC_CR_REV_IN

#define CRC_CR_REV_IN CRC_CR_REV_IN_Msk

REV_IN Reverse Input Data bits

◆ CRC_CR_REV_IN_0

#define CRC_CR_REV_IN_0 (0x1UL << CRC_CR_REV_IN_Pos)

0x00000020

◆ CRC_CR_REV_IN_1

#define CRC_CR_REV_IN_1 (0x2UL << CRC_CR_REV_IN_Pos)

0x00000040

◆ CRC_CR_REV_IN_Msk

#define CRC_CR_REV_IN_Msk (0x3UL << CRC_CR_REV_IN_Pos)

0x00000060

◆ CRC_CR_REV_IN_Pos

#define CRC_CR_REV_IN_Pos (5U)

◆ CRC_CR_REV_OUT

#define CRC_CR_REV_OUT CRC_CR_REV_OUT_Msk

REV_OUT Reverse Output Data bits

◆ CRC_CR_REV_OUT_Msk

#define CRC_CR_REV_OUT_Msk (0x1UL << CRC_CR_REV_OUT_Pos)

0x00000080

◆ CRC_CR_REV_OUT_Pos

#define CRC_CR_REV_OUT_Pos (7U)

◆ CRC_DR_DR

#define CRC_DR_DR CRC_DR_DR_Msk

Data register bits

◆ CRC_DR_DR_Msk

#define CRC_DR_DR_Msk (0xFFFFFFFFUL << CRC_DR_DR_Pos)

0xFFFFFFFF

◆ CRC_DR_DR_Pos

#define CRC_DR_DR_Pos (0U)

◆ CRC_IDR_IDR

#define CRC_IDR_IDR ((uint8_t)0xFFU)

General-purpose 8-bit data register bits

◆ CRC_INIT_INIT

#define CRC_INIT_INIT CRC_INIT_INIT_Msk

Initial CRC value bits

◆ CRC_INIT_INIT_Msk

#define CRC_INIT_INIT_Msk (0xFFFFFFFFUL << CRC_INIT_INIT_Pos)

0xFFFFFFFF

◆ CRC_INIT_INIT_Pos

#define CRC_INIT_INIT_Pos (0U)

◆ CRC_POL_POL

#define CRC_POL_POL CRC_POL_POL_Msk

Coefficients of the polynomial

◆ CRC_POL_POL_Msk

#define CRC_POL_POL_Msk (0xFFFFFFFFUL << CRC_POL_POL_Pos)

0xFFFFFFFF

◆ CRC_POL_POL_Pos

#define CRC_POL_POL_Pos (0U)

◆ DAC_CHANNEL2_SUPPORT

#define DAC_CHANNEL2_SUPPORT

DAC feature available only on specific devices: DAC channel 2 available (may not be available on all DAC instances DACx)

◆ DAC_CR_BOFF1

#define DAC_CR_BOFF1 DAC_CR_BOFF1_Msk

DAC channel1 output buffer disable

◆ DAC_CR_BOFF1_Msk

#define DAC_CR_BOFF1_Msk (0x1UL << DAC_CR_BOFF1_Pos)

0x00000002

◆ DAC_CR_BOFF1_Pos

#define DAC_CR_BOFF1_Pos (1U)

◆ DAC_CR_BOFF2

#define DAC_CR_BOFF2 DAC_CR_BOFF2_Msk

DAC channel2 output buffer disable

◆ DAC_CR_BOFF2_Msk

#define DAC_CR_BOFF2_Msk (0x1UL << DAC_CR_BOFF2_Pos)

0x00020000

◆ DAC_CR_BOFF2_Pos

#define DAC_CR_BOFF2_Pos (17U)

◆ DAC_CR_DMAEN1

#define DAC_CR_DMAEN1 DAC_CR_DMAEN1_Msk

DAC channel1 DMA enable

◆ DAC_CR_DMAEN1_Msk

#define DAC_CR_DMAEN1_Msk (0x1UL << DAC_CR_DMAEN1_Pos)

0x00001000

◆ DAC_CR_DMAEN1_Pos

#define DAC_CR_DMAEN1_Pos (12U)

◆ DAC_CR_DMAEN2

#define DAC_CR_DMAEN2 DAC_CR_DMAEN2_Msk

DAC channel2 DMA enabled

◆ DAC_CR_DMAEN2_Msk

#define DAC_CR_DMAEN2_Msk (0x1UL << DAC_CR_DMAEN2_Pos)

0x10000000

◆ DAC_CR_DMAEN2_Pos

#define DAC_CR_DMAEN2_Pos (28U)

◆ DAC_CR_DMAUDRIE1

#define DAC_CR_DMAUDRIE1 DAC_CR_DMAUDRIE1_Msk

DAC channel1 DMA underrun IT enable

◆ DAC_CR_DMAUDRIE1_Msk

#define DAC_CR_DMAUDRIE1_Msk (0x1UL << DAC_CR_DMAUDRIE1_Pos)

0x00002000

◆ DAC_CR_DMAUDRIE1_Pos

#define DAC_CR_DMAUDRIE1_Pos (13U)

◆ DAC_CR_DMAUDRIE2

#define DAC_CR_DMAUDRIE2 DAC_CR_DMAUDRIE2_Msk

DAC channel2 DMA underrun IT enable

◆ DAC_CR_DMAUDRIE2_Msk

#define DAC_CR_DMAUDRIE2_Msk (0x1UL << DAC_CR_DMAUDRIE2_Pos)

0x20000000

◆ DAC_CR_DMAUDRIE2_Pos

#define DAC_CR_DMAUDRIE2_Pos (29U)

◆ DAC_CR_EN1

#define DAC_CR_EN1 DAC_CR_EN1_Msk

DAC channel1 enable

◆ DAC_CR_EN1_Msk

#define DAC_CR_EN1_Msk (0x1UL << DAC_CR_EN1_Pos)

0x00000001

◆ DAC_CR_EN1_Pos

#define DAC_CR_EN1_Pos (0U)

◆ DAC_CR_EN2

#define DAC_CR_EN2 DAC_CR_EN2_Msk

DAC channel2 enable

◆ DAC_CR_EN2_Msk

#define DAC_CR_EN2_Msk (0x1UL << DAC_CR_EN2_Pos)

0x00010000

◆ DAC_CR_EN2_Pos

#define DAC_CR_EN2_Pos (16U)

◆ DAC_CR_MAMP1

#define DAC_CR_MAMP1 DAC_CR_MAMP1_Msk

MAMP1[3:0] (DAC channel1 Mask/Amplitude selector)

◆ DAC_CR_MAMP1_0

#define DAC_CR_MAMP1_0 (0x1UL << DAC_CR_MAMP1_Pos)

0x00000100

◆ DAC_CR_MAMP1_1

#define DAC_CR_MAMP1_1 (0x2UL << DAC_CR_MAMP1_Pos)

0x00000200

◆ DAC_CR_MAMP1_2

#define DAC_CR_MAMP1_2 (0x4UL << DAC_CR_MAMP1_Pos)

0x00000400

◆ DAC_CR_MAMP1_3

#define DAC_CR_MAMP1_3 (0x8UL << DAC_CR_MAMP1_Pos)

0x00000800

◆ DAC_CR_MAMP1_Msk

#define DAC_CR_MAMP1_Msk (0xFUL << DAC_CR_MAMP1_Pos)

0x00000F00

◆ DAC_CR_MAMP1_Pos

#define DAC_CR_MAMP1_Pos (8U)

◆ DAC_CR_MAMP2

#define DAC_CR_MAMP2 DAC_CR_MAMP2_Msk

MAMP2[3:0] (DAC channel2 Mask/Amplitude selector)

◆ DAC_CR_MAMP2_0

#define DAC_CR_MAMP2_0 (0x1UL << DAC_CR_MAMP2_Pos)

0x01000000

◆ DAC_CR_MAMP2_1

#define DAC_CR_MAMP2_1 (0x2UL << DAC_CR_MAMP2_Pos)

0x02000000

◆ DAC_CR_MAMP2_2

#define DAC_CR_MAMP2_2 (0x4UL << DAC_CR_MAMP2_Pos)

0x04000000

◆ DAC_CR_MAMP2_3

#define DAC_CR_MAMP2_3 (0x8UL << DAC_CR_MAMP2_Pos)

0x08000000

◆ DAC_CR_MAMP2_Msk

#define DAC_CR_MAMP2_Msk (0xFUL << DAC_CR_MAMP2_Pos)

0x0F000000

◆ DAC_CR_MAMP2_Pos

#define DAC_CR_MAMP2_Pos (24U)

◆ DAC_CR_TEN1

#define DAC_CR_TEN1 DAC_CR_TEN1_Msk

DAC channel1 Trigger enable

◆ DAC_CR_TEN1_Msk

#define DAC_CR_TEN1_Msk (0x1UL << DAC_CR_TEN1_Pos)

0x00000004

◆ DAC_CR_TEN1_Pos

#define DAC_CR_TEN1_Pos (2U)

◆ DAC_CR_TEN2

#define DAC_CR_TEN2 DAC_CR_TEN2_Msk

DAC channel2 Trigger enable

◆ DAC_CR_TEN2_Msk

#define DAC_CR_TEN2_Msk (0x1UL << DAC_CR_TEN2_Pos)

0x00040000

◆ DAC_CR_TEN2_Pos

#define DAC_CR_TEN2_Pos (18U)

◆ DAC_CR_TSEL1

#define DAC_CR_TSEL1 DAC_CR_TSEL1_Msk

TSEL1[2:0] (DAC channel1 Trigger selection)

◆ DAC_CR_TSEL1_0

#define DAC_CR_TSEL1_0 (0x1UL << DAC_CR_TSEL1_Pos)

0x00000008

◆ DAC_CR_TSEL1_1

#define DAC_CR_TSEL1_1 (0x2UL << DAC_CR_TSEL1_Pos)

0x00000010

◆ DAC_CR_TSEL1_2

#define DAC_CR_TSEL1_2 (0x4UL << DAC_CR_TSEL1_Pos)

0x00000020

◆ DAC_CR_TSEL1_Msk

#define DAC_CR_TSEL1_Msk (0x7UL << DAC_CR_TSEL1_Pos)

0x00000038

◆ DAC_CR_TSEL1_Pos

#define DAC_CR_TSEL1_Pos (3U)

◆ DAC_CR_TSEL2

#define DAC_CR_TSEL2 DAC_CR_TSEL2_Msk

TSEL2[2:0] (DAC channel2 Trigger selection)

◆ DAC_CR_TSEL2_0

#define DAC_CR_TSEL2_0 (0x1UL << DAC_CR_TSEL2_Pos)

0x00080000

◆ DAC_CR_TSEL2_1

#define DAC_CR_TSEL2_1 (0x2UL << DAC_CR_TSEL2_Pos)

0x00100000

◆ DAC_CR_TSEL2_2

#define DAC_CR_TSEL2_2 (0x4UL << DAC_CR_TSEL2_Pos)

0x00200000

◆ DAC_CR_TSEL2_Msk

#define DAC_CR_TSEL2_Msk (0x7UL << DAC_CR_TSEL2_Pos)

0x00380000

◆ DAC_CR_TSEL2_Pos

#define DAC_CR_TSEL2_Pos (19U)

◆ DAC_CR_WAVE1

#define DAC_CR_WAVE1 DAC_CR_WAVE1_Msk

WAVE1[1:0] (DAC channel1 noise/triangle wave generation enable)

◆ DAC_CR_WAVE1_0

#define DAC_CR_WAVE1_0 (0x1UL << DAC_CR_WAVE1_Pos)

0x00000040

◆ DAC_CR_WAVE1_1

#define DAC_CR_WAVE1_1 (0x2UL << DAC_CR_WAVE1_Pos)

0x00000080

◆ DAC_CR_WAVE1_Msk

#define DAC_CR_WAVE1_Msk (0x3UL << DAC_CR_WAVE1_Pos)

0x000000C0

◆ DAC_CR_WAVE1_Pos

#define DAC_CR_WAVE1_Pos (6U)

◆ DAC_CR_WAVE2

#define DAC_CR_WAVE2 DAC_CR_WAVE2_Msk

WAVE2[1:0] (DAC channel2 noise/triangle wave generation enable)

◆ DAC_CR_WAVE2_0

#define DAC_CR_WAVE2_0 (0x1UL << DAC_CR_WAVE2_Pos)

0x00400000

◆ DAC_CR_WAVE2_1

#define DAC_CR_WAVE2_1 (0x2UL << DAC_CR_WAVE2_Pos)

0x00800000

◆ DAC_CR_WAVE2_Msk

#define DAC_CR_WAVE2_Msk (0x3UL << DAC_CR_WAVE2_Pos)

0x00C00000

◆ DAC_CR_WAVE2_Pos

#define DAC_CR_WAVE2_Pos (22U)

◆ DAC_DHR12L1_DACC1DHR

#define DAC_DHR12L1_DACC1DHR DAC_DHR12L1_DACC1DHR_Msk

DAC channel1 12-bit Left aligned data

◆ DAC_DHR12L1_DACC1DHR_Msk

#define DAC_DHR12L1_DACC1DHR_Msk (0xFFFUL << DAC_DHR12L1_DACC1DHR_Pos)

0x0000FFF0

◆ DAC_DHR12L1_DACC1DHR_Pos

#define DAC_DHR12L1_DACC1DHR_Pos (4U)

◆ DAC_DHR12L2_DACC2DHR

#define DAC_DHR12L2_DACC2DHR DAC_DHR12L2_DACC2DHR_Msk

DAC channel2 12-bit Left aligned data

◆ DAC_DHR12L2_DACC2DHR_Msk

#define DAC_DHR12L2_DACC2DHR_Msk (0xFFFUL << DAC_DHR12L2_DACC2DHR_Pos)

0x0000FFF0

◆ DAC_DHR12L2_DACC2DHR_Pos

#define DAC_DHR12L2_DACC2DHR_Pos (4U)

◆ DAC_DHR12LD_DACC1DHR

#define DAC_DHR12LD_DACC1DHR DAC_DHR12LD_DACC1DHR_Msk

DAC channel1 12-bit Left aligned data

◆ DAC_DHR12LD_DACC1DHR_Msk

#define DAC_DHR12LD_DACC1DHR_Msk (0xFFFUL << DAC_DHR12LD_DACC1DHR_Pos)

0x0000FFF0

◆ DAC_DHR12LD_DACC1DHR_Pos

#define DAC_DHR12LD_DACC1DHR_Pos (4U)

◆ DAC_DHR12LD_DACC2DHR

#define DAC_DHR12LD_DACC2DHR DAC_DHR12LD_DACC2DHR_Msk

DAC channel2 12-bit Left aligned data

◆ DAC_DHR12LD_DACC2DHR_Msk

#define DAC_DHR12LD_DACC2DHR_Msk (0xFFFUL << DAC_DHR12LD_DACC2DHR_Pos)

0xFFF00000

◆ DAC_DHR12LD_DACC2DHR_Pos

#define DAC_DHR12LD_DACC2DHR_Pos (20U)

◆ DAC_DHR12R1_DACC1DHR

#define DAC_DHR12R1_DACC1DHR DAC_DHR12R1_DACC1DHR_Msk

DAC channel1 12-bit Right aligned data

◆ DAC_DHR12R1_DACC1DHR_Msk

#define DAC_DHR12R1_DACC1DHR_Msk (0xFFFUL << DAC_DHR12R1_DACC1DHR_Pos)

0x00000FFF

◆ DAC_DHR12R1_DACC1DHR_Pos

#define DAC_DHR12R1_DACC1DHR_Pos (0U)

◆ DAC_DHR12R2_DACC2DHR

#define DAC_DHR12R2_DACC2DHR DAC_DHR12R2_DACC2DHR_Msk

DAC channel2 12-bit Right aligned data

◆ DAC_DHR12R2_DACC2DHR_Msk

#define DAC_DHR12R2_DACC2DHR_Msk (0xFFFUL << DAC_DHR12R2_DACC2DHR_Pos)

0x00000FFF

◆ DAC_DHR12R2_DACC2DHR_Pos

#define DAC_DHR12R2_DACC2DHR_Pos (0U)

◆ DAC_DHR12RD_DACC1DHR

#define DAC_DHR12RD_DACC1DHR DAC_DHR12RD_DACC1DHR_Msk

DAC channel1 12-bit Right aligned data

◆ DAC_DHR12RD_DACC1DHR_Msk

#define DAC_DHR12RD_DACC1DHR_Msk (0xFFFUL << DAC_DHR12RD_DACC1DHR_Pos)

0x00000FFF

◆ DAC_DHR12RD_DACC1DHR_Pos

#define DAC_DHR12RD_DACC1DHR_Pos (0U)

◆ DAC_DHR12RD_DACC2DHR

#define DAC_DHR12RD_DACC2DHR DAC_DHR12RD_DACC2DHR_Msk

DAC channel2 12-bit Right aligned data

◆ DAC_DHR12RD_DACC2DHR_Msk

#define DAC_DHR12RD_DACC2DHR_Msk (0xFFFUL << DAC_DHR12RD_DACC2DHR_Pos)

0x0FFF0000

◆ DAC_DHR12RD_DACC2DHR_Pos

#define DAC_DHR12RD_DACC2DHR_Pos (16U)

◆ DAC_DHR8R1_DACC1DHR

#define DAC_DHR8R1_DACC1DHR DAC_DHR8R1_DACC1DHR_Msk

DAC channel1 8-bit Right aligned data

◆ DAC_DHR8R1_DACC1DHR_Msk

#define DAC_DHR8R1_DACC1DHR_Msk (0xFFUL << DAC_DHR8R1_DACC1DHR_Pos)

0x000000FF

◆ DAC_DHR8R1_DACC1DHR_Pos

#define DAC_DHR8R1_DACC1DHR_Pos (0U)

◆ DAC_DHR8R2_DACC2DHR

#define DAC_DHR8R2_DACC2DHR DAC_DHR8R2_DACC2DHR_Msk

DAC channel2 8-bit Right aligned data

◆ DAC_DHR8R2_DACC2DHR_Msk

#define DAC_DHR8R2_DACC2DHR_Msk (0xFFUL << DAC_DHR8R2_DACC2DHR_Pos)

0x000000FF

◆ DAC_DHR8R2_DACC2DHR_Pos

#define DAC_DHR8R2_DACC2DHR_Pos (0U)

◆ DAC_DHR8RD_DACC1DHR

#define DAC_DHR8RD_DACC1DHR DAC_DHR8RD_DACC1DHR_Msk

DAC channel1 8-bit Right aligned data

◆ DAC_DHR8RD_DACC1DHR_Msk

#define DAC_DHR8RD_DACC1DHR_Msk (0xFFUL << DAC_DHR8RD_DACC1DHR_Pos)

0x000000FF

◆ DAC_DHR8RD_DACC1DHR_Pos

#define DAC_DHR8RD_DACC1DHR_Pos (0U)

◆ DAC_DHR8RD_DACC2DHR

#define DAC_DHR8RD_DACC2DHR DAC_DHR8RD_DACC2DHR_Msk

DAC channel2 8-bit Right aligned data

◆ DAC_DHR8RD_DACC2DHR_Msk

#define DAC_DHR8RD_DACC2DHR_Msk (0xFFUL << DAC_DHR8RD_DACC2DHR_Pos)

0x0000FF00

◆ DAC_DHR8RD_DACC2DHR_Pos

#define DAC_DHR8RD_DACC2DHR_Pos (8U)

◆ DAC_DOR1_DACC1DOR

#define DAC_DOR1_DACC1DOR DAC_DOR1_DACC1DOR_Msk

DAC channel1 data output

◆ DAC_DOR1_DACC1DOR_Msk

#define DAC_DOR1_DACC1DOR_Msk (0xFFFUL << DAC_DOR1_DACC1DOR_Pos)

0x00000FFF

◆ DAC_DOR1_DACC1DOR_Pos

#define DAC_DOR1_DACC1DOR_Pos (0U)

◆ DAC_DOR2_DACC2DOR

#define DAC_DOR2_DACC2DOR DAC_DOR2_DACC2DOR_Msk

DAC channel2 data output

◆ DAC_DOR2_DACC2DOR_Msk

#define DAC_DOR2_DACC2DOR_Msk (0xFFFUL << DAC_DOR2_DACC2DOR_Pos)

0x00000FFF

◆ DAC_DOR2_DACC2DOR_Pos

#define DAC_DOR2_DACC2DOR_Pos (0U)

◆ DAC_SR_DMAUDR1

#define DAC_SR_DMAUDR1 DAC_SR_DMAUDR1_Msk

DAC channel1 DMA underrun flag

◆ DAC_SR_DMAUDR1_Msk

#define DAC_SR_DMAUDR1_Msk (0x1UL << DAC_SR_DMAUDR1_Pos)

0x00002000

◆ DAC_SR_DMAUDR1_Pos

#define DAC_SR_DMAUDR1_Pos (13U)

◆ DAC_SR_DMAUDR2

#define DAC_SR_DMAUDR2 DAC_SR_DMAUDR2_Msk

DAC channel2 DMA underrun flag

◆ DAC_SR_DMAUDR2_Msk

#define DAC_SR_DMAUDR2_Msk (0x1UL << DAC_SR_DMAUDR2_Pos)

0x20000000

◆ DAC_SR_DMAUDR2_Pos

#define DAC_SR_DMAUDR2_Pos (29U)

◆ DAC_SWTRIGR_SWTRIG1

#define DAC_SWTRIGR_SWTRIG1 DAC_SWTRIGR_SWTRIG1_Msk

DAC channel1 software trigger

◆ DAC_SWTRIGR_SWTRIG1_Msk

#define DAC_SWTRIGR_SWTRIG1_Msk (0x1UL << DAC_SWTRIGR_SWTRIG1_Pos)

0x00000001

◆ DAC_SWTRIGR_SWTRIG1_Pos

#define DAC_SWTRIGR_SWTRIG1_Pos (0U)

◆ DAC_SWTRIGR_SWTRIG2

#define DAC_SWTRIGR_SWTRIG2 DAC_SWTRIGR_SWTRIG2_Msk

DAC channel2 software trigger

◆ DAC_SWTRIGR_SWTRIG2_Msk

#define DAC_SWTRIGR_SWTRIG2_Msk (0x1UL << DAC_SWTRIGR_SWTRIG2_Pos)

0x00000002

◆ DAC_SWTRIGR_SWTRIG2_Pos

#define DAC_SWTRIGR_SWTRIG2_Pos (1U)

◆ DBGMCU_APB1_FZ_DBG_CAN_STOP

#define DBGMCU_APB1_FZ_DBG_CAN_STOP DBGMCU_APB1_FZ_DBG_CAN_STOP_Msk

◆ DBGMCU_APB1_FZ_DBG_CAN_STOP_Msk

#define DBGMCU_APB1_FZ_DBG_CAN_STOP_Msk (0x1UL << DBGMCU_APB1_FZ_DBG_CAN_STOP_Pos)

0x02000000

◆ DBGMCU_APB1_FZ_DBG_CAN_STOP_Pos

#define DBGMCU_APB1_FZ_DBG_CAN_STOP_Pos (25U)

◆ DBGMCU_APB1_FZ_DBG_I2C1_SMBUS_TIMEOUT

#define DBGMCU_APB1_FZ_DBG_I2C1_SMBUS_TIMEOUT DBGMCU_APB1_FZ_DBG_I2C1_SMBUS_TIMEOUT_Msk

◆ DBGMCU_APB1_FZ_DBG_I2C1_SMBUS_TIMEOUT_Msk

#define DBGMCU_APB1_FZ_DBG_I2C1_SMBUS_TIMEOUT_Msk (0x1UL << DBGMCU_APB1_FZ_DBG_I2C1_SMBUS_TIMEOUT_Pos)

0x00200000

◆ DBGMCU_APB1_FZ_DBG_I2C1_SMBUS_TIMEOUT_Pos

#define DBGMCU_APB1_FZ_DBG_I2C1_SMBUS_TIMEOUT_Pos (21U)

◆ DBGMCU_APB1_FZ_DBG_I2C2_SMBUS_TIMEOUT

#define DBGMCU_APB1_FZ_DBG_I2C2_SMBUS_TIMEOUT DBGMCU_APB1_FZ_DBG_I2C2_SMBUS_TIMEOUT_Msk

◆ DBGMCU_APB1_FZ_DBG_I2C2_SMBUS_TIMEOUT_Msk

#define DBGMCU_APB1_FZ_DBG_I2C2_SMBUS_TIMEOUT_Msk (0x1UL << DBGMCU_APB1_FZ_DBG_I2C2_SMBUS_TIMEOUT_Pos)

0x00400000

◆ DBGMCU_APB1_FZ_DBG_I2C2_SMBUS_TIMEOUT_Pos

#define DBGMCU_APB1_FZ_DBG_I2C2_SMBUS_TIMEOUT_Pos (22U)

◆ DBGMCU_APB1_FZ_DBG_I2C3_SMBUS_TIMEOUT

#define DBGMCU_APB1_FZ_DBG_I2C3_SMBUS_TIMEOUT DBGMCU_APB1_FZ_DBG_I2C3_SMBUS_TIMEOUT_Msk

◆ DBGMCU_APB1_FZ_DBG_I2C3_SMBUS_TIMEOUT_Msk

#define DBGMCU_APB1_FZ_DBG_I2C3_SMBUS_TIMEOUT_Msk (0x1UL << DBGMCU_APB1_FZ_DBG_I2C3_SMBUS_TIMEOUT_Pos)

0x40000000

◆ DBGMCU_APB1_FZ_DBG_I2C3_SMBUS_TIMEOUT_Pos

#define DBGMCU_APB1_FZ_DBG_I2C3_SMBUS_TIMEOUT_Pos (30U)

◆ DBGMCU_APB1_FZ_DBG_IWDG_STOP

#define DBGMCU_APB1_FZ_DBG_IWDG_STOP DBGMCU_APB1_FZ_DBG_IWDG_STOP_Msk

◆ DBGMCU_APB1_FZ_DBG_IWDG_STOP_Msk

#define DBGMCU_APB1_FZ_DBG_IWDG_STOP_Msk (0x1UL << DBGMCU_APB1_FZ_DBG_IWDG_STOP_Pos)

0x00001000

◆ DBGMCU_APB1_FZ_DBG_IWDG_STOP_Pos

#define DBGMCU_APB1_FZ_DBG_IWDG_STOP_Pos (12U)

◆ DBGMCU_APB1_FZ_DBG_RTC_STOP

#define DBGMCU_APB1_FZ_DBG_RTC_STOP DBGMCU_APB1_FZ_DBG_RTC_STOP_Msk

◆ DBGMCU_APB1_FZ_DBG_RTC_STOP_Msk

#define DBGMCU_APB1_FZ_DBG_RTC_STOP_Msk (0x1UL << DBGMCU_APB1_FZ_DBG_RTC_STOP_Pos)

0x00000400

◆ DBGMCU_APB1_FZ_DBG_RTC_STOP_Pos

#define DBGMCU_APB1_FZ_DBG_RTC_STOP_Pos (10U)

◆ DBGMCU_APB1_FZ_DBG_TIM2_STOP

#define DBGMCU_APB1_FZ_DBG_TIM2_STOP DBGMCU_APB1_FZ_DBG_TIM2_STOP_Msk

◆ DBGMCU_APB1_FZ_DBG_TIM2_STOP_Msk

#define DBGMCU_APB1_FZ_DBG_TIM2_STOP_Msk (0x1UL << DBGMCU_APB1_FZ_DBG_TIM2_STOP_Pos)

0x00000001

◆ DBGMCU_APB1_FZ_DBG_TIM2_STOP_Pos

#define DBGMCU_APB1_FZ_DBG_TIM2_STOP_Pos (0U)

◆ DBGMCU_APB1_FZ_DBG_TIM3_STOP

#define DBGMCU_APB1_FZ_DBG_TIM3_STOP DBGMCU_APB1_FZ_DBG_TIM3_STOP_Msk

◆ DBGMCU_APB1_FZ_DBG_TIM3_STOP_Msk

#define DBGMCU_APB1_FZ_DBG_TIM3_STOP_Msk (0x1UL << DBGMCU_APB1_FZ_DBG_TIM3_STOP_Pos)

0x00000002

◆ DBGMCU_APB1_FZ_DBG_TIM3_STOP_Pos

#define DBGMCU_APB1_FZ_DBG_TIM3_STOP_Pos (1U)

◆ DBGMCU_APB1_FZ_DBG_TIM4_STOP

#define DBGMCU_APB1_FZ_DBG_TIM4_STOP DBGMCU_APB1_FZ_DBG_TIM4_STOP_Msk

◆ DBGMCU_APB1_FZ_DBG_TIM4_STOP_Msk

#define DBGMCU_APB1_FZ_DBG_TIM4_STOP_Msk (0x1UL << DBGMCU_APB1_FZ_DBG_TIM4_STOP_Pos)

0x00000004

◆ DBGMCU_APB1_FZ_DBG_TIM4_STOP_Pos

#define DBGMCU_APB1_FZ_DBG_TIM4_STOP_Pos (2U)

◆ DBGMCU_APB1_FZ_DBG_TIM6_STOP

#define DBGMCU_APB1_FZ_DBG_TIM6_STOP DBGMCU_APB1_FZ_DBG_TIM6_STOP_Msk

◆ DBGMCU_APB1_FZ_DBG_TIM6_STOP_Msk

#define DBGMCU_APB1_FZ_DBG_TIM6_STOP_Msk (0x1UL << DBGMCU_APB1_FZ_DBG_TIM6_STOP_Pos)

0x00000010

◆ DBGMCU_APB1_FZ_DBG_TIM6_STOP_Pos

#define DBGMCU_APB1_FZ_DBG_TIM6_STOP_Pos (4U)

◆ DBGMCU_APB1_FZ_DBG_TIM7_STOP

#define DBGMCU_APB1_FZ_DBG_TIM7_STOP DBGMCU_APB1_FZ_DBG_TIM7_STOP_Msk

◆ DBGMCU_APB1_FZ_DBG_TIM7_STOP_Msk

#define DBGMCU_APB1_FZ_DBG_TIM7_STOP_Msk (0x1UL << DBGMCU_APB1_FZ_DBG_TIM7_STOP_Pos)

0x00000020

◆ DBGMCU_APB1_FZ_DBG_TIM7_STOP_Pos

#define DBGMCU_APB1_FZ_DBG_TIM7_STOP_Pos (5U)

◆ DBGMCU_APB1_FZ_DBG_WWDG_STOP

#define DBGMCU_APB1_FZ_DBG_WWDG_STOP DBGMCU_APB1_FZ_DBG_WWDG_STOP_Msk

◆ DBGMCU_APB1_FZ_DBG_WWDG_STOP_Msk

#define DBGMCU_APB1_FZ_DBG_WWDG_STOP_Msk (0x1UL << DBGMCU_APB1_FZ_DBG_WWDG_STOP_Pos)

0x00000800

◆ DBGMCU_APB1_FZ_DBG_WWDG_STOP_Pos

#define DBGMCU_APB1_FZ_DBG_WWDG_STOP_Pos (11U)

◆ DBGMCU_APB2_FZ_DBG_TIM15_STOP

#define DBGMCU_APB2_FZ_DBG_TIM15_STOP DBGMCU_APB2_FZ_DBG_TIM15_STOP_Msk

◆ DBGMCU_APB2_FZ_DBG_TIM15_STOP_Msk

#define DBGMCU_APB2_FZ_DBG_TIM15_STOP_Msk (0x1UL << DBGMCU_APB2_FZ_DBG_TIM15_STOP_Pos)

0x00000004

◆ DBGMCU_APB2_FZ_DBG_TIM15_STOP_Pos

#define DBGMCU_APB2_FZ_DBG_TIM15_STOP_Pos (2U)

◆ DBGMCU_APB2_FZ_DBG_TIM16_STOP

#define DBGMCU_APB2_FZ_DBG_TIM16_STOP DBGMCU_APB2_FZ_DBG_TIM16_STOP_Msk

◆ DBGMCU_APB2_FZ_DBG_TIM16_STOP_Msk

#define DBGMCU_APB2_FZ_DBG_TIM16_STOP_Msk (0x1UL << DBGMCU_APB2_FZ_DBG_TIM16_STOP_Pos)

0x00000008

◆ DBGMCU_APB2_FZ_DBG_TIM16_STOP_Pos

#define DBGMCU_APB2_FZ_DBG_TIM16_STOP_Pos (3U)

◆ DBGMCU_APB2_FZ_DBG_TIM17_STOP

#define DBGMCU_APB2_FZ_DBG_TIM17_STOP DBGMCU_APB2_FZ_DBG_TIM17_STOP_Msk

◆ DBGMCU_APB2_FZ_DBG_TIM17_STOP_Msk

#define DBGMCU_APB2_FZ_DBG_TIM17_STOP_Msk (0x1UL << DBGMCU_APB2_FZ_DBG_TIM17_STOP_Pos)

0x00000010

◆ DBGMCU_APB2_FZ_DBG_TIM17_STOP_Pos

#define DBGMCU_APB2_FZ_DBG_TIM17_STOP_Pos (4U)

◆ DBGMCU_APB2_FZ_DBG_TIM1_STOP

#define DBGMCU_APB2_FZ_DBG_TIM1_STOP DBGMCU_APB2_FZ_DBG_TIM1_STOP_Msk

◆ DBGMCU_APB2_FZ_DBG_TIM1_STOP_Msk

#define DBGMCU_APB2_FZ_DBG_TIM1_STOP_Msk (0x1UL << DBGMCU_APB2_FZ_DBG_TIM1_STOP_Pos)

0x00000001

◆ DBGMCU_APB2_FZ_DBG_TIM1_STOP_Pos

#define DBGMCU_APB2_FZ_DBG_TIM1_STOP_Pos (0U)

◆ DBGMCU_APB2_FZ_DBG_TIM20_STOP

#define DBGMCU_APB2_FZ_DBG_TIM20_STOP DBGMCU_APB2_FZ_DBG_TIM20_STOP_Msk

◆ DBGMCU_APB2_FZ_DBG_TIM20_STOP_Msk

#define DBGMCU_APB2_FZ_DBG_TIM20_STOP_Msk (0x1UL << DBGMCU_APB2_FZ_DBG_TIM20_STOP_Pos)

0x00000020

◆ DBGMCU_APB2_FZ_DBG_TIM20_STOP_Pos

#define DBGMCU_APB2_FZ_DBG_TIM20_STOP_Pos (5U)

◆ DBGMCU_APB2_FZ_DBG_TIM8_STOP

#define DBGMCU_APB2_FZ_DBG_TIM8_STOP DBGMCU_APB2_FZ_DBG_TIM8_STOP_Msk

◆ DBGMCU_APB2_FZ_DBG_TIM8_STOP_Msk

#define DBGMCU_APB2_FZ_DBG_TIM8_STOP_Msk (0x1UL << DBGMCU_APB2_FZ_DBG_TIM8_STOP_Pos)

0x00000002

◆ DBGMCU_APB2_FZ_DBG_TIM8_STOP_Pos

#define DBGMCU_APB2_FZ_DBG_TIM8_STOP_Pos (1U)

◆ DBGMCU_CR_DBG_SLEEP

#define DBGMCU_CR_DBG_SLEEP DBGMCU_CR_DBG_SLEEP_Msk

◆ DBGMCU_CR_DBG_SLEEP_Msk

#define DBGMCU_CR_DBG_SLEEP_Msk (0x1UL << DBGMCU_CR_DBG_SLEEP_Pos)

0x00000001

◆ DBGMCU_CR_DBG_SLEEP_Pos

#define DBGMCU_CR_DBG_SLEEP_Pos (0U)

◆ DBGMCU_CR_DBG_STANDBY

#define DBGMCU_CR_DBG_STANDBY DBGMCU_CR_DBG_STANDBY_Msk

◆ DBGMCU_CR_DBG_STANDBY_Msk

#define DBGMCU_CR_DBG_STANDBY_Msk (0x1UL << DBGMCU_CR_DBG_STANDBY_Pos)

0x00000004

◆ DBGMCU_CR_DBG_STANDBY_Pos

#define DBGMCU_CR_DBG_STANDBY_Pos (2U)

◆ DBGMCU_CR_DBG_STOP

#define DBGMCU_CR_DBG_STOP DBGMCU_CR_DBG_STOP_Msk

◆ DBGMCU_CR_DBG_STOP_Msk

#define DBGMCU_CR_DBG_STOP_Msk (0x1UL << DBGMCU_CR_DBG_STOP_Pos)

0x00000002

◆ DBGMCU_CR_DBG_STOP_Pos

#define DBGMCU_CR_DBG_STOP_Pos (1U)

◆ DBGMCU_CR_TRACE_IOEN

#define DBGMCU_CR_TRACE_IOEN DBGMCU_CR_TRACE_IOEN_Msk

◆ DBGMCU_CR_TRACE_IOEN_Msk

#define DBGMCU_CR_TRACE_IOEN_Msk (0x1UL << DBGMCU_CR_TRACE_IOEN_Pos)

0x00000020

◆ DBGMCU_CR_TRACE_IOEN_Pos

#define DBGMCU_CR_TRACE_IOEN_Pos (5U)

◆ DBGMCU_CR_TRACE_MODE

#define DBGMCU_CR_TRACE_MODE DBGMCU_CR_TRACE_MODE_Msk

◆ DBGMCU_CR_TRACE_MODE_0

#define DBGMCU_CR_TRACE_MODE_0 (0x1UL << DBGMCU_CR_TRACE_MODE_Pos)

0x00000040

◆ DBGMCU_CR_TRACE_MODE_1

#define DBGMCU_CR_TRACE_MODE_1 (0x2UL << DBGMCU_CR_TRACE_MODE_Pos)

0x00000080

◆ DBGMCU_CR_TRACE_MODE_Msk

#define DBGMCU_CR_TRACE_MODE_Msk (0x3UL << DBGMCU_CR_TRACE_MODE_Pos)

0x000000C0

◆ DBGMCU_CR_TRACE_MODE_Pos

#define DBGMCU_CR_TRACE_MODE_Pos (6U)

◆ DBGMCU_IDCODE_DEV_ID

#define DBGMCU_IDCODE_DEV_ID DBGMCU_IDCODE_DEV_ID_Msk

◆ DBGMCU_IDCODE_DEV_ID_Msk

#define DBGMCU_IDCODE_DEV_ID_Msk (0xFFFUL << DBGMCU_IDCODE_DEV_ID_Pos)

0x00000FFF

◆ DBGMCU_IDCODE_DEV_ID_Pos

#define DBGMCU_IDCODE_DEV_ID_Pos (0U)

◆ DBGMCU_IDCODE_REV_ID

#define DBGMCU_IDCODE_REV_ID DBGMCU_IDCODE_REV_ID_Msk

◆ DBGMCU_IDCODE_REV_ID_Msk

#define DBGMCU_IDCODE_REV_ID_Msk (0xFFFFUL << DBGMCU_IDCODE_REV_ID_Pos)

0xFFFF0000

◆ DBGMCU_IDCODE_REV_ID_Pos

#define DBGMCU_IDCODE_REV_ID_Pos (16U)

◆ DMA_CCR_CIRC

#define DMA_CCR_CIRC DMA_CCR_CIRC_Msk

Circular mode

◆ DMA_CCR_CIRC_Msk

#define DMA_CCR_CIRC_Msk (0x1UL << DMA_CCR_CIRC_Pos)

0x00000020

◆ DMA_CCR_CIRC_Pos

#define DMA_CCR_CIRC_Pos (5U)

◆ DMA_CCR_DIR

#define DMA_CCR_DIR DMA_CCR_DIR_Msk

Data transfer direction

◆ DMA_CCR_DIR_Msk

#define DMA_CCR_DIR_Msk (0x1UL << DMA_CCR_DIR_Pos)

0x00000010

◆ DMA_CCR_DIR_Pos

#define DMA_CCR_DIR_Pos (4U)

◆ DMA_CCR_EN

#define DMA_CCR_EN DMA_CCR_EN_Msk

Channel enable

◆ DMA_CCR_EN_Msk

#define DMA_CCR_EN_Msk (0x1UL << DMA_CCR_EN_Pos)

0x00000001

◆ DMA_CCR_EN_Pos

#define DMA_CCR_EN_Pos (0U)

◆ DMA_CCR_HTIE

#define DMA_CCR_HTIE DMA_CCR_HTIE_Msk

Half Transfer interrupt enable

◆ DMA_CCR_HTIE_Msk

#define DMA_CCR_HTIE_Msk (0x1UL << DMA_CCR_HTIE_Pos)

0x00000004

◆ DMA_CCR_HTIE_Pos

#define DMA_CCR_HTIE_Pos (2U)

◆ DMA_CCR_MEM2MEM

#define DMA_CCR_MEM2MEM DMA_CCR_MEM2MEM_Msk

Memory to memory mode

◆ DMA_CCR_MEM2MEM_Msk

#define DMA_CCR_MEM2MEM_Msk (0x1UL << DMA_CCR_MEM2MEM_Pos)

0x00004000

◆ DMA_CCR_MEM2MEM_Pos

#define DMA_CCR_MEM2MEM_Pos (14U)

◆ DMA_CCR_MINC

#define DMA_CCR_MINC DMA_CCR_MINC_Msk

Memory increment mode

◆ DMA_CCR_MINC_Msk

#define DMA_CCR_MINC_Msk (0x1UL << DMA_CCR_MINC_Pos)

0x00000080

◆ DMA_CCR_MINC_Pos

#define DMA_CCR_MINC_Pos (7U)

◆ DMA_CCR_MSIZE

#define DMA_CCR_MSIZE DMA_CCR_MSIZE_Msk

MSIZE[1:0] bits (Memory size)

◆ DMA_CCR_MSIZE_0

#define DMA_CCR_MSIZE_0 (0x1UL << DMA_CCR_MSIZE_Pos)

0x00000400

◆ DMA_CCR_MSIZE_1

#define DMA_CCR_MSIZE_1 (0x2UL << DMA_CCR_MSIZE_Pos)

0x00000800

◆ DMA_CCR_MSIZE_Msk

#define DMA_CCR_MSIZE_Msk (0x3UL << DMA_CCR_MSIZE_Pos)

0x00000C00

◆ DMA_CCR_MSIZE_Pos

#define DMA_CCR_MSIZE_Pos (10U)

◆ DMA_CCR_PINC

#define DMA_CCR_PINC DMA_CCR_PINC_Msk

Peripheral increment mode

◆ DMA_CCR_PINC_Msk

#define DMA_CCR_PINC_Msk (0x1UL << DMA_CCR_PINC_Pos)

0x00000040

◆ DMA_CCR_PINC_Pos

#define DMA_CCR_PINC_Pos (6U)

◆ DMA_CCR_PL

#define DMA_CCR_PL DMA_CCR_PL_Msk

PL[1:0] bits(Channel Priority level)

◆ DMA_CCR_PL_0

#define DMA_CCR_PL_0 (0x1UL << DMA_CCR_PL_Pos)

0x00001000

◆ DMA_CCR_PL_1

#define DMA_CCR_PL_1 (0x2UL << DMA_CCR_PL_Pos)

0x00002000

◆ DMA_CCR_PL_Msk

#define DMA_CCR_PL_Msk (0x3UL << DMA_CCR_PL_Pos)

0x00003000

◆ DMA_CCR_PL_Pos

#define DMA_CCR_PL_Pos (12U)

◆ DMA_CCR_PSIZE

#define DMA_CCR_PSIZE DMA_CCR_PSIZE_Msk

PSIZE[1:0] bits (Peripheral size)

◆ DMA_CCR_PSIZE_0

#define DMA_CCR_PSIZE_0 (0x1UL << DMA_CCR_PSIZE_Pos)

0x00000100

◆ DMA_CCR_PSIZE_1

#define DMA_CCR_PSIZE_1 (0x2UL << DMA_CCR_PSIZE_Pos)

0x00000200

◆ DMA_CCR_PSIZE_Msk

#define DMA_CCR_PSIZE_Msk (0x3UL << DMA_CCR_PSIZE_Pos)

0x00000300

◆ DMA_CCR_PSIZE_Pos

#define DMA_CCR_PSIZE_Pos (8U)

◆ DMA_CCR_TCIE

#define DMA_CCR_TCIE DMA_CCR_TCIE_Msk

Transfer complete interrupt enable

◆ DMA_CCR_TCIE_Msk

#define DMA_CCR_TCIE_Msk (0x1UL << DMA_CCR_TCIE_Pos)

0x00000002

◆ DMA_CCR_TCIE_Pos

#define DMA_CCR_TCIE_Pos (1U)

◆ DMA_CCR_TEIE

#define DMA_CCR_TEIE DMA_CCR_TEIE_Msk

Transfer error interrupt enable

◆ DMA_CCR_TEIE_Msk

#define DMA_CCR_TEIE_Msk (0x1UL << DMA_CCR_TEIE_Pos)

0x00000008

◆ DMA_CCR_TEIE_Pos

#define DMA_CCR_TEIE_Pos (3U)

◆ DMA_CMAR_MA

#define DMA_CMAR_MA DMA_CMAR_MA_Msk

Memory Address

◆ DMA_CMAR_MA_Msk

#define DMA_CMAR_MA_Msk (0xFFFFFFFFUL << DMA_CMAR_MA_Pos)

0xFFFFFFFF

◆ DMA_CMAR_MA_Pos

#define DMA_CMAR_MA_Pos (0U)

◆ DMA_CNDTR_NDT

#define DMA_CNDTR_NDT DMA_CNDTR_NDT_Msk

Number of data to Transfer

◆ DMA_CNDTR_NDT_Msk

#define DMA_CNDTR_NDT_Msk (0xFFFFUL << DMA_CNDTR_NDT_Pos)

0x0000FFFF

◆ DMA_CNDTR_NDT_Pos

#define DMA_CNDTR_NDT_Pos (0U)

◆ DMA_CPAR_PA

#define DMA_CPAR_PA DMA_CPAR_PA_Msk

Peripheral Address

◆ DMA_CPAR_PA_Msk

#define DMA_CPAR_PA_Msk (0xFFFFFFFFUL << DMA_CPAR_PA_Pos)

0xFFFFFFFF

◆ DMA_CPAR_PA_Pos

#define DMA_CPAR_PA_Pos (0U)

◆ DMA_IFCR_CGIF1

#define DMA_IFCR_CGIF1 DMA_IFCR_CGIF1_Msk

Channel 1 Global interrupt clear

◆ DMA_IFCR_CGIF1_Msk

#define DMA_IFCR_CGIF1_Msk (0x1UL << DMA_IFCR_CGIF1_Pos)

0x00000001

◆ DMA_IFCR_CGIF1_Pos

#define DMA_IFCR_CGIF1_Pos (0U)

◆ DMA_IFCR_CGIF2

#define DMA_IFCR_CGIF2 DMA_IFCR_CGIF2_Msk

Channel 2 Global interrupt clear

◆ DMA_IFCR_CGIF2_Msk

#define DMA_IFCR_CGIF2_Msk (0x1UL << DMA_IFCR_CGIF2_Pos)

0x00000010

◆ DMA_IFCR_CGIF2_Pos

#define DMA_IFCR_CGIF2_Pos (4U)

◆ DMA_IFCR_CGIF3

#define DMA_IFCR_CGIF3 DMA_IFCR_CGIF3_Msk

Channel 3 Global interrupt clear

◆ DMA_IFCR_CGIF3_Msk

#define DMA_IFCR_CGIF3_Msk (0x1UL << DMA_IFCR_CGIF3_Pos)

0x00000100

◆ DMA_IFCR_CGIF3_Pos

#define DMA_IFCR_CGIF3_Pos (8U)

◆ DMA_IFCR_CGIF4

#define DMA_IFCR_CGIF4 DMA_IFCR_CGIF4_Msk

Channel 4 Global interrupt clear

◆ DMA_IFCR_CGIF4_Msk

#define DMA_IFCR_CGIF4_Msk (0x1UL << DMA_IFCR_CGIF4_Pos)

0x00001000

◆ DMA_IFCR_CGIF4_Pos

#define DMA_IFCR_CGIF4_Pos (12U)

◆ DMA_IFCR_CGIF5

#define DMA_IFCR_CGIF5 DMA_IFCR_CGIF5_Msk

Channel 5 Global interrupt clear

◆ DMA_IFCR_CGIF5_Msk

#define DMA_IFCR_CGIF5_Msk (0x1UL << DMA_IFCR_CGIF5_Pos)

0x00010000

◆ DMA_IFCR_CGIF5_Pos

#define DMA_IFCR_CGIF5_Pos (16U)

◆ DMA_IFCR_CGIF6

#define DMA_IFCR_CGIF6 DMA_IFCR_CGIF6_Msk

Channel 6 Global interrupt clear

◆ DMA_IFCR_CGIF6_Msk

#define DMA_IFCR_CGIF6_Msk (0x1UL << DMA_IFCR_CGIF6_Pos)

0x00100000

◆ DMA_IFCR_CGIF6_Pos

#define DMA_IFCR_CGIF6_Pos (20U)

◆ DMA_IFCR_CGIF7

#define DMA_IFCR_CGIF7 DMA_IFCR_CGIF7_Msk

Channel 7 Global interrupt clear

◆ DMA_IFCR_CGIF7_Msk

#define DMA_IFCR_CGIF7_Msk (0x1UL << DMA_IFCR_CGIF7_Pos)

0x01000000

◆ DMA_IFCR_CGIF7_Pos

#define DMA_IFCR_CGIF7_Pos (24U)

◆ DMA_IFCR_CHTIF1

#define DMA_IFCR_CHTIF1 DMA_IFCR_CHTIF1_Msk

Channel 1 Half Transfer clear

◆ DMA_IFCR_CHTIF1_Msk

#define DMA_IFCR_CHTIF1_Msk (0x1UL << DMA_IFCR_CHTIF1_Pos)

0x00000004

◆ DMA_IFCR_CHTIF1_Pos

#define DMA_IFCR_CHTIF1_Pos (2U)

◆ DMA_IFCR_CHTIF2

#define DMA_IFCR_CHTIF2 DMA_IFCR_CHTIF2_Msk

Channel 2 Half Transfer clear

◆ DMA_IFCR_CHTIF2_Msk

#define DMA_IFCR_CHTIF2_Msk (0x1UL << DMA_IFCR_CHTIF2_Pos)

0x00000040

◆ DMA_IFCR_CHTIF2_Pos

#define DMA_IFCR_CHTIF2_Pos (6U)

◆ DMA_IFCR_CHTIF3

#define DMA_IFCR_CHTIF3 DMA_IFCR_CHTIF3_Msk

Channel 3 Half Transfer clear

◆ DMA_IFCR_CHTIF3_Msk

#define DMA_IFCR_CHTIF3_Msk (0x1UL << DMA_IFCR_CHTIF3_Pos)

0x00000400

◆ DMA_IFCR_CHTIF3_Pos

#define DMA_IFCR_CHTIF3_Pos (10U)

◆ DMA_IFCR_CHTIF4

#define DMA_IFCR_CHTIF4 DMA_IFCR_CHTIF4_Msk

Channel 4 Half Transfer clear

◆ DMA_IFCR_CHTIF4_Msk

#define DMA_IFCR_CHTIF4_Msk (0x1UL << DMA_IFCR_CHTIF4_Pos)

0x00004000

◆ DMA_IFCR_CHTIF4_Pos

#define DMA_IFCR_CHTIF4_Pos (14U)

◆ DMA_IFCR_CHTIF5

#define DMA_IFCR_CHTIF5 DMA_IFCR_CHTIF5_Msk

Channel 5 Half Transfer clear

◆ DMA_IFCR_CHTIF5_Msk

#define DMA_IFCR_CHTIF5_Msk (0x1UL << DMA_IFCR_CHTIF5_Pos)

0x00040000

◆ DMA_IFCR_CHTIF5_Pos

#define DMA_IFCR_CHTIF5_Pos (18U)

◆ DMA_IFCR_CHTIF6

#define DMA_IFCR_CHTIF6 DMA_IFCR_CHTIF6_Msk

Channel 6 Half Transfer clear

◆ DMA_IFCR_CHTIF6_Msk

#define DMA_IFCR_CHTIF6_Msk (0x1UL << DMA_IFCR_CHTIF6_Pos)

0x00400000

◆ DMA_IFCR_CHTIF6_Pos

#define DMA_IFCR_CHTIF6_Pos (22U)

◆ DMA_IFCR_CHTIF7

#define DMA_IFCR_CHTIF7 DMA_IFCR_CHTIF7_Msk

Channel 7 Half Transfer clear

◆ DMA_IFCR_CHTIF7_Msk

#define DMA_IFCR_CHTIF7_Msk (0x1UL << DMA_IFCR_CHTIF7_Pos)

0x04000000

◆ DMA_IFCR_CHTIF7_Pos

#define DMA_IFCR_CHTIF7_Pos (26U)

◆ DMA_IFCR_CTCIF1

#define DMA_IFCR_CTCIF1 DMA_IFCR_CTCIF1_Msk

Channel 1 Transfer Complete clear

◆ DMA_IFCR_CTCIF1_Msk

#define DMA_IFCR_CTCIF1_Msk (0x1UL << DMA_IFCR_CTCIF1_Pos)

0x00000002

◆ DMA_IFCR_CTCIF1_Pos

#define DMA_IFCR_CTCIF1_Pos (1U)

◆ DMA_IFCR_CTCIF2

#define DMA_IFCR_CTCIF2 DMA_IFCR_CTCIF2_Msk

Channel 2 Transfer Complete clear

◆ DMA_IFCR_CTCIF2_Msk

#define DMA_IFCR_CTCIF2_Msk (0x1UL << DMA_IFCR_CTCIF2_Pos)

0x00000020

◆ DMA_IFCR_CTCIF2_Pos

#define DMA_IFCR_CTCIF2_Pos (5U)

◆ DMA_IFCR_CTCIF3

#define DMA_IFCR_CTCIF3 DMA_IFCR_CTCIF3_Msk

Channel 3 Transfer Complete clear

◆ DMA_IFCR_CTCIF3_Msk

#define DMA_IFCR_CTCIF3_Msk (0x1UL << DMA_IFCR_CTCIF3_Pos)

0x00000200

◆ DMA_IFCR_CTCIF3_Pos

#define DMA_IFCR_CTCIF3_Pos (9U)

◆ DMA_IFCR_CTCIF4

#define DMA_IFCR_CTCIF4 DMA_IFCR_CTCIF4_Msk

Channel 4 Transfer Complete clear

◆ DMA_IFCR_CTCIF4_Msk

#define DMA_IFCR_CTCIF4_Msk (0x1UL << DMA_IFCR_CTCIF4_Pos)

0x00002000

◆ DMA_IFCR_CTCIF4_Pos

#define DMA_IFCR_CTCIF4_Pos (13U)

◆ DMA_IFCR_CTCIF5

#define DMA_IFCR_CTCIF5 DMA_IFCR_CTCIF5_Msk

Channel 5 Transfer Complete clear

◆ DMA_IFCR_CTCIF5_Msk

#define DMA_IFCR_CTCIF5_Msk (0x1UL << DMA_IFCR_CTCIF5_Pos)

0x00020000

◆ DMA_IFCR_CTCIF5_Pos

#define DMA_IFCR_CTCIF5_Pos (17U)

◆ DMA_IFCR_CTCIF6

#define DMA_IFCR_CTCIF6 DMA_IFCR_CTCIF6_Msk

Channel 6 Transfer Complete clear

◆ DMA_IFCR_CTCIF6_Msk

#define DMA_IFCR_CTCIF6_Msk (0x1UL << DMA_IFCR_CTCIF6_Pos)

0x00200000

◆ DMA_IFCR_CTCIF6_Pos

#define DMA_IFCR_CTCIF6_Pos (21U)

◆ DMA_IFCR_CTCIF7

#define DMA_IFCR_CTCIF7 DMA_IFCR_CTCIF7_Msk

Channel 7 Transfer Complete clear

◆ DMA_IFCR_CTCIF7_Msk

#define DMA_IFCR_CTCIF7_Msk (0x1UL << DMA_IFCR_CTCIF7_Pos)

0x02000000

◆ DMA_IFCR_CTCIF7_Pos

#define DMA_IFCR_CTCIF7_Pos (25U)

◆ DMA_IFCR_CTEIF1

#define DMA_IFCR_CTEIF1 DMA_IFCR_CTEIF1_Msk

Channel 1 Transfer Error clear

◆ DMA_IFCR_CTEIF1_Msk

#define DMA_IFCR_CTEIF1_Msk (0x1UL << DMA_IFCR_CTEIF1_Pos)

0x00000008

◆ DMA_IFCR_CTEIF1_Pos

#define DMA_IFCR_CTEIF1_Pos (3U)

◆ DMA_IFCR_CTEIF2

#define DMA_IFCR_CTEIF2 DMA_IFCR_CTEIF2_Msk

Channel 2 Transfer Error clear

◆ DMA_IFCR_CTEIF2_Msk

#define DMA_IFCR_CTEIF2_Msk (0x1UL << DMA_IFCR_CTEIF2_Pos)

0x00000080

◆ DMA_IFCR_CTEIF2_Pos

#define DMA_IFCR_CTEIF2_Pos (7U)

◆ DMA_IFCR_CTEIF3

#define DMA_IFCR_CTEIF3 DMA_IFCR_CTEIF3_Msk

Channel 3 Transfer Error clear

◆ DMA_IFCR_CTEIF3_Msk

#define DMA_IFCR_CTEIF3_Msk (0x1UL << DMA_IFCR_CTEIF3_Pos)

0x00000800

◆ DMA_IFCR_CTEIF3_Pos

#define DMA_IFCR_CTEIF3_Pos (11U)

◆ DMA_IFCR_CTEIF4

#define DMA_IFCR_CTEIF4 DMA_IFCR_CTEIF4_Msk

Channel 4 Transfer Error clear

◆ DMA_IFCR_CTEIF4_Msk

#define DMA_IFCR_CTEIF4_Msk (0x1UL << DMA_IFCR_CTEIF4_Pos)

0x00008000

◆ DMA_IFCR_CTEIF4_Pos

#define DMA_IFCR_CTEIF4_Pos (15U)

◆ DMA_IFCR_CTEIF5

#define DMA_IFCR_CTEIF5 DMA_IFCR_CTEIF5_Msk

Channel 5 Transfer Error clear

◆ DMA_IFCR_CTEIF5_Msk

#define DMA_IFCR_CTEIF5_Msk (0x1UL << DMA_IFCR_CTEIF5_Pos)

0x00080000

◆ DMA_IFCR_CTEIF5_Pos

#define DMA_IFCR_CTEIF5_Pos (19U)

◆ DMA_IFCR_CTEIF6

#define DMA_IFCR_CTEIF6 DMA_IFCR_CTEIF6_Msk

Channel 6 Transfer Error clear

◆ DMA_IFCR_CTEIF6_Msk

#define DMA_IFCR_CTEIF6_Msk (0x1UL << DMA_IFCR_CTEIF6_Pos)

0x00800000

◆ DMA_IFCR_CTEIF6_Pos

#define DMA_IFCR_CTEIF6_Pos (23U)

◆ DMA_IFCR_CTEIF7

#define DMA_IFCR_CTEIF7 DMA_IFCR_CTEIF7_Msk

Channel 7 Transfer Error clear

◆ DMA_IFCR_CTEIF7_Msk

#define DMA_IFCR_CTEIF7_Msk (0x1UL << DMA_IFCR_CTEIF7_Pos)

0x08000000

◆ DMA_IFCR_CTEIF7_Pos

#define DMA_IFCR_CTEIF7_Pos (27U)

◆ DMA_ISR_GIF1

#define DMA_ISR_GIF1 DMA_ISR_GIF1_Msk

Channel 1 Global interrupt flag

◆ DMA_ISR_GIF1_Msk

#define DMA_ISR_GIF1_Msk (0x1UL << DMA_ISR_GIF1_Pos)

0x00000001

◆ DMA_ISR_GIF1_Pos

#define DMA_ISR_GIF1_Pos (0U)

◆ DMA_ISR_GIF2

#define DMA_ISR_GIF2 DMA_ISR_GIF2_Msk

Channel 2 Global interrupt flag

◆ DMA_ISR_GIF2_Msk

#define DMA_ISR_GIF2_Msk (0x1UL << DMA_ISR_GIF2_Pos)

0x00000010

◆ DMA_ISR_GIF2_Pos

#define DMA_ISR_GIF2_Pos (4U)

◆ DMA_ISR_GIF3

#define DMA_ISR_GIF3 DMA_ISR_GIF3_Msk

Channel 3 Global interrupt flag

◆ DMA_ISR_GIF3_Msk

#define DMA_ISR_GIF3_Msk (0x1UL << DMA_ISR_GIF3_Pos)

0x00000100

◆ DMA_ISR_GIF3_Pos

#define DMA_ISR_GIF3_Pos (8U)

◆ DMA_ISR_GIF4

#define DMA_ISR_GIF4 DMA_ISR_GIF4_Msk

Channel 4 Global interrupt flag

◆ DMA_ISR_GIF4_Msk

#define DMA_ISR_GIF4_Msk (0x1UL << DMA_ISR_GIF4_Pos)

0x00001000

◆ DMA_ISR_GIF4_Pos

#define DMA_ISR_GIF4_Pos (12U)

◆ DMA_ISR_GIF5

#define DMA_ISR_GIF5 DMA_ISR_GIF5_Msk

Channel 5 Global interrupt flag

◆ DMA_ISR_GIF5_Msk

#define DMA_ISR_GIF5_Msk (0x1UL << DMA_ISR_GIF5_Pos)

0x00010000

◆ DMA_ISR_GIF5_Pos

#define DMA_ISR_GIF5_Pos (16U)

◆ DMA_ISR_GIF6

#define DMA_ISR_GIF6 DMA_ISR_GIF6_Msk

Channel 6 Global interrupt flag

◆ DMA_ISR_GIF6_Msk

#define DMA_ISR_GIF6_Msk (0x1UL << DMA_ISR_GIF6_Pos)

0x00100000

◆ DMA_ISR_GIF6_Pos

#define DMA_ISR_GIF6_Pos (20U)

◆ DMA_ISR_GIF7

#define DMA_ISR_GIF7 DMA_ISR_GIF7_Msk

Channel 7 Global interrupt flag

◆ DMA_ISR_GIF7_Msk

#define DMA_ISR_GIF7_Msk (0x1UL << DMA_ISR_GIF7_Pos)

0x01000000

◆ DMA_ISR_GIF7_Pos

#define DMA_ISR_GIF7_Pos (24U)

◆ DMA_ISR_HTIF1

#define DMA_ISR_HTIF1 DMA_ISR_HTIF1_Msk

Channel 1 Half Transfer flag

◆ DMA_ISR_HTIF1_Msk

#define DMA_ISR_HTIF1_Msk (0x1UL << DMA_ISR_HTIF1_Pos)

0x00000004

◆ DMA_ISR_HTIF1_Pos

#define DMA_ISR_HTIF1_Pos (2U)

◆ DMA_ISR_HTIF2

#define DMA_ISR_HTIF2 DMA_ISR_HTIF2_Msk

Channel 2 Half Transfer flag

◆ DMA_ISR_HTIF2_Msk

#define DMA_ISR_HTIF2_Msk (0x1UL << DMA_ISR_HTIF2_Pos)

0x00000040

◆ DMA_ISR_HTIF2_Pos

#define DMA_ISR_HTIF2_Pos (6U)

◆ DMA_ISR_HTIF3

#define DMA_ISR_HTIF3 DMA_ISR_HTIF3_Msk

Channel 3 Half Transfer flag

◆ DMA_ISR_HTIF3_Msk

#define DMA_ISR_HTIF3_Msk (0x1UL << DMA_ISR_HTIF3_Pos)

0x00000400

◆ DMA_ISR_HTIF3_Pos

#define DMA_ISR_HTIF3_Pos (10U)

◆ DMA_ISR_HTIF4

#define DMA_ISR_HTIF4 DMA_ISR_HTIF4_Msk

Channel 4 Half Transfer flag

◆ DMA_ISR_HTIF4_Msk

#define DMA_ISR_HTIF4_Msk (0x1UL << DMA_ISR_HTIF4_Pos)

0x00004000

◆ DMA_ISR_HTIF4_Pos

#define DMA_ISR_HTIF4_Pos (14U)

◆ DMA_ISR_HTIF5

#define DMA_ISR_HTIF5 DMA_ISR_HTIF5_Msk

Channel 5 Half Transfer flag

◆ DMA_ISR_HTIF5_Msk

#define DMA_ISR_HTIF5_Msk (0x1UL << DMA_ISR_HTIF5_Pos)

0x00040000

◆ DMA_ISR_HTIF5_Pos

#define DMA_ISR_HTIF5_Pos (18U)

◆ DMA_ISR_HTIF6

#define DMA_ISR_HTIF6 DMA_ISR_HTIF6_Msk

Channel 6 Half Transfer flag

◆ DMA_ISR_HTIF6_Msk

#define DMA_ISR_HTIF6_Msk (0x1UL << DMA_ISR_HTIF6_Pos)

0x00400000

◆ DMA_ISR_HTIF6_Pos

#define DMA_ISR_HTIF6_Pos (22U)

◆ DMA_ISR_HTIF7

#define DMA_ISR_HTIF7 DMA_ISR_HTIF7_Msk

Channel 7 Half Transfer flag

◆ DMA_ISR_HTIF7_Msk

#define DMA_ISR_HTIF7_Msk (0x1UL << DMA_ISR_HTIF7_Pos)

0x04000000

◆ DMA_ISR_HTIF7_Pos

#define DMA_ISR_HTIF7_Pos (26U)

◆ DMA_ISR_TCIF1

#define DMA_ISR_TCIF1 DMA_ISR_TCIF1_Msk

Channel 1 Transfer Complete flag

◆ DMA_ISR_TCIF1_Msk

#define DMA_ISR_TCIF1_Msk (0x1UL << DMA_ISR_TCIF1_Pos)

0x00000002

◆ DMA_ISR_TCIF1_Pos

#define DMA_ISR_TCIF1_Pos (1U)

◆ DMA_ISR_TCIF2

#define DMA_ISR_TCIF2 DMA_ISR_TCIF2_Msk

Channel 2 Transfer Complete flag

◆ DMA_ISR_TCIF2_Msk

#define DMA_ISR_TCIF2_Msk (0x1UL << DMA_ISR_TCIF2_Pos)

0x00000020

◆ DMA_ISR_TCIF2_Pos

#define DMA_ISR_TCIF2_Pos (5U)

◆ DMA_ISR_TCIF3

#define DMA_ISR_TCIF3 DMA_ISR_TCIF3_Msk

Channel 3 Transfer Complete flag

◆ DMA_ISR_TCIF3_Msk

#define DMA_ISR_TCIF3_Msk (0x1UL << DMA_ISR_TCIF3_Pos)

0x00000200

◆ DMA_ISR_TCIF3_Pos

#define DMA_ISR_TCIF3_Pos (9U)

◆ DMA_ISR_TCIF4

#define DMA_ISR_TCIF4 DMA_ISR_TCIF4_Msk

Channel 4 Transfer Complete flag

◆ DMA_ISR_TCIF4_Msk

#define DMA_ISR_TCIF4_Msk (0x1UL << DMA_ISR_TCIF4_Pos)

0x00002000

◆ DMA_ISR_TCIF4_Pos

#define DMA_ISR_TCIF4_Pos (13U)

◆ DMA_ISR_TCIF5

#define DMA_ISR_TCIF5 DMA_ISR_TCIF5_Msk

Channel 5 Transfer Complete flag

◆ DMA_ISR_TCIF5_Msk

#define DMA_ISR_TCIF5_Msk (0x1UL << DMA_ISR_TCIF5_Pos)

0x00020000

◆ DMA_ISR_TCIF5_Pos

#define DMA_ISR_TCIF5_Pos (17U)

◆ DMA_ISR_TCIF6

#define DMA_ISR_TCIF6 DMA_ISR_TCIF6_Msk

Channel 6 Transfer Complete flag

◆ DMA_ISR_TCIF6_Msk

#define DMA_ISR_TCIF6_Msk (0x1UL << DMA_ISR_TCIF6_Pos)

0x00200000

◆ DMA_ISR_TCIF6_Pos

#define DMA_ISR_TCIF6_Pos (21U)

◆ DMA_ISR_TCIF7

#define DMA_ISR_TCIF7 DMA_ISR_TCIF7_Msk

Channel 7 Transfer Complete flag

◆ DMA_ISR_TCIF7_Msk

#define DMA_ISR_TCIF7_Msk (0x1UL << DMA_ISR_TCIF7_Pos)

0x02000000

◆ DMA_ISR_TCIF7_Pos

#define DMA_ISR_TCIF7_Pos (25U)

◆ DMA_ISR_TEIF1

#define DMA_ISR_TEIF1 DMA_ISR_TEIF1_Msk

Channel 1 Transfer Error flag

◆ DMA_ISR_TEIF1_Msk

#define DMA_ISR_TEIF1_Msk (0x1UL << DMA_ISR_TEIF1_Pos)

0x00000008

◆ DMA_ISR_TEIF1_Pos

#define DMA_ISR_TEIF1_Pos (3U)

◆ DMA_ISR_TEIF2

#define DMA_ISR_TEIF2 DMA_ISR_TEIF2_Msk

Channel 2 Transfer Error flag

◆ DMA_ISR_TEIF2_Msk

#define DMA_ISR_TEIF2_Msk (0x1UL << DMA_ISR_TEIF2_Pos)

0x00000080

◆ DMA_ISR_TEIF2_Pos

#define DMA_ISR_TEIF2_Pos (7U)

◆ DMA_ISR_TEIF3

#define DMA_ISR_TEIF3 DMA_ISR_TEIF3_Msk

Channel 3 Transfer Error flag

◆ DMA_ISR_TEIF3_Msk

#define DMA_ISR_TEIF3_Msk (0x1UL << DMA_ISR_TEIF3_Pos)

0x00000800

◆ DMA_ISR_TEIF3_Pos

#define DMA_ISR_TEIF3_Pos (11U)

◆ DMA_ISR_TEIF4

#define DMA_ISR_TEIF4 DMA_ISR_TEIF4_Msk

Channel 4 Transfer Error flag

◆ DMA_ISR_TEIF4_Msk

#define DMA_ISR_TEIF4_Msk (0x1UL << DMA_ISR_TEIF4_Pos)

0x00008000

◆ DMA_ISR_TEIF4_Pos

#define DMA_ISR_TEIF4_Pos (15U)

◆ DMA_ISR_TEIF5

#define DMA_ISR_TEIF5 DMA_ISR_TEIF5_Msk

Channel 5 Transfer Error flag

◆ DMA_ISR_TEIF5_Msk

#define DMA_ISR_TEIF5_Msk (0x1UL << DMA_ISR_TEIF5_Pos)

0x00080000

◆ DMA_ISR_TEIF5_Pos

#define DMA_ISR_TEIF5_Pos (19U)

◆ DMA_ISR_TEIF6

#define DMA_ISR_TEIF6 DMA_ISR_TEIF6_Msk

Channel 6 Transfer Error flag

◆ DMA_ISR_TEIF6_Msk

#define DMA_ISR_TEIF6_Msk (0x1UL << DMA_ISR_TEIF6_Pos)

0x00800000

◆ DMA_ISR_TEIF6_Pos

#define DMA_ISR_TEIF6_Pos (23U)

◆ DMA_ISR_TEIF7

#define DMA_ISR_TEIF7 DMA_ISR_TEIF7_Msk

Channel 7 Transfer Error flag

◆ DMA_ISR_TEIF7_Msk

#define DMA_ISR_TEIF7_Msk (0x1UL << DMA_ISR_TEIF7_Pos)

0x08000000

◆ DMA_ISR_TEIF7_Pos

#define DMA_ISR_TEIF7_Pos (27U)

◆ EXTI_32_63_SUPPORT

#define EXTI_32_63_SUPPORT /* EXTI support more than 32 lines */

◆ EXTI_EMR2_EM

#define EXTI_EMR2_EM EXTI_EMR2_EM_Msk

◆ EXTI_EMR2_EM32

#define EXTI_EMR2_EM32 EXTI_EMR2_MR32

◆ EXTI_EMR2_EM33

#define EXTI_EMR2_EM33 EXTI_EMR2_MR33

◆ EXTI_EMR2_EM34

#define EXTI_EMR2_EM34 EXTI_EMR2_MR34

◆ EXTI_EMR2_EM35

#define EXTI_EMR2_EM35 EXTI_EMR2_MR35

◆ EXTI_EMR2_EM_Msk

#define EXTI_EMR2_EM_Msk (0xFUL << EXTI_EMR2_EM_Pos)

0x0000000F

◆ EXTI_EMR2_EM_Pos

#define EXTI_EMR2_EM_Pos (0U)

◆ EXTI_EMR2_MR32

#define EXTI_EMR2_MR32 EXTI_EMR2_MR32_Msk

Event Mask on line 32

◆ EXTI_EMR2_MR32_Msk

#define EXTI_EMR2_MR32_Msk (0x1UL << EXTI_EMR2_MR32_Pos)

0x00000001

◆ EXTI_EMR2_MR32_Pos

#define EXTI_EMR2_MR32_Pos (0U)

◆ EXTI_EMR2_MR33

#define EXTI_EMR2_MR33 EXTI_EMR2_MR33_Msk

Event Mask on line 33

◆ EXTI_EMR2_MR33_Msk

#define EXTI_EMR2_MR33_Msk (0x1UL << EXTI_EMR2_MR33_Pos)

0x00000002

◆ EXTI_EMR2_MR33_Pos

#define EXTI_EMR2_MR33_Pos (1U)

◆ EXTI_EMR2_MR34

#define EXTI_EMR2_MR34 EXTI_EMR2_MR34_Msk

Event Mask on line 34

◆ EXTI_EMR2_MR34_Msk

#define EXTI_EMR2_MR34_Msk (0x1UL << EXTI_EMR2_MR34_Pos)

0x00000004

◆ EXTI_EMR2_MR34_Pos

#define EXTI_EMR2_MR34_Pos (2U)

◆ EXTI_EMR2_MR35

#define EXTI_EMR2_MR35 EXTI_EMR2_MR35_Msk

Event Mask on line 34

◆ EXTI_EMR2_MR35_Msk

#define EXTI_EMR2_MR35_Msk (0x1UL << EXTI_EMR2_MR35_Pos)

0x00000008

◆ EXTI_EMR2_MR35_Pos

#define EXTI_EMR2_MR35_Pos (3U)

◆ EXTI_EMR_EM0

#define EXTI_EMR_EM0 EXTI_EMR_MR0

◆ EXTI_EMR_EM1

#define EXTI_EMR_EM1 EXTI_EMR_MR1

◆ EXTI_EMR_EM10

#define EXTI_EMR_EM10 EXTI_EMR_MR10

◆ EXTI_EMR_EM11

#define EXTI_EMR_EM11 EXTI_EMR_MR11

◆ EXTI_EMR_EM12

#define EXTI_EMR_EM12 EXTI_EMR_MR12

◆ EXTI_EMR_EM13

#define EXTI_EMR_EM13 EXTI_EMR_MR13

◆ EXTI_EMR_EM14

#define EXTI_EMR_EM14 EXTI_EMR_MR14

◆ EXTI_EMR_EM15

#define EXTI_EMR_EM15 EXTI_EMR_MR15

◆ EXTI_EMR_EM16

#define EXTI_EMR_EM16 EXTI_EMR_MR16

◆ EXTI_EMR_EM17

#define EXTI_EMR_EM17 EXTI_EMR_MR17

◆ EXTI_EMR_EM18

#define EXTI_EMR_EM18 EXTI_EMR_MR18

◆ EXTI_EMR_EM19

#define EXTI_EMR_EM19 EXTI_EMR_MR19

◆ EXTI_EMR_EM2

#define EXTI_EMR_EM2 EXTI_EMR_MR2

◆ EXTI_EMR_EM20

#define EXTI_EMR_EM20 EXTI_EMR_MR20

◆ EXTI_EMR_EM21

#define EXTI_EMR_EM21 EXTI_EMR_MR21

◆ EXTI_EMR_EM22

#define EXTI_EMR_EM22 EXTI_EMR_MR22

◆ EXTI_EMR_EM23

#define EXTI_EMR_EM23 EXTI_EMR_MR23

◆ EXTI_EMR_EM24

#define EXTI_EMR_EM24 EXTI_EMR_MR24

◆ EXTI_EMR_EM25

#define EXTI_EMR_EM25 EXTI_EMR_MR25

◆ EXTI_EMR_EM26

#define EXTI_EMR_EM26 EXTI_EMR_MR26

◆ EXTI_EMR_EM27

#define EXTI_EMR_EM27 EXTI_EMR_MR27

◆ EXTI_EMR_EM28

#define EXTI_EMR_EM28 EXTI_EMR_MR28

◆ EXTI_EMR_EM29

#define EXTI_EMR_EM29 EXTI_EMR_MR29

◆ EXTI_EMR_EM3

#define EXTI_EMR_EM3 EXTI_EMR_MR3

◆ EXTI_EMR_EM30

#define EXTI_EMR_EM30 EXTI_EMR_MR30

◆ EXTI_EMR_EM31

#define EXTI_EMR_EM31 EXTI_EMR_MR31

◆ EXTI_EMR_EM4

#define EXTI_EMR_EM4 EXTI_EMR_MR4

◆ EXTI_EMR_EM5

#define EXTI_EMR_EM5 EXTI_EMR_MR5

◆ EXTI_EMR_EM6

#define EXTI_EMR_EM6 EXTI_EMR_MR6

◆ EXTI_EMR_EM7

#define EXTI_EMR_EM7 EXTI_EMR_MR7

◆ EXTI_EMR_EM8

#define EXTI_EMR_EM8 EXTI_EMR_MR8

◆ EXTI_EMR_EM9

#define EXTI_EMR_EM9 EXTI_EMR_MR9

◆ EXTI_EMR_MR0

#define EXTI_EMR_MR0 EXTI_EMR_MR0_Msk

Event Mask on line 0

◆ EXTI_EMR_MR0_Msk

#define EXTI_EMR_MR0_Msk (0x1UL << EXTI_EMR_MR0_Pos)

0x00000001

◆ EXTI_EMR_MR0_Pos

#define EXTI_EMR_MR0_Pos (0U)

◆ EXTI_EMR_MR1

#define EXTI_EMR_MR1 EXTI_EMR_MR1_Msk

Event Mask on line 1

◆ EXTI_EMR_MR10

#define EXTI_EMR_MR10 EXTI_EMR_MR10_Msk

Event Mask on line 10

◆ EXTI_EMR_MR10_Msk

#define EXTI_EMR_MR10_Msk (0x1UL << EXTI_EMR_MR10_Pos)

0x00000400

◆ EXTI_EMR_MR10_Pos

#define EXTI_EMR_MR10_Pos (10U)

◆ EXTI_EMR_MR11

#define EXTI_EMR_MR11 EXTI_EMR_MR11_Msk

Event Mask on line 11

◆ EXTI_EMR_MR11_Msk

#define EXTI_EMR_MR11_Msk (0x1UL << EXTI_EMR_MR11_Pos)

0x00000800

◆ EXTI_EMR_MR11_Pos

#define EXTI_EMR_MR11_Pos (11U)

◆ EXTI_EMR_MR12

#define EXTI_EMR_MR12 EXTI_EMR_MR12_Msk

Event Mask on line 12

◆ EXTI_EMR_MR12_Msk

#define EXTI_EMR_MR12_Msk (0x1UL << EXTI_EMR_MR12_Pos)

0x00001000

◆ EXTI_EMR_MR12_Pos

#define EXTI_EMR_MR12_Pos (12U)

◆ EXTI_EMR_MR13

#define EXTI_EMR_MR13 EXTI_EMR_MR13_Msk

Event Mask on line 13

◆ EXTI_EMR_MR13_Msk

#define EXTI_EMR_MR13_Msk (0x1UL << EXTI_EMR_MR13_Pos)

0x00002000

◆ EXTI_EMR_MR13_Pos

#define EXTI_EMR_MR13_Pos (13U)

◆ EXTI_EMR_MR14

#define EXTI_EMR_MR14 EXTI_EMR_MR14_Msk

Event Mask on line 14

◆ EXTI_EMR_MR14_Msk

#define EXTI_EMR_MR14_Msk (0x1UL << EXTI_EMR_MR14_Pos)

0x00004000

◆ EXTI_EMR_MR14_Pos

#define EXTI_EMR_MR14_Pos (14U)

◆ EXTI_EMR_MR15

#define EXTI_EMR_MR15 EXTI_EMR_MR15_Msk

Event Mask on line 15

◆ EXTI_EMR_MR15_Msk

#define EXTI_EMR_MR15_Msk (0x1UL << EXTI_EMR_MR15_Pos)

0x00008000

◆ EXTI_EMR_MR15_Pos

#define EXTI_EMR_MR15_Pos (15U)

◆ EXTI_EMR_MR16

#define EXTI_EMR_MR16 EXTI_EMR_MR16_Msk

Event Mask on line 16

◆ EXTI_EMR_MR16_Msk

#define EXTI_EMR_MR16_Msk (0x1UL << EXTI_EMR_MR16_Pos)

0x00010000

◆ EXTI_EMR_MR16_Pos

#define EXTI_EMR_MR16_Pos (16U)

◆ EXTI_EMR_MR17

#define EXTI_EMR_MR17 EXTI_EMR_MR17_Msk

Event Mask on line 17

◆ EXTI_EMR_MR17_Msk

#define EXTI_EMR_MR17_Msk (0x1UL << EXTI_EMR_MR17_Pos)

0x00020000

◆ EXTI_EMR_MR17_Pos

#define EXTI_EMR_MR17_Pos (17U)

◆ EXTI_EMR_MR18

#define EXTI_EMR_MR18 EXTI_EMR_MR18_Msk

Event Mask on line 18

◆ EXTI_EMR_MR18_Msk

#define EXTI_EMR_MR18_Msk (0x1UL << EXTI_EMR_MR18_Pos)

0x00040000

◆ EXTI_EMR_MR18_Pos

#define EXTI_EMR_MR18_Pos (18U)

◆ EXTI_EMR_MR19

#define EXTI_EMR_MR19 EXTI_EMR_MR19_Msk

Event Mask on line 19

◆ EXTI_EMR_MR19_Msk

#define EXTI_EMR_MR19_Msk (0x1UL << EXTI_EMR_MR19_Pos)

0x00080000

◆ EXTI_EMR_MR19_Pos

#define EXTI_EMR_MR19_Pos (19U)

◆ EXTI_EMR_MR1_Msk

#define EXTI_EMR_MR1_Msk (0x1UL << EXTI_EMR_MR1_Pos)

0x00000002

◆ EXTI_EMR_MR1_Pos

#define EXTI_EMR_MR1_Pos (1U)

◆ EXTI_EMR_MR2

#define EXTI_EMR_MR2 EXTI_EMR_MR2_Msk

Event Mask on line 2

◆ EXTI_EMR_MR20

#define EXTI_EMR_MR20 EXTI_EMR_MR20_Msk

Event Mask on line 20

◆ EXTI_EMR_MR20_Msk

#define EXTI_EMR_MR20_Msk (0x1UL << EXTI_EMR_MR20_Pos)

0x00100000

◆ EXTI_EMR_MR20_Pos

#define EXTI_EMR_MR20_Pos (20U)

◆ EXTI_EMR_MR21

#define EXTI_EMR_MR21 EXTI_EMR_MR21_Msk

Event Mask on line 21

◆ EXTI_EMR_MR21_Msk

#define EXTI_EMR_MR21_Msk (0x1UL << EXTI_EMR_MR21_Pos)

0x00200000

◆ EXTI_EMR_MR21_Pos

#define EXTI_EMR_MR21_Pos (21U)

◆ EXTI_EMR_MR22

#define EXTI_EMR_MR22 EXTI_EMR_MR22_Msk

Event Mask on line 22

◆ EXTI_EMR_MR22_Msk

#define EXTI_EMR_MR22_Msk (0x1UL << EXTI_EMR_MR22_Pos)

0x00400000

◆ EXTI_EMR_MR22_Pos

#define EXTI_EMR_MR22_Pos (22U)

◆ EXTI_EMR_MR23

#define EXTI_EMR_MR23 EXTI_EMR_MR23_Msk

Event Mask on line 23

◆ EXTI_EMR_MR23_Msk

#define EXTI_EMR_MR23_Msk (0x1UL << EXTI_EMR_MR23_Pos)

0x00800000

◆ EXTI_EMR_MR23_Pos

#define EXTI_EMR_MR23_Pos (23U)

◆ EXTI_EMR_MR24

#define EXTI_EMR_MR24 EXTI_EMR_MR24_Msk

Event Mask on line 24

◆ EXTI_EMR_MR24_Msk

#define EXTI_EMR_MR24_Msk (0x1UL << EXTI_EMR_MR24_Pos)

0x01000000

◆ EXTI_EMR_MR24_Pos

#define EXTI_EMR_MR24_Pos (24U)

◆ EXTI_EMR_MR25

#define EXTI_EMR_MR25 EXTI_EMR_MR25_Msk

Event Mask on line 25

◆ EXTI_EMR_MR25_Msk

#define EXTI_EMR_MR25_Msk (0x1UL << EXTI_EMR_MR25_Pos)

0x02000000

◆ EXTI_EMR_MR25_Pos

#define EXTI_EMR_MR25_Pos (25U)

◆ EXTI_EMR_MR26

#define EXTI_EMR_MR26 EXTI_EMR_MR26_Msk

Event Mask on line 26

◆ EXTI_EMR_MR26_Msk

#define EXTI_EMR_MR26_Msk (0x1UL << EXTI_EMR_MR26_Pos)

0x04000000

◆ EXTI_EMR_MR26_Pos

#define EXTI_EMR_MR26_Pos (26U)

◆ EXTI_EMR_MR27

#define EXTI_EMR_MR27 EXTI_EMR_MR27_Msk

Event Mask on line 27

◆ EXTI_EMR_MR27_Msk

#define EXTI_EMR_MR27_Msk (0x1UL << EXTI_EMR_MR27_Pos)

0x08000000

◆ EXTI_EMR_MR27_Pos

#define EXTI_EMR_MR27_Pos (27U)

◆ EXTI_EMR_MR28

#define EXTI_EMR_MR28 EXTI_EMR_MR28_Msk

Event Mask on line 28

◆ EXTI_EMR_MR28_Msk

#define EXTI_EMR_MR28_Msk (0x1UL << EXTI_EMR_MR28_Pos)

0x10000000

◆ EXTI_EMR_MR28_Pos

#define EXTI_EMR_MR28_Pos (28U)

◆ EXTI_EMR_MR29

#define EXTI_EMR_MR29 EXTI_EMR_MR29_Msk

Event Mask on line 29

◆ EXTI_EMR_MR29_Msk

#define EXTI_EMR_MR29_Msk (0x1UL << EXTI_EMR_MR29_Pos)

0x20000000

◆ EXTI_EMR_MR29_Pos

#define EXTI_EMR_MR29_Pos (29U)

◆ EXTI_EMR_MR2_Msk

#define EXTI_EMR_MR2_Msk (0x1UL << EXTI_EMR_MR2_Pos)

0x00000004

◆ EXTI_EMR_MR2_Pos

#define EXTI_EMR_MR2_Pos (2U)

◆ EXTI_EMR_MR3

#define EXTI_EMR_MR3 EXTI_EMR_MR3_Msk

Event Mask on line 3

◆ EXTI_EMR_MR30

#define EXTI_EMR_MR30 EXTI_EMR_MR30_Msk

Event Mask on line 30

◆ EXTI_EMR_MR30_Msk

#define EXTI_EMR_MR30_Msk (0x1UL << EXTI_EMR_MR30_Pos)

0x40000000

◆ EXTI_EMR_MR30_Pos

#define EXTI_EMR_MR30_Pos (30U)

◆ EXTI_EMR_MR31

#define EXTI_EMR_MR31 EXTI_EMR_MR31_Msk

Event Mask on line 31

◆ EXTI_EMR_MR31_Msk

#define EXTI_EMR_MR31_Msk (0x1UL << EXTI_EMR_MR31_Pos)

0x80000000

◆ EXTI_EMR_MR31_Pos

#define EXTI_EMR_MR31_Pos (31U)

◆ EXTI_EMR_MR3_Msk

#define EXTI_EMR_MR3_Msk (0x1UL << EXTI_EMR_MR3_Pos)

0x00000008

◆ EXTI_EMR_MR3_Pos

#define EXTI_EMR_MR3_Pos (3U)

◆ EXTI_EMR_MR4

#define EXTI_EMR_MR4 EXTI_EMR_MR4_Msk

Event Mask on line 4

◆ EXTI_EMR_MR4_Msk

#define EXTI_EMR_MR4_Msk (0x1UL << EXTI_EMR_MR4_Pos)

0x00000010

◆ EXTI_EMR_MR4_Pos

#define EXTI_EMR_MR4_Pos (4U)

◆ EXTI_EMR_MR5

#define EXTI_EMR_MR5 EXTI_EMR_MR5_Msk

Event Mask on line 5

◆ EXTI_EMR_MR5_Msk

#define EXTI_EMR_MR5_Msk (0x1UL << EXTI_EMR_MR5_Pos)

0x00000020

◆ EXTI_EMR_MR5_Pos

#define EXTI_EMR_MR5_Pos (5U)

◆ EXTI_EMR_MR6

#define EXTI_EMR_MR6 EXTI_EMR_MR6_Msk

Event Mask on line 6

◆ EXTI_EMR_MR6_Msk

#define EXTI_EMR_MR6_Msk (0x1UL << EXTI_EMR_MR6_Pos)

0x00000040

◆ EXTI_EMR_MR6_Pos

#define EXTI_EMR_MR6_Pos (6U)

◆ EXTI_EMR_MR7

#define EXTI_EMR_MR7 EXTI_EMR_MR7_Msk

Event Mask on line 7

◆ EXTI_EMR_MR7_Msk

#define EXTI_EMR_MR7_Msk (0x1UL << EXTI_EMR_MR7_Pos)

0x00000080

◆ EXTI_EMR_MR7_Pos

#define EXTI_EMR_MR7_Pos (7U)

◆ EXTI_EMR_MR8

#define EXTI_EMR_MR8 EXTI_EMR_MR8_Msk

Event Mask on line 8

◆ EXTI_EMR_MR8_Msk

#define EXTI_EMR_MR8_Msk (0x1UL << EXTI_EMR_MR8_Pos)

0x00000100

◆ EXTI_EMR_MR8_Pos

#define EXTI_EMR_MR8_Pos (8U)

◆ EXTI_EMR_MR9

#define EXTI_EMR_MR9 EXTI_EMR_MR9_Msk

Event Mask on line 9

◆ EXTI_EMR_MR9_Msk

#define EXTI_EMR_MR9_Msk (0x1UL << EXTI_EMR_MR9_Pos)

0x00000200

◆ EXTI_EMR_MR9_Pos

#define EXTI_EMR_MR9_Pos (9U)

◆ EXTI_FTSR2_FT32

#define EXTI_FTSR2_FT32 EXTI_FTSR2_TR32

◆ EXTI_FTSR2_FT33

#define EXTI_FTSR2_FT33 EXTI_FTSR2_TR33

◆ EXTI_FTSR2_TR32

#define EXTI_FTSR2_TR32 EXTI_FTSR2_TR32_Msk

Falling trigger event configuration bit of line 32

◆ EXTI_FTSR2_TR32_Msk

#define EXTI_FTSR2_TR32_Msk (0x1UL << EXTI_FTSR2_TR32_Pos)

0x00000001

◆ EXTI_FTSR2_TR32_Pos

#define EXTI_FTSR2_TR32_Pos (0U)

◆ EXTI_FTSR2_TR33

#define EXTI_FTSR2_TR33 EXTI_FTSR2_TR33_Msk

Falling trigger event configuration bit of line 33

◆ EXTI_FTSR2_TR33_Msk

#define EXTI_FTSR2_TR33_Msk (0x1UL << EXTI_FTSR2_TR33_Pos)

0x00000002

◆ EXTI_FTSR2_TR33_Pos

#define EXTI_FTSR2_TR33_Pos (1U)

◆ EXTI_FTSR_FT0

#define EXTI_FTSR_FT0 EXTI_FTSR_TR0

◆ EXTI_FTSR_FT1

#define EXTI_FTSR_FT1 EXTI_FTSR_TR1

◆ EXTI_FTSR_FT10

#define EXTI_FTSR_FT10 EXTI_FTSR_TR10

◆ EXTI_FTSR_FT11

#define EXTI_FTSR_FT11 EXTI_FTSR_TR11

◆ EXTI_FTSR_FT12

#define EXTI_FTSR_FT12 EXTI_FTSR_TR12

◆ EXTI_FTSR_FT13

#define EXTI_FTSR_FT13 EXTI_FTSR_TR13

◆ EXTI_FTSR_FT14

#define EXTI_FTSR_FT14 EXTI_FTSR_TR14

◆ EXTI_FTSR_FT15

#define EXTI_FTSR_FT15 EXTI_FTSR_TR15

◆ EXTI_FTSR_FT16

#define EXTI_FTSR_FT16 EXTI_FTSR_TR16

◆ EXTI_FTSR_FT17

#define EXTI_FTSR_FT17 EXTI_FTSR_TR17

◆ EXTI_FTSR_FT18

#define EXTI_FTSR_FT18 EXTI_FTSR_TR18

◆ EXTI_FTSR_FT19

#define EXTI_FTSR_FT19 EXTI_FTSR_TR19

◆ EXTI_FTSR_FT2

#define EXTI_FTSR_FT2 EXTI_FTSR_TR2

◆ EXTI_FTSR_FT20

#define EXTI_FTSR_FT20 EXTI_FTSR_TR20

◆ EXTI_FTSR_FT21

#define EXTI_FTSR_FT21 EXTI_FTSR_TR21

◆ EXTI_FTSR_FT22

#define EXTI_FTSR_FT22 EXTI_FTSR_TR22

◆ EXTI_FTSR_FT29

#define EXTI_FTSR_FT29 EXTI_FTSR_TR29

◆ EXTI_FTSR_FT3

#define EXTI_FTSR_FT3 EXTI_FTSR_TR3

◆ EXTI_FTSR_FT30

#define EXTI_FTSR_FT30 EXTI_FTSR_TR30

◆ EXTI_FTSR_FT31

#define EXTI_FTSR_FT31 EXTI_FTSR_TR31

◆ EXTI_FTSR_FT4

#define EXTI_FTSR_FT4 EXTI_FTSR_TR4

◆ EXTI_FTSR_FT5

#define EXTI_FTSR_FT5 EXTI_FTSR_TR5

◆ EXTI_FTSR_FT6

#define EXTI_FTSR_FT6 EXTI_FTSR_TR6

◆ EXTI_FTSR_FT7

#define EXTI_FTSR_FT7 EXTI_FTSR_TR7

◆ EXTI_FTSR_FT8

#define EXTI_FTSR_FT8 EXTI_FTSR_TR8

◆ EXTI_FTSR_FT9

#define EXTI_FTSR_FT9 EXTI_FTSR_TR9

◆ EXTI_FTSR_TR0

#define EXTI_FTSR_TR0 EXTI_FTSR_TR0_Msk

Falling trigger event configuration bit of line 0

◆ EXTI_FTSR_TR0_Msk

#define EXTI_FTSR_TR0_Msk (0x1UL << EXTI_FTSR_TR0_Pos)

0x00000001

◆ EXTI_FTSR_TR0_Pos

#define EXTI_FTSR_TR0_Pos (0U)

◆ EXTI_FTSR_TR1

#define EXTI_FTSR_TR1 EXTI_FTSR_TR1_Msk

Falling trigger event configuration bit of line 1

◆ EXTI_FTSR_TR10

#define EXTI_FTSR_TR10 EXTI_FTSR_TR10_Msk

Falling trigger event configuration bit of line 10

◆ EXTI_FTSR_TR10_Msk

#define EXTI_FTSR_TR10_Msk (0x1UL << EXTI_FTSR_TR10_Pos)

0x00000400

◆ EXTI_FTSR_TR10_Pos

#define EXTI_FTSR_TR10_Pos (10U)

◆ EXTI_FTSR_TR11

#define EXTI_FTSR_TR11 EXTI_FTSR_TR11_Msk

Falling trigger event configuration bit of line 11

◆ EXTI_FTSR_TR11_Msk

#define EXTI_FTSR_TR11_Msk (0x1UL << EXTI_FTSR_TR11_Pos)

0x00000800

◆ EXTI_FTSR_TR11_Pos

#define EXTI_FTSR_TR11_Pos (11U)

◆ EXTI_FTSR_TR12

#define EXTI_FTSR_TR12 EXTI_FTSR_TR12_Msk

Falling trigger event configuration bit of line 12

◆ EXTI_FTSR_TR12_Msk

#define EXTI_FTSR_TR12_Msk (0x1UL << EXTI_FTSR_TR12_Pos)

0x00001000

◆ EXTI_FTSR_TR12_Pos

#define EXTI_FTSR_TR12_Pos (12U)

◆ EXTI_FTSR_TR13

#define EXTI_FTSR_TR13 EXTI_FTSR_TR13_Msk

Falling trigger event configuration bit of line 13

◆ EXTI_FTSR_TR13_Msk

#define EXTI_FTSR_TR13_Msk (0x1UL << EXTI_FTSR_TR13_Pos)

0x00002000

◆ EXTI_FTSR_TR13_Pos

#define EXTI_FTSR_TR13_Pos (13U)

◆ EXTI_FTSR_TR14

#define EXTI_FTSR_TR14 EXTI_FTSR_TR14_Msk

Falling trigger event configuration bit of line 14

◆ EXTI_FTSR_TR14_Msk

#define EXTI_FTSR_TR14_Msk (0x1UL << EXTI_FTSR_TR14_Pos)

0x00004000

◆ EXTI_FTSR_TR14_Pos

#define EXTI_FTSR_TR14_Pos (14U)

◆ EXTI_FTSR_TR15

#define EXTI_FTSR_TR15 EXTI_FTSR_TR15_Msk

Falling trigger event configuration bit of line 15

◆ EXTI_FTSR_TR15_Msk

#define EXTI_FTSR_TR15_Msk (0x1UL << EXTI_FTSR_TR15_Pos)

0x00008000

◆ EXTI_FTSR_TR15_Pos

#define EXTI_FTSR_TR15_Pos (15U)

◆ EXTI_FTSR_TR16

#define EXTI_FTSR_TR16 EXTI_FTSR_TR16_Msk

Falling trigger event configuration bit of line 16

◆ EXTI_FTSR_TR16_Msk

#define EXTI_FTSR_TR16_Msk (0x1UL << EXTI_FTSR_TR16_Pos)

0x00010000

◆ EXTI_FTSR_TR16_Pos

#define EXTI_FTSR_TR16_Pos (16U)

◆ EXTI_FTSR_TR17

#define EXTI_FTSR_TR17 EXTI_FTSR_TR17_Msk

Falling trigger event configuration bit of line 17

◆ EXTI_FTSR_TR17_Msk

#define EXTI_FTSR_TR17_Msk (0x1UL << EXTI_FTSR_TR17_Pos)

0x00020000

◆ EXTI_FTSR_TR17_Pos

#define EXTI_FTSR_TR17_Pos (17U)

◆ EXTI_FTSR_TR18

#define EXTI_FTSR_TR18 EXTI_FTSR_TR18_Msk

Falling trigger event configuration bit of line 18

◆ EXTI_FTSR_TR18_Msk

#define EXTI_FTSR_TR18_Msk (0x1UL << EXTI_FTSR_TR18_Pos)

0x00040000

◆ EXTI_FTSR_TR18_Pos

#define EXTI_FTSR_TR18_Pos (18U)

◆ EXTI_FTSR_TR19

#define EXTI_FTSR_TR19 EXTI_FTSR_TR19_Msk

Falling trigger event configuration bit of line 19

◆ EXTI_FTSR_TR19_Msk

#define EXTI_FTSR_TR19_Msk (0x1UL << EXTI_FTSR_TR19_Pos)

0x00080000

◆ EXTI_FTSR_TR19_Pos

#define EXTI_FTSR_TR19_Pos (19U)

◆ EXTI_FTSR_TR1_Msk

#define EXTI_FTSR_TR1_Msk (0x1UL << EXTI_FTSR_TR1_Pos)

0x00000002

◆ EXTI_FTSR_TR1_Pos

#define EXTI_FTSR_TR1_Pos (1U)

◆ EXTI_FTSR_TR2

#define EXTI_FTSR_TR2 EXTI_FTSR_TR2_Msk

Falling trigger event configuration bit of line 2

◆ EXTI_FTSR_TR20

#define EXTI_FTSR_TR20 EXTI_FTSR_TR20_Msk

Falling trigger event configuration bit of line 20

◆ EXTI_FTSR_TR20_Msk

#define EXTI_FTSR_TR20_Msk (0x1UL << EXTI_FTSR_TR20_Pos)

0x00100000

◆ EXTI_FTSR_TR20_Pos

#define EXTI_FTSR_TR20_Pos (20U)

◆ EXTI_FTSR_TR21

#define EXTI_FTSR_TR21 EXTI_FTSR_TR21_Msk

Falling trigger event configuration bit of line 21

◆ EXTI_FTSR_TR21_Msk

#define EXTI_FTSR_TR21_Msk (0x1UL << EXTI_FTSR_TR21_Pos)

0x00200000

◆ EXTI_FTSR_TR21_Pos

#define EXTI_FTSR_TR21_Pos (21U)

◆ EXTI_FTSR_TR22

#define EXTI_FTSR_TR22 EXTI_FTSR_TR22_Msk

Falling trigger event configuration bit of line 22

◆ EXTI_FTSR_TR22_Msk

#define EXTI_FTSR_TR22_Msk (0x1UL << EXTI_FTSR_TR22_Pos)

0x00400000

◆ EXTI_FTSR_TR22_Pos

#define EXTI_FTSR_TR22_Pos (22U)

◆ EXTI_FTSR_TR29

#define EXTI_FTSR_TR29 EXTI_FTSR_TR29_Msk

Falling trigger event configuration bit of line 29

◆ EXTI_FTSR_TR29_Msk

#define EXTI_FTSR_TR29_Msk (0x1UL << EXTI_FTSR_TR29_Pos)

0x20000000

◆ EXTI_FTSR_TR29_Pos

#define EXTI_FTSR_TR29_Pos (29U)

◆ EXTI_FTSR_TR2_Msk

#define EXTI_FTSR_TR2_Msk (0x1UL << EXTI_FTSR_TR2_Pos)

0x00000004

◆ EXTI_FTSR_TR2_Pos

#define EXTI_FTSR_TR2_Pos (2U)

◆ EXTI_FTSR_TR3

#define EXTI_FTSR_TR3 EXTI_FTSR_TR3_Msk

Falling trigger event configuration bit of line 3

◆ EXTI_FTSR_TR30

#define EXTI_FTSR_TR30 EXTI_FTSR_TR30_Msk

Falling trigger event configuration bit of line 30

◆ EXTI_FTSR_TR30_Msk

#define EXTI_FTSR_TR30_Msk (0x1UL << EXTI_FTSR_TR30_Pos)

0x40000000

◆ EXTI_FTSR_TR30_Pos

#define EXTI_FTSR_TR30_Pos (30U)

◆ EXTI_FTSR_TR31

#define EXTI_FTSR_TR31 EXTI_FTSR_TR31_Msk

Falling trigger event configuration bit of line 31

◆ EXTI_FTSR_TR31_Msk

#define EXTI_FTSR_TR31_Msk (0x1UL << EXTI_FTSR_TR31_Pos)

0x80000000

◆ EXTI_FTSR_TR31_Pos

#define EXTI_FTSR_TR31_Pos (31U)

◆ EXTI_FTSR_TR3_Msk

#define EXTI_FTSR_TR3_Msk (0x1UL << EXTI_FTSR_TR3_Pos)

0x00000008

◆ EXTI_FTSR_TR3_Pos

#define EXTI_FTSR_TR3_Pos (3U)

◆ EXTI_FTSR_TR4

#define EXTI_FTSR_TR4 EXTI_FTSR_TR4_Msk

Falling trigger event configuration bit of line 4

◆ EXTI_FTSR_TR4_Msk

#define EXTI_FTSR_TR4_Msk (0x1UL << EXTI_FTSR_TR4_Pos)

0x00000010

◆ EXTI_FTSR_TR4_Pos

#define EXTI_FTSR_TR4_Pos (4U)

◆ EXTI_FTSR_TR5

#define EXTI_FTSR_TR5 EXTI_FTSR_TR5_Msk

Falling trigger event configuration bit of line 5

◆ EXTI_FTSR_TR5_Msk

#define EXTI_FTSR_TR5_Msk (0x1UL << EXTI_FTSR_TR5_Pos)

0x00000020

◆ EXTI_FTSR_TR5_Pos

#define EXTI_FTSR_TR5_Pos (5U)

◆ EXTI_FTSR_TR6

#define EXTI_FTSR_TR6 EXTI_FTSR_TR6_Msk

Falling trigger event configuration bit of line 6

◆ EXTI_FTSR_TR6_Msk

#define EXTI_FTSR_TR6_Msk (0x1UL << EXTI_FTSR_TR6_Pos)

0x00000040

◆ EXTI_FTSR_TR6_Pos

#define EXTI_FTSR_TR6_Pos (6U)

◆ EXTI_FTSR_TR7

#define EXTI_FTSR_TR7 EXTI_FTSR_TR7_Msk

Falling trigger event configuration bit of line 7

◆ EXTI_FTSR_TR7_Msk

#define EXTI_FTSR_TR7_Msk (0x1UL << EXTI_FTSR_TR7_Pos)

0x00000080

◆ EXTI_FTSR_TR7_Pos

#define EXTI_FTSR_TR7_Pos (7U)

◆ EXTI_FTSR_TR8

#define EXTI_FTSR_TR8 EXTI_FTSR_TR8_Msk

Falling trigger event configuration bit of line 8

◆ EXTI_FTSR_TR8_Msk

#define EXTI_FTSR_TR8_Msk (0x1UL << EXTI_FTSR_TR8_Pos)

0x00000100

◆ EXTI_FTSR_TR8_Pos

#define EXTI_FTSR_TR8_Pos (8U)

◆ EXTI_FTSR_TR9

#define EXTI_FTSR_TR9 EXTI_FTSR_TR9_Msk

Falling trigger event configuration bit of line 9

◆ EXTI_FTSR_TR9_Msk

#define EXTI_FTSR_TR9_Msk (0x1UL << EXTI_FTSR_TR9_Pos)

0x00000200

◆ EXTI_FTSR_TR9_Pos

#define EXTI_FTSR_TR9_Pos (9U)

◆ EXTI_IMR2_IM

#define EXTI_IMR2_IM EXTI_IMR2_IM_Msk

◆ EXTI_IMR2_IM32

#define EXTI_IMR2_IM32 EXTI_IMR2_MR32

◆ EXTI_IMR2_IM33

#define EXTI_IMR2_IM33 EXTI_IMR2_MR33

◆ EXTI_IMR2_IM34

#define EXTI_IMR2_IM34 EXTI_IMR2_MR34

◆ EXTI_IMR2_IM35

#define EXTI_IMR2_IM35 EXTI_IMR2_MR35

◆ EXTI_IMR2_IM_Msk

#define EXTI_IMR2_IM_Msk (0xFUL << EXTI_IMR2_IM_Pos)

0x0000000F

◆ EXTI_IMR2_IM_Pos

#define EXTI_IMR2_IM_Pos (0U)

◆ EXTI_IMR2_MR32

#define EXTI_IMR2_MR32 EXTI_IMR2_MR32_Msk

Interrupt Mask on line 32

◆ EXTI_IMR2_MR32_Msk

#define EXTI_IMR2_MR32_Msk (0x1UL << EXTI_IMR2_MR32_Pos)

0x00000001

◆ EXTI_IMR2_MR32_Pos

#define EXTI_IMR2_MR32_Pos (0U)

◆ EXTI_IMR2_MR33

#define EXTI_IMR2_MR33 EXTI_IMR2_MR33_Msk

Interrupt Mask on line 33

◆ EXTI_IMR2_MR33_Msk

#define EXTI_IMR2_MR33_Msk (0x1UL << EXTI_IMR2_MR33_Pos)

0x00000002

◆ EXTI_IMR2_MR33_Pos

#define EXTI_IMR2_MR33_Pos (1U)

◆ EXTI_IMR2_MR34

#define EXTI_IMR2_MR34 EXTI_IMR2_MR34_Msk

Interrupt Mask on line 34

◆ EXTI_IMR2_MR34_Msk

#define EXTI_IMR2_MR34_Msk (0x1UL << EXTI_IMR2_MR34_Pos)

0x00000004

◆ EXTI_IMR2_MR34_Pos

#define EXTI_IMR2_MR34_Pos (2U)

◆ EXTI_IMR2_MR35

#define EXTI_IMR2_MR35 EXTI_IMR2_MR35_Msk

Interrupt Mask on line 35

◆ EXTI_IMR2_MR35_Msk

#define EXTI_IMR2_MR35_Msk (0x1UL << EXTI_IMR2_MR35_Pos)

0x00000008

◆ EXTI_IMR2_MR35_Pos

#define EXTI_IMR2_MR35_Pos (3U)

◆ EXTI_IMR_IM

#define EXTI_IMR_IM EXTI_IMR_IM_Msk

Interrupt Mask All

◆ EXTI_IMR_IM0

#define EXTI_IMR_IM0 EXTI_IMR_MR0

◆ EXTI_IMR_IM1

#define EXTI_IMR_IM1 EXTI_IMR_MR1

◆ EXTI_IMR_IM10

#define EXTI_IMR_IM10 EXTI_IMR_MR10

◆ EXTI_IMR_IM11

#define EXTI_IMR_IM11 EXTI_IMR_MR11

◆ EXTI_IMR_IM12

#define EXTI_IMR_IM12 EXTI_IMR_MR12

◆ EXTI_IMR_IM13

#define EXTI_IMR_IM13 EXTI_IMR_MR13

◆ EXTI_IMR_IM14

#define EXTI_IMR_IM14 EXTI_IMR_MR14

◆ EXTI_IMR_IM15

#define EXTI_IMR_IM15 EXTI_IMR_MR15

◆ EXTI_IMR_IM16

#define EXTI_IMR_IM16 EXTI_IMR_MR16

◆ EXTI_IMR_IM17

#define EXTI_IMR_IM17 EXTI_IMR_MR17

◆ EXTI_IMR_IM18

#define EXTI_IMR_IM18 EXTI_IMR_MR18

◆ EXTI_IMR_IM19

#define EXTI_IMR_IM19 EXTI_IMR_MR19

◆ EXTI_IMR_IM2

#define EXTI_IMR_IM2 EXTI_IMR_MR2

◆ EXTI_IMR_IM20

#define EXTI_IMR_IM20 EXTI_IMR_MR20

◆ EXTI_IMR_IM21

#define EXTI_IMR_IM21 EXTI_IMR_MR21

◆ EXTI_IMR_IM22

#define EXTI_IMR_IM22 EXTI_IMR_MR22

◆ EXTI_IMR_IM23

#define EXTI_IMR_IM23 EXTI_IMR_MR23

◆ EXTI_IMR_IM24

#define EXTI_IMR_IM24 EXTI_IMR_MR24

◆ EXTI_IMR_IM25

#define EXTI_IMR_IM25 EXTI_IMR_MR25

◆ EXTI_IMR_IM26

#define EXTI_IMR_IM26 EXTI_IMR_MR26

◆ EXTI_IMR_IM27

#define EXTI_IMR_IM27 EXTI_IMR_MR27

◆ EXTI_IMR_IM28

#define EXTI_IMR_IM28 EXTI_IMR_MR28

◆ EXTI_IMR_IM29

#define EXTI_IMR_IM29 EXTI_IMR_MR29

◆ EXTI_IMR_IM3

#define EXTI_IMR_IM3 EXTI_IMR_MR3

◆ EXTI_IMR_IM30

#define EXTI_IMR_IM30 EXTI_IMR_MR30

◆ EXTI_IMR_IM31

#define EXTI_IMR_IM31 EXTI_IMR_MR31

◆ EXTI_IMR_IM4

#define EXTI_IMR_IM4 EXTI_IMR_MR4

◆ EXTI_IMR_IM5

#define EXTI_IMR_IM5 EXTI_IMR_MR5

◆ EXTI_IMR_IM6

#define EXTI_IMR_IM6 EXTI_IMR_MR6

◆ EXTI_IMR_IM7

#define EXTI_IMR_IM7 EXTI_IMR_MR7

◆ EXTI_IMR_IM8

#define EXTI_IMR_IM8 EXTI_IMR_MR8

◆ EXTI_IMR_IM9

#define EXTI_IMR_IM9 EXTI_IMR_MR9

◆ EXTI_IMR_IM_Msk

#define EXTI_IMR_IM_Msk (0xFFFFFFFFUL << EXTI_IMR_IM_Pos)

0xFFFFFFFF

◆ EXTI_IMR_IM_Pos

#define EXTI_IMR_IM_Pos (0U)

◆ EXTI_IMR_MR0

#define EXTI_IMR_MR0 EXTI_IMR_MR0_Msk

Interrupt Mask on line 0

◆ EXTI_IMR_MR0_Msk

#define EXTI_IMR_MR0_Msk (0x1UL << EXTI_IMR_MR0_Pos)

0x00000001

◆ EXTI_IMR_MR0_Pos

#define EXTI_IMR_MR0_Pos (0U)

◆ EXTI_IMR_MR1

#define EXTI_IMR_MR1 EXTI_IMR_MR1_Msk

Interrupt Mask on line 1

◆ EXTI_IMR_MR10

#define EXTI_IMR_MR10 EXTI_IMR_MR10_Msk

Interrupt Mask on line 10

◆ EXTI_IMR_MR10_Msk

#define EXTI_IMR_MR10_Msk (0x1UL << EXTI_IMR_MR10_Pos)

0x00000400

◆ EXTI_IMR_MR10_Pos

#define EXTI_IMR_MR10_Pos (10U)

◆ EXTI_IMR_MR11

#define EXTI_IMR_MR11 EXTI_IMR_MR11_Msk

Interrupt Mask on line 11

◆ EXTI_IMR_MR11_Msk

#define EXTI_IMR_MR11_Msk (0x1UL << EXTI_IMR_MR11_Pos)

0x00000800

◆ EXTI_IMR_MR11_Pos

#define EXTI_IMR_MR11_Pos (11U)

◆ EXTI_IMR_MR12

#define EXTI_IMR_MR12 EXTI_IMR_MR12_Msk

Interrupt Mask on line 12

◆ EXTI_IMR_MR12_Msk

#define EXTI_IMR_MR12_Msk (0x1UL << EXTI_IMR_MR12_Pos)

0x00001000

◆ EXTI_IMR_MR12_Pos

#define EXTI_IMR_MR12_Pos (12U)

◆ EXTI_IMR_MR13

#define EXTI_IMR_MR13 EXTI_IMR_MR13_Msk

Interrupt Mask on line 13

◆ EXTI_IMR_MR13_Msk

#define EXTI_IMR_MR13_Msk (0x1UL << EXTI_IMR_MR13_Pos)

0x00002000

◆ EXTI_IMR_MR13_Pos

#define EXTI_IMR_MR13_Pos (13U)

◆ EXTI_IMR_MR14

#define EXTI_IMR_MR14 EXTI_IMR_MR14_Msk

Interrupt Mask on line 14

◆ EXTI_IMR_MR14_Msk

#define EXTI_IMR_MR14_Msk (0x1UL << EXTI_IMR_MR14_Pos)

0x00004000

◆ EXTI_IMR_MR14_Pos

#define EXTI_IMR_MR14_Pos (14U)

◆ EXTI_IMR_MR15

#define EXTI_IMR_MR15 EXTI_IMR_MR15_Msk

Interrupt Mask on line 15

◆ EXTI_IMR_MR15_Msk

#define EXTI_IMR_MR15_Msk (0x1UL << EXTI_IMR_MR15_Pos)

0x00008000

◆ EXTI_IMR_MR15_Pos

#define EXTI_IMR_MR15_Pos (15U)

◆ EXTI_IMR_MR16

#define EXTI_IMR_MR16 EXTI_IMR_MR16_Msk

Interrupt Mask on line 16

◆ EXTI_IMR_MR16_Msk

#define EXTI_IMR_MR16_Msk (0x1UL << EXTI_IMR_MR16_Pos)

0x00010000

◆ EXTI_IMR_MR16_Pos

#define EXTI_IMR_MR16_Pos (16U)

◆ EXTI_IMR_MR17

#define EXTI_IMR_MR17 EXTI_IMR_MR17_Msk

Interrupt Mask on line 17

◆ EXTI_IMR_MR17_Msk

#define EXTI_IMR_MR17_Msk (0x1UL << EXTI_IMR_MR17_Pos)

0x00020000

◆ EXTI_IMR_MR17_Pos

#define EXTI_IMR_MR17_Pos (17U)

◆ EXTI_IMR_MR18

#define EXTI_IMR_MR18 EXTI_IMR_MR18_Msk

Interrupt Mask on line 18

◆ EXTI_IMR_MR18_Msk

#define EXTI_IMR_MR18_Msk (0x1UL << EXTI_IMR_MR18_Pos)

0x00040000

◆ EXTI_IMR_MR18_Pos

#define EXTI_IMR_MR18_Pos (18U)

◆ EXTI_IMR_MR19

#define EXTI_IMR_MR19 EXTI_IMR_MR19_Msk

Interrupt Mask on line 19

◆ EXTI_IMR_MR19_Msk

#define EXTI_IMR_MR19_Msk (0x1UL << EXTI_IMR_MR19_Pos)

0x00080000

◆ EXTI_IMR_MR19_Pos

#define EXTI_IMR_MR19_Pos (19U)

◆ EXTI_IMR_MR1_Msk

#define EXTI_IMR_MR1_Msk (0x1UL << EXTI_IMR_MR1_Pos)

0x00000002

◆ EXTI_IMR_MR1_Pos

#define EXTI_IMR_MR1_Pos (1U)

◆ EXTI_IMR_MR2

#define EXTI_IMR_MR2 EXTI_IMR_MR2_Msk

Interrupt Mask on line 2

◆ EXTI_IMR_MR20

#define EXTI_IMR_MR20 EXTI_IMR_MR20_Msk

Interrupt Mask on line 20

◆ EXTI_IMR_MR20_Msk

#define EXTI_IMR_MR20_Msk (0x1UL << EXTI_IMR_MR20_Pos)

0x00100000

◆ EXTI_IMR_MR20_Pos

#define EXTI_IMR_MR20_Pos (20U)

◆ EXTI_IMR_MR21

#define EXTI_IMR_MR21 EXTI_IMR_MR21_Msk

Interrupt Mask on line 21

◆ EXTI_IMR_MR21_Msk

#define EXTI_IMR_MR21_Msk (0x1UL << EXTI_IMR_MR21_Pos)

0x00200000

◆ EXTI_IMR_MR21_Pos

#define EXTI_IMR_MR21_Pos (21U)

◆ EXTI_IMR_MR22

#define EXTI_IMR_MR22 EXTI_IMR_MR22_Msk

Interrupt Mask on line 22

◆ EXTI_IMR_MR22_Msk

#define EXTI_IMR_MR22_Msk (0x1UL << EXTI_IMR_MR22_Pos)

0x00400000

◆ EXTI_IMR_MR22_Pos

#define EXTI_IMR_MR22_Pos (22U)

◆ EXTI_IMR_MR23

#define EXTI_IMR_MR23 EXTI_IMR_MR23_Msk

Interrupt Mask on line 23

◆ EXTI_IMR_MR23_Msk

#define EXTI_IMR_MR23_Msk (0x1UL << EXTI_IMR_MR23_Pos)

0x00800000

◆ EXTI_IMR_MR23_Pos

#define EXTI_IMR_MR23_Pos (23U)

◆ EXTI_IMR_MR24

#define EXTI_IMR_MR24 EXTI_IMR_MR24_Msk

Interrupt Mask on line 24

◆ EXTI_IMR_MR24_Msk

#define EXTI_IMR_MR24_Msk (0x1UL << EXTI_IMR_MR24_Pos)

0x01000000

◆ EXTI_IMR_MR24_Pos

#define EXTI_IMR_MR24_Pos (24U)

◆ EXTI_IMR_MR25

#define EXTI_IMR_MR25 EXTI_IMR_MR25_Msk

Interrupt Mask on line 25

◆ EXTI_IMR_MR25_Msk

#define EXTI_IMR_MR25_Msk (0x1UL << EXTI_IMR_MR25_Pos)

0x02000000

◆ EXTI_IMR_MR25_Pos

#define EXTI_IMR_MR25_Pos (25U)

◆ EXTI_IMR_MR26

#define EXTI_IMR_MR26 EXTI_IMR_MR26_Msk

Interrupt Mask on line 26

◆ EXTI_IMR_MR26_Msk

#define EXTI_IMR_MR26_Msk (0x1UL << EXTI_IMR_MR26_Pos)

0x04000000

◆ EXTI_IMR_MR26_Pos

#define EXTI_IMR_MR26_Pos (26U)

◆ EXTI_IMR_MR27

#define EXTI_IMR_MR27 EXTI_IMR_MR27_Msk

Interrupt Mask on line 27

◆ EXTI_IMR_MR27_Msk

#define EXTI_IMR_MR27_Msk (0x1UL << EXTI_IMR_MR27_Pos)

0x08000000

◆ EXTI_IMR_MR27_Pos

#define EXTI_IMR_MR27_Pos (27U)

◆ EXTI_IMR_MR28

#define EXTI_IMR_MR28 EXTI_IMR_MR28_Msk

Interrupt Mask on line 28

◆ EXTI_IMR_MR28_Msk

#define EXTI_IMR_MR28_Msk (0x1UL << EXTI_IMR_MR28_Pos)

0x10000000

◆ EXTI_IMR_MR28_Pos

#define EXTI_IMR_MR28_Pos (28U)

◆ EXTI_IMR_MR29

#define EXTI_IMR_MR29 EXTI_IMR_MR29_Msk

Interrupt Mask on line 29

◆ EXTI_IMR_MR29_Msk

#define EXTI_IMR_MR29_Msk (0x1UL << EXTI_IMR_MR29_Pos)

0x20000000

◆ EXTI_IMR_MR29_Pos

#define EXTI_IMR_MR29_Pos (29U)

◆ EXTI_IMR_MR2_Msk

#define EXTI_IMR_MR2_Msk (0x1UL << EXTI_IMR_MR2_Pos)

0x00000004

◆ EXTI_IMR_MR2_Pos

#define EXTI_IMR_MR2_Pos (2U)

◆ EXTI_IMR_MR3

#define EXTI_IMR_MR3 EXTI_IMR_MR3_Msk

Interrupt Mask on line 3

◆ EXTI_IMR_MR30

#define EXTI_IMR_MR30 EXTI_IMR_MR30_Msk

Interrupt Mask on line 30

◆ EXTI_IMR_MR30_Msk

#define EXTI_IMR_MR30_Msk (0x1UL << EXTI_IMR_MR30_Pos)

0x40000000

◆ EXTI_IMR_MR30_Pos

#define EXTI_IMR_MR30_Pos (30U)

◆ EXTI_IMR_MR31

#define EXTI_IMR_MR31 EXTI_IMR_MR31_Msk

Interrupt Mask on line 31

◆ EXTI_IMR_MR31_Msk

#define EXTI_IMR_MR31_Msk (0x1UL << EXTI_IMR_MR31_Pos)

0x80000000

◆ EXTI_IMR_MR31_Pos

#define EXTI_IMR_MR31_Pos (31U)

◆ EXTI_IMR_MR3_Msk

#define EXTI_IMR_MR3_Msk (0x1UL << EXTI_IMR_MR3_Pos)

0x00000008

◆ EXTI_IMR_MR3_Pos

#define EXTI_IMR_MR3_Pos (3U)

◆ EXTI_IMR_MR4

#define EXTI_IMR_MR4 EXTI_IMR_MR4_Msk

Interrupt Mask on line 4

◆ EXTI_IMR_MR4_Msk

#define EXTI_IMR_MR4_Msk (0x1UL << EXTI_IMR_MR4_Pos)

0x00000010

◆ EXTI_IMR_MR4_Pos

#define EXTI_IMR_MR4_Pos (4U)

◆ EXTI_IMR_MR5

#define EXTI_IMR_MR5 EXTI_IMR_MR5_Msk

Interrupt Mask on line 5

◆ EXTI_IMR_MR5_Msk

#define EXTI_IMR_MR5_Msk (0x1UL << EXTI_IMR_MR5_Pos)

0x00000020

◆ EXTI_IMR_MR5_Pos

#define EXTI_IMR_MR5_Pos (5U)

◆ EXTI_IMR_MR6

#define EXTI_IMR_MR6 EXTI_IMR_MR6_Msk

Interrupt Mask on line 6

◆ EXTI_IMR_MR6_Msk

#define EXTI_IMR_MR6_Msk (0x1UL << EXTI_IMR_MR6_Pos)

0x00000040

◆ EXTI_IMR_MR6_Pos

#define EXTI_IMR_MR6_Pos (6U)

◆ EXTI_IMR_MR7

#define EXTI_IMR_MR7 EXTI_IMR_MR7_Msk

Interrupt Mask on line 7

◆ EXTI_IMR_MR7_Msk

#define EXTI_IMR_MR7_Msk (0x1UL << EXTI_IMR_MR7_Pos)

0x00000080

◆ EXTI_IMR_MR7_Pos

#define EXTI_IMR_MR7_Pos (7U)

◆ EXTI_IMR_MR8

#define EXTI_IMR_MR8 EXTI_IMR_MR8_Msk

Interrupt Mask on line 8

◆ EXTI_IMR_MR8_Msk

#define EXTI_IMR_MR8_Msk (0x1UL << EXTI_IMR_MR8_Pos)

0x00000100

◆ EXTI_IMR_MR8_Pos

#define EXTI_IMR_MR8_Pos (8U)

◆ EXTI_IMR_MR9

#define EXTI_IMR_MR9 EXTI_IMR_MR9_Msk

Interrupt Mask on line 9

◆ EXTI_IMR_MR9_Msk

#define EXTI_IMR_MR9_Msk (0x1UL << EXTI_IMR_MR9_Pos)

0x00000200

◆ EXTI_IMR_MR9_Pos

#define EXTI_IMR_MR9_Pos (9U)

◆ EXTI_PR2_PIF32

#define EXTI_PR2_PIF32 EXTI_PR2_PR32

◆ EXTI_PR2_PIF33

#define EXTI_PR2_PIF33 EXTI_PR2_PR33

◆ EXTI_PR2_PR32

#define EXTI_PR2_PR32 EXTI_PR2_PR32_Msk

Pending bit for line 32

◆ EXTI_PR2_PR32_Msk

#define EXTI_PR2_PR32_Msk (0x1UL << EXTI_PR2_PR32_Pos)

0x00000001

◆ EXTI_PR2_PR32_Pos

#define EXTI_PR2_PR32_Pos (0U)

◆ EXTI_PR2_PR33

#define EXTI_PR2_PR33 EXTI_PR2_PR33_Msk

Pending bit for line 33

◆ EXTI_PR2_PR33_Msk

#define EXTI_PR2_PR33_Msk (0x1UL << EXTI_PR2_PR33_Pos)

0x00000002

◆ EXTI_PR2_PR33_Pos

#define EXTI_PR2_PR33_Pos (1U)

◆ EXTI_PR_PIF0

#define EXTI_PR_PIF0 EXTI_PR_PR0

◆ EXTI_PR_PIF1

#define EXTI_PR_PIF1 EXTI_PR_PR1

◆ EXTI_PR_PIF10

#define EXTI_PR_PIF10 EXTI_PR_PR10

◆ EXTI_PR_PIF11

#define EXTI_PR_PIF11 EXTI_PR_PR11

◆ EXTI_PR_PIF12

#define EXTI_PR_PIF12 EXTI_PR_PR12

◆ EXTI_PR_PIF13

#define EXTI_PR_PIF13 EXTI_PR_PR13

◆ EXTI_PR_PIF14

#define EXTI_PR_PIF14 EXTI_PR_PR14

◆ EXTI_PR_PIF15

#define EXTI_PR_PIF15 EXTI_PR_PR15

◆ EXTI_PR_PIF16

#define EXTI_PR_PIF16 EXTI_PR_PR16

◆ EXTI_PR_PIF17

#define EXTI_PR_PIF17 EXTI_PR_PR17

◆ EXTI_PR_PIF18

#define EXTI_PR_PIF18 EXTI_PR_PR18

◆ EXTI_PR_PIF19

#define EXTI_PR_PIF19 EXTI_PR_PR19

◆ EXTI_PR_PIF2

#define EXTI_PR_PIF2 EXTI_PR_PR2

◆ EXTI_PR_PIF20

#define EXTI_PR_PIF20 EXTI_PR_PR20

◆ EXTI_PR_PIF21

#define EXTI_PR_PIF21 EXTI_PR_PR21

◆ EXTI_PR_PIF22

#define EXTI_PR_PIF22 EXTI_PR_PR22

◆ EXTI_PR_PIF29

#define EXTI_PR_PIF29 EXTI_PR_PR29

◆ EXTI_PR_PIF3

#define EXTI_PR_PIF3 EXTI_PR_PR3

◆ EXTI_PR_PIF30

#define EXTI_PR_PIF30 EXTI_PR_PR30

◆ EXTI_PR_PIF31

#define EXTI_PR_PIF31 EXTI_PR_PR31

◆ EXTI_PR_PIF4

#define EXTI_PR_PIF4 EXTI_PR_PR4

◆ EXTI_PR_PIF5

#define EXTI_PR_PIF5 EXTI_PR_PR5

◆ EXTI_PR_PIF6 [1/2]

#define EXTI_PR_PIF6 EXTI_PR_PR6

◆ EXTI_PR_PIF6 [2/2]

#define EXTI_PR_PIF6 EXTI_PR_PR6

◆ EXTI_PR_PIF7

#define EXTI_PR_PIF7 EXTI_PR_PR7

◆ EXTI_PR_PIF8

#define EXTI_PR_PIF8 EXTI_PR_PR8

◆ EXTI_PR_PIF9

#define EXTI_PR_PIF9 EXTI_PR_PR9

◆ EXTI_PR_PR0

#define EXTI_PR_PR0 EXTI_PR_PR0_Msk

Pending bit for line 0

◆ EXTI_PR_PR0_Msk

#define EXTI_PR_PR0_Msk (0x1UL << EXTI_PR_PR0_Pos)

0x00000001

◆ EXTI_PR_PR0_Pos

#define EXTI_PR_PR0_Pos (0U)

◆ EXTI_PR_PR1

#define EXTI_PR_PR1 EXTI_PR_PR1_Msk

Pending bit for line 1

◆ EXTI_PR_PR10

#define EXTI_PR_PR10 EXTI_PR_PR10_Msk

Pending bit for line 10

◆ EXTI_PR_PR10_Msk

#define EXTI_PR_PR10_Msk (0x1UL << EXTI_PR_PR10_Pos)

0x00000400

◆ EXTI_PR_PR10_Pos

#define EXTI_PR_PR10_Pos (10U)

◆ EXTI_PR_PR11

#define EXTI_PR_PR11 EXTI_PR_PR11_Msk

Pending bit for line 11

◆ EXTI_PR_PR11_Msk

#define EXTI_PR_PR11_Msk (0x1UL << EXTI_PR_PR11_Pos)

0x00000800

◆ EXTI_PR_PR11_Pos

#define EXTI_PR_PR11_Pos (11U)

◆ EXTI_PR_PR12

#define EXTI_PR_PR12 EXTI_PR_PR12_Msk

Pending bit for line 12

◆ EXTI_PR_PR12_Msk

#define EXTI_PR_PR12_Msk (0x1UL << EXTI_PR_PR12_Pos)

0x00001000

◆ EXTI_PR_PR12_Pos

#define EXTI_PR_PR12_Pos (12U)

◆ EXTI_PR_PR13

#define EXTI_PR_PR13 EXTI_PR_PR13_Msk

Pending bit for line 13

◆ EXTI_PR_PR13_Msk

#define EXTI_PR_PR13_Msk (0x1UL << EXTI_PR_PR13_Pos)

0x00002000

◆ EXTI_PR_PR13_Pos

#define EXTI_PR_PR13_Pos (13U)

◆ EXTI_PR_PR14

#define EXTI_PR_PR14 EXTI_PR_PR14_Msk

Pending bit for line 14

◆ EXTI_PR_PR14_Msk

#define EXTI_PR_PR14_Msk (0x1UL << EXTI_PR_PR14_Pos)

0x00004000

◆ EXTI_PR_PR14_Pos

#define EXTI_PR_PR14_Pos (14U)

◆ EXTI_PR_PR15

#define EXTI_PR_PR15 EXTI_PR_PR15_Msk

Pending bit for line 15

◆ EXTI_PR_PR15_Msk

#define EXTI_PR_PR15_Msk (0x1UL << EXTI_PR_PR15_Pos)

0x00008000

◆ EXTI_PR_PR15_Pos

#define EXTI_PR_PR15_Pos (15U)

◆ EXTI_PR_PR16

#define EXTI_PR_PR16 EXTI_PR_PR16_Msk

Pending bit for line 16

◆ EXTI_PR_PR16_Msk

#define EXTI_PR_PR16_Msk (0x1UL << EXTI_PR_PR16_Pos)

0x00010000

◆ EXTI_PR_PR16_Pos

#define EXTI_PR_PR16_Pos (16U)

◆ EXTI_PR_PR17

#define EXTI_PR_PR17 EXTI_PR_PR17_Msk

Pending bit for line 17

◆ EXTI_PR_PR17_Msk

#define EXTI_PR_PR17_Msk (0x1UL << EXTI_PR_PR17_Pos)

0x00020000

◆ EXTI_PR_PR17_Pos

#define EXTI_PR_PR17_Pos (17U)

◆ EXTI_PR_PR18

#define EXTI_PR_PR18 EXTI_PR_PR18_Msk

Pending bit for line 18

◆ EXTI_PR_PR18_Msk

#define EXTI_PR_PR18_Msk (0x1UL << EXTI_PR_PR18_Pos)

0x00040000

◆ EXTI_PR_PR18_Pos

#define EXTI_PR_PR18_Pos (18U)

◆ EXTI_PR_PR19

#define EXTI_PR_PR19 EXTI_PR_PR19_Msk

Pending bit for line 19

◆ EXTI_PR_PR19_Msk

#define EXTI_PR_PR19_Msk (0x1UL << EXTI_PR_PR19_Pos)

0x00080000

◆ EXTI_PR_PR19_Pos

#define EXTI_PR_PR19_Pos (19U)

◆ EXTI_PR_PR1_Msk

#define EXTI_PR_PR1_Msk (0x1UL << EXTI_PR_PR1_Pos)

0x00000002

◆ EXTI_PR_PR1_Pos

#define EXTI_PR_PR1_Pos (1U)

◆ EXTI_PR_PR2

#define EXTI_PR_PR2 EXTI_PR_PR2_Msk

Pending bit for line 2

◆ EXTI_PR_PR20

#define EXTI_PR_PR20 EXTI_PR_PR20_Msk

Pending bit for line 20

◆ EXTI_PR_PR20_Msk

#define EXTI_PR_PR20_Msk (0x1UL << EXTI_PR_PR20_Pos)

0x00100000

◆ EXTI_PR_PR20_Pos

#define EXTI_PR_PR20_Pos (20U)

◆ EXTI_PR_PR21

#define EXTI_PR_PR21 EXTI_PR_PR21_Msk

Pending bit for line 21

◆ EXTI_PR_PR21_Msk

#define EXTI_PR_PR21_Msk (0x1UL << EXTI_PR_PR21_Pos)

0x00200000

◆ EXTI_PR_PR21_Pos

#define EXTI_PR_PR21_Pos (21U)

◆ EXTI_PR_PR22

#define EXTI_PR_PR22 EXTI_PR_PR22_Msk

Pending bit for line 22

◆ EXTI_PR_PR22_Msk

#define EXTI_PR_PR22_Msk (0x1UL << EXTI_PR_PR22_Pos)

0x00400000

◆ EXTI_PR_PR22_Pos

#define EXTI_PR_PR22_Pos (22U)

◆ EXTI_PR_PR29

#define EXTI_PR_PR29 EXTI_PR_PR29_Msk

Pending bit for line 29

◆ EXTI_PR_PR29_Msk

#define EXTI_PR_PR29_Msk (0x1UL << EXTI_PR_PR29_Pos)

0x20000000

◆ EXTI_PR_PR29_Pos

#define EXTI_PR_PR29_Pos (29U)

◆ EXTI_PR_PR2_Msk

#define EXTI_PR_PR2_Msk (0x1UL << EXTI_PR_PR2_Pos)

0x00000004

◆ EXTI_PR_PR2_Pos

#define EXTI_PR_PR2_Pos (2U)

◆ EXTI_PR_PR3

#define EXTI_PR_PR3 EXTI_PR_PR3_Msk

Pending bit for line 3

◆ EXTI_PR_PR30

#define EXTI_PR_PR30 EXTI_PR_PR30_Msk

Pending bit for line 30

◆ EXTI_PR_PR30_Msk

#define EXTI_PR_PR30_Msk (0x1UL << EXTI_PR_PR30_Pos)

0x40000000

◆ EXTI_PR_PR30_Pos

#define EXTI_PR_PR30_Pos (30U)

◆ EXTI_PR_PR31

#define EXTI_PR_PR31 EXTI_PR_PR31_Msk

Pending bit for line 31

◆ EXTI_PR_PR31_Msk

#define EXTI_PR_PR31_Msk (0x1UL << EXTI_PR_PR31_Pos)

0x80000000

◆ EXTI_PR_PR31_Pos

#define EXTI_PR_PR31_Pos (31U)

◆ EXTI_PR_PR3_Msk

#define EXTI_PR_PR3_Msk (0x1UL << EXTI_PR_PR3_Pos)

0x00000008

◆ EXTI_PR_PR3_Pos

#define EXTI_PR_PR3_Pos (3U)

◆ EXTI_PR_PR4

#define EXTI_PR_PR4 EXTI_PR_PR4_Msk

Pending bit for line 4

◆ EXTI_PR_PR4_Msk

#define EXTI_PR_PR4_Msk (0x1UL << EXTI_PR_PR4_Pos)

0x00000010

◆ EXTI_PR_PR4_Pos

#define EXTI_PR_PR4_Pos (4U)

◆ EXTI_PR_PR5

#define EXTI_PR_PR5 EXTI_PR_PR5_Msk

Pending bit for line 5

◆ EXTI_PR_PR5_Msk

#define EXTI_PR_PR5_Msk (0x1UL << EXTI_PR_PR5_Pos)

0x00000020

◆ EXTI_PR_PR5_Pos

#define EXTI_PR_PR5_Pos (5U)

◆ EXTI_PR_PR6

#define EXTI_PR_PR6 EXTI_PR_PR6_Msk

Pending bit for line 6

◆ EXTI_PR_PR6_Msk

#define EXTI_PR_PR6_Msk (0x1UL << EXTI_PR_PR6_Pos)

0x00000040

◆ EXTI_PR_PR6_Pos

#define EXTI_PR_PR6_Pos (6U)

◆ EXTI_PR_PR7

#define EXTI_PR_PR7 EXTI_PR_PR7_Msk

Pending bit for line 7

◆ EXTI_PR_PR7_Msk

#define EXTI_PR_PR7_Msk (0x1UL << EXTI_PR_PR7_Pos)

0x00000080

◆ EXTI_PR_PR7_Pos

#define EXTI_PR_PR7_Pos (7U)

◆ EXTI_PR_PR8

#define EXTI_PR_PR8 EXTI_PR_PR8_Msk

Pending bit for line 8

◆ EXTI_PR_PR8_Msk

#define EXTI_PR_PR8_Msk (0x1UL << EXTI_PR_PR8_Pos)

0x00000100

◆ EXTI_PR_PR8_Pos

#define EXTI_PR_PR8_Pos (8U)

◆ EXTI_PR_PR9

#define EXTI_PR_PR9 EXTI_PR_PR9_Msk

Pending bit for line 9

◆ EXTI_PR_PR9_Msk

#define EXTI_PR_PR9_Msk (0x1UL << EXTI_PR_PR9_Pos)

0x00000200

◆ EXTI_PR_PR9_Pos

#define EXTI_PR_PR9_Pos (9U)

◆ EXTI_RTSR2_RT32

#define EXTI_RTSR2_RT32 EXTI_RTSR2_TR32

◆ EXTI_RTSR2_RT33

#define EXTI_RTSR2_RT33 EXTI_RTSR2_TR33

◆ EXTI_RTSR2_TR32

#define EXTI_RTSR2_TR32 EXTI_RTSR2_TR32_Msk

Rising trigger event configuration bit of line 32

◆ EXTI_RTSR2_TR32_Msk

#define EXTI_RTSR2_TR32_Msk (0x1UL << EXTI_RTSR2_TR32_Pos)

0x00000001

◆ EXTI_RTSR2_TR32_Pos

#define EXTI_RTSR2_TR32_Pos (0U)

◆ EXTI_RTSR2_TR33

#define EXTI_RTSR2_TR33 EXTI_RTSR2_TR33_Msk

Rising trigger event configuration bit of line 33

◆ EXTI_RTSR2_TR33_Msk

#define EXTI_RTSR2_TR33_Msk (0x1UL << EXTI_RTSR2_TR33_Pos)

0x00000002

◆ EXTI_RTSR2_TR33_Pos

#define EXTI_RTSR2_TR33_Pos (1U)

◆ EXTI_RTSR_RT0

#define EXTI_RTSR_RT0 EXTI_RTSR_TR0

◆ EXTI_RTSR_RT1

#define EXTI_RTSR_RT1 EXTI_RTSR_TR1

◆ EXTI_RTSR_RT10

#define EXTI_RTSR_RT10 EXTI_RTSR_TR10

◆ EXTI_RTSR_RT11

#define EXTI_RTSR_RT11 EXTI_RTSR_TR11

◆ EXTI_RTSR_RT12

#define EXTI_RTSR_RT12 EXTI_RTSR_TR12

◆ EXTI_RTSR_RT13

#define EXTI_RTSR_RT13 EXTI_RTSR_TR13

◆ EXTI_RTSR_RT14

#define EXTI_RTSR_RT14 EXTI_RTSR_TR14

◆ EXTI_RTSR_RT15

#define EXTI_RTSR_RT15 EXTI_RTSR_TR15

◆ EXTI_RTSR_RT16

#define EXTI_RTSR_RT16 EXTI_RTSR_TR16

◆ EXTI_RTSR_RT17

#define EXTI_RTSR_RT17 EXTI_RTSR_TR17

◆ EXTI_RTSR_RT18

#define EXTI_RTSR_RT18 EXTI_RTSR_TR18

◆ EXTI_RTSR_RT19

#define EXTI_RTSR_RT19 EXTI_RTSR_TR19

◆ EXTI_RTSR_RT2

#define EXTI_RTSR_RT2 EXTI_RTSR_TR2

◆ EXTI_RTSR_RT20

#define EXTI_RTSR_RT20 EXTI_RTSR_TR20

◆ EXTI_RTSR_RT21

#define EXTI_RTSR_RT21 EXTI_RTSR_TR21

◆ EXTI_RTSR_RT22

#define EXTI_RTSR_RT22 EXTI_RTSR_TR22

◆ EXTI_RTSR_RT29

#define EXTI_RTSR_RT29 EXTI_RTSR_TR29

◆ EXTI_RTSR_RT3

#define EXTI_RTSR_RT3 EXTI_RTSR_TR3

◆ EXTI_RTSR_RT30

#define EXTI_RTSR_RT30 EXTI_RTSR_TR30

◆ EXTI_RTSR_RT31

#define EXTI_RTSR_RT31 EXTI_RTSR_TR31

◆ EXTI_RTSR_RT4

#define EXTI_RTSR_RT4 EXTI_RTSR_TR4

◆ EXTI_RTSR_RT5

#define EXTI_RTSR_RT5 EXTI_RTSR_TR5

◆ EXTI_RTSR_RT6

#define EXTI_RTSR_RT6 EXTI_RTSR_TR6

◆ EXTI_RTSR_RT7

#define EXTI_RTSR_RT7 EXTI_RTSR_TR7

◆ EXTI_RTSR_RT8

#define EXTI_RTSR_RT8 EXTI_RTSR_TR8

◆ EXTI_RTSR_RT9

#define EXTI_RTSR_RT9 EXTI_RTSR_TR9

◆ EXTI_RTSR_TR0

#define EXTI_RTSR_TR0 EXTI_RTSR_TR0_Msk

Rising trigger event configuration bit of line 0

◆ EXTI_RTSR_TR0_Msk

#define EXTI_RTSR_TR0_Msk (0x1UL << EXTI_RTSR_TR0_Pos)

0x00000001

◆ EXTI_RTSR_TR0_Pos

#define EXTI_RTSR_TR0_Pos (0U)

◆ EXTI_RTSR_TR1

#define EXTI_RTSR_TR1 EXTI_RTSR_TR1_Msk

Rising trigger event configuration bit of line 1

◆ EXTI_RTSR_TR10

#define EXTI_RTSR_TR10 EXTI_RTSR_TR10_Msk

Rising trigger event configuration bit of line 10

◆ EXTI_RTSR_TR10_Msk

#define EXTI_RTSR_TR10_Msk (0x1UL << EXTI_RTSR_TR10_Pos)

0x00000400

◆ EXTI_RTSR_TR10_Pos

#define EXTI_RTSR_TR10_Pos (10U)

◆ EXTI_RTSR_TR11

#define EXTI_RTSR_TR11 EXTI_RTSR_TR11_Msk

Rising trigger event configuration bit of line 11

◆ EXTI_RTSR_TR11_Msk

#define EXTI_RTSR_TR11_Msk (0x1UL << EXTI_RTSR_TR11_Pos)

0x00000800

◆ EXTI_RTSR_TR11_Pos

#define EXTI_RTSR_TR11_Pos (11U)

◆ EXTI_RTSR_TR12

#define EXTI_RTSR_TR12 EXTI_RTSR_TR12_Msk

Rising trigger event configuration bit of line 12

◆ EXTI_RTSR_TR12_Msk

#define EXTI_RTSR_TR12_Msk (0x1UL << EXTI_RTSR_TR12_Pos)

0x00001000

◆ EXTI_RTSR_TR12_Pos

#define EXTI_RTSR_TR12_Pos (12U)

◆ EXTI_RTSR_TR13

#define EXTI_RTSR_TR13 EXTI_RTSR_TR13_Msk

Rising trigger event configuration bit of line 13

◆ EXTI_RTSR_TR13_Msk

#define EXTI_RTSR_TR13_Msk (0x1UL << EXTI_RTSR_TR13_Pos)

0x00002000

◆ EXTI_RTSR_TR13_Pos

#define EXTI_RTSR_TR13_Pos (13U)

◆ EXTI_RTSR_TR14

#define EXTI_RTSR_TR14 EXTI_RTSR_TR14_Msk

Rising trigger event configuration bit of line 14

◆ EXTI_RTSR_TR14_Msk

#define EXTI_RTSR_TR14_Msk (0x1UL << EXTI_RTSR_TR14_Pos)

0x00004000

◆ EXTI_RTSR_TR14_Pos

#define EXTI_RTSR_TR14_Pos (14U)

◆ EXTI_RTSR_TR15

#define EXTI_RTSR_TR15 EXTI_RTSR_TR15_Msk

Rising trigger event configuration bit of line 15

◆ EXTI_RTSR_TR15_Msk

#define EXTI_RTSR_TR15_Msk (0x1UL << EXTI_RTSR_TR15_Pos)

0x00008000

◆ EXTI_RTSR_TR15_Pos

#define EXTI_RTSR_TR15_Pos (15U)

◆ EXTI_RTSR_TR16

#define EXTI_RTSR_TR16 EXTI_RTSR_TR16_Msk

Rising trigger event configuration bit of line 16

◆ EXTI_RTSR_TR16_Msk

#define EXTI_RTSR_TR16_Msk (0x1UL << EXTI_RTSR_TR16_Pos)

0x00010000

◆ EXTI_RTSR_TR16_Pos

#define EXTI_RTSR_TR16_Pos (16U)

◆ EXTI_RTSR_TR17

#define EXTI_RTSR_TR17 EXTI_RTSR_TR17_Msk

Rising trigger event configuration bit of line 17

◆ EXTI_RTSR_TR17_Msk

#define EXTI_RTSR_TR17_Msk (0x1UL << EXTI_RTSR_TR17_Pos)

0x00020000

◆ EXTI_RTSR_TR17_Pos

#define EXTI_RTSR_TR17_Pos (17U)

◆ EXTI_RTSR_TR18

#define EXTI_RTSR_TR18 EXTI_RTSR_TR18_Msk

Rising trigger event configuration bit of line 18

◆ EXTI_RTSR_TR18_Msk

#define EXTI_RTSR_TR18_Msk (0x1UL << EXTI_RTSR_TR18_Pos)

0x00040000

◆ EXTI_RTSR_TR18_Pos

#define EXTI_RTSR_TR18_Pos (18U)

◆ EXTI_RTSR_TR19

#define EXTI_RTSR_TR19 EXTI_RTSR_TR19_Msk

Rising trigger event configuration bit of line 19

◆ EXTI_RTSR_TR19_Msk

#define EXTI_RTSR_TR19_Msk (0x1UL << EXTI_RTSR_TR19_Pos)

0x00080000

◆ EXTI_RTSR_TR19_Pos

#define EXTI_RTSR_TR19_Pos (19U)

◆ EXTI_RTSR_TR1_Msk

#define EXTI_RTSR_TR1_Msk (0x1UL << EXTI_RTSR_TR1_Pos)

0x00000002

◆ EXTI_RTSR_TR1_Pos

#define EXTI_RTSR_TR1_Pos (1U)

◆ EXTI_RTSR_TR2

#define EXTI_RTSR_TR2 EXTI_RTSR_TR2_Msk

Rising trigger event configuration bit of line 2

◆ EXTI_RTSR_TR20

#define EXTI_RTSR_TR20 EXTI_RTSR_TR20_Msk

Rising trigger event configuration bit of line 20

◆ EXTI_RTSR_TR20_Msk

#define EXTI_RTSR_TR20_Msk (0x1UL << EXTI_RTSR_TR20_Pos)

0x00100000

◆ EXTI_RTSR_TR20_Pos

#define EXTI_RTSR_TR20_Pos (20U)

◆ EXTI_RTSR_TR21

#define EXTI_RTSR_TR21 EXTI_RTSR_TR21_Msk

Rising trigger event configuration bit of line 21

◆ EXTI_RTSR_TR21_Msk

#define EXTI_RTSR_TR21_Msk (0x1UL << EXTI_RTSR_TR21_Pos)

0x00200000

◆ EXTI_RTSR_TR21_Pos

#define EXTI_RTSR_TR21_Pos (21U)

◆ EXTI_RTSR_TR22

#define EXTI_RTSR_TR22 EXTI_RTSR_TR22_Msk

Rising trigger event configuration bit of line 22

◆ EXTI_RTSR_TR22_Msk

#define EXTI_RTSR_TR22_Msk (0x1UL << EXTI_RTSR_TR22_Pos)

0x00400000

◆ EXTI_RTSR_TR22_Pos

#define EXTI_RTSR_TR22_Pos (22U)

◆ EXTI_RTSR_TR29

#define EXTI_RTSR_TR29 EXTI_RTSR_TR29_Msk

Rising trigger event configuration bit of line 29

◆ EXTI_RTSR_TR29_Msk

#define EXTI_RTSR_TR29_Msk (0x1UL << EXTI_RTSR_TR29_Pos)

0x20000000

◆ EXTI_RTSR_TR29_Pos

#define EXTI_RTSR_TR29_Pos (29U)

◆ EXTI_RTSR_TR2_Msk

#define EXTI_RTSR_TR2_Msk (0x1UL << EXTI_RTSR_TR2_Pos)

0x00000004

◆ EXTI_RTSR_TR2_Pos

#define EXTI_RTSR_TR2_Pos (2U)

◆ EXTI_RTSR_TR3

#define EXTI_RTSR_TR3 EXTI_RTSR_TR3_Msk

Rising trigger event configuration bit of line 3

◆ EXTI_RTSR_TR30

#define EXTI_RTSR_TR30 EXTI_RTSR_TR30_Msk

Rising trigger event configuration bit of line 30

◆ EXTI_RTSR_TR30_Msk

#define EXTI_RTSR_TR30_Msk (0x1UL << EXTI_RTSR_TR30_Pos)

0x40000000

◆ EXTI_RTSR_TR30_Pos

#define EXTI_RTSR_TR30_Pos (30U)

◆ EXTI_RTSR_TR31

#define EXTI_RTSR_TR31 EXTI_RTSR_TR31_Msk

Rising trigger event configuration bit of line 31

◆ EXTI_RTSR_TR31_Msk

#define EXTI_RTSR_TR31_Msk (0x1UL << EXTI_RTSR_TR31_Pos)

0x80000000

◆ EXTI_RTSR_TR31_Pos

#define EXTI_RTSR_TR31_Pos (31U)

◆ EXTI_RTSR_TR3_Msk

#define EXTI_RTSR_TR3_Msk (0x1UL << EXTI_RTSR_TR3_Pos)

0x00000008

◆ EXTI_RTSR_TR3_Pos

#define EXTI_RTSR_TR3_Pos (3U)

◆ EXTI_RTSR_TR4

#define EXTI_RTSR_TR4 EXTI_RTSR_TR4_Msk

Rising trigger event configuration bit of line 4

◆ EXTI_RTSR_TR4_Msk

#define EXTI_RTSR_TR4_Msk (0x1UL << EXTI_RTSR_TR4_Pos)

0x00000010

◆ EXTI_RTSR_TR4_Pos

#define EXTI_RTSR_TR4_Pos (4U)

◆ EXTI_RTSR_TR5

#define EXTI_RTSR_TR5 EXTI_RTSR_TR5_Msk

Rising trigger event configuration bit of line 5

◆ EXTI_RTSR_TR5_Msk

#define EXTI_RTSR_TR5_Msk (0x1UL << EXTI_RTSR_TR5_Pos)

0x00000020

◆ EXTI_RTSR_TR5_Pos

#define EXTI_RTSR_TR5_Pos (5U)

◆ EXTI_RTSR_TR6

#define EXTI_RTSR_TR6 EXTI_RTSR_TR6_Msk

Rising trigger event configuration bit of line 6

◆ EXTI_RTSR_TR6_Msk

#define EXTI_RTSR_TR6_Msk (0x1UL << EXTI_RTSR_TR6_Pos)

0x00000040

◆ EXTI_RTSR_TR6_Pos

#define EXTI_RTSR_TR6_Pos (6U)

◆ EXTI_RTSR_TR7

#define EXTI_RTSR_TR7 EXTI_RTSR_TR7_Msk

Rising trigger event configuration bit of line 7

◆ EXTI_RTSR_TR7_Msk

#define EXTI_RTSR_TR7_Msk (0x1UL << EXTI_RTSR_TR7_Pos)

0x00000080

◆ EXTI_RTSR_TR7_Pos

#define EXTI_RTSR_TR7_Pos (7U)

◆ EXTI_RTSR_TR8

#define EXTI_RTSR_TR8 EXTI_RTSR_TR8_Msk

Rising trigger event configuration bit of line 8

◆ EXTI_RTSR_TR8_Msk

#define EXTI_RTSR_TR8_Msk (0x1UL << EXTI_RTSR_TR8_Pos)

0x00000100

◆ EXTI_RTSR_TR8_Pos

#define EXTI_RTSR_TR8_Pos (8U)

◆ EXTI_RTSR_TR9

#define EXTI_RTSR_TR9 EXTI_RTSR_TR9_Msk

Rising trigger event configuration bit of line 9

◆ EXTI_RTSR_TR9_Msk

#define EXTI_RTSR_TR9_Msk (0x1UL << EXTI_RTSR_TR9_Pos)

0x00000200

◆ EXTI_RTSR_TR9_Pos

#define EXTI_RTSR_TR9_Pos (9U)

◆ EXTI_SWIER2_SWI32

#define EXTI_SWIER2_SWI32 EXTI_SWIER2_SWIER32

◆ EXTI_SWIER2_SWI33

#define EXTI_SWIER2_SWI33 EXTI_SWIER2_SWIER33

◆ EXTI_SWIER2_SWIER32

#define EXTI_SWIER2_SWIER32 EXTI_SWIER2_SWIER32_Msk

Software Interrupt on line 32

◆ EXTI_SWIER2_SWIER32_Msk

#define EXTI_SWIER2_SWIER32_Msk (0x1UL << EXTI_SWIER2_SWIER32_Pos)

0x00000001

◆ EXTI_SWIER2_SWIER32_Pos

#define EXTI_SWIER2_SWIER32_Pos (0U)

◆ EXTI_SWIER2_SWIER33

#define EXTI_SWIER2_SWIER33 EXTI_SWIER2_SWIER33_Msk

Software Interrupt on line 33

◆ EXTI_SWIER2_SWIER33_Msk

#define EXTI_SWIER2_SWIER33_Msk (0x1UL << EXTI_SWIER2_SWIER33_Pos)

0x00000002

◆ EXTI_SWIER2_SWIER33_Pos

#define EXTI_SWIER2_SWIER33_Pos (1U)

◆ EXTI_SWIER_SWI0

#define EXTI_SWIER_SWI0 EXTI_SWIER_SWIER0

◆ EXTI_SWIER_SWI1

#define EXTI_SWIER_SWI1 EXTI_SWIER_SWIER1

◆ EXTI_SWIER_SWI10

#define EXTI_SWIER_SWI10 EXTI_SWIER_SWIER10

◆ EXTI_SWIER_SWI11

#define EXTI_SWIER_SWI11 EXTI_SWIER_SWIER11

◆ EXTI_SWIER_SWI12

#define EXTI_SWIER_SWI12 EXTI_SWIER_SWIER12

◆ EXTI_SWIER_SWI13

#define EXTI_SWIER_SWI13 EXTI_SWIER_SWIER13

◆ EXTI_SWIER_SWI14

#define EXTI_SWIER_SWI14 EXTI_SWIER_SWIER14

◆ EXTI_SWIER_SWI15

#define EXTI_SWIER_SWI15 EXTI_SWIER_SWIER15

◆ EXTI_SWIER_SWI16

#define EXTI_SWIER_SWI16 EXTI_SWIER_SWIER16

◆ EXTI_SWIER_SWI17

#define EXTI_SWIER_SWI17 EXTI_SWIER_SWIER17

◆ EXTI_SWIER_SWI18

#define EXTI_SWIER_SWI18 EXTI_SWIER_SWIER18

◆ EXTI_SWIER_SWI19

#define EXTI_SWIER_SWI19 EXTI_SWIER_SWIER19

◆ EXTI_SWIER_SWI2

#define EXTI_SWIER_SWI2 EXTI_SWIER_SWIER2

◆ EXTI_SWIER_SWI20

#define EXTI_SWIER_SWI20 EXTI_SWIER_SWIER20

◆ EXTI_SWIER_SWI21

#define EXTI_SWIER_SWI21 EXTI_SWIER_SWIER21

◆ EXTI_SWIER_SWI22

#define EXTI_SWIER_SWI22 EXTI_SWIER_SWIER22

◆ EXTI_SWIER_SWI29

#define EXTI_SWIER_SWI29 EXTI_SWIER_SWIER29

◆ EXTI_SWIER_SWI3

#define EXTI_SWIER_SWI3 EXTI_SWIER_SWIER3

◆ EXTI_SWIER_SWI30

#define EXTI_SWIER_SWI30 EXTI_SWIER_SWIER30

◆ EXTI_SWIER_SWI31

#define EXTI_SWIER_SWI31 EXTI_SWIER_SWIER31

◆ EXTI_SWIER_SWI4

#define EXTI_SWIER_SWI4 EXTI_SWIER_SWIER4

◆ EXTI_SWIER_SWI5

#define EXTI_SWIER_SWI5 EXTI_SWIER_SWIER5

◆ EXTI_SWIER_SWI6

#define EXTI_SWIER_SWI6 EXTI_SWIER_SWIER6

◆ EXTI_SWIER_SWI7

#define EXTI_SWIER_SWI7 EXTI_SWIER_SWIER7

◆ EXTI_SWIER_SWI8

#define EXTI_SWIER_SWI8 EXTI_SWIER_SWIER8

◆ EXTI_SWIER_SWI9

#define EXTI_SWIER_SWI9 EXTI_SWIER_SWIER9

◆ EXTI_SWIER_SWIER0

#define EXTI_SWIER_SWIER0 EXTI_SWIER_SWIER0_Msk

Software Interrupt on line 0

◆ EXTI_SWIER_SWIER0_Msk

#define EXTI_SWIER_SWIER0_Msk (0x1UL << EXTI_SWIER_SWIER0_Pos)

0x00000001

◆ EXTI_SWIER_SWIER0_Pos

#define EXTI_SWIER_SWIER0_Pos (0U)

◆ EXTI_SWIER_SWIER1

#define EXTI_SWIER_SWIER1 EXTI_SWIER_SWIER1_Msk

Software Interrupt on line 1

◆ EXTI_SWIER_SWIER10

#define EXTI_SWIER_SWIER10 EXTI_SWIER_SWIER10_Msk

Software Interrupt on line 10

◆ EXTI_SWIER_SWIER10_Msk

#define EXTI_SWIER_SWIER10_Msk (0x1UL << EXTI_SWIER_SWIER10_Pos)

0x00000400

◆ EXTI_SWIER_SWIER10_Pos

#define EXTI_SWIER_SWIER10_Pos (10U)

◆ EXTI_SWIER_SWIER11

#define EXTI_SWIER_SWIER11 EXTI_SWIER_SWIER11_Msk

Software Interrupt on line 11

◆ EXTI_SWIER_SWIER11_Msk

#define EXTI_SWIER_SWIER11_Msk (0x1UL << EXTI_SWIER_SWIER11_Pos)

0x00000800

◆ EXTI_SWIER_SWIER11_Pos

#define EXTI_SWIER_SWIER11_Pos (11U)

◆ EXTI_SWIER_SWIER12

#define EXTI_SWIER_SWIER12 EXTI_SWIER_SWIER12_Msk

Software Interrupt on line 12

◆ EXTI_SWIER_SWIER12_Msk

#define EXTI_SWIER_SWIER12_Msk (0x1UL << EXTI_SWIER_SWIER12_Pos)

0x00001000

◆ EXTI_SWIER_SWIER12_Pos

#define EXTI_SWIER_SWIER12_Pos (12U)

◆ EXTI_SWIER_SWIER13

#define EXTI_SWIER_SWIER13 EXTI_SWIER_SWIER13_Msk

Software Interrupt on line 13

◆ EXTI_SWIER_SWIER13_Msk

#define EXTI_SWIER_SWIER13_Msk (0x1UL << EXTI_SWIER_SWIER13_Pos)

0x00002000

◆ EXTI_SWIER_SWIER13_Pos

#define EXTI_SWIER_SWIER13_Pos (13U)

◆ EXTI_SWIER_SWIER14

#define EXTI_SWIER_SWIER14 EXTI_SWIER_SWIER14_Msk

Software Interrupt on line 14

◆ EXTI_SWIER_SWIER14_Msk

#define EXTI_SWIER_SWIER14_Msk (0x1UL << EXTI_SWIER_SWIER14_Pos)

0x00004000

◆ EXTI_SWIER_SWIER14_Pos

#define EXTI_SWIER_SWIER14_Pos (14U)

◆ EXTI_SWIER_SWIER15

#define EXTI_SWIER_SWIER15 EXTI_SWIER_SWIER15_Msk

Software Interrupt on line 15

◆ EXTI_SWIER_SWIER15_Msk

#define EXTI_SWIER_SWIER15_Msk (0x1UL << EXTI_SWIER_SWIER15_Pos)

0x00008000

◆ EXTI_SWIER_SWIER15_Pos

#define EXTI_SWIER_SWIER15_Pos (15U)

◆ EXTI_SWIER_SWIER16

#define EXTI_SWIER_SWIER16 EXTI_SWIER_SWIER16_Msk

Software Interrupt on line 16

◆ EXTI_SWIER_SWIER16_Msk

#define EXTI_SWIER_SWIER16_Msk (0x1UL << EXTI_SWIER_SWIER16_Pos)

0x00010000

◆ EXTI_SWIER_SWIER16_Pos

#define EXTI_SWIER_SWIER16_Pos (16U)

◆ EXTI_SWIER_SWIER17

#define EXTI_SWIER_SWIER17 EXTI_SWIER_SWIER17_Msk

Software Interrupt on line 17

◆ EXTI_SWIER_SWIER17_Msk

#define EXTI_SWIER_SWIER17_Msk (0x1UL << EXTI_SWIER_SWIER17_Pos)

0x00020000

◆ EXTI_SWIER_SWIER17_Pos

#define EXTI_SWIER_SWIER17_Pos (17U)

◆ EXTI_SWIER_SWIER18

#define EXTI_SWIER_SWIER18 EXTI_SWIER_SWIER18_Msk

Software Interrupt on line 18

◆ EXTI_SWIER_SWIER18_Msk

#define EXTI_SWIER_SWIER18_Msk (0x1UL << EXTI_SWIER_SWIER18_Pos)

0x00040000

◆ EXTI_SWIER_SWIER18_Pos

#define EXTI_SWIER_SWIER18_Pos (18U)

◆ EXTI_SWIER_SWIER19

#define EXTI_SWIER_SWIER19 EXTI_SWIER_SWIER19_Msk

Software Interrupt on line 19

◆ EXTI_SWIER_SWIER19_Msk

#define EXTI_SWIER_SWIER19_Msk (0x1UL << EXTI_SWIER_SWIER19_Pos)

0x00080000

◆ EXTI_SWIER_SWIER19_Pos

#define EXTI_SWIER_SWIER19_Pos (19U)

◆ EXTI_SWIER_SWIER1_Msk

#define EXTI_SWIER_SWIER1_Msk (0x1UL << EXTI_SWIER_SWIER1_Pos)

0x00000002

◆ EXTI_SWIER_SWIER1_Pos

#define EXTI_SWIER_SWIER1_Pos (1U)

◆ EXTI_SWIER_SWIER2

#define EXTI_SWIER_SWIER2 EXTI_SWIER_SWIER2_Msk

Software Interrupt on line 2

◆ EXTI_SWIER_SWIER20

#define EXTI_SWIER_SWIER20 EXTI_SWIER_SWIER20_Msk

Software Interrupt on line 20

◆ EXTI_SWIER_SWIER20_Msk

#define EXTI_SWIER_SWIER20_Msk (0x1UL << EXTI_SWIER_SWIER20_Pos)

0x00100000

◆ EXTI_SWIER_SWIER20_Pos

#define EXTI_SWIER_SWIER20_Pos (20U)

◆ EXTI_SWIER_SWIER21

#define EXTI_SWIER_SWIER21 EXTI_SWIER_SWIER21_Msk

Software Interrupt on line 21

◆ EXTI_SWIER_SWIER21_Msk

#define EXTI_SWIER_SWIER21_Msk (0x1UL << EXTI_SWIER_SWIER21_Pos)

0x00200000

◆ EXTI_SWIER_SWIER21_Pos

#define EXTI_SWIER_SWIER21_Pos (21U)

◆ EXTI_SWIER_SWIER22

#define EXTI_SWIER_SWIER22 EXTI_SWIER_SWIER22_Msk

Software Interrupt on line 22

◆ EXTI_SWIER_SWIER22_Msk

#define EXTI_SWIER_SWIER22_Msk (0x1UL << EXTI_SWIER_SWIER22_Pos)

0x00400000

◆ EXTI_SWIER_SWIER22_Pos

#define EXTI_SWIER_SWIER22_Pos (22U)

◆ EXTI_SWIER_SWIER29

#define EXTI_SWIER_SWIER29 EXTI_SWIER_SWIER29_Msk

Software Interrupt on line 29

◆ EXTI_SWIER_SWIER29_Msk

#define EXTI_SWIER_SWIER29_Msk (0x1UL << EXTI_SWIER_SWIER29_Pos)

0x20000000

◆ EXTI_SWIER_SWIER29_Pos

#define EXTI_SWIER_SWIER29_Pos (29U)

◆ EXTI_SWIER_SWIER2_Msk

#define EXTI_SWIER_SWIER2_Msk (0x1UL << EXTI_SWIER_SWIER2_Pos)

0x00000004

◆ EXTI_SWIER_SWIER2_Pos

#define EXTI_SWIER_SWIER2_Pos (2U)

◆ EXTI_SWIER_SWIER3

#define EXTI_SWIER_SWIER3 EXTI_SWIER_SWIER3_Msk

Software Interrupt on line 3

◆ EXTI_SWIER_SWIER30

#define EXTI_SWIER_SWIER30 EXTI_SWIER_SWIER30_Msk

Software Interrupt on line 30

◆ EXTI_SWIER_SWIER30_Msk

#define EXTI_SWIER_SWIER30_Msk (0x1UL << EXTI_SWIER_SWIER30_Pos)

0x40000000

◆ EXTI_SWIER_SWIER30_Pos

#define EXTI_SWIER_SWIER30_Pos (30U)

◆ EXTI_SWIER_SWIER31

#define EXTI_SWIER_SWIER31 EXTI_SWIER_SWIER31_Msk

Software Interrupt on line 31

◆ EXTI_SWIER_SWIER31_Msk

#define EXTI_SWIER_SWIER31_Msk (0x1UL << EXTI_SWIER_SWIER31_Pos)

0x80000000

◆ EXTI_SWIER_SWIER31_Pos

#define EXTI_SWIER_SWIER31_Pos (31U)

◆ EXTI_SWIER_SWIER3_Msk

#define EXTI_SWIER_SWIER3_Msk (0x1UL << EXTI_SWIER_SWIER3_Pos)

0x00000008

◆ EXTI_SWIER_SWIER3_Pos

#define EXTI_SWIER_SWIER3_Pos (3U)

◆ EXTI_SWIER_SWIER4

#define EXTI_SWIER_SWIER4 EXTI_SWIER_SWIER4_Msk

Software Interrupt on line 4

◆ EXTI_SWIER_SWIER4_Msk

#define EXTI_SWIER_SWIER4_Msk (0x1UL << EXTI_SWIER_SWIER4_Pos)

0x00000010

◆ EXTI_SWIER_SWIER4_Pos

#define EXTI_SWIER_SWIER4_Pos (4U)

◆ EXTI_SWIER_SWIER5

#define EXTI_SWIER_SWIER5 EXTI_SWIER_SWIER5_Msk

Software Interrupt on line 5

◆ EXTI_SWIER_SWIER5_Msk

#define EXTI_SWIER_SWIER5_Msk (0x1UL << EXTI_SWIER_SWIER5_Pos)

0x00000020

◆ EXTI_SWIER_SWIER5_Pos

#define EXTI_SWIER_SWIER5_Pos (5U)

◆ EXTI_SWIER_SWIER6

#define EXTI_SWIER_SWIER6 EXTI_SWIER_SWIER6_Msk

Software Interrupt on line 6

◆ EXTI_SWIER_SWIER6_Msk

#define EXTI_SWIER_SWIER6_Msk (0x1UL << EXTI_SWIER_SWIER6_Pos)

0x00000040

◆ EXTI_SWIER_SWIER6_Pos

#define EXTI_SWIER_SWIER6_Pos (6U)

◆ EXTI_SWIER_SWIER7

#define EXTI_SWIER_SWIER7 EXTI_SWIER_SWIER7_Msk

Software Interrupt on line 7

◆ EXTI_SWIER_SWIER7_Msk

#define EXTI_SWIER_SWIER7_Msk (0x1UL << EXTI_SWIER_SWIER7_Pos)

0x00000080

◆ EXTI_SWIER_SWIER7_Pos

#define EXTI_SWIER_SWIER7_Pos (7U)

◆ EXTI_SWIER_SWIER8

#define EXTI_SWIER_SWIER8 EXTI_SWIER_SWIER8_Msk

Software Interrupt on line 8

◆ EXTI_SWIER_SWIER8_Msk

#define EXTI_SWIER_SWIER8_Msk (0x1UL << EXTI_SWIER_SWIER8_Pos)

0x00000100

◆ EXTI_SWIER_SWIER8_Pos

#define EXTI_SWIER_SWIER8_Pos (8U)

◆ EXTI_SWIER_SWIER9

#define EXTI_SWIER_SWIER9 EXTI_SWIER_SWIER9_Msk

Software Interrupt on line 9

◆ EXTI_SWIER_SWIER9_Msk

#define EXTI_SWIER_SWIER9_Msk (0x1UL << EXTI_SWIER_SWIER9_Pos)

0x00000200

◆ EXTI_SWIER_SWIER9_Pos

#define EXTI_SWIER_SWIER9_Pos (9U)

◆ FLASH_ACR_HLFCYA

#define FLASH_ACR_HLFCYA FLASH_ACR_HLFCYA_Msk

Flash Half Cycle Access Enable

◆ FLASH_ACR_HLFCYA_Msk

#define FLASH_ACR_HLFCYA_Msk (0x1UL << FLASH_ACR_HLFCYA_Pos)

0x00000008

◆ FLASH_ACR_HLFCYA_Pos

#define FLASH_ACR_HLFCYA_Pos (3U)

◆ FLASH_ACR_LATENCY

#define FLASH_ACR_LATENCY FLASH_ACR_LATENCY_Msk

LATENCY[2:0] bits (Latency)

◆ FLASH_ACR_LATENCY_0

#define FLASH_ACR_LATENCY_0 (0x1UL << FLASH_ACR_LATENCY_Pos)

0x00000001

◆ FLASH_ACR_LATENCY_1

#define FLASH_ACR_LATENCY_1 (0x2UL << FLASH_ACR_LATENCY_Pos)

0x00000002

◆ FLASH_ACR_LATENCY_2

#define FLASH_ACR_LATENCY_2 (0x4UL << FLASH_ACR_LATENCY_Pos)

0x00000004

◆ FLASH_ACR_LATENCY_Msk

#define FLASH_ACR_LATENCY_Msk (0x7UL << FLASH_ACR_LATENCY_Pos)

0x00000007

◆ FLASH_ACR_LATENCY_Pos

#define FLASH_ACR_LATENCY_Pos (0U)

◆ FLASH_ACR_PRFTBE

#define FLASH_ACR_PRFTBE FLASH_ACR_PRFTBE_Msk

Prefetch Buffer Enable

◆ FLASH_ACR_PRFTBE_Msk

#define FLASH_ACR_PRFTBE_Msk (0x1UL << FLASH_ACR_PRFTBE_Pos)

0x00000010

◆ FLASH_ACR_PRFTBE_Pos

#define FLASH_ACR_PRFTBE_Pos (4U)

◆ FLASH_ACR_PRFTBS

#define FLASH_ACR_PRFTBS FLASH_ACR_PRFTBS_Msk

Prefetch Buffer Status

◆ FLASH_ACR_PRFTBS_Msk

#define FLASH_ACR_PRFTBS_Msk (0x1UL << FLASH_ACR_PRFTBS_Pos)

0x00000020

◆ FLASH_ACR_PRFTBS_Pos

#define FLASH_ACR_PRFTBS_Pos (5U)

◆ FLASH_AR_FAR

#define FLASH_AR_FAR FLASH_AR_FAR_Msk

Flash Address

◆ FLASH_AR_FAR_Msk

#define FLASH_AR_FAR_Msk (0xFFFFFFFFUL << FLASH_AR_FAR_Pos)

0xFFFFFFFF

◆ FLASH_AR_FAR_Pos

#define FLASH_AR_FAR_Pos (0U)

◆ FLASH_CR_EOPIE

#define FLASH_CR_EOPIE FLASH_CR_EOPIE_Msk

End of operation interrupt enable

◆ FLASH_CR_EOPIE_Msk

#define FLASH_CR_EOPIE_Msk (0x1UL << FLASH_CR_EOPIE_Pos)

0x00001000

◆ FLASH_CR_EOPIE_Pos

#define FLASH_CR_EOPIE_Pos (12U)

◆ FLASH_CR_ERRIE

#define FLASH_CR_ERRIE FLASH_CR_ERRIE_Msk

Error Interrupt Enable

◆ FLASH_CR_ERRIE_Msk

#define FLASH_CR_ERRIE_Msk (0x1UL << FLASH_CR_ERRIE_Pos)

0x00000400

◆ FLASH_CR_ERRIE_Pos

#define FLASH_CR_ERRIE_Pos (10U)

◆ FLASH_CR_LOCK

#define FLASH_CR_LOCK FLASH_CR_LOCK_Msk

Lock

◆ FLASH_CR_LOCK_Msk

#define FLASH_CR_LOCK_Msk (0x1UL << FLASH_CR_LOCK_Pos)

0x00000080

◆ FLASH_CR_LOCK_Pos

#define FLASH_CR_LOCK_Pos (7U)

◆ FLASH_CR_MER

#define FLASH_CR_MER FLASH_CR_MER_Msk

Mass Erase

◆ FLASH_CR_MER_Msk

#define FLASH_CR_MER_Msk (0x1UL << FLASH_CR_MER_Pos)

0x00000004

◆ FLASH_CR_MER_Pos

#define FLASH_CR_MER_Pos (2U)

◆ FLASH_CR_OBL_LAUNCH

#define FLASH_CR_OBL_LAUNCH FLASH_CR_OBL_LAUNCH_Msk

OptionBytes Loader Launch

◆ FLASH_CR_OBL_LAUNCH_Msk

#define FLASH_CR_OBL_LAUNCH_Msk (0x1UL << FLASH_CR_OBL_LAUNCH_Pos)

0x00002000

◆ FLASH_CR_OBL_LAUNCH_Pos

#define FLASH_CR_OBL_LAUNCH_Pos (13U)

◆ FLASH_CR_OPTER

#define FLASH_CR_OPTER FLASH_CR_OPTER_Msk

Option Byte Erase

◆ FLASH_CR_OPTER_Msk

#define FLASH_CR_OPTER_Msk (0x1UL << FLASH_CR_OPTER_Pos)

0x00000020

◆ FLASH_CR_OPTER_Pos

#define FLASH_CR_OPTER_Pos (5U)

◆ FLASH_CR_OPTPG

#define FLASH_CR_OPTPG FLASH_CR_OPTPG_Msk

Option Byte Programming

◆ FLASH_CR_OPTPG_Msk

#define FLASH_CR_OPTPG_Msk (0x1UL << FLASH_CR_OPTPG_Pos)

0x00000010

◆ FLASH_CR_OPTPG_Pos

#define FLASH_CR_OPTPG_Pos (4U)

◆ FLASH_CR_OPTWRE

#define FLASH_CR_OPTWRE FLASH_CR_OPTWRE_Msk

Option Bytes Write Enable

◆ FLASH_CR_OPTWRE_Msk

#define FLASH_CR_OPTWRE_Msk (0x1UL << FLASH_CR_OPTWRE_Pos)

0x00000200

◆ FLASH_CR_OPTWRE_Pos

#define FLASH_CR_OPTWRE_Pos (9U)

◆ FLASH_CR_PER

#define FLASH_CR_PER FLASH_CR_PER_Msk

Page Erase

◆ FLASH_CR_PER_Msk

#define FLASH_CR_PER_Msk (0x1UL << FLASH_CR_PER_Pos)

0x00000002

◆ FLASH_CR_PER_Pos

#define FLASH_CR_PER_Pos (1U)

◆ FLASH_CR_PG

#define FLASH_CR_PG FLASH_CR_PG_Msk

Programming

◆ FLASH_CR_PG_Msk

#define FLASH_CR_PG_Msk (0x1UL << FLASH_CR_PG_Pos)

0x00000001

◆ FLASH_CR_PG_Pos

#define FLASH_CR_PG_Pos (0U)

◆ FLASH_CR_STRT

#define FLASH_CR_STRT FLASH_CR_STRT_Msk

Start

◆ FLASH_CR_STRT_Msk

#define FLASH_CR_STRT_Msk (0x1UL << FLASH_CR_STRT_Pos)

0x00000040

◆ FLASH_CR_STRT_Pos

#define FLASH_CR_STRT_Pos (6U)

◆ FLASH_KEY1

#define FLASH_KEY1 FLASH_KEY1_Msk

FPEC Key1

◆ FLASH_KEY1_Msk

#define FLASH_KEY1_Msk (0x45670123UL << FLASH_KEY1_Pos)

0x45670123

◆ FLASH_KEY1_Pos

#define FLASH_KEY1_Pos (0U)

◆ FLASH_KEY2

#define FLASH_KEY2 FLASH_KEY2_Msk

FPEC Key2

◆ FLASH_KEY2_Msk

#define FLASH_KEY2_Msk (0xCDEF89ABUL << FLASH_KEY2_Pos)

0xCDEF89AB

◆ FLASH_KEY2_Pos

#define FLASH_KEY2_Pos (0U)

◆ FLASH_KEYR_FKEYR

#define FLASH_KEYR_FKEYR FLASH_KEYR_FKEYR_Msk

FPEC Key

◆ FLASH_KEYR_FKEYR_Msk

#define FLASH_KEYR_FKEYR_Msk (0xFFFFFFFFUL << FLASH_KEYR_FKEYR_Pos)

0xFFFFFFFF

◆ FLASH_KEYR_FKEYR_Pos

#define FLASH_KEYR_FKEYR_Pos (0U)

◆ FLASH_OBR_DATA0

#define FLASH_OBR_DATA0 FLASH_OBR_DATA0_Msk

Data0

◆ FLASH_OBR_DATA0_Msk

#define FLASH_OBR_DATA0_Msk (0xFFUL << FLASH_OBR_DATA0_Pos)

0x00FF0000

◆ FLASH_OBR_DATA0_Pos

#define FLASH_OBR_DATA0_Pos (16U)

◆ FLASH_OBR_DATA1

#define FLASH_OBR_DATA1 FLASH_OBR_DATA1_Msk

Data1

◆ FLASH_OBR_DATA1_Msk

#define FLASH_OBR_DATA1_Msk (0xFFUL << FLASH_OBR_DATA1_Pos)

0xFF000000

◆ FLASH_OBR_DATA1_Pos

#define FLASH_OBR_DATA1_Pos (24U)

◆ FLASH_OBR_IWDG_SW

#define FLASH_OBR_IWDG_SW FLASH_OBR_IWDG_SW_Msk

IWDG SW

◆ FLASH_OBR_IWDG_SW_Msk

#define FLASH_OBR_IWDG_SW_Msk (0x1UL << FLASH_OBR_IWDG_SW_Pos)

0x00000100

◆ FLASH_OBR_IWDG_SW_Pos

#define FLASH_OBR_IWDG_SW_Pos (8U)

◆ FLASH_OBR_nBOOT1

#define FLASH_OBR_nBOOT1 FLASH_OBR_nBOOT1_Msk

nBOOT1

◆ FLASH_OBR_nBOOT1_Msk

#define FLASH_OBR_nBOOT1_Msk (0x1UL << FLASH_OBR_nBOOT1_Pos)

0x00001000

◆ FLASH_OBR_nBOOT1_Pos

#define FLASH_OBR_nBOOT1_Pos (12U)

◆ FLASH_OBR_nRST_STDBY

#define FLASH_OBR_nRST_STDBY FLASH_OBR_nRST_STDBY_Msk

nRST_STDBY

◆ FLASH_OBR_nRST_STDBY_Msk

#define FLASH_OBR_nRST_STDBY_Msk (0x1UL << FLASH_OBR_nRST_STDBY_Pos)

0x00000400

◆ FLASH_OBR_nRST_STDBY_Pos

#define FLASH_OBR_nRST_STDBY_Pos (10U)

◆ FLASH_OBR_nRST_STOP

#define FLASH_OBR_nRST_STOP FLASH_OBR_nRST_STOP_Msk

nRST_STOP

◆ FLASH_OBR_nRST_STOP_Msk

#define FLASH_OBR_nRST_STOP_Msk (0x1UL << FLASH_OBR_nRST_STOP_Pos)

0x00000200

◆ FLASH_OBR_nRST_STOP_Pos

#define FLASH_OBR_nRST_STOP_Pos (9U)

◆ FLASH_OBR_OPTERR

#define FLASH_OBR_OPTERR FLASH_OBR_OPTERR_Msk

Option Byte Error

◆ FLASH_OBR_OPTERR_Msk

#define FLASH_OBR_OPTERR_Msk (0x1UL << FLASH_OBR_OPTERR_Pos)

0x00000001

◆ FLASH_OBR_OPTERR_Pos

#define FLASH_OBR_OPTERR_Pos (0U)

◆ FLASH_OBR_RDPRT

#define FLASH_OBR_RDPRT FLASH_OBR_RDPRT_Msk

Read protection

◆ FLASH_OBR_RDPRT_1

#define FLASH_OBR_RDPRT_1 (0x1UL << FLASH_OBR_RDPRT_Pos)

0x00000002

◆ FLASH_OBR_RDPRT_2

#define FLASH_OBR_RDPRT_2 (0x3UL << FLASH_OBR_RDPRT_Pos)

0x00000006

◆ FLASH_OBR_RDPRT_Msk

#define FLASH_OBR_RDPRT_Msk (0x3UL << FLASH_OBR_RDPRT_Pos)

0x00000006

◆ FLASH_OBR_RDPRT_Pos

#define FLASH_OBR_RDPRT_Pos (1U)

◆ FLASH_OBR_SRAM_PE

#define FLASH_OBR_SRAM_PE FLASH_OBR_SRAM_PE_Msk

SRAM_PE

◆ FLASH_OBR_SRAM_PE_Msk

#define FLASH_OBR_SRAM_PE_Msk (0x1UL << FLASH_OBR_SRAM_PE_Pos)

0x00004000

◆ FLASH_OBR_SRAM_PE_Pos

#define FLASH_OBR_SRAM_PE_Pos (14U)

◆ FLASH_OBR_USER

#define FLASH_OBR_USER FLASH_OBR_USER_Msk

User Option Bytes

◆ FLASH_OBR_USER_Msk

#define FLASH_OBR_USER_Msk (0x77UL << FLASH_OBR_USER_Pos)

0x00007700

◆ FLASH_OBR_USER_Pos

#define FLASH_OBR_USER_Pos (8U)

◆ FLASH_OBR_VDDA_MONITOR

#define FLASH_OBR_VDDA_MONITOR FLASH_OBR_VDDA_MONITOR_Msk

VDDA_MONITOR

◆ FLASH_OBR_VDDA_MONITOR_Msk

#define FLASH_OBR_VDDA_MONITOR_Msk (0x1UL << FLASH_OBR_VDDA_MONITOR_Pos)

0x00002000

◆ FLASH_OBR_VDDA_MONITOR_Pos

#define FLASH_OBR_VDDA_MONITOR_Pos (13U)

◆ FLASH_OBR_WDG_SW

#define FLASH_OBR_WDG_SW FLASH_OBR_IWDG_SW

◆ FLASH_OPTKEY1

#define FLASH_OPTKEY1 FLASH_KEY1

Option Byte Key1

◆ FLASH_OPTKEY2

#define FLASH_OPTKEY2 FLASH_KEY2

Option Byte Key2

◆ FLASH_OPTKEYR_OPTKEYR

#define FLASH_OPTKEYR_OPTKEYR FLASH_OPTKEYR_OPTKEYR_Msk

Option Byte Key

◆ FLASH_OPTKEYR_OPTKEYR_Msk

#define FLASH_OPTKEYR_OPTKEYR_Msk (0xFFFFFFFFUL << FLASH_OPTKEYR_OPTKEYR_Pos)

0xFFFFFFFF

◆ FLASH_OPTKEYR_OPTKEYR_Pos

#define FLASH_OPTKEYR_OPTKEYR_Pos (0U)

◆ FLASH_SR_BSY

#define FLASH_SR_BSY FLASH_SR_BSY_Msk

Busy

◆ FLASH_SR_BSY_Msk

#define FLASH_SR_BSY_Msk (0x1UL << FLASH_SR_BSY_Pos)

0x00000001

◆ FLASH_SR_BSY_Pos

#define FLASH_SR_BSY_Pos (0U)

◆ FLASH_SR_EOP

#define FLASH_SR_EOP FLASH_SR_EOP_Msk

End of operation

◆ FLASH_SR_EOP_Msk

#define FLASH_SR_EOP_Msk (0x1UL << FLASH_SR_EOP_Pos)

0x00000020

◆ FLASH_SR_EOP_Pos

#define FLASH_SR_EOP_Pos (5U)

◆ FLASH_SR_PGERR

#define FLASH_SR_PGERR FLASH_SR_PGERR_Msk

Programming Error

◆ FLASH_SR_PGERR_Msk

#define FLASH_SR_PGERR_Msk (0x1UL << FLASH_SR_PGERR_Pos)

0x00000004

◆ FLASH_SR_PGERR_Pos

#define FLASH_SR_PGERR_Pos (2U)

◆ FLASH_SR_WRPERR

#define FLASH_SR_WRPERR FLASH_SR_WRPERR_Msk

Write Protection Error

◆ FLASH_SR_WRPERR_Msk

#define FLASH_SR_WRPERR_Msk (0x1UL << FLASH_SR_WRPERR_Pos)

0x00000010

◆ FLASH_SR_WRPERR_Pos

#define FLASH_SR_WRPERR_Pos (4U)

◆ FLASH_WRPR_WRP

#define FLASH_WRPR_WRP FLASH_WRPR_WRP_Msk

Write Protect

◆ FLASH_WRPR_WRP_Msk

#define FLASH_WRPR_WRP_Msk (0xFFFFFFFFUL << FLASH_WRPR_WRP_Pos)

0xFFFFFFFF

◆ FLASH_WRPR_WRP_Pos

#define FLASH_WRPR_WRP_Pos (0U)

◆ FMC_BCR1_ASYNCWAIT

#define FMC_BCR1_ASYNCWAIT FMC_BCR1_ASYNCWAIT_Msk

Asynchronous wait

◆ FMC_BCR1_ASYNCWAIT_Msk

#define FMC_BCR1_ASYNCWAIT_Msk (0x1UL << FMC_BCR1_ASYNCWAIT_Pos)

0x00008000

◆ FMC_BCR1_ASYNCWAIT_Pos

#define FMC_BCR1_ASYNCWAIT_Pos (15U)

◆ FMC_BCR1_BURSTEN

#define FMC_BCR1_BURSTEN FMC_BCR1_BURSTEN_Msk

Burst enable bit

◆ FMC_BCR1_BURSTEN_Msk

#define FMC_BCR1_BURSTEN_Msk (0x1UL << FMC_BCR1_BURSTEN_Pos)

0x00000100

◆ FMC_BCR1_BURSTEN_Pos

#define FMC_BCR1_BURSTEN_Pos (8U)

◆ FMC_BCR1_CBURSTRW

#define FMC_BCR1_CBURSTRW FMC_BCR1_CBURSTRW_Msk

Write burst enable

◆ FMC_BCR1_CBURSTRW_Msk

#define FMC_BCR1_CBURSTRW_Msk (0x1UL << FMC_BCR1_CBURSTRW_Pos)

0x00080000

◆ FMC_BCR1_CBURSTRW_Pos

#define FMC_BCR1_CBURSTRW_Pos (19U)

◆ FMC_BCR1_CCLKEN

#define FMC_BCR1_CCLKEN FMC_BCR1_CCLKEN_Msk

Continuous clock enable

◆ FMC_BCR1_CCLKEN_Msk

#define FMC_BCR1_CCLKEN_Msk (0x1UL << FMC_BCR1_CCLKEN_Pos)

0x00100000

◆ FMC_BCR1_CCLKEN_Pos

#define FMC_BCR1_CCLKEN_Pos (20U)

◆ FMC_BCR1_EXTMOD

#define FMC_BCR1_EXTMOD FMC_BCR1_EXTMOD_Msk

Extended mode enable

◆ FMC_BCR1_EXTMOD_Msk

#define FMC_BCR1_EXTMOD_Msk (0x1UL << FMC_BCR1_EXTMOD_Pos)

0x00004000

◆ FMC_BCR1_EXTMOD_Pos

#define FMC_BCR1_EXTMOD_Pos (14U)

◆ FMC_BCR1_FACCEN

#define FMC_BCR1_FACCEN FMC_BCR1_FACCEN_Msk

Flash access enable

◆ FMC_BCR1_FACCEN_Msk

#define FMC_BCR1_FACCEN_Msk (0x1UL << FMC_BCR1_FACCEN_Pos)

0x00000040

◆ FMC_BCR1_FACCEN_Pos

#define FMC_BCR1_FACCEN_Pos (6U)

◆ FMC_BCR1_MBKEN

#define FMC_BCR1_MBKEN FMC_BCR1_MBKEN_Msk

Memory bank enable bit

◆ FMC_BCR1_MBKEN_Msk

#define FMC_BCR1_MBKEN_Msk (0x1UL << FMC_BCR1_MBKEN_Pos)

0x00000001

◆ FMC_BCR1_MBKEN_Pos

#define FMC_BCR1_MBKEN_Pos (0U)

◆ FMC_BCR1_MTYP

#define FMC_BCR1_MTYP FMC_BCR1_MTYP_Msk

MTYP[1:0] bits (Memory type)

◆ FMC_BCR1_MTYP_0

#define FMC_BCR1_MTYP_0 (0x1UL << FMC_BCR1_MTYP_Pos)

0x00000004

◆ FMC_BCR1_MTYP_1

#define FMC_BCR1_MTYP_1 (0x2UL << FMC_BCR1_MTYP_Pos)

0x00000008

◆ FMC_BCR1_MTYP_Msk

#define FMC_BCR1_MTYP_Msk (0x3UL << FMC_BCR1_MTYP_Pos)

0x0000000C

◆ FMC_BCR1_MTYP_Pos

#define FMC_BCR1_MTYP_Pos (2U)

◆ FMC_BCR1_MUXEN

#define FMC_BCR1_MUXEN FMC_BCR1_MUXEN_Msk

Address/data multiplexing enable bit

◆ FMC_BCR1_MUXEN_Msk

#define FMC_BCR1_MUXEN_Msk (0x1UL << FMC_BCR1_MUXEN_Pos)

0x00000002

◆ FMC_BCR1_MUXEN_Pos

#define FMC_BCR1_MUXEN_Pos (1U)

◆ FMC_BCR1_MWID

#define FMC_BCR1_MWID FMC_BCR1_MWID_Msk

MWID[1:0] bits (Memory data bus width)

◆ FMC_BCR1_MWID_0

#define FMC_BCR1_MWID_0 (0x1UL << FMC_BCR1_MWID_Pos)

0x00000010

◆ FMC_BCR1_MWID_1

#define FMC_BCR1_MWID_1 (0x2UL << FMC_BCR1_MWID_Pos)

0x00000020

◆ FMC_BCR1_MWID_Msk

#define FMC_BCR1_MWID_Msk (0x3UL << FMC_BCR1_MWID_Pos)

0x00000030

◆ FMC_BCR1_MWID_Pos

#define FMC_BCR1_MWID_Pos (4U)

◆ FMC_BCR1_WAITCFG

#define FMC_BCR1_WAITCFG FMC_BCR1_WAITCFG_Msk

Wait timing configuration

◆ FMC_BCR1_WAITCFG_Msk

#define FMC_BCR1_WAITCFG_Msk (0x1UL << FMC_BCR1_WAITCFG_Pos)

0x00000800

◆ FMC_BCR1_WAITCFG_Pos

#define FMC_BCR1_WAITCFG_Pos (11U)

◆ FMC_BCR1_WAITEN

#define FMC_BCR1_WAITEN FMC_BCR1_WAITEN_Msk

Wait enable bit

◆ FMC_BCR1_WAITEN_Msk

#define FMC_BCR1_WAITEN_Msk (0x1UL << FMC_BCR1_WAITEN_Pos)

0x00002000

◆ FMC_BCR1_WAITEN_Pos

#define FMC_BCR1_WAITEN_Pos (13U)

◆ FMC_BCR1_WAITPOL

#define FMC_BCR1_WAITPOL FMC_BCR1_WAITPOL_Msk

Wait signal polarity bit

◆ FMC_BCR1_WAITPOL_Msk

#define FMC_BCR1_WAITPOL_Msk (0x1UL << FMC_BCR1_WAITPOL_Pos)

0x00000200

◆ FMC_BCR1_WAITPOL_Pos

#define FMC_BCR1_WAITPOL_Pos (9U)

◆ FMC_BCR1_WRAPMOD

#define FMC_BCR1_WRAPMOD FMC_BCR1_WRAPMOD_Msk

Wrapped burst mode support

◆ FMC_BCR1_WRAPMOD_Msk

#define FMC_BCR1_WRAPMOD_Msk (0x1UL << FMC_BCR1_WRAPMOD_Pos)

0x00000400

◆ FMC_BCR1_WRAPMOD_Pos

#define FMC_BCR1_WRAPMOD_Pos (10U)

◆ FMC_BCR1_WREN

#define FMC_BCR1_WREN FMC_BCR1_WREN_Msk

Write enable bit

◆ FMC_BCR1_WREN_Msk

#define FMC_BCR1_WREN_Msk (0x1UL << FMC_BCR1_WREN_Pos)

0x00001000

◆ FMC_BCR1_WREN_Pos

#define FMC_BCR1_WREN_Pos (12U)

◆ FMC_BCR2_ASYNCWAIT

#define FMC_BCR2_ASYNCWAIT FMC_BCR2_ASYNCWAIT_Msk

Asynchronous wait

◆ FMC_BCR2_ASYNCWAIT_Msk

#define FMC_BCR2_ASYNCWAIT_Msk (0x1UL << FMC_BCR2_ASYNCWAIT_Pos)

0x00008000

◆ FMC_BCR2_ASYNCWAIT_Pos

#define FMC_BCR2_ASYNCWAIT_Pos (15U)

◆ FMC_BCR2_BURSTEN

#define FMC_BCR2_BURSTEN FMC_BCR2_BURSTEN_Msk

Burst enable bit

◆ FMC_BCR2_BURSTEN_Msk

#define FMC_BCR2_BURSTEN_Msk (0x1UL << FMC_BCR2_BURSTEN_Pos)

0x00000100

◆ FMC_BCR2_BURSTEN_Pos

#define FMC_BCR2_BURSTEN_Pos (8U)

◆ FMC_BCR2_CBURSTRW

#define FMC_BCR2_CBURSTRW FMC_BCR2_CBURSTRW_Msk

Write burst enable

◆ FMC_BCR2_CBURSTRW_Msk

#define FMC_BCR2_CBURSTRW_Msk (0x1UL << FMC_BCR2_CBURSTRW_Pos)

0x00080000

◆ FMC_BCR2_CBURSTRW_Pos

#define FMC_BCR2_CBURSTRW_Pos (19U)

◆ FMC_BCR2_EXTMOD

#define FMC_BCR2_EXTMOD FMC_BCR2_EXTMOD_Msk

Extended mode enable

◆ FMC_BCR2_EXTMOD_Msk

#define FMC_BCR2_EXTMOD_Msk (0x1UL << FMC_BCR2_EXTMOD_Pos)

0x00004000

◆ FMC_BCR2_EXTMOD_Pos

#define FMC_BCR2_EXTMOD_Pos (14U)

◆ FMC_BCR2_FACCEN

#define FMC_BCR2_FACCEN FMC_BCR2_FACCEN_Msk

Flash access enable

◆ FMC_BCR2_FACCEN_Msk

#define FMC_BCR2_FACCEN_Msk (0x1UL << FMC_BCR2_FACCEN_Pos)

0x00000040

◆ FMC_BCR2_FACCEN_Pos

#define FMC_BCR2_FACCEN_Pos (6U)

◆ FMC_BCR2_MBKEN

#define FMC_BCR2_MBKEN FMC_BCR2_MBKEN_Msk

Memory bank enable bit

◆ FMC_BCR2_MBKEN_Msk

#define FMC_BCR2_MBKEN_Msk (0x1UL << FMC_BCR2_MBKEN_Pos)

0x00000001

◆ FMC_BCR2_MBKEN_Pos

#define FMC_BCR2_MBKEN_Pos (0U)

◆ FMC_BCR2_MTYP

#define FMC_BCR2_MTYP FMC_BCR2_MTYP_Msk

MTYP[1:0] bits (Memory type)

◆ FMC_BCR2_MTYP_0

#define FMC_BCR2_MTYP_0 (0x1UL << FMC_BCR2_MTYP_Pos)

0x00000004

◆ FMC_BCR2_MTYP_1

#define FMC_BCR2_MTYP_1 (0x2UL << FMC_BCR2_MTYP_Pos)

0x00000008

◆ FMC_BCR2_MTYP_Msk

#define FMC_BCR2_MTYP_Msk (0x3UL << FMC_BCR2_MTYP_Pos)

0x0000000C

◆ FMC_BCR2_MTYP_Pos

#define FMC_BCR2_MTYP_Pos (2U)

◆ FMC_BCR2_MUXEN

#define FMC_BCR2_MUXEN FMC_BCR2_MUXEN_Msk

Address/data multiplexing enable bit

◆ FMC_BCR2_MUXEN_Msk

#define FMC_BCR2_MUXEN_Msk (0x1UL << FMC_BCR2_MUXEN_Pos)

0x00000002

◆ FMC_BCR2_MUXEN_Pos

#define FMC_BCR2_MUXEN_Pos (1U)

◆ FMC_BCR2_MWID

#define FMC_BCR2_MWID FMC_BCR2_MWID_Msk

MWID[1:0] bits (Memory data bus width)

◆ FMC_BCR2_MWID_0

#define FMC_BCR2_MWID_0 (0x1UL << FMC_BCR2_MWID_Pos)

0x00000010

◆ FMC_BCR2_MWID_1

#define FMC_BCR2_MWID_1 (0x2UL << FMC_BCR2_MWID_Pos)

0x00000020

◆ FMC_BCR2_MWID_Msk

#define FMC_BCR2_MWID_Msk (0x3UL << FMC_BCR2_MWID_Pos)

0x00000030

◆ FMC_BCR2_MWID_Pos

#define FMC_BCR2_MWID_Pos (4U)

◆ FMC_BCR2_WAITCFG

#define FMC_BCR2_WAITCFG FMC_BCR2_WAITCFG_Msk

Wait timing configuration

◆ FMC_BCR2_WAITCFG_Msk

#define FMC_BCR2_WAITCFG_Msk (0x1UL << FMC_BCR2_WAITCFG_Pos)

0x00000800

◆ FMC_BCR2_WAITCFG_Pos

#define FMC_BCR2_WAITCFG_Pos (11U)

◆ FMC_BCR2_WAITEN

#define FMC_BCR2_WAITEN FMC_BCR2_WAITEN_Msk

Wait enable bit

◆ FMC_BCR2_WAITEN_Msk

#define FMC_BCR2_WAITEN_Msk (0x1UL << FMC_BCR2_WAITEN_Pos)

0x00002000

◆ FMC_BCR2_WAITEN_Pos

#define FMC_BCR2_WAITEN_Pos (13U)

◆ FMC_BCR2_WAITPOL

#define FMC_BCR2_WAITPOL FMC_BCR2_WAITPOL_Msk

Wait signal polarity bit

◆ FMC_BCR2_WAITPOL_Msk

#define FMC_BCR2_WAITPOL_Msk (0x1UL << FMC_BCR2_WAITPOL_Pos)

0x00000200

◆ FMC_BCR2_WAITPOL_Pos

#define FMC_BCR2_WAITPOL_Pos (9U)

◆ FMC_BCR2_WRAPMOD

#define FMC_BCR2_WRAPMOD FMC_BCR2_WRAPMOD_Msk

Wrapped burst mode support

◆ FMC_BCR2_WRAPMOD_Msk

#define FMC_BCR2_WRAPMOD_Msk (0x1UL << FMC_BCR2_WRAPMOD_Pos)

0x00000400

◆ FMC_BCR2_WRAPMOD_Pos

#define FMC_BCR2_WRAPMOD_Pos (10U)

◆ FMC_BCR2_WREN

#define FMC_BCR2_WREN FMC_BCR2_WREN_Msk

Write enable bit

◆ FMC_BCR2_WREN_Msk

#define FMC_BCR2_WREN_Msk (0x1UL << FMC_BCR2_WREN_Pos)

0x00001000

◆ FMC_BCR2_WREN_Pos

#define FMC_BCR2_WREN_Pos (12U)

◆ FMC_BCR3_ASYNCWAIT

#define FMC_BCR3_ASYNCWAIT FMC_BCR3_ASYNCWAIT_Msk

Asynchronous wait

◆ FMC_BCR3_ASYNCWAIT_Msk

#define FMC_BCR3_ASYNCWAIT_Msk (0x1UL << FMC_BCR3_ASYNCWAIT_Pos)

0x00008000

◆ FMC_BCR3_ASYNCWAIT_Pos

#define FMC_BCR3_ASYNCWAIT_Pos (15U)

◆ FMC_BCR3_BURSTEN

#define FMC_BCR3_BURSTEN FMC_BCR3_BURSTEN_Msk

Burst enable bit

◆ FMC_BCR3_BURSTEN_Msk

#define FMC_BCR3_BURSTEN_Msk (0x1UL << FMC_BCR3_BURSTEN_Pos)

0x00000100

◆ FMC_BCR3_BURSTEN_Pos

#define FMC_BCR3_BURSTEN_Pos (8U)

◆ FMC_BCR3_CBURSTRW

#define FMC_BCR3_CBURSTRW FMC_BCR3_CBURSTRW_Msk

Write burst enable

◆ FMC_BCR3_CBURSTRW_Msk

#define FMC_BCR3_CBURSTRW_Msk (0x1UL << FMC_BCR3_CBURSTRW_Pos)

0x00080000

◆ FMC_BCR3_CBURSTRW_Pos

#define FMC_BCR3_CBURSTRW_Pos (19U)

◆ FMC_BCR3_EXTMOD

#define FMC_BCR3_EXTMOD FMC_BCR3_EXTMOD_Msk

Extended mode enable

◆ FMC_BCR3_EXTMOD_Msk

#define FMC_BCR3_EXTMOD_Msk (0x1UL << FMC_BCR3_EXTMOD_Pos)

0x00004000

◆ FMC_BCR3_EXTMOD_Pos

#define FMC_BCR3_EXTMOD_Pos (14U)

◆ FMC_BCR3_FACCEN

#define FMC_BCR3_FACCEN FMC_BCR3_FACCEN_Msk

Flash access enable

◆ FMC_BCR3_FACCEN_Msk

#define FMC_BCR3_FACCEN_Msk (0x1UL << FMC_BCR3_FACCEN_Pos)

0x00000040

◆ FMC_BCR3_FACCEN_Pos

#define FMC_BCR3_FACCEN_Pos (6U)

◆ FMC_BCR3_MBKEN

#define FMC_BCR3_MBKEN FMC_BCR3_MBKEN_Msk

Memory bank enable bit

◆ FMC_BCR3_MBKEN_Msk

#define FMC_BCR3_MBKEN_Msk (0x1UL << FMC_BCR3_MBKEN_Pos)

0x00000001

◆ FMC_BCR3_MBKEN_Pos

#define FMC_BCR3_MBKEN_Pos (0U)

◆ FMC_BCR3_MTYP

#define FMC_BCR3_MTYP FMC_BCR3_MTYP_Msk

MTYP[1:0] bits (Memory type)

◆ FMC_BCR3_MTYP_0

#define FMC_BCR3_MTYP_0 (0x1UL << FMC_BCR3_MTYP_Pos)

0x00000004

◆ FMC_BCR3_MTYP_1

#define FMC_BCR3_MTYP_1 (0x2UL << FMC_BCR3_MTYP_Pos)

0x00000008

◆ FMC_BCR3_MTYP_Msk

#define FMC_BCR3_MTYP_Msk (0x3UL << FMC_BCR3_MTYP_Pos)

0x0000000C

◆ FMC_BCR3_MTYP_Pos

#define FMC_BCR3_MTYP_Pos (2U)

◆ FMC_BCR3_MUXEN

#define FMC_BCR3_MUXEN FMC_BCR3_MUXEN_Msk

Address/data multiplexing enable bit

◆ FMC_BCR3_MUXEN_Msk

#define FMC_BCR3_MUXEN_Msk (0x1UL << FMC_BCR3_MUXEN_Pos)

0x00000002

◆ FMC_BCR3_MUXEN_Pos

#define FMC_BCR3_MUXEN_Pos (1U)

◆ FMC_BCR3_MWID

#define FMC_BCR3_MWID FMC_BCR3_MWID_Msk

MWID[1:0] bits (Memory data bus width)

◆ FMC_BCR3_MWID_0

#define FMC_BCR3_MWID_0 (0x1UL << FMC_BCR3_MWID_Pos)

0x00000010

◆ FMC_BCR3_MWID_1

#define FMC_BCR3_MWID_1 (0x2UL << FMC_BCR3_MWID_Pos)

0x00000020

◆ FMC_BCR3_MWID_Msk

#define FMC_BCR3_MWID_Msk (0x3UL << FMC_BCR3_MWID_Pos)

0x00000030

◆ FMC_BCR3_MWID_Pos

#define FMC_BCR3_MWID_Pos (4U)

◆ FMC_BCR3_WAITCFG

#define FMC_BCR3_WAITCFG FMC_BCR3_WAITCFG_Msk

Wait timing configuration

◆ FMC_BCR3_WAITCFG_Msk

#define FMC_BCR3_WAITCFG_Msk (0x1UL << FMC_BCR3_WAITCFG_Pos)

0x00000800

◆ FMC_BCR3_WAITCFG_Pos

#define FMC_BCR3_WAITCFG_Pos (11U)

◆ FMC_BCR3_WAITEN

#define FMC_BCR3_WAITEN FMC_BCR3_WAITEN_Msk

Wait enable bit

◆ FMC_BCR3_WAITEN_Msk

#define FMC_BCR3_WAITEN_Msk (0x1UL << FMC_BCR3_WAITEN_Pos)

0x00002000

◆ FMC_BCR3_WAITEN_Pos

#define FMC_BCR3_WAITEN_Pos (13U)

◆ FMC_BCR3_WAITPOL

#define FMC_BCR3_WAITPOL FMC_BCR3_WAITPOL_Msk

Wait signal polarity bit

◆ FMC_BCR3_WAITPOL_Msk

#define FMC_BCR3_WAITPOL_Msk (0x1UL << FMC_BCR3_WAITPOL_Pos)

0x00000200

◆ FMC_BCR3_WAITPOL_Pos

#define FMC_BCR3_WAITPOL_Pos (9U)

◆ FMC_BCR3_WRAPMOD

#define FMC_BCR3_WRAPMOD FMC_BCR3_WRAPMOD_Msk

Wrapped burst mode support

◆ FMC_BCR3_WRAPMOD_Msk

#define FMC_BCR3_WRAPMOD_Msk (0x1UL << FMC_BCR3_WRAPMOD_Pos)

0x00000400

◆ FMC_BCR3_WRAPMOD_Pos

#define FMC_BCR3_WRAPMOD_Pos (10U)

◆ FMC_BCR3_WREN

#define FMC_BCR3_WREN FMC_BCR3_WREN_Msk

Write enable bit

◆ FMC_BCR3_WREN_Msk

#define FMC_BCR3_WREN_Msk (0x1UL << FMC_BCR3_WREN_Pos)

0x00001000

◆ FMC_BCR3_WREN_Pos

#define FMC_BCR3_WREN_Pos (12U)

◆ FMC_BCR4_ASYNCWAIT

#define FMC_BCR4_ASYNCWAIT FMC_BCR4_ASYNCWAIT_Msk

Asynchronous wait

◆ FMC_BCR4_ASYNCWAIT_Msk

#define FMC_BCR4_ASYNCWAIT_Msk (0x1UL << FMC_BCR4_ASYNCWAIT_Pos)

0x00008000

◆ FMC_BCR4_ASYNCWAIT_Pos

#define FMC_BCR4_ASYNCWAIT_Pos (15U)

◆ FMC_BCR4_BURSTEN

#define FMC_BCR4_BURSTEN FMC_BCR4_BURSTEN_Msk

Burst enable bit

◆ FMC_BCR4_BURSTEN_Msk

#define FMC_BCR4_BURSTEN_Msk (0x1UL << FMC_BCR4_BURSTEN_Pos)

0x00000100

◆ FMC_BCR4_BURSTEN_Pos

#define FMC_BCR4_BURSTEN_Pos (8U)

◆ FMC_BCR4_CBURSTRW

#define FMC_BCR4_CBURSTRW FMC_BCR4_CBURSTRW_Msk

Write burst enable

◆ FMC_BCR4_CBURSTRW_Msk

#define FMC_BCR4_CBURSTRW_Msk (0x1UL << FMC_BCR4_CBURSTRW_Pos)

0x00080000

◆ FMC_BCR4_CBURSTRW_Pos

#define FMC_BCR4_CBURSTRW_Pos (19U)

◆ FMC_BCR4_EXTMOD

#define FMC_BCR4_EXTMOD FMC_BCR4_EXTMOD_Msk

Extended mode enable

◆ FMC_BCR4_EXTMOD_Msk

#define FMC_BCR4_EXTMOD_Msk (0x1UL << FMC_BCR4_EXTMOD_Pos)

0x00004000

◆ FMC_BCR4_EXTMOD_Pos

#define FMC_BCR4_EXTMOD_Pos (14U)

◆ FMC_BCR4_FACCEN

#define FMC_BCR4_FACCEN FMC_BCR4_FACCEN_Msk

Flash access enable

◆ FMC_BCR4_FACCEN_Msk

#define FMC_BCR4_FACCEN_Msk (0x1UL << FMC_BCR4_FACCEN_Pos)

0x00000040

◆ FMC_BCR4_FACCEN_Pos

#define FMC_BCR4_FACCEN_Pos (6U)

◆ FMC_BCR4_MBKEN

#define FMC_BCR4_MBKEN FMC_BCR4_MBKEN_Msk

Memory bank enable bit

◆ FMC_BCR4_MBKEN_Msk

#define FMC_BCR4_MBKEN_Msk (0x1UL << FMC_BCR4_MBKEN_Pos)

0x00000001

◆ FMC_BCR4_MBKEN_Pos

#define FMC_BCR4_MBKEN_Pos (0U)

◆ FMC_BCR4_MTYP

#define FMC_BCR4_MTYP FMC_BCR4_MTYP_Msk

MTYP[1:0] bits (Memory type)

◆ FMC_BCR4_MTYP_0

#define FMC_BCR4_MTYP_0 (0x1UL << FMC_BCR4_MTYP_Pos)

0x00000004

◆ FMC_BCR4_MTYP_1

#define FMC_BCR4_MTYP_1 (0x2UL << FMC_BCR4_MTYP_Pos)

0x00000008

◆ FMC_BCR4_MTYP_Msk

#define FMC_BCR4_MTYP_Msk (0x3UL << FMC_BCR4_MTYP_Pos)

0x0000000C

◆ FMC_BCR4_MTYP_Pos

#define FMC_BCR4_MTYP_Pos (2U)

◆ FMC_BCR4_MUXEN

#define FMC_BCR4_MUXEN FMC_BCR4_MUXEN_Msk

Address/data multiplexing enable bit

◆ FMC_BCR4_MUXEN_Msk

#define FMC_BCR4_MUXEN_Msk (0x1UL << FMC_BCR4_MUXEN_Pos)

0x00000002

◆ FMC_BCR4_MUXEN_Pos

#define FMC_BCR4_MUXEN_Pos (1U)

◆ FMC_BCR4_MWID

#define FMC_BCR4_MWID FMC_BCR4_MWID_Msk

MWID[1:0] bits (Memory data bus width)

◆ FMC_BCR4_MWID_0

#define FMC_BCR4_MWID_0 (0x1UL << FMC_BCR4_MWID_Pos)

0x00000010

◆ FMC_BCR4_MWID_1

#define FMC_BCR4_MWID_1 (0x2UL << FMC_BCR4_MWID_Pos)

0x00000020

◆ FMC_BCR4_MWID_Msk

#define FMC_BCR4_MWID_Msk (0x3UL << FMC_BCR4_MWID_Pos)

0x00000030

◆ FMC_BCR4_MWID_Pos

#define FMC_BCR4_MWID_Pos (4U)

◆ FMC_BCR4_WAITCFG

#define FMC_BCR4_WAITCFG FMC_BCR4_WAITCFG_Msk

Wait timing configuration

◆ FMC_BCR4_WAITCFG_Msk

#define FMC_BCR4_WAITCFG_Msk (0x1UL << FMC_BCR4_WAITCFG_Pos)

0x00000800

◆ FMC_BCR4_WAITCFG_Pos

#define FMC_BCR4_WAITCFG_Pos (11U)

◆ FMC_BCR4_WAITEN

#define FMC_BCR4_WAITEN FMC_BCR4_WAITEN_Msk

Wait enable bit

◆ FMC_BCR4_WAITEN_Msk

#define FMC_BCR4_WAITEN_Msk (0x1UL << FMC_BCR4_WAITEN_Pos)

0x00002000

◆ FMC_BCR4_WAITEN_Pos

#define FMC_BCR4_WAITEN_Pos (13U)

◆ FMC_BCR4_WAITPOL

#define FMC_BCR4_WAITPOL FMC_BCR4_WAITPOL_Msk

Wait signal polarity bit

◆ FMC_BCR4_WAITPOL_Msk

#define FMC_BCR4_WAITPOL_Msk (0x1UL << FMC_BCR4_WAITPOL_Pos)

0x00000200

◆ FMC_BCR4_WAITPOL_Pos

#define FMC_BCR4_WAITPOL_Pos (9U)

◆ FMC_BCR4_WRAPMOD

#define FMC_BCR4_WRAPMOD FMC_BCR4_WRAPMOD_Msk

Wrapped burst mode support

◆ FMC_BCR4_WRAPMOD_Msk

#define FMC_BCR4_WRAPMOD_Msk (0x1UL << FMC_BCR4_WRAPMOD_Pos)

0x00000400

◆ FMC_BCR4_WRAPMOD_Pos

#define FMC_BCR4_WRAPMOD_Pos (10U)

◆ FMC_BCR4_WREN

#define FMC_BCR4_WREN FMC_BCR4_WREN_Msk

Write enable bit

◆ FMC_BCR4_WREN_Msk

#define FMC_BCR4_WREN_Msk (0x1UL << FMC_BCR4_WREN_Pos)

0x00001000

◆ FMC_BCR4_WREN_Pos

#define FMC_BCR4_WREN_Pos (12U)

◆ FMC_BCRx_ASYNCWAIT

#define FMC_BCRx_ASYNCWAIT FMC_BCRx_ASYNCWAIT_Msk

Asynchronous wait

◆ FMC_BCRx_ASYNCWAIT_Msk

#define FMC_BCRx_ASYNCWAIT_Msk (0x1UL << FMC_BCRx_ASYNCWAIT_Pos)

0x00008000

◆ FMC_BCRx_ASYNCWAIT_Pos

#define FMC_BCRx_ASYNCWAIT_Pos (15U)

◆ FMC_BCRx_BURSTEN

#define FMC_BCRx_BURSTEN FMC_BCRx_BURSTEN_Msk

Burst enable bit

◆ FMC_BCRx_BURSTEN_Msk

#define FMC_BCRx_BURSTEN_Msk (0x1UL << FMC_BCRx_BURSTEN_Pos)

0x00000100

◆ FMC_BCRx_BURSTEN_Pos

#define FMC_BCRx_BURSTEN_Pos (8U)

◆ FMC_BCRx_CBURSTRW

#define FMC_BCRx_CBURSTRW FMC_BCRx_CBURSTRW_Msk

Write burst enable

◆ FMC_BCRx_CBURSTRW_Msk

#define FMC_BCRx_CBURSTRW_Msk (0x1UL << FMC_BCRx_CBURSTRW_Pos)

0x00080000

◆ FMC_BCRx_CBURSTRW_Pos

#define FMC_BCRx_CBURSTRW_Pos (19U)

◆ FMC_BCRx_EXTMOD

#define FMC_BCRx_EXTMOD FMC_BCRx_EXTMOD_Msk

Extended mode enable

◆ FMC_BCRx_EXTMOD_Msk

#define FMC_BCRx_EXTMOD_Msk (0x1UL << FMC_BCRx_EXTMOD_Pos)

0x00004000

◆ FMC_BCRx_EXTMOD_Pos

#define FMC_BCRx_EXTMOD_Pos (14U)

◆ FMC_BCRx_FACCEN

#define FMC_BCRx_FACCEN FMC_BCRx_FACCEN_Msk

Flash access enable

◆ FMC_BCRx_FACCEN_Msk

#define FMC_BCRx_FACCEN_Msk (0x1UL << FMC_BCRx_FACCEN_Pos)

0x00000040

◆ FMC_BCRx_FACCEN_Pos

#define FMC_BCRx_FACCEN_Pos (6U)

◆ FMC_BCRx_MBKEN

#define FMC_BCRx_MBKEN FMC_BCRx_MBKEN_Msk

Memory bank enable bit

◆ FMC_BCRx_MBKEN_Msk

#define FMC_BCRx_MBKEN_Msk (0x1UL << FMC_BCRx_MBKEN_Pos)

0x00000001

◆ FMC_BCRx_MBKEN_Pos

#define FMC_BCRx_MBKEN_Pos (0U)

◆ FMC_BCRx_MTYP

#define FMC_BCRx_MTYP FMC_BCRx_MTYP_Msk

MTYP[1:0] bits (Memory type)

◆ FMC_BCRx_MTYP_0

#define FMC_BCRx_MTYP_0 (0x1UL << FMC_BCRx_MTYP_Pos)

0x00000004

◆ FMC_BCRx_MTYP_1

#define FMC_BCRx_MTYP_1 (0x2UL << FMC_BCRx_MTYP_Pos)

0x00000008

◆ FMC_BCRx_MTYP_Msk

#define FMC_BCRx_MTYP_Msk (0x3UL << FMC_BCRx_MTYP_Pos)

0x0000000C

◆ FMC_BCRx_MTYP_Pos

#define FMC_BCRx_MTYP_Pos (2U)

◆ FMC_BCRx_MUXEN

#define FMC_BCRx_MUXEN FMC_BCRx_MUXEN_Msk

Address/data multiplexing enable bit

◆ FMC_BCRx_MUXEN_Msk

#define FMC_BCRx_MUXEN_Msk (0x1UL << FMC_BCRx_MUXEN_Pos)

0x00000002

◆ FMC_BCRx_MUXEN_Pos

#define FMC_BCRx_MUXEN_Pos (1U)

◆ FMC_BCRx_MWID

#define FMC_BCRx_MWID FMC_BCRx_MWID_Msk

MWID[1:0] bits (Memory data bus width)

◆ FMC_BCRx_MWID_0

#define FMC_BCRx_MWID_0 (0x1UL << FMC_BCRx_MWID_Pos)

0x00000010

◆ FMC_BCRx_MWID_1

#define FMC_BCRx_MWID_1 (0x2UL << FMC_BCRx_MWID_Pos)

0x00000020

◆ FMC_BCRx_MWID_Msk

#define FMC_BCRx_MWID_Msk (0x3UL << FMC_BCRx_MWID_Pos)

0x00000030

◆ FMC_BCRx_MWID_Pos

#define FMC_BCRx_MWID_Pos (4U)

◆ FMC_BCRx_WAITCFG

#define FMC_BCRx_WAITCFG FMC_BCRx_WAITCFG_Msk

Wait timing configuration

◆ FMC_BCRx_WAITCFG_Msk

#define FMC_BCRx_WAITCFG_Msk (0x1UL << FMC_BCRx_WAITCFG_Pos)

0x00000800

◆ FMC_BCRx_WAITCFG_Pos

#define FMC_BCRx_WAITCFG_Pos (11U)

◆ FMC_BCRx_WAITEN

#define FMC_BCRx_WAITEN FMC_BCRx_WAITEN_Msk

Wait enable bit

◆ FMC_BCRx_WAITEN_Msk

#define FMC_BCRx_WAITEN_Msk (0x1UL << FMC_BCRx_WAITEN_Pos)

0x00002000

◆ FMC_BCRx_WAITEN_Pos

#define FMC_BCRx_WAITEN_Pos (13U)

◆ FMC_BCRx_WAITPOL

#define FMC_BCRx_WAITPOL FMC_BCRx_WAITPOL_Msk

Wait signal polarity bit

◆ FMC_BCRx_WAITPOL_Msk

#define FMC_BCRx_WAITPOL_Msk (0x1UL << FMC_BCRx_WAITPOL_Pos)

0x00000200

◆ FMC_BCRx_WAITPOL_Pos

#define FMC_BCRx_WAITPOL_Pos (9U)

◆ FMC_BCRx_WRAPMOD

#define FMC_BCRx_WRAPMOD FMC_BCRx_WRAPMOD_Msk

Wrapped burst mode support

◆ FMC_BCRx_WRAPMOD_Msk

#define FMC_BCRx_WRAPMOD_Msk (0x1UL << FMC_BCRx_WRAPMOD_Pos)

0x00000400

◆ FMC_BCRx_WRAPMOD_Pos

#define FMC_BCRx_WRAPMOD_Pos (10U)

◆ FMC_BCRx_WREN

#define FMC_BCRx_WREN FMC_BCRx_WREN_Msk

Write enable bit

◆ FMC_BCRx_WREN_Msk

#define FMC_BCRx_WREN_Msk (0x1UL << FMC_BCRx_WREN_Pos)

0x00001000

◆ FMC_BCRx_WREN_Pos

#define FMC_BCRx_WREN_Pos (12U)

◆ FMC_BTR1_ACCMOD

#define FMC_BTR1_ACCMOD FMC_BTR1_ACCMOD_Msk

ACCMOD[1:0] bits (Access mode)

◆ FMC_BTR1_ACCMOD_0

#define FMC_BTR1_ACCMOD_0 (0x1UL << FMC_BTR1_ACCMOD_Pos)

0x10000000

◆ FMC_BTR1_ACCMOD_1

#define FMC_BTR1_ACCMOD_1 (0x2UL << FMC_BTR1_ACCMOD_Pos)

0x20000000

◆ FMC_BTR1_ACCMOD_Msk

#define FMC_BTR1_ACCMOD_Msk (0x3UL << FMC_BTR1_ACCMOD_Pos)

0x30000000

◆ FMC_BTR1_ACCMOD_Pos

#define FMC_BTR1_ACCMOD_Pos (28U)

◆ FMC_BTR1_ADDHLD

#define FMC_BTR1_ADDHLD FMC_BTR1_ADDHLD_Msk

ADDHLD[3:0] bits (Address-hold phase duration)

◆ FMC_BTR1_ADDHLD_0

#define FMC_BTR1_ADDHLD_0 (0x1UL << FMC_BTR1_ADDHLD_Pos)

0x00000010

◆ FMC_BTR1_ADDHLD_1

#define FMC_BTR1_ADDHLD_1 (0x2UL << FMC_BTR1_ADDHLD_Pos)

0x00000020

◆ FMC_BTR1_ADDHLD_2

#define FMC_BTR1_ADDHLD_2 (0x4UL << FMC_BTR1_ADDHLD_Pos)

0x00000040

◆ FMC_BTR1_ADDHLD_3

#define FMC_BTR1_ADDHLD_3 (0x8UL << FMC_BTR1_ADDHLD_Pos)

0x00000080

◆ FMC_BTR1_ADDHLD_Msk

#define FMC_BTR1_ADDHLD_Msk (0xFUL << FMC_BTR1_ADDHLD_Pos)

0x000000F0

◆ FMC_BTR1_ADDHLD_Pos

#define FMC_BTR1_ADDHLD_Pos (4U)

◆ FMC_BTR1_ADDSET

#define FMC_BTR1_ADDSET FMC_BTR1_ADDSET_Msk

ADDSET[3:0] bits (Address setup phase duration)

◆ FMC_BTR1_ADDSET_0

#define FMC_BTR1_ADDSET_0 (0x1UL << FMC_BTR1_ADDSET_Pos)

0x00000001

◆ FMC_BTR1_ADDSET_1

#define FMC_BTR1_ADDSET_1 (0x2UL << FMC_BTR1_ADDSET_Pos)

0x00000002

◆ FMC_BTR1_ADDSET_2

#define FMC_BTR1_ADDSET_2 (0x4UL << FMC_BTR1_ADDSET_Pos)

0x00000004

◆ FMC_BTR1_ADDSET_3

#define FMC_BTR1_ADDSET_3 (0x8UL << FMC_BTR1_ADDSET_Pos)

0x00000008

◆ FMC_BTR1_ADDSET_Msk

#define FMC_BTR1_ADDSET_Msk (0xFUL << FMC_BTR1_ADDSET_Pos)

0x0000000F

◆ FMC_BTR1_ADDSET_Pos

#define FMC_BTR1_ADDSET_Pos (0U)

◆ FMC_BTR1_BUSTURN

#define FMC_BTR1_BUSTURN FMC_BTR1_BUSTURN_Msk

BUSTURN[3:0] bits (Bus turnaround phase duration)

◆ FMC_BTR1_BUSTURN_0

#define FMC_BTR1_BUSTURN_0 (0x1UL << FMC_BTR1_BUSTURN_Pos)

0x00010000

◆ FMC_BTR1_BUSTURN_1

#define FMC_BTR1_BUSTURN_1 (0x2UL << FMC_BTR1_BUSTURN_Pos)

0x00020000

◆ FMC_BTR1_BUSTURN_2

#define FMC_BTR1_BUSTURN_2 (0x4UL << FMC_BTR1_BUSTURN_Pos)

0x00040000

◆ FMC_BTR1_BUSTURN_3

#define FMC_BTR1_BUSTURN_3 (0x8UL << FMC_BTR1_BUSTURN_Pos)

0x00080000

◆ FMC_BTR1_BUSTURN_Msk

#define FMC_BTR1_BUSTURN_Msk (0xFUL << FMC_BTR1_BUSTURN_Pos)

0x000F0000

◆ FMC_BTR1_BUSTURN_Pos

#define FMC_BTR1_BUSTURN_Pos (16U)

◆ FMC_BTR1_CLKDIV

#define FMC_BTR1_CLKDIV FMC_BTR1_CLKDIV_Msk

CLKDIV[3:0] bits (Clock divide ratio)

◆ FMC_BTR1_CLKDIV_0

#define FMC_BTR1_CLKDIV_0 (0x1UL << FMC_BTR1_CLKDIV_Pos)

0x00100000

◆ FMC_BTR1_CLKDIV_1

#define FMC_BTR1_CLKDIV_1 (0x2UL << FMC_BTR1_CLKDIV_Pos)

0x00200000

◆ FMC_BTR1_CLKDIV_2

#define FMC_BTR1_CLKDIV_2 (0x4UL << FMC_BTR1_CLKDIV_Pos)

0x00400000

◆ FMC_BTR1_CLKDIV_3

#define FMC_BTR1_CLKDIV_3 (0x8UL << FMC_BTR1_CLKDIV_Pos)

0x00800000

◆ FMC_BTR1_CLKDIV_Msk

#define FMC_BTR1_CLKDIV_Msk (0xFUL << FMC_BTR1_CLKDIV_Pos)

0x00F00000

◆ FMC_BTR1_CLKDIV_Pos

#define FMC_BTR1_CLKDIV_Pos (20U)

◆ FMC_BTR1_DATAST

#define FMC_BTR1_DATAST FMC_BTR1_DATAST_Msk

DATAST [3:0] bits (Data-phase duration)

◆ FMC_BTR1_DATAST_0

#define FMC_BTR1_DATAST_0 (0x01UL << FMC_BTR1_DATAST_Pos)

0x00000100

◆ FMC_BTR1_DATAST_1

#define FMC_BTR1_DATAST_1 (0x02UL << FMC_BTR1_DATAST_Pos)

0x00000200

◆ FMC_BTR1_DATAST_2

#define FMC_BTR1_DATAST_2 (0x04UL << FMC_BTR1_DATAST_Pos)

0x00000400

◆ FMC_BTR1_DATAST_3

#define FMC_BTR1_DATAST_3 (0x08UL << FMC_BTR1_DATAST_Pos)

0x00000800

◆ FMC_BTR1_DATAST_4

#define FMC_BTR1_DATAST_4 (0x10UL << FMC_BTR1_DATAST_Pos)

0x00001000

◆ FMC_BTR1_DATAST_5

#define FMC_BTR1_DATAST_5 (0x20UL << FMC_BTR1_DATAST_Pos)

0x00002000

◆ FMC_BTR1_DATAST_6

#define FMC_BTR1_DATAST_6 (0x40UL << FMC_BTR1_DATAST_Pos)

0x00004000

◆ FMC_BTR1_DATAST_7

#define FMC_BTR1_DATAST_7 (0x80UL << FMC_BTR1_DATAST_Pos)

0x00008000

◆ FMC_BTR1_DATAST_Msk

#define FMC_BTR1_DATAST_Msk (0xFFUL << FMC_BTR1_DATAST_Pos)

0x0000FF00

◆ FMC_BTR1_DATAST_Pos

#define FMC_BTR1_DATAST_Pos (8U)

◆ FMC_BTR1_DATLAT

#define FMC_BTR1_DATLAT FMC_BTR1_DATLAT_Msk

DATLA[3:0] bits (Data latency)

◆ FMC_BTR1_DATLAT_0

#define FMC_BTR1_DATLAT_0 (0x1UL << FMC_BTR1_DATLAT_Pos)

0x01000000

◆ FMC_BTR1_DATLAT_1

#define FMC_BTR1_DATLAT_1 (0x2UL << FMC_BTR1_DATLAT_Pos)

0x02000000

◆ FMC_BTR1_DATLAT_2

#define FMC_BTR1_DATLAT_2 (0x4UL << FMC_BTR1_DATLAT_Pos)

0x04000000

◆ FMC_BTR1_DATLAT_3

#define FMC_BTR1_DATLAT_3 (0x8UL << FMC_BTR1_DATLAT_Pos)

0x08000000

◆ FMC_BTR1_DATLAT_Msk

#define FMC_BTR1_DATLAT_Msk (0xFUL << FMC_BTR1_DATLAT_Pos)

0x0F000000

◆ FMC_BTR1_DATLAT_Pos

#define FMC_BTR1_DATLAT_Pos (24U)

◆ FMC_BTR2_ACCMOD

#define FMC_BTR2_ACCMOD FMC_BTR2_ACCMOD_Msk

ACCMOD[1:0] bits (Access mode)

◆ FMC_BTR2_ACCMOD_0

#define FMC_BTR2_ACCMOD_0 (0x1UL << FMC_BTR2_ACCMOD_Pos)

0x10000000

◆ FMC_BTR2_ACCMOD_1

#define FMC_BTR2_ACCMOD_1 (0x2UL << FMC_BTR2_ACCMOD_Pos)

0x20000000

◆ FMC_BTR2_ACCMOD_Msk

#define FMC_BTR2_ACCMOD_Msk (0x3UL << FMC_BTR2_ACCMOD_Pos)

0x30000000

◆ FMC_BTR2_ACCMOD_Pos

#define FMC_BTR2_ACCMOD_Pos (28U)

◆ FMC_BTR2_ADDHLD

#define FMC_BTR2_ADDHLD FMC_BTR2_ADDHLD_Msk

ADDHLD[3:0] bits (Address-hold phase duration)

◆ FMC_BTR2_ADDHLD_0

#define FMC_BTR2_ADDHLD_0 (0x1UL << FMC_BTR2_ADDHLD_Pos)

0x00000010

◆ FMC_BTR2_ADDHLD_1

#define FMC_BTR2_ADDHLD_1 (0x2UL << FMC_BTR2_ADDHLD_Pos)

0x00000020

◆ FMC_BTR2_ADDHLD_2

#define FMC_BTR2_ADDHLD_2 (0x4UL << FMC_BTR2_ADDHLD_Pos)

0x00000040

◆ FMC_BTR2_ADDHLD_3

#define FMC_BTR2_ADDHLD_3 (0x8UL << FMC_BTR2_ADDHLD_Pos)

0x00000080

◆ FMC_BTR2_ADDHLD_Msk

#define FMC_BTR2_ADDHLD_Msk (0xFUL << FMC_BTR2_ADDHLD_Pos)

0x000000F0

◆ FMC_BTR2_ADDHLD_Pos

#define FMC_BTR2_ADDHLD_Pos (4U)

◆ FMC_BTR2_ADDSET

#define FMC_BTR2_ADDSET FMC_BTR2_ADDSET_Msk

ADDSET[3:0] bits (Address setup phase duration)

◆ FMC_BTR2_ADDSET_0

#define FMC_BTR2_ADDSET_0 (0x1UL << FMC_BTR2_ADDSET_Pos)

0x00000001

◆ FMC_BTR2_ADDSET_1

#define FMC_BTR2_ADDSET_1 (0x2UL << FMC_BTR2_ADDSET_Pos)

0x00000002

◆ FMC_BTR2_ADDSET_2

#define FMC_BTR2_ADDSET_2 (0x4UL << FMC_BTR2_ADDSET_Pos)

0x00000004

◆ FMC_BTR2_ADDSET_3

#define FMC_BTR2_ADDSET_3 (0x8UL << FMC_BTR2_ADDSET_Pos)

0x00000008

◆ FMC_BTR2_ADDSET_Msk

#define FMC_BTR2_ADDSET_Msk (0xFUL << FMC_BTR2_ADDSET_Pos)

0x0000000F

◆ FMC_BTR2_ADDSET_Pos

#define FMC_BTR2_ADDSET_Pos (0U)

◆ FMC_BTR2_BUSTURN

#define FMC_BTR2_BUSTURN FMC_BTR2_BUSTURN_Msk

BUSTURN[3:0] bits (Bus turnaround phase duration)

◆ FMC_BTR2_BUSTURN_0

#define FMC_BTR2_BUSTURN_0 (0x1UL << FMC_BTR2_BUSTURN_Pos)

0x00010000

◆ FMC_BTR2_BUSTURN_1

#define FMC_BTR2_BUSTURN_1 (0x2UL << FMC_BTR2_BUSTURN_Pos)

0x00020000

◆ FMC_BTR2_BUSTURN_2

#define FMC_BTR2_BUSTURN_2 (0x4UL << FMC_BTR2_BUSTURN_Pos)

0x00040000

◆ FMC_BTR2_BUSTURN_3

#define FMC_BTR2_BUSTURN_3 (0x8UL << FMC_BTR2_BUSTURN_Pos)

0x00080000

◆ FMC_BTR2_BUSTURN_Msk

#define FMC_BTR2_BUSTURN_Msk (0xFUL << FMC_BTR2_BUSTURN_Pos)

0x000F0000

◆ FMC_BTR2_BUSTURN_Pos

#define FMC_BTR2_BUSTURN_Pos (16U)

◆ FMC_BTR2_CLKDIV

#define FMC_BTR2_CLKDIV FMC_BTR2_CLKDIV_Msk

CLKDIV[3:0] bits (Clock divide ratio)

◆ FMC_BTR2_CLKDIV_0

#define FMC_BTR2_CLKDIV_0 (0x1UL << FMC_BTR2_CLKDIV_Pos)

0x00100000

◆ FMC_BTR2_CLKDIV_1

#define FMC_BTR2_CLKDIV_1 (0x2UL << FMC_BTR2_CLKDIV_Pos)

0x00200000

◆ FMC_BTR2_CLKDIV_2

#define FMC_BTR2_CLKDIV_2 (0x4UL << FMC_BTR2_CLKDIV_Pos)

0x00400000

◆ FMC_BTR2_CLKDIV_3

#define FMC_BTR2_CLKDIV_3 (0x8UL << FMC_BTR2_CLKDIV_Pos)

0x00800000

◆ FMC_BTR2_CLKDIV_Msk

#define FMC_BTR2_CLKDIV_Msk (0xFUL << FMC_BTR2_CLKDIV_Pos)

0x00F00000

◆ FMC_BTR2_CLKDIV_Pos

#define FMC_BTR2_CLKDIV_Pos (20U)

◆ FMC_BTR2_DATAST

#define FMC_BTR2_DATAST FMC_BTR2_DATAST_Msk

DATAST [3:0] bits (Data-phase duration)

◆ FMC_BTR2_DATAST_0

#define FMC_BTR2_DATAST_0 (0x01UL << FMC_BTR2_DATAST_Pos)

0x00000100

◆ FMC_BTR2_DATAST_1

#define FMC_BTR2_DATAST_1 (0x02UL << FMC_BTR2_DATAST_Pos)

0x00000200

◆ FMC_BTR2_DATAST_2

#define FMC_BTR2_DATAST_2 (0x04UL << FMC_BTR2_DATAST_Pos)

0x00000400

◆ FMC_BTR2_DATAST_3

#define FMC_BTR2_DATAST_3 (0x08UL << FMC_BTR2_DATAST_Pos)

0x00000800

◆ FMC_BTR2_DATAST_4

#define FMC_BTR2_DATAST_4 (0x10UL << FMC_BTR2_DATAST_Pos)

0x00001000

◆ FMC_BTR2_DATAST_5

#define FMC_BTR2_DATAST_5 (0x20UL << FMC_BTR2_DATAST_Pos)

0x00002000

◆ FMC_BTR2_DATAST_6

#define FMC_BTR2_DATAST_6 (0x40UL << FMC_BTR2_DATAST_Pos)

0x00004000

◆ FMC_BTR2_DATAST_7

#define FMC_BTR2_DATAST_7 (0x80UL << FMC_BTR2_DATAST_Pos)

0x00008000

◆ FMC_BTR2_DATAST_Msk

#define FMC_BTR2_DATAST_Msk (0xFFUL << FMC_BTR2_DATAST_Pos)

0x0000FF00

◆ FMC_BTR2_DATAST_Pos

#define FMC_BTR2_DATAST_Pos (8U)

◆ FMC_BTR2_DATLAT

#define FMC_BTR2_DATLAT FMC_BTR2_DATLAT_Msk

DATLA[3:0] bits (Data latency)

◆ FMC_BTR2_DATLAT_0

#define FMC_BTR2_DATLAT_0 (0x1UL << FMC_BTR2_DATLAT_Pos)

0x01000000

◆ FMC_BTR2_DATLAT_1

#define FMC_BTR2_DATLAT_1 (0x2UL << FMC_BTR2_DATLAT_Pos)

0x02000000

◆ FMC_BTR2_DATLAT_2

#define FMC_BTR2_DATLAT_2 (0x4UL << FMC_BTR2_DATLAT_Pos)

0x04000000

◆ FMC_BTR2_DATLAT_3

#define FMC_BTR2_DATLAT_3 (0x8UL << FMC_BTR2_DATLAT_Pos)

0x08000000

◆ FMC_BTR2_DATLAT_Msk

#define FMC_BTR2_DATLAT_Msk (0xFUL << FMC_BTR2_DATLAT_Pos)

0x0F000000

◆ FMC_BTR2_DATLAT_Pos

#define FMC_BTR2_DATLAT_Pos (24U)

◆ FMC_BTR3_ACCMOD

#define FMC_BTR3_ACCMOD FMC_BTR3_ACCMOD_Msk

ACCMOD[1:0] bits (Access mode)

◆ FMC_BTR3_ACCMOD_0

#define FMC_BTR3_ACCMOD_0 (0x1UL << FMC_BTR3_ACCMOD_Pos)

0x10000000

◆ FMC_BTR3_ACCMOD_1

#define FMC_BTR3_ACCMOD_1 (0x2UL << FMC_BTR3_ACCMOD_Pos)

0x20000000

◆ FMC_BTR3_ACCMOD_Msk

#define FMC_BTR3_ACCMOD_Msk (0x3UL << FMC_BTR3_ACCMOD_Pos)

0x30000000

◆ FMC_BTR3_ACCMOD_Pos

#define FMC_BTR3_ACCMOD_Pos (28U)

◆ FMC_BTR3_ADDHLD

#define FMC_BTR3_ADDHLD FMC_BTR3_ADDHLD_Msk

ADDHLD[3:0] bits (Address-hold phase duration)

◆ FMC_BTR3_ADDHLD_0

#define FMC_BTR3_ADDHLD_0 (0x1UL << FMC_BTR3_ADDHLD_Pos)

0x00000010

◆ FMC_BTR3_ADDHLD_1

#define FMC_BTR3_ADDHLD_1 (0x2UL << FMC_BTR3_ADDHLD_Pos)

0x00000020

◆ FMC_BTR3_ADDHLD_2

#define FMC_BTR3_ADDHLD_2 (0x4UL << FMC_BTR3_ADDHLD_Pos)

0x00000040

◆ FMC_BTR3_ADDHLD_3

#define FMC_BTR3_ADDHLD_3 (0x8UL << FMC_BTR3_ADDHLD_Pos)

0x00000080

◆ FMC_BTR3_ADDHLD_Msk

#define FMC_BTR3_ADDHLD_Msk (0xFUL << FMC_BTR3_ADDHLD_Pos)

0x000000F0

◆ FMC_BTR3_ADDHLD_Pos

#define FMC_BTR3_ADDHLD_Pos (4U)

◆ FMC_BTR3_ADDSET

#define FMC_BTR3_ADDSET FMC_BTR3_ADDSET_Msk

ADDSET[3:0] bits (Address setup phase duration)

◆ FMC_BTR3_ADDSET_0

#define FMC_BTR3_ADDSET_0 (0x1UL << FMC_BTR3_ADDSET_Pos)

0x00000001

◆ FMC_BTR3_ADDSET_1

#define FMC_BTR3_ADDSET_1 (0x2UL << FMC_BTR3_ADDSET_Pos)

0x00000002

◆ FMC_BTR3_ADDSET_2

#define FMC_BTR3_ADDSET_2 (0x4UL << FMC_BTR3_ADDSET_Pos)

0x00000004

◆ FMC_BTR3_ADDSET_3

#define FMC_BTR3_ADDSET_3 (0x8UL << FMC_BTR3_ADDSET_Pos)

0x00000008

◆ FMC_BTR3_ADDSET_Msk

#define FMC_BTR3_ADDSET_Msk (0xFUL << FMC_BTR3_ADDSET_Pos)

0x0000000F

◆ FMC_BTR3_ADDSET_Pos

#define FMC_BTR3_ADDSET_Pos (0U)

◆ FMC_BTR3_BUSTURN

#define FMC_BTR3_BUSTURN FMC_BTR3_BUSTURN_Msk

BUSTURN[3:0] bits (Bus turnaround phase duration)

◆ FMC_BTR3_BUSTURN_0

#define FMC_BTR3_BUSTURN_0 (0x1UL << FMC_BTR3_BUSTURN_Pos)

0x00010000

◆ FMC_BTR3_BUSTURN_1

#define FMC_BTR3_BUSTURN_1 (0x2UL << FMC_BTR3_BUSTURN_Pos)

0x00020000

◆ FMC_BTR3_BUSTURN_2

#define FMC_BTR3_BUSTURN_2 (0x4UL << FMC_BTR3_BUSTURN_Pos)

0x00040000

◆ FMC_BTR3_BUSTURN_3

#define FMC_BTR3_BUSTURN_3 (0x8UL << FMC_BTR3_BUSTURN_Pos)

0x00080000

◆ FMC_BTR3_BUSTURN_Msk

#define FMC_BTR3_BUSTURN_Msk (0xFUL << FMC_BTR3_BUSTURN_Pos)

0x000F0000

◆ FMC_BTR3_BUSTURN_Pos

#define FMC_BTR3_BUSTURN_Pos (16U)

◆ FMC_BTR3_CLKDIV

#define FMC_BTR3_CLKDIV FMC_BTR3_CLKDIV_Msk

CLKDIV[3:0] bits (Clock divide ratio)

◆ FMC_BTR3_CLKDIV_0

#define FMC_BTR3_CLKDIV_0 (0x1UL << FMC_BTR3_CLKDIV_Pos)

0x00100000

◆ FMC_BTR3_CLKDIV_1

#define FMC_BTR3_CLKDIV_1 (0x2UL << FMC_BTR3_CLKDIV_Pos)

0x00200000

◆ FMC_BTR3_CLKDIV_2

#define FMC_BTR3_CLKDIV_2 (0x4UL << FMC_BTR3_CLKDIV_Pos)

0x00400000

◆ FMC_BTR3_CLKDIV_3

#define FMC_BTR3_CLKDIV_3 (0x8UL << FMC_BTR3_CLKDIV_Pos)

0x00800000

◆ FMC_BTR3_CLKDIV_Msk

#define FMC_BTR3_CLKDIV_Msk (0xFUL << FMC_BTR3_CLKDIV_Pos)

0x00F00000

◆ FMC_BTR3_CLKDIV_Pos

#define FMC_BTR3_CLKDIV_Pos (20U)

◆ FMC_BTR3_DATAST

#define FMC_BTR3_DATAST FMC_BTR3_DATAST_Msk

DATAST [3:0] bits (Data-phase duration)

◆ FMC_BTR3_DATAST_0

#define FMC_BTR3_DATAST_0 (0x01UL << FMC_BTR3_DATAST_Pos)

0x00000100

◆ FMC_BTR3_DATAST_1

#define FMC_BTR3_DATAST_1 (0x02UL << FMC_BTR3_DATAST_Pos)

0x00000200

◆ FMC_BTR3_DATAST_2

#define FMC_BTR3_DATAST_2 (0x04UL << FMC_BTR3_DATAST_Pos)

0x00000400

◆ FMC_BTR3_DATAST_3

#define FMC_BTR3_DATAST_3 (0x08UL << FMC_BTR3_DATAST_Pos)

0x00000800

◆ FMC_BTR3_DATAST_4

#define FMC_BTR3_DATAST_4 (0x10UL << FMC_BTR3_DATAST_Pos)

0x00001000

◆ FMC_BTR3_DATAST_5

#define FMC_BTR3_DATAST_5 (0x20UL << FMC_BTR3_DATAST_Pos)

0x00002000

◆ FMC_BTR3_DATAST_6

#define FMC_BTR3_DATAST_6 (0x40UL << FMC_BTR3_DATAST_Pos)

0x00004000

◆ FMC_BTR3_DATAST_7

#define FMC_BTR3_DATAST_7 (0x80UL << FMC_BTR3_DATAST_Pos)

0x00008000

◆ FMC_BTR3_DATAST_Msk

#define FMC_BTR3_DATAST_Msk (0xFFUL << FMC_BTR3_DATAST_Pos)

0x0000FF00

◆ FMC_BTR3_DATAST_Pos

#define FMC_BTR3_DATAST_Pos (8U)

◆ FMC_BTR3_DATLAT

#define FMC_BTR3_DATLAT FMC_BTR3_DATLAT_Msk

DATLA[3:0] bits (Data latency)

◆ FMC_BTR3_DATLAT_0

#define FMC_BTR3_DATLAT_0 (0x1UL << FMC_BTR3_DATLAT_Pos)

0x01000000

◆ FMC_BTR3_DATLAT_1

#define FMC_BTR3_DATLAT_1 (0x2UL << FMC_BTR3_DATLAT_Pos)

0x02000000

◆ FMC_BTR3_DATLAT_2

#define FMC_BTR3_DATLAT_2 (0x4UL << FMC_BTR3_DATLAT_Pos)

0x04000000

◆ FMC_BTR3_DATLAT_3

#define FMC_BTR3_DATLAT_3 (0x8UL << FMC_BTR3_DATLAT_Pos)

0x08000000

◆ FMC_BTR3_DATLAT_Msk

#define FMC_BTR3_DATLAT_Msk (0xFUL << FMC_BTR3_DATLAT_Pos)

0x0F000000

◆ FMC_BTR3_DATLAT_Pos

#define FMC_BTR3_DATLAT_Pos (24U)

◆ FMC_BTR4_ACCMOD

#define FMC_BTR4_ACCMOD FMC_BTR4_ACCMOD_Msk

ACCMOD[1:0] bits (Access mode)

◆ FMC_BTR4_ACCMOD_0

#define FMC_BTR4_ACCMOD_0 (0x1UL << FMC_BTR4_ACCMOD_Pos)

0x10000000

◆ FMC_BTR4_ACCMOD_1

#define FMC_BTR4_ACCMOD_1 (0x2UL << FMC_BTR4_ACCMOD_Pos)

0x20000000

◆ FMC_BTR4_ACCMOD_Msk

#define FMC_BTR4_ACCMOD_Msk (0x3UL << FMC_BTR4_ACCMOD_Pos)

0x30000000

◆ FMC_BTR4_ACCMOD_Pos

#define FMC_BTR4_ACCMOD_Pos (28U)

◆ FMC_BTR4_ADDHLD

#define FMC_BTR4_ADDHLD FMC_BTR4_ADDHLD_Msk

ADDHLD[3:0] bits (Address-hold phase duration)

◆ FMC_BTR4_ADDHLD_0

#define FMC_BTR4_ADDHLD_0 (0x1UL << FMC_BTR4_ADDHLD_Pos)

0x00000010

◆ FMC_BTR4_ADDHLD_1

#define FMC_BTR4_ADDHLD_1 (0x2UL << FMC_BTR4_ADDHLD_Pos)

0x00000020

◆ FMC_BTR4_ADDHLD_2

#define FMC_BTR4_ADDHLD_2 (0x4UL << FMC_BTR4_ADDHLD_Pos)

0x00000040

◆ FMC_BTR4_ADDHLD_3

#define FMC_BTR4_ADDHLD_3 (0x8UL << FMC_BTR4_ADDHLD_Pos)

0x00000080

◆ FMC_BTR4_ADDHLD_Msk

#define FMC_BTR4_ADDHLD_Msk (0xFUL << FMC_BTR4_ADDHLD_Pos)

0x000000F0

◆ FMC_BTR4_ADDHLD_Pos

#define FMC_BTR4_ADDHLD_Pos (4U)

◆ FMC_BTR4_ADDSET

#define FMC_BTR4_ADDSET FMC_BTR4_ADDSET_Msk

ADDSET[3:0] bits (Address setup phase duration)

◆ FMC_BTR4_ADDSET_0

#define FMC_BTR4_ADDSET_0 (0x1UL << FMC_BTR4_ADDSET_Pos)

0x00000001

◆ FMC_BTR4_ADDSET_1

#define FMC_BTR4_ADDSET_1 (0x2UL << FMC_BTR4_ADDSET_Pos)

0x00000002

◆ FMC_BTR4_ADDSET_2

#define FMC_BTR4_ADDSET_2 (0x4UL << FMC_BTR4_ADDSET_Pos)

0x00000004

◆ FMC_BTR4_ADDSET_3

#define FMC_BTR4_ADDSET_3 (0x8UL << FMC_BTR4_ADDSET_Pos)

0x00000008

◆ FMC_BTR4_ADDSET_Msk

#define FMC_BTR4_ADDSET_Msk (0xFUL << FMC_BTR4_ADDSET_Pos)

0x0000000F

◆ FMC_BTR4_ADDSET_Pos

#define FMC_BTR4_ADDSET_Pos (0U)

◆ FMC_BTR4_BUSTURN

#define FMC_BTR4_BUSTURN FMC_BTR4_BUSTURN_Msk

BUSTURN[3:0] bits (Bus turnaround phase duration)

◆ FMC_BTR4_BUSTURN_0

#define FMC_BTR4_BUSTURN_0 (0x1UL << FMC_BTR4_BUSTURN_Pos)

0x00010000

◆ FMC_BTR4_BUSTURN_1

#define FMC_BTR4_BUSTURN_1 (0x2UL << FMC_BTR4_BUSTURN_Pos)

0x00020000

◆ FMC_BTR4_BUSTURN_2

#define FMC_BTR4_BUSTURN_2 (0x4UL << FMC_BTR4_BUSTURN_Pos)

0x00040000

◆ FMC_BTR4_BUSTURN_3

#define FMC_BTR4_BUSTURN_3 (0x8UL << FMC_BTR4_BUSTURN_Pos)

0x00080000

◆ FMC_BTR4_BUSTURN_Msk

#define FMC_BTR4_BUSTURN_Msk (0xFUL << FMC_BTR4_BUSTURN_Pos)

0x000F0000

◆ FMC_BTR4_BUSTURN_Pos

#define FMC_BTR4_BUSTURN_Pos (16U)

◆ FMC_BTR4_CLKDIV

#define FMC_BTR4_CLKDIV FMC_BTR4_CLKDIV_Msk

CLKDIV[3:0] bits (Clock divide ratio)

◆ FMC_BTR4_CLKDIV_0

#define FMC_BTR4_CLKDIV_0 (0x1UL << FMC_BTR4_CLKDIV_Pos)

0x00100000

◆ FMC_BTR4_CLKDIV_1

#define FMC_BTR4_CLKDIV_1 (0x2UL << FMC_BTR4_CLKDIV_Pos)

0x00200000

◆ FMC_BTR4_CLKDIV_2

#define FMC_BTR4_CLKDIV_2 (0x4UL << FMC_BTR4_CLKDIV_Pos)

0x00400000

◆ FMC_BTR4_CLKDIV_3

#define FMC_BTR4_CLKDIV_3 (0x8UL << FMC_BTR4_CLKDIV_Pos)

0x00800000

◆ FMC_BTR4_CLKDIV_Msk

#define FMC_BTR4_CLKDIV_Msk (0xFUL << FMC_BTR4_CLKDIV_Pos)

0x00F00000

◆ FMC_BTR4_CLKDIV_Pos

#define FMC_BTR4_CLKDIV_Pos (20U)

◆ FMC_BTR4_DATAST

#define FMC_BTR4_DATAST FMC_BTR4_DATAST_Msk

DATAST [3:0] bits (Data-phase duration)

◆ FMC_BTR4_DATAST_0

#define FMC_BTR4_DATAST_0 (0x01UL << FMC_BTR4_DATAST_Pos)

0x00000100

◆ FMC_BTR4_DATAST_1

#define FMC_BTR4_DATAST_1 (0x02UL << FMC_BTR4_DATAST_Pos)

0x00000200

◆ FMC_BTR4_DATAST_2

#define FMC_BTR4_DATAST_2 (0x04UL << FMC_BTR4_DATAST_Pos)

0x00000400

◆ FMC_BTR4_DATAST_3

#define FMC_BTR4_DATAST_3 (0x08UL << FMC_BTR4_DATAST_Pos)

0x00000800

◆ FMC_BTR4_DATAST_4

#define FMC_BTR4_DATAST_4 (0x10UL << FMC_BTR4_DATAST_Pos)

0x00001000

◆ FMC_BTR4_DATAST_5

#define FMC_BTR4_DATAST_5 (0x20UL << FMC_BTR4_DATAST_Pos)

0x00002000

◆ FMC_BTR4_DATAST_6

#define FMC_BTR4_DATAST_6 (0x40UL << FMC_BTR4_DATAST_Pos)

0x00004000

◆ FMC_BTR4_DATAST_7

#define FMC_BTR4_DATAST_7 (0x80UL << FMC_BTR4_DATAST_Pos)

0x00008000

◆ FMC_BTR4_DATAST_Msk

#define FMC_BTR4_DATAST_Msk (0xFFUL << FMC_BTR4_DATAST_Pos)

0x0000FF00

◆ FMC_BTR4_DATAST_Pos

#define FMC_BTR4_DATAST_Pos (8U)

◆ FMC_BTR4_DATLAT

#define FMC_BTR4_DATLAT FMC_BTR4_DATLAT_Msk

DATLA[3:0] bits (Data latency)

◆ FMC_BTR4_DATLAT_0

#define FMC_BTR4_DATLAT_0 (0x1UL << FMC_BTR4_DATLAT_Pos)

0x01000000

◆ FMC_BTR4_DATLAT_1

#define FMC_BTR4_DATLAT_1 (0x2UL << FMC_BTR4_DATLAT_Pos)

0x02000000

◆ FMC_BTR4_DATLAT_2

#define FMC_BTR4_DATLAT_2 (0x4UL << FMC_BTR4_DATLAT_Pos)

0x04000000

◆ FMC_BTR4_DATLAT_3

#define FMC_BTR4_DATLAT_3 (0x8UL << FMC_BTR4_DATLAT_Pos)

0x08000000

◆ FMC_BTR4_DATLAT_Msk

#define FMC_BTR4_DATLAT_Msk (0xFUL << FMC_BTR4_DATLAT_Pos)

0x0F000000

◆ FMC_BTR4_DATLAT_Pos

#define FMC_BTR4_DATLAT_Pos (24U)

◆ FMC_BTR_ADDSET_3

#define FMC_BTR_ADDSET_3 (0x00000008U)

Bit 3

◆ FMC_BTR_DATAST_0

#define FMC_BTR_DATAST_0 (0x00000100U)

Bit 0

◆ FMC_BTRx_ACCMOD

#define FMC_BTRx_ACCMOD FMC_BTRx_ACCMOD_Msk

ACCMOD[1:0] bits (Access mode)

◆ FMC_BTRx_ACCMOD_0

#define FMC_BTRx_ACCMOD_0 (0x1UL << FMC_BTRx_ACCMOD_Pos)

0x10000000

◆ FMC_BTRx_ACCMOD_1

#define FMC_BTRx_ACCMOD_1 (0x2UL << FMC_BTRx_ACCMOD_Pos)

0x20000000

◆ FMC_BTRx_ACCMOD_Msk

#define FMC_BTRx_ACCMOD_Msk (0x3UL << FMC_BTRx_ACCMOD_Pos)

0x30000000

◆ FMC_BTRx_ACCMOD_Pos

#define FMC_BTRx_ACCMOD_Pos (28U)

◆ FMC_BTRx_ADDHLD

#define FMC_BTRx_ADDHLD FMC_BTRx_ADDHLD_Msk

ADDHLD[3:0] bits (Address-hold phase duration)

◆ FMC_BTRx_ADDHLD_0

#define FMC_BTRx_ADDHLD_0 (0x1UL << FMC_BTRx_ADDHLD_Pos)

0x00000010

◆ FMC_BTRx_ADDHLD_1

#define FMC_BTRx_ADDHLD_1 (0x2UL << FMC_BTRx_ADDHLD_Pos)

0x00000020

◆ FMC_BTRx_ADDHLD_2

#define FMC_BTRx_ADDHLD_2 (0x4UL << FMC_BTRx_ADDHLD_Pos)

0x00000040

◆ FMC_BTRx_ADDHLD_3

#define FMC_BTRx_ADDHLD_3 (0x8UL << FMC_BTRx_ADDHLD_Pos)

0x00000080

◆ FMC_BTRx_ADDHLD_Msk

#define FMC_BTRx_ADDHLD_Msk (0xFUL << FMC_BTRx_ADDHLD_Pos)

0x000000F0

◆ FMC_BTRx_ADDHLD_Pos

#define FMC_BTRx_ADDHLD_Pos (4U)

◆ FMC_BTRx_ADDSET

#define FMC_BTRx_ADDSET FMC_BTRx_ADDSET_Msk

ADDSET[3:0] bits (Address setup phase duration)

◆ FMC_BTRx_ADDSET_0

#define FMC_BTRx_ADDSET_0 (0x1UL << FMC_BTRx_ADDSET_Pos)

0x00000001

◆ FMC_BTRx_ADDSET_1

#define FMC_BTRx_ADDSET_1 (0x2UL << FMC_BTRx_ADDSET_Pos)

0x00000002

◆ FMC_BTRx_ADDSET_2

#define FMC_BTRx_ADDSET_2 (0x4UL << FMC_BTRx_ADDSET_Pos)

0x00000004

◆ FMC_BTRx_ADDSET_Msk

#define FMC_BTRx_ADDSET_Msk (0xFUL << FMC_BTRx_ADDSET_Pos)

0x0000000F

◆ FMC_BTRx_ADDSET_Pos

#define FMC_BTRx_ADDSET_Pos (0U)

◆ FMC_BTRx_BUSTURN

#define FMC_BTRx_BUSTURN FMC_BTRx_BUSTURN_Msk

BUSTURN[3:0] bits (Bus turnaround phase duration)

◆ FMC_BTRx_BUSTURN_0

#define FMC_BTRx_BUSTURN_0 (0x1UL << FMC_BTRx_BUSTURN_Pos)

0x00010000

◆ FMC_BTRx_BUSTURN_1

#define FMC_BTRx_BUSTURN_1 (0x2UL << FMC_BTRx_BUSTURN_Pos)

0x00020000

◆ FMC_BTRx_BUSTURN_2

#define FMC_BTRx_BUSTURN_2 (0x4UL << FMC_BTRx_BUSTURN_Pos)

0x00040000

◆ FMC_BTRx_BUSTURN_3

#define FMC_BTRx_BUSTURN_3 (0x8UL << FMC_BTRx_BUSTURN_Pos)

0x00080000

◆ FMC_BTRx_BUSTURN_Msk

#define FMC_BTRx_BUSTURN_Msk (0xFUL << FMC_BTRx_BUSTURN_Pos)

0x000F0000

◆ FMC_BTRx_BUSTURN_Pos

#define FMC_BTRx_BUSTURN_Pos (16U)

◆ FMC_BTRx_CLKDIV

#define FMC_BTRx_CLKDIV FMC_BTRx_CLKDIV_Msk

CLKDIV[3:0] bits (Clock divide ratio)

◆ FMC_BTRx_CLKDIV_0

#define FMC_BTRx_CLKDIV_0 (0x1UL << FMC_BTRx_CLKDIV_Pos)

0x00100000

◆ FMC_BTRx_CLKDIV_1

#define FMC_BTRx_CLKDIV_1 (0x2UL << FMC_BTRx_CLKDIV_Pos)

0x00200000

◆ FMC_BTRx_CLKDIV_2

#define FMC_BTRx_CLKDIV_2 (0x4UL << FMC_BTRx_CLKDIV_Pos)

0x00400000

◆ FMC_BTRx_CLKDIV_3

#define FMC_BTRx_CLKDIV_3 (0x8UL << FMC_BTRx_CLKDIV_Pos)

0x00800000

◆ FMC_BTRx_CLKDIV_Msk

#define FMC_BTRx_CLKDIV_Msk (0xFUL << FMC_BTRx_CLKDIV_Pos)

0x00F00000

◆ FMC_BTRx_CLKDIV_Pos

#define FMC_BTRx_CLKDIV_Pos (20U)

◆ FMC_BTRx_DATAST

#define FMC_BTRx_DATAST FMC_BTRx_DATAST_Msk

DATAST [3:0] bits (Data-phase duration)

◆ FMC_BTRx_DATAST_1

#define FMC_BTRx_DATAST_1 (0x00000200U)

Bit 1

◆ FMC_BTRx_DATAST_2

#define FMC_BTRx_DATAST_2 (0x00000400U)

Bit 2

◆ FMC_BTRx_DATAST_3

#define FMC_BTRx_DATAST_3 (0x00000800U)

Bit 3

◆ FMC_BTRx_DATAST_4

#define FMC_BTRx_DATAST_4 (0x00001000U)

Bit 4

◆ FMC_BTRx_DATAST_5

#define FMC_BTRx_DATAST_5 (0x00002000U)

Bit 5

◆ FMC_BTRx_DATAST_6

#define FMC_BTRx_DATAST_6 (0x00004000U)

Bit 6

◆ FMC_BTRx_DATAST_7

#define FMC_BTRx_DATAST_7 (0x00008000U)

Bit 7

◆ FMC_BTRx_DATAST_Msk

#define FMC_BTRx_DATAST_Msk (0xFFUL << FMC_BTRx_DATAST_Pos)

0x0000FF00

◆ FMC_BTRx_DATAST_Pos

#define FMC_BTRx_DATAST_Pos (8U)

◆ FMC_BTRx_DATLAT

#define FMC_BTRx_DATLAT FMC_BTRx_DATLAT_Msk

DATLA[3:0] bits (Data latency)

◆ FMC_BTRx_DATLAT_0

#define FMC_BTRx_DATLAT_0 (0x1UL << FMC_BTRx_DATLAT_Pos)

0x01000000

◆ FMC_BTRx_DATLAT_1

#define FMC_BTRx_DATLAT_1 (0x2UL << FMC_BTRx_DATLAT_Pos)

0x02000000

◆ FMC_BTRx_DATLAT_2

#define FMC_BTRx_DATLAT_2 (0x4UL << FMC_BTRx_DATLAT_Pos)

0x04000000

◆ FMC_BTRx_DATLAT_3

#define FMC_BTRx_DATLAT_3 (0x8UL << FMC_BTRx_DATLAT_Pos)

0x08000000

◆ FMC_BTRx_DATLAT_Msk

#define FMC_BTRx_DATLAT_Msk (0xFUL << FMC_BTRx_DATLAT_Pos)

0x0F000000

◆ FMC_BTRx_DATLAT_Pos

#define FMC_BTRx_DATLAT_Pos (24U)

◆ FMC_BWTR1_ACCMOD

#define FMC_BWTR1_ACCMOD FMC_BWTR1_ACCMOD_Msk

ACCMOD[1:0] bits (Access mode)

◆ FMC_BWTR1_ACCMOD_0

#define FMC_BWTR1_ACCMOD_0 (0x1UL << FMC_BWTR1_ACCMOD_Pos)

0x10000000

◆ FMC_BWTR1_ACCMOD_1

#define FMC_BWTR1_ACCMOD_1 (0x2UL << FMC_BWTR1_ACCMOD_Pos)

0x20000000

◆ FMC_BWTR1_ACCMOD_Msk

#define FMC_BWTR1_ACCMOD_Msk (0x3UL << FMC_BWTR1_ACCMOD_Pos)

0x30000000

◆ FMC_BWTR1_ACCMOD_Pos

#define FMC_BWTR1_ACCMOD_Pos (28U)

◆ FMC_BWTR1_ADDHLD

#define FMC_BWTR1_ADDHLD FMC_BWTR1_ADDHLD_Msk

ADDHLD[3:0] bits (Address-hold phase duration)

◆ FMC_BWTR1_ADDHLD_0

#define FMC_BWTR1_ADDHLD_0 (0x1UL << FMC_BWTR1_ADDHLD_Pos)

0x00000010

◆ FMC_BWTR1_ADDHLD_1

#define FMC_BWTR1_ADDHLD_1 (0x2UL << FMC_BWTR1_ADDHLD_Pos)

0x00000020

◆ FMC_BWTR1_ADDHLD_2

#define FMC_BWTR1_ADDHLD_2 (0x4UL << FMC_BWTR1_ADDHLD_Pos)

0x00000040

◆ FMC_BWTR1_ADDHLD_3

#define FMC_BWTR1_ADDHLD_3 (0x8UL << FMC_BWTR1_ADDHLD_Pos)

0x00000080

◆ FMC_BWTR1_ADDHLD_Msk

#define FMC_BWTR1_ADDHLD_Msk (0xFUL << FMC_BWTR1_ADDHLD_Pos)

0x000000F0

◆ FMC_BWTR1_ADDHLD_Pos

#define FMC_BWTR1_ADDHLD_Pos (4U)

◆ FMC_BWTR1_ADDSET

#define FMC_BWTR1_ADDSET FMC_BWTR1_ADDSET_Msk

ADDSET[3:0] bits (Address setup phase duration)

◆ FMC_BWTR1_ADDSET_0

#define FMC_BWTR1_ADDSET_0 (0x1UL << FMC_BWTR1_ADDSET_Pos)

0x00000001

◆ FMC_BWTR1_ADDSET_1

#define FMC_BWTR1_ADDSET_1 (0x2UL << FMC_BWTR1_ADDSET_Pos)

0x00000002

◆ FMC_BWTR1_ADDSET_2

#define FMC_BWTR1_ADDSET_2 (0x4UL << FMC_BWTR1_ADDSET_Pos)

0x00000004

◆ FMC_BWTR1_ADDSET_3

#define FMC_BWTR1_ADDSET_3 (0x8UL << FMC_BWTR1_ADDSET_Pos)

0x00000008

◆ FMC_BWTR1_ADDSET_Msk

#define FMC_BWTR1_ADDSET_Msk (0xFUL << FMC_BWTR1_ADDSET_Pos)

0x0000000F

◆ FMC_BWTR1_ADDSET_Pos

#define FMC_BWTR1_ADDSET_Pos (0U)

◆ FMC_BWTR1_CLKDIV

#define FMC_BWTR1_CLKDIV FMC_BWTR1_CLKDIV_Msk

CLKDIV[3:0] bits (Clock divide ratio)

◆ FMC_BWTR1_CLKDIV_0

#define FMC_BWTR1_CLKDIV_0 (0x1UL << FMC_BWTR1_CLKDIV_Pos)

0x00100000

◆ FMC_BWTR1_CLKDIV_1

#define FMC_BWTR1_CLKDIV_1 (0x2UL << FMC_BWTR1_CLKDIV_Pos)

0x00200000

◆ FMC_BWTR1_CLKDIV_2

#define FMC_BWTR1_CLKDIV_2 (0x4UL << FMC_BWTR1_CLKDIV_Pos)

0x00400000

◆ FMC_BWTR1_CLKDIV_3

#define FMC_BWTR1_CLKDIV_3 (0x8UL << FMC_BWTR1_CLKDIV_Pos)

0x00800000

◆ FMC_BWTR1_CLKDIV_Msk

#define FMC_BWTR1_CLKDIV_Msk (0xFUL << FMC_BWTR1_CLKDIV_Pos)

0x00F00000

◆ FMC_BWTR1_CLKDIV_Pos

#define FMC_BWTR1_CLKDIV_Pos (20U)

◆ FMC_BWTR1_DATAST

#define FMC_BWTR1_DATAST FMC_BWTR1_DATAST_Msk

DATAST [3:0] bits (Data-phase duration)

◆ FMC_BWTR1_DATAST_0

#define FMC_BWTR1_DATAST_0 (0x01UL << FMC_BWTR1_DATAST_Pos)

0x00000100

◆ FMC_BWTR1_DATAST_1

#define FMC_BWTR1_DATAST_1 (0x02UL << FMC_BWTR1_DATAST_Pos)

0x00000200

◆ FMC_BWTR1_DATAST_2

#define FMC_BWTR1_DATAST_2 (0x04UL << FMC_BWTR1_DATAST_Pos)

0x00000400

◆ FMC_BWTR1_DATAST_3

#define FMC_BWTR1_DATAST_3 (0x08UL << FMC_BWTR1_DATAST_Pos)

0x00000800

◆ FMC_BWTR1_DATAST_4

#define FMC_BWTR1_DATAST_4 (0x10UL << FMC_BWTR1_DATAST_Pos)

0x00001000

◆ FMC_BWTR1_DATAST_5

#define FMC_BWTR1_DATAST_5 (0x20UL << FMC_BWTR1_DATAST_Pos)

0x00002000

◆ FMC_BWTR1_DATAST_6

#define FMC_BWTR1_DATAST_6 (0x40UL << FMC_BWTR1_DATAST_Pos)

0x00004000

◆ FMC_BWTR1_DATAST_7

#define FMC_BWTR1_DATAST_7 (0x80UL << FMC_BWTR1_DATAST_Pos)

0x00008000

◆ FMC_BWTR1_DATAST_Msk

#define FMC_BWTR1_DATAST_Msk (0xFFUL << FMC_BWTR1_DATAST_Pos)

0x0000FF00

◆ FMC_BWTR1_DATAST_Pos

#define FMC_BWTR1_DATAST_Pos (8U)

◆ FMC_BWTR1_DATLAT

#define FMC_BWTR1_DATLAT FMC_BWTR1_DATLAT_Msk

DATLA[3:0] bits (Data latency)

◆ FMC_BWTR1_DATLAT_0

#define FMC_BWTR1_DATLAT_0 (0x1UL << FMC_BWTR1_DATLAT_Pos)

0x01000000

◆ FMC_BWTR1_DATLAT_1

#define FMC_BWTR1_DATLAT_1 (0x2UL << FMC_BWTR1_DATLAT_Pos)

0x02000000

◆ FMC_BWTR1_DATLAT_2

#define FMC_BWTR1_DATLAT_2 (0x4UL << FMC_BWTR1_DATLAT_Pos)

0x04000000

◆ FMC_BWTR1_DATLAT_3

#define FMC_BWTR1_DATLAT_3 (0x8UL << FMC_BWTR1_DATLAT_Pos)

0x08000000

◆ FMC_BWTR1_DATLAT_Msk

#define FMC_BWTR1_DATLAT_Msk (0xFUL << FMC_BWTR1_DATLAT_Pos)

0x0F000000

◆ FMC_BWTR1_DATLAT_Pos

#define FMC_BWTR1_DATLAT_Pos (24U)

◆ FMC_BWTR2_ACCMOD

#define FMC_BWTR2_ACCMOD FMC_BWTR2_ACCMOD_Msk

ACCMOD[1:0] bits (Access mode)

◆ FMC_BWTR2_ACCMOD_0

#define FMC_BWTR2_ACCMOD_0 (0x1UL << FMC_BWTR2_ACCMOD_Pos)

0x10000000

◆ FMC_BWTR2_ACCMOD_1

#define FMC_BWTR2_ACCMOD_1 (0x2UL << FMC_BWTR2_ACCMOD_Pos)

0x20000000

◆ FMC_BWTR2_ACCMOD_Msk

#define FMC_BWTR2_ACCMOD_Msk (0x3UL << FMC_BWTR2_ACCMOD_Pos)

0x30000000

◆ FMC_BWTR2_ACCMOD_Pos

#define FMC_BWTR2_ACCMOD_Pos (28U)

◆ FMC_BWTR2_ADDHLD

#define FMC_BWTR2_ADDHLD FMC_BWTR2_ADDHLD_Msk

ADDHLD[3:0] bits (Address-hold phase duration)

◆ FMC_BWTR2_ADDHLD_0

#define FMC_BWTR2_ADDHLD_0 (0x1UL << FMC_BWTR2_ADDHLD_Pos)

0x00000010

◆ FMC_BWTR2_ADDHLD_1

#define FMC_BWTR2_ADDHLD_1 (0x2UL << FMC_BWTR2_ADDHLD_Pos)

0x00000020

◆ FMC_BWTR2_ADDHLD_2

#define FMC_BWTR2_ADDHLD_2 (0x4UL << FMC_BWTR2_ADDHLD_Pos)

0x00000040

◆ FMC_BWTR2_ADDHLD_3

#define FMC_BWTR2_ADDHLD_3 (0x8UL << FMC_BWTR2_ADDHLD_Pos)

0x00000080

◆ FMC_BWTR2_ADDHLD_Msk

#define FMC_BWTR2_ADDHLD_Msk (0xFUL << FMC_BWTR2_ADDHLD_Pos)

0x000000F0

◆ FMC_BWTR2_ADDHLD_Pos

#define FMC_BWTR2_ADDHLD_Pos (4U)

◆ FMC_BWTR2_ADDSET

#define FMC_BWTR2_ADDSET FMC_BWTR2_ADDSET_Msk

ADDSET[3:0] bits (Address setup phase duration)

◆ FMC_BWTR2_ADDSET_0

#define FMC_BWTR2_ADDSET_0 (0x1UL << FMC_BWTR2_ADDSET_Pos)

0x00000001

◆ FMC_BWTR2_ADDSET_1

#define FMC_BWTR2_ADDSET_1 (0x2UL << FMC_BWTR2_ADDSET_Pos)

0x00000002

◆ FMC_BWTR2_ADDSET_2

#define FMC_BWTR2_ADDSET_2 (0x4UL << FMC_BWTR2_ADDSET_Pos)

0x00000004

◆ FMC_BWTR2_ADDSET_3

#define FMC_BWTR2_ADDSET_3 (0x8UL << FMC_BWTR2_ADDSET_Pos)

0x00000008

◆ FMC_BWTR2_ADDSET_Msk

#define FMC_BWTR2_ADDSET_Msk (0xFUL << FMC_BWTR2_ADDSET_Pos)

0x0000000F

◆ FMC_BWTR2_ADDSET_Pos

#define FMC_BWTR2_ADDSET_Pos (0U)

◆ FMC_BWTR2_CLKDIV

#define FMC_BWTR2_CLKDIV FMC_BWTR2_CLKDIV_Msk

CLKDIV[3:0] bits (Clock divide ratio)

◆ FMC_BWTR2_CLKDIV_0

#define FMC_BWTR2_CLKDIV_0 (0x1UL << FMC_BWTR2_CLKDIV_Pos)

0x00100000

◆ FMC_BWTR2_CLKDIV_1

#define FMC_BWTR2_CLKDIV_1 (0x2UL << FMC_BWTR2_CLKDIV_Pos)

0x00200000

◆ FMC_BWTR2_CLKDIV_2

#define FMC_BWTR2_CLKDIV_2 (0x4UL << FMC_BWTR2_CLKDIV_Pos)

0x00400000

◆ FMC_BWTR2_CLKDIV_3

#define FMC_BWTR2_CLKDIV_3 (0x8UL << FMC_BWTR2_CLKDIV_Pos)

0x00800000

◆ FMC_BWTR2_CLKDIV_Msk

#define FMC_BWTR2_CLKDIV_Msk (0xFUL << FMC_BWTR2_CLKDIV_Pos)

0x00F00000

◆ FMC_BWTR2_CLKDIV_Pos

#define FMC_BWTR2_CLKDIV_Pos (20U)

◆ FMC_BWTR2_DATAST

#define FMC_BWTR2_DATAST FMC_BWTR2_DATAST_Msk

DATAST [3:0] bits (Data-phase duration)

◆ FMC_BWTR2_DATAST_0

#define FMC_BWTR2_DATAST_0 (0x01UL << FMC_BWTR2_DATAST_Pos)

0x00000100

◆ FMC_BWTR2_DATAST_1

#define FMC_BWTR2_DATAST_1 (0x02UL << FMC_BWTR2_DATAST_Pos)

0x00000200

◆ FMC_BWTR2_DATAST_2

#define FMC_BWTR2_DATAST_2 (0x04UL << FMC_BWTR2_DATAST_Pos)

0x00000400

◆ FMC_BWTR2_DATAST_3

#define FMC_BWTR2_DATAST_3 (0x08UL << FMC_BWTR2_DATAST_Pos)

0x00000800

◆ FMC_BWTR2_DATAST_4

#define FMC_BWTR2_DATAST_4 (0x10UL << FMC_BWTR2_DATAST_Pos)

0x00001000

◆ FMC_BWTR2_DATAST_5

#define FMC_BWTR2_DATAST_5 (0x20UL << FMC_BWTR2_DATAST_Pos)

0x00002000

◆ FMC_BWTR2_DATAST_6

#define FMC_BWTR2_DATAST_6 (0x40UL << FMC_BWTR2_DATAST_Pos)

0x00004000

◆ FMC_BWTR2_DATAST_7

#define FMC_BWTR2_DATAST_7 (0x80UL << FMC_BWTR2_DATAST_Pos)

0x00008000

◆ FMC_BWTR2_DATAST_Msk

#define FMC_BWTR2_DATAST_Msk (0xFFUL << FMC_BWTR2_DATAST_Pos)

0x0000FF00

◆ FMC_BWTR2_DATAST_Pos

#define FMC_BWTR2_DATAST_Pos (8U)

◆ FMC_BWTR2_DATLAT

#define FMC_BWTR2_DATLAT FMC_BWTR2_DATLAT_Msk

DATLA[3:0] bits (Data latency)

◆ FMC_BWTR2_DATLAT_0

#define FMC_BWTR2_DATLAT_0 (0x1UL << FMC_BWTR2_DATLAT_Pos)

0x01000000

◆ FMC_BWTR2_DATLAT_1

#define FMC_BWTR2_DATLAT_1 (0x2UL << FMC_BWTR2_DATLAT_Pos)

0x02000000

◆ FMC_BWTR2_DATLAT_2

#define FMC_BWTR2_DATLAT_2 (0x4UL << FMC_BWTR2_DATLAT_Pos)

0x04000000

◆ FMC_BWTR2_DATLAT_3

#define FMC_BWTR2_DATLAT_3 (0x8UL << FMC_BWTR2_DATLAT_Pos)

0x08000000

◆ FMC_BWTR2_DATLAT_Msk

#define FMC_BWTR2_DATLAT_Msk (0xFUL << FMC_BWTR2_DATLAT_Pos)

0x0F000000

◆ FMC_BWTR2_DATLAT_Pos

#define FMC_BWTR2_DATLAT_Pos (24U)

◆ FMC_BWTR3_ACCMOD

#define FMC_BWTR3_ACCMOD FMC_BWTR3_ACCMOD_Msk

ACCMOD[1:0] bits (Access mode)

◆ FMC_BWTR3_ACCMOD_0

#define FMC_BWTR3_ACCMOD_0 (0x1UL << FMC_BWTR3_ACCMOD_Pos)

0x10000000

◆ FMC_BWTR3_ACCMOD_1

#define FMC_BWTR3_ACCMOD_1 (0x2UL << FMC_BWTR3_ACCMOD_Pos)

0x20000000

◆ FMC_BWTR3_ACCMOD_Msk

#define FMC_BWTR3_ACCMOD_Msk (0x3UL << FMC_BWTR3_ACCMOD_Pos)

0x30000000

◆ FMC_BWTR3_ACCMOD_Pos

#define FMC_BWTR3_ACCMOD_Pos (28U)

◆ FMC_BWTR3_ADDHLD

#define FMC_BWTR3_ADDHLD FMC_BWTR3_ADDHLD_Msk

ADDHLD[3:0] bits (Address-hold phase duration)

◆ FMC_BWTR3_ADDHLD_0

#define FMC_BWTR3_ADDHLD_0 (0x1UL << FMC_BWTR3_ADDHLD_Pos)

0x00000010

◆ FMC_BWTR3_ADDHLD_1

#define FMC_BWTR3_ADDHLD_1 (0x2UL << FMC_BWTR3_ADDHLD_Pos)

0x00000020

◆ FMC_BWTR3_ADDHLD_2

#define FMC_BWTR3_ADDHLD_2 (0x4UL << FMC_BWTR3_ADDHLD_Pos)

0x00000040

◆ FMC_BWTR3_ADDHLD_3

#define FMC_BWTR3_ADDHLD_3 (0x8UL << FMC_BWTR3_ADDHLD_Pos)

0x00000080

◆ FMC_BWTR3_ADDHLD_Msk

#define FMC_BWTR3_ADDHLD_Msk (0xFUL << FMC_BWTR3_ADDHLD_Pos)

0x000000F0

◆ FMC_BWTR3_ADDHLD_Pos

#define FMC_BWTR3_ADDHLD_Pos (4U)

◆ FMC_BWTR3_ADDSET

#define FMC_BWTR3_ADDSET FMC_BWTR3_ADDSET_Msk

ADDSET[3:0] bits (Address setup phase duration)

◆ FMC_BWTR3_ADDSET_0

#define FMC_BWTR3_ADDSET_0 (0x1UL << FMC_BWTR3_ADDSET_Pos)

0x00000001

◆ FMC_BWTR3_ADDSET_1

#define FMC_BWTR3_ADDSET_1 (0x2UL << FMC_BWTR3_ADDSET_Pos)

0x00000002

◆ FMC_BWTR3_ADDSET_2

#define FMC_BWTR3_ADDSET_2 (0x4UL << FMC_BWTR3_ADDSET_Pos)

0x00000004

◆ FMC_BWTR3_ADDSET_3

#define FMC_BWTR3_ADDSET_3 (0x8UL << FMC_BWTR3_ADDSET_Pos)

0x00000008

◆ FMC_BWTR3_ADDSET_Msk

#define FMC_BWTR3_ADDSET_Msk (0xFUL << FMC_BWTR3_ADDSET_Pos)

0x0000000F

◆ FMC_BWTR3_ADDSET_Pos

#define FMC_BWTR3_ADDSET_Pos (0U)

◆ FMC_BWTR3_CLKDIV

#define FMC_BWTR3_CLKDIV FMC_BWTR3_CLKDIV_Msk

CLKDIV[3:0] bits (Clock divide ratio)

◆ FMC_BWTR3_CLKDIV_0

#define FMC_BWTR3_CLKDIV_0 (0x1UL << FMC_BWTR3_CLKDIV_Pos)

0x00100000

◆ FMC_BWTR3_CLKDIV_1

#define FMC_BWTR3_CLKDIV_1 (0x2UL << FMC_BWTR3_CLKDIV_Pos)

0x00200000

◆ FMC_BWTR3_CLKDIV_2

#define FMC_BWTR3_CLKDIV_2 (0x4UL << FMC_BWTR3_CLKDIV_Pos)

0x00400000

◆ FMC_BWTR3_CLKDIV_3

#define FMC_BWTR3_CLKDIV_3 (0x8UL << FMC_BWTR3_CLKDIV_Pos)

0x00800000

◆ FMC_BWTR3_CLKDIV_Msk

#define FMC_BWTR3_CLKDIV_Msk (0xFUL << FMC_BWTR3_CLKDIV_Pos)

0x00F00000

◆ FMC_BWTR3_CLKDIV_Pos

#define FMC_BWTR3_CLKDIV_Pos (20U)

◆ FMC_BWTR3_DATAST

#define FMC_BWTR3_DATAST FMC_BWTR3_DATAST_Msk

DATAST [3:0] bits (Data-phase duration)

◆ FMC_BWTR3_DATAST_0

#define FMC_BWTR3_DATAST_0 (0x01UL << FMC_BWTR3_DATAST_Pos)

0x00000100

◆ FMC_BWTR3_DATAST_1

#define FMC_BWTR3_DATAST_1 (0x02UL << FMC_BWTR3_DATAST_Pos)

0x00000200

◆ FMC_BWTR3_DATAST_2

#define FMC_BWTR3_DATAST_2 (0x04UL << FMC_BWTR3_DATAST_Pos)

0x00000400

◆ FMC_BWTR3_DATAST_3

#define FMC_BWTR3_DATAST_3 (0x08UL << FMC_BWTR3_DATAST_Pos)

0x00000800

◆ FMC_BWTR3_DATAST_4

#define FMC_BWTR3_DATAST_4 (0x10UL << FMC_BWTR3_DATAST_Pos)

0x00001000

◆ FMC_BWTR3_DATAST_5

#define FMC_BWTR3_DATAST_5 (0x20UL << FMC_BWTR3_DATAST_Pos)

0x00002000

◆ FMC_BWTR3_DATAST_6

#define FMC_BWTR3_DATAST_6 (0x40UL << FMC_BWTR3_DATAST_Pos)

0x00004000

◆ FMC_BWTR3_DATAST_7

#define FMC_BWTR3_DATAST_7 (0x80UL << FMC_BWTR3_DATAST_Pos)

0x00008000

◆ FMC_BWTR3_DATAST_Msk

#define FMC_BWTR3_DATAST_Msk (0xFFUL << FMC_BWTR3_DATAST_Pos)

0x0000FF00

◆ FMC_BWTR3_DATAST_Pos

#define FMC_BWTR3_DATAST_Pos (8U)

◆ FMC_BWTR3_DATLAT

#define FMC_BWTR3_DATLAT FMC_BWTR3_DATLAT_Msk

DATLA[3:0] bits (Data latency)

◆ FMC_BWTR3_DATLAT_0

#define FMC_BWTR3_DATLAT_0 (0x1UL << FMC_BWTR3_DATLAT_Pos)

0x01000000

◆ FMC_BWTR3_DATLAT_1

#define FMC_BWTR3_DATLAT_1 (0x2UL << FMC_BWTR3_DATLAT_Pos)

0x02000000

◆ FMC_BWTR3_DATLAT_2

#define FMC_BWTR3_DATLAT_2 (0x4UL << FMC_BWTR3_DATLAT_Pos)

0x04000000

◆ FMC_BWTR3_DATLAT_3

#define FMC_BWTR3_DATLAT_3 (0x8UL << FMC_BWTR3_DATLAT_Pos)

0x08000000

◆ FMC_BWTR3_DATLAT_Msk

#define FMC_BWTR3_DATLAT_Msk (0xFUL << FMC_BWTR3_DATLAT_Pos)

0x0F000000

◆ FMC_BWTR3_DATLAT_Pos

#define FMC_BWTR3_DATLAT_Pos (24U)

◆ FMC_BWTR4_ACCMOD

#define FMC_BWTR4_ACCMOD FMC_BWTR4_ACCMOD_Msk

ACCMOD[1:0] bits (Access mode)

◆ FMC_BWTR4_ACCMOD_0

#define FMC_BWTR4_ACCMOD_0 (0x1UL << FMC_BWTR4_ACCMOD_Pos)

0x10000000

◆ FMC_BWTR4_ACCMOD_1

#define FMC_BWTR4_ACCMOD_1 (0x2UL << FMC_BWTR4_ACCMOD_Pos)

0x20000000

◆ FMC_BWTR4_ACCMOD_Msk

#define FMC_BWTR4_ACCMOD_Msk (0x3UL << FMC_BWTR4_ACCMOD_Pos)

0x30000000

◆ FMC_BWTR4_ACCMOD_Pos

#define FMC_BWTR4_ACCMOD_Pos (28U)

◆ FMC_BWTR4_ADDHLD

#define FMC_BWTR4_ADDHLD FMC_BWTR4_ADDHLD_Msk

ADDHLD[3:0] bits (Address-hold phase duration)

◆ FMC_BWTR4_ADDHLD_0

#define FMC_BWTR4_ADDHLD_0 (0x1UL << FMC_BWTR4_ADDHLD_Pos)

0x00000010

◆ FMC_BWTR4_ADDHLD_1

#define FMC_BWTR4_ADDHLD_1 (0x2UL << FMC_BWTR4_ADDHLD_Pos)

0x00000020

◆ FMC_BWTR4_ADDHLD_2

#define FMC_BWTR4_ADDHLD_2 (0x4UL << FMC_BWTR4_ADDHLD_Pos)

0x00000040

◆ FMC_BWTR4_ADDHLD_3

#define FMC_BWTR4_ADDHLD_3 (0x8UL << FMC_BWTR4_ADDHLD_Pos)

0x00000080

◆ FMC_BWTR4_ADDHLD_Msk

#define FMC_BWTR4_ADDHLD_Msk (0xFUL << FMC_BWTR4_ADDHLD_Pos)

0x000000F0

◆ FMC_BWTR4_ADDHLD_Pos

#define FMC_BWTR4_ADDHLD_Pos (4U)

◆ FMC_BWTR4_ADDSET

#define FMC_BWTR4_ADDSET FMC_BWTR4_ADDSET_Msk

ADDSET[3:0] bits (Address setup phase duration)

◆ FMC_BWTR4_ADDSET_0

#define FMC_BWTR4_ADDSET_0 (0x1UL << FMC_BWTR4_ADDSET_Pos)

0x00000001

◆ FMC_BWTR4_ADDSET_1

#define FMC_BWTR4_ADDSET_1 (0x2UL << FMC_BWTR4_ADDSET_Pos)

0x00000002

◆ FMC_BWTR4_ADDSET_2

#define FMC_BWTR4_ADDSET_2 (0x4UL << FMC_BWTR4_ADDSET_Pos)

0x00000004

◆ FMC_BWTR4_ADDSET_3

#define FMC_BWTR4_ADDSET_3 (0x8UL << FMC_BWTR4_ADDSET_Pos)

0x00000008

◆ FMC_BWTR4_ADDSET_Msk

#define FMC_BWTR4_ADDSET_Msk (0xFUL << FMC_BWTR4_ADDSET_Pos)

0x0000000F

◆ FMC_BWTR4_ADDSET_Pos

#define FMC_BWTR4_ADDSET_Pos (0U)

◆ FMC_BWTR4_CLKDIV

#define FMC_BWTR4_CLKDIV FMC_BWTR4_CLKDIV_Msk

CLKDIV[3:0] bits (Clock divide ratio)

◆ FMC_BWTR4_CLKDIV_0

#define FMC_BWTR4_CLKDIV_0 (0x1UL << FMC_BWTR4_CLKDIV_Pos)

0x00100000

◆ FMC_BWTR4_CLKDIV_1

#define FMC_BWTR4_CLKDIV_1 (0x2UL << FMC_BWTR4_CLKDIV_Pos)

0x00200000

◆ FMC_BWTR4_CLKDIV_2

#define FMC_BWTR4_CLKDIV_2 (0x4UL << FMC_BWTR4_CLKDIV_Pos)

0x00400000

◆ FMC_BWTR4_CLKDIV_3

#define FMC_BWTR4_CLKDIV_3 (0x8UL << FMC_BWTR4_CLKDIV_Pos)

0x00800000

◆ FMC_BWTR4_CLKDIV_Msk

#define FMC_BWTR4_CLKDIV_Msk (0xFUL << FMC_BWTR4_CLKDIV_Pos)

0x00F00000

◆ FMC_BWTR4_CLKDIV_Pos

#define FMC_BWTR4_CLKDIV_Pos (20U)

◆ FMC_BWTR4_DATAST

#define FMC_BWTR4_DATAST FMC_BWTR4_DATAST_Msk

DATAST [3:0] bits (Data-phase duration)

◆ FMC_BWTR4_DATAST_0

#define FMC_BWTR4_DATAST_0 (0x01UL << FMC_BWTR4_DATAST_Pos)

0x00000100

◆ FMC_BWTR4_DATAST_1

#define FMC_BWTR4_DATAST_1 (0x02UL << FMC_BWTR4_DATAST_Pos)

0x00000200

◆ FMC_BWTR4_DATAST_2

#define FMC_BWTR4_DATAST_2 (0x04UL << FMC_BWTR4_DATAST_Pos)

0x00000400

◆ FMC_BWTR4_DATAST_3

#define FMC_BWTR4_DATAST_3 (0x08UL << FMC_BWTR4_DATAST_Pos)

0x00000800

◆ FMC_BWTR4_DATAST_4

#define FMC_BWTR4_DATAST_4 (0x10UL << FMC_BWTR4_DATAST_Pos)

0x00001000

◆ FMC_BWTR4_DATAST_5

#define FMC_BWTR4_DATAST_5 (0x20UL << FMC_BWTR4_DATAST_Pos)

0x00002000

◆ FMC_BWTR4_DATAST_6

#define FMC_BWTR4_DATAST_6 (0x40UL << FMC_BWTR4_DATAST_Pos)

0x00004000

◆ FMC_BWTR4_DATAST_7

#define FMC_BWTR4_DATAST_7 (0x80UL << FMC_BWTR4_DATAST_Pos)

0x00008000

◆ FMC_BWTR4_DATAST_Msk

#define FMC_BWTR4_DATAST_Msk (0xFFUL << FMC_BWTR4_DATAST_Pos)

0x0000FF00

◆ FMC_BWTR4_DATAST_Pos

#define FMC_BWTR4_DATAST_Pos (8U)

◆ FMC_BWTR4_DATLAT

#define FMC_BWTR4_DATLAT FMC_BWTR4_DATLAT_Msk

DATLA[3:0] bits (Data latency)

◆ FMC_BWTR4_DATLAT_0

#define FMC_BWTR4_DATLAT_0 (0x1UL << FMC_BWTR4_DATLAT_Pos)

0x01000000

◆ FMC_BWTR4_DATLAT_1

#define FMC_BWTR4_DATLAT_1 (0x2UL << FMC_BWTR4_DATLAT_Pos)

0x02000000

◆ FMC_BWTR4_DATLAT_2

#define FMC_BWTR4_DATLAT_2 (0x4UL << FMC_BWTR4_DATLAT_Pos)

0x04000000

◆ FMC_BWTR4_DATLAT_3

#define FMC_BWTR4_DATLAT_3 (0x8UL << FMC_BWTR4_DATLAT_Pos)

0x08000000

◆ FMC_BWTR4_DATLAT_Msk

#define FMC_BWTR4_DATLAT_Msk (0xFUL << FMC_BWTR4_DATLAT_Pos)

0x0F000000

◆ FMC_BWTR4_DATLAT_Pos

#define FMC_BWTR4_DATLAT_Pos (24U)

◆ FMC_BWTRx_ACCMOD

#define FMC_BWTRx_ACCMOD FMC_BWTRx_ACCMOD_Msk

ACCMOD[1:0] bits (Access mode)

◆ FMC_BWTRx_ACCMOD_0

#define FMC_BWTRx_ACCMOD_0 (0x1UL << FMC_BWTRx_ACCMOD_Pos)

0x10000000

◆ FMC_BWTRx_ACCMOD_1

#define FMC_BWTRx_ACCMOD_1 (0x2UL << FMC_BWTRx_ACCMOD_Pos)

0x20000000

◆ FMC_BWTRx_ACCMOD_Msk

#define FMC_BWTRx_ACCMOD_Msk (0x3UL << FMC_BWTRx_ACCMOD_Pos)

0x30000000

◆ FMC_BWTRx_ACCMOD_Pos

#define FMC_BWTRx_ACCMOD_Pos (28U)

◆ FMC_BWTRx_ACCMODx

#define FMC_BWTRx_ACCMODx FMC_BWTRx_ACCMOD

◆ FMC_BWTRx_ACCMODx_0

#define FMC_BWTRx_ACCMODx_0 FMC_BWTRx_ACCMOD_0

◆ FMC_BWTRx_ACCMODx_1

#define FMC_BWTRx_ACCMODx_1 FMC_BWTRx_ACCMOD_1

◆ FMC_BWTRx_ADDHLD

#define FMC_BWTRx_ADDHLD FMC_BWTRx_ADDHLD_Msk

ADDHLD[3:0] bits (Address-hold phase duration)

◆ FMC_BWTRx_ADDHLD_0

#define FMC_BWTRx_ADDHLD_0 (0x1UL << FMC_BWTRx_ADDHLD_Pos)

0x00000010

◆ FMC_BWTRx_ADDHLD_1

#define FMC_BWTRx_ADDHLD_1 (0x2UL << FMC_BWTRx_ADDHLD_Pos)

0x00000020

◆ FMC_BWTRx_ADDHLD_2

#define FMC_BWTRx_ADDHLD_2 (0x4UL << FMC_BWTRx_ADDHLD_Pos)

0x00000040

◆ FMC_BWTRx_ADDHLD_3

#define FMC_BWTRx_ADDHLD_3 (0x8UL << FMC_BWTRx_ADDHLD_Pos)

0x00000080

◆ FMC_BWTRx_ADDHLD_Msk

#define FMC_BWTRx_ADDHLD_Msk (0xFUL << FMC_BWTRx_ADDHLD_Pos)

0x000000F0

◆ FMC_BWTRx_ADDHLD_Pos

#define FMC_BWTRx_ADDHLD_Pos (4U)

◆ FMC_BWTRx_ADDHLDx

#define FMC_BWTRx_ADDHLDx FMC_BWTRx_ADDHLD

◆ FMC_BWTRx_ADDHLDx_0

#define FMC_BWTRx_ADDHLDx_0 FMC_BWTRx_ADDHLD_0

◆ FMC_BWTRx_ADDHLDx_1

#define FMC_BWTRx_ADDHLDx_1 FMC_BWTRx_ADDHLD_1

◆ FMC_BWTRx_ADDHLDx_2

#define FMC_BWTRx_ADDHLDx_2 FMC_BWTRx_ADDHLD_2

◆ FMC_BWTRx_ADDHLDx_3

#define FMC_BWTRx_ADDHLDx_3 FMC_BWTRx_ADDHLD_3

◆ FMC_BWTRx_ADDSET

#define FMC_BWTRx_ADDSET FMC_BWTRx_ADDSET_Msk

ADDSET[3:0] bits (Address setup phase duration)

◆ FMC_BWTRx_ADDSET_0

#define FMC_BWTRx_ADDSET_0 (0x1UL << FMC_BWTRx_ADDSET_Pos)

0x00000001

◆ FMC_BWTRx_ADDSET_1

#define FMC_BWTRx_ADDSET_1 (0x2UL << FMC_BWTRx_ADDSET_Pos)

0x00000002

◆ FMC_BWTRx_ADDSET_2

#define FMC_BWTRx_ADDSET_2 (0x4UL << FMC_BWTRx_ADDSET_Pos)

0x00000004

◆ FMC_BWTRx_ADDSET_3

#define FMC_BWTRx_ADDSET_3 (0x8UL << FMC_BWTRx_ADDSET_Pos)

0x00000008

◆ FMC_BWTRx_ADDSET_Msk

#define FMC_BWTRx_ADDSET_Msk (0xFUL << FMC_BWTRx_ADDSET_Pos)

0x0000000F

◆ FMC_BWTRx_ADDSET_Pos

#define FMC_BWTRx_ADDSET_Pos (0U)

◆ FMC_BWTRx_ADDSETx

#define FMC_BWTRx_ADDSETx FMC_BWTRx_ADDSET

◆ FMC_BWTRx_ADDSETx_0

#define FMC_BWTRx_ADDSETx_0 FMC_BWTRx_ADDSET_0

◆ FMC_BWTRx_ADDSETx_1

#define FMC_BWTRx_ADDSETx_1 FMC_BWTRx_ADDSET_1

◆ FMC_BWTRx_ADDSETx_2

#define FMC_BWTRx_ADDSETx_2 FMC_BWTRx_ADDSET_2

◆ FMC_BWTRx_ADDSETx_3

#define FMC_BWTRx_ADDSETx_3 FMC_BWTRx_ADDSET_3

◆ FMC_BWTRx_DATAST

#define FMC_BWTRx_DATAST FMC_BWTRx_DATAST_Msk

DATAST [3:0] bits (Data-phase duration)

◆ FMC_BWTRx_DATAST_0

#define FMC_BWTRx_DATAST_0 (0x01UL << FMC_BWTRx_DATAST_Pos)

0x00000100

◆ FMC_BWTRx_DATAST_1

#define FMC_BWTRx_DATAST_1 (0x02UL << FMC_BWTRx_DATAST_Pos)

0x00000200

◆ FMC_BWTRx_DATAST_2

#define FMC_BWTRx_DATAST_2 (0x04UL << FMC_BWTRx_DATAST_Pos)

0x00000400

◆ FMC_BWTRx_DATAST_3

#define FMC_BWTRx_DATAST_3 (0x08UL << FMC_BWTRx_DATAST_Pos)

0x00000800

◆ FMC_BWTRx_DATAST_4

#define FMC_BWTRx_DATAST_4 (0x10UL << FMC_BWTRx_DATAST_Pos)

0x00001000

◆ FMC_BWTRx_DATAST_5

#define FMC_BWTRx_DATAST_5 (0x20UL << FMC_BWTRx_DATAST_Pos)

0x00002000

◆ FMC_BWTRx_DATAST_6

#define FMC_BWTRx_DATAST_6 (0x40UL << FMC_BWTRx_DATAST_Pos)

0x00004000

◆ FMC_BWTRx_DATAST_7

#define FMC_BWTRx_DATAST_7 (0x80UL << FMC_BWTRx_DATAST_Pos)

0x00008000

◆ FMC_BWTRx_DATAST_Msk

#define FMC_BWTRx_DATAST_Msk (0xFFUL << FMC_BWTRx_DATAST_Pos)

0x0000FF00

◆ FMC_BWTRx_DATAST_Pos

#define FMC_BWTRx_DATAST_Pos (8U)

◆ FMC_BWTRx_DATASTx

#define FMC_BWTRx_DATASTx FMC_BWTRx_DATAST

◆ FMC_BWTRx_DATASTx_0

#define FMC_BWTRx_DATASTx_0 FMC_BWTRx_DATAST_0

◆ FMC_BWTRx_DATASTx_1

#define FMC_BWTRx_DATASTx_1 FMC_BWTRx_DATAST_1

◆ FMC_BWTRx_DATASTx_2

#define FMC_BWTRx_DATASTx_2 FMC_BWTRx_DATAST_2

◆ FMC_BWTRx_DATASTx_3

#define FMC_BWTRx_DATASTx_3 FMC_BWTRx_DATAST_3

◆ FMC_BWTRx_DATASTx_4

#define FMC_BWTRx_DATASTx_4 FMC_BWTRx_DATAST_4

◆ FMC_BWTRx_DATASTx_5

#define FMC_BWTRx_DATASTx_5 FMC_BWTRx_DATAST_5

◆ FMC_BWTRx_DATASTx_6

#define FMC_BWTRx_DATASTx_6 FMC_BWTRx_DATAST_6

◆ FMC_BWTRx_DATASTx_7

#define FMC_BWTRx_DATASTx_7 FMC_BWTRx_DATAST_7

◆ FMC_ECCR2_ECC2

#define FMC_ECCR2_ECC2 FMC_ECCR2_ECC2_Msk

ECC result

◆ FMC_ECCR2_ECC2_Msk

#define FMC_ECCR2_ECC2_Msk (0xFFFFFFFFUL << FMC_ECCR2_ECC2_Pos)

0xFFFFFFFF

◆ FMC_ECCR2_ECC2_Pos

#define FMC_ECCR2_ECC2_Pos (0U)

◆ FMC_ECCR3_ECC3

#define FMC_ECCR3_ECC3 FMC_ECCR3_ECC3_Msk

ECC result

◆ FMC_ECCR3_ECC3_Msk

#define FMC_ECCR3_ECC3_Msk (0xFFFFFFFFUL << FMC_ECCR3_ECC3_Pos)

0xFFFFFFFF

◆ FMC_ECCR3_ECC3_Pos

#define FMC_ECCR3_ECC3_Pos (0U)

◆ FMC_PATT2_ATTHIZ2

#define FMC_PATT2_ATTHIZ2 FMC_PATT2_ATTHIZ2_Msk

ATTHIZ2[7:0] bits (Attribute memory 2 databus HiZ time)

◆ FMC_PATT2_ATTHIZ2_0

#define FMC_PATT2_ATTHIZ2_0 (0x01UL << FMC_PATT2_ATTHIZ2_Pos)

0x01000000

◆ FMC_PATT2_ATTHIZ2_1

#define FMC_PATT2_ATTHIZ2_1 (0x02UL << FMC_PATT2_ATTHIZ2_Pos)

0x02000000

◆ FMC_PATT2_ATTHIZ2_2

#define FMC_PATT2_ATTHIZ2_2 (0x04UL << FMC_PATT2_ATTHIZ2_Pos)

0x04000000

◆ FMC_PATT2_ATTHIZ2_3

#define FMC_PATT2_ATTHIZ2_3 (0x08UL << FMC_PATT2_ATTHIZ2_Pos)

0x08000000

◆ FMC_PATT2_ATTHIZ2_4

#define FMC_PATT2_ATTHIZ2_4 (0x10UL << FMC_PATT2_ATTHIZ2_Pos)

0x10000000

◆ FMC_PATT2_ATTHIZ2_5

#define FMC_PATT2_ATTHIZ2_5 (0x20UL << FMC_PATT2_ATTHIZ2_Pos)

0x20000000

◆ FMC_PATT2_ATTHIZ2_6

#define FMC_PATT2_ATTHIZ2_6 (0x40UL << FMC_PATT2_ATTHIZ2_Pos)

0x40000000

◆ FMC_PATT2_ATTHIZ2_7

#define FMC_PATT2_ATTHIZ2_7 (0x80UL << FMC_PATT2_ATTHIZ2_Pos)

0x80000000

◆ FMC_PATT2_ATTHIZ2_Msk

#define FMC_PATT2_ATTHIZ2_Msk (0xFFUL << FMC_PATT2_ATTHIZ2_Pos)

0xFF000000

◆ FMC_PATT2_ATTHIZ2_Pos

#define FMC_PATT2_ATTHIZ2_Pos (24U)

◆ FMC_PATT2_ATTHOLD2

#define FMC_PATT2_ATTHOLD2 FMC_PATT2_ATTHOLD2_Msk

ATTHOLD2[7:0] bits (Attribute memory 2 hold time)

◆ FMC_PATT2_ATTHOLD2_0

#define FMC_PATT2_ATTHOLD2_0 (0x01UL << FMC_PATT2_ATTHOLD2_Pos)

0x00010000

◆ FMC_PATT2_ATTHOLD2_1

#define FMC_PATT2_ATTHOLD2_1 (0x02UL << FMC_PATT2_ATTHOLD2_Pos)

0x00020000

◆ FMC_PATT2_ATTHOLD2_2

#define FMC_PATT2_ATTHOLD2_2 (0x04UL << FMC_PATT2_ATTHOLD2_Pos)

0x00040000

◆ FMC_PATT2_ATTHOLD2_3

#define FMC_PATT2_ATTHOLD2_3 (0x08UL << FMC_PATT2_ATTHOLD2_Pos)

0x00080000

◆ FMC_PATT2_ATTHOLD2_4

#define FMC_PATT2_ATTHOLD2_4 (0x10UL << FMC_PATT2_ATTHOLD2_Pos)

0x00100000

◆ FMC_PATT2_ATTHOLD2_5

#define FMC_PATT2_ATTHOLD2_5 (0x20UL << FMC_PATT2_ATTHOLD2_Pos)

0x00200000

◆ FMC_PATT2_ATTHOLD2_6

#define FMC_PATT2_ATTHOLD2_6 (0x40UL << FMC_PATT2_ATTHOLD2_Pos)

0x00400000

◆ FMC_PATT2_ATTHOLD2_7

#define FMC_PATT2_ATTHOLD2_7 (0x80UL << FMC_PATT2_ATTHOLD2_Pos)

0x00800000

◆ FMC_PATT2_ATTHOLD2_Msk

#define FMC_PATT2_ATTHOLD2_Msk (0xFFUL << FMC_PATT2_ATTHOLD2_Pos)

0x00FF0000

◆ FMC_PATT2_ATTHOLD2_Pos

#define FMC_PATT2_ATTHOLD2_Pos (16U)

◆ FMC_PATT2_ATTSET2

#define FMC_PATT2_ATTSET2 FMC_PATT2_ATTSET2_Msk

ATTSET2[7:0] bits (Attribute memory 2 setup time)

◆ FMC_PATT2_ATTSET2_0

#define FMC_PATT2_ATTSET2_0 (0x01UL << FMC_PATT2_ATTSET2_Pos)

0x00000001

◆ FMC_PATT2_ATTSET2_1

#define FMC_PATT2_ATTSET2_1 (0x02UL << FMC_PATT2_ATTSET2_Pos)

0x00000002

◆ FMC_PATT2_ATTSET2_2

#define FMC_PATT2_ATTSET2_2 (0x04UL << FMC_PATT2_ATTSET2_Pos)

0x00000004

◆ FMC_PATT2_ATTSET2_3

#define FMC_PATT2_ATTSET2_3 (0x08UL << FMC_PATT2_ATTSET2_Pos)

0x00000008

◆ FMC_PATT2_ATTSET2_4

#define FMC_PATT2_ATTSET2_4 (0x10UL << FMC_PATT2_ATTSET2_Pos)

0x00000010

◆ FMC_PATT2_ATTSET2_5

#define FMC_PATT2_ATTSET2_5 (0x20UL << FMC_PATT2_ATTSET2_Pos)

0x00000020

◆ FMC_PATT2_ATTSET2_6

#define FMC_PATT2_ATTSET2_6 (0x40UL << FMC_PATT2_ATTSET2_Pos)

0x00000040

◆ FMC_PATT2_ATTSET2_7

#define FMC_PATT2_ATTSET2_7 (0x80UL << FMC_PATT2_ATTSET2_Pos)

0x00000080

◆ FMC_PATT2_ATTSET2_Msk

#define FMC_PATT2_ATTSET2_Msk (0xFFUL << FMC_PATT2_ATTSET2_Pos)

0x000000FF

◆ FMC_PATT2_ATTSET2_Pos

#define FMC_PATT2_ATTSET2_Pos (0U)

◆ FMC_PATT2_ATTWAIT2

#define FMC_PATT2_ATTWAIT2 FMC_PATT2_ATTWAIT2_Msk

ATTWAIT2[7:0] bits (Attribute memory 2 wait time)

◆ FMC_PATT2_ATTWAIT2_0

#define FMC_PATT2_ATTWAIT2_0 (0x01UL << FMC_PATT2_ATTWAIT2_Pos)

0x00000100

◆ FMC_PATT2_ATTWAIT2_1

#define FMC_PATT2_ATTWAIT2_1 (0x02UL << FMC_PATT2_ATTWAIT2_Pos)

0x00000200

◆ FMC_PATT2_ATTWAIT2_2

#define FMC_PATT2_ATTWAIT2_2 (0x04UL << FMC_PATT2_ATTWAIT2_Pos)

0x00000400

◆ FMC_PATT2_ATTWAIT2_3

#define FMC_PATT2_ATTWAIT2_3 (0x08UL << FMC_PATT2_ATTWAIT2_Pos)

0x00000800

◆ FMC_PATT2_ATTWAIT2_4

#define FMC_PATT2_ATTWAIT2_4 (0x10UL << FMC_PATT2_ATTWAIT2_Pos)

0x00001000

◆ FMC_PATT2_ATTWAIT2_5

#define FMC_PATT2_ATTWAIT2_5 (0x20UL << FMC_PATT2_ATTWAIT2_Pos)

0x00002000

◆ FMC_PATT2_ATTWAIT2_6

#define FMC_PATT2_ATTWAIT2_6 (0x40UL << FMC_PATT2_ATTWAIT2_Pos)

0x00004000

◆ FMC_PATT2_ATTWAIT2_7

#define FMC_PATT2_ATTWAIT2_7 (0x80UL << FMC_PATT2_ATTWAIT2_Pos)

0x00008000

◆ FMC_PATT2_ATTWAIT2_Msk

#define FMC_PATT2_ATTWAIT2_Msk (0xFFUL << FMC_PATT2_ATTWAIT2_Pos)

0x0000FF00

◆ FMC_PATT2_ATTWAIT2_Pos

#define FMC_PATT2_ATTWAIT2_Pos (8U)

◆ FMC_PATT3_ATTHIZ3

#define FMC_PATT3_ATTHIZ3 FMC_PATT3_ATTHIZ3_Msk

ATTHIZ3[7:0] bits (Attribute memory 3 databus HiZ time)

◆ FMC_PATT3_ATTHIZ3_0

#define FMC_PATT3_ATTHIZ3_0 (0x01UL << FMC_PATT3_ATTHIZ3_Pos)

0x01000000

◆ FMC_PATT3_ATTHIZ3_1

#define FMC_PATT3_ATTHIZ3_1 (0x02UL << FMC_PATT3_ATTHIZ3_Pos)

0x02000000

◆ FMC_PATT3_ATTHIZ3_2

#define FMC_PATT3_ATTHIZ3_2 (0x04UL << FMC_PATT3_ATTHIZ3_Pos)

0x04000000

◆ FMC_PATT3_ATTHIZ3_3

#define FMC_PATT3_ATTHIZ3_3 (0x08UL << FMC_PATT3_ATTHIZ3_Pos)

0x08000000

◆ FMC_PATT3_ATTHIZ3_4

#define FMC_PATT3_ATTHIZ3_4 (0x10UL << FMC_PATT3_ATTHIZ3_Pos)

0x10000000

◆ FMC_PATT3_ATTHIZ3_5

#define FMC_PATT3_ATTHIZ3_5 (0x20UL << FMC_PATT3_ATTHIZ3_Pos)

0x20000000

◆ FMC_PATT3_ATTHIZ3_6

#define FMC_PATT3_ATTHIZ3_6 (0x40UL << FMC_PATT3_ATTHIZ3_Pos)

0x40000000

◆ FMC_PATT3_ATTHIZ3_7

#define FMC_PATT3_ATTHIZ3_7 (0x80UL << FMC_PATT3_ATTHIZ3_Pos)

0x80000000

◆ FMC_PATT3_ATTHIZ3_Msk

#define FMC_PATT3_ATTHIZ3_Msk (0xFFUL << FMC_PATT3_ATTHIZ3_Pos)

0xFF000000

◆ FMC_PATT3_ATTHIZ3_Pos

#define FMC_PATT3_ATTHIZ3_Pos (24U)

◆ FMC_PATT3_ATTHOLD3

#define FMC_PATT3_ATTHOLD3 FMC_PATT3_ATTHOLD3_Msk

ATTHOLD3[7:0] bits (Attribute memory 3 hold time)

◆ FMC_PATT3_ATTHOLD3_0

#define FMC_PATT3_ATTHOLD3_0 (0x01UL << FMC_PATT3_ATTHOLD3_Pos)

0x00010000

◆ FMC_PATT3_ATTHOLD3_1

#define FMC_PATT3_ATTHOLD3_1 (0x02UL << FMC_PATT3_ATTHOLD3_Pos)

0x00020000

◆ FMC_PATT3_ATTHOLD3_2

#define FMC_PATT3_ATTHOLD3_2 (0x04UL << FMC_PATT3_ATTHOLD3_Pos)

0x00040000

◆ FMC_PATT3_ATTHOLD3_3

#define FMC_PATT3_ATTHOLD3_3 (0x08UL << FMC_PATT3_ATTHOLD3_Pos)

0x00080000

◆ FMC_PATT3_ATTHOLD3_4

#define FMC_PATT3_ATTHOLD3_4 (0x10UL << FMC_PATT3_ATTHOLD3_Pos)

0x00100000

◆ FMC_PATT3_ATTHOLD3_5

#define FMC_PATT3_ATTHOLD3_5 (0x20UL << FMC_PATT3_ATTHOLD3_Pos)

0x00200000

◆ FMC_PATT3_ATTHOLD3_6

#define FMC_PATT3_ATTHOLD3_6 (0x40UL << FMC_PATT3_ATTHOLD3_Pos)

0x00400000

◆ FMC_PATT3_ATTHOLD3_7

#define FMC_PATT3_ATTHOLD3_7 (0x80UL << FMC_PATT3_ATTHOLD3_Pos)

0x00800000

◆ FMC_PATT3_ATTHOLD3_Msk

#define FMC_PATT3_ATTHOLD3_Msk (0xFFUL << FMC_PATT3_ATTHOLD3_Pos)

0x00FF0000

◆ FMC_PATT3_ATTHOLD3_Pos

#define FMC_PATT3_ATTHOLD3_Pos (16U)

◆ FMC_PATT3_ATTSET3

#define FMC_PATT3_ATTSET3 FMC_PATT3_ATTSET3_Msk

ATTSET3[7:0] bits (Attribute memory 3 setup time)

◆ FMC_PATT3_ATTSET3_0

#define FMC_PATT3_ATTSET3_0 (0x01UL << FMC_PATT3_ATTSET3_Pos)

0x00000001

◆ FMC_PATT3_ATTSET3_1

#define FMC_PATT3_ATTSET3_1 (0x02UL << FMC_PATT3_ATTSET3_Pos)

0x00000002

◆ FMC_PATT3_ATTSET3_2

#define FMC_PATT3_ATTSET3_2 (0x04UL << FMC_PATT3_ATTSET3_Pos)

0x00000004

◆ FMC_PATT3_ATTSET3_3

#define FMC_PATT3_ATTSET3_3 (0x08UL << FMC_PATT3_ATTSET3_Pos)

0x00000008

◆ FMC_PATT3_ATTSET3_4

#define FMC_PATT3_ATTSET3_4 (0x10UL << FMC_PATT3_ATTSET3_Pos)

0x00000010

◆ FMC_PATT3_ATTSET3_5

#define FMC_PATT3_ATTSET3_5 (0x20UL << FMC_PATT3_ATTSET3_Pos)

0x00000020

◆ FMC_PATT3_ATTSET3_6

#define FMC_PATT3_ATTSET3_6 (0x40UL << FMC_PATT3_ATTSET3_Pos)

0x00000040

◆ FMC_PATT3_ATTSET3_7

#define FMC_PATT3_ATTSET3_7 (0x80UL << FMC_PATT3_ATTSET3_Pos)

0x00000080

◆ FMC_PATT3_ATTSET3_Msk

#define FMC_PATT3_ATTSET3_Msk (0xFFUL << FMC_PATT3_ATTSET3_Pos)

0x000000FF

◆ FMC_PATT3_ATTSET3_Pos

#define FMC_PATT3_ATTSET3_Pos (0U)

◆ FMC_PATT3_ATTWAIT3

#define FMC_PATT3_ATTWAIT3 FMC_PATT3_ATTWAIT3_Msk

ATTWAIT3[7:0] bits (Attribute memory 3 wait time)

◆ FMC_PATT3_ATTWAIT3_0

#define FMC_PATT3_ATTWAIT3_0 (0x01UL << FMC_PATT3_ATTWAIT3_Pos)

0x00000100

◆ FMC_PATT3_ATTWAIT3_1

#define FMC_PATT3_ATTWAIT3_1 (0x02UL << FMC_PATT3_ATTWAIT3_Pos)

0x00000200

◆ FMC_PATT3_ATTWAIT3_2

#define FMC_PATT3_ATTWAIT3_2 (0x04UL << FMC_PATT3_ATTWAIT3_Pos)

0x00000400

◆ FMC_PATT3_ATTWAIT3_3

#define FMC_PATT3_ATTWAIT3_3 (0x08UL << FMC_PATT3_ATTWAIT3_Pos)

0x00000800

◆ FMC_PATT3_ATTWAIT3_4

#define FMC_PATT3_ATTWAIT3_4 (0x10UL << FMC_PATT3_ATTWAIT3_Pos)

0x00001000

◆ FMC_PATT3_ATTWAIT3_5

#define FMC_PATT3_ATTWAIT3_5 (0x20UL << FMC_PATT3_ATTWAIT3_Pos)

0x00002000

◆ FMC_PATT3_ATTWAIT3_6

#define FMC_PATT3_ATTWAIT3_6 (0x40UL << FMC_PATT3_ATTWAIT3_Pos)

0x00004000

◆ FMC_PATT3_ATTWAIT3_7

#define FMC_PATT3_ATTWAIT3_7 (0x80UL << FMC_PATT3_ATTWAIT3_Pos)

0x00008000

◆ FMC_PATT3_ATTWAIT3_Msk

#define FMC_PATT3_ATTWAIT3_Msk (0xFFUL << FMC_PATT3_ATTWAIT3_Pos)

0x0000FF00

◆ FMC_PATT3_ATTWAIT3_Pos

#define FMC_PATT3_ATTWAIT3_Pos (8U)

◆ FMC_PATT4_ATTHIZ4

#define FMC_PATT4_ATTHIZ4 FMC_PATT4_ATTHIZ4_Msk

ATTHIZ4[7:0] bits (Attribute memory 4 databus HiZ time)

◆ FMC_PATT4_ATTHIZ4_0

#define FMC_PATT4_ATTHIZ4_0 (0x01UL << FMC_PATT4_ATTHIZ4_Pos)

0x01000000

◆ FMC_PATT4_ATTHIZ4_1

#define FMC_PATT4_ATTHIZ4_1 (0x02UL << FMC_PATT4_ATTHIZ4_Pos)

0x02000000

◆ FMC_PATT4_ATTHIZ4_2

#define FMC_PATT4_ATTHIZ4_2 (0x04UL << FMC_PATT4_ATTHIZ4_Pos)

0x04000000

◆ FMC_PATT4_ATTHIZ4_3

#define FMC_PATT4_ATTHIZ4_3 (0x08UL << FMC_PATT4_ATTHIZ4_Pos)

0x08000000

◆ FMC_PATT4_ATTHIZ4_4

#define FMC_PATT4_ATTHIZ4_4 (0x10UL << FMC_PATT4_ATTHIZ4_Pos)

0x10000000

◆ FMC_PATT4_ATTHIZ4_5

#define FMC_PATT4_ATTHIZ4_5 (0x20UL << FMC_PATT4_ATTHIZ4_Pos)

0x20000000

◆ FMC_PATT4_ATTHIZ4_6

#define FMC_PATT4_ATTHIZ4_6 (0x40UL << FMC_PATT4_ATTHIZ4_Pos)

0x40000000

◆ FMC_PATT4_ATTHIZ4_7

#define FMC_PATT4_ATTHIZ4_7 (0x80UL << FMC_PATT4_ATTHIZ4_Pos)

0x80000000

◆ FMC_PATT4_ATTHIZ4_Msk

#define FMC_PATT4_ATTHIZ4_Msk (0xFFUL << FMC_PATT4_ATTHIZ4_Pos)

0xFF000000

◆ FMC_PATT4_ATTHIZ4_Pos

#define FMC_PATT4_ATTHIZ4_Pos (24U)

◆ FMC_PATT4_ATTHOLD4

#define FMC_PATT4_ATTHOLD4 FMC_PATT4_ATTHOLD4_Msk

ATTHOLD4[7:0] bits (Attribute memory 4 hold time)

◆ FMC_PATT4_ATTHOLD4_0

#define FMC_PATT4_ATTHOLD4_0 (0x01UL << FMC_PATT4_ATTHOLD4_Pos)

0x00010000

◆ FMC_PATT4_ATTHOLD4_1

#define FMC_PATT4_ATTHOLD4_1 (0x02UL << FMC_PATT4_ATTHOLD4_Pos)

0x00020000

◆ FMC_PATT4_ATTHOLD4_2

#define FMC_PATT4_ATTHOLD4_2 (0x04UL << FMC_PATT4_ATTHOLD4_Pos)

0x00040000

◆ FMC_PATT4_ATTHOLD4_3

#define FMC_PATT4_ATTHOLD4_3 (0x08UL << FMC_PATT4_ATTHOLD4_Pos)

0x00080000

◆ FMC_PATT4_ATTHOLD4_4

#define FMC_PATT4_ATTHOLD4_4 (0x10UL << FMC_PATT4_ATTHOLD4_Pos)

0x00100000

◆ FMC_PATT4_ATTHOLD4_5

#define FMC_PATT4_ATTHOLD4_5 (0x20UL << FMC_PATT4_ATTHOLD4_Pos)

0x00200000

◆ FMC_PATT4_ATTHOLD4_6

#define FMC_PATT4_ATTHOLD4_6 (0x40UL << FMC_PATT4_ATTHOLD4_Pos)

0x00400000

◆ FMC_PATT4_ATTHOLD4_7

#define FMC_PATT4_ATTHOLD4_7 (0x80UL << FMC_PATT4_ATTHOLD4_Pos)

0x00800000

◆ FMC_PATT4_ATTHOLD4_Msk

#define FMC_PATT4_ATTHOLD4_Msk (0xFFUL << FMC_PATT4_ATTHOLD4_Pos)

0x00FF0000

◆ FMC_PATT4_ATTHOLD4_Pos

#define FMC_PATT4_ATTHOLD4_Pos (16U)

◆ FMC_PATT4_ATTSET4

#define FMC_PATT4_ATTSET4 FMC_PATT4_ATTSET4_Msk

ATTSET4[7:0] bits (Attribute memory 4 setup time)

◆ FMC_PATT4_ATTSET4_0

#define FMC_PATT4_ATTSET4_0 (0x01UL << FMC_PATT4_ATTSET4_Pos)

0x00000001

◆ FMC_PATT4_ATTSET4_1

#define FMC_PATT4_ATTSET4_1 (0x02UL << FMC_PATT4_ATTSET4_Pos)

0x00000002

◆ FMC_PATT4_ATTSET4_2

#define FMC_PATT4_ATTSET4_2 (0x04UL << FMC_PATT4_ATTSET4_Pos)

0x00000004

◆ FMC_PATT4_ATTSET4_3

#define FMC_PATT4_ATTSET4_3 (0x08UL << FMC_PATT4_ATTSET4_Pos)

0x00000008

◆ FMC_PATT4_ATTSET4_4

#define FMC_PATT4_ATTSET4_4 (0x10UL << FMC_PATT4_ATTSET4_Pos)

0x00000010

◆ FMC_PATT4_ATTSET4_5

#define FMC_PATT4_ATTSET4_5 (0x20UL << FMC_PATT4_ATTSET4_Pos)

0x00000020

◆ FMC_PATT4_ATTSET4_6

#define FMC_PATT4_ATTSET4_6 (0x40UL << FMC_PATT4_ATTSET4_Pos)

0x00000040

◆ FMC_PATT4_ATTSET4_7

#define FMC_PATT4_ATTSET4_7 (0x80UL << FMC_PATT4_ATTSET4_Pos)

0x00000080

◆ FMC_PATT4_ATTSET4_Msk

#define FMC_PATT4_ATTSET4_Msk (0xFFUL << FMC_PATT4_ATTSET4_Pos)

0x000000FF

◆ FMC_PATT4_ATTSET4_Pos

#define FMC_PATT4_ATTSET4_Pos (0U)

◆ FMC_PATT4_ATTWAIT4

#define FMC_PATT4_ATTWAIT4 FMC_PATT4_ATTWAIT4_Msk

ATTWAIT4[7:0] bits (Attribute memory 4 wait time)

◆ FMC_PATT4_ATTWAIT4_0

#define FMC_PATT4_ATTWAIT4_0 (0x01UL << FMC_PATT4_ATTWAIT4_Pos)

0x00000100

◆ FMC_PATT4_ATTWAIT4_1

#define FMC_PATT4_ATTWAIT4_1 (0x02UL << FMC_PATT4_ATTWAIT4_Pos)

0x00000200

◆ FMC_PATT4_ATTWAIT4_2

#define FMC_PATT4_ATTWAIT4_2 (0x04UL << FMC_PATT4_ATTWAIT4_Pos)

0x00000400

◆ FMC_PATT4_ATTWAIT4_3

#define FMC_PATT4_ATTWAIT4_3 (0x08UL << FMC_PATT4_ATTWAIT4_Pos)

0x00000800

◆ FMC_PATT4_ATTWAIT4_4

#define FMC_PATT4_ATTWAIT4_4 (0x10UL << FMC_PATT4_ATTWAIT4_Pos)

0x00001000

◆ FMC_PATT4_ATTWAIT4_5

#define FMC_PATT4_ATTWAIT4_5 (0x20UL << FMC_PATT4_ATTWAIT4_Pos)

0x00002000

◆ FMC_PATT4_ATTWAIT4_6

#define FMC_PATT4_ATTWAIT4_6 (0x40UL << FMC_PATT4_ATTWAIT4_Pos)

0x00004000

◆ FMC_PATT4_ATTWAIT4_7

#define FMC_PATT4_ATTWAIT4_7 (0x80UL << FMC_PATT4_ATTWAIT4_Pos)

0x00008000

◆ FMC_PATT4_ATTWAIT4_Msk

#define FMC_PATT4_ATTWAIT4_Msk (0xFFUL << FMC_PATT4_ATTWAIT4_Pos)

0x0000FF00

◆ FMC_PATT4_ATTWAIT4_Pos

#define FMC_PATT4_ATTWAIT4_Pos (8U)

◆ FMC_PATTx_ATTHIZx

#define FMC_PATTx_ATTHIZx FMC_PATTx_ATTHIZx_Msk

ATTHIZx[7:0] bits (Attribute memory x databus HiZ time)

◆ FMC_PATTx_ATTHIZx_0

#define FMC_PATTx_ATTHIZx_0 (0x01UL << FMC_PATTx_ATTHIZx_Pos)

0x01000000

◆ FMC_PATTx_ATTHIZx_1

#define FMC_PATTx_ATTHIZx_1 (0x02UL << FMC_PATTx_ATTHIZx_Pos)

0x02000000

◆ FMC_PATTx_ATTHIZx_2

#define FMC_PATTx_ATTHIZx_2 (0x04UL << FMC_PATTx_ATTHIZx_Pos)

0x04000000

◆ FMC_PATTx_ATTHIZx_3

#define FMC_PATTx_ATTHIZx_3 (0x08UL << FMC_PATTx_ATTHIZx_Pos)

0x08000000

◆ FMC_PATTx_ATTHIZx_4

#define FMC_PATTx_ATTHIZx_4 (0x10UL << FMC_PATTx_ATTHIZx_Pos)

0x10000000

◆ FMC_PATTx_ATTHIZx_5

#define FMC_PATTx_ATTHIZx_5 (0x20UL << FMC_PATTx_ATTHIZx_Pos)

0x20000000

◆ FMC_PATTx_ATTHIZx_6

#define FMC_PATTx_ATTHIZx_6 (0x40UL << FMC_PATTx_ATTHIZx_Pos)

0x40000000

◆ FMC_PATTx_ATTHIZx_7

#define FMC_PATTx_ATTHIZx_7 (0x80UL << FMC_PATTx_ATTHIZx_Pos)

0x80000000

◆ FMC_PATTx_ATTHIZx_Msk

#define FMC_PATTx_ATTHIZx_Msk (0xFFUL << FMC_PATTx_ATTHIZx_Pos)

0xFF000000

◆ FMC_PATTx_ATTHIZx_Pos

#define FMC_PATTx_ATTHIZx_Pos (24U)

◆ FMC_PATTx_ATTHOLDx

#define FMC_PATTx_ATTHOLDx FMC_PATTx_ATTHOLDx_Msk

ATTHOLDx[7:0] bits (Attribute memory x hold time)

◆ FMC_PATTx_ATTHOLDx_0

#define FMC_PATTx_ATTHOLDx_0 (0x01UL << FMC_PATTx_ATTHOLDx_Pos)

0x00010000

◆ FMC_PATTx_ATTHOLDx_1

#define FMC_PATTx_ATTHOLDx_1 (0x02UL << FMC_PATTx_ATTHOLDx_Pos)

0x00020000

◆ FMC_PATTx_ATTHOLDx_2

#define FMC_PATTx_ATTHOLDx_2 (0x04UL << FMC_PATTx_ATTHOLDx_Pos)

0x00040000

◆ FMC_PATTx_ATTHOLDx_3

#define FMC_PATTx_ATTHOLDx_3 (0x08UL << FMC_PATTx_ATTHOLDx_Pos)

0x00080000

◆ FMC_PATTx_ATTHOLDx_4

#define FMC_PATTx_ATTHOLDx_4 (0x10UL << FMC_PATTx_ATTHOLDx_Pos)

0x00100000

◆ FMC_PATTx_ATTHOLDx_5

#define FMC_PATTx_ATTHOLDx_5 (0x20UL << FMC_PATTx_ATTHOLDx_Pos)

0x00200000

◆ FMC_PATTx_ATTHOLDx_6

#define FMC_PATTx_ATTHOLDx_6 (0x40UL << FMC_PATTx_ATTHOLDx_Pos)

0x00400000

◆ FMC_PATTx_ATTHOLDx_7

#define FMC_PATTx_ATTHOLDx_7 (0x80UL << FMC_PATTx_ATTHOLDx_Pos)

0x00800000

◆ FMC_PATTx_ATTHOLDx_Msk

#define FMC_PATTx_ATTHOLDx_Msk (0xFFUL << FMC_PATTx_ATTHOLDx_Pos)

0x00FF0000

◆ FMC_PATTx_ATTHOLDx_Pos

#define FMC_PATTx_ATTHOLDx_Pos (16U)

◆ FMC_PATTx_ATTSETx

#define FMC_PATTx_ATTSETx FMC_PATTx_ATTSETx_Msk

ATTSETx[7:0] bits (Attribute memory x setup time)

◆ FMC_PATTx_ATTSETx_0

#define FMC_PATTx_ATTSETx_0 (0x01UL << FMC_PATTx_ATTSETx_Pos)

0x00000001

◆ FMC_PATTx_ATTSETx_1

#define FMC_PATTx_ATTSETx_1 (0x02UL << FMC_PATTx_ATTSETx_Pos)

0x00000002

◆ FMC_PATTx_ATTSETx_2

#define FMC_PATTx_ATTSETx_2 (0x04UL << FMC_PATTx_ATTSETx_Pos)

0x00000004

◆ FMC_PATTx_ATTSETx_3

#define FMC_PATTx_ATTSETx_3 (0x08UL << FMC_PATTx_ATTSETx_Pos)

0x00000008

◆ FMC_PATTx_ATTSETx_4

#define FMC_PATTx_ATTSETx_4 (0x10UL << FMC_PATTx_ATTSETx_Pos)

0x00000010

◆ FMC_PATTx_ATTSETx_5

#define FMC_PATTx_ATTSETx_5 (0x20UL << FMC_PATTx_ATTSETx_Pos)

0x00000020

◆ FMC_PATTx_ATTSETx_6

#define FMC_PATTx_ATTSETx_6 (0x40UL << FMC_PATTx_ATTSETx_Pos)

0x00000040

◆ FMC_PATTx_ATTSETx_7

#define FMC_PATTx_ATTSETx_7 (0x80UL << FMC_PATTx_ATTSETx_Pos)

0x00000080

◆ FMC_PATTx_ATTSETx_Msk

#define FMC_PATTx_ATTSETx_Msk (0xFFUL << FMC_PATTx_ATTSETx_Pos)

0x000000FF

◆ FMC_PATTx_ATTSETx_Pos

#define FMC_PATTx_ATTSETx_Pos (0U)

◆ FMC_PATTx_ATTWAITx

#define FMC_PATTx_ATTWAITx FMC_PATTx_ATTWAITx_Msk

ATTWAITx[7:0] bits (Attribute memory x wait time)

◆ FMC_PATTx_ATTWAITx_0

#define FMC_PATTx_ATTWAITx_0 (0x01UL << FMC_PATTx_ATTWAITx_Pos)

0x00000100

◆ FMC_PATTx_ATTWAITx_1

#define FMC_PATTx_ATTWAITx_1 (0x02UL << FMC_PATTx_ATTWAITx_Pos)

0x00000200

◆ FMC_PATTx_ATTWAITx_2

#define FMC_PATTx_ATTWAITx_2 (0x04UL << FMC_PATTx_ATTWAITx_Pos)

0x00000400

◆ FMC_PATTx_ATTWAITx_3

#define FMC_PATTx_ATTWAITx_3 (0x08UL << FMC_PATTx_ATTWAITx_Pos)

0x00000800

◆ FMC_PATTx_ATTWAITx_4

#define FMC_PATTx_ATTWAITx_4 (0x10UL << FMC_PATTx_ATTWAITx_Pos)

0x00001000

◆ FMC_PATTx_ATTWAITx_5

#define FMC_PATTx_ATTWAITx_5 (0x20UL << FMC_PATTx_ATTWAITx_Pos)

0x00002000

◆ FMC_PATTx_ATTWAITx_6

#define FMC_PATTx_ATTWAITx_6 (0x40UL << FMC_PATTx_ATTWAITx_Pos)

0x00004000

◆ FMC_PATTx_ATTWAITx_7

#define FMC_PATTx_ATTWAITx_7 (0x80UL << FMC_PATTx_ATTWAITx_Pos)

0x00008000

◆ FMC_PATTx_ATTWAITx_Msk

#define FMC_PATTx_ATTWAITx_Msk (0xFFUL << FMC_PATTx_ATTWAITx_Pos)

0x0000FF00

◆ FMC_PATTx_ATTWAITx_Pos

#define FMC_PATTx_ATTWAITx_Pos (8U)

◆ FMC_PCR2_ECCEN

#define FMC_PCR2_ECCEN FMC_PCR2_ECCEN_Msk

ECC computation logic enable bit

◆ FMC_PCR2_ECCEN_Msk

#define FMC_PCR2_ECCEN_Msk (0x1UL << FMC_PCR2_ECCEN_Pos)

0x00000040

◆ FMC_PCR2_ECCEN_Pos

#define FMC_PCR2_ECCEN_Pos (6U)

◆ FMC_PCR2_ECCPS

#define FMC_PCR2_ECCPS FMC_PCR2_ECCPS_Msk

ECCPS[1:0] bits (ECC page size)

◆ FMC_PCR2_ECCPS_0

#define FMC_PCR2_ECCPS_0 (0x1UL << FMC_PCR2_ECCPS_Pos)

0x00020000

◆ FMC_PCR2_ECCPS_1

#define FMC_PCR2_ECCPS_1 (0x2UL << FMC_PCR2_ECCPS_Pos)

0x00040000

◆ FMC_PCR2_ECCPS_2

#define FMC_PCR2_ECCPS_2 (0x4UL << FMC_PCR2_ECCPS_Pos)

0x00080000

◆ FMC_PCR2_ECCPS_Msk

#define FMC_PCR2_ECCPS_Msk (0x7UL << FMC_PCR2_ECCPS_Pos)

0x000E0000

◆ FMC_PCR2_ECCPS_Pos

#define FMC_PCR2_ECCPS_Pos (17U)

◆ FMC_PCR2_PBKEN

#define FMC_PCR2_PBKEN FMC_PCR2_PBKEN_Msk

PC Card/NAND Flash memory bank enable bit

◆ FMC_PCR2_PBKEN_Msk

#define FMC_PCR2_PBKEN_Msk (0x1UL << FMC_PCR2_PBKEN_Pos)

0x00000004

◆ FMC_PCR2_PBKEN_Pos

#define FMC_PCR2_PBKEN_Pos (2U)

◆ FMC_PCR2_PTYP

#define FMC_PCR2_PTYP FMC_PCR2_PTYP_Msk

Memory type

◆ FMC_PCR2_PTYP_Msk

#define FMC_PCR2_PTYP_Msk (0x1UL << FMC_PCR2_PTYP_Pos)

0x00000008

◆ FMC_PCR2_PTYP_Pos

#define FMC_PCR2_PTYP_Pos (3U)

◆ FMC_PCR2_PWAITEN

#define FMC_PCR2_PWAITEN FMC_PCR2_PWAITEN_Msk

Wait feature enable bit

◆ FMC_PCR2_PWAITEN_Msk

#define FMC_PCR2_PWAITEN_Msk (0x1UL << FMC_PCR2_PWAITEN_Pos)

0x00000002

◆ FMC_PCR2_PWAITEN_Pos

#define FMC_PCR2_PWAITEN_Pos (1U)

◆ FMC_PCR2_PWID

#define FMC_PCR2_PWID FMC_PCR2_PWID_Msk

PWID[1:0] bits (NAND Flash databus width)

◆ FMC_PCR2_PWID_0

#define FMC_PCR2_PWID_0 (0x1UL << FMC_PCR2_PWID_Pos)

0x00000010

◆ FMC_PCR2_PWID_1

#define FMC_PCR2_PWID_1 (0x2UL << FMC_PCR2_PWID_Pos)

0x00000020

◆ FMC_PCR2_PWID_Msk

#define FMC_PCR2_PWID_Msk (0x3UL << FMC_PCR2_PWID_Pos)

0x00000030

◆ FMC_PCR2_PWID_Pos

#define FMC_PCR2_PWID_Pos (4U)

◆ FMC_PCR2_TAR

#define FMC_PCR2_TAR FMC_PCR2_TAR_Msk

TAR[3:0] bits (ALE to RE delay)

◆ FMC_PCR2_TAR_0

#define FMC_PCR2_TAR_0 (0x1UL << FMC_PCR2_TAR_Pos)

0x00002000

◆ FMC_PCR2_TAR_1

#define FMC_PCR2_TAR_1 (0x2UL << FMC_PCR2_TAR_Pos)

0x00004000

◆ FMC_PCR2_TAR_2

#define FMC_PCR2_TAR_2 (0x4UL << FMC_PCR2_TAR_Pos)

0x00008000

◆ FMC_PCR2_TAR_3

#define FMC_PCR2_TAR_3 (0x8UL << FMC_PCR2_TAR_Pos)

0x00010000

◆ FMC_PCR2_TAR_Msk

#define FMC_PCR2_TAR_Msk (0xFUL << FMC_PCR2_TAR_Pos)

0x0001E000

◆ FMC_PCR2_TAR_Pos

#define FMC_PCR2_TAR_Pos (13U)

◆ FMC_PCR2_TCLR

#define FMC_PCR2_TCLR FMC_PCR2_TCLR_Msk

TCLR[3:0] bits (CLE to RE delay)

◆ FMC_PCR2_TCLR_0

#define FMC_PCR2_TCLR_0 (0x1UL << FMC_PCR2_TCLR_Pos)

0x00000200

◆ FMC_PCR2_TCLR_1

#define FMC_PCR2_TCLR_1 (0x2UL << FMC_PCR2_TCLR_Pos)

0x00000400

◆ FMC_PCR2_TCLR_2

#define FMC_PCR2_TCLR_2 (0x4UL << FMC_PCR2_TCLR_Pos)

0x00000800

◆ FMC_PCR2_TCLR_3

#define FMC_PCR2_TCLR_3 (0x8UL << FMC_PCR2_TCLR_Pos)

0x00001000

◆ FMC_PCR2_TCLR_Msk

#define FMC_PCR2_TCLR_Msk (0xFUL << FMC_PCR2_TCLR_Pos)

0x00001E00

◆ FMC_PCR2_TCLR_Pos

#define FMC_PCR2_TCLR_Pos (9U)

◆ FMC_PCR3_ECCEN

#define FMC_PCR3_ECCEN FMC_PCR3_ECCEN_Msk

ECC computation logic enable bit

◆ FMC_PCR3_ECCEN_Msk

#define FMC_PCR3_ECCEN_Msk (0x1UL << FMC_PCR3_ECCEN_Pos)

0x00000040

◆ FMC_PCR3_ECCEN_Pos

#define FMC_PCR3_ECCEN_Pos (6U)

◆ FMC_PCR3_ECCPS

#define FMC_PCR3_ECCPS FMC_PCR3_ECCPS_Msk

ECCPS[2:0] bits (ECC page size)

◆ FMC_PCR3_ECCPS_0

#define FMC_PCR3_ECCPS_0 (0x1UL << FMC_PCR3_ECCPS_Pos)

0x00020000

◆ FMC_PCR3_ECCPS_1

#define FMC_PCR3_ECCPS_1 (0x2UL << FMC_PCR3_ECCPS_Pos)

0x00040000

◆ FMC_PCR3_ECCPS_2

#define FMC_PCR3_ECCPS_2 (0x4UL << FMC_PCR3_ECCPS_Pos)

0x00080000

◆ FMC_PCR3_ECCPS_Msk

#define FMC_PCR3_ECCPS_Msk (0x7UL << FMC_PCR3_ECCPS_Pos)

0x000E0000

◆ FMC_PCR3_ECCPS_Pos

#define FMC_PCR3_ECCPS_Pos (17U)

◆ FMC_PCR3_PBKEN

#define FMC_PCR3_PBKEN FMC_PCR3_PBKEN_Msk

PC Card/NAND Flash memory bank enable bit

◆ FMC_PCR3_PBKEN_Msk

#define FMC_PCR3_PBKEN_Msk (0x1UL << FMC_PCR3_PBKEN_Pos)

0x00000004

◆ FMC_PCR3_PBKEN_Pos

#define FMC_PCR3_PBKEN_Pos (2U)

◆ FMC_PCR3_PTYP

#define FMC_PCR3_PTYP FMC_PCR3_PTYP_Msk

Memory type

◆ FMC_PCR3_PTYP_Msk

#define FMC_PCR3_PTYP_Msk (0x1UL << FMC_PCR3_PTYP_Pos)

0x00000008

◆ FMC_PCR3_PTYP_Pos

#define FMC_PCR3_PTYP_Pos (3U)

◆ FMC_PCR3_PWAITEN

#define FMC_PCR3_PWAITEN FMC_PCR3_PWAITEN_Msk

Wait feature enable bit

◆ FMC_PCR3_PWAITEN_Msk

#define FMC_PCR3_PWAITEN_Msk (0x1UL << FMC_PCR3_PWAITEN_Pos)

0x00000002

◆ FMC_PCR3_PWAITEN_Pos

#define FMC_PCR3_PWAITEN_Pos (1U)

◆ FMC_PCR3_PWID

#define FMC_PCR3_PWID FMC_PCR3_PWID_Msk

PWID[1:0] bits (NAND Flash databus width)

◆ FMC_PCR3_PWID_0

#define FMC_PCR3_PWID_0 (0x1UL << FMC_PCR3_PWID_Pos)

0x00000010

◆ FMC_PCR3_PWID_1

#define FMC_PCR3_PWID_1 (0x2UL << FMC_PCR3_PWID_Pos)

0x00000020

◆ FMC_PCR3_PWID_Msk

#define FMC_PCR3_PWID_Msk (0x3UL << FMC_PCR3_PWID_Pos)

0x00000030

◆ FMC_PCR3_PWID_Pos

#define FMC_PCR3_PWID_Pos (4U)

◆ FMC_PCR3_TAR

#define FMC_PCR3_TAR FMC_PCR3_TAR_Msk

TAR[3:0] bits (ALE to RE delay)

◆ FMC_PCR3_TAR_0

#define FMC_PCR3_TAR_0 (0x1UL << FMC_PCR3_TAR_Pos)

0x00002000

◆ FMC_PCR3_TAR_1

#define FMC_PCR3_TAR_1 (0x2UL << FMC_PCR3_TAR_Pos)

0x00004000

◆ FMC_PCR3_TAR_2

#define FMC_PCR3_TAR_2 (0x4UL << FMC_PCR3_TAR_Pos)

0x00008000

◆ FMC_PCR3_TAR_3

#define FMC_PCR3_TAR_3 (0x8UL << FMC_PCR3_TAR_Pos)

0x00010000

◆ FMC_PCR3_TAR_Msk

#define FMC_PCR3_TAR_Msk (0xFUL << FMC_PCR3_TAR_Pos)

0x0001E000

◆ FMC_PCR3_TAR_Pos

#define FMC_PCR3_TAR_Pos (13U)

◆ FMC_PCR3_TCLR

#define FMC_PCR3_TCLR FMC_PCR3_TCLR_Msk

TCLR[3:0] bits (CLE to RE delay)

◆ FMC_PCR3_TCLR_0

#define FMC_PCR3_TCLR_0 (0x1UL << FMC_PCR3_TCLR_Pos)

0x00000200

◆ FMC_PCR3_TCLR_1

#define FMC_PCR3_TCLR_1 (0x2UL << FMC_PCR3_TCLR_Pos)

0x00000400

◆ FMC_PCR3_TCLR_2

#define FMC_PCR3_TCLR_2 (0x4UL << FMC_PCR3_TCLR_Pos)

0x00000800

◆ FMC_PCR3_TCLR_3

#define FMC_PCR3_TCLR_3 (0x8UL << FMC_PCR3_TCLR_Pos)

0x00001000

◆ FMC_PCR3_TCLR_Msk

#define FMC_PCR3_TCLR_Msk (0xFUL << FMC_PCR3_TCLR_Pos)

0x00001E00

◆ FMC_PCR3_TCLR_Pos

#define FMC_PCR3_TCLR_Pos (9U)

◆ FMC_PCR4_ECCEN

#define FMC_PCR4_ECCEN FMC_PCR4_ECCEN_Msk

ECC computation logic enable bit

◆ FMC_PCR4_ECCEN_Msk

#define FMC_PCR4_ECCEN_Msk (0x1UL << FMC_PCR4_ECCEN_Pos)

0x00000040

◆ FMC_PCR4_ECCEN_Pos

#define FMC_PCR4_ECCEN_Pos (6U)

◆ FMC_PCR4_ECCPS

#define FMC_PCR4_ECCPS FMC_PCR4_ECCPS_Msk

ECCPS[2:0] bits (ECC page size)

◆ FMC_PCR4_ECCPS_0

#define FMC_PCR4_ECCPS_0 (0x1UL << FMC_PCR4_ECCPS_Pos)

0x00020000

◆ FMC_PCR4_ECCPS_1

#define FMC_PCR4_ECCPS_1 (0x2UL << FMC_PCR4_ECCPS_Pos)

0x00040000

◆ FMC_PCR4_ECCPS_2

#define FMC_PCR4_ECCPS_2 (0x4UL << FMC_PCR4_ECCPS_Pos)

0x00080000

◆ FMC_PCR4_ECCPS_Msk

#define FMC_PCR4_ECCPS_Msk (0x7UL << FMC_PCR4_ECCPS_Pos)

0x000E0000

◆ FMC_PCR4_ECCPS_Pos

#define FMC_PCR4_ECCPS_Pos (17U)

◆ FMC_PCR4_PBKEN

#define FMC_PCR4_PBKEN FMC_PCR4_PBKEN_Msk

PC Card/NAND Flash memory bank enable bit

◆ FMC_PCR4_PBKEN_Msk

#define FMC_PCR4_PBKEN_Msk (0x1UL << FMC_PCR4_PBKEN_Pos)

0x00000004

◆ FMC_PCR4_PBKEN_Pos

#define FMC_PCR4_PBKEN_Pos (2U)

◆ FMC_PCR4_PTYP

#define FMC_PCR4_PTYP FMC_PCR4_PTYP_Msk

Memory type

◆ FMC_PCR4_PTYP_Msk

#define FMC_PCR4_PTYP_Msk (0x1UL << FMC_PCR4_PTYP_Pos)

0x00000008

◆ FMC_PCR4_PTYP_Pos

#define FMC_PCR4_PTYP_Pos (3U)

◆ FMC_PCR4_PWAITEN

#define FMC_PCR4_PWAITEN FMC_PCR4_PWAITEN_Msk

Wait feature enable bit

◆ FMC_PCR4_PWAITEN_Msk

#define FMC_PCR4_PWAITEN_Msk (0x1UL << FMC_PCR4_PWAITEN_Pos)

0x00000002

◆ FMC_PCR4_PWAITEN_Pos

#define FMC_PCR4_PWAITEN_Pos (1U)

◆ FMC_PCR4_PWID

#define FMC_PCR4_PWID FMC_PCR4_PWID_Msk

PWID[1:0] bits (NAND Flash databus width)

◆ FMC_PCR4_PWID_0

#define FMC_PCR4_PWID_0 (0x1UL << FMC_PCR4_PWID_Pos)

0x00000010

◆ FMC_PCR4_PWID_1

#define FMC_PCR4_PWID_1 (0x2UL << FMC_PCR4_PWID_Pos)

0x00000020

◆ FMC_PCR4_PWID_Msk

#define FMC_PCR4_PWID_Msk (0x3UL << FMC_PCR4_PWID_Pos)

0x00000030

◆ FMC_PCR4_PWID_Pos

#define FMC_PCR4_PWID_Pos (4U)

◆ FMC_PCR4_TAR

#define FMC_PCR4_TAR FMC_PCR4_TAR_Msk

TAR[3:0] bits (ALE to RE delay)

◆ FMC_PCR4_TAR_0

#define FMC_PCR4_TAR_0 (0x1UL << FMC_PCR4_TAR_Pos)

0x00002000

◆ FMC_PCR4_TAR_1

#define FMC_PCR4_TAR_1 (0x2UL << FMC_PCR4_TAR_Pos)

0x00004000

◆ FMC_PCR4_TAR_2

#define FMC_PCR4_TAR_2 (0x4UL << FMC_PCR4_TAR_Pos)

0x00008000

◆ FMC_PCR4_TAR_3

#define FMC_PCR4_TAR_3 (0x8UL << FMC_PCR4_TAR_Pos)

0x00010000

◆ FMC_PCR4_TAR_Msk

#define FMC_PCR4_TAR_Msk (0xFUL << FMC_PCR4_TAR_Pos)

0x0001E000

◆ FMC_PCR4_TAR_Pos

#define FMC_PCR4_TAR_Pos (13U)

◆ FMC_PCR4_TCLR

#define FMC_PCR4_TCLR FMC_PCR4_TCLR_Msk

TCLR[3:0] bits (CLE to RE delay)

◆ FMC_PCR4_TCLR_0

#define FMC_PCR4_TCLR_0 (0x1UL << FMC_PCR4_TCLR_Pos)

0x00000200

◆ FMC_PCR4_TCLR_1

#define FMC_PCR4_TCLR_1 (0x2UL << FMC_PCR4_TCLR_Pos)

0x00000400

◆ FMC_PCR4_TCLR_2

#define FMC_PCR4_TCLR_2 (0x4UL << FMC_PCR4_TCLR_Pos)

0x00000800

◆ FMC_PCR4_TCLR_3

#define FMC_PCR4_TCLR_3 (0x8UL << FMC_PCR4_TCLR_Pos)

0x00001000

◆ FMC_PCR4_TCLR_Msk

#define FMC_PCR4_TCLR_Msk (0xFUL << FMC_PCR4_TCLR_Pos)

0x00001E00

◆ FMC_PCR4_TCLR_Pos

#define FMC_PCR4_TCLR_Pos (9U)

◆ FMC_PCRx_ECCEN

#define FMC_PCRx_ECCEN FMC_PCRx_ECCEN_Msk

ECC computation logic enable bit

◆ FMC_PCRx_ECCEN_Msk

#define FMC_PCRx_ECCEN_Msk (0x1UL << FMC_PCRx_ECCEN_Pos)

0x00000040

◆ FMC_PCRx_ECCEN_Pos

#define FMC_PCRx_ECCEN_Pos (6U)

◆ FMC_PCRx_ECCPS

#define FMC_PCRx_ECCPS FMC_PCRx_ECCPS_Msk

ECCPS[1:0] bits (ECC page size)

◆ FMC_PCRx_ECCPS_0

#define FMC_PCRx_ECCPS_0 (0x1UL << FMC_PCRx_ECCPS_Pos)

0x00020000

◆ FMC_PCRx_ECCPS_1

#define FMC_PCRx_ECCPS_1 (0x2UL << FMC_PCRx_ECCPS_Pos)

0x00040000

◆ FMC_PCRx_ECCPS_2

#define FMC_PCRx_ECCPS_2 (0x4UL << FMC_PCRx_ECCPS_Pos)

0x00080000

◆ FMC_PCRx_ECCPS_Msk

#define FMC_PCRx_ECCPS_Msk (0x7UL << FMC_PCRx_ECCPS_Pos)

0x000E0000

◆ FMC_PCRx_ECCPS_Pos

#define FMC_PCRx_ECCPS_Pos (17U)

◆ FMC_PCRx_PBKEN

#define FMC_PCRx_PBKEN FMC_PCRx_PBKEN_Msk

PC Card/NAND Flash memory bank enable bit

◆ FMC_PCRx_PBKEN_Msk

#define FMC_PCRx_PBKEN_Msk (0x1UL << FMC_PCRx_PBKEN_Pos)

0x00000004

◆ FMC_PCRx_PBKEN_Pos

#define FMC_PCRx_PBKEN_Pos (2U)

◆ FMC_PCRx_PTYP

#define FMC_PCRx_PTYP FMC_PCRx_PTYP_Msk

Memory type

◆ FMC_PCRx_PTYP_Msk

#define FMC_PCRx_PTYP_Msk (0x1UL << FMC_PCRx_PTYP_Pos)

0x00000008

◆ FMC_PCRx_PTYP_Pos

#define FMC_PCRx_PTYP_Pos (3U)

◆ FMC_PCRx_PWAITEN

#define FMC_PCRx_PWAITEN FMC_PCRx_PWAITEN_Msk

Wait feature enable bit

◆ FMC_PCRx_PWAITEN_Msk

#define FMC_PCRx_PWAITEN_Msk (0x1UL << FMC_PCRx_PWAITEN_Pos)

0x00000002

◆ FMC_PCRx_PWAITEN_Pos

#define FMC_PCRx_PWAITEN_Pos (1U)

◆ FMC_PCRx_PWID

#define FMC_PCRx_PWID FMC_PCRx_PWID_Msk

PWID[1:0] bits (NAND Flash databus width)

◆ FMC_PCRx_PWID_0

#define FMC_PCRx_PWID_0 (0x1UL << FMC_PCRx_PWID_Pos)

0x00000010

◆ FMC_PCRx_PWID_1

#define FMC_PCRx_PWID_1 (0x2UL << FMC_PCRx_PWID_Pos)

0x00000020

◆ FMC_PCRx_PWID_Msk

#define FMC_PCRx_PWID_Msk (0x3UL << FMC_PCRx_PWID_Pos)

0x00000030

◆ FMC_PCRx_PWID_Pos

#define FMC_PCRx_PWID_Pos (4U)

◆ FMC_PCRx_TAR

#define FMC_PCRx_TAR FMC_PCRx_TAR_Msk

TAR[3:0] bits (ALE to RE delay)

◆ FMC_PCRx_TAR_0

#define FMC_PCRx_TAR_0 (0x1UL << FMC_PCRx_TAR_Pos)

0x00002000

◆ FMC_PCRx_TAR_1

#define FMC_PCRx_TAR_1 (0x2UL << FMC_PCRx_TAR_Pos)

0x00004000

◆ FMC_PCRx_TAR_2

#define FMC_PCRx_TAR_2 (0x4UL << FMC_PCRx_TAR_Pos)

0x00008000

◆ FMC_PCRx_TAR_3

#define FMC_PCRx_TAR_3 (0x8UL << FMC_PCRx_TAR_Pos)

0x00010000

◆ FMC_PCRx_TAR_Msk

#define FMC_PCRx_TAR_Msk (0xFUL << FMC_PCRx_TAR_Pos)

0x0001E000

◆ FMC_PCRx_TAR_Pos

#define FMC_PCRx_TAR_Pos (13U)

◆ FMC_PCRx_TCLR

#define FMC_PCRx_TCLR FMC_PCRx_TCLR_Msk

TCLR[3:0] bits (CLE to RE delay)

◆ FMC_PCRx_TCLR_0

#define FMC_PCRx_TCLR_0 (0x1UL << FMC_PCRx_TCLR_Pos)

0x00000200

◆ FMC_PCRx_TCLR_1

#define FMC_PCRx_TCLR_1 (0x2UL << FMC_PCRx_TCLR_Pos)

0x00000400

◆ FMC_PCRx_TCLR_2

#define FMC_PCRx_TCLR_2 (0x4UL << FMC_PCRx_TCLR_Pos)

0x00000800

◆ FMC_PCRx_TCLR_3

#define FMC_PCRx_TCLR_3 (0x8UL << FMC_PCRx_TCLR_Pos)

0x00001000

◆ FMC_PCRx_TCLR_Msk

#define FMC_PCRx_TCLR_Msk (0xFUL << FMC_PCRx_TCLR_Pos)

0x00001E00

◆ FMC_PCRx_TCLR_Pos

#define FMC_PCRx_TCLR_Pos (9U)

◆ FMC_PIO4_IOHIZ4

#define FMC_PIO4_IOHIZ4 FMC_PIO4_IOHIZ4_Msk

IOHIZ4[7:0] bits (I/O 4 databus HiZ time)

◆ FMC_PIO4_IOHIZ4_0

#define FMC_PIO4_IOHIZ4_0 (0x01UL << FMC_PIO4_IOHIZ4_Pos)

0x01000000

◆ FMC_PIO4_IOHIZ4_1

#define FMC_PIO4_IOHIZ4_1 (0x02UL << FMC_PIO4_IOHIZ4_Pos)

0x02000000

◆ FMC_PIO4_IOHIZ4_2

#define FMC_PIO4_IOHIZ4_2 (0x04UL << FMC_PIO4_IOHIZ4_Pos)

0x04000000

◆ FMC_PIO4_IOHIZ4_3

#define FMC_PIO4_IOHIZ4_3 (0x08UL << FMC_PIO4_IOHIZ4_Pos)

0x08000000

◆ FMC_PIO4_IOHIZ4_4

#define FMC_PIO4_IOHIZ4_4 (0x10UL << FMC_PIO4_IOHIZ4_Pos)

0x10000000

◆ FMC_PIO4_IOHIZ4_5

#define FMC_PIO4_IOHIZ4_5 (0x20UL << FMC_PIO4_IOHIZ4_Pos)

0x20000000

◆ FMC_PIO4_IOHIZ4_6

#define FMC_PIO4_IOHIZ4_6 (0x40UL << FMC_PIO4_IOHIZ4_Pos)

0x40000000

◆ FMC_PIO4_IOHIZ4_7

#define FMC_PIO4_IOHIZ4_7 (0x80UL << FMC_PIO4_IOHIZ4_Pos)

0x80000000

◆ FMC_PIO4_IOHIZ4_Msk

#define FMC_PIO4_IOHIZ4_Msk (0xFFUL << FMC_PIO4_IOHIZ4_Pos)

0xFF000000

◆ FMC_PIO4_IOHIZ4_Pos

#define FMC_PIO4_IOHIZ4_Pos (24U)

◆ FMC_PIO4_IOHOLD4

#define FMC_PIO4_IOHOLD4 FMC_PIO4_IOHOLD4_Msk

IOHOLD4[7:0] bits (I/O 4 hold time)

◆ FMC_PIO4_IOHOLD4_0

#define FMC_PIO4_IOHOLD4_0 (0x01UL << FMC_PIO4_IOHOLD4_Pos)

0x00010000

◆ FMC_PIO4_IOHOLD4_1

#define FMC_PIO4_IOHOLD4_1 (0x02UL << FMC_PIO4_IOHOLD4_Pos)

0x00020000

◆ FMC_PIO4_IOHOLD4_2

#define FMC_PIO4_IOHOLD4_2 (0x04UL << FMC_PIO4_IOHOLD4_Pos)

0x00040000

◆ FMC_PIO4_IOHOLD4_3

#define FMC_PIO4_IOHOLD4_3 (0x08UL << FMC_PIO4_IOHOLD4_Pos)

0x00080000

◆ FMC_PIO4_IOHOLD4_4

#define FMC_PIO4_IOHOLD4_4 (0x10UL << FMC_PIO4_IOHOLD4_Pos)

0x00100000

◆ FMC_PIO4_IOHOLD4_5

#define FMC_PIO4_IOHOLD4_5 (0x20UL << FMC_PIO4_IOHOLD4_Pos)

0x00200000

◆ FMC_PIO4_IOHOLD4_6

#define FMC_PIO4_IOHOLD4_6 (0x40UL << FMC_PIO4_IOHOLD4_Pos)

0x00400000

◆ FMC_PIO4_IOHOLD4_7

#define FMC_PIO4_IOHOLD4_7 (0x80UL << FMC_PIO4_IOHOLD4_Pos)

0x00800000

◆ FMC_PIO4_IOHOLD4_Msk

#define FMC_PIO4_IOHOLD4_Msk (0xFFUL << FMC_PIO4_IOHOLD4_Pos)

0x00FF0000

◆ FMC_PIO4_IOHOLD4_Pos

#define FMC_PIO4_IOHOLD4_Pos (16U)

◆ FMC_PIO4_IOSET4

#define FMC_PIO4_IOSET4 FMC_PIO4_IOSET4_Msk

IOSET4[7:0] bits (I/O 4 setup time)

◆ FMC_PIO4_IOSET4_0

#define FMC_PIO4_IOSET4_0 (0x01UL << FMC_PIO4_IOSET4_Pos)

0x00000001

◆ FMC_PIO4_IOSET4_1

#define FMC_PIO4_IOSET4_1 (0x02UL << FMC_PIO4_IOSET4_Pos)

0x00000002

◆ FMC_PIO4_IOSET4_2

#define FMC_PIO4_IOSET4_2 (0x04UL << FMC_PIO4_IOSET4_Pos)

0x00000004

◆ FMC_PIO4_IOSET4_3

#define FMC_PIO4_IOSET4_3 (0x08UL << FMC_PIO4_IOSET4_Pos)

0x00000008

◆ FMC_PIO4_IOSET4_4

#define FMC_PIO4_IOSET4_4 (0x10UL << FMC_PIO4_IOSET4_Pos)

0x00000010

◆ FMC_PIO4_IOSET4_5

#define FMC_PIO4_IOSET4_5 (0x20UL << FMC_PIO4_IOSET4_Pos)

0x00000020

◆ FMC_PIO4_IOSET4_6

#define FMC_PIO4_IOSET4_6 (0x40UL << FMC_PIO4_IOSET4_Pos)

0x00000040

◆ FMC_PIO4_IOSET4_7

#define FMC_PIO4_IOSET4_7 (0x80UL << FMC_PIO4_IOSET4_Pos)

0x00000080

◆ FMC_PIO4_IOSET4_Msk

#define FMC_PIO4_IOSET4_Msk (0xFFUL << FMC_PIO4_IOSET4_Pos)

0x000000FF

◆ FMC_PIO4_IOSET4_Pos

#define FMC_PIO4_IOSET4_Pos (0U)

◆ FMC_PIO4_IOWAIT4

#define FMC_PIO4_IOWAIT4 FMC_PIO4_IOWAIT4_Msk

IOWAIT4[7:0] bits (I/O 4 wait time)

◆ FMC_PIO4_IOWAIT4_0

#define FMC_PIO4_IOWAIT4_0 (0x01UL << FMC_PIO4_IOWAIT4_Pos)

0x00000100

◆ FMC_PIO4_IOWAIT4_1

#define FMC_PIO4_IOWAIT4_1 (0x02UL << FMC_PIO4_IOWAIT4_Pos)

0x00000200

◆ FMC_PIO4_IOWAIT4_2

#define FMC_PIO4_IOWAIT4_2 (0x04UL << FMC_PIO4_IOWAIT4_Pos)

0x00000400

◆ FMC_PIO4_IOWAIT4_3

#define FMC_PIO4_IOWAIT4_3 (0x08UL << FMC_PIO4_IOWAIT4_Pos)

0x00000800

◆ FMC_PIO4_IOWAIT4_4

#define FMC_PIO4_IOWAIT4_4 (0x10UL << FMC_PIO4_IOWAIT4_Pos)

0x00001000

◆ FMC_PIO4_IOWAIT4_5

#define FMC_PIO4_IOWAIT4_5 (0x20UL << FMC_PIO4_IOWAIT4_Pos)

0x00002000

◆ FMC_PIO4_IOWAIT4_6

#define FMC_PIO4_IOWAIT4_6 (0x40UL << FMC_PIO4_IOWAIT4_Pos)

0x00004000

◆ FMC_PIO4_IOWAIT4_7

#define FMC_PIO4_IOWAIT4_7 (0x80UL << FMC_PIO4_IOWAIT4_Pos)

0x00008000

◆ FMC_PIO4_IOWAIT4_Msk

#define FMC_PIO4_IOWAIT4_Msk (0xFFUL << FMC_PIO4_IOWAIT4_Pos)

0x0000FF00

◆ FMC_PIO4_IOWAIT4_Pos

#define FMC_PIO4_IOWAIT4_Pos (8U)

◆ FMC_PMEM2_MEMHIZ2

#define FMC_PMEM2_MEMHIZ2 FMC_PMEM2_MEMHIZ2_Msk

MEMHIZ2[7:0] bits (Common memory 2 databus HiZ time)

◆ FMC_PMEM2_MEMHIZ2_0

#define FMC_PMEM2_MEMHIZ2_0 (0x01UL << FMC_PMEM2_MEMHIZ2_Pos)

0x01000000

◆ FMC_PMEM2_MEMHIZ2_1

#define FMC_PMEM2_MEMHIZ2_1 (0x02UL << FMC_PMEM2_MEMHIZ2_Pos)

0x02000000

◆ FMC_PMEM2_MEMHIZ2_2

#define FMC_PMEM2_MEMHIZ2_2 (0x04UL << FMC_PMEM2_MEMHIZ2_Pos)

0x04000000

◆ FMC_PMEM2_MEMHIZ2_3

#define FMC_PMEM2_MEMHIZ2_3 (0x08UL << FMC_PMEM2_MEMHIZ2_Pos)

0x08000000

◆ FMC_PMEM2_MEMHIZ2_4

#define FMC_PMEM2_MEMHIZ2_4 (0x10UL << FMC_PMEM2_MEMHIZ2_Pos)

0x10000000

◆ FMC_PMEM2_MEMHIZ2_5

#define FMC_PMEM2_MEMHIZ2_5 (0x20UL << FMC_PMEM2_MEMHIZ2_Pos)

0x20000000

◆ FMC_PMEM2_MEMHIZ2_6

#define FMC_PMEM2_MEMHIZ2_6 (0x40UL << FMC_PMEM2_MEMHIZ2_Pos)

0x40000000

◆ FMC_PMEM2_MEMHIZ2_7

#define FMC_PMEM2_MEMHIZ2_7 (0x80UL << FMC_PMEM2_MEMHIZ2_Pos)

0x80000000

◆ FMC_PMEM2_MEMHIZ2_Msk

#define FMC_PMEM2_MEMHIZ2_Msk (0xFFUL << FMC_PMEM2_MEMHIZ2_Pos)

0xFF000000

◆ FMC_PMEM2_MEMHIZ2_Pos

#define FMC_PMEM2_MEMHIZ2_Pos (24U)

◆ FMC_PMEM2_MEMHOLD2

#define FMC_PMEM2_MEMHOLD2 FMC_PMEM2_MEMHOLD2_Msk

MEMHOLD2[7:0] bits (Common memory 2 hold time)

◆ FMC_PMEM2_MEMHOLD2_0

#define FMC_PMEM2_MEMHOLD2_0 (0x01UL << FMC_PMEM2_MEMHOLD2_Pos)

0x00010000

◆ FMC_PMEM2_MEMHOLD2_1

#define FMC_PMEM2_MEMHOLD2_1 (0x02UL << FMC_PMEM2_MEMHOLD2_Pos)

0x00020000

◆ FMC_PMEM2_MEMHOLD2_2

#define FMC_PMEM2_MEMHOLD2_2 (0x04UL << FMC_PMEM2_MEMHOLD2_Pos)

0x00040000

◆ FMC_PMEM2_MEMHOLD2_3

#define FMC_PMEM2_MEMHOLD2_3 (0x08UL << FMC_PMEM2_MEMHOLD2_Pos)

0x00080000

◆ FMC_PMEM2_MEMHOLD2_4

#define FMC_PMEM2_MEMHOLD2_4 (0x10UL << FMC_PMEM2_MEMHOLD2_Pos)

0x00100000

◆ FMC_PMEM2_MEMHOLD2_5

#define FMC_PMEM2_MEMHOLD2_5 (0x20UL << FMC_PMEM2_MEMHOLD2_Pos)

0x00200000

◆ FMC_PMEM2_MEMHOLD2_6

#define FMC_PMEM2_MEMHOLD2_6 (0x40UL << FMC_PMEM2_MEMHOLD2_Pos)

0x00400000

◆ FMC_PMEM2_MEMHOLD2_7

#define FMC_PMEM2_MEMHOLD2_7 (0x80UL << FMC_PMEM2_MEMHOLD2_Pos)

0x00800000

◆ FMC_PMEM2_MEMHOLD2_Msk

#define FMC_PMEM2_MEMHOLD2_Msk (0xFFUL << FMC_PMEM2_MEMHOLD2_Pos)

0x00FF0000

◆ FMC_PMEM2_MEMHOLD2_Pos

#define FMC_PMEM2_MEMHOLD2_Pos (16U)

◆ FMC_PMEM2_MEMSET2

#define FMC_PMEM2_MEMSET2 FMC_PMEM2_MEMSET2_Msk

MEMSET2[7:0] bits (Common memory 2 setup time)

◆ FMC_PMEM2_MEMSET2_0

#define FMC_PMEM2_MEMSET2_0 (0x01UL << FMC_PMEM2_MEMSET2_Pos)

0x00000001

◆ FMC_PMEM2_MEMSET2_1

#define FMC_PMEM2_MEMSET2_1 (0x02UL << FMC_PMEM2_MEMSET2_Pos)

0x00000002

◆ FMC_PMEM2_MEMSET2_2

#define FMC_PMEM2_MEMSET2_2 (0x04UL << FMC_PMEM2_MEMSET2_Pos)

0x00000004

◆ FMC_PMEM2_MEMSET2_3

#define FMC_PMEM2_MEMSET2_3 (0x08UL << FMC_PMEM2_MEMSET2_Pos)

0x00000008

◆ FMC_PMEM2_MEMSET2_4

#define FMC_PMEM2_MEMSET2_4 (0x10UL << FMC_PMEM2_MEMSET2_Pos)

0x00000010

◆ FMC_PMEM2_MEMSET2_5

#define FMC_PMEM2_MEMSET2_5 (0x20UL << FMC_PMEM2_MEMSET2_Pos)

0x00000020

◆ FMC_PMEM2_MEMSET2_6

#define FMC_PMEM2_MEMSET2_6 (0x40UL << FMC_PMEM2_MEMSET2_Pos)

0x00000040

◆ FMC_PMEM2_MEMSET2_7

#define FMC_PMEM2_MEMSET2_7 (0x80UL << FMC_PMEM2_MEMSET2_Pos)

0x00000080

◆ FMC_PMEM2_MEMSET2_Msk

#define FMC_PMEM2_MEMSET2_Msk (0xFFUL << FMC_PMEM2_MEMSET2_Pos)

0x000000FF

◆ FMC_PMEM2_MEMSET2_Pos

#define FMC_PMEM2_MEMSET2_Pos (0U)

◆ FMC_PMEM2_MEMWAIT2

#define FMC_PMEM2_MEMWAIT2 FMC_PMEM2_MEMWAIT2_Msk

MEMWAIT2[7:0] bits (Common memory 2 wait time)

◆ FMC_PMEM2_MEMWAIT2_0

#define FMC_PMEM2_MEMWAIT2_0 (0x01UL << FMC_PMEM2_MEMWAIT2_Pos)

0x00000100

◆ FMC_PMEM2_MEMWAIT2_1

#define FMC_PMEM2_MEMWAIT2_1 (0x02UL << FMC_PMEM2_MEMWAIT2_Pos)

0x00000200

◆ FMC_PMEM2_MEMWAIT2_2

#define FMC_PMEM2_MEMWAIT2_2 (0x04UL << FMC_PMEM2_MEMWAIT2_Pos)

0x00000400

◆ FMC_PMEM2_MEMWAIT2_3

#define FMC_PMEM2_MEMWAIT2_3 (0x08UL << FMC_PMEM2_MEMWAIT2_Pos)

0x00000800

◆ FMC_PMEM2_MEMWAIT2_4

#define FMC_PMEM2_MEMWAIT2_4 (0x10UL << FMC_PMEM2_MEMWAIT2_Pos)

0x00001000

◆ FMC_PMEM2_MEMWAIT2_5

#define FMC_PMEM2_MEMWAIT2_5 (0x20UL << FMC_PMEM2_MEMWAIT2_Pos)

0x00002000

◆ FMC_PMEM2_MEMWAIT2_6

#define FMC_PMEM2_MEMWAIT2_6 (0x40UL << FMC_PMEM2_MEMWAIT2_Pos)

0x00004000

◆ FMC_PMEM2_MEMWAIT2_7

#define FMC_PMEM2_MEMWAIT2_7 (0x80UL << FMC_PMEM2_MEMWAIT2_Pos)

0x00008000

◆ FMC_PMEM2_MEMWAIT2_Msk

#define FMC_PMEM2_MEMWAIT2_Msk (0xFFUL << FMC_PMEM2_MEMWAIT2_Pos)

0x0000FF00

◆ FMC_PMEM2_MEMWAIT2_Pos

#define FMC_PMEM2_MEMWAIT2_Pos (8U)

◆ FMC_PMEM3_MEMHIZ3

#define FMC_PMEM3_MEMHIZ3 FMC_PMEM3_MEMHIZ3_Msk

MEMHIZ3[7:0] bits (Common memory 3 databus HiZ time)

◆ FMC_PMEM3_MEMHIZ3_0

#define FMC_PMEM3_MEMHIZ3_0 (0x01UL << FMC_PMEM3_MEMHIZ3_Pos)

0x01000000

◆ FMC_PMEM3_MEMHIZ3_1

#define FMC_PMEM3_MEMHIZ3_1 (0x02UL << FMC_PMEM3_MEMHIZ3_Pos)

0x02000000

◆ FMC_PMEM3_MEMHIZ3_2

#define FMC_PMEM3_MEMHIZ3_2 (0x04UL << FMC_PMEM3_MEMHIZ3_Pos)

0x04000000

◆ FMC_PMEM3_MEMHIZ3_3

#define FMC_PMEM3_MEMHIZ3_3 (0x08UL << FMC_PMEM3_MEMHIZ3_Pos)

0x08000000

◆ FMC_PMEM3_MEMHIZ3_4

#define FMC_PMEM3_MEMHIZ3_4 (0x10UL << FMC_PMEM3_MEMHIZ3_Pos)

0x10000000

◆ FMC_PMEM3_MEMHIZ3_5

#define FMC_PMEM3_MEMHIZ3_5 (0x20UL << FMC_PMEM3_MEMHIZ3_Pos)

0x20000000

◆ FMC_PMEM3_MEMHIZ3_6

#define FMC_PMEM3_MEMHIZ3_6 (0x40UL << FMC_PMEM3_MEMHIZ3_Pos)

0x40000000

◆ FMC_PMEM3_MEMHIZ3_7

#define FMC_PMEM3_MEMHIZ3_7 (0x80UL << FMC_PMEM3_MEMHIZ3_Pos)

0x80000000

◆ FMC_PMEM3_MEMHIZ3_Msk

#define FMC_PMEM3_MEMHIZ3_Msk (0xFFUL << FMC_PMEM3_MEMHIZ3_Pos)

0xFF000000

◆ FMC_PMEM3_MEMHIZ3_Pos

#define FMC_PMEM3_MEMHIZ3_Pos (24U)

◆ FMC_PMEM3_MEMHOLD3

#define FMC_PMEM3_MEMHOLD3 FMC_PMEM3_MEMHOLD3_Msk

MEMHOLD3[7:0] bits (Common memory 3 hold time)

◆ FMC_PMEM3_MEMHOLD3_0

#define FMC_PMEM3_MEMHOLD3_0 (0x01UL << FMC_PMEM3_MEMHOLD3_Pos)

0x00010000

◆ FMC_PMEM3_MEMHOLD3_1

#define FMC_PMEM3_MEMHOLD3_1 (0x02UL << FMC_PMEM3_MEMHOLD3_Pos)

0x00020000

◆ FMC_PMEM3_MEMHOLD3_2

#define FMC_PMEM3_MEMHOLD3_2 (0x04UL << FMC_PMEM3_MEMHOLD3_Pos)

0x00040000

◆ FMC_PMEM3_MEMHOLD3_3

#define FMC_PMEM3_MEMHOLD3_3 (0x08UL << FMC_PMEM3_MEMHOLD3_Pos)

0x00080000

◆ FMC_PMEM3_MEMHOLD3_4

#define FMC_PMEM3_MEMHOLD3_4 (0x10UL << FMC_PMEM3_MEMHOLD3_Pos)

0x00100000

◆ FMC_PMEM3_MEMHOLD3_5

#define FMC_PMEM3_MEMHOLD3_5 (0x20UL << FMC_PMEM3_MEMHOLD3_Pos)

0x00200000

◆ FMC_PMEM3_MEMHOLD3_6

#define FMC_PMEM3_MEMHOLD3_6 (0x40UL << FMC_PMEM3_MEMHOLD3_Pos)

0x00400000

◆ FMC_PMEM3_MEMHOLD3_7

#define FMC_PMEM3_MEMHOLD3_7 (0x80UL << FMC_PMEM3_MEMHOLD3_Pos)

0x00800000

◆ FMC_PMEM3_MEMHOLD3_Msk

#define FMC_PMEM3_MEMHOLD3_Msk (0xFFUL << FMC_PMEM3_MEMHOLD3_Pos)

0x00FF0000

◆ FMC_PMEM3_MEMHOLD3_Pos

#define FMC_PMEM3_MEMHOLD3_Pos (16U)

◆ FMC_PMEM3_MEMSET3

#define FMC_PMEM3_MEMSET3 FMC_PMEM3_MEMSET3_Msk

MEMSET3[7:0] bits (Common memory 3 setup time)

◆ FMC_PMEM3_MEMSET3_0

#define FMC_PMEM3_MEMSET3_0 (0x01UL << FMC_PMEM3_MEMSET3_Pos)

0x00000001

◆ FMC_PMEM3_MEMSET3_1

#define FMC_PMEM3_MEMSET3_1 (0x02UL << FMC_PMEM3_MEMSET3_Pos)

0x00000002

◆ FMC_PMEM3_MEMSET3_2

#define FMC_PMEM3_MEMSET3_2 (0x04UL << FMC_PMEM3_MEMSET3_Pos)

0x00000004

◆ FMC_PMEM3_MEMSET3_3

#define FMC_PMEM3_MEMSET3_3 (0x08UL << FMC_PMEM3_MEMSET3_Pos)

0x00000008

◆ FMC_PMEM3_MEMSET3_4

#define FMC_PMEM3_MEMSET3_4 (0x10UL << FMC_PMEM3_MEMSET3_Pos)

0x00000010

◆ FMC_PMEM3_MEMSET3_5

#define FMC_PMEM3_MEMSET3_5 (0x20UL << FMC_PMEM3_MEMSET3_Pos)

0x00000020

◆ FMC_PMEM3_MEMSET3_6

#define FMC_PMEM3_MEMSET3_6 (0x40UL << FMC_PMEM3_MEMSET3_Pos)

0x00000040

◆ FMC_PMEM3_MEMSET3_7

#define FMC_PMEM3_MEMSET3_7 (0x80UL << FMC_PMEM3_MEMSET3_Pos)

0x00000080

◆ FMC_PMEM3_MEMSET3_Msk

#define FMC_PMEM3_MEMSET3_Msk (0xFFUL << FMC_PMEM3_MEMSET3_Pos)

0x000000FF

◆ FMC_PMEM3_MEMSET3_Pos

#define FMC_PMEM3_MEMSET3_Pos (0U)

◆ FMC_PMEM3_MEMWAIT3

#define FMC_PMEM3_MEMWAIT3 FMC_PMEM3_MEMWAIT3_Msk

MEMWAIT3[7:0] bits (Common memory 3 wait time)

◆ FMC_PMEM3_MEMWAIT3_0

#define FMC_PMEM3_MEMWAIT3_0 (0x01UL << FMC_PMEM3_MEMWAIT3_Pos)

0x00000100

◆ FMC_PMEM3_MEMWAIT3_1

#define FMC_PMEM3_MEMWAIT3_1 (0x02UL << FMC_PMEM3_MEMWAIT3_Pos)

0x00000200

◆ FMC_PMEM3_MEMWAIT3_2

#define FMC_PMEM3_MEMWAIT3_2 (0x04UL << FMC_PMEM3_MEMWAIT3_Pos)

0x00000400

◆ FMC_PMEM3_MEMWAIT3_3

#define FMC_PMEM3_MEMWAIT3_3 (0x08UL << FMC_PMEM3_MEMWAIT3_Pos)

0x00000800

◆ FMC_PMEM3_MEMWAIT3_4

#define FMC_PMEM3_MEMWAIT3_4 (0x10UL << FMC_PMEM3_MEMWAIT3_Pos)

0x00001000

◆ FMC_PMEM3_MEMWAIT3_5

#define FMC_PMEM3_MEMWAIT3_5 (0x20UL << FMC_PMEM3_MEMWAIT3_Pos)

0x00002000

◆ FMC_PMEM3_MEMWAIT3_6

#define FMC_PMEM3_MEMWAIT3_6 (0x40UL << FMC_PMEM3_MEMWAIT3_Pos)

0x00004000

◆ FMC_PMEM3_MEMWAIT3_7

#define FMC_PMEM3_MEMWAIT3_7 (0x80UL << FMC_PMEM3_MEMWAIT3_Pos)

0x00008000

◆ FMC_PMEM3_MEMWAIT3_Msk

#define FMC_PMEM3_MEMWAIT3_Msk (0xFFUL << FMC_PMEM3_MEMWAIT3_Pos)

0x0000FF00

◆ FMC_PMEM3_MEMWAIT3_Pos

#define FMC_PMEM3_MEMWAIT3_Pos (8U)

◆ FMC_PMEM4_MEMHIZ4

#define FMC_PMEM4_MEMHIZ4 FMC_PMEM4_MEMHIZ4_Msk

MEMHIZ4[7:0] bits (Common memory 4 databus HiZ time)

◆ FMC_PMEM4_MEMHIZ4_0

#define FMC_PMEM4_MEMHIZ4_0 (0x01UL << FMC_PMEM4_MEMHIZ4_Pos)

0x01000000

◆ FMC_PMEM4_MEMHIZ4_1

#define FMC_PMEM4_MEMHIZ4_1 (0x02UL << FMC_PMEM4_MEMHIZ4_Pos)

0x02000000

◆ FMC_PMEM4_MEMHIZ4_2

#define FMC_PMEM4_MEMHIZ4_2 (0x04UL << FMC_PMEM4_MEMHIZ4_Pos)

0x04000000

◆ FMC_PMEM4_MEMHIZ4_3

#define FMC_PMEM4_MEMHIZ4_3 (0x08UL << FMC_PMEM4_MEMHIZ4_Pos)

0x08000000

◆ FMC_PMEM4_MEMHIZ4_4

#define FMC_PMEM4_MEMHIZ4_4 (0x10UL << FMC_PMEM4_MEMHIZ4_Pos)

0x10000000

◆ FMC_PMEM4_MEMHIZ4_5

#define FMC_PMEM4_MEMHIZ4_5 (0x20UL << FMC_PMEM4_MEMHIZ4_Pos)

0x20000000

◆ FMC_PMEM4_MEMHIZ4_6

#define FMC_PMEM4_MEMHIZ4_6 (0x40UL << FMC_PMEM4_MEMHIZ4_Pos)

0x40000000

◆ FMC_PMEM4_MEMHIZ4_7

#define FMC_PMEM4_MEMHIZ4_7 (0x80UL << FMC_PMEM4_MEMHIZ4_Pos)

0x80000000

◆ FMC_PMEM4_MEMHIZ4_Msk

#define FMC_PMEM4_MEMHIZ4_Msk (0xFFUL << FMC_PMEM4_MEMHIZ4_Pos)

0xFF000000

◆ FMC_PMEM4_MEMHIZ4_Pos

#define FMC_PMEM4_MEMHIZ4_Pos (24U)

◆ FMC_PMEM4_MEMHOLD4

#define FMC_PMEM4_MEMHOLD4 FMC_PMEM4_MEMHOLD4_Msk

MEMHOLD4[7:0] bits (Common memory 4 hold time)

◆ FMC_PMEM4_MEMHOLD4_0

#define FMC_PMEM4_MEMHOLD4_0 (0x01UL << FMC_PMEM4_MEMHOLD4_Pos)

0x00010000

◆ FMC_PMEM4_MEMHOLD4_1

#define FMC_PMEM4_MEMHOLD4_1 (0x02UL << FMC_PMEM4_MEMHOLD4_Pos)

0x00020000

◆ FMC_PMEM4_MEMHOLD4_2

#define FMC_PMEM4_MEMHOLD4_2 (0x04UL << FMC_PMEM4_MEMHOLD4_Pos)

0x00040000

◆ FMC_PMEM4_MEMHOLD4_3

#define FMC_PMEM4_MEMHOLD4_3 (0x08UL << FMC_PMEM4_MEMHOLD4_Pos)

0x00080000

◆ FMC_PMEM4_MEMHOLD4_4

#define FMC_PMEM4_MEMHOLD4_4 (0x10UL << FMC_PMEM4_MEMHOLD4_Pos)

0x00100000

◆ FMC_PMEM4_MEMHOLD4_5

#define FMC_PMEM4_MEMHOLD4_5 (0x20UL << FMC_PMEM4_MEMHOLD4_Pos)

0x00200000

◆ FMC_PMEM4_MEMHOLD4_6

#define FMC_PMEM4_MEMHOLD4_6 (0x40UL << FMC_PMEM4_MEMHOLD4_Pos)

0x00400000

◆ FMC_PMEM4_MEMHOLD4_7

#define FMC_PMEM4_MEMHOLD4_7 (0x80UL << FMC_PMEM4_MEMHOLD4_Pos)

0x00800000

◆ FMC_PMEM4_MEMHOLD4_Msk

#define FMC_PMEM4_MEMHOLD4_Msk (0xFFUL << FMC_PMEM4_MEMHOLD4_Pos)

0x00FF0000

◆ FMC_PMEM4_MEMHOLD4_Pos

#define FMC_PMEM4_MEMHOLD4_Pos (16U)

◆ FMC_PMEM4_MEMSET4

#define FMC_PMEM4_MEMSET4 FMC_PMEM4_MEMSET4_Msk

MEMSET4[7:0] bits (Common memory 4 setup time)

◆ FMC_PMEM4_MEMSET4_0

#define FMC_PMEM4_MEMSET4_0 (0x01UL << FMC_PMEM4_MEMSET4_Pos)

0x00000001

◆ FMC_PMEM4_MEMSET4_1

#define FMC_PMEM4_MEMSET4_1 (0x02UL << FMC_PMEM4_MEMSET4_Pos)

0x00000002

◆ FMC_PMEM4_MEMSET4_2

#define FMC_PMEM4_MEMSET4_2 (0x04UL << FMC_PMEM4_MEMSET4_Pos)

0x00000004

◆ FMC_PMEM4_MEMSET4_3

#define FMC_PMEM4_MEMSET4_3 (0x08UL << FMC_PMEM4_MEMSET4_Pos)

0x00000008

◆ FMC_PMEM4_MEMSET4_4

#define FMC_PMEM4_MEMSET4_4 (0x10UL << FMC_PMEM4_MEMSET4_Pos)

0x00000010

◆ FMC_PMEM4_MEMSET4_5

#define FMC_PMEM4_MEMSET4_5 (0x20UL << FMC_PMEM4_MEMSET4_Pos)

0x00000020

◆ FMC_PMEM4_MEMSET4_6

#define FMC_PMEM4_MEMSET4_6 (0x40UL << FMC_PMEM4_MEMSET4_Pos)

0x00000040

◆ FMC_PMEM4_MEMSET4_7

#define FMC_PMEM4_MEMSET4_7 (0x80UL << FMC_PMEM4_MEMSET4_Pos)

0x00000080

◆ FMC_PMEM4_MEMSET4_Msk

#define FMC_PMEM4_MEMSET4_Msk (0xFFUL << FMC_PMEM4_MEMSET4_Pos)

0x000000FF

◆ FMC_PMEM4_MEMSET4_Pos

#define FMC_PMEM4_MEMSET4_Pos (0U)

◆ FMC_PMEM4_MEMWAIT4

#define FMC_PMEM4_MEMWAIT4 FMC_PMEM4_MEMWAIT4_Msk

MEMWAIT4[7:0] bits (Common memory 4 wait time)

◆ FMC_PMEM4_MEMWAIT4_0

#define FMC_PMEM4_MEMWAIT4_0 (0x01UL << FMC_PMEM4_MEMWAIT4_Pos)

0x00000100

◆ FMC_PMEM4_MEMWAIT4_1

#define FMC_PMEM4_MEMWAIT4_1 (0x02UL << FMC_PMEM4_MEMWAIT4_Pos)

0x00000200

◆ FMC_PMEM4_MEMWAIT4_2

#define FMC_PMEM4_MEMWAIT4_2 (0x04UL << FMC_PMEM4_MEMWAIT4_Pos)

0x00000400

◆ FMC_PMEM4_MEMWAIT4_3

#define FMC_PMEM4_MEMWAIT4_3 (0x08UL << FMC_PMEM4_MEMWAIT4_Pos)

0x00000800

◆ FMC_PMEM4_MEMWAIT4_4

#define FMC_PMEM4_MEMWAIT4_4 (0x10UL << FMC_PMEM4_MEMWAIT4_Pos)

0x00001000

◆ FMC_PMEM4_MEMWAIT4_5

#define FMC_PMEM4_MEMWAIT4_5 (0x20UL << FMC_PMEM4_MEMWAIT4_Pos)

0x00002000

◆ FMC_PMEM4_MEMWAIT4_6

#define FMC_PMEM4_MEMWAIT4_6 (0x40UL << FMC_PMEM4_MEMWAIT4_Pos)

0x00004000

◆ FMC_PMEM4_MEMWAIT4_7

#define FMC_PMEM4_MEMWAIT4_7 (0x80UL << FMC_PMEM4_MEMWAIT4_Pos)

0x00008000

◆ FMC_PMEM4_MEMWAIT4_Msk

#define FMC_PMEM4_MEMWAIT4_Msk (0xFFUL << FMC_PMEM4_MEMWAIT4_Pos)

0x0000FF00

◆ FMC_PMEM4_MEMWAIT4_Pos

#define FMC_PMEM4_MEMWAIT4_Pos (8U)

◆ FMC_PMEMx_MEMHIZx

#define FMC_PMEMx_MEMHIZx FMC_PMEMx_MEMHIZx_Msk

MEMHIZx[7:0] bits (Common memory x databus HiZ time)

◆ FMC_PMEMx_MEMHIZx_0

#define FMC_PMEMx_MEMHIZx_0 (0x01UL << FMC_PMEMx_MEMHIZx_Pos)

0x01000000

◆ FMC_PMEMx_MEMHIZx_1

#define FMC_PMEMx_MEMHIZx_1 (0x02UL << FMC_PMEMx_MEMHIZx_Pos)

0x02000000

◆ FMC_PMEMx_MEMHIZx_2

#define FMC_PMEMx_MEMHIZx_2 (0x04UL << FMC_PMEMx_MEMHIZx_Pos)

0x04000000

◆ FMC_PMEMx_MEMHIZx_3

#define FMC_PMEMx_MEMHIZx_3 (0x08UL << FMC_PMEMx_MEMHIZx_Pos)

0x08000000

◆ FMC_PMEMx_MEMHIZx_4

#define FMC_PMEMx_MEMHIZx_4 (0x10UL << FMC_PMEMx_MEMHIZx_Pos)

0x10000000

◆ FMC_PMEMx_MEMHIZx_5

#define FMC_PMEMx_MEMHIZx_5 (0x20UL << FMC_PMEMx_MEMHIZx_Pos)

0x20000000

◆ FMC_PMEMx_MEMHIZx_6

#define FMC_PMEMx_MEMHIZx_6 (0x40UL << FMC_PMEMx_MEMHIZx_Pos)

0x40000000

◆ FMC_PMEMx_MEMHIZx_7

#define FMC_PMEMx_MEMHIZx_7 (0x80UL << FMC_PMEMx_MEMHIZx_Pos)

0x80000000

◆ FMC_PMEMx_MEMHIZx_Msk

#define FMC_PMEMx_MEMHIZx_Msk (0xFFUL << FMC_PMEMx_MEMHIZx_Pos)

0xFF000000

◆ FMC_PMEMx_MEMHIZx_Pos

#define FMC_PMEMx_MEMHIZx_Pos (24U)

◆ FMC_PMEMx_MEMHOLDx

#define FMC_PMEMx_MEMHOLDx FMC_PMEMx_MEMHOLDx_Msk

MEMHOLDx[7:0] bits (Common memory x hold time)

◆ FMC_PMEMx_MEMHOLDx_0

#define FMC_PMEMx_MEMHOLDx_0 (0x01UL << FMC_PMEMx_MEMHOLDx_Pos)

0x00010000

◆ FMC_PMEMx_MEMHOLDx_1

#define FMC_PMEMx_MEMHOLDx_1 (0x02UL << FMC_PMEMx_MEMHOLDx_Pos)

0x00020000

◆ FMC_PMEMx_MEMHOLDx_2

#define FMC_PMEMx_MEMHOLDx_2 (0x04UL << FMC_PMEMx_MEMHOLDx_Pos)

0x00040000

◆ FMC_PMEMx_MEMHOLDx_3

#define FMC_PMEMx_MEMHOLDx_3 (0x08UL << FMC_PMEMx_MEMHOLDx_Pos)

0x00080000

◆ FMC_PMEMx_MEMHOLDx_4

#define FMC_PMEMx_MEMHOLDx_4 (0x10UL << FMC_PMEMx_MEMHOLDx_Pos)

0x00100000

◆ FMC_PMEMx_MEMHOLDx_5

#define FMC_PMEMx_MEMHOLDx_5 (0x20UL << FMC_PMEMx_MEMHOLDx_Pos)

0x00200000

◆ FMC_PMEMx_MEMHOLDx_6

#define FMC_PMEMx_MEMHOLDx_6 (0x40UL << FMC_PMEMx_MEMHOLDx_Pos)

0x00400000

◆ FMC_PMEMx_MEMHOLDx_7

#define FMC_PMEMx_MEMHOLDx_7 (0x80UL << FMC_PMEMx_MEMHOLDx_Pos)

0x00800000

◆ FMC_PMEMx_MEMHOLDx_Msk

#define FMC_PMEMx_MEMHOLDx_Msk (0xFFUL << FMC_PMEMx_MEMHOLDx_Pos)

0x00FF0000

◆ FMC_PMEMx_MEMHOLDx_Pos

#define FMC_PMEMx_MEMHOLDx_Pos (16U)

◆ FMC_PMEMx_MEMSETx

#define FMC_PMEMx_MEMSETx FMC_PMEMx_MEMSETx_Msk

MEMSETx[7:0] bits (Common memory x setup time)

◆ FMC_PMEMx_MEMSETx_0

#define FMC_PMEMx_MEMSETx_0 (0x01UL << FMC_PMEMx_MEMSETx_Pos)

0x00000001

◆ FMC_PMEMx_MEMSETx_1

#define FMC_PMEMx_MEMSETx_1 (0x02UL << FMC_PMEMx_MEMSETx_Pos)

0x00000002

◆ FMC_PMEMx_MEMSETx_2

#define FMC_PMEMx_MEMSETx_2 (0x04UL << FMC_PMEMx_MEMSETx_Pos)

0x00000004

◆ FMC_PMEMx_MEMSETx_3

#define FMC_PMEMx_MEMSETx_3 (0x08UL << FMC_PMEMx_MEMSETx_Pos)

0x00000008

◆ FMC_PMEMx_MEMSETx_4

#define FMC_PMEMx_MEMSETx_4 (0x10UL << FMC_PMEMx_MEMSETx_Pos)

0x00000010

◆ FMC_PMEMx_MEMSETx_5

#define FMC_PMEMx_MEMSETx_5 (0x20UL << FMC_PMEMx_MEMSETx_Pos)

0x00000020

◆ FMC_PMEMx_MEMSETx_6

#define FMC_PMEMx_MEMSETx_6 (0x40UL << FMC_PMEMx_MEMSETx_Pos)

0x00000040

◆ FMC_PMEMx_MEMSETx_7

#define FMC_PMEMx_MEMSETx_7 (0x80UL << FMC_PMEMx_MEMSETx_Pos)

0x00000080

◆ FMC_PMEMx_MEMSETx_Msk

#define FMC_PMEMx_MEMSETx_Msk (0xFFUL << FMC_PMEMx_MEMSETx_Pos)

0x000000FF

◆ FMC_PMEMx_MEMSETx_Pos

#define FMC_PMEMx_MEMSETx_Pos (0U)

◆ FMC_PMEMx_MEMWAITx

#define FMC_PMEMx_MEMWAITx FMC_PMEMx_MEMWAITx_Msk

MEMWAITx[7:0] bits (Common memory x wait time)

◆ FMC_PMEMx_MEMWAITx_0

#define FMC_PMEMx_MEMWAITx_0 (0x01UL << FMC_PMEMx_MEMWAITx_Pos)

0x00000100

◆ FMC_PMEMx_MEMWAITx_1

#define FMC_PMEMx_MEMWAITx_1 (0x02UL << FMC_PMEMx_MEMWAITx_Pos)

0x00000200

◆ FMC_PMEMx_MEMWAITx_2

#define FMC_PMEMx_MEMWAITx_2 (0x04UL << FMC_PMEMx_MEMWAITx_Pos)

0x00000400

◆ FMC_PMEMx_MEMWAITx_3

#define FMC_PMEMx_MEMWAITx_3 (0x08UL << FMC_PMEMx_MEMWAITx_Pos)

0x00000800

◆ FMC_PMEMx_MEMWAITx_4

#define FMC_PMEMx_MEMWAITx_4 (0x10UL << FMC_PMEMx_MEMWAITx_Pos)

0x00001000

◆ FMC_PMEMx_MEMWAITx_5

#define FMC_PMEMx_MEMWAITx_5 (0x20UL << FMC_PMEMx_MEMWAITx_Pos)

0x00002000

◆ FMC_PMEMx_MEMWAITx_6

#define FMC_PMEMx_MEMWAITx_6 (0x40UL << FMC_PMEMx_MEMWAITx_Pos)

0x00004000

◆ FMC_PMEMx_MEMWAITx_7

#define FMC_PMEMx_MEMWAITx_7 (0x80UL << FMC_PMEMx_MEMWAITx_Pos)

0x00008000

◆ FMC_PMEMx_MEMWAITx_Msk

#define FMC_PMEMx_MEMWAITx_Msk (0xFFUL << FMC_PMEMx_MEMWAITx_Pos)

0x0000FF00

◆ FMC_PMEMx_MEMWAITx_Pos

#define FMC_PMEMx_MEMWAITx_Pos (8U)

◆ FMC_SR2_FEMPT

#define FMC_SR2_FEMPT FMC_SR2_FEMPT_Msk

FIFO empty

◆ FMC_SR2_FEMPT_Msk

#define FMC_SR2_FEMPT_Msk (0x1UL << FMC_SR2_FEMPT_Pos)

0x00000040

◆ FMC_SR2_FEMPT_Pos

#define FMC_SR2_FEMPT_Pos (6U)

◆ FMC_SR2_IFEN

#define FMC_SR2_IFEN FMC_SR2_IFEN_Msk

Interrupt Falling Edge detection Enable bit

◆ FMC_SR2_IFEN_Msk

#define FMC_SR2_IFEN_Msk (0x1UL << FMC_SR2_IFEN_Pos)

0x00000020

◆ FMC_SR2_IFEN_Pos

#define FMC_SR2_IFEN_Pos (5U)

◆ FMC_SR2_IFS

#define FMC_SR2_IFS FMC_SR2_IFS_Msk

Interrupt Falling Edge status

◆ FMC_SR2_IFS_Msk

#define FMC_SR2_IFS_Msk (0x1UL << FMC_SR2_IFS_Pos)

0x00000004

◆ FMC_SR2_IFS_Pos

#define FMC_SR2_IFS_Pos (2U)

◆ FMC_SR2_ILEN

#define FMC_SR2_ILEN FMC_SR2_ILEN_Msk

Interrupt Level detection Enable bit

◆ FMC_SR2_ILEN_Msk

#define FMC_SR2_ILEN_Msk (0x1UL << FMC_SR2_ILEN_Pos)

0x00000010

◆ FMC_SR2_ILEN_Pos

#define FMC_SR2_ILEN_Pos (4U)

◆ FMC_SR2_ILS

#define FMC_SR2_ILS FMC_SR2_ILS_Msk

Interrupt Level status

◆ FMC_SR2_ILS_Msk

#define FMC_SR2_ILS_Msk (0x1UL << FMC_SR2_ILS_Pos)

0x00000002

◆ FMC_SR2_ILS_Pos

#define FMC_SR2_ILS_Pos (1U)

◆ FMC_SR2_IREN

#define FMC_SR2_IREN FMC_SR2_IREN_Msk

Interrupt Rising Edge detection Enable bit

◆ FMC_SR2_IREN_Msk

#define FMC_SR2_IREN_Msk (0x1UL << FMC_SR2_IREN_Pos)

0x00000008

◆ FMC_SR2_IREN_Pos

#define FMC_SR2_IREN_Pos (3U)

◆ FMC_SR2_IRS

#define FMC_SR2_IRS FMC_SR2_IRS_Msk

Interrupt Rising Edge status

◆ FMC_SR2_IRS_Msk

#define FMC_SR2_IRS_Msk (0x1UL << FMC_SR2_IRS_Pos)

0x00000001

◆ FMC_SR2_IRS_Pos

#define FMC_SR2_IRS_Pos (0U)

◆ FMC_SR3_FEMPT

#define FMC_SR3_FEMPT FMC_SR3_FEMPT_Msk

FIFO empty

◆ FMC_SR3_FEMPT_Msk

#define FMC_SR3_FEMPT_Msk (0x1UL << FMC_SR3_FEMPT_Pos)

0x00000040

◆ FMC_SR3_FEMPT_Pos

#define FMC_SR3_FEMPT_Pos (6U)

◆ FMC_SR3_IFEN

#define FMC_SR3_IFEN FMC_SR3_IFEN_Msk

Interrupt Falling Edge detection Enable bit

◆ FMC_SR3_IFEN_Msk

#define FMC_SR3_IFEN_Msk (0x1UL << FMC_SR3_IFEN_Pos)

0x00000020

◆ FMC_SR3_IFEN_Pos

#define FMC_SR3_IFEN_Pos (5U)

◆ FMC_SR3_IFS

#define FMC_SR3_IFS FMC_SR3_IFS_Msk

Interrupt Falling Edge status

◆ FMC_SR3_IFS_Msk

#define FMC_SR3_IFS_Msk (0x1UL << FMC_SR3_IFS_Pos)

0x00000004

◆ FMC_SR3_IFS_Pos

#define FMC_SR3_IFS_Pos (2U)

◆ FMC_SR3_ILEN

#define FMC_SR3_ILEN FMC_SR3_ILEN_Msk

Interrupt Level detection Enable bit

◆ FMC_SR3_ILEN_Msk

#define FMC_SR3_ILEN_Msk (0x1UL << FMC_SR3_ILEN_Pos)

0x00000010

◆ FMC_SR3_ILEN_Pos

#define FMC_SR3_ILEN_Pos (4U)

◆ FMC_SR3_ILS

#define FMC_SR3_ILS FMC_SR3_ILS_Msk

Interrupt Level status

◆ FMC_SR3_ILS_Msk

#define FMC_SR3_ILS_Msk (0x1UL << FMC_SR3_ILS_Pos)

0x00000002

◆ FMC_SR3_ILS_Pos

#define FMC_SR3_ILS_Pos (1U)

◆ FMC_SR3_IREN

#define FMC_SR3_IREN FMC_SR3_IREN_Msk

Interrupt Rising Edge detection Enable bit

◆ FMC_SR3_IREN_Msk

#define FMC_SR3_IREN_Msk (0x1UL << FMC_SR3_IREN_Pos)

0x00000008

◆ FMC_SR3_IREN_Pos

#define FMC_SR3_IREN_Pos (3U)

◆ FMC_SR3_IRS

#define FMC_SR3_IRS FMC_SR3_IRS_Msk

Interrupt Rising Edge status

◆ FMC_SR3_IRS_Msk

#define FMC_SR3_IRS_Msk (0x1UL << FMC_SR3_IRS_Pos)

0x00000001

◆ FMC_SR3_IRS_Pos

#define FMC_SR3_IRS_Pos (0U)

◆ FMC_SR4_FEMPT

#define FMC_SR4_FEMPT FMC_SR4_FEMPT_Msk

FIFO empty

◆ FMC_SR4_FEMPT_Msk

#define FMC_SR4_FEMPT_Msk (0x1UL << FMC_SR4_FEMPT_Pos)

0x00000040

◆ FMC_SR4_FEMPT_Pos

#define FMC_SR4_FEMPT_Pos (6U)

◆ FMC_SR4_IFEN

#define FMC_SR4_IFEN FMC_SR4_IFEN_Msk

Interrupt Falling Edge detection Enable bit

◆ FMC_SR4_IFEN_Msk

#define FMC_SR4_IFEN_Msk (0x1UL << FMC_SR4_IFEN_Pos)

0x00000020

◆ FMC_SR4_IFEN_Pos

#define FMC_SR4_IFEN_Pos (5U)

◆ FMC_SR4_IFS

#define FMC_SR4_IFS FMC_SR4_IFS_Msk

Interrupt Falling Edge status

◆ FMC_SR4_IFS_Msk

#define FMC_SR4_IFS_Msk (0x1UL << FMC_SR4_IFS_Pos)

0x00000004

◆ FMC_SR4_IFS_Pos

#define FMC_SR4_IFS_Pos (2U)

◆ FMC_SR4_ILEN

#define FMC_SR4_ILEN FMC_SR4_ILEN_Msk

Interrupt Level detection Enable bit

◆ FMC_SR4_ILEN_Msk

#define FMC_SR4_ILEN_Msk (0x1UL << FMC_SR4_ILEN_Pos)

0x00000010

◆ FMC_SR4_ILEN_Pos

#define FMC_SR4_ILEN_Pos (4U)

◆ FMC_SR4_ILS

#define FMC_SR4_ILS FMC_SR4_ILS_Msk

Interrupt Level status

◆ FMC_SR4_ILS_Msk

#define FMC_SR4_ILS_Msk (0x1UL << FMC_SR4_ILS_Pos)

0x00000002

◆ FMC_SR4_ILS_Pos

#define FMC_SR4_ILS_Pos (1U)

◆ FMC_SR4_IREN

#define FMC_SR4_IREN FMC_SR4_IREN_Msk

Interrupt Rising Edge detection Enable bit

◆ FMC_SR4_IREN_Msk

#define FMC_SR4_IREN_Msk (0x1UL << FMC_SR4_IREN_Pos)

0x00000008

◆ FMC_SR4_IREN_Pos

#define FMC_SR4_IREN_Pos (3U)

◆ FMC_SR4_IRS

#define FMC_SR4_IRS FMC_SR4_IRS_Msk

Interrupt Rising Edge status

◆ FMC_SR4_IRS_Msk

#define FMC_SR4_IRS_Msk (0x1UL << FMC_SR4_IRS_Pos)

0x00000001

◆ FMC_SR4_IRS_Pos

#define FMC_SR4_IRS_Pos (0U)

◆ FMC_SRx_FEMPT

#define FMC_SRx_FEMPT FMC_SRx_FEMPT_Msk

FIFO empty

◆ FMC_SRx_FEMPT_Msk

#define FMC_SRx_FEMPT_Msk (0x1UL << FMC_SRx_FEMPT_Pos)

0x00000040

◆ FMC_SRx_FEMPT_Pos

#define FMC_SRx_FEMPT_Pos (6U)

◆ FMC_SRx_IFEN

#define FMC_SRx_IFEN FMC_SRx_IFEN_Msk

Interrupt Falling Edge detection Enable bit

◆ FMC_SRx_IFEN_Msk

#define FMC_SRx_IFEN_Msk (0x1UL << FMC_SRx_IFEN_Pos)

0x00000020

◆ FMC_SRx_IFEN_Pos

#define FMC_SRx_IFEN_Pos (5U)

◆ FMC_SRx_IFS

#define FMC_SRx_IFS FMC_SRx_IFS_Msk

Interrupt Falling Edge status

◆ FMC_SRx_IFS_Msk

#define FMC_SRx_IFS_Msk (0x1UL << FMC_SRx_IFS_Pos)

0x00000004

◆ FMC_SRx_IFS_Pos

#define FMC_SRx_IFS_Pos (2U)

◆ FMC_SRx_ILEN

#define FMC_SRx_ILEN FMC_SRx_ILEN_Msk

Interrupt Level detection Enable bit

◆ FMC_SRx_ILEN_Msk

#define FMC_SRx_ILEN_Msk (0x1UL << FMC_SRx_ILEN_Pos)

0x00000010

◆ FMC_SRx_ILEN_Pos

#define FMC_SRx_ILEN_Pos (4U)

◆ FMC_SRx_ILS

#define FMC_SRx_ILS FMC_SRx_ILS_Msk

Interrupt Level status

◆ FMC_SRx_ILS_Msk

#define FMC_SRx_ILS_Msk (0x1UL << FMC_SRx_ILS_Pos)

0x00000002

◆ FMC_SRx_ILS_Pos

#define FMC_SRx_ILS_Pos (1U)

◆ FMC_SRx_IREN

#define FMC_SRx_IREN FMC_SRx_IREN_Msk

Interrupt Rising Edge detection Enable bit

◆ FMC_SRx_IREN_Msk

#define FMC_SRx_IREN_Msk (0x1UL << FMC_SRx_IREN_Pos)

0x00000008

◆ FMC_SRx_IREN_Pos

#define FMC_SRx_IREN_Pos (3U)

◆ FMC_SRx_IRS

#define FMC_SRx_IRS FMC_SRx_IRS_Msk

Interrupt Rising Edge status

◆ FMC_SRx_IRS_Msk

#define FMC_SRx_IRS_Msk (0x1UL << FMC_SRx_IRS_Pos)

0x00000001

◆ FMC_SRx_IRS_Pos

#define FMC_SRx_IRS_Pos (0U)

◆ GPIO_AFRH_AFRH0

#define GPIO_AFRH_AFRH0 GPIO_AFRH_AFRH0_Msk

◆ GPIO_AFRH_AFRH0_Msk

#define GPIO_AFRH_AFRH0_Msk (0xFUL << GPIO_AFRH_AFRH0_Pos)

0x0000000F

◆ GPIO_AFRH_AFRH0_Pos

#define GPIO_AFRH_AFRH0_Pos (0U)

◆ GPIO_AFRH_AFRH1

#define GPIO_AFRH_AFRH1 GPIO_AFRH_AFRH1_Msk

◆ GPIO_AFRH_AFRH1_Msk

#define GPIO_AFRH_AFRH1_Msk (0xFUL << GPIO_AFRH_AFRH1_Pos)

0x000000F0

◆ GPIO_AFRH_AFRH1_Pos

#define GPIO_AFRH_AFRH1_Pos (4U)

◆ GPIO_AFRH_AFRH2

#define GPIO_AFRH_AFRH2 GPIO_AFRH_AFRH2_Msk

◆ GPIO_AFRH_AFRH2_Msk

#define GPIO_AFRH_AFRH2_Msk (0xFUL << GPIO_AFRH_AFRH2_Pos)

0x00000F00

◆ GPIO_AFRH_AFRH2_Pos

#define GPIO_AFRH_AFRH2_Pos (8U)

◆ GPIO_AFRH_AFRH3

#define GPIO_AFRH_AFRH3 GPIO_AFRH_AFRH3_Msk

◆ GPIO_AFRH_AFRH3_Msk

#define GPIO_AFRH_AFRH3_Msk (0xFUL << GPIO_AFRH_AFRH3_Pos)

0x0000F000

◆ GPIO_AFRH_AFRH3_Pos

#define GPIO_AFRH_AFRH3_Pos (12U)

◆ GPIO_AFRH_AFRH4

#define GPIO_AFRH_AFRH4 GPIO_AFRH_AFRH4_Msk

◆ GPIO_AFRH_AFRH4_Msk

#define GPIO_AFRH_AFRH4_Msk (0xFUL << GPIO_AFRH_AFRH4_Pos)

0x000F0000

◆ GPIO_AFRH_AFRH4_Pos

#define GPIO_AFRH_AFRH4_Pos (16U)

◆ GPIO_AFRH_AFRH5

#define GPIO_AFRH_AFRH5 GPIO_AFRH_AFRH5_Msk

◆ GPIO_AFRH_AFRH5_Msk

#define GPIO_AFRH_AFRH5_Msk (0xFUL << GPIO_AFRH_AFRH5_Pos)

0x00F00000

◆ GPIO_AFRH_AFRH5_Pos

#define GPIO_AFRH_AFRH5_Pos (20U)

◆ GPIO_AFRH_AFRH6

#define GPIO_AFRH_AFRH6 GPIO_AFRH_AFRH6_Msk

◆ GPIO_AFRH_AFRH6_Msk

#define GPIO_AFRH_AFRH6_Msk (0xFUL << GPIO_AFRH_AFRH6_Pos)

0x0F000000

◆ GPIO_AFRH_AFRH6_Pos

#define GPIO_AFRH_AFRH6_Pos (24U)

◆ GPIO_AFRH_AFRH7

#define GPIO_AFRH_AFRH7 GPIO_AFRH_AFRH7_Msk

◆ GPIO_AFRH_AFRH7_Msk

#define GPIO_AFRH_AFRH7_Msk (0xFUL << GPIO_AFRH_AFRH7_Pos)

0xF0000000

◆ GPIO_AFRH_AFRH7_Pos

#define GPIO_AFRH_AFRH7_Pos (28U)

◆ GPIO_AFRL_AFRL0

#define GPIO_AFRL_AFRL0 GPIO_AFRL_AFRL0_Msk

◆ GPIO_AFRL_AFRL0_Msk

#define GPIO_AFRL_AFRL0_Msk (0xFUL << GPIO_AFRL_AFRL0_Pos)

0x0000000F

◆ GPIO_AFRL_AFRL0_Pos

#define GPIO_AFRL_AFRL0_Pos (0U)

◆ GPIO_AFRL_AFRL1

#define GPIO_AFRL_AFRL1 GPIO_AFRL_AFRL1_Msk

◆ GPIO_AFRL_AFRL1_Msk

#define GPIO_AFRL_AFRL1_Msk (0xFUL << GPIO_AFRL_AFRL1_Pos)

0x000000F0

◆ GPIO_AFRL_AFRL1_Pos

#define GPIO_AFRL_AFRL1_Pos (4U)

◆ GPIO_AFRL_AFRL2

#define GPIO_AFRL_AFRL2 GPIO_AFRL_AFRL2_Msk

◆ GPIO_AFRL_AFRL2_Msk

#define GPIO_AFRL_AFRL2_Msk (0xFUL << GPIO_AFRL_AFRL2_Pos)

0x00000F00

◆ GPIO_AFRL_AFRL2_Pos

#define GPIO_AFRL_AFRL2_Pos (8U)

◆ GPIO_AFRL_AFRL3

#define GPIO_AFRL_AFRL3 GPIO_AFRL_AFRL3_Msk

◆ GPIO_AFRL_AFRL3_Msk

#define GPIO_AFRL_AFRL3_Msk (0xFUL << GPIO_AFRL_AFRL3_Pos)

0x0000F000

◆ GPIO_AFRL_AFRL3_Pos

#define GPIO_AFRL_AFRL3_Pos (12U)

◆ GPIO_AFRL_AFRL4

#define GPIO_AFRL_AFRL4 GPIO_AFRL_AFRL4_Msk

◆ GPIO_AFRL_AFRL4_Msk

#define GPIO_AFRL_AFRL4_Msk (0xFUL << GPIO_AFRL_AFRL4_Pos)

0x000F0000

◆ GPIO_AFRL_AFRL4_Pos

#define GPIO_AFRL_AFRL4_Pos (16U)

◆ GPIO_AFRL_AFRL5

#define GPIO_AFRL_AFRL5 GPIO_AFRL_AFRL5_Msk

◆ GPIO_AFRL_AFRL5_Msk

#define GPIO_AFRL_AFRL5_Msk (0xFUL << GPIO_AFRL_AFRL5_Pos)

0x00F00000

◆ GPIO_AFRL_AFRL5_Pos

#define GPIO_AFRL_AFRL5_Pos (20U)

◆ GPIO_AFRL_AFRL6

#define GPIO_AFRL_AFRL6 GPIO_AFRL_AFRL6_Msk

◆ GPIO_AFRL_AFRL6_Msk

#define GPIO_AFRL_AFRL6_Msk (0xFUL << GPIO_AFRL_AFRL6_Pos)

0x0F000000

◆ GPIO_AFRL_AFRL6_Pos

#define GPIO_AFRL_AFRL6_Pos (24U)

◆ GPIO_AFRL_AFRL7

#define GPIO_AFRL_AFRL7 GPIO_AFRL_AFRL7_Msk

◆ GPIO_AFRL_AFRL7_Msk

#define GPIO_AFRL_AFRL7_Msk (0xFUL << GPIO_AFRL_AFRL7_Pos)

0xF0000000

◆ GPIO_AFRL_AFRL7_Pos

#define GPIO_AFRL_AFRL7_Pos (28U)

◆ GPIO_BRR_BR_0

#define GPIO_BRR_BR_0 (0x00000001U)

◆ GPIO_BRR_BR_1

#define GPIO_BRR_BR_1 (0x00000002U)

◆ GPIO_BRR_BR_10

#define GPIO_BRR_BR_10 (0x00000400U)

◆ GPIO_BRR_BR_11

#define GPIO_BRR_BR_11 (0x00000800U)

◆ GPIO_BRR_BR_12

#define GPIO_BRR_BR_12 (0x00001000U)

◆ GPIO_BRR_BR_13

#define GPIO_BRR_BR_13 (0x00002000U)

◆ GPIO_BRR_BR_14

#define GPIO_BRR_BR_14 (0x00004000U)

◆ GPIO_BRR_BR_15

#define GPIO_BRR_BR_15 (0x00008000U)

◆ GPIO_BRR_BR_2

#define GPIO_BRR_BR_2 (0x00000004U)

◆ GPIO_BRR_BR_3

#define GPIO_BRR_BR_3 (0x00000008U)

◆ GPIO_BRR_BR_4

#define GPIO_BRR_BR_4 (0x00000010U)

◆ GPIO_BRR_BR_5

#define GPIO_BRR_BR_5 (0x00000020U)

◆ GPIO_BRR_BR_6

#define GPIO_BRR_BR_6 (0x00000040U)

◆ GPIO_BRR_BR_7

#define GPIO_BRR_BR_7 (0x00000080U)

◆ GPIO_BRR_BR_8

#define GPIO_BRR_BR_8 (0x00000100U)

◆ GPIO_BRR_BR_9

#define GPIO_BRR_BR_9 (0x00000200U)

◆ GPIO_BSRR_BR_0

#define GPIO_BSRR_BR_0 (0x00010000U)

◆ GPIO_BSRR_BR_1

#define GPIO_BSRR_BR_1 (0x00020000U)

◆ GPIO_BSRR_BR_10

#define GPIO_BSRR_BR_10 (0x04000000U)

◆ GPIO_BSRR_BR_11

#define GPIO_BSRR_BR_11 (0x08000000U)

◆ GPIO_BSRR_BR_12

#define GPIO_BSRR_BR_12 (0x10000000U)

◆ GPIO_BSRR_BR_13

#define GPIO_BSRR_BR_13 (0x20000000U)

◆ GPIO_BSRR_BR_14

#define GPIO_BSRR_BR_14 (0x40000000U)

◆ GPIO_BSRR_BR_15

#define GPIO_BSRR_BR_15 (0x80000000U)

◆ GPIO_BSRR_BR_2

#define GPIO_BSRR_BR_2 (0x00040000U)

◆ GPIO_BSRR_BR_3

#define GPIO_BSRR_BR_3 (0x00080000U)

◆ GPIO_BSRR_BR_4

#define GPIO_BSRR_BR_4 (0x00100000U)

◆ GPIO_BSRR_BR_5

#define GPIO_BSRR_BR_5 (0x00200000U)

◆ GPIO_BSRR_BR_6

#define GPIO_BSRR_BR_6 (0x00400000U)

◆ GPIO_BSRR_BR_7

#define GPIO_BSRR_BR_7 (0x00800000U)

◆ GPIO_BSRR_BR_8

#define GPIO_BSRR_BR_8 (0x01000000U)

◆ GPIO_BSRR_BR_9

#define GPIO_BSRR_BR_9 (0x02000000U)

◆ GPIO_BSRR_BS_0

#define GPIO_BSRR_BS_0 (0x00000001U)

◆ GPIO_BSRR_BS_1

#define GPIO_BSRR_BS_1 (0x00000002U)

◆ GPIO_BSRR_BS_10

#define GPIO_BSRR_BS_10 (0x00000400U)

◆ GPIO_BSRR_BS_11

#define GPIO_BSRR_BS_11 (0x00000800U)

◆ GPIO_BSRR_BS_12

#define GPIO_BSRR_BS_12 (0x00001000U)

◆ GPIO_BSRR_BS_13

#define GPIO_BSRR_BS_13 (0x00002000U)

◆ GPIO_BSRR_BS_14

#define GPIO_BSRR_BS_14 (0x00004000U)

◆ GPIO_BSRR_BS_15

#define GPIO_BSRR_BS_15 (0x00008000U)

◆ GPIO_BSRR_BS_2

#define GPIO_BSRR_BS_2 (0x00000004U)

◆ GPIO_BSRR_BS_3

#define GPIO_BSRR_BS_3 (0x00000008U)

◆ GPIO_BSRR_BS_4

#define GPIO_BSRR_BS_4 (0x00000010U)

◆ GPIO_BSRR_BS_5

#define GPIO_BSRR_BS_5 (0x00000020U)

◆ GPIO_BSRR_BS_6

#define GPIO_BSRR_BS_6 (0x00000040U)

◆ GPIO_BSRR_BS_7

#define GPIO_BSRR_BS_7 (0x00000080U)

◆ GPIO_BSRR_BS_8

#define GPIO_BSRR_BS_8 (0x00000100U)

◆ GPIO_BSRR_BS_9

#define GPIO_BSRR_BS_9 (0x00000200U)

◆ GPIO_IDR_0

#define GPIO_IDR_0 (0x00000001U)

◆ GPIO_IDR_1

#define GPIO_IDR_1 (0x00000002U)

◆ GPIO_IDR_10

#define GPIO_IDR_10 (0x00000400U)

◆ GPIO_IDR_11

#define GPIO_IDR_11 (0x00000800U)

◆ GPIO_IDR_12

#define GPIO_IDR_12 (0x00001000U)

◆ GPIO_IDR_13

#define GPIO_IDR_13 (0x00002000U)

◆ GPIO_IDR_14

#define GPIO_IDR_14 (0x00004000U)

◆ GPIO_IDR_15

#define GPIO_IDR_15 (0x00008000U)

◆ GPIO_IDR_2

#define GPIO_IDR_2 (0x00000004U)

◆ GPIO_IDR_3

#define GPIO_IDR_3 (0x00000008U)

◆ GPIO_IDR_4

#define GPIO_IDR_4 (0x00000010U)

◆ GPIO_IDR_5

#define GPIO_IDR_5 (0x00000020U)

◆ GPIO_IDR_6

#define GPIO_IDR_6 (0x00000040U)

◆ GPIO_IDR_7

#define GPIO_IDR_7 (0x00000080U)

◆ GPIO_IDR_8

#define GPIO_IDR_8 (0x00000100U)

◆ GPIO_IDR_9

#define GPIO_IDR_9 (0x00000200U)

◆ GPIO_LCKR_LCK0

#define GPIO_LCKR_LCK0 GPIO_LCKR_LCK0_Msk

◆ GPIO_LCKR_LCK0_Msk

#define GPIO_LCKR_LCK0_Msk (0x1UL << GPIO_LCKR_LCK0_Pos)

0x00000001

◆ GPIO_LCKR_LCK0_Pos

#define GPIO_LCKR_LCK0_Pos (0U)

◆ GPIO_LCKR_LCK1

#define GPIO_LCKR_LCK1 GPIO_LCKR_LCK1_Msk

◆ GPIO_LCKR_LCK10

#define GPIO_LCKR_LCK10 GPIO_LCKR_LCK10_Msk

◆ GPIO_LCKR_LCK10_Msk

#define GPIO_LCKR_LCK10_Msk (0x1UL << GPIO_LCKR_LCK10_Pos)

0x00000400

◆ GPIO_LCKR_LCK10_Pos

#define GPIO_LCKR_LCK10_Pos (10U)

◆ GPIO_LCKR_LCK11

#define GPIO_LCKR_LCK11 GPIO_LCKR_LCK11_Msk

◆ GPIO_LCKR_LCK11_Msk

#define GPIO_LCKR_LCK11_Msk (0x1UL << GPIO_LCKR_LCK11_Pos)

0x00000800

◆ GPIO_LCKR_LCK11_Pos

#define GPIO_LCKR_LCK11_Pos (11U)

◆ GPIO_LCKR_LCK12

#define GPIO_LCKR_LCK12 GPIO_LCKR_LCK12_Msk

◆ GPIO_LCKR_LCK12_Msk

#define GPIO_LCKR_LCK12_Msk (0x1UL << GPIO_LCKR_LCK12_Pos)

0x00001000

◆ GPIO_LCKR_LCK12_Pos

#define GPIO_LCKR_LCK12_Pos (12U)

◆ GPIO_LCKR_LCK13

#define GPIO_LCKR_LCK13 GPIO_LCKR_LCK13_Msk

◆ GPIO_LCKR_LCK13_Msk

#define GPIO_LCKR_LCK13_Msk (0x1UL << GPIO_LCKR_LCK13_Pos)

0x00002000

◆ GPIO_LCKR_LCK13_Pos

#define GPIO_LCKR_LCK13_Pos (13U)

◆ GPIO_LCKR_LCK14

#define GPIO_LCKR_LCK14 GPIO_LCKR_LCK14_Msk

◆ GPIO_LCKR_LCK14_Msk

#define GPIO_LCKR_LCK14_Msk (0x1UL << GPIO_LCKR_LCK14_Pos)

0x00004000

◆ GPIO_LCKR_LCK14_Pos

#define GPIO_LCKR_LCK14_Pos (14U)

◆ GPIO_LCKR_LCK15

#define GPIO_LCKR_LCK15 GPIO_LCKR_LCK15_Msk

◆ GPIO_LCKR_LCK15_Msk

#define GPIO_LCKR_LCK15_Msk (0x1UL << GPIO_LCKR_LCK15_Pos)

0x00008000

◆ GPIO_LCKR_LCK15_Pos

#define GPIO_LCKR_LCK15_Pos (15U)

◆ GPIO_LCKR_LCK1_Msk

#define GPIO_LCKR_LCK1_Msk (0x1UL << GPIO_LCKR_LCK1_Pos)

0x00000002

◆ GPIO_LCKR_LCK1_Pos

#define GPIO_LCKR_LCK1_Pos (1U)

◆ GPIO_LCKR_LCK2

#define GPIO_LCKR_LCK2 GPIO_LCKR_LCK2_Msk

◆ GPIO_LCKR_LCK2_Msk

#define GPIO_LCKR_LCK2_Msk (0x1UL << GPIO_LCKR_LCK2_Pos)

0x00000004

◆ GPIO_LCKR_LCK2_Pos

#define GPIO_LCKR_LCK2_Pos (2U)

◆ GPIO_LCKR_LCK3

#define GPIO_LCKR_LCK3 GPIO_LCKR_LCK3_Msk

◆ GPIO_LCKR_LCK3_Msk

#define GPIO_LCKR_LCK3_Msk (0x1UL << GPIO_LCKR_LCK3_Pos)

0x00000008

◆ GPIO_LCKR_LCK3_Pos

#define GPIO_LCKR_LCK3_Pos (3U)

◆ GPIO_LCKR_LCK4

#define GPIO_LCKR_LCK4 GPIO_LCKR_LCK4_Msk

◆ GPIO_LCKR_LCK4_Msk

#define GPIO_LCKR_LCK4_Msk (0x1UL << GPIO_LCKR_LCK4_Pos)

0x00000010

◆ GPIO_LCKR_LCK4_Pos

#define GPIO_LCKR_LCK4_Pos (4U)

◆ GPIO_LCKR_LCK5

#define GPIO_LCKR_LCK5 GPIO_LCKR_LCK5_Msk

◆ GPIO_LCKR_LCK5_Msk

#define GPIO_LCKR_LCK5_Msk (0x1UL << GPIO_LCKR_LCK5_Pos)

0x00000020

◆ GPIO_LCKR_LCK5_Pos

#define GPIO_LCKR_LCK5_Pos (5U)

◆ GPIO_LCKR_LCK6

#define GPIO_LCKR_LCK6 GPIO_LCKR_LCK6_Msk

◆ GPIO_LCKR_LCK6_Msk

#define GPIO_LCKR_LCK6_Msk (0x1UL << GPIO_LCKR_LCK6_Pos)

0x00000040

◆ GPIO_LCKR_LCK6_Pos

#define GPIO_LCKR_LCK6_Pos (6U)

◆ GPIO_LCKR_LCK7

#define GPIO_LCKR_LCK7 GPIO_LCKR_LCK7_Msk

◆ GPIO_LCKR_LCK7_Msk

#define GPIO_LCKR_LCK7_Msk (0x1UL << GPIO_LCKR_LCK7_Pos)

0x00000080

◆ GPIO_LCKR_LCK7_Pos

#define GPIO_LCKR_LCK7_Pos (7U)

◆ GPIO_LCKR_LCK8

#define GPIO_LCKR_LCK8 GPIO_LCKR_LCK8_Msk

◆ GPIO_LCKR_LCK8_Msk

#define GPIO_LCKR_LCK8_Msk (0x1UL << GPIO_LCKR_LCK8_Pos)

0x00000100

◆ GPIO_LCKR_LCK8_Pos

#define GPIO_LCKR_LCK8_Pos (8U)

◆ GPIO_LCKR_LCK9

#define GPIO_LCKR_LCK9 GPIO_LCKR_LCK9_Msk

◆ GPIO_LCKR_LCK9_Msk

#define GPIO_LCKR_LCK9_Msk (0x1UL << GPIO_LCKR_LCK9_Pos)

0x00000200

◆ GPIO_LCKR_LCK9_Pos

#define GPIO_LCKR_LCK9_Pos (9U)

◆ GPIO_LCKR_LCKK

#define GPIO_LCKR_LCKK GPIO_LCKR_LCKK_Msk

◆ GPIO_LCKR_LCKK_Msk

#define GPIO_LCKR_LCKK_Msk (0x1UL << GPIO_LCKR_LCKK_Pos)

0x00010000

◆ GPIO_LCKR_LCKK_Pos

#define GPIO_LCKR_LCKK_Pos (16U)

◆ GPIO_MODER_MODER0

#define GPIO_MODER_MODER0 GPIO_MODER_MODER0_Msk

◆ GPIO_MODER_MODER0_0

#define GPIO_MODER_MODER0_0 (0x1UL << GPIO_MODER_MODER0_Pos)

0x00000001

◆ GPIO_MODER_MODER0_1

#define GPIO_MODER_MODER0_1 (0x2UL << GPIO_MODER_MODER0_Pos)

0x00000002

◆ GPIO_MODER_MODER0_Msk

#define GPIO_MODER_MODER0_Msk (0x3UL << GPIO_MODER_MODER0_Pos)

0x00000003

◆ GPIO_MODER_MODER0_Pos

#define GPIO_MODER_MODER0_Pos (0U)

◆ GPIO_MODER_MODER1

#define GPIO_MODER_MODER1 GPIO_MODER_MODER1_Msk

◆ GPIO_MODER_MODER10

#define GPIO_MODER_MODER10 GPIO_MODER_MODER10_Msk

◆ GPIO_MODER_MODER10_0

#define GPIO_MODER_MODER10_0 (0x1UL << GPIO_MODER_MODER10_Pos)

0x00100000

◆ GPIO_MODER_MODER10_1

#define GPIO_MODER_MODER10_1 (0x2UL << GPIO_MODER_MODER10_Pos)

0x00200000

◆ GPIO_MODER_MODER10_Msk

#define GPIO_MODER_MODER10_Msk (0x3UL << GPIO_MODER_MODER10_Pos)

0x00300000

◆ GPIO_MODER_MODER10_Pos

#define GPIO_MODER_MODER10_Pos (20U)

◆ GPIO_MODER_MODER11

#define GPIO_MODER_MODER11 GPIO_MODER_MODER11_Msk

◆ GPIO_MODER_MODER11_0

#define GPIO_MODER_MODER11_0 (0x1UL << GPIO_MODER_MODER11_Pos)

0x00400000

◆ GPIO_MODER_MODER11_1

#define GPIO_MODER_MODER11_1 (0x2UL << GPIO_MODER_MODER11_Pos)

0x00800000

◆ GPIO_MODER_MODER11_Msk

#define GPIO_MODER_MODER11_Msk (0x3UL << GPIO_MODER_MODER11_Pos)

0x00C00000

◆ GPIO_MODER_MODER11_Pos

#define GPIO_MODER_MODER11_Pos (22U)

◆ GPIO_MODER_MODER12

#define GPIO_MODER_MODER12 GPIO_MODER_MODER12_Msk

◆ GPIO_MODER_MODER12_0

#define GPIO_MODER_MODER12_0 (0x1UL << GPIO_MODER_MODER12_Pos)

0x01000000

◆ GPIO_MODER_MODER12_1

#define GPIO_MODER_MODER12_1 (0x2UL << GPIO_MODER_MODER12_Pos)

0x02000000

◆ GPIO_MODER_MODER12_Msk

#define GPIO_MODER_MODER12_Msk (0x3UL << GPIO_MODER_MODER12_Pos)

0x03000000

◆ GPIO_MODER_MODER12_Pos

#define GPIO_MODER_MODER12_Pos (24U)

◆ GPIO_MODER_MODER13

#define GPIO_MODER_MODER13 GPIO_MODER_MODER13_Msk

◆ GPIO_MODER_MODER13_0

#define GPIO_MODER_MODER13_0 (0x1UL << GPIO_MODER_MODER13_Pos)

0x04000000

◆ GPIO_MODER_MODER13_1

#define GPIO_MODER_MODER13_1 (0x2UL << GPIO_MODER_MODER13_Pos)

0x08000000

◆ GPIO_MODER_MODER13_Msk

#define GPIO_MODER_MODER13_Msk (0x3UL << GPIO_MODER_MODER13_Pos)

0x0C000000

◆ GPIO_MODER_MODER13_Pos

#define GPIO_MODER_MODER13_Pos (26U)

◆ GPIO_MODER_MODER14

#define GPIO_MODER_MODER14 GPIO_MODER_MODER14_Msk

◆ GPIO_MODER_MODER14_0

#define GPIO_MODER_MODER14_0 (0x1UL << GPIO_MODER_MODER14_Pos)

0x10000000

◆ GPIO_MODER_MODER14_1

#define GPIO_MODER_MODER14_1 (0x2UL << GPIO_MODER_MODER14_Pos)

0x20000000

◆ GPIO_MODER_MODER14_Msk

#define GPIO_MODER_MODER14_Msk (0x3UL << GPIO_MODER_MODER14_Pos)

0x30000000

◆ GPIO_MODER_MODER14_Pos

#define GPIO_MODER_MODER14_Pos (28U)

◆ GPIO_MODER_MODER15

#define GPIO_MODER_MODER15 GPIO_MODER_MODER15_Msk

◆ GPIO_MODER_MODER15_0

#define GPIO_MODER_MODER15_0 (0x1UL << GPIO_MODER_MODER15_Pos)

0x40000000

◆ GPIO_MODER_MODER15_1

#define GPIO_MODER_MODER15_1 (0x2UL << GPIO_MODER_MODER15_Pos)

0x80000000

◆ GPIO_MODER_MODER15_Msk

#define GPIO_MODER_MODER15_Msk (0x3UL << GPIO_MODER_MODER15_Pos)

0xC0000000

◆ GPIO_MODER_MODER15_Pos

#define GPIO_MODER_MODER15_Pos (30U)

◆ GPIO_MODER_MODER1_0

#define GPIO_MODER_MODER1_0 (0x1UL << GPIO_MODER_MODER1_Pos)

0x00000004

◆ GPIO_MODER_MODER1_1

#define GPIO_MODER_MODER1_1 (0x2UL << GPIO_MODER_MODER1_Pos)

0x00000008

◆ GPIO_MODER_MODER1_Msk

#define GPIO_MODER_MODER1_Msk (0x3UL << GPIO_MODER_MODER1_Pos)

0x0000000C

◆ GPIO_MODER_MODER1_Pos

#define GPIO_MODER_MODER1_Pos (2U)

◆ GPIO_MODER_MODER2

#define GPIO_MODER_MODER2 GPIO_MODER_MODER2_Msk

◆ GPIO_MODER_MODER2_0

#define GPIO_MODER_MODER2_0 (0x1UL << GPIO_MODER_MODER2_Pos)

0x00000010

◆ GPIO_MODER_MODER2_1

#define GPIO_MODER_MODER2_1 (0x2UL << GPIO_MODER_MODER2_Pos)

0x00000020

◆ GPIO_MODER_MODER2_Msk

#define GPIO_MODER_MODER2_Msk (0x3UL << GPIO_MODER_MODER2_Pos)

0x00000030

◆ GPIO_MODER_MODER2_Pos

#define GPIO_MODER_MODER2_Pos (4U)

◆ GPIO_MODER_MODER3

#define GPIO_MODER_MODER3 GPIO_MODER_MODER3_Msk

◆ GPIO_MODER_MODER3_0

#define GPIO_MODER_MODER3_0 (0x1UL << GPIO_MODER_MODER3_Pos)

0x00000040

◆ GPIO_MODER_MODER3_1

#define GPIO_MODER_MODER3_1 (0x2UL << GPIO_MODER_MODER3_Pos)

0x00000080

◆ GPIO_MODER_MODER3_Msk

#define GPIO_MODER_MODER3_Msk (0x3UL << GPIO_MODER_MODER3_Pos)

0x000000C0

◆ GPIO_MODER_MODER3_Pos

#define GPIO_MODER_MODER3_Pos (6U)

◆ GPIO_MODER_MODER4

#define GPIO_MODER_MODER4 GPIO_MODER_MODER4_Msk

◆ GPIO_MODER_MODER4_0

#define GPIO_MODER_MODER4_0 (0x1UL << GPIO_MODER_MODER4_Pos)

0x00000100

◆ GPIO_MODER_MODER4_1

#define GPIO_MODER_MODER4_1 (0x2UL << GPIO_MODER_MODER4_Pos)

0x00000200

◆ GPIO_MODER_MODER4_Msk

#define GPIO_MODER_MODER4_Msk (0x3UL << GPIO_MODER_MODER4_Pos)

0x00000300

◆ GPIO_MODER_MODER4_Pos

#define GPIO_MODER_MODER4_Pos (8U)

◆ GPIO_MODER_MODER5

#define GPIO_MODER_MODER5 GPIO_MODER_MODER5_Msk

◆ GPIO_MODER_MODER5_0

#define GPIO_MODER_MODER5_0 (0x1UL << GPIO_MODER_MODER5_Pos)

0x00000400

◆ GPIO_MODER_MODER5_1

#define GPIO_MODER_MODER5_1 (0x2UL << GPIO_MODER_MODER5_Pos)

0x00000800

◆ GPIO_MODER_MODER5_Msk

#define GPIO_MODER_MODER5_Msk (0x3UL << GPIO_MODER_MODER5_Pos)

0x00000C00

◆ GPIO_MODER_MODER5_Pos

#define GPIO_MODER_MODER5_Pos (10U)

◆ GPIO_MODER_MODER6

#define GPIO_MODER_MODER6 GPIO_MODER_MODER6_Msk

◆ GPIO_MODER_MODER6_0

#define GPIO_MODER_MODER6_0 (0x1UL << GPIO_MODER_MODER6_Pos)

0x00001000

◆ GPIO_MODER_MODER6_1

#define GPIO_MODER_MODER6_1 (0x2UL << GPIO_MODER_MODER6_Pos)

0x00002000

◆ GPIO_MODER_MODER6_Msk

#define GPIO_MODER_MODER6_Msk (0x3UL << GPIO_MODER_MODER6_Pos)

0x00003000

◆ GPIO_MODER_MODER6_Pos

#define GPIO_MODER_MODER6_Pos (12U)

◆ GPIO_MODER_MODER7

#define GPIO_MODER_MODER7 GPIO_MODER_MODER7_Msk

◆ GPIO_MODER_MODER7_0

#define GPIO_MODER_MODER7_0 (0x1UL << GPIO_MODER_MODER7_Pos)

0x00004000

◆ GPIO_MODER_MODER7_1

#define GPIO_MODER_MODER7_1 (0x2UL << GPIO_MODER_MODER7_Pos)

0x00008000

◆ GPIO_MODER_MODER7_Msk

#define GPIO_MODER_MODER7_Msk (0x3UL << GPIO_MODER_MODER7_Pos)

0x0000C000

◆ GPIO_MODER_MODER7_Pos

#define GPIO_MODER_MODER7_Pos (14U)

◆ GPIO_MODER_MODER8

#define GPIO_MODER_MODER8 GPIO_MODER_MODER8_Msk

◆ GPIO_MODER_MODER8_0

#define GPIO_MODER_MODER8_0 (0x1UL << GPIO_MODER_MODER8_Pos)

0x00010000

◆ GPIO_MODER_MODER8_1

#define GPIO_MODER_MODER8_1 (0x2UL << GPIO_MODER_MODER8_Pos)

0x00020000

◆ GPIO_MODER_MODER8_Msk

#define GPIO_MODER_MODER8_Msk (0x3UL << GPIO_MODER_MODER8_Pos)

0x00030000

◆ GPIO_MODER_MODER8_Pos

#define GPIO_MODER_MODER8_Pos (16U)

◆ GPIO_MODER_MODER9

#define GPIO_MODER_MODER9 GPIO_MODER_MODER9_Msk

◆ GPIO_MODER_MODER9_0

#define GPIO_MODER_MODER9_0 (0x1UL << GPIO_MODER_MODER9_Pos)

0x00040000

◆ GPIO_MODER_MODER9_1

#define GPIO_MODER_MODER9_1 (0x2UL << GPIO_MODER_MODER9_Pos)

0x00080000

◆ GPIO_MODER_MODER9_Msk

#define GPIO_MODER_MODER9_Msk (0x3UL << GPIO_MODER_MODER9_Pos)

0x000C0000

◆ GPIO_MODER_MODER9_Pos

#define GPIO_MODER_MODER9_Pos (18U)

◆ GPIO_ODR_0

#define GPIO_ODR_0 (0x00000001U)

◆ GPIO_ODR_1

#define GPIO_ODR_1 (0x00000002U)

◆ GPIO_ODR_10

#define GPIO_ODR_10 (0x00000400U)

◆ GPIO_ODR_11

#define GPIO_ODR_11 (0x00000800U)

◆ GPIO_ODR_12

#define GPIO_ODR_12 (0x00001000U)

◆ GPIO_ODR_13

#define GPIO_ODR_13 (0x00002000U)

◆ GPIO_ODR_14

#define GPIO_ODR_14 (0x00004000U)

◆ GPIO_ODR_15

#define GPIO_ODR_15 (0x00008000U)

◆ GPIO_ODR_2

#define GPIO_ODR_2 (0x00000004U)

◆ GPIO_ODR_3

#define GPIO_ODR_3 (0x00000008U)

◆ GPIO_ODR_4

#define GPIO_ODR_4 (0x00000010U)

◆ GPIO_ODR_5

#define GPIO_ODR_5 (0x00000020U)

◆ GPIO_ODR_6

#define GPIO_ODR_6 (0x00000040U)

◆ GPIO_ODR_7

#define GPIO_ODR_7 (0x00000080U)

◆ GPIO_ODR_8

#define GPIO_ODR_8 (0x00000100U)

◆ GPIO_ODR_9

#define GPIO_ODR_9 (0x00000200U)

◆ GPIO_OSPEEDER_OSPEEDR0

#define GPIO_OSPEEDER_OSPEEDR0 GPIO_OSPEEDER_OSPEEDR0_Msk

◆ GPIO_OSPEEDER_OSPEEDR0_0

#define GPIO_OSPEEDER_OSPEEDR0_0 (0x1UL << GPIO_OSPEEDER_OSPEEDR0_Pos)

0x00000001

◆ GPIO_OSPEEDER_OSPEEDR0_1

#define GPIO_OSPEEDER_OSPEEDR0_1 (0x2UL << GPIO_OSPEEDER_OSPEEDR0_Pos)

0x00000002

◆ GPIO_OSPEEDER_OSPEEDR0_Msk

#define GPIO_OSPEEDER_OSPEEDR0_Msk (0x3UL << GPIO_OSPEEDER_OSPEEDR0_Pos)

0x00000003

◆ GPIO_OSPEEDER_OSPEEDR0_Pos

#define GPIO_OSPEEDER_OSPEEDR0_Pos (0U)

◆ GPIO_OSPEEDER_OSPEEDR1

#define GPIO_OSPEEDER_OSPEEDR1 GPIO_OSPEEDER_OSPEEDR1_Msk

◆ GPIO_OSPEEDER_OSPEEDR10

#define GPIO_OSPEEDER_OSPEEDR10 GPIO_OSPEEDER_OSPEEDR10_Msk

◆ GPIO_OSPEEDER_OSPEEDR10_0

#define GPIO_OSPEEDER_OSPEEDR10_0 (0x1UL << GPIO_OSPEEDER_OSPEEDR10_Pos)

0x00100000

◆ GPIO_OSPEEDER_OSPEEDR10_1

#define GPIO_OSPEEDER_OSPEEDR10_1 (0x2UL << GPIO_OSPEEDER_OSPEEDR10_Pos)

0x00200000

◆ GPIO_OSPEEDER_OSPEEDR10_Msk

#define GPIO_OSPEEDER_OSPEEDR10_Msk (0x3UL << GPIO_OSPEEDER_OSPEEDR10_Pos)

0x00300000

◆ GPIO_OSPEEDER_OSPEEDR10_Pos

#define GPIO_OSPEEDER_OSPEEDR10_Pos (20U)

◆ GPIO_OSPEEDER_OSPEEDR11

#define GPIO_OSPEEDER_OSPEEDR11 GPIO_OSPEEDER_OSPEEDR11_Msk

◆ GPIO_OSPEEDER_OSPEEDR11_0

#define GPIO_OSPEEDER_OSPEEDR11_0 (0x1UL << GPIO_OSPEEDER_OSPEEDR11_Pos)

0x00400000

◆ GPIO_OSPEEDER_OSPEEDR11_1

#define GPIO_OSPEEDER_OSPEEDR11_1 (0x2UL << GPIO_OSPEEDER_OSPEEDR11_Pos)

0x00800000

◆ GPIO_OSPEEDER_OSPEEDR11_Msk

#define GPIO_OSPEEDER_OSPEEDR11_Msk (0x3UL << GPIO_OSPEEDER_OSPEEDR11_Pos)

0x00C00000

◆ GPIO_OSPEEDER_OSPEEDR11_Pos

#define GPIO_OSPEEDER_OSPEEDR11_Pos (22U)

◆ GPIO_OSPEEDER_OSPEEDR12

#define GPIO_OSPEEDER_OSPEEDR12 GPIO_OSPEEDER_OSPEEDR12_Msk

◆ GPIO_OSPEEDER_OSPEEDR12_0

#define GPIO_OSPEEDER_OSPEEDR12_0 (0x1UL << GPIO_OSPEEDER_OSPEEDR12_Pos)

0x01000000

◆ GPIO_OSPEEDER_OSPEEDR12_1

#define GPIO_OSPEEDER_OSPEEDR12_1 (0x2UL << GPIO_OSPEEDER_OSPEEDR12_Pos)

0x02000000

◆ GPIO_OSPEEDER_OSPEEDR12_Msk

#define GPIO_OSPEEDER_OSPEEDR12_Msk (0x3UL << GPIO_OSPEEDER_OSPEEDR12_Pos)

0x03000000

◆ GPIO_OSPEEDER_OSPEEDR12_Pos

#define GPIO_OSPEEDER_OSPEEDR12_Pos (24U)

◆ GPIO_OSPEEDER_OSPEEDR13

#define GPIO_OSPEEDER_OSPEEDR13 GPIO_OSPEEDER_OSPEEDR13_Msk

◆ GPIO_OSPEEDER_OSPEEDR13_0

#define GPIO_OSPEEDER_OSPEEDR13_0 (0x1UL << GPIO_OSPEEDER_OSPEEDR13_Pos)

0x04000000

◆ GPIO_OSPEEDER_OSPEEDR13_1

#define GPIO_OSPEEDER_OSPEEDR13_1 (0x2UL << GPIO_OSPEEDER_OSPEEDR13_Pos)

0x08000000

◆ GPIO_OSPEEDER_OSPEEDR13_Msk

#define GPIO_OSPEEDER_OSPEEDR13_Msk (0x3UL << GPIO_OSPEEDER_OSPEEDR13_Pos)

0x0C000000

◆ GPIO_OSPEEDER_OSPEEDR13_Pos

#define GPIO_OSPEEDER_OSPEEDR13_Pos (26U)

◆ GPIO_OSPEEDER_OSPEEDR14

#define GPIO_OSPEEDER_OSPEEDR14 GPIO_OSPEEDER_OSPEEDR14_Msk

◆ GPIO_OSPEEDER_OSPEEDR14_0

#define GPIO_OSPEEDER_OSPEEDR14_0 (0x1UL << GPIO_OSPEEDER_OSPEEDR14_Pos)

0x10000000

◆ GPIO_OSPEEDER_OSPEEDR14_1

#define GPIO_OSPEEDER_OSPEEDR14_1 (0x2UL << GPIO_OSPEEDER_OSPEEDR14_Pos)

0x20000000

◆ GPIO_OSPEEDER_OSPEEDR14_Msk

#define GPIO_OSPEEDER_OSPEEDR14_Msk (0x3UL << GPIO_OSPEEDER_OSPEEDR14_Pos)

0x30000000

◆ GPIO_OSPEEDER_OSPEEDR14_Pos

#define GPIO_OSPEEDER_OSPEEDR14_Pos (28U)

◆ GPIO_OSPEEDER_OSPEEDR15

#define GPIO_OSPEEDER_OSPEEDR15 GPIO_OSPEEDER_OSPEEDR15_Msk

◆ GPIO_OSPEEDER_OSPEEDR15_0

#define GPIO_OSPEEDER_OSPEEDR15_0 (0x1UL << GPIO_OSPEEDER_OSPEEDR15_Pos)

0x40000000

◆ GPIO_OSPEEDER_OSPEEDR15_1

#define GPIO_OSPEEDER_OSPEEDR15_1 (0x2UL << GPIO_OSPEEDER_OSPEEDR15_Pos)

0x80000000

◆ GPIO_OSPEEDER_OSPEEDR15_Msk

#define GPIO_OSPEEDER_OSPEEDR15_Msk (0x3UL << GPIO_OSPEEDER_OSPEEDR15_Pos)

0xC0000000

◆ GPIO_OSPEEDER_OSPEEDR15_Pos

#define GPIO_OSPEEDER_OSPEEDR15_Pos (30U)

◆ GPIO_OSPEEDER_OSPEEDR1_0

#define GPIO_OSPEEDER_OSPEEDR1_0 (0x1UL << GPIO_OSPEEDER_OSPEEDR1_Pos)

0x00000004

◆ GPIO_OSPEEDER_OSPEEDR1_1

#define GPIO_OSPEEDER_OSPEEDR1_1 (0x2UL << GPIO_OSPEEDER_OSPEEDR1_Pos)

0x00000008

◆ GPIO_OSPEEDER_OSPEEDR1_Msk

#define GPIO_OSPEEDER_OSPEEDR1_Msk (0x3UL << GPIO_OSPEEDER_OSPEEDR1_Pos)

0x0000000C

◆ GPIO_OSPEEDER_OSPEEDR1_Pos

#define GPIO_OSPEEDER_OSPEEDR1_Pos (2U)

◆ GPIO_OSPEEDER_OSPEEDR2

#define GPIO_OSPEEDER_OSPEEDR2 GPIO_OSPEEDER_OSPEEDR2_Msk

◆ GPIO_OSPEEDER_OSPEEDR2_0

#define GPIO_OSPEEDER_OSPEEDR2_0 (0x1UL << GPIO_OSPEEDER_OSPEEDR2_Pos)

0x00000010

◆ GPIO_OSPEEDER_OSPEEDR2_1

#define GPIO_OSPEEDER_OSPEEDR2_1 (0x2UL << GPIO_OSPEEDER_OSPEEDR2_Pos)

0x00000020

◆ GPIO_OSPEEDER_OSPEEDR2_Msk

#define GPIO_OSPEEDER_OSPEEDR2_Msk (0x3UL << GPIO_OSPEEDER_OSPEEDR2_Pos)

0x00000030

◆ GPIO_OSPEEDER_OSPEEDR2_Pos

#define GPIO_OSPEEDER_OSPEEDR2_Pos (4U)

◆ GPIO_OSPEEDER_OSPEEDR3

#define GPIO_OSPEEDER_OSPEEDR3 GPIO_OSPEEDER_OSPEEDR3_Msk

◆ GPIO_OSPEEDER_OSPEEDR3_0

#define GPIO_OSPEEDER_OSPEEDR3_0 (0x1UL << GPIO_OSPEEDER_OSPEEDR3_Pos)

0x00000040

◆ GPIO_OSPEEDER_OSPEEDR3_1

#define GPIO_OSPEEDER_OSPEEDR3_1 (0x2UL << GPIO_OSPEEDER_OSPEEDR3_Pos)

0x00000080

◆ GPIO_OSPEEDER_OSPEEDR3_Msk

#define GPIO_OSPEEDER_OSPEEDR3_Msk (0x3UL << GPIO_OSPEEDER_OSPEEDR3_Pos)

0x000000C0

◆ GPIO_OSPEEDER_OSPEEDR3_Pos

#define GPIO_OSPEEDER_OSPEEDR3_Pos (6U)

◆ GPIO_OSPEEDER_OSPEEDR4

#define GPIO_OSPEEDER_OSPEEDR4 GPIO_OSPEEDER_OSPEEDR4_Msk

◆ GPIO_OSPEEDER_OSPEEDR4_0

#define GPIO_OSPEEDER_OSPEEDR4_0 (0x1UL << GPIO_OSPEEDER_OSPEEDR4_Pos)

0x00000100

◆ GPIO_OSPEEDER_OSPEEDR4_1

#define GPIO_OSPEEDER_OSPEEDR4_1 (0x2UL << GPIO_OSPEEDER_OSPEEDR4_Pos)

0x00000200

◆ GPIO_OSPEEDER_OSPEEDR4_Msk

#define GPIO_OSPEEDER_OSPEEDR4_Msk (0x3UL << GPIO_OSPEEDER_OSPEEDR4_Pos)

0x00000300

◆ GPIO_OSPEEDER_OSPEEDR4_Pos

#define GPIO_OSPEEDER_OSPEEDR4_Pos (8U)

◆ GPIO_OSPEEDER_OSPEEDR5

#define GPIO_OSPEEDER_OSPEEDR5 GPIO_OSPEEDER_OSPEEDR5_Msk

◆ GPIO_OSPEEDER_OSPEEDR5_0

#define GPIO_OSPEEDER_OSPEEDR5_0 (0x1UL << GPIO_OSPEEDER_OSPEEDR5_Pos)

0x00000400

◆ GPIO_OSPEEDER_OSPEEDR5_1

#define GPIO_OSPEEDER_OSPEEDR5_1 (0x2UL << GPIO_OSPEEDER_OSPEEDR5_Pos)

0x00000800

◆ GPIO_OSPEEDER_OSPEEDR5_Msk

#define GPIO_OSPEEDER_OSPEEDR5_Msk (0x3UL << GPIO_OSPEEDER_OSPEEDR5_Pos)

0x00000C00

◆ GPIO_OSPEEDER_OSPEEDR5_Pos

#define GPIO_OSPEEDER_OSPEEDR5_Pos (10U)

◆ GPIO_OSPEEDER_OSPEEDR6

#define GPIO_OSPEEDER_OSPEEDR6 GPIO_OSPEEDER_OSPEEDR6_Msk

◆ GPIO_OSPEEDER_OSPEEDR6_0

#define GPIO_OSPEEDER_OSPEEDR6_0 (0x1UL << GPIO_OSPEEDER_OSPEEDR6_Pos)

0x00001000

◆ GPIO_OSPEEDER_OSPEEDR6_1

#define GPIO_OSPEEDER_OSPEEDR6_1 (0x2UL << GPIO_OSPEEDER_OSPEEDR6_Pos)

0x00002000

◆ GPIO_OSPEEDER_OSPEEDR6_Msk

#define GPIO_OSPEEDER_OSPEEDR6_Msk (0x3UL << GPIO_OSPEEDER_OSPEEDR6_Pos)

0x00003000

◆ GPIO_OSPEEDER_OSPEEDR6_Pos

#define GPIO_OSPEEDER_OSPEEDR6_Pos (12U)

◆ GPIO_OSPEEDER_OSPEEDR7

#define GPIO_OSPEEDER_OSPEEDR7 GPIO_OSPEEDER_OSPEEDR7_Msk

◆ GPIO_OSPEEDER_OSPEEDR7_0

#define GPIO_OSPEEDER_OSPEEDR7_0 (0x1UL << GPIO_OSPEEDER_OSPEEDR7_Pos)

0x00004000

◆ GPIO_OSPEEDER_OSPEEDR7_1

#define GPIO_OSPEEDER_OSPEEDR7_1 (0x2UL << GPIO_OSPEEDER_OSPEEDR7_Pos)

0x00008000

◆ GPIO_OSPEEDER_OSPEEDR7_Msk

#define GPIO_OSPEEDER_OSPEEDR7_Msk (0x3UL << GPIO_OSPEEDER_OSPEEDR7_Pos)

0x0000C000

◆ GPIO_OSPEEDER_OSPEEDR7_Pos

#define GPIO_OSPEEDER_OSPEEDR7_Pos (14U)

◆ GPIO_OSPEEDER_OSPEEDR8

#define GPIO_OSPEEDER_OSPEEDR8 GPIO_OSPEEDER_OSPEEDR8_Msk

◆ GPIO_OSPEEDER_OSPEEDR8_0

#define GPIO_OSPEEDER_OSPEEDR8_0 (0x1UL << GPIO_OSPEEDER_OSPEEDR8_Pos)

0x00010000

◆ GPIO_OSPEEDER_OSPEEDR8_1

#define GPIO_OSPEEDER_OSPEEDR8_1 (0x2UL << GPIO_OSPEEDER_OSPEEDR8_Pos)

0x00020000

◆ GPIO_OSPEEDER_OSPEEDR8_Msk

#define GPIO_OSPEEDER_OSPEEDR8_Msk (0x3UL << GPIO_OSPEEDER_OSPEEDR8_Pos)

0x00030000

◆ GPIO_OSPEEDER_OSPEEDR8_Pos

#define GPIO_OSPEEDER_OSPEEDR8_Pos (16U)

◆ GPIO_OSPEEDER_OSPEEDR9

#define GPIO_OSPEEDER_OSPEEDR9 GPIO_OSPEEDER_OSPEEDR9_Msk

◆ GPIO_OSPEEDER_OSPEEDR9_0

#define GPIO_OSPEEDER_OSPEEDR9_0 (0x1UL << GPIO_OSPEEDER_OSPEEDR9_Pos)

0x00040000

◆ GPIO_OSPEEDER_OSPEEDR9_1

#define GPIO_OSPEEDER_OSPEEDR9_1 (0x2UL << GPIO_OSPEEDER_OSPEEDR9_Pos)

0x00080000

◆ GPIO_OSPEEDER_OSPEEDR9_Msk

#define GPIO_OSPEEDER_OSPEEDR9_Msk (0x3UL << GPIO_OSPEEDER_OSPEEDR9_Pos)

0x000C0000

◆ GPIO_OSPEEDER_OSPEEDR9_Pos

#define GPIO_OSPEEDER_OSPEEDR9_Pos (18U)

◆ GPIO_OTYPER_OT_0

#define GPIO_OTYPER_OT_0 (0x00000001U)

◆ GPIO_OTYPER_OT_1

#define GPIO_OTYPER_OT_1 (0x00000002U)

◆ GPIO_OTYPER_OT_10

#define GPIO_OTYPER_OT_10 (0x00000400U)

◆ GPIO_OTYPER_OT_11

#define GPIO_OTYPER_OT_11 (0x00000800U)

◆ GPIO_OTYPER_OT_12

#define GPIO_OTYPER_OT_12 (0x00001000U)

◆ GPIO_OTYPER_OT_13

#define GPIO_OTYPER_OT_13 (0x00002000U)

◆ GPIO_OTYPER_OT_14

#define GPIO_OTYPER_OT_14 (0x00004000U)

◆ GPIO_OTYPER_OT_15

#define GPIO_OTYPER_OT_15 (0x00008000U)

◆ GPIO_OTYPER_OT_2

#define GPIO_OTYPER_OT_2 (0x00000004U)

◆ GPIO_OTYPER_OT_3

#define GPIO_OTYPER_OT_3 (0x00000008U)

◆ GPIO_OTYPER_OT_4

#define GPIO_OTYPER_OT_4 (0x00000010U)

◆ GPIO_OTYPER_OT_5

#define GPIO_OTYPER_OT_5 (0x00000020U)

◆ GPIO_OTYPER_OT_6

#define GPIO_OTYPER_OT_6 (0x00000040U)

◆ GPIO_OTYPER_OT_7

#define GPIO_OTYPER_OT_7 (0x00000080U)

◆ GPIO_OTYPER_OT_8

#define GPIO_OTYPER_OT_8 (0x00000100U)

◆ GPIO_OTYPER_OT_9

#define GPIO_OTYPER_OT_9 (0x00000200U)

◆ GPIO_PUPDR_PUPDR0

#define GPIO_PUPDR_PUPDR0 GPIO_PUPDR_PUPDR0_Msk

◆ GPIO_PUPDR_PUPDR0_0

#define GPIO_PUPDR_PUPDR0_0 (0x1UL << GPIO_PUPDR_PUPDR0_Pos)

0x00000001

◆ GPIO_PUPDR_PUPDR0_1

#define GPIO_PUPDR_PUPDR0_1 (0x2UL << GPIO_PUPDR_PUPDR0_Pos)

0x00000002

◆ GPIO_PUPDR_PUPDR0_Msk

#define GPIO_PUPDR_PUPDR0_Msk (0x3UL << GPIO_PUPDR_PUPDR0_Pos)

0x00000003

◆ GPIO_PUPDR_PUPDR0_Pos

#define GPIO_PUPDR_PUPDR0_Pos (0U)

◆ GPIO_PUPDR_PUPDR1

#define GPIO_PUPDR_PUPDR1 GPIO_PUPDR_PUPDR1_Msk

◆ GPIO_PUPDR_PUPDR10

#define GPIO_PUPDR_PUPDR10 GPIO_PUPDR_PUPDR10_Msk

◆ GPIO_PUPDR_PUPDR10_0

#define GPIO_PUPDR_PUPDR10_0 (0x1UL << GPIO_PUPDR_PUPDR10_Pos)

0x00100000

◆ GPIO_PUPDR_PUPDR10_1

#define GPIO_PUPDR_PUPDR10_1 (0x2UL << GPIO_PUPDR_PUPDR10_Pos)

0x00200000

◆ GPIO_PUPDR_PUPDR10_Msk

#define GPIO_PUPDR_PUPDR10_Msk (0x3UL << GPIO_PUPDR_PUPDR10_Pos)

0x00300000

◆ GPIO_PUPDR_PUPDR10_Pos

#define GPIO_PUPDR_PUPDR10_Pos (20U)

◆ GPIO_PUPDR_PUPDR11

#define GPIO_PUPDR_PUPDR11 GPIO_PUPDR_PUPDR11_Msk

◆ GPIO_PUPDR_PUPDR11_0

#define GPIO_PUPDR_PUPDR11_0 (0x1UL << GPIO_PUPDR_PUPDR11_Pos)

0x00400000

◆ GPIO_PUPDR_PUPDR11_1

#define GPIO_PUPDR_PUPDR11_1 (0x2UL << GPIO_PUPDR_PUPDR11_Pos)

0x00800000

◆ GPIO_PUPDR_PUPDR11_Msk

#define GPIO_PUPDR_PUPDR11_Msk (0x3UL << GPIO_PUPDR_PUPDR11_Pos)

0x00C00000

◆ GPIO_PUPDR_PUPDR11_Pos

#define GPIO_PUPDR_PUPDR11_Pos (22U)

◆ GPIO_PUPDR_PUPDR12

#define GPIO_PUPDR_PUPDR12 GPIO_PUPDR_PUPDR12_Msk

◆ GPIO_PUPDR_PUPDR12_0

#define GPIO_PUPDR_PUPDR12_0 (0x1UL << GPIO_PUPDR_PUPDR12_Pos)

0x01000000

◆ GPIO_PUPDR_PUPDR12_1

#define GPIO_PUPDR_PUPDR12_1 (0x2UL << GPIO_PUPDR_PUPDR12_Pos)

0x02000000

◆ GPIO_PUPDR_PUPDR12_Msk

#define GPIO_PUPDR_PUPDR12_Msk (0x3UL << GPIO_PUPDR_PUPDR12_Pos)

0x03000000

◆ GPIO_PUPDR_PUPDR12_Pos

#define GPIO_PUPDR_PUPDR12_Pos (24U)

◆ GPIO_PUPDR_PUPDR13

#define GPIO_PUPDR_PUPDR13 GPIO_PUPDR_PUPDR13_Msk

◆ GPIO_PUPDR_PUPDR13_0

#define GPIO_PUPDR_PUPDR13_0 (0x1UL << GPIO_PUPDR_PUPDR13_Pos)

0x04000000

◆ GPIO_PUPDR_PUPDR13_1

#define GPIO_PUPDR_PUPDR13_1 (0x2UL << GPIO_PUPDR_PUPDR13_Pos)

0x08000000

◆ GPIO_PUPDR_PUPDR13_Msk

#define GPIO_PUPDR_PUPDR13_Msk (0x3UL << GPIO_PUPDR_PUPDR13_Pos)

0x0C000000

◆ GPIO_PUPDR_PUPDR13_Pos

#define GPIO_PUPDR_PUPDR13_Pos (26U)

◆ GPIO_PUPDR_PUPDR14

#define GPIO_PUPDR_PUPDR14 GPIO_PUPDR_PUPDR14_Msk

◆ GPIO_PUPDR_PUPDR14_0

#define GPIO_PUPDR_PUPDR14_0 (0x1UL << GPIO_PUPDR_PUPDR14_Pos)

0x10000000

◆ GPIO_PUPDR_PUPDR14_1

#define GPIO_PUPDR_PUPDR14_1 (0x2UL << GPIO_PUPDR_PUPDR14_Pos)

0x20000000

◆ GPIO_PUPDR_PUPDR14_Msk

#define GPIO_PUPDR_PUPDR14_Msk (0x3UL << GPIO_PUPDR_PUPDR14_Pos)

0x30000000

◆ GPIO_PUPDR_PUPDR14_Pos

#define GPIO_PUPDR_PUPDR14_Pos (28U)

◆ GPIO_PUPDR_PUPDR15

#define GPIO_PUPDR_PUPDR15 GPIO_PUPDR_PUPDR15_Msk

◆ GPIO_PUPDR_PUPDR15_0

#define GPIO_PUPDR_PUPDR15_0 (0x1UL << GPIO_PUPDR_PUPDR15_Pos)

0x40000000

◆ GPIO_PUPDR_PUPDR15_1

#define GPIO_PUPDR_PUPDR15_1 (0x2UL << GPIO_PUPDR_PUPDR15_Pos)

0x80000000

◆ GPIO_PUPDR_PUPDR15_Msk

#define GPIO_PUPDR_PUPDR15_Msk (0x3UL << GPIO_PUPDR_PUPDR15_Pos)

0xC0000000

◆ GPIO_PUPDR_PUPDR15_Pos

#define GPIO_PUPDR_PUPDR15_Pos (30U)

◆ GPIO_PUPDR_PUPDR1_0

#define GPIO_PUPDR_PUPDR1_0 (0x1UL << GPIO_PUPDR_PUPDR1_Pos)

0x00000004

◆ GPIO_PUPDR_PUPDR1_1

#define GPIO_PUPDR_PUPDR1_1 (0x2UL << GPIO_PUPDR_PUPDR1_Pos)

0x00000008

◆ GPIO_PUPDR_PUPDR1_Msk

#define GPIO_PUPDR_PUPDR1_Msk (0x3UL << GPIO_PUPDR_PUPDR1_Pos)

0x0000000C

◆ GPIO_PUPDR_PUPDR1_Pos

#define GPIO_PUPDR_PUPDR1_Pos (2U)

◆ GPIO_PUPDR_PUPDR2

#define GPIO_PUPDR_PUPDR2 GPIO_PUPDR_PUPDR2_Msk

◆ GPIO_PUPDR_PUPDR2_0

#define GPIO_PUPDR_PUPDR2_0 (0x1UL << GPIO_PUPDR_PUPDR2_Pos)

0x00000010

◆ GPIO_PUPDR_PUPDR2_1

#define GPIO_PUPDR_PUPDR2_1 (0x2UL << GPIO_PUPDR_PUPDR2_Pos)

0x00000020

◆ GPIO_PUPDR_PUPDR2_Msk

#define GPIO_PUPDR_PUPDR2_Msk (0x3UL << GPIO_PUPDR_PUPDR2_Pos)

0x00000030

◆ GPIO_PUPDR_PUPDR2_Pos

#define GPIO_PUPDR_PUPDR2_Pos (4U)

◆ GPIO_PUPDR_PUPDR3

#define GPIO_PUPDR_PUPDR3 GPIO_PUPDR_PUPDR3_Msk

◆ GPIO_PUPDR_PUPDR3_0

#define GPIO_PUPDR_PUPDR3_0 (0x1UL << GPIO_PUPDR_PUPDR3_Pos)

0x00000040

◆ GPIO_PUPDR_PUPDR3_1

#define GPIO_PUPDR_PUPDR3_1 (0x2UL << GPIO_PUPDR_PUPDR3_Pos)

0x00000080

◆ GPIO_PUPDR_PUPDR3_Msk

#define GPIO_PUPDR_PUPDR3_Msk (0x3UL << GPIO_PUPDR_PUPDR3_Pos)

0x000000C0

◆ GPIO_PUPDR_PUPDR3_Pos

#define GPIO_PUPDR_PUPDR3_Pos (6U)

◆ GPIO_PUPDR_PUPDR4

#define GPIO_PUPDR_PUPDR4 GPIO_PUPDR_PUPDR4_Msk

◆ GPIO_PUPDR_PUPDR4_0

#define GPIO_PUPDR_PUPDR4_0 (0x1UL << GPIO_PUPDR_PUPDR4_Pos)

0x00000100

◆ GPIO_PUPDR_PUPDR4_1

#define GPIO_PUPDR_PUPDR4_1 (0x2UL << GPIO_PUPDR_PUPDR4_Pos)

0x00000200

◆ GPIO_PUPDR_PUPDR4_Msk

#define GPIO_PUPDR_PUPDR4_Msk (0x3UL << GPIO_PUPDR_PUPDR4_Pos)

0x00000300

◆ GPIO_PUPDR_PUPDR4_Pos

#define GPIO_PUPDR_PUPDR4_Pos (8U)

◆ GPIO_PUPDR_PUPDR5

#define GPIO_PUPDR_PUPDR5 GPIO_PUPDR_PUPDR5_Msk

◆ GPIO_PUPDR_PUPDR5_0

#define GPIO_PUPDR_PUPDR5_0 (0x1UL << GPIO_PUPDR_PUPDR5_Pos)

0x00000400

◆ GPIO_PUPDR_PUPDR5_1

#define GPIO_PUPDR_PUPDR5_1 (0x2UL << GPIO_PUPDR_PUPDR5_Pos)

0x00000800

◆ GPIO_PUPDR_PUPDR5_Msk

#define GPIO_PUPDR_PUPDR5_Msk (0x3UL << GPIO_PUPDR_PUPDR5_Pos)

0x00000C00

◆ GPIO_PUPDR_PUPDR5_Pos

#define GPIO_PUPDR_PUPDR5_Pos (10U)

◆ GPIO_PUPDR_PUPDR6

#define GPIO_PUPDR_PUPDR6 GPIO_PUPDR_PUPDR6_Msk

◆ GPIO_PUPDR_PUPDR6_0

#define GPIO_PUPDR_PUPDR6_0 (0x1UL << GPIO_PUPDR_PUPDR6_Pos)

0x00001000

◆ GPIO_PUPDR_PUPDR6_1

#define GPIO_PUPDR_PUPDR6_1 (0x2UL << GPIO_PUPDR_PUPDR6_Pos)

0x00002000

◆ GPIO_PUPDR_PUPDR6_Msk

#define GPIO_PUPDR_PUPDR6_Msk (0x3UL << GPIO_PUPDR_PUPDR6_Pos)

0x00003000

◆ GPIO_PUPDR_PUPDR6_Pos

#define GPIO_PUPDR_PUPDR6_Pos (12U)

◆ GPIO_PUPDR_PUPDR7

#define GPIO_PUPDR_PUPDR7 GPIO_PUPDR_PUPDR7_Msk

◆ GPIO_PUPDR_PUPDR7_0

#define GPIO_PUPDR_PUPDR7_0 (0x1UL << GPIO_PUPDR_PUPDR7_Pos)

0x00004000

◆ GPIO_PUPDR_PUPDR7_1

#define GPIO_PUPDR_PUPDR7_1 (0x2UL << GPIO_PUPDR_PUPDR7_Pos)

0x00008000

◆ GPIO_PUPDR_PUPDR7_Msk

#define GPIO_PUPDR_PUPDR7_Msk (0x3UL << GPIO_PUPDR_PUPDR7_Pos)

0x0000C000

◆ GPIO_PUPDR_PUPDR7_Pos

#define GPIO_PUPDR_PUPDR7_Pos (14U)

◆ GPIO_PUPDR_PUPDR8

#define GPIO_PUPDR_PUPDR8 GPIO_PUPDR_PUPDR8_Msk

◆ GPIO_PUPDR_PUPDR8_0

#define GPIO_PUPDR_PUPDR8_0 (0x1UL << GPIO_PUPDR_PUPDR8_Pos)

0x00010000

◆ GPIO_PUPDR_PUPDR8_1

#define GPIO_PUPDR_PUPDR8_1 (0x2UL << GPIO_PUPDR_PUPDR8_Pos)

0x00020000

◆ GPIO_PUPDR_PUPDR8_Msk

#define GPIO_PUPDR_PUPDR8_Msk (0x3UL << GPIO_PUPDR_PUPDR8_Pos)

0x00030000

◆ GPIO_PUPDR_PUPDR8_Pos

#define GPIO_PUPDR_PUPDR8_Pos (16U)

◆ GPIO_PUPDR_PUPDR9

#define GPIO_PUPDR_PUPDR9 GPIO_PUPDR_PUPDR9_Msk

◆ GPIO_PUPDR_PUPDR9_0

#define GPIO_PUPDR_PUPDR9_0 (0x1UL << GPIO_PUPDR_PUPDR9_Pos)

0x00040000

◆ GPIO_PUPDR_PUPDR9_1

#define GPIO_PUPDR_PUPDR9_1 (0x2UL << GPIO_PUPDR_PUPDR9_Pos)

0x00080000

◆ GPIO_PUPDR_PUPDR9_Msk

#define GPIO_PUPDR_PUPDR9_Msk (0x3UL << GPIO_PUPDR_PUPDR9_Pos)

0x000C0000

◆ GPIO_PUPDR_PUPDR9_Pos

#define GPIO_PUPDR_PUPDR9_Pos (18U)

◆ I2C_CR1_ADDRIE

#define I2C_CR1_ADDRIE I2C_CR1_ADDRIE_Msk

Address match interrupt enable

◆ I2C_CR1_ADDRIE_Msk

#define I2C_CR1_ADDRIE_Msk (0x1UL << I2C_CR1_ADDRIE_Pos)

0x00000008

◆ I2C_CR1_ADDRIE_Pos

#define I2C_CR1_ADDRIE_Pos (3U)

◆ I2C_CR1_ALERTEN

#define I2C_CR1_ALERTEN I2C_CR1_ALERTEN_Msk

SMBus alert enable

◆ I2C_CR1_ALERTEN_Msk

#define I2C_CR1_ALERTEN_Msk (0x1UL << I2C_CR1_ALERTEN_Pos)

0x00400000

◆ I2C_CR1_ALERTEN_Pos

#define I2C_CR1_ALERTEN_Pos (22U)

◆ I2C_CR1_ANFOFF

#define I2C_CR1_ANFOFF I2C_CR1_ANFOFF_Msk

Analog noise filter OFF

◆ I2C_CR1_ANFOFF_Msk

#define I2C_CR1_ANFOFF_Msk (0x1UL << I2C_CR1_ANFOFF_Pos)

0x00001000

◆ I2C_CR1_ANFOFF_Pos

#define I2C_CR1_ANFOFF_Pos (12U)

◆ I2C_CR1_DFN

#define I2C_CR1_DFN I2C_CR1_DNF

◆ I2C_CR1_DNF

#define I2C_CR1_DNF I2C_CR1_DNF_Msk

Digital noise filter

◆ I2C_CR1_DNF_Msk

#define I2C_CR1_DNF_Msk (0xFUL << I2C_CR1_DNF_Pos)

0x00000F00

◆ I2C_CR1_DNF_Pos

#define I2C_CR1_DNF_Pos (8U)

◆ I2C_CR1_ERRIE

#define I2C_CR1_ERRIE I2C_CR1_ERRIE_Msk

Errors interrupt enable

◆ I2C_CR1_ERRIE_Msk

#define I2C_CR1_ERRIE_Msk (0x1UL << I2C_CR1_ERRIE_Pos)

0x00000080

◆ I2C_CR1_ERRIE_Pos

#define I2C_CR1_ERRIE_Pos (7U)

◆ I2C_CR1_GCEN

#define I2C_CR1_GCEN I2C_CR1_GCEN_Msk

General call enable

◆ I2C_CR1_GCEN_Msk

#define I2C_CR1_GCEN_Msk (0x1UL << I2C_CR1_GCEN_Pos)

0x00080000

◆ I2C_CR1_GCEN_Pos

#define I2C_CR1_GCEN_Pos (19U)

◆ I2C_CR1_NACKIE

#define I2C_CR1_NACKIE I2C_CR1_NACKIE_Msk

NACK received interrupt enable

◆ I2C_CR1_NACKIE_Msk

#define I2C_CR1_NACKIE_Msk (0x1UL << I2C_CR1_NACKIE_Pos)

0x00000010

◆ I2C_CR1_NACKIE_Pos

#define I2C_CR1_NACKIE_Pos (4U)

◆ I2C_CR1_NOSTRETCH

#define I2C_CR1_NOSTRETCH I2C_CR1_NOSTRETCH_Msk

Clock stretching disable

◆ I2C_CR1_NOSTRETCH_Msk

#define I2C_CR1_NOSTRETCH_Msk (0x1UL << I2C_CR1_NOSTRETCH_Pos)

0x00020000

◆ I2C_CR1_NOSTRETCH_Pos

#define I2C_CR1_NOSTRETCH_Pos (17U)

◆ I2C_CR1_PE

#define I2C_CR1_PE I2C_CR1_PE_Msk

Peripheral enable

◆ I2C_CR1_PE_Msk

#define I2C_CR1_PE_Msk (0x1UL << I2C_CR1_PE_Pos)

0x00000001

◆ I2C_CR1_PE_Pos

#define I2C_CR1_PE_Pos (0U)

◆ I2C_CR1_PECEN

#define I2C_CR1_PECEN I2C_CR1_PECEN_Msk

PEC enable

◆ I2C_CR1_PECEN_Msk

#define I2C_CR1_PECEN_Msk (0x1UL << I2C_CR1_PECEN_Pos)

0x00800000

◆ I2C_CR1_PECEN_Pos

#define I2C_CR1_PECEN_Pos (23U)

◆ I2C_CR1_RXDMAEN

#define I2C_CR1_RXDMAEN I2C_CR1_RXDMAEN_Msk

DMA reception requests enable

◆ I2C_CR1_RXDMAEN_Msk

#define I2C_CR1_RXDMAEN_Msk (0x1UL << I2C_CR1_RXDMAEN_Pos)

0x00008000

◆ I2C_CR1_RXDMAEN_Pos

#define I2C_CR1_RXDMAEN_Pos (15U)

◆ I2C_CR1_RXIE

#define I2C_CR1_RXIE I2C_CR1_RXIE_Msk

RX interrupt enable

◆ I2C_CR1_RXIE_Msk

#define I2C_CR1_RXIE_Msk (0x1UL << I2C_CR1_RXIE_Pos)

0x00000004

◆ I2C_CR1_RXIE_Pos

#define I2C_CR1_RXIE_Pos (2U)

◆ I2C_CR1_SBC

#define I2C_CR1_SBC I2C_CR1_SBC_Msk

Slave byte control

◆ I2C_CR1_SBC_Msk

#define I2C_CR1_SBC_Msk (0x1UL << I2C_CR1_SBC_Pos)

0x00010000

◆ I2C_CR1_SBC_Pos

#define I2C_CR1_SBC_Pos (16U)

◆ I2C_CR1_SMBDEN

#define I2C_CR1_SMBDEN I2C_CR1_SMBDEN_Msk

SMBus device default address enable

◆ I2C_CR1_SMBDEN_Msk

#define I2C_CR1_SMBDEN_Msk (0x1UL << I2C_CR1_SMBDEN_Pos)

0x00200000

◆ I2C_CR1_SMBDEN_Pos

#define I2C_CR1_SMBDEN_Pos (21U)

◆ I2C_CR1_SMBHEN

#define I2C_CR1_SMBHEN I2C_CR1_SMBHEN_Msk

SMBus host address enable

◆ I2C_CR1_SMBHEN_Msk

#define I2C_CR1_SMBHEN_Msk (0x1UL << I2C_CR1_SMBHEN_Pos)

0x00100000

◆ I2C_CR1_SMBHEN_Pos

#define I2C_CR1_SMBHEN_Pos (20U)

◆ I2C_CR1_STOPIE

#define I2C_CR1_STOPIE I2C_CR1_STOPIE_Msk

STOP detection interrupt enable

◆ I2C_CR1_STOPIE_Msk

#define I2C_CR1_STOPIE_Msk (0x1UL << I2C_CR1_STOPIE_Pos)

0x00000020

◆ I2C_CR1_STOPIE_Pos

#define I2C_CR1_STOPIE_Pos (5U)

◆ I2C_CR1_SWRST

#define I2C_CR1_SWRST I2C_CR1_SWRST_Msk

Software reset

◆ I2C_CR1_SWRST_Msk

#define I2C_CR1_SWRST_Msk (0x1UL << I2C_CR1_SWRST_Pos)

0x00002000

◆ I2C_CR1_SWRST_Pos

#define I2C_CR1_SWRST_Pos (13U)

◆ I2C_CR1_TCIE

#define I2C_CR1_TCIE I2C_CR1_TCIE_Msk

Transfer complete interrupt enable

◆ I2C_CR1_TCIE_Msk

#define I2C_CR1_TCIE_Msk (0x1UL << I2C_CR1_TCIE_Pos)

0x00000040

◆ I2C_CR1_TCIE_Pos

#define I2C_CR1_TCIE_Pos (6U)

◆ I2C_CR1_TXDMAEN

#define I2C_CR1_TXDMAEN I2C_CR1_TXDMAEN_Msk

DMA transmission requests enable

◆ I2C_CR1_TXDMAEN_Msk

#define I2C_CR1_TXDMAEN_Msk (0x1UL << I2C_CR1_TXDMAEN_Pos)

0x00004000

◆ I2C_CR1_TXDMAEN_Pos

#define I2C_CR1_TXDMAEN_Pos (14U)

◆ I2C_CR1_TXIE

#define I2C_CR1_TXIE I2C_CR1_TXIE_Msk

TX interrupt enable

◆ I2C_CR1_TXIE_Msk

#define I2C_CR1_TXIE_Msk (0x1UL << I2C_CR1_TXIE_Pos)

0x00000002

◆ I2C_CR1_TXIE_Pos

#define I2C_CR1_TXIE_Pos (1U)

◆ I2C_CR1_WUPEN

#define I2C_CR1_WUPEN I2C_CR1_WUPEN_Msk

Wakeup from STOP enable

◆ I2C_CR1_WUPEN_Msk

#define I2C_CR1_WUPEN_Msk (0x1UL << I2C_CR1_WUPEN_Pos)

0x00040000

◆ I2C_CR1_WUPEN_Pos

#define I2C_CR1_WUPEN_Pos (18U)

◆ I2C_CR2_ADD10

#define I2C_CR2_ADD10 I2C_CR2_ADD10_Msk

10-bit addressing mode (master mode)

◆ I2C_CR2_ADD10_Msk

#define I2C_CR2_ADD10_Msk (0x1UL << I2C_CR2_ADD10_Pos)

0x00000800

◆ I2C_CR2_ADD10_Pos

#define I2C_CR2_ADD10_Pos (11U)

◆ I2C_CR2_AUTOEND

#define I2C_CR2_AUTOEND I2C_CR2_AUTOEND_Msk

Automatic end mode (master mode)

◆ I2C_CR2_AUTOEND_Msk

#define I2C_CR2_AUTOEND_Msk (0x1UL << I2C_CR2_AUTOEND_Pos)

0x02000000

◆ I2C_CR2_AUTOEND_Pos

#define I2C_CR2_AUTOEND_Pos (25U)

◆ I2C_CR2_HEAD10R

#define I2C_CR2_HEAD10R I2C_CR2_HEAD10R_Msk

10-bit address header only read direction (master mode)

◆ I2C_CR2_HEAD10R_Msk

#define I2C_CR2_HEAD10R_Msk (0x1UL << I2C_CR2_HEAD10R_Pos)

0x00001000

◆ I2C_CR2_HEAD10R_Pos

#define I2C_CR2_HEAD10R_Pos (12U)

◆ I2C_CR2_NACK

#define I2C_CR2_NACK I2C_CR2_NACK_Msk

NACK generation (slave mode)

◆ I2C_CR2_NACK_Msk

#define I2C_CR2_NACK_Msk (0x1UL << I2C_CR2_NACK_Pos)

0x00008000

◆ I2C_CR2_NACK_Pos

#define I2C_CR2_NACK_Pos (15U)

◆ I2C_CR2_NBYTES

#define I2C_CR2_NBYTES I2C_CR2_NBYTES_Msk

Number of bytes

◆ I2C_CR2_NBYTES_Msk

#define I2C_CR2_NBYTES_Msk (0xFFUL << I2C_CR2_NBYTES_Pos)

0x00FF0000

◆ I2C_CR2_NBYTES_Pos

#define I2C_CR2_NBYTES_Pos (16U)

◆ I2C_CR2_PECBYTE

#define I2C_CR2_PECBYTE I2C_CR2_PECBYTE_Msk

Packet error checking byte

◆ I2C_CR2_PECBYTE_Msk

#define I2C_CR2_PECBYTE_Msk (0x1UL << I2C_CR2_PECBYTE_Pos)

0x04000000

◆ I2C_CR2_PECBYTE_Pos

#define I2C_CR2_PECBYTE_Pos (26U)

◆ I2C_CR2_RD_WRN

#define I2C_CR2_RD_WRN I2C_CR2_RD_WRN_Msk

Transfer direction (master mode)

◆ I2C_CR2_RD_WRN_Msk

#define I2C_CR2_RD_WRN_Msk (0x1UL << I2C_CR2_RD_WRN_Pos)

0x00000400

◆ I2C_CR2_RD_WRN_Pos

#define I2C_CR2_RD_WRN_Pos (10U)

◆ I2C_CR2_RELOAD

#define I2C_CR2_RELOAD I2C_CR2_RELOAD_Msk

NBYTES reload mode

◆ I2C_CR2_RELOAD_Msk

#define I2C_CR2_RELOAD_Msk (0x1UL << I2C_CR2_RELOAD_Pos)

0x01000000

◆ I2C_CR2_RELOAD_Pos

#define I2C_CR2_RELOAD_Pos (24U)

◆ I2C_CR2_SADD

#define I2C_CR2_SADD I2C_CR2_SADD_Msk

Slave address (master mode)

◆ I2C_CR2_SADD_Msk

#define I2C_CR2_SADD_Msk (0x3FFUL << I2C_CR2_SADD_Pos)

0x000003FF

◆ I2C_CR2_SADD_Pos

#define I2C_CR2_SADD_Pos (0U)

◆ I2C_CR2_START

#define I2C_CR2_START I2C_CR2_START_Msk

START generation

◆ I2C_CR2_START_Msk

#define I2C_CR2_START_Msk (0x1UL << I2C_CR2_START_Pos)

0x00002000

◆ I2C_CR2_START_Pos

#define I2C_CR2_START_Pos (13U)

◆ I2C_CR2_STOP

#define I2C_CR2_STOP I2C_CR2_STOP_Msk

STOP generation (master mode)

◆ I2C_CR2_STOP_Msk

#define I2C_CR2_STOP_Msk (0x1UL << I2C_CR2_STOP_Pos)

0x00004000

◆ I2C_CR2_STOP_Pos

#define I2C_CR2_STOP_Pos (14U)

◆ I2C_ICR_ADDRCF

#define I2C_ICR_ADDRCF I2C_ICR_ADDRCF_Msk

Address matched clear flag

◆ I2C_ICR_ADDRCF_Msk

#define I2C_ICR_ADDRCF_Msk (0x1UL << I2C_ICR_ADDRCF_Pos)

0x00000008

◆ I2C_ICR_ADDRCF_Pos

#define I2C_ICR_ADDRCF_Pos (3U)

◆ I2C_ICR_ALERTCF

#define I2C_ICR_ALERTCF I2C_ICR_ALERTCF_Msk

Alert clear flag

◆ I2C_ICR_ALERTCF_Msk

#define I2C_ICR_ALERTCF_Msk (0x1UL << I2C_ICR_ALERTCF_Pos)

0x00002000

◆ I2C_ICR_ALERTCF_Pos

#define I2C_ICR_ALERTCF_Pos (13U)

◆ I2C_ICR_ARLOCF

#define I2C_ICR_ARLOCF I2C_ICR_ARLOCF_Msk

Arbitration lost clear flag

◆ I2C_ICR_ARLOCF_Msk

#define I2C_ICR_ARLOCF_Msk (0x1UL << I2C_ICR_ARLOCF_Pos)

0x00000200

◆ I2C_ICR_ARLOCF_Pos

#define I2C_ICR_ARLOCF_Pos (9U)

◆ I2C_ICR_BERRCF

#define I2C_ICR_BERRCF I2C_ICR_BERRCF_Msk

Bus error clear flag

◆ I2C_ICR_BERRCF_Msk

#define I2C_ICR_BERRCF_Msk (0x1UL << I2C_ICR_BERRCF_Pos)

0x00000100

◆ I2C_ICR_BERRCF_Pos

#define I2C_ICR_BERRCF_Pos (8U)

◆ I2C_ICR_NACKCF

#define I2C_ICR_NACKCF I2C_ICR_NACKCF_Msk

NACK clear flag

◆ I2C_ICR_NACKCF_Msk

#define I2C_ICR_NACKCF_Msk (0x1UL << I2C_ICR_NACKCF_Pos)

0x00000010

◆ I2C_ICR_NACKCF_Pos

#define I2C_ICR_NACKCF_Pos (4U)

◆ I2C_ICR_OVRCF

#define I2C_ICR_OVRCF I2C_ICR_OVRCF_Msk

Overrun/Underrun clear flag

◆ I2C_ICR_OVRCF_Msk

#define I2C_ICR_OVRCF_Msk (0x1UL << I2C_ICR_OVRCF_Pos)

0x00000400

◆ I2C_ICR_OVRCF_Pos

#define I2C_ICR_OVRCF_Pos (10U)

◆ I2C_ICR_PECCF

#define I2C_ICR_PECCF I2C_ICR_PECCF_Msk

PAC error clear flag

◆ I2C_ICR_PECCF_Msk

#define I2C_ICR_PECCF_Msk (0x1UL << I2C_ICR_PECCF_Pos)

0x00000800

◆ I2C_ICR_PECCF_Pos

#define I2C_ICR_PECCF_Pos (11U)

◆ I2C_ICR_STOPCF

#define I2C_ICR_STOPCF I2C_ICR_STOPCF_Msk

STOP detection clear flag

◆ I2C_ICR_STOPCF_Msk

#define I2C_ICR_STOPCF_Msk (0x1UL << I2C_ICR_STOPCF_Pos)

0x00000020

◆ I2C_ICR_STOPCF_Pos

#define I2C_ICR_STOPCF_Pos (5U)

◆ I2C_ICR_TIMOUTCF

#define I2C_ICR_TIMOUTCF I2C_ICR_TIMOUTCF_Msk

Timeout clear flag

◆ I2C_ICR_TIMOUTCF_Msk

#define I2C_ICR_TIMOUTCF_Msk (0x1UL << I2C_ICR_TIMOUTCF_Pos)

0x00001000

◆ I2C_ICR_TIMOUTCF_Pos

#define I2C_ICR_TIMOUTCF_Pos (12U)

◆ I2C_ISR_ADDCODE

#define I2C_ISR_ADDCODE I2C_ISR_ADDCODE_Msk

Address match code (slave mode)

◆ I2C_ISR_ADDCODE_Msk

#define I2C_ISR_ADDCODE_Msk (0x7FUL << I2C_ISR_ADDCODE_Pos)

0x00FE0000

◆ I2C_ISR_ADDCODE_Pos

#define I2C_ISR_ADDCODE_Pos (17U)

◆ I2C_ISR_ADDR

#define I2C_ISR_ADDR I2C_ISR_ADDR_Msk

Address matched (slave mode)

◆ I2C_ISR_ADDR_Msk

#define I2C_ISR_ADDR_Msk (0x1UL << I2C_ISR_ADDR_Pos)

0x00000008

◆ I2C_ISR_ADDR_Pos

#define I2C_ISR_ADDR_Pos (3U)

◆ I2C_ISR_ALERT

#define I2C_ISR_ALERT I2C_ISR_ALERT_Msk

SMBus alert

◆ I2C_ISR_ALERT_Msk

#define I2C_ISR_ALERT_Msk (0x1UL << I2C_ISR_ALERT_Pos)

0x00002000

◆ I2C_ISR_ALERT_Pos

#define I2C_ISR_ALERT_Pos (13U)

◆ I2C_ISR_ARLO

#define I2C_ISR_ARLO I2C_ISR_ARLO_Msk

Arbitration lost

◆ I2C_ISR_ARLO_Msk

#define I2C_ISR_ARLO_Msk (0x1UL << I2C_ISR_ARLO_Pos)

0x00000200

◆ I2C_ISR_ARLO_Pos

#define I2C_ISR_ARLO_Pos (9U)

◆ I2C_ISR_BERR

#define I2C_ISR_BERR I2C_ISR_BERR_Msk

Bus error

◆ I2C_ISR_BERR_Msk

#define I2C_ISR_BERR_Msk (0x1UL << I2C_ISR_BERR_Pos)

0x00000100

◆ I2C_ISR_BERR_Pos

#define I2C_ISR_BERR_Pos (8U)

◆ I2C_ISR_BUSY

#define I2C_ISR_BUSY I2C_ISR_BUSY_Msk

Bus busy

◆ I2C_ISR_BUSY_Msk

#define I2C_ISR_BUSY_Msk (0x1UL << I2C_ISR_BUSY_Pos)

0x00008000

◆ I2C_ISR_BUSY_Pos

#define I2C_ISR_BUSY_Pos (15U)

◆ I2C_ISR_DIR

#define I2C_ISR_DIR I2C_ISR_DIR_Msk

Transfer direction (slave mode)

◆ I2C_ISR_DIR_Msk

#define I2C_ISR_DIR_Msk (0x1UL << I2C_ISR_DIR_Pos)

0x00010000

◆ I2C_ISR_DIR_Pos

#define I2C_ISR_DIR_Pos (16U)

◆ I2C_ISR_NACKF

#define I2C_ISR_NACKF I2C_ISR_NACKF_Msk

NACK received flag

◆ I2C_ISR_NACKF_Msk

#define I2C_ISR_NACKF_Msk (0x1UL << I2C_ISR_NACKF_Pos)

0x00000010

◆ I2C_ISR_NACKF_Pos

#define I2C_ISR_NACKF_Pos (4U)

◆ I2C_ISR_OVR

#define I2C_ISR_OVR I2C_ISR_OVR_Msk

Overrun/Underrun

◆ I2C_ISR_OVR_Msk

#define I2C_ISR_OVR_Msk (0x1UL << I2C_ISR_OVR_Pos)

0x00000400

◆ I2C_ISR_OVR_Pos

#define I2C_ISR_OVR_Pos (10U)

◆ I2C_ISR_PECERR

#define I2C_ISR_PECERR I2C_ISR_PECERR_Msk

PEC error in reception

◆ I2C_ISR_PECERR_Msk

#define I2C_ISR_PECERR_Msk (0x1UL << I2C_ISR_PECERR_Pos)

0x00000800

◆ I2C_ISR_PECERR_Pos

#define I2C_ISR_PECERR_Pos (11U)

◆ I2C_ISR_RXNE

#define I2C_ISR_RXNE I2C_ISR_RXNE_Msk

Receive data register not empty

◆ I2C_ISR_RXNE_Msk

#define I2C_ISR_RXNE_Msk (0x1UL << I2C_ISR_RXNE_Pos)

0x00000004

◆ I2C_ISR_RXNE_Pos

#define I2C_ISR_RXNE_Pos (2U)

◆ I2C_ISR_STOPF

#define I2C_ISR_STOPF I2C_ISR_STOPF_Msk

STOP detection flag

◆ I2C_ISR_STOPF_Msk

#define I2C_ISR_STOPF_Msk (0x1UL << I2C_ISR_STOPF_Pos)

0x00000020

◆ I2C_ISR_STOPF_Pos

#define I2C_ISR_STOPF_Pos (5U)

◆ I2C_ISR_TC

#define I2C_ISR_TC I2C_ISR_TC_Msk

Transfer complete (master mode)

◆ I2C_ISR_TC_Msk

#define I2C_ISR_TC_Msk (0x1UL << I2C_ISR_TC_Pos)

0x00000040

◆ I2C_ISR_TC_Pos

#define I2C_ISR_TC_Pos (6U)

◆ I2C_ISR_TCR

#define I2C_ISR_TCR I2C_ISR_TCR_Msk

Transfer complete reload

◆ I2C_ISR_TCR_Msk

#define I2C_ISR_TCR_Msk (0x1UL << I2C_ISR_TCR_Pos)

0x00000080

◆ I2C_ISR_TCR_Pos

#define I2C_ISR_TCR_Pos (7U)

◆ I2C_ISR_TIMEOUT

#define I2C_ISR_TIMEOUT I2C_ISR_TIMEOUT_Msk

Timeout or Tlow detection flag

◆ I2C_ISR_TIMEOUT_Msk

#define I2C_ISR_TIMEOUT_Msk (0x1UL << I2C_ISR_TIMEOUT_Pos)

0x00001000

◆ I2C_ISR_TIMEOUT_Pos

#define I2C_ISR_TIMEOUT_Pos (12U)

◆ I2C_ISR_TXE

#define I2C_ISR_TXE I2C_ISR_TXE_Msk

Transmit data register empty

◆ I2C_ISR_TXE_Msk

#define I2C_ISR_TXE_Msk (0x1UL << I2C_ISR_TXE_Pos)

0x00000001

◆ I2C_ISR_TXE_Pos

#define I2C_ISR_TXE_Pos (0U)

◆ I2C_ISR_TXIS

#define I2C_ISR_TXIS I2C_ISR_TXIS_Msk

Transmit interrupt status

◆ I2C_ISR_TXIS_Msk

#define I2C_ISR_TXIS_Msk (0x1UL << I2C_ISR_TXIS_Pos)

0x00000002

◆ I2C_ISR_TXIS_Pos

#define I2C_ISR_TXIS_Pos (1U)

◆ I2C_OAR1_OA1

#define I2C_OAR1_OA1 I2C_OAR1_OA1_Msk

Interface own address 1

◆ I2C_OAR1_OA1_Msk

#define I2C_OAR1_OA1_Msk (0x3FFUL << I2C_OAR1_OA1_Pos)

0x000003FF

◆ I2C_OAR1_OA1_Pos

#define I2C_OAR1_OA1_Pos (0U)

◆ I2C_OAR1_OA1EN

#define I2C_OAR1_OA1EN I2C_OAR1_OA1EN_Msk

Own address 1 enable

◆ I2C_OAR1_OA1EN_Msk

#define I2C_OAR1_OA1EN_Msk (0x1UL << I2C_OAR1_OA1EN_Pos)

0x00008000

◆ I2C_OAR1_OA1EN_Pos

#define I2C_OAR1_OA1EN_Pos (15U)

◆ I2C_OAR1_OA1MODE

#define I2C_OAR1_OA1MODE I2C_OAR1_OA1MODE_Msk

Own address 1 10-bit mode

◆ I2C_OAR1_OA1MODE_Msk

#define I2C_OAR1_OA1MODE_Msk (0x1UL << I2C_OAR1_OA1MODE_Pos)

0x00000400

◆ I2C_OAR1_OA1MODE_Pos

#define I2C_OAR1_OA1MODE_Pos (10U)

◆ I2C_OAR2_OA2

#define I2C_OAR2_OA2 I2C_OAR2_OA2_Msk

Interface own address 2

◆ I2C_OAR2_OA2_Msk

#define I2C_OAR2_OA2_Msk (0x7FUL << I2C_OAR2_OA2_Pos)

0x000000FE

◆ I2C_OAR2_OA2_Pos

#define I2C_OAR2_OA2_Pos (1U)

◆ I2C_OAR2_OA2EN

#define I2C_OAR2_OA2EN I2C_OAR2_OA2EN_Msk

Own address 2 enable

◆ I2C_OAR2_OA2EN_Msk

#define I2C_OAR2_OA2EN_Msk (0x1UL << I2C_OAR2_OA2EN_Pos)

0x00008000

◆ I2C_OAR2_OA2EN_Pos

#define I2C_OAR2_OA2EN_Pos (15U)

◆ I2C_OAR2_OA2MASK01

#define I2C_OAR2_OA2MASK01 I2C_OAR2_OA2MASK01_Msk

OA2[1] is masked, Only OA2[7:2] are compared

◆ I2C_OAR2_OA2MASK01_Msk

#define I2C_OAR2_OA2MASK01_Msk (0x1UL << I2C_OAR2_OA2MASK01_Pos)

0x00000100

◆ I2C_OAR2_OA2MASK01_Pos

#define I2C_OAR2_OA2MASK01_Pos (8U)

◆ I2C_OAR2_OA2MASK02

#define I2C_OAR2_OA2MASK02 I2C_OAR2_OA2MASK02_Msk

OA2[2:1] is masked, Only OA2[7:3] are compared

◆ I2C_OAR2_OA2MASK02_Msk

#define I2C_OAR2_OA2MASK02_Msk (0x1UL << I2C_OAR2_OA2MASK02_Pos)

0x00000200

◆ I2C_OAR2_OA2MASK02_Pos

#define I2C_OAR2_OA2MASK02_Pos (9U)

◆ I2C_OAR2_OA2MASK03

#define I2C_OAR2_OA2MASK03 I2C_OAR2_OA2MASK03_Msk

OA2[3:1] is masked, Only OA2[7:4] are compared

◆ I2C_OAR2_OA2MASK03_Msk

#define I2C_OAR2_OA2MASK03_Msk (0x3UL << I2C_OAR2_OA2MASK03_Pos)

0x00000300

◆ I2C_OAR2_OA2MASK03_Pos

#define I2C_OAR2_OA2MASK03_Pos (8U)

◆ I2C_OAR2_OA2MASK04

#define I2C_OAR2_OA2MASK04 I2C_OAR2_OA2MASK04_Msk

OA2[4:1] is masked, Only OA2[7:5] are compared

◆ I2C_OAR2_OA2MASK04_Msk

#define I2C_OAR2_OA2MASK04_Msk (0x1UL << I2C_OAR2_OA2MASK04_Pos)

0x00000400

◆ I2C_OAR2_OA2MASK04_Pos

#define I2C_OAR2_OA2MASK04_Pos (10U)

◆ I2C_OAR2_OA2MASK05

#define I2C_OAR2_OA2MASK05 I2C_OAR2_OA2MASK05_Msk

OA2[5:1] is masked, Only OA2[7:6] are compared

◆ I2C_OAR2_OA2MASK05_Msk

#define I2C_OAR2_OA2MASK05_Msk (0x5UL << I2C_OAR2_OA2MASK05_Pos)

0x00000500

◆ I2C_OAR2_OA2MASK05_Pos

#define I2C_OAR2_OA2MASK05_Pos (8U)

◆ I2C_OAR2_OA2MASK06

#define I2C_OAR2_OA2MASK06 I2C_OAR2_OA2MASK06_Msk

OA2[6:1] is masked, Only OA2[7] are compared

◆ I2C_OAR2_OA2MASK06_Msk

#define I2C_OAR2_OA2MASK06_Msk (0x3UL << I2C_OAR2_OA2MASK06_Pos)

0x00000600

◆ I2C_OAR2_OA2MASK06_Pos

#define I2C_OAR2_OA2MASK06_Pos (9U)

◆ I2C_OAR2_OA2MASK07

#define I2C_OAR2_OA2MASK07 I2C_OAR2_OA2MASK07_Msk

OA2[7:1] is masked, No comparison is done

◆ I2C_OAR2_OA2MASK07_Msk

#define I2C_OAR2_OA2MASK07_Msk (0x7UL << I2C_OAR2_OA2MASK07_Pos)

0x00000700

◆ I2C_OAR2_OA2MASK07_Pos

#define I2C_OAR2_OA2MASK07_Pos (8U)

◆ I2C_OAR2_OA2MSK

#define I2C_OAR2_OA2MSK I2C_OAR2_OA2MSK_Msk

Own address 2 masks

◆ I2C_OAR2_OA2MSK_Msk

#define I2C_OAR2_OA2MSK_Msk (0x7UL << I2C_OAR2_OA2MSK_Pos)

0x00000700

◆ I2C_OAR2_OA2MSK_Pos

#define I2C_OAR2_OA2MSK_Pos (8U)

◆ I2C_OAR2_OA2NOMASK

#define I2C_OAR2_OA2NOMASK (0x00000000U)

No mask

◆ I2C_PECR_PEC

#define I2C_PECR_PEC I2C_PECR_PEC_Msk

PEC register

◆ I2C_PECR_PEC_Msk

#define I2C_PECR_PEC_Msk (0xFFUL << I2C_PECR_PEC_Pos)

0x000000FF

◆ I2C_PECR_PEC_Pos

#define I2C_PECR_PEC_Pos (0U)

◆ I2C_RXDR_RXDATA

#define I2C_RXDR_RXDATA I2C_RXDR_RXDATA_Msk

8-bit receive data

◆ I2C_RXDR_RXDATA_Msk

#define I2C_RXDR_RXDATA_Msk (0xFFUL << I2C_RXDR_RXDATA_Pos)

0x000000FF

◆ I2C_RXDR_RXDATA_Pos

#define I2C_RXDR_RXDATA_Pos (0U)

◆ I2C_TIMEOUTR_TEXTEN

#define I2C_TIMEOUTR_TEXTEN I2C_TIMEOUTR_TEXTEN_Msk

Extended clock timeout enable

◆ I2C_TIMEOUTR_TEXTEN_Msk

#define I2C_TIMEOUTR_TEXTEN_Msk (0x1UL << I2C_TIMEOUTR_TEXTEN_Pos)

0x80000000

◆ I2C_TIMEOUTR_TEXTEN_Pos

#define I2C_TIMEOUTR_TEXTEN_Pos (31U)

◆ I2C_TIMEOUTR_TIDLE

#define I2C_TIMEOUTR_TIDLE I2C_TIMEOUTR_TIDLE_Msk

Idle clock timeout detection

◆ I2C_TIMEOUTR_TIDLE_Msk

#define I2C_TIMEOUTR_TIDLE_Msk (0x1UL << I2C_TIMEOUTR_TIDLE_Pos)

0x00001000

◆ I2C_TIMEOUTR_TIDLE_Pos

#define I2C_TIMEOUTR_TIDLE_Pos (12U)

◆ I2C_TIMEOUTR_TIMEOUTA

#define I2C_TIMEOUTR_TIMEOUTA I2C_TIMEOUTR_TIMEOUTA_Msk

Bus timeout A

◆ I2C_TIMEOUTR_TIMEOUTA_Msk

#define I2C_TIMEOUTR_TIMEOUTA_Msk (0xFFFUL << I2C_TIMEOUTR_TIMEOUTA_Pos)

0x00000FFF

◆ I2C_TIMEOUTR_TIMEOUTA_Pos

#define I2C_TIMEOUTR_TIMEOUTA_Pos (0U)

◆ I2C_TIMEOUTR_TIMEOUTB

#define I2C_TIMEOUTR_TIMEOUTB I2C_TIMEOUTR_TIMEOUTB_Msk

Bus timeout B

◆ I2C_TIMEOUTR_TIMEOUTB_Msk

#define I2C_TIMEOUTR_TIMEOUTB_Msk (0xFFFUL << I2C_TIMEOUTR_TIMEOUTB_Pos)

0x0FFF0000

◆ I2C_TIMEOUTR_TIMEOUTB_Pos

#define I2C_TIMEOUTR_TIMEOUTB_Pos (16U)

◆ I2C_TIMEOUTR_TIMOUTEN

#define I2C_TIMEOUTR_TIMOUTEN I2C_TIMEOUTR_TIMOUTEN_Msk

Clock timeout enable

◆ I2C_TIMEOUTR_TIMOUTEN_Msk

#define I2C_TIMEOUTR_TIMOUTEN_Msk (0x1UL << I2C_TIMEOUTR_TIMOUTEN_Pos)

0x00008000

◆ I2C_TIMEOUTR_TIMOUTEN_Pos

#define I2C_TIMEOUTR_TIMOUTEN_Pos (15U)

◆ I2C_TIMINGR_PRESC

#define I2C_TIMINGR_PRESC I2C_TIMINGR_PRESC_Msk

Timings prescaler

◆ I2C_TIMINGR_PRESC_Msk

#define I2C_TIMINGR_PRESC_Msk (0xFUL << I2C_TIMINGR_PRESC_Pos)

0xF0000000

◆ I2C_TIMINGR_PRESC_Pos

#define I2C_TIMINGR_PRESC_Pos (28U)

◆ I2C_TIMINGR_SCLDEL

#define I2C_TIMINGR_SCLDEL I2C_TIMINGR_SCLDEL_Msk

Data setup time

◆ I2C_TIMINGR_SCLDEL_Msk

#define I2C_TIMINGR_SCLDEL_Msk (0xFUL << I2C_TIMINGR_SCLDEL_Pos)

0x00F00000

◆ I2C_TIMINGR_SCLDEL_Pos

#define I2C_TIMINGR_SCLDEL_Pos (20U)

◆ I2C_TIMINGR_SCLH

#define I2C_TIMINGR_SCLH I2C_TIMINGR_SCLH_Msk

SCL high period (master mode)

◆ I2C_TIMINGR_SCLH_Msk

#define I2C_TIMINGR_SCLH_Msk (0xFFUL << I2C_TIMINGR_SCLH_Pos)

0x0000FF00

◆ I2C_TIMINGR_SCLH_Pos

#define I2C_TIMINGR_SCLH_Pos (8U)

◆ I2C_TIMINGR_SCLL

#define I2C_TIMINGR_SCLL I2C_TIMINGR_SCLL_Msk

SCL low period (master mode)

◆ I2C_TIMINGR_SCLL_Msk

#define I2C_TIMINGR_SCLL_Msk (0xFFUL << I2C_TIMINGR_SCLL_Pos)

0x000000FF

◆ I2C_TIMINGR_SCLL_Pos

#define I2C_TIMINGR_SCLL_Pos (0U)

◆ I2C_TIMINGR_SDADEL

#define I2C_TIMINGR_SDADEL I2C_TIMINGR_SDADEL_Msk

Data hold time

◆ I2C_TIMINGR_SDADEL_Msk

#define I2C_TIMINGR_SDADEL_Msk (0xFUL << I2C_TIMINGR_SDADEL_Pos)

0x000F0000

◆ I2C_TIMINGR_SDADEL_Pos

#define I2C_TIMINGR_SDADEL_Pos (16U)

◆ I2C_TXDR_TXDATA

#define I2C_TXDR_TXDATA I2C_TXDR_TXDATA_Msk

8-bit transmit data

◆ I2C_TXDR_TXDATA_Msk

#define I2C_TXDR_TXDATA_Msk (0xFFUL << I2C_TXDR_TXDATA_Pos)

0x000000FF

◆ I2C_TXDR_TXDATA_Pos

#define I2C_TXDR_TXDATA_Pos (0U)

◆ IWDG_KR_KEY

#define IWDG_KR_KEY IWDG_KR_KEY_Msk

Key value (write only, read 0000h)

◆ IWDG_KR_KEY_Msk

#define IWDG_KR_KEY_Msk (0xFFFFUL << IWDG_KR_KEY_Pos)

0x0000FFFF

◆ IWDG_KR_KEY_Pos

#define IWDG_KR_KEY_Pos (0U)

◆ IWDG_PR_PR

#define IWDG_PR_PR IWDG_PR_PR_Msk

PR[2:0] (Prescaler divider)

◆ IWDG_PR_PR_0

#define IWDG_PR_PR_0 (0x1UL << IWDG_PR_PR_Pos)

0x00000001

◆ IWDG_PR_PR_1

#define IWDG_PR_PR_1 (0x2UL << IWDG_PR_PR_Pos)

0x00000002

◆ IWDG_PR_PR_2

#define IWDG_PR_PR_2 (0x4UL << IWDG_PR_PR_Pos)

0x00000004

◆ IWDG_PR_PR_Msk

#define IWDG_PR_PR_Msk (0x7UL << IWDG_PR_PR_Pos)

0x00000007

◆ IWDG_PR_PR_Pos

#define IWDG_PR_PR_Pos (0U)

◆ IWDG_RLR_RL

#define IWDG_RLR_RL IWDG_RLR_RL_Msk

Watchdog counter reload value

◆ IWDG_RLR_RL_Msk

#define IWDG_RLR_RL_Msk (0xFFFUL << IWDG_RLR_RL_Pos)

0x00000FFF

◆ IWDG_RLR_RL_Pos

#define IWDG_RLR_RL_Pos (0U)

◆ IWDG_SR_PVU

#define IWDG_SR_PVU IWDG_SR_PVU_Msk

Watchdog prescaler value update

◆ IWDG_SR_PVU_Msk

#define IWDG_SR_PVU_Msk (0x1UL << IWDG_SR_PVU_Pos)

0x00000001

◆ IWDG_SR_PVU_Pos

#define IWDG_SR_PVU_Pos (0U)

◆ IWDG_SR_RVU

#define IWDG_SR_RVU IWDG_SR_RVU_Msk

Watchdog counter reload value update

◆ IWDG_SR_RVU_Msk

#define IWDG_SR_RVU_Msk (0x1UL << IWDG_SR_RVU_Pos)

0x00000002

◆ IWDG_SR_RVU_Pos

#define IWDG_SR_RVU_Pos (1U)

◆ IWDG_SR_WVU

#define IWDG_SR_WVU IWDG_SR_WVU_Msk

Watchdog counter window value update

◆ IWDG_SR_WVU_Msk

#define IWDG_SR_WVU_Msk (0x1UL << IWDG_SR_WVU_Pos)

0x00000004

◆ IWDG_SR_WVU_Pos

#define IWDG_SR_WVU_Pos (2U)

◆ IWDG_WINR_WIN

#define IWDG_WINR_WIN IWDG_WINR_WIN_Msk

Watchdog counter window value

◆ IWDG_WINR_WIN_Msk

#define IWDG_WINR_WIN_Msk (0xFFFUL << IWDG_WINR_WIN_Pos)

0x00000FFF

◆ IWDG_WINR_WIN_Pos

#define IWDG_WINR_WIN_Pos (0U)

◆ OB_RDP_nRDP

#define OB_RDP_nRDP OB_RDP_nRDP_Msk

Read protection complemented option byte

◆ OB_RDP_nRDP_Msk

#define OB_RDP_nRDP_Msk (0xFFUL << OB_RDP_nRDP_Pos)

0x0000FF00

◆ OB_RDP_nRDP_Pos

#define OB_RDP_nRDP_Pos (8U)

◆ OB_RDP_RDP

#define OB_RDP_RDP OB_RDP_RDP_Msk

Read protection option byte

◆ OB_RDP_RDP_Msk

#define OB_RDP_RDP_Msk (0xFFUL << OB_RDP_RDP_Pos)

0x000000FF

◆ OB_RDP_RDP_Pos

#define OB_RDP_RDP_Pos (0U)

◆ OB_USER_nUSER

#define OB_USER_nUSER OB_USER_nUSER_Msk

User complemented option byte

◆ OB_USER_nUSER_Msk

#define OB_USER_nUSER_Msk (0xFFUL << OB_USER_nUSER_Pos)

0xFF000000

◆ OB_USER_nUSER_Pos

#define OB_USER_nUSER_Pos (24U)

◆ OB_USER_USER

#define OB_USER_USER OB_USER_USER_Msk

User option byte

◆ OB_USER_USER_Msk

#define OB_USER_USER_Msk (0xFFUL << OB_USER_USER_Pos)

0x00FF0000

◆ OB_USER_USER_Pos

#define OB_USER_USER_Pos (16U)

◆ OB_WRP0_nWRP0

#define OB_WRP0_nWRP0 OB_WRP0_nWRP0_Msk

Flash memory write protection complemented option bytes

◆ OB_WRP0_nWRP0_Msk

#define OB_WRP0_nWRP0_Msk (0xFFUL << OB_WRP0_nWRP0_Pos)

0x0000FF00

◆ OB_WRP0_nWRP0_Pos

#define OB_WRP0_nWRP0_Pos (8U)

◆ OB_WRP0_WRP0

#define OB_WRP0_WRP0 OB_WRP0_WRP0_Msk

Flash memory write protection option bytes

◆ OB_WRP0_WRP0_Msk

#define OB_WRP0_WRP0_Msk (0xFFUL << OB_WRP0_WRP0_Pos)

0x000000FF

◆ OB_WRP0_WRP0_Pos

#define OB_WRP0_WRP0_Pos (0U)

◆ OB_WRP1_nWRP1

#define OB_WRP1_nWRP1 OB_WRP1_nWRP1_Msk

Flash memory write protection complemented option bytes

◆ OB_WRP1_nWRP1_Msk

#define OB_WRP1_nWRP1_Msk (0xFFUL << OB_WRP1_nWRP1_Pos)

0xFF000000

◆ OB_WRP1_nWRP1_Pos

#define OB_WRP1_nWRP1_Pos (24U)

◆ OB_WRP1_WRP1

#define OB_WRP1_WRP1 OB_WRP1_WRP1_Msk

Flash memory write protection option bytes

◆ OB_WRP1_WRP1_Msk

#define OB_WRP1_WRP1_Msk (0xFFUL << OB_WRP1_WRP1_Pos)

0x00FF0000

◆ OB_WRP1_WRP1_Pos

#define OB_WRP1_WRP1_Pos (16U)

◆ OB_WRP2_nWRP2

#define OB_WRP2_nWRP2 OB_WRP2_nWRP2_Msk

Flash memory write protection complemented option bytes

◆ OB_WRP2_nWRP2_Msk

#define OB_WRP2_nWRP2_Msk (0xFFUL << OB_WRP2_nWRP2_Pos)

0x0000FF00

◆ OB_WRP2_nWRP2_Pos

#define OB_WRP2_nWRP2_Pos (8U)

◆ OB_WRP2_WRP2

#define OB_WRP2_WRP2 OB_WRP2_WRP2_Msk

Flash memory write protection option bytes

◆ OB_WRP2_WRP2_Msk

#define OB_WRP2_WRP2_Msk (0xFFUL << OB_WRP2_WRP2_Pos)

0x000000FF

◆ OB_WRP2_WRP2_Pos

#define OB_WRP2_WRP2_Pos (0U)

◆ OB_WRP3_nWRP3

#define OB_WRP3_nWRP3 OB_WRP3_nWRP3_Msk

Flash memory write protection complemented option bytes

◆ OB_WRP3_nWRP3_Msk

#define OB_WRP3_nWRP3_Msk (0xFFUL << OB_WRP3_nWRP3_Pos)

0xFF000000

◆ OB_WRP3_nWRP3_Pos

#define OB_WRP3_nWRP3_Pos (24U)

◆ OB_WRP3_WRP3

#define OB_WRP3_WRP3 OB_WRP3_WRP3_Msk

Flash memory write protection option bytes

◆ OB_WRP3_WRP3_Msk

#define OB_WRP3_WRP3_Msk (0xFFUL << OB_WRP3_WRP3_Pos)

0x00FF0000

◆ OB_WRP3_WRP3_Pos

#define OB_WRP3_WRP3_Pos (16U)

◆ OPAMP1_CSR_CALON

#define OPAMP1_CSR_CALON OPAMP1_CSR_CALON_Msk

Calibration mode enable

◆ OPAMP1_CSR_CALON_Msk

#define OPAMP1_CSR_CALON_Msk (0x1UL << OPAMP1_CSR_CALON_Pos)

0x00000800

◆ OPAMP1_CSR_CALON_Pos

#define OPAMP1_CSR_CALON_Pos (11U)

◆ OPAMP1_CSR_CALSEL

#define OPAMP1_CSR_CALSEL OPAMP1_CSR_CALSEL_Msk

Calibration selection

◆ OPAMP1_CSR_CALSEL_0

#define OPAMP1_CSR_CALSEL_0 (0x1UL << OPAMP1_CSR_CALSEL_Pos)

0x00001000

◆ OPAMP1_CSR_CALSEL_1

#define OPAMP1_CSR_CALSEL_1 (0x2UL << OPAMP1_CSR_CALSEL_Pos)

0x00002000

◆ OPAMP1_CSR_CALSEL_Msk

#define OPAMP1_CSR_CALSEL_Msk (0x3UL << OPAMP1_CSR_CALSEL_Pos)

0x00003000

◆ OPAMP1_CSR_CALSEL_Pos

#define OPAMP1_CSR_CALSEL_Pos (12U)

◆ OPAMP1_CSR_FORCEVP

#define OPAMP1_CSR_FORCEVP OPAMP1_CSR_FORCEVP_Msk

Connect the internal references to the plus input of the OPAMPX

◆ OPAMP1_CSR_FORCEVP_Msk

#define OPAMP1_CSR_FORCEVP_Msk (0x1UL << OPAMP1_CSR_FORCEVP_Pos)

0x00000002

◆ OPAMP1_CSR_FORCEVP_Pos

#define OPAMP1_CSR_FORCEVP_Pos (1U)

◆ OPAMP1_CSR_LOCK

#define OPAMP1_CSR_LOCK OPAMP1_CSR_LOCK_Msk

OPAMP lock

◆ OPAMP1_CSR_LOCK_Msk

#define OPAMP1_CSR_LOCK_Msk (0x1UL << OPAMP1_CSR_LOCK_Pos)

0x80000000

◆ OPAMP1_CSR_LOCK_Pos

#define OPAMP1_CSR_LOCK_Pos (31U)

◆ OPAMP1_CSR_OPAMP1EN

#define OPAMP1_CSR_OPAMP1EN OPAMP1_CSR_OPAMP1EN_Msk

OPAMP1 enable

◆ OPAMP1_CSR_OPAMP1EN_Msk

#define OPAMP1_CSR_OPAMP1EN_Msk (0x1UL << OPAMP1_CSR_OPAMP1EN_Pos)

0x00000001

◆ OPAMP1_CSR_OPAMP1EN_Pos

#define OPAMP1_CSR_OPAMP1EN_Pos (0U)

◆ OPAMP1_CSR_OUTCAL

#define OPAMP1_CSR_OUTCAL OPAMP1_CSR_OUTCAL_Msk

OPAMP output status flag

◆ OPAMP1_CSR_OUTCAL_Msk

#define OPAMP1_CSR_OUTCAL_Msk (0x1UL << OPAMP1_CSR_OUTCAL_Pos)

0x40000000

◆ OPAMP1_CSR_OUTCAL_Pos

#define OPAMP1_CSR_OUTCAL_Pos (30U)

◆ OPAMP1_CSR_PGGAIN

#define OPAMP1_CSR_PGGAIN OPAMP1_CSR_PGGAIN_Msk

Gain in PGA mode

◆ OPAMP1_CSR_PGGAIN_0

#define OPAMP1_CSR_PGGAIN_0 (0x1UL << OPAMP1_CSR_PGGAIN_Pos)

0x00004000

◆ OPAMP1_CSR_PGGAIN_1

#define OPAMP1_CSR_PGGAIN_1 (0x2UL << OPAMP1_CSR_PGGAIN_Pos)

0x00008000

◆ OPAMP1_CSR_PGGAIN_2

#define OPAMP1_CSR_PGGAIN_2 (0x4UL << OPAMP1_CSR_PGGAIN_Pos)

0x00010000

◆ OPAMP1_CSR_PGGAIN_3

#define OPAMP1_CSR_PGGAIN_3 (0x8UL << OPAMP1_CSR_PGGAIN_Pos)

0x00020000

◆ OPAMP1_CSR_PGGAIN_Msk

#define OPAMP1_CSR_PGGAIN_Msk (0xFUL << OPAMP1_CSR_PGGAIN_Pos)

0x0003C000

◆ OPAMP1_CSR_PGGAIN_Pos

#define OPAMP1_CSR_PGGAIN_Pos (14U)

◆ OPAMP1_CSR_TCMEN

#define OPAMP1_CSR_TCMEN OPAMP1_CSR_TCMEN_Msk

Timer-Controlled Mux mode enable

◆ OPAMP1_CSR_TCMEN_Msk

#define OPAMP1_CSR_TCMEN_Msk (0x1UL << OPAMP1_CSR_TCMEN_Pos)

0x00000080

◆ OPAMP1_CSR_TCMEN_Pos

#define OPAMP1_CSR_TCMEN_Pos (7U)

◆ OPAMP1_CSR_TRIMOFFSETN

#define OPAMP1_CSR_TRIMOFFSETN OPAMP1_CSR_TRIMOFFSETN_Msk

Offset trimming value (NMOS)

◆ OPAMP1_CSR_TRIMOFFSETN_Msk

#define OPAMP1_CSR_TRIMOFFSETN_Msk (0x1FUL << OPAMP1_CSR_TRIMOFFSETN_Pos)

0x1F000000

◆ OPAMP1_CSR_TRIMOFFSETN_Pos

#define OPAMP1_CSR_TRIMOFFSETN_Pos (24U)

◆ OPAMP1_CSR_TRIMOFFSETP

#define OPAMP1_CSR_TRIMOFFSETP OPAMP1_CSR_TRIMOFFSETP_Msk

Offset trimming value (PMOS)

◆ OPAMP1_CSR_TRIMOFFSETP_Msk

#define OPAMP1_CSR_TRIMOFFSETP_Msk (0x1FUL << OPAMP1_CSR_TRIMOFFSETP_Pos)

0x00F80000

◆ OPAMP1_CSR_TRIMOFFSETP_Pos

#define OPAMP1_CSR_TRIMOFFSETP_Pos (19U)

◆ OPAMP1_CSR_TSTREF

#define OPAMP1_CSR_TSTREF OPAMP1_CSR_TSTREF_Msk

It enables the switch to put out the internal reference

◆ OPAMP1_CSR_TSTREF_Msk

#define OPAMP1_CSR_TSTREF_Msk (0x1UL << OPAMP1_CSR_TSTREF_Pos)

0x20000000

◆ OPAMP1_CSR_TSTREF_Pos

#define OPAMP1_CSR_TSTREF_Pos (29U)

◆ OPAMP1_CSR_USERTRIM

#define OPAMP1_CSR_USERTRIM OPAMP1_CSR_USERTRIM_Msk

User trimming enable

◆ OPAMP1_CSR_USERTRIM_Msk

#define OPAMP1_CSR_USERTRIM_Msk (0x1UL << OPAMP1_CSR_USERTRIM_Pos)

0x00040000

◆ OPAMP1_CSR_USERTRIM_Pos

#define OPAMP1_CSR_USERTRIM_Pos (18U)

◆ OPAMP1_CSR_VMSEL

#define OPAMP1_CSR_VMSEL OPAMP1_CSR_VMSEL_Msk

Inverting input selection

◆ OPAMP1_CSR_VMSEL_0

#define OPAMP1_CSR_VMSEL_0 (0x1UL << OPAMP1_CSR_VMSEL_Pos)

0x00000020

◆ OPAMP1_CSR_VMSEL_1

#define OPAMP1_CSR_VMSEL_1 (0x2UL << OPAMP1_CSR_VMSEL_Pos)

0x00000040

◆ OPAMP1_CSR_VMSEL_Msk

#define OPAMP1_CSR_VMSEL_Msk (0x3UL << OPAMP1_CSR_VMSEL_Pos)

0x00000060

◆ OPAMP1_CSR_VMSEL_Pos

#define OPAMP1_CSR_VMSEL_Pos (5U)

◆ OPAMP1_CSR_VMSSEL

#define OPAMP1_CSR_VMSSEL OPAMP1_CSR_VMSSEL_Msk

Inverting input secondary selection

◆ OPAMP1_CSR_VMSSEL_Msk

#define OPAMP1_CSR_VMSSEL_Msk (0x1UL << OPAMP1_CSR_VMSSEL_Pos)

0x00000100

◆ OPAMP1_CSR_VMSSEL_Pos

#define OPAMP1_CSR_VMSSEL_Pos (8U)

◆ OPAMP1_CSR_VPSEL

#define OPAMP1_CSR_VPSEL OPAMP1_CSR_VPSEL_Msk

Non inverting input selection

◆ OPAMP1_CSR_VPSEL_0

#define OPAMP1_CSR_VPSEL_0 (0x1UL << OPAMP1_CSR_VPSEL_Pos)

0x00000004

◆ OPAMP1_CSR_VPSEL_1

#define OPAMP1_CSR_VPSEL_1 (0x2UL << OPAMP1_CSR_VPSEL_Pos)

0x00000008

◆ OPAMP1_CSR_VPSEL_Msk

#define OPAMP1_CSR_VPSEL_Msk (0x3UL << OPAMP1_CSR_VPSEL_Pos)

0x0000000C

◆ OPAMP1_CSR_VPSEL_Pos

#define OPAMP1_CSR_VPSEL_Pos (2U)

◆ OPAMP1_CSR_VPSSEL

#define OPAMP1_CSR_VPSSEL OPAMP1_CSR_VPSSEL_Msk

Non inverting input secondary selection

◆ OPAMP1_CSR_VPSSEL_0

#define OPAMP1_CSR_VPSSEL_0 (0x1UL << OPAMP1_CSR_VPSSEL_Pos)

0x00000200

◆ OPAMP1_CSR_VPSSEL_1

#define OPAMP1_CSR_VPSSEL_1 (0x2UL << OPAMP1_CSR_VPSSEL_Pos)

0x00000400

◆ OPAMP1_CSR_VPSSEL_Msk

#define OPAMP1_CSR_VPSSEL_Msk (0x3UL << OPAMP1_CSR_VPSSEL_Pos)

0x00000600

◆ OPAMP1_CSR_VPSSEL_Pos

#define OPAMP1_CSR_VPSSEL_Pos (9U)

◆ OPAMP2_CSR_CALON

#define OPAMP2_CSR_CALON OPAMP2_CSR_CALON_Msk

Calibration mode enable

◆ OPAMP2_CSR_CALON_Msk

#define OPAMP2_CSR_CALON_Msk (0x1UL << OPAMP2_CSR_CALON_Pos)

0x00000800

◆ OPAMP2_CSR_CALON_Pos

#define OPAMP2_CSR_CALON_Pos (11U)

◆ OPAMP2_CSR_CALSEL

#define OPAMP2_CSR_CALSEL OPAMP2_CSR_CALSEL_Msk

Calibration selection

◆ OPAMP2_CSR_CALSEL_0

#define OPAMP2_CSR_CALSEL_0 (0x1UL << OPAMP2_CSR_CALSEL_Pos)

0x00001000

◆ OPAMP2_CSR_CALSEL_1

#define OPAMP2_CSR_CALSEL_1 (0x2UL << OPAMP2_CSR_CALSEL_Pos)

0x00002000

◆ OPAMP2_CSR_CALSEL_Msk

#define OPAMP2_CSR_CALSEL_Msk (0x3UL << OPAMP2_CSR_CALSEL_Pos)

0x00003000

◆ OPAMP2_CSR_CALSEL_Pos

#define OPAMP2_CSR_CALSEL_Pos (12U)

◆ OPAMP2_CSR_FORCEVP

#define OPAMP2_CSR_FORCEVP OPAMP2_CSR_FORCEVP_Msk

Connect the internal references to the plus input of the OPAMPX

◆ OPAMP2_CSR_FORCEVP_Msk

#define OPAMP2_CSR_FORCEVP_Msk (0x1UL << OPAMP2_CSR_FORCEVP_Pos)

0x00000002

◆ OPAMP2_CSR_FORCEVP_Pos

#define OPAMP2_CSR_FORCEVP_Pos (1U)

◆ OPAMP2_CSR_LOCK

#define OPAMP2_CSR_LOCK OPAMP2_CSR_LOCK_Msk

OPAMP lock

◆ OPAMP2_CSR_LOCK_Msk

#define OPAMP2_CSR_LOCK_Msk (0x1UL << OPAMP2_CSR_LOCK_Pos)

0x80000000

◆ OPAMP2_CSR_LOCK_Pos

#define OPAMP2_CSR_LOCK_Pos (31U)

◆ OPAMP2_CSR_OPAMP2EN

#define OPAMP2_CSR_OPAMP2EN OPAMP2_CSR_OPAMP2EN_Msk

OPAMP2 enable

◆ OPAMP2_CSR_OPAMP2EN_Msk

#define OPAMP2_CSR_OPAMP2EN_Msk (0x1UL << OPAMP2_CSR_OPAMP2EN_Pos)

0x00000001

◆ OPAMP2_CSR_OPAMP2EN_Pos

#define OPAMP2_CSR_OPAMP2EN_Pos (0U)

◆ OPAMP2_CSR_OUTCAL

#define OPAMP2_CSR_OUTCAL OPAMP2_CSR_OUTCAL_Msk

OPAMP output status flag

◆ OPAMP2_CSR_OUTCAL_Msk

#define OPAMP2_CSR_OUTCAL_Msk (0x1UL << OPAMP2_CSR_OUTCAL_Pos)

0x40000000

◆ OPAMP2_CSR_OUTCAL_Pos

#define OPAMP2_CSR_OUTCAL_Pos (30U)

◆ OPAMP2_CSR_PGGAIN

#define OPAMP2_CSR_PGGAIN OPAMP2_CSR_PGGAIN_Msk

Gain in PGA mode

◆ OPAMP2_CSR_PGGAIN_0

#define OPAMP2_CSR_PGGAIN_0 (0x1UL << OPAMP2_CSR_PGGAIN_Pos)

0x00004000

◆ OPAMP2_CSR_PGGAIN_1

#define OPAMP2_CSR_PGGAIN_1 (0x2UL << OPAMP2_CSR_PGGAIN_Pos)

0x00008000

◆ OPAMP2_CSR_PGGAIN_2

#define OPAMP2_CSR_PGGAIN_2 (0x4UL << OPAMP2_CSR_PGGAIN_Pos)

0x00010000

◆ OPAMP2_CSR_PGGAIN_3

#define OPAMP2_CSR_PGGAIN_3 (0x8UL << OPAMP2_CSR_PGGAIN_Pos)

0x00020000

◆ OPAMP2_CSR_PGGAIN_Msk

#define OPAMP2_CSR_PGGAIN_Msk (0xFUL << OPAMP2_CSR_PGGAIN_Pos)

0x0003C000

◆ OPAMP2_CSR_PGGAIN_Pos

#define OPAMP2_CSR_PGGAIN_Pos (14U)

◆ OPAMP2_CSR_TCMEN

#define OPAMP2_CSR_TCMEN OPAMP2_CSR_TCMEN_Msk

Timer-Controlled Mux mode enable

◆ OPAMP2_CSR_TCMEN_Msk

#define OPAMP2_CSR_TCMEN_Msk (0x1UL << OPAMP2_CSR_TCMEN_Pos)

0x00000080

◆ OPAMP2_CSR_TCMEN_Pos

#define OPAMP2_CSR_TCMEN_Pos (7U)

◆ OPAMP2_CSR_TRIMOFFSETN

#define OPAMP2_CSR_TRIMOFFSETN OPAMP2_CSR_TRIMOFFSETN_Msk

Offset trimming value (NMOS)

◆ OPAMP2_CSR_TRIMOFFSETN_Msk

#define OPAMP2_CSR_TRIMOFFSETN_Msk (0x1FUL << OPAMP2_CSR_TRIMOFFSETN_Pos)

0x1F000000

◆ OPAMP2_CSR_TRIMOFFSETN_Pos

#define OPAMP2_CSR_TRIMOFFSETN_Pos (24U)

◆ OPAMP2_CSR_TRIMOFFSETP

#define OPAMP2_CSR_TRIMOFFSETP OPAMP2_CSR_TRIMOFFSETP_Msk

Offset trimming value (PMOS)

◆ OPAMP2_CSR_TRIMOFFSETP_Msk

#define OPAMP2_CSR_TRIMOFFSETP_Msk (0x1FUL << OPAMP2_CSR_TRIMOFFSETP_Pos)

0x00F80000

◆ OPAMP2_CSR_TRIMOFFSETP_Pos

#define OPAMP2_CSR_TRIMOFFSETP_Pos (19U)

◆ OPAMP2_CSR_TSTREF

#define OPAMP2_CSR_TSTREF OPAMP2_CSR_TSTREF_Msk

It enables the switch to put out the internal reference

◆ OPAMP2_CSR_TSTREF_Msk

#define OPAMP2_CSR_TSTREF_Msk (0x1UL << OPAMP2_CSR_TSTREF_Pos)

0x20000000

◆ OPAMP2_CSR_TSTREF_Pos

#define OPAMP2_CSR_TSTREF_Pos (29U)

◆ OPAMP2_CSR_USERTRIM

#define OPAMP2_CSR_USERTRIM OPAMP2_CSR_USERTRIM_Msk

User trimming enable

◆ OPAMP2_CSR_USERTRIM_Msk

#define OPAMP2_CSR_USERTRIM_Msk (0x1UL << OPAMP2_CSR_USERTRIM_Pos)

0x00040000

◆ OPAMP2_CSR_USERTRIM_Pos

#define OPAMP2_CSR_USERTRIM_Pos (18U)

◆ OPAMP2_CSR_VMSEL

#define OPAMP2_CSR_VMSEL OPAMP2_CSR_VMSEL_Msk

Inverting input selection

◆ OPAMP2_CSR_VMSEL_0

#define OPAMP2_CSR_VMSEL_0 (0x1UL << OPAMP2_CSR_VMSEL_Pos)

0x00000020

◆ OPAMP2_CSR_VMSEL_1

#define OPAMP2_CSR_VMSEL_1 (0x2UL << OPAMP2_CSR_VMSEL_Pos)

0x00000040

◆ OPAMP2_CSR_VMSEL_Msk

#define OPAMP2_CSR_VMSEL_Msk (0x3UL << OPAMP2_CSR_VMSEL_Pos)

0x00000060

◆ OPAMP2_CSR_VMSEL_Pos

#define OPAMP2_CSR_VMSEL_Pos (5U)

◆ OPAMP2_CSR_VMSSEL

#define OPAMP2_CSR_VMSSEL OPAMP2_CSR_VMSSEL_Msk

Inverting input secondary selection

◆ OPAMP2_CSR_VMSSEL_Msk

#define OPAMP2_CSR_VMSSEL_Msk (0x1UL << OPAMP2_CSR_VMSSEL_Pos)

0x00000100

◆ OPAMP2_CSR_VMSSEL_Pos

#define OPAMP2_CSR_VMSSEL_Pos (8U)

◆ OPAMP2_CSR_VPSEL

#define OPAMP2_CSR_VPSEL OPAMP2_CSR_VPSEL_Msk

Non inverting input selection

◆ OPAMP2_CSR_VPSEL_0

#define OPAMP2_CSR_VPSEL_0 (0x1UL << OPAMP2_CSR_VPSEL_Pos)

0x00000004

◆ OPAMP2_CSR_VPSEL_1

#define OPAMP2_CSR_VPSEL_1 (0x2UL << OPAMP2_CSR_VPSEL_Pos)

0x00000008

◆ OPAMP2_CSR_VPSEL_Msk

#define OPAMP2_CSR_VPSEL_Msk (0x3UL << OPAMP2_CSR_VPSEL_Pos)

0x0000000C

◆ OPAMP2_CSR_VPSEL_Pos

#define OPAMP2_CSR_VPSEL_Pos (2U)

◆ OPAMP2_CSR_VPSSEL

#define OPAMP2_CSR_VPSSEL OPAMP2_CSR_VPSSEL_Msk

Non inverting input secondary selection

◆ OPAMP2_CSR_VPSSEL_0

#define OPAMP2_CSR_VPSSEL_0 (0x1UL << OPAMP2_CSR_VPSSEL_Pos)

0x00000200

◆ OPAMP2_CSR_VPSSEL_1

#define OPAMP2_CSR_VPSSEL_1 (0x2UL << OPAMP2_CSR_VPSSEL_Pos)

0x00000400

◆ OPAMP2_CSR_VPSSEL_Msk

#define OPAMP2_CSR_VPSSEL_Msk (0x3UL << OPAMP2_CSR_VPSSEL_Pos)

0x00000600

◆ OPAMP2_CSR_VPSSEL_Pos

#define OPAMP2_CSR_VPSSEL_Pos (9U)

◆ OPAMP3_CSR_CALON

#define OPAMP3_CSR_CALON OPAMP3_CSR_CALON_Msk

Calibration mode enable

◆ OPAMP3_CSR_CALON_Msk

#define OPAMP3_CSR_CALON_Msk (0x1UL << OPAMP3_CSR_CALON_Pos)

0x00000800

◆ OPAMP3_CSR_CALON_Pos

#define OPAMP3_CSR_CALON_Pos (11U)

◆ OPAMP3_CSR_CALSEL

#define OPAMP3_CSR_CALSEL OPAMP3_CSR_CALSEL_Msk

Calibration selection

◆ OPAMP3_CSR_CALSEL_0

#define OPAMP3_CSR_CALSEL_0 (0x1UL << OPAMP3_CSR_CALSEL_Pos)

0x00001000

◆ OPAMP3_CSR_CALSEL_1

#define OPAMP3_CSR_CALSEL_1 (0x2UL << OPAMP3_CSR_CALSEL_Pos)

0x00002000

◆ OPAMP3_CSR_CALSEL_Msk

#define OPAMP3_CSR_CALSEL_Msk (0x3UL << OPAMP3_CSR_CALSEL_Pos)

0x00003000

◆ OPAMP3_CSR_CALSEL_Pos

#define OPAMP3_CSR_CALSEL_Pos (12U)

◆ OPAMP3_CSR_FORCEVP

#define OPAMP3_CSR_FORCEVP OPAMP3_CSR_FORCEVP_Msk

Connect the internal references to the plus input of the OPAMPX

◆ OPAMP3_CSR_FORCEVP_Msk

#define OPAMP3_CSR_FORCEVP_Msk (0x1UL << OPAMP3_CSR_FORCEVP_Pos)

0x00000002

◆ OPAMP3_CSR_FORCEVP_Pos

#define OPAMP3_CSR_FORCEVP_Pos (1U)

◆ OPAMP3_CSR_LOCK

#define OPAMP3_CSR_LOCK OPAMP3_CSR_LOCK_Msk

OPAMP lock

◆ OPAMP3_CSR_LOCK_Msk

#define OPAMP3_CSR_LOCK_Msk (0x1UL << OPAMP3_CSR_LOCK_Pos)

0x80000000

◆ OPAMP3_CSR_LOCK_Pos

#define OPAMP3_CSR_LOCK_Pos (31U)

◆ OPAMP3_CSR_OPAMP3EN

#define OPAMP3_CSR_OPAMP3EN OPAMP3_CSR_OPAMP3EN_Msk

OPAMP3 enable

◆ OPAMP3_CSR_OPAMP3EN_Msk

#define OPAMP3_CSR_OPAMP3EN_Msk (0x1UL << OPAMP3_CSR_OPAMP3EN_Pos)

0x00000001

◆ OPAMP3_CSR_OPAMP3EN_Pos

#define OPAMP3_CSR_OPAMP3EN_Pos (0U)

◆ OPAMP3_CSR_OUTCAL

#define OPAMP3_CSR_OUTCAL OPAMP3_CSR_OUTCAL_Msk

OPAMP output status flag

◆ OPAMP3_CSR_OUTCAL_Msk

#define OPAMP3_CSR_OUTCAL_Msk (0x1UL << OPAMP3_CSR_OUTCAL_Pos)

0x40000000

◆ OPAMP3_CSR_OUTCAL_Pos

#define OPAMP3_CSR_OUTCAL_Pos (30U)

◆ OPAMP3_CSR_PGGAIN

#define OPAMP3_CSR_PGGAIN OPAMP3_CSR_PGGAIN_Msk

Gain in PGA mode

◆ OPAMP3_CSR_PGGAIN_0

#define OPAMP3_CSR_PGGAIN_0 (0x1UL << OPAMP3_CSR_PGGAIN_Pos)

0x00004000

◆ OPAMP3_CSR_PGGAIN_1

#define OPAMP3_CSR_PGGAIN_1 (0x2UL << OPAMP3_CSR_PGGAIN_Pos)

0x00008000

◆ OPAMP3_CSR_PGGAIN_2

#define OPAMP3_CSR_PGGAIN_2 (0x4UL << OPAMP3_CSR_PGGAIN_Pos)

0x00010000

◆ OPAMP3_CSR_PGGAIN_3

#define OPAMP3_CSR_PGGAIN_3 (0x8UL << OPAMP3_CSR_PGGAIN_Pos)

0x00020000

◆ OPAMP3_CSR_PGGAIN_Msk

#define OPAMP3_CSR_PGGAIN_Msk (0xFUL << OPAMP3_CSR_PGGAIN_Pos)

0x0003C000

◆ OPAMP3_CSR_PGGAIN_Pos

#define OPAMP3_CSR_PGGAIN_Pos (14U)

◆ OPAMP3_CSR_TCMEN

#define OPAMP3_CSR_TCMEN OPAMP3_CSR_TCMEN_Msk

Timer-Controlled Mux mode enable

◆ OPAMP3_CSR_TCMEN_Msk

#define OPAMP3_CSR_TCMEN_Msk (0x1UL << OPAMP3_CSR_TCMEN_Pos)

0x00000080

◆ OPAMP3_CSR_TCMEN_Pos

#define OPAMP3_CSR_TCMEN_Pos (7U)

◆ OPAMP3_CSR_TRIMOFFSETN

#define OPAMP3_CSR_TRIMOFFSETN OPAMP3_CSR_TRIMOFFSETN_Msk

Offset trimming value (NMOS)

◆ OPAMP3_CSR_TRIMOFFSETN_Msk

#define OPAMP3_CSR_TRIMOFFSETN_Msk (0x1FUL << OPAMP3_CSR_TRIMOFFSETN_Pos)

0x1F000000

◆ OPAMP3_CSR_TRIMOFFSETN_Pos

#define OPAMP3_CSR_TRIMOFFSETN_Pos (24U)

◆ OPAMP3_CSR_TRIMOFFSETP

#define OPAMP3_CSR_TRIMOFFSETP OPAMP3_CSR_TRIMOFFSETP_Msk

Offset trimming value (PMOS)

◆ OPAMP3_CSR_TRIMOFFSETP_Msk

#define OPAMP3_CSR_TRIMOFFSETP_Msk (0x1FUL << OPAMP3_CSR_TRIMOFFSETP_Pos)

0x00F80000

◆ OPAMP3_CSR_TRIMOFFSETP_Pos

#define OPAMP3_CSR_TRIMOFFSETP_Pos (19U)

◆ OPAMP3_CSR_TSTREF

#define OPAMP3_CSR_TSTREF OPAMP3_CSR_TSTREF_Msk

It enables the switch to put out the internal reference

◆ OPAMP3_CSR_TSTREF_Msk

#define OPAMP3_CSR_TSTREF_Msk (0x1UL << OPAMP3_CSR_TSTREF_Pos)

0x20000000

◆ OPAMP3_CSR_TSTREF_Pos

#define OPAMP3_CSR_TSTREF_Pos (29U)

◆ OPAMP3_CSR_USERTRIM

#define OPAMP3_CSR_USERTRIM OPAMP3_CSR_USERTRIM_Msk

User trimming enable

◆ OPAMP3_CSR_USERTRIM_Msk

#define OPAMP3_CSR_USERTRIM_Msk (0x1UL << OPAMP3_CSR_USERTRIM_Pos)

0x00040000

◆ OPAMP3_CSR_USERTRIM_Pos

#define OPAMP3_CSR_USERTRIM_Pos (18U)

◆ OPAMP3_CSR_VMSEL

#define OPAMP3_CSR_VMSEL OPAMP3_CSR_VMSEL_Msk

Inverting input selection

◆ OPAMP3_CSR_VMSEL_0

#define OPAMP3_CSR_VMSEL_0 (0x1UL << OPAMP3_CSR_VMSEL_Pos)

0x00000020

◆ OPAMP3_CSR_VMSEL_1

#define OPAMP3_CSR_VMSEL_1 (0x2UL << OPAMP3_CSR_VMSEL_Pos)

0x00000040

◆ OPAMP3_CSR_VMSEL_Msk

#define OPAMP3_CSR_VMSEL_Msk (0x3UL << OPAMP3_CSR_VMSEL_Pos)

0x00000060

◆ OPAMP3_CSR_VMSEL_Pos

#define OPAMP3_CSR_VMSEL_Pos (5U)

◆ OPAMP3_CSR_VMSSEL

#define OPAMP3_CSR_VMSSEL OPAMP3_CSR_VMSSEL_Msk

Inverting input secondary selection

◆ OPAMP3_CSR_VMSSEL_Msk

#define OPAMP3_CSR_VMSSEL_Msk (0x1UL << OPAMP3_CSR_VMSSEL_Pos)

0x00000100

◆ OPAMP3_CSR_VMSSEL_Pos

#define OPAMP3_CSR_VMSSEL_Pos (8U)

◆ OPAMP3_CSR_VPSEL

#define OPAMP3_CSR_VPSEL OPAMP3_CSR_VPSEL_Msk

Non inverting input selection

◆ OPAMP3_CSR_VPSEL_0

#define OPAMP3_CSR_VPSEL_0 (0x1UL << OPAMP3_CSR_VPSEL_Pos)

0x00000004

◆ OPAMP3_CSR_VPSEL_1

#define OPAMP3_CSR_VPSEL_1 (0x2UL << OPAMP3_CSR_VPSEL_Pos)

0x00000008

◆ OPAMP3_CSR_VPSEL_Msk

#define OPAMP3_CSR_VPSEL_Msk (0x3UL << OPAMP3_CSR_VPSEL_Pos)

0x0000000C

◆ OPAMP3_CSR_VPSEL_Pos

#define OPAMP3_CSR_VPSEL_Pos (2U)

◆ OPAMP3_CSR_VPSSEL

#define OPAMP3_CSR_VPSSEL OPAMP3_CSR_VPSSEL_Msk

Non inverting input secondary selection

◆ OPAMP3_CSR_VPSSEL_0

#define OPAMP3_CSR_VPSSEL_0 (0x1UL << OPAMP3_CSR_VPSSEL_Pos)

0x00000200

◆ OPAMP3_CSR_VPSSEL_1

#define OPAMP3_CSR_VPSSEL_1 (0x2UL << OPAMP3_CSR_VPSSEL_Pos)

0x00000400

◆ OPAMP3_CSR_VPSSEL_Msk

#define OPAMP3_CSR_VPSSEL_Msk (0x3UL << OPAMP3_CSR_VPSSEL_Pos)

0x00000600

◆ OPAMP3_CSR_VPSSEL_Pos

#define OPAMP3_CSR_VPSSEL_Pos (9U)

◆ OPAMP4_CSR_CALON

#define OPAMP4_CSR_CALON OPAMP4_CSR_CALON_Msk

Calibration mode enable

◆ OPAMP4_CSR_CALON_Msk

#define OPAMP4_CSR_CALON_Msk (0x1UL << OPAMP4_CSR_CALON_Pos)

0x00000800

◆ OPAMP4_CSR_CALON_Pos

#define OPAMP4_CSR_CALON_Pos (11U)

◆ OPAMP4_CSR_CALSEL

#define OPAMP4_CSR_CALSEL OPAMP4_CSR_CALSEL_Msk

Calibration selection

◆ OPAMP4_CSR_CALSEL_0

#define OPAMP4_CSR_CALSEL_0 (0x1UL << OPAMP4_CSR_CALSEL_Pos)

0x00001000

◆ OPAMP4_CSR_CALSEL_1

#define OPAMP4_CSR_CALSEL_1 (0x2UL << OPAMP4_CSR_CALSEL_Pos)

0x00002000

◆ OPAMP4_CSR_CALSEL_Msk

#define OPAMP4_CSR_CALSEL_Msk (0x3UL << OPAMP4_CSR_CALSEL_Pos)

0x00003000

◆ OPAMP4_CSR_CALSEL_Pos

#define OPAMP4_CSR_CALSEL_Pos (12U)

◆ OPAMP4_CSR_FORCEVP

#define OPAMP4_CSR_FORCEVP OPAMP4_CSR_FORCEVP_Msk

Connect the internal references to the plus input of the OPAMPX

◆ OPAMP4_CSR_FORCEVP_Msk

#define OPAMP4_CSR_FORCEVP_Msk (0x1UL << OPAMP4_CSR_FORCEVP_Pos)

0x00000002

◆ OPAMP4_CSR_FORCEVP_Pos

#define OPAMP4_CSR_FORCEVP_Pos (1U)

◆ OPAMP4_CSR_LOCK

#define OPAMP4_CSR_LOCK OPAMP4_CSR_LOCK_Msk

OPAMP lock

◆ OPAMP4_CSR_LOCK_Msk

#define OPAMP4_CSR_LOCK_Msk (0x1UL << OPAMP4_CSR_LOCK_Pos)

0x80000000

◆ OPAMP4_CSR_LOCK_Pos

#define OPAMP4_CSR_LOCK_Pos (31U)

◆ OPAMP4_CSR_OPAMP4EN

#define OPAMP4_CSR_OPAMP4EN OPAMP4_CSR_OPAMP4EN_Msk

OPAMP4 enable

◆ OPAMP4_CSR_OPAMP4EN_Msk

#define OPAMP4_CSR_OPAMP4EN_Msk (0x1UL << OPAMP4_CSR_OPAMP4EN_Pos)

0x00000001

◆ OPAMP4_CSR_OPAMP4EN_Pos

#define OPAMP4_CSR_OPAMP4EN_Pos (0U)

◆ OPAMP4_CSR_OUTCAL

#define OPAMP4_CSR_OUTCAL OPAMP4_CSR_OUTCAL_Msk

OPAMP output status flag

◆ OPAMP4_CSR_OUTCAL_Msk

#define OPAMP4_CSR_OUTCAL_Msk (0x1UL << OPAMP4_CSR_OUTCAL_Pos)

0x40000000

◆ OPAMP4_CSR_OUTCAL_Pos

#define OPAMP4_CSR_OUTCAL_Pos (30U)

◆ OPAMP4_CSR_PGGAIN

#define OPAMP4_CSR_PGGAIN OPAMP4_CSR_PGGAIN_Msk

Gain in PGA mode

◆ OPAMP4_CSR_PGGAIN_0

#define OPAMP4_CSR_PGGAIN_0 (0x1UL << OPAMP4_CSR_PGGAIN_Pos)

0x00004000

◆ OPAMP4_CSR_PGGAIN_1

#define OPAMP4_CSR_PGGAIN_1 (0x2UL << OPAMP4_CSR_PGGAIN_Pos)

0x00008000

◆ OPAMP4_CSR_PGGAIN_2

#define OPAMP4_CSR_PGGAIN_2 (0x4UL << OPAMP4_CSR_PGGAIN_Pos)

0x00010000

◆ OPAMP4_CSR_PGGAIN_3

#define OPAMP4_CSR_PGGAIN_3 (0x8UL << OPAMP4_CSR_PGGAIN_Pos)

0x00020000

◆ OPAMP4_CSR_PGGAIN_Msk

#define OPAMP4_CSR_PGGAIN_Msk (0xFUL << OPAMP4_CSR_PGGAIN_Pos)

0x0003C000

◆ OPAMP4_CSR_PGGAIN_Pos

#define OPAMP4_CSR_PGGAIN_Pos (14U)

◆ OPAMP4_CSR_TCMEN

#define OPAMP4_CSR_TCMEN OPAMP4_CSR_TCMEN_Msk

Timer-Controlled Mux mode enable

◆ OPAMP4_CSR_TCMEN_Msk

#define OPAMP4_CSR_TCMEN_Msk (0x1UL << OPAMP4_CSR_TCMEN_Pos)

0x00000080

◆ OPAMP4_CSR_TCMEN_Pos

#define OPAMP4_CSR_TCMEN_Pos (7U)

◆ OPAMP4_CSR_TRIMOFFSETN

#define OPAMP4_CSR_TRIMOFFSETN OPAMP4_CSR_TRIMOFFSETN_Msk

Offset trimming value (NMOS)

◆ OPAMP4_CSR_TRIMOFFSETN_Msk

#define OPAMP4_CSR_TRIMOFFSETN_Msk (0x1FUL << OPAMP4_CSR_TRIMOFFSETN_Pos)

0x1F000000

◆ OPAMP4_CSR_TRIMOFFSETN_Pos

#define OPAMP4_CSR_TRIMOFFSETN_Pos (24U)

◆ OPAMP4_CSR_TRIMOFFSETP

#define OPAMP4_CSR_TRIMOFFSETP OPAMP4_CSR_TRIMOFFSETP_Msk

Offset trimming value (PMOS)

◆ OPAMP4_CSR_TRIMOFFSETP_Msk

#define OPAMP4_CSR_TRIMOFFSETP_Msk (0x1FUL << OPAMP4_CSR_TRIMOFFSETP_Pos)

0x00F80000

◆ OPAMP4_CSR_TRIMOFFSETP_Pos

#define OPAMP4_CSR_TRIMOFFSETP_Pos (19U)

◆ OPAMP4_CSR_TSTREF

#define OPAMP4_CSR_TSTREF OPAMP4_CSR_TSTREF_Msk

It enables the switch to put out the internal reference

◆ OPAMP4_CSR_TSTREF_Msk

#define OPAMP4_CSR_TSTREF_Msk (0x1UL << OPAMP4_CSR_TSTREF_Pos)

0x20000000

◆ OPAMP4_CSR_TSTREF_Pos

#define OPAMP4_CSR_TSTREF_Pos (29U)

◆ OPAMP4_CSR_USERTRIM

#define OPAMP4_CSR_USERTRIM OPAMP4_CSR_USERTRIM_Msk

User trimming enable

◆ OPAMP4_CSR_USERTRIM_Msk

#define OPAMP4_CSR_USERTRIM_Msk (0x1UL << OPAMP4_CSR_USERTRIM_Pos)

0x00040000

◆ OPAMP4_CSR_USERTRIM_Pos

#define OPAMP4_CSR_USERTRIM_Pos (18U)

◆ OPAMP4_CSR_VMSEL

#define OPAMP4_CSR_VMSEL OPAMP4_CSR_VMSEL_Msk

Inverting input selection

◆ OPAMP4_CSR_VMSEL_0

#define OPAMP4_CSR_VMSEL_0 (0x1UL << OPAMP4_CSR_VMSEL_Pos)

0x00000020

◆ OPAMP4_CSR_VMSEL_1

#define OPAMP4_CSR_VMSEL_1 (0x2UL << OPAMP4_CSR_VMSEL_Pos)

0x00000040

◆ OPAMP4_CSR_VMSEL_Msk

#define OPAMP4_CSR_VMSEL_Msk (0x3UL << OPAMP4_CSR_VMSEL_Pos)

0x00000060

◆ OPAMP4_CSR_VMSEL_Pos

#define OPAMP4_CSR_VMSEL_Pos (5U)

◆ OPAMP4_CSR_VMSSEL

#define OPAMP4_CSR_VMSSEL OPAMP4_CSR_VMSSEL_Msk

Inverting input secondary selection

◆ OPAMP4_CSR_VMSSEL_Msk

#define OPAMP4_CSR_VMSSEL_Msk (0x1UL << OPAMP4_CSR_VMSSEL_Pos)

0x00000100

◆ OPAMP4_CSR_VMSSEL_Pos

#define OPAMP4_CSR_VMSSEL_Pos (8U)

◆ OPAMP4_CSR_VPSEL

#define OPAMP4_CSR_VPSEL OPAMP4_CSR_VPSEL_Msk

Non inverting input selection

◆ OPAMP4_CSR_VPSEL_0

#define OPAMP4_CSR_VPSEL_0 (0x1UL << OPAMP4_CSR_VPSEL_Pos)

0x00000004

◆ OPAMP4_CSR_VPSEL_1

#define OPAMP4_CSR_VPSEL_1 (0x2UL << OPAMP4_CSR_VPSEL_Pos)

0x00000008

◆ OPAMP4_CSR_VPSEL_Msk

#define OPAMP4_CSR_VPSEL_Msk (0x3UL << OPAMP4_CSR_VPSEL_Pos)

0x0000000C

◆ OPAMP4_CSR_VPSEL_Pos

#define OPAMP4_CSR_VPSEL_Pos (2U)

◆ OPAMP4_CSR_VPSSEL

#define OPAMP4_CSR_VPSSEL OPAMP4_CSR_VPSSEL_Msk

Non inverting input secondary selection

◆ OPAMP4_CSR_VPSSEL_0

#define OPAMP4_CSR_VPSSEL_0 (0x1UL << OPAMP4_CSR_VPSSEL_Pos)

0x00000200

◆ OPAMP4_CSR_VPSSEL_1

#define OPAMP4_CSR_VPSSEL_1 (0x2UL << OPAMP4_CSR_VPSSEL_Pos)

0x00000400

◆ OPAMP4_CSR_VPSSEL_Msk

#define OPAMP4_CSR_VPSSEL_Msk (0x3UL << OPAMP4_CSR_VPSSEL_Pos)

0x00000600

◆ OPAMP4_CSR_VPSSEL_Pos

#define OPAMP4_CSR_VPSSEL_Pos (9U)

◆ OPAMP_CSR_CALON

#define OPAMP_CSR_CALON OPAMP_CSR_CALON_Msk

Calibration mode enable

◆ OPAMP_CSR_CALON_Msk

#define OPAMP_CSR_CALON_Msk (0x1UL << OPAMP_CSR_CALON_Pos)

0x00000800

◆ OPAMP_CSR_CALON_Pos

#define OPAMP_CSR_CALON_Pos (11U)

◆ OPAMP_CSR_CALSEL

#define OPAMP_CSR_CALSEL OPAMP_CSR_CALSEL_Msk

Calibration selection

◆ OPAMP_CSR_CALSEL_0

#define OPAMP_CSR_CALSEL_0 (0x1UL << OPAMP_CSR_CALSEL_Pos)

0x00001000

◆ OPAMP_CSR_CALSEL_1

#define OPAMP_CSR_CALSEL_1 (0x2UL << OPAMP_CSR_CALSEL_Pos)

0x00002000

◆ OPAMP_CSR_CALSEL_Msk

#define OPAMP_CSR_CALSEL_Msk (0x3UL << OPAMP_CSR_CALSEL_Pos)

0x00003000

◆ OPAMP_CSR_CALSEL_Pos

#define OPAMP_CSR_CALSEL_Pos (12U)

◆ OPAMP_CSR_FORCEVP

#define OPAMP_CSR_FORCEVP OPAMP_CSR_FORCEVP_Msk

Connect the internal references to the plus input of the OPAMPX

◆ OPAMP_CSR_FORCEVP_Msk

#define OPAMP_CSR_FORCEVP_Msk (0x1UL << OPAMP_CSR_FORCEVP_Pos)

0x00000002

◆ OPAMP_CSR_FORCEVP_Pos

#define OPAMP_CSR_FORCEVP_Pos (1U)

◆ OPAMP_CSR_LOCK

#define OPAMP_CSR_LOCK OPAMP_CSR_LOCK_Msk

OPAMP lock

◆ OPAMP_CSR_LOCK_Msk

#define OPAMP_CSR_LOCK_Msk (0x1UL << OPAMP_CSR_LOCK_Pos)

0x80000000

◆ OPAMP_CSR_LOCK_Pos

#define OPAMP_CSR_LOCK_Pos (31U)

◆ OPAMP_CSR_OPAMPxEN

#define OPAMP_CSR_OPAMPxEN OPAMP_CSR_OPAMPxEN_Msk

OPAMP enable

◆ OPAMP_CSR_OPAMPxEN_Msk

#define OPAMP_CSR_OPAMPxEN_Msk (0x1UL << OPAMP_CSR_OPAMPxEN_Pos)

0x00000001

◆ OPAMP_CSR_OPAMPxEN_Pos

#define OPAMP_CSR_OPAMPxEN_Pos (0U)

◆ OPAMP_CSR_OUTCAL

#define OPAMP_CSR_OUTCAL OPAMP_CSR_OUTCAL_Msk

OPAMP output status flag

◆ OPAMP_CSR_OUTCAL_Msk

#define OPAMP_CSR_OUTCAL_Msk (0x1UL << OPAMP_CSR_OUTCAL_Pos)

0x40000000

◆ OPAMP_CSR_OUTCAL_Pos

#define OPAMP_CSR_OUTCAL_Pos (30U)

◆ OPAMP_CSR_PGGAIN

#define OPAMP_CSR_PGGAIN OPAMP_CSR_PGGAIN_Msk

Gain in PGA mode

◆ OPAMP_CSR_PGGAIN_0

#define OPAMP_CSR_PGGAIN_0 (0x1UL << OPAMP_CSR_PGGAIN_Pos)

0x00004000

◆ OPAMP_CSR_PGGAIN_1

#define OPAMP_CSR_PGGAIN_1 (0x2UL << OPAMP_CSR_PGGAIN_Pos)

0x00008000

◆ OPAMP_CSR_PGGAIN_2

#define OPAMP_CSR_PGGAIN_2 (0x4UL << OPAMP_CSR_PGGAIN_Pos)

0x00010000

◆ OPAMP_CSR_PGGAIN_3

#define OPAMP_CSR_PGGAIN_3 (0x8UL << OPAMP_CSR_PGGAIN_Pos)

0x00020000

◆ OPAMP_CSR_PGGAIN_Msk

#define OPAMP_CSR_PGGAIN_Msk (0xFUL << OPAMP_CSR_PGGAIN_Pos)

0x0003C000

◆ OPAMP_CSR_PGGAIN_Pos

#define OPAMP_CSR_PGGAIN_Pos (14U)

◆ OPAMP_CSR_TCMEN

#define OPAMP_CSR_TCMEN OPAMP_CSR_TCMEN_Msk

Timer-Controlled Mux mode enable

◆ OPAMP_CSR_TCMEN_Msk

#define OPAMP_CSR_TCMEN_Msk (0x1UL << OPAMP_CSR_TCMEN_Pos)

0x00000080

◆ OPAMP_CSR_TCMEN_Pos

#define OPAMP_CSR_TCMEN_Pos (7U)

◆ OPAMP_CSR_TRIMOFFSETN

#define OPAMP_CSR_TRIMOFFSETN OPAMP_CSR_TRIMOFFSETN_Msk

Offset trimming value (NMOS)

◆ OPAMP_CSR_TRIMOFFSETN_Msk

#define OPAMP_CSR_TRIMOFFSETN_Msk (0x1FUL << OPAMP_CSR_TRIMOFFSETN_Pos)

0x1F000000

◆ OPAMP_CSR_TRIMOFFSETN_Pos

#define OPAMP_CSR_TRIMOFFSETN_Pos (24U)

◆ OPAMP_CSR_TRIMOFFSETP

#define OPAMP_CSR_TRIMOFFSETP OPAMP_CSR_TRIMOFFSETP_Msk

Offset trimming value (PMOS)

◆ OPAMP_CSR_TRIMOFFSETP_Msk

#define OPAMP_CSR_TRIMOFFSETP_Msk (0x1FUL << OPAMP_CSR_TRIMOFFSETP_Pos)

0x00F80000

◆ OPAMP_CSR_TRIMOFFSETP_Pos

#define OPAMP_CSR_TRIMOFFSETP_Pos (19U)

◆ OPAMP_CSR_TSTREF

#define OPAMP_CSR_TSTREF OPAMP_CSR_TSTREF_Msk

It enables the switch to put out the internal reference

◆ OPAMP_CSR_TSTREF_Msk

#define OPAMP_CSR_TSTREF_Msk (0x1UL << OPAMP_CSR_TSTREF_Pos)

0x20000000

◆ OPAMP_CSR_TSTREF_Pos

#define OPAMP_CSR_TSTREF_Pos (29U)

◆ OPAMP_CSR_USERTRIM

#define OPAMP_CSR_USERTRIM OPAMP_CSR_USERTRIM_Msk

User trimming enable

◆ OPAMP_CSR_USERTRIM_Msk

#define OPAMP_CSR_USERTRIM_Msk (0x1UL << OPAMP_CSR_USERTRIM_Pos)

0x00040000

◆ OPAMP_CSR_USERTRIM_Pos

#define OPAMP_CSR_USERTRIM_Pos (18U)

◆ OPAMP_CSR_VMSEL

#define OPAMP_CSR_VMSEL OPAMP_CSR_VMSEL_Msk

Inverting input selection

◆ OPAMP_CSR_VMSEL_0

#define OPAMP_CSR_VMSEL_0 (0x1UL << OPAMP_CSR_VMSEL_Pos)

0x00000020

◆ OPAMP_CSR_VMSEL_1

#define OPAMP_CSR_VMSEL_1 (0x2UL << OPAMP_CSR_VMSEL_Pos)

0x00000040

◆ OPAMP_CSR_VMSEL_Msk

#define OPAMP_CSR_VMSEL_Msk (0x3UL << OPAMP_CSR_VMSEL_Pos)

0x00000060

◆ OPAMP_CSR_VMSEL_Pos

#define OPAMP_CSR_VMSEL_Pos (5U)

◆ OPAMP_CSR_VMSSEL

#define OPAMP_CSR_VMSSEL OPAMP_CSR_VMSSEL_Msk

Inverting input secondary selection

◆ OPAMP_CSR_VMSSEL_Msk

#define OPAMP_CSR_VMSSEL_Msk (0x1UL << OPAMP_CSR_VMSSEL_Pos)

0x00000100

◆ OPAMP_CSR_VMSSEL_Pos

#define OPAMP_CSR_VMSSEL_Pos (8U)

◆ OPAMP_CSR_VPSEL

#define OPAMP_CSR_VPSEL OPAMP_CSR_VPSEL_Msk

Non inverting input selection

◆ OPAMP_CSR_VPSEL_0

#define OPAMP_CSR_VPSEL_0 (0x1UL << OPAMP_CSR_VPSEL_Pos)

0x00000004

◆ OPAMP_CSR_VPSEL_1

#define OPAMP_CSR_VPSEL_1 (0x2UL << OPAMP_CSR_VPSEL_Pos)

0x00000008

◆ OPAMP_CSR_VPSEL_Msk

#define OPAMP_CSR_VPSEL_Msk (0x3UL << OPAMP_CSR_VPSEL_Pos)

0x0000000C

◆ OPAMP_CSR_VPSEL_Pos

#define OPAMP_CSR_VPSEL_Pos (2U)

◆ OPAMP_CSR_VPSSEL

#define OPAMP_CSR_VPSSEL OPAMP_CSR_VPSSEL_Msk

Non inverting input secondary selection

◆ OPAMP_CSR_VPSSEL_0

#define OPAMP_CSR_VPSSEL_0 (0x1UL << OPAMP_CSR_VPSSEL_Pos)

0x00000200

◆ OPAMP_CSR_VPSSEL_1

#define OPAMP_CSR_VPSSEL_1 (0x2UL << OPAMP_CSR_VPSSEL_Pos)

0x00000400

◆ OPAMP_CSR_VPSSEL_Msk

#define OPAMP_CSR_VPSSEL_Msk (0x3UL << OPAMP_CSR_VPSSEL_Pos)

0x00000600

◆ OPAMP_CSR_VPSSEL_Pos

#define OPAMP_CSR_VPSSEL_Pos (9U)

◆ PWR_CR_CSBF

#define PWR_CR_CSBF PWR_CR_CSBF_Msk

Clear Standby Flag

◆ PWR_CR_CSBF_Msk

#define PWR_CR_CSBF_Msk (0x1UL << PWR_CR_CSBF_Pos)

0x00000008

◆ PWR_CR_CSBF_Pos

#define PWR_CR_CSBF_Pos (3U)

◆ PWR_CR_CWUF

#define PWR_CR_CWUF PWR_CR_CWUF_Msk

Clear Wakeup Flag

◆ PWR_CR_CWUF_Msk

#define PWR_CR_CWUF_Msk (0x1UL << PWR_CR_CWUF_Pos)

0x00000004

◆ PWR_CR_CWUF_Pos

#define PWR_CR_CWUF_Pos (2U)

◆ PWR_CR_DBP

#define PWR_CR_DBP PWR_CR_DBP_Msk

Disable Backup Domain write protection

◆ PWR_CR_DBP_Msk

#define PWR_CR_DBP_Msk (0x1UL << PWR_CR_DBP_Pos)

0x00000100

◆ PWR_CR_DBP_Pos

#define PWR_CR_DBP_Pos (8U)

◆ PWR_CR_LPDS

#define PWR_CR_LPDS PWR_CR_LPDS_Msk

Low-power Deepsleep

◆ PWR_CR_LPDS_Msk

#define PWR_CR_LPDS_Msk (0x1UL << PWR_CR_LPDS_Pos)

0x00000001

◆ PWR_CR_LPDS_Pos

#define PWR_CR_LPDS_Pos (0U)

◆ PWR_CR_PDDS

#define PWR_CR_PDDS PWR_CR_PDDS_Msk

Power Down Deepsleep

◆ PWR_CR_PDDS_Msk

#define PWR_CR_PDDS_Msk (0x1UL << PWR_CR_PDDS_Pos)

0x00000002

◆ PWR_CR_PDDS_Pos

#define PWR_CR_PDDS_Pos (1U)

◆ PWR_CR_PLS

#define PWR_CR_PLS PWR_CR_PLS_Msk

PLS[2:0] bits (PVD Level Selection)

◆ PWR_CR_PLS_0

#define PWR_CR_PLS_0 (0x1UL << PWR_CR_PLS_Pos)

0x00000020

◆ PWR_CR_PLS_1

#define PWR_CR_PLS_1 (0x2UL << PWR_CR_PLS_Pos)

0x00000040

◆ PWR_CR_PLS_2

#define PWR_CR_PLS_2 (0x4UL << PWR_CR_PLS_Pos)

0x00000080 PVD level configuration

◆ PWR_CR_PLS_LEV0

#define PWR_CR_PLS_LEV0 (0x00000000U)

PVD level 0

◆ PWR_CR_PLS_LEV1

#define PWR_CR_PLS_LEV1 (0x00000020U)

PVD level 1

◆ PWR_CR_PLS_LEV2

#define PWR_CR_PLS_LEV2 (0x00000040U)

PVD level 2

◆ PWR_CR_PLS_LEV3

#define PWR_CR_PLS_LEV3 (0x00000060U)

PVD level 3

◆ PWR_CR_PLS_LEV4

#define PWR_CR_PLS_LEV4 (0x00000080U)

PVD level 4

◆ PWR_CR_PLS_LEV5

#define PWR_CR_PLS_LEV5 (0x000000A0U)

PVD level 5

◆ PWR_CR_PLS_LEV6

#define PWR_CR_PLS_LEV6 (0x000000C0U)

PVD level 6

◆ PWR_CR_PLS_LEV7

#define PWR_CR_PLS_LEV7 (0x000000E0U)

PVD level 7

◆ PWR_CR_PLS_Msk

#define PWR_CR_PLS_Msk (0x7UL << PWR_CR_PLS_Pos)

0x000000E0

◆ PWR_CR_PLS_Pos

#define PWR_CR_PLS_Pos (5U)

◆ PWR_CR_PVDE

#define PWR_CR_PVDE PWR_CR_PVDE_Msk

Power Voltage Detector Enable

◆ PWR_CR_PVDE_Msk

#define PWR_CR_PVDE_Msk (0x1UL << PWR_CR_PVDE_Pos)

0x00000010

◆ PWR_CR_PVDE_Pos

#define PWR_CR_PVDE_Pos (4U)

◆ PWR_CSR_EWUP1

#define PWR_CSR_EWUP1 PWR_CSR_EWUP1_Msk

Enable WKUP pin 1

◆ PWR_CSR_EWUP1_Msk

#define PWR_CSR_EWUP1_Msk (0x1UL << PWR_CSR_EWUP1_Pos)

0x00000100

◆ PWR_CSR_EWUP1_Pos

#define PWR_CSR_EWUP1_Pos (8U)

◆ PWR_CSR_EWUP2

#define PWR_CSR_EWUP2 PWR_CSR_EWUP2_Msk

Enable WKUP pin 2

◆ PWR_CSR_EWUP2_Msk

#define PWR_CSR_EWUP2_Msk (0x1UL << PWR_CSR_EWUP2_Pos)

0x00000200

◆ PWR_CSR_EWUP2_Pos

#define PWR_CSR_EWUP2_Pos (9U)

◆ PWR_CSR_EWUP3

#define PWR_CSR_EWUP3 PWR_CSR_EWUP3_Msk

Enable WKUP pin 3

◆ PWR_CSR_EWUP3_Msk

#define PWR_CSR_EWUP3_Msk (0x1UL << PWR_CSR_EWUP3_Pos)

0x00000400

◆ PWR_CSR_EWUP3_Pos

#define PWR_CSR_EWUP3_Pos (10U)

◆ PWR_CSR_PVDO

#define PWR_CSR_PVDO PWR_CSR_PVDO_Msk

PVD Output

◆ PWR_CSR_PVDO_Msk

#define PWR_CSR_PVDO_Msk (0x1UL << PWR_CSR_PVDO_Pos)

0x00000004

◆ PWR_CSR_PVDO_Pos

#define PWR_CSR_PVDO_Pos (2U)

◆ PWR_CSR_SBF

#define PWR_CSR_SBF PWR_CSR_SBF_Msk

Standby Flag

◆ PWR_CSR_SBF_Msk

#define PWR_CSR_SBF_Msk (0x1UL << PWR_CSR_SBF_Pos)

0x00000002

◆ PWR_CSR_SBF_Pos

#define PWR_CSR_SBF_Pos (1U)

◆ PWR_CSR_VREFINTRDYF

#define PWR_CSR_VREFINTRDYF PWR_CSR_VREFINTRDYF_Msk

Internal voltage reference (VREFINT) ready flag

◆ PWR_CSR_VREFINTRDYF_Msk

#define PWR_CSR_VREFINTRDYF_Msk (0x1UL << PWR_CSR_VREFINTRDYF_Pos)

0x00000008

◆ PWR_CSR_VREFINTRDYF_Pos

#define PWR_CSR_VREFINTRDYF_Pos (3U)

◆ PWR_CSR_WUF

#define PWR_CSR_WUF PWR_CSR_WUF_Msk

Wakeup Flag

◆ PWR_CSR_WUF_Msk

#define PWR_CSR_WUF_Msk (0x1UL << PWR_CSR_WUF_Pos)

0x00000001

◆ PWR_CSR_WUF_Pos

#define PWR_CSR_WUF_Pos (0U)

◆ PWR_PVD_SUPPORT

#define PWR_PVD_SUPPORT

PWR feature available only on specific devices: Power Voltage Detection feature

◆ RCC_AHBENR_ADC12EN

#define RCC_AHBENR_ADC12EN RCC_AHBENR_ADC12EN_Msk

ADC1/ ADC2 clock enable

◆ RCC_AHBENR_ADC12EN_Msk

#define RCC_AHBENR_ADC12EN_Msk (0x1UL << RCC_AHBENR_ADC12EN_Pos)

0x10000000

◆ RCC_AHBENR_ADC12EN_Pos

#define RCC_AHBENR_ADC12EN_Pos (28U)

◆ RCC_AHBENR_ADC34EN

#define RCC_AHBENR_ADC34EN RCC_AHBENR_ADC34EN_Msk

ADC3/ ADC4 clock enable

◆ RCC_AHBENR_ADC34EN_Msk

#define RCC_AHBENR_ADC34EN_Msk (0x1UL << RCC_AHBENR_ADC34EN_Pos)

0x20000000

◆ RCC_AHBENR_ADC34EN_Pos

#define RCC_AHBENR_ADC34EN_Pos (29U)

◆ RCC_AHBENR_CRCEN

#define RCC_AHBENR_CRCEN RCC_AHBENR_CRCEN_Msk

CRC clock enable

◆ RCC_AHBENR_CRCEN_Msk

#define RCC_AHBENR_CRCEN_Msk (0x1UL << RCC_AHBENR_CRCEN_Pos)

0x00000040

◆ RCC_AHBENR_CRCEN_Pos

#define RCC_AHBENR_CRCEN_Pos (6U)

◆ RCC_AHBENR_DMA1EN

#define RCC_AHBENR_DMA1EN RCC_AHBENR_DMA1EN_Msk

DMA1 clock enable

◆ RCC_AHBENR_DMA1EN_Msk

#define RCC_AHBENR_DMA1EN_Msk (0x1UL << RCC_AHBENR_DMA1EN_Pos)

0x00000001

◆ RCC_AHBENR_DMA1EN_Pos

#define RCC_AHBENR_DMA1EN_Pos (0U)

◆ RCC_AHBENR_DMA2EN

#define RCC_AHBENR_DMA2EN RCC_AHBENR_DMA2EN_Msk

DMA2 clock enable

◆ RCC_AHBENR_DMA2EN_Msk

#define RCC_AHBENR_DMA2EN_Msk (0x1UL << RCC_AHBENR_DMA2EN_Pos)

0x00000002

◆ RCC_AHBENR_DMA2EN_Pos

#define RCC_AHBENR_DMA2EN_Pos (1U)

◆ RCC_AHBENR_FLITFEN

#define RCC_AHBENR_FLITFEN RCC_AHBENR_FLITFEN_Msk

FLITF clock enable

◆ RCC_AHBENR_FLITFEN_Msk

#define RCC_AHBENR_FLITFEN_Msk (0x1UL << RCC_AHBENR_FLITFEN_Pos)

0x00000010

◆ RCC_AHBENR_FLITFEN_Pos

#define RCC_AHBENR_FLITFEN_Pos (4U)

◆ RCC_AHBENR_FMCEN

#define RCC_AHBENR_FMCEN RCC_AHBENR_FMCEN_Msk

FMC clock enable

◆ RCC_AHBENR_FMCEN_Msk

#define RCC_AHBENR_FMCEN_Msk (0x1UL << RCC_AHBENR_FMCEN_Pos)

0x00000020

◆ RCC_AHBENR_FMCEN_Pos

#define RCC_AHBENR_FMCEN_Pos (5U)

◆ RCC_AHBENR_GPIOAEN

#define RCC_AHBENR_GPIOAEN RCC_AHBENR_GPIOAEN_Msk

GPIOA clock enable

◆ RCC_AHBENR_GPIOAEN_Msk

#define RCC_AHBENR_GPIOAEN_Msk (0x1UL << RCC_AHBENR_GPIOAEN_Pos)

0x00020000

◆ RCC_AHBENR_GPIOAEN_Pos

#define RCC_AHBENR_GPIOAEN_Pos (17U)

◆ RCC_AHBENR_GPIOBEN

#define RCC_AHBENR_GPIOBEN RCC_AHBENR_GPIOBEN_Msk

GPIOB clock enable

◆ RCC_AHBENR_GPIOBEN_Msk

#define RCC_AHBENR_GPIOBEN_Msk (0x1UL << RCC_AHBENR_GPIOBEN_Pos)

0x00040000

◆ RCC_AHBENR_GPIOBEN_Pos

#define RCC_AHBENR_GPIOBEN_Pos (18U)

◆ RCC_AHBENR_GPIOCEN

#define RCC_AHBENR_GPIOCEN RCC_AHBENR_GPIOCEN_Msk

GPIOC clock enable

◆ RCC_AHBENR_GPIOCEN_Msk

#define RCC_AHBENR_GPIOCEN_Msk (0x1UL << RCC_AHBENR_GPIOCEN_Pos)

0x00080000

◆ RCC_AHBENR_GPIOCEN_Pos

#define RCC_AHBENR_GPIOCEN_Pos (19U)

◆ RCC_AHBENR_GPIODEN

#define RCC_AHBENR_GPIODEN RCC_AHBENR_GPIODEN_Msk

GPIOD clock enable

◆ RCC_AHBENR_GPIODEN_Msk

#define RCC_AHBENR_GPIODEN_Msk (0x1UL << RCC_AHBENR_GPIODEN_Pos)

0x00100000

◆ RCC_AHBENR_GPIODEN_Pos

#define RCC_AHBENR_GPIODEN_Pos (20U)

◆ RCC_AHBENR_GPIOEEN

#define RCC_AHBENR_GPIOEEN RCC_AHBENR_GPIOEEN_Msk

GPIOE clock enable

◆ RCC_AHBENR_GPIOEEN_Msk

#define RCC_AHBENR_GPIOEEN_Msk (0x1UL << RCC_AHBENR_GPIOEEN_Pos)

0x00200000

◆ RCC_AHBENR_GPIOEEN_Pos

#define RCC_AHBENR_GPIOEEN_Pos (21U)

◆ RCC_AHBENR_GPIOFEN

#define RCC_AHBENR_GPIOFEN RCC_AHBENR_GPIOFEN_Msk

GPIOF clock enable

◆ RCC_AHBENR_GPIOFEN_Msk

#define RCC_AHBENR_GPIOFEN_Msk (0x1UL << RCC_AHBENR_GPIOFEN_Pos)

0x00400000

◆ RCC_AHBENR_GPIOFEN_Pos

#define RCC_AHBENR_GPIOFEN_Pos (22U)

◆ RCC_AHBENR_GPIOGEN

#define RCC_AHBENR_GPIOGEN RCC_AHBENR_GPIOGEN_Msk

GPIOG clock enable

◆ RCC_AHBENR_GPIOGEN_Msk

#define RCC_AHBENR_GPIOGEN_Msk (0x1UL << RCC_AHBENR_GPIOGEN_Pos)

0x00800000

◆ RCC_AHBENR_GPIOGEN_Pos

#define RCC_AHBENR_GPIOGEN_Pos (23U)

◆ RCC_AHBENR_GPIOHEN

#define RCC_AHBENR_GPIOHEN RCC_AHBENR_GPIOHEN_Msk

GPIOH clock enable

◆ RCC_AHBENR_GPIOHEN_Msk

#define RCC_AHBENR_GPIOHEN_Msk (0x1UL << RCC_AHBENR_GPIOHEN_Pos)

0x00010000

◆ RCC_AHBENR_GPIOHEN_Pos

#define RCC_AHBENR_GPIOHEN_Pos (16U)

◆ RCC_AHBENR_SRAMEN

#define RCC_AHBENR_SRAMEN RCC_AHBENR_SRAMEN_Msk

SRAM interface clock enable

◆ RCC_AHBENR_SRAMEN_Msk

#define RCC_AHBENR_SRAMEN_Msk (0x1UL << RCC_AHBENR_SRAMEN_Pos)

0x00000004

◆ RCC_AHBENR_SRAMEN_Pos

#define RCC_AHBENR_SRAMEN_Pos (2U)

◆ RCC_AHBENR_TSCEN

#define RCC_AHBENR_TSCEN RCC_AHBENR_TSCEN_Msk

TS clock enable

◆ RCC_AHBENR_TSCEN_Msk

#define RCC_AHBENR_TSCEN_Msk (0x1UL << RCC_AHBENR_TSCEN_Pos)

0x01000000

◆ RCC_AHBENR_TSCEN_Pos

#define RCC_AHBENR_TSCEN_Pos (24U)

◆ RCC_AHBRSTR_ADC12RST

#define RCC_AHBRSTR_ADC12RST RCC_AHBRSTR_ADC12RST_Msk

ADC1 & ADC2 reset

◆ RCC_AHBRSTR_ADC12RST_Msk

#define RCC_AHBRSTR_ADC12RST_Msk (0x1UL << RCC_AHBRSTR_ADC12RST_Pos)

0x10000000

◆ RCC_AHBRSTR_ADC12RST_Pos

#define RCC_AHBRSTR_ADC12RST_Pos (28U)

◆ RCC_AHBRSTR_ADC34RST

#define RCC_AHBRSTR_ADC34RST RCC_AHBRSTR_ADC34RST_Msk

ADC3 & ADC4 reset

◆ RCC_AHBRSTR_ADC34RST_Msk

#define RCC_AHBRSTR_ADC34RST_Msk (0x1UL << RCC_AHBRSTR_ADC34RST_Pos)

0x20000000

◆ RCC_AHBRSTR_ADC34RST_Pos

#define RCC_AHBRSTR_ADC34RST_Pos (29U)

◆ RCC_AHBRSTR_FMCRST

#define RCC_AHBRSTR_FMCRST RCC_AHBRSTR_FMCRST_Msk

FMC reset

◆ RCC_AHBRSTR_FMCRST_Msk

#define RCC_AHBRSTR_FMCRST_Msk (0x1UL << RCC_AHBRSTR_FMCRST_Pos)

0x00000020

◆ RCC_AHBRSTR_FMCRST_Pos

#define RCC_AHBRSTR_FMCRST_Pos (5U)

◆ RCC_AHBRSTR_GPIOARST

#define RCC_AHBRSTR_GPIOARST RCC_AHBRSTR_GPIOARST_Msk

GPIOA reset

◆ RCC_AHBRSTR_GPIOARST_Msk

#define RCC_AHBRSTR_GPIOARST_Msk (0x1UL << RCC_AHBRSTR_GPIOARST_Pos)

0x00020000

◆ RCC_AHBRSTR_GPIOARST_Pos

#define RCC_AHBRSTR_GPIOARST_Pos (17U)

◆ RCC_AHBRSTR_GPIOBRST

#define RCC_AHBRSTR_GPIOBRST RCC_AHBRSTR_GPIOBRST_Msk

GPIOB reset

◆ RCC_AHBRSTR_GPIOBRST_Msk

#define RCC_AHBRSTR_GPIOBRST_Msk (0x1UL << RCC_AHBRSTR_GPIOBRST_Pos)

0x00040000

◆ RCC_AHBRSTR_GPIOBRST_Pos

#define RCC_AHBRSTR_GPIOBRST_Pos (18U)

◆ RCC_AHBRSTR_GPIOCRST

#define RCC_AHBRSTR_GPIOCRST RCC_AHBRSTR_GPIOCRST_Msk

GPIOC reset

◆ RCC_AHBRSTR_GPIOCRST_Msk

#define RCC_AHBRSTR_GPIOCRST_Msk (0x1UL << RCC_AHBRSTR_GPIOCRST_Pos)

0x00080000

◆ RCC_AHBRSTR_GPIOCRST_Pos

#define RCC_AHBRSTR_GPIOCRST_Pos (19U)

◆ RCC_AHBRSTR_GPIODRST

#define RCC_AHBRSTR_GPIODRST RCC_AHBRSTR_GPIODRST_Msk

GPIOD reset

◆ RCC_AHBRSTR_GPIODRST_Msk

#define RCC_AHBRSTR_GPIODRST_Msk (0x1UL << RCC_AHBRSTR_GPIODRST_Pos)

0x00100000

◆ RCC_AHBRSTR_GPIODRST_Pos

#define RCC_AHBRSTR_GPIODRST_Pos (20U)

◆ RCC_AHBRSTR_GPIOERST

#define RCC_AHBRSTR_GPIOERST RCC_AHBRSTR_GPIOERST_Msk

GPIOE reset

◆ RCC_AHBRSTR_GPIOERST_Msk

#define RCC_AHBRSTR_GPIOERST_Msk (0x1UL << RCC_AHBRSTR_GPIOERST_Pos)

0x00200000

◆ RCC_AHBRSTR_GPIOERST_Pos

#define RCC_AHBRSTR_GPIOERST_Pos (21U)

◆ RCC_AHBRSTR_GPIOFRST

#define RCC_AHBRSTR_GPIOFRST RCC_AHBRSTR_GPIOFRST_Msk

GPIOF reset

◆ RCC_AHBRSTR_GPIOFRST_Msk

#define RCC_AHBRSTR_GPIOFRST_Msk (0x1UL << RCC_AHBRSTR_GPIOFRST_Pos)

0x00400000

◆ RCC_AHBRSTR_GPIOFRST_Pos

#define RCC_AHBRSTR_GPIOFRST_Pos (22U)

◆ RCC_AHBRSTR_GPIOGRST

#define RCC_AHBRSTR_GPIOGRST RCC_AHBRSTR_GPIOGRST_Msk

GPIOG reset

◆ RCC_AHBRSTR_GPIOGRST_Msk

#define RCC_AHBRSTR_GPIOGRST_Msk (0x1UL << RCC_AHBRSTR_GPIOGRST_Pos)

0x00800000

◆ RCC_AHBRSTR_GPIOGRST_Pos

#define RCC_AHBRSTR_GPIOGRST_Pos (23U)

◆ RCC_AHBRSTR_GPIOHRST

#define RCC_AHBRSTR_GPIOHRST RCC_AHBRSTR_GPIOHRST_Msk

GPIOH reset

◆ RCC_AHBRSTR_GPIOHRST_Msk

#define RCC_AHBRSTR_GPIOHRST_Msk (0x1UL << RCC_AHBRSTR_GPIOHRST_Pos)

0x00010000

◆ RCC_AHBRSTR_GPIOHRST_Pos

#define RCC_AHBRSTR_GPIOHRST_Pos (16U)

◆ RCC_AHBRSTR_TSCRST

#define RCC_AHBRSTR_TSCRST RCC_AHBRSTR_TSCRST_Msk

TSC reset

◆ RCC_AHBRSTR_TSCRST_Msk

#define RCC_AHBRSTR_TSCRST_Msk (0x1UL << RCC_AHBRSTR_TSCRST_Pos)

0x01000000

◆ RCC_AHBRSTR_TSCRST_Pos

#define RCC_AHBRSTR_TSCRST_Pos (24U)

◆ RCC_APB1ENR_CANEN

#define RCC_APB1ENR_CANEN RCC_APB1ENR_CANEN_Msk

CAN clock enable

◆ RCC_APB1ENR_CANEN_Msk

#define RCC_APB1ENR_CANEN_Msk (0x1UL << RCC_APB1ENR_CANEN_Pos)

0x02000000

◆ RCC_APB1ENR_CANEN_Pos

#define RCC_APB1ENR_CANEN_Pos (25U)

◆ RCC_APB1ENR_DAC1EN

#define RCC_APB1ENR_DAC1EN RCC_APB1ENR_DAC1EN_Msk

DAC 1 clock enable

◆ RCC_APB1ENR_DAC1EN_Msk

#define RCC_APB1ENR_DAC1EN_Msk (0x1UL << RCC_APB1ENR_DAC1EN_Pos)

0x20000000

◆ RCC_APB1ENR_DAC1EN_Pos

#define RCC_APB1ENR_DAC1EN_Pos (29U)

◆ RCC_APB1ENR_I2C1EN

#define RCC_APB1ENR_I2C1EN RCC_APB1ENR_I2C1EN_Msk

I2C 1 clock enable

◆ RCC_APB1ENR_I2C1EN_Msk

#define RCC_APB1ENR_I2C1EN_Msk (0x1UL << RCC_APB1ENR_I2C1EN_Pos)

0x00200000

◆ RCC_APB1ENR_I2C1EN_Pos

#define RCC_APB1ENR_I2C1EN_Pos (21U)

◆ RCC_APB1ENR_I2C2EN

#define RCC_APB1ENR_I2C2EN RCC_APB1ENR_I2C2EN_Msk

I2C 2 clock enable

◆ RCC_APB1ENR_I2C2EN_Msk

#define RCC_APB1ENR_I2C2EN_Msk (0x1UL << RCC_APB1ENR_I2C2EN_Pos)

0x00400000

◆ RCC_APB1ENR_I2C2EN_Pos

#define RCC_APB1ENR_I2C2EN_Pos (22U)

◆ RCC_APB1ENR_I2C3EN

#define RCC_APB1ENR_I2C3EN RCC_APB1ENR_I2C3EN_Msk

I2C 3 clock enable

◆ RCC_APB1ENR_I2C3EN_Msk

#define RCC_APB1ENR_I2C3EN_Msk (0x1UL << RCC_APB1ENR_I2C3EN_Pos)

0x40000000

◆ RCC_APB1ENR_I2C3EN_Pos

#define RCC_APB1ENR_I2C3EN_Pos (30U)

◆ RCC_APB1ENR_PWREN

#define RCC_APB1ENR_PWREN RCC_APB1ENR_PWREN_Msk

PWR clock enable

◆ RCC_APB1ENR_PWREN_Msk

#define RCC_APB1ENR_PWREN_Msk (0x1UL << RCC_APB1ENR_PWREN_Pos)

0x10000000

◆ RCC_APB1ENR_PWREN_Pos

#define RCC_APB1ENR_PWREN_Pos (28U)

◆ RCC_APB1ENR_SPI2EN

#define RCC_APB1ENR_SPI2EN RCC_APB1ENR_SPI2EN_Msk

SPI2 clock enable

◆ RCC_APB1ENR_SPI2EN_Msk

#define RCC_APB1ENR_SPI2EN_Msk (0x1UL << RCC_APB1ENR_SPI2EN_Pos)

0x00004000

◆ RCC_APB1ENR_SPI2EN_Pos

#define RCC_APB1ENR_SPI2EN_Pos (14U)

◆ RCC_APB1ENR_SPI3EN

#define RCC_APB1ENR_SPI3EN RCC_APB1ENR_SPI3EN_Msk

SPI3 clock enable

◆ RCC_APB1ENR_SPI3EN_Msk

#define RCC_APB1ENR_SPI3EN_Msk (0x1UL << RCC_APB1ENR_SPI3EN_Pos)

0x00008000

◆ RCC_APB1ENR_SPI3EN_Pos

#define RCC_APB1ENR_SPI3EN_Pos (15U)

◆ RCC_APB1ENR_TIM2EN

#define RCC_APB1ENR_TIM2EN RCC_APB1ENR_TIM2EN_Msk

Timer 2 clock enable

◆ RCC_APB1ENR_TIM2EN_Msk

#define RCC_APB1ENR_TIM2EN_Msk (0x1UL << RCC_APB1ENR_TIM2EN_Pos)

0x00000001

◆ RCC_APB1ENR_TIM2EN_Pos

#define RCC_APB1ENR_TIM2EN_Pos (0U)

◆ RCC_APB1ENR_TIM3EN

#define RCC_APB1ENR_TIM3EN RCC_APB1ENR_TIM3EN_Msk

Timer 3 clock enable

◆ RCC_APB1ENR_TIM3EN_Msk

#define RCC_APB1ENR_TIM3EN_Msk (0x1UL << RCC_APB1ENR_TIM3EN_Pos)

0x00000002

◆ RCC_APB1ENR_TIM3EN_Pos

#define RCC_APB1ENR_TIM3EN_Pos (1U)

◆ RCC_APB1ENR_TIM4EN

#define RCC_APB1ENR_TIM4EN RCC_APB1ENR_TIM4EN_Msk

Timer 4 clock enable

◆ RCC_APB1ENR_TIM4EN_Msk

#define RCC_APB1ENR_TIM4EN_Msk (0x1UL << RCC_APB1ENR_TIM4EN_Pos)

0x00000004

◆ RCC_APB1ENR_TIM4EN_Pos

#define RCC_APB1ENR_TIM4EN_Pos (2U)

◆ RCC_APB1ENR_TIM6EN

#define RCC_APB1ENR_TIM6EN RCC_APB1ENR_TIM6EN_Msk

Timer 6 clock enable

◆ RCC_APB1ENR_TIM6EN_Msk

#define RCC_APB1ENR_TIM6EN_Msk (0x1UL << RCC_APB1ENR_TIM6EN_Pos)

0x00000010

◆ RCC_APB1ENR_TIM6EN_Pos

#define RCC_APB1ENR_TIM6EN_Pos (4U)

◆ RCC_APB1ENR_TIM7EN

#define RCC_APB1ENR_TIM7EN RCC_APB1ENR_TIM7EN_Msk

Timer 7 clock enable

◆ RCC_APB1ENR_TIM7EN_Msk

#define RCC_APB1ENR_TIM7EN_Msk (0x1UL << RCC_APB1ENR_TIM7EN_Pos)

0x00000020

◆ RCC_APB1ENR_TIM7EN_Pos

#define RCC_APB1ENR_TIM7EN_Pos (5U)

◆ RCC_APB1ENR_UART4EN

#define RCC_APB1ENR_UART4EN RCC_APB1ENR_UART4EN_Msk

UART 4 clock enable

◆ RCC_APB1ENR_UART4EN_Msk

#define RCC_APB1ENR_UART4EN_Msk (0x1UL << RCC_APB1ENR_UART4EN_Pos)

0x00080000

◆ RCC_APB1ENR_UART4EN_Pos

#define RCC_APB1ENR_UART4EN_Pos (19U)

◆ RCC_APB1ENR_UART5EN

#define RCC_APB1ENR_UART5EN RCC_APB1ENR_UART5EN_Msk

UART 5 clock enable

◆ RCC_APB1ENR_UART5EN_Msk

#define RCC_APB1ENR_UART5EN_Msk (0x1UL << RCC_APB1ENR_UART5EN_Pos)

0x00100000

◆ RCC_APB1ENR_UART5EN_Pos

#define RCC_APB1ENR_UART5EN_Pos (20U)

◆ RCC_APB1ENR_USART2EN

#define RCC_APB1ENR_USART2EN RCC_APB1ENR_USART2EN_Msk

USART 2 clock enable

◆ RCC_APB1ENR_USART2EN_Msk

#define RCC_APB1ENR_USART2EN_Msk (0x1UL << RCC_APB1ENR_USART2EN_Pos)

0x00020000

◆ RCC_APB1ENR_USART2EN_Pos

#define RCC_APB1ENR_USART2EN_Pos (17U)

◆ RCC_APB1ENR_USART3EN

#define RCC_APB1ENR_USART3EN RCC_APB1ENR_USART3EN_Msk

USART 3 clock enable

◆ RCC_APB1ENR_USART3EN_Msk

#define RCC_APB1ENR_USART3EN_Msk (0x1UL << RCC_APB1ENR_USART3EN_Pos)

0x00040000

◆ RCC_APB1ENR_USART3EN_Pos

#define RCC_APB1ENR_USART3EN_Pos (18U)

◆ RCC_APB1ENR_USBEN

#define RCC_APB1ENR_USBEN RCC_APB1ENR_USBEN_Msk

USB clock enable

◆ RCC_APB1ENR_USBEN_Msk

#define RCC_APB1ENR_USBEN_Msk (0x1UL << RCC_APB1ENR_USBEN_Pos)

0x00800000

◆ RCC_APB1ENR_USBEN_Pos

#define RCC_APB1ENR_USBEN_Pos (23U)

◆ RCC_APB1ENR_WWDGEN

#define RCC_APB1ENR_WWDGEN RCC_APB1ENR_WWDGEN_Msk

Window Watchdog clock enable

◆ RCC_APB1ENR_WWDGEN_Msk

#define RCC_APB1ENR_WWDGEN_Msk (0x1UL << RCC_APB1ENR_WWDGEN_Pos)

0x00000800

◆ RCC_APB1ENR_WWDGEN_Pos

#define RCC_APB1ENR_WWDGEN_Pos (11U)

◆ RCC_APB1RSTR_CANRST

#define RCC_APB1RSTR_CANRST RCC_APB1RSTR_CANRST_Msk

CAN reset

◆ RCC_APB1RSTR_CANRST_Msk

#define RCC_APB1RSTR_CANRST_Msk (0x1UL << RCC_APB1RSTR_CANRST_Pos)

0x02000000

◆ RCC_APB1RSTR_CANRST_Pos

#define RCC_APB1RSTR_CANRST_Pos (25U)

◆ RCC_APB1RSTR_DAC1RST

#define RCC_APB1RSTR_DAC1RST RCC_APB1RSTR_DAC1RST_Msk

DAC 1 reset

◆ RCC_APB1RSTR_DAC1RST_Msk

#define RCC_APB1RSTR_DAC1RST_Msk (0x1UL << RCC_APB1RSTR_DAC1RST_Pos)

0x20000000

◆ RCC_APB1RSTR_DAC1RST_Pos

#define RCC_APB1RSTR_DAC1RST_Pos (29U)

◆ RCC_APB1RSTR_I2C1RST

#define RCC_APB1RSTR_I2C1RST RCC_APB1RSTR_I2C1RST_Msk

I2C 1 reset

◆ RCC_APB1RSTR_I2C1RST_Msk

#define RCC_APB1RSTR_I2C1RST_Msk (0x1UL << RCC_APB1RSTR_I2C1RST_Pos)

0x00200000

◆ RCC_APB1RSTR_I2C1RST_Pos

#define RCC_APB1RSTR_I2C1RST_Pos (21U)

◆ RCC_APB1RSTR_I2C2RST

#define RCC_APB1RSTR_I2C2RST RCC_APB1RSTR_I2C2RST_Msk

I2C 2 reset

◆ RCC_APB1RSTR_I2C2RST_Msk

#define RCC_APB1RSTR_I2C2RST_Msk (0x1UL << RCC_APB1RSTR_I2C2RST_Pos)

0x00400000

◆ RCC_APB1RSTR_I2C2RST_Pos

#define RCC_APB1RSTR_I2C2RST_Pos (22U)

◆ RCC_APB1RSTR_I2C3RST

#define RCC_APB1RSTR_I2C3RST RCC_APB1RSTR_I2C3RST_Msk

I2C 3 reset

◆ RCC_APB1RSTR_I2C3RST_Msk

#define RCC_APB1RSTR_I2C3RST_Msk (0x1UL << RCC_APB1RSTR_I2C3RST_Pos)

0x40000000

◆ RCC_APB1RSTR_I2C3RST_Pos

#define RCC_APB1RSTR_I2C3RST_Pos (30U)

◆ RCC_APB1RSTR_PWRRST

#define RCC_APB1RSTR_PWRRST RCC_APB1RSTR_PWRRST_Msk

PWR reset

◆ RCC_APB1RSTR_PWRRST_Msk

#define RCC_APB1RSTR_PWRRST_Msk (0x1UL << RCC_APB1RSTR_PWRRST_Pos)

0x10000000

◆ RCC_APB1RSTR_PWRRST_Pos

#define RCC_APB1RSTR_PWRRST_Pos (28U)

◆ RCC_APB1RSTR_SPI2RST

#define RCC_APB1RSTR_SPI2RST RCC_APB1RSTR_SPI2RST_Msk

SPI2 reset

◆ RCC_APB1RSTR_SPI2RST_Msk

#define RCC_APB1RSTR_SPI2RST_Msk (0x1UL << RCC_APB1RSTR_SPI2RST_Pos)

0x00004000

◆ RCC_APB1RSTR_SPI2RST_Pos

#define RCC_APB1RSTR_SPI2RST_Pos (14U)

◆ RCC_APB1RSTR_SPI3RST

#define RCC_APB1RSTR_SPI3RST RCC_APB1RSTR_SPI3RST_Msk

SPI3 reset

◆ RCC_APB1RSTR_SPI3RST_Msk

#define RCC_APB1RSTR_SPI3RST_Msk (0x1UL << RCC_APB1RSTR_SPI3RST_Pos)

0x00008000

◆ RCC_APB1RSTR_SPI3RST_Pos

#define RCC_APB1RSTR_SPI3RST_Pos (15U)

◆ RCC_APB1RSTR_TIM2RST

#define RCC_APB1RSTR_TIM2RST RCC_APB1RSTR_TIM2RST_Msk

Timer 2 reset

◆ RCC_APB1RSTR_TIM2RST_Msk

#define RCC_APB1RSTR_TIM2RST_Msk (0x1UL << RCC_APB1RSTR_TIM2RST_Pos)

0x00000001

◆ RCC_APB1RSTR_TIM2RST_Pos

#define RCC_APB1RSTR_TIM2RST_Pos (0U)

◆ RCC_APB1RSTR_TIM3RST

#define RCC_APB1RSTR_TIM3RST RCC_APB1RSTR_TIM3RST_Msk

Timer 3 reset

◆ RCC_APB1RSTR_TIM3RST_Msk

#define RCC_APB1RSTR_TIM3RST_Msk (0x1UL << RCC_APB1RSTR_TIM3RST_Pos)

0x00000002

◆ RCC_APB1RSTR_TIM3RST_Pos

#define RCC_APB1RSTR_TIM3RST_Pos (1U)

◆ RCC_APB1RSTR_TIM4RST

#define RCC_APB1RSTR_TIM4RST RCC_APB1RSTR_TIM4RST_Msk

Timer 4 reset

◆ RCC_APB1RSTR_TIM4RST_Msk

#define RCC_APB1RSTR_TIM4RST_Msk (0x1UL << RCC_APB1RSTR_TIM4RST_Pos)

0x00000004

◆ RCC_APB1RSTR_TIM4RST_Pos

#define RCC_APB1RSTR_TIM4RST_Pos (2U)

◆ RCC_APB1RSTR_TIM6RST

#define RCC_APB1RSTR_TIM6RST RCC_APB1RSTR_TIM6RST_Msk

Timer 6 reset

◆ RCC_APB1RSTR_TIM6RST_Msk

#define RCC_APB1RSTR_TIM6RST_Msk (0x1UL << RCC_APB1RSTR_TIM6RST_Pos)

0x00000010

◆ RCC_APB1RSTR_TIM6RST_Pos

#define RCC_APB1RSTR_TIM6RST_Pos (4U)

◆ RCC_APB1RSTR_TIM7RST

#define RCC_APB1RSTR_TIM7RST RCC_APB1RSTR_TIM7RST_Msk

Timer 7 reset

◆ RCC_APB1RSTR_TIM7RST_Msk

#define RCC_APB1RSTR_TIM7RST_Msk (0x1UL << RCC_APB1RSTR_TIM7RST_Pos)

0x00000020

◆ RCC_APB1RSTR_TIM7RST_Pos

#define RCC_APB1RSTR_TIM7RST_Pos (5U)

◆ RCC_APB1RSTR_UART4RST

#define RCC_APB1RSTR_UART4RST RCC_APB1RSTR_UART4RST_Msk

UART 4 reset

◆ RCC_APB1RSTR_UART4RST_Msk

#define RCC_APB1RSTR_UART4RST_Msk (0x1UL << RCC_APB1RSTR_UART4RST_Pos)

0x00080000

◆ RCC_APB1RSTR_UART4RST_Pos

#define RCC_APB1RSTR_UART4RST_Pos (19U)

◆ RCC_APB1RSTR_UART5RST

#define RCC_APB1RSTR_UART5RST RCC_APB1RSTR_UART5RST_Msk

UART 5 reset

◆ RCC_APB1RSTR_UART5RST_Msk

#define RCC_APB1RSTR_UART5RST_Msk (0x1UL << RCC_APB1RSTR_UART5RST_Pos)

0x00100000

◆ RCC_APB1RSTR_UART5RST_Pos

#define RCC_APB1RSTR_UART5RST_Pos (20U)

◆ RCC_APB1RSTR_USART2RST

#define RCC_APB1RSTR_USART2RST RCC_APB1RSTR_USART2RST_Msk

USART 2 reset

◆ RCC_APB1RSTR_USART2RST_Msk

#define RCC_APB1RSTR_USART2RST_Msk (0x1UL << RCC_APB1RSTR_USART2RST_Pos)

0x00020000

◆ RCC_APB1RSTR_USART2RST_Pos

#define RCC_APB1RSTR_USART2RST_Pos (17U)

◆ RCC_APB1RSTR_USART3RST

#define RCC_APB1RSTR_USART3RST RCC_APB1RSTR_USART3RST_Msk

USART 3 reset

◆ RCC_APB1RSTR_USART3RST_Msk

#define RCC_APB1RSTR_USART3RST_Msk (0x1UL << RCC_APB1RSTR_USART3RST_Pos)

0x00040000

◆ RCC_APB1RSTR_USART3RST_Pos

#define RCC_APB1RSTR_USART3RST_Pos (18U)

◆ RCC_APB1RSTR_USBRST

#define RCC_APB1RSTR_USBRST RCC_APB1RSTR_USBRST_Msk

USB reset

◆ RCC_APB1RSTR_USBRST_Msk

#define RCC_APB1RSTR_USBRST_Msk (0x1UL << RCC_APB1RSTR_USBRST_Pos)

0x00800000

◆ RCC_APB1RSTR_USBRST_Pos

#define RCC_APB1RSTR_USBRST_Pos (23U)

◆ RCC_APB1RSTR_WWDGRST

#define RCC_APB1RSTR_WWDGRST RCC_APB1RSTR_WWDGRST_Msk

Window Watchdog reset

◆ RCC_APB1RSTR_WWDGRST_Msk

#define RCC_APB1RSTR_WWDGRST_Msk (0x1UL << RCC_APB1RSTR_WWDGRST_Pos)

0x00000800

◆ RCC_APB1RSTR_WWDGRST_Pos

#define RCC_APB1RSTR_WWDGRST_Pos (11U)

◆ RCC_APB2ENR_SPI1EN

#define RCC_APB2ENR_SPI1EN RCC_APB2ENR_SPI1EN_Msk

SPI1 clock enable

◆ RCC_APB2ENR_SPI1EN_Msk

#define RCC_APB2ENR_SPI1EN_Msk (0x1UL << RCC_APB2ENR_SPI1EN_Pos)

0x00001000

◆ RCC_APB2ENR_SPI1EN_Pos

#define RCC_APB2ENR_SPI1EN_Pos (12U)

◆ RCC_APB2ENR_SPI4EN

#define RCC_APB2ENR_SPI4EN RCC_APB2ENR_SPI4EN_Msk

SPI4 clock enable

◆ RCC_APB2ENR_SPI4EN_Msk

#define RCC_APB2ENR_SPI4EN_Msk (0x1UL << RCC_APB2ENR_SPI4EN_Pos)

0x00008000

◆ RCC_APB2ENR_SPI4EN_Pos

#define RCC_APB2ENR_SPI4EN_Pos (15U)

◆ RCC_APB2ENR_SYSCFGEN

#define RCC_APB2ENR_SYSCFGEN RCC_APB2ENR_SYSCFGEN_Msk

SYSCFG clock enable

◆ RCC_APB2ENR_SYSCFGEN_Msk

#define RCC_APB2ENR_SYSCFGEN_Msk (0x1UL << RCC_APB2ENR_SYSCFGEN_Pos)

0x00000001

◆ RCC_APB2ENR_SYSCFGEN_Pos

#define RCC_APB2ENR_SYSCFGEN_Pos (0U)

◆ RCC_APB2ENR_TIM15EN

#define RCC_APB2ENR_TIM15EN RCC_APB2ENR_TIM15EN_Msk

TIM15 clock enable

◆ RCC_APB2ENR_TIM15EN_Msk

#define RCC_APB2ENR_TIM15EN_Msk (0x1UL << RCC_APB2ENR_TIM15EN_Pos)

0x00010000

◆ RCC_APB2ENR_TIM15EN_Pos

#define RCC_APB2ENR_TIM15EN_Pos (16U)

◆ RCC_APB2ENR_TIM16EN

#define RCC_APB2ENR_TIM16EN RCC_APB2ENR_TIM16EN_Msk

TIM16 clock enable

◆ RCC_APB2ENR_TIM16EN_Msk

#define RCC_APB2ENR_TIM16EN_Msk (0x1UL << RCC_APB2ENR_TIM16EN_Pos)

0x00020000

◆ RCC_APB2ENR_TIM16EN_Pos

#define RCC_APB2ENR_TIM16EN_Pos (17U)

◆ RCC_APB2ENR_TIM17EN

#define RCC_APB2ENR_TIM17EN RCC_APB2ENR_TIM17EN_Msk

TIM17 clock enable

◆ RCC_APB2ENR_TIM17EN_Msk

#define RCC_APB2ENR_TIM17EN_Msk (0x1UL << RCC_APB2ENR_TIM17EN_Pos)

0x00040000

◆ RCC_APB2ENR_TIM17EN_Pos

#define RCC_APB2ENR_TIM17EN_Pos (18U)

◆ RCC_APB2ENR_TIM1EN

#define RCC_APB2ENR_TIM1EN RCC_APB2ENR_TIM1EN_Msk

TIM1 clock enable

◆ RCC_APB2ENR_TIM1EN_Msk

#define RCC_APB2ENR_TIM1EN_Msk (0x1UL << RCC_APB2ENR_TIM1EN_Pos)

0x00000800

◆ RCC_APB2ENR_TIM1EN_Pos

#define RCC_APB2ENR_TIM1EN_Pos (11U)

◆ RCC_APB2ENR_TIM20EN

#define RCC_APB2ENR_TIM20EN RCC_APB2ENR_TIM20EN_Msk

TIM20 clock enable

◆ RCC_APB2ENR_TIM20EN_Msk

#define RCC_APB2ENR_TIM20EN_Msk (0x1UL << RCC_APB2ENR_TIM20EN_Pos)

0x00100000

◆ RCC_APB2ENR_TIM20EN_Pos

#define RCC_APB2ENR_TIM20EN_Pos (20U)

◆ RCC_APB2ENR_TIM8EN

#define RCC_APB2ENR_TIM8EN RCC_APB2ENR_TIM8EN_Msk

TIM8 clock enable

◆ RCC_APB2ENR_TIM8EN_Msk

#define RCC_APB2ENR_TIM8EN_Msk (0x1UL << RCC_APB2ENR_TIM8EN_Pos)

0x00002000

◆ RCC_APB2ENR_TIM8EN_Pos

#define RCC_APB2ENR_TIM8EN_Pos (13U)

◆ RCC_APB2ENR_USART1EN

#define RCC_APB2ENR_USART1EN RCC_APB2ENR_USART1EN_Msk

USART1 clock enable

◆ RCC_APB2ENR_USART1EN_Msk

#define RCC_APB2ENR_USART1EN_Msk (0x1UL << RCC_APB2ENR_USART1EN_Pos)

0x00004000

◆ RCC_APB2ENR_USART1EN_Pos

#define RCC_APB2ENR_USART1EN_Pos (14U)

◆ RCC_APB2RSTR_SPI1RST

#define RCC_APB2RSTR_SPI1RST RCC_APB2RSTR_SPI1RST_Msk

SPI1 reset

◆ RCC_APB2RSTR_SPI1RST_Msk

#define RCC_APB2RSTR_SPI1RST_Msk (0x1UL << RCC_APB2RSTR_SPI1RST_Pos)

0x00001000

◆ RCC_APB2RSTR_SPI1RST_Pos

#define RCC_APB2RSTR_SPI1RST_Pos (12U)

◆ RCC_APB2RSTR_SPI4RST

#define RCC_APB2RSTR_SPI4RST RCC_APB2RSTR_SPI4RST_Msk

SPI4 reset

◆ RCC_APB2RSTR_SPI4RST_Msk

#define RCC_APB2RSTR_SPI4RST_Msk (0x1UL << RCC_APB2RSTR_SPI4RST_Pos)

0x00008000

◆ RCC_APB2RSTR_SPI4RST_Pos

#define RCC_APB2RSTR_SPI4RST_Pos (15U)

◆ RCC_APB2RSTR_SYSCFGRST

#define RCC_APB2RSTR_SYSCFGRST RCC_APB2RSTR_SYSCFGRST_Msk

SYSCFG reset

◆ RCC_APB2RSTR_SYSCFGRST_Msk

#define RCC_APB2RSTR_SYSCFGRST_Msk (0x1UL << RCC_APB2RSTR_SYSCFGRST_Pos)

0x00000001

◆ RCC_APB2RSTR_SYSCFGRST_Pos

#define RCC_APB2RSTR_SYSCFGRST_Pos (0U)

◆ RCC_APB2RSTR_TIM15RST

#define RCC_APB2RSTR_TIM15RST RCC_APB2RSTR_TIM15RST_Msk

TIM15 reset

◆ RCC_APB2RSTR_TIM15RST_Msk

#define RCC_APB2RSTR_TIM15RST_Msk (0x1UL << RCC_APB2RSTR_TIM15RST_Pos)

0x00010000

◆ RCC_APB2RSTR_TIM15RST_Pos

#define RCC_APB2RSTR_TIM15RST_Pos (16U)

◆ RCC_APB2RSTR_TIM16RST

#define RCC_APB2RSTR_TIM16RST RCC_APB2RSTR_TIM16RST_Msk

TIM16 reset

◆ RCC_APB2RSTR_TIM16RST_Msk

#define RCC_APB2RSTR_TIM16RST_Msk (0x1UL << RCC_APB2RSTR_TIM16RST_Pos)

0x00020000

◆ RCC_APB2RSTR_TIM16RST_Pos

#define RCC_APB2RSTR_TIM16RST_Pos (17U)

◆ RCC_APB2RSTR_TIM17RST

#define RCC_APB2RSTR_TIM17RST RCC_APB2RSTR_TIM17RST_Msk

TIM17 reset

◆ RCC_APB2RSTR_TIM17RST_Msk

#define RCC_APB2RSTR_TIM17RST_Msk (0x1UL << RCC_APB2RSTR_TIM17RST_Pos)

0x00040000

◆ RCC_APB2RSTR_TIM17RST_Pos

#define RCC_APB2RSTR_TIM17RST_Pos (18U)

◆ RCC_APB2RSTR_TIM1RST

#define RCC_APB2RSTR_TIM1RST RCC_APB2RSTR_TIM1RST_Msk

TIM1 reset

◆ RCC_APB2RSTR_TIM1RST_Msk

#define RCC_APB2RSTR_TIM1RST_Msk (0x1UL << RCC_APB2RSTR_TIM1RST_Pos)

0x00000800

◆ RCC_APB2RSTR_TIM1RST_Pos

#define RCC_APB2RSTR_TIM1RST_Pos (11U)

◆ RCC_APB2RSTR_TIM20RST

#define RCC_APB2RSTR_TIM20RST RCC_APB2RSTR_TIM20RST_Msk

TIM20 reset

◆ RCC_APB2RSTR_TIM20RST_Msk

#define RCC_APB2RSTR_TIM20RST_Msk (0x1UL << RCC_APB2RSTR_TIM20RST_Pos)

0x00100000

◆ RCC_APB2RSTR_TIM20RST_Pos

#define RCC_APB2RSTR_TIM20RST_Pos (20U)

◆ RCC_APB2RSTR_TIM8RST

#define RCC_APB2RSTR_TIM8RST RCC_APB2RSTR_TIM8RST_Msk

TIM8 reset

◆ RCC_APB2RSTR_TIM8RST_Msk

#define RCC_APB2RSTR_TIM8RST_Msk (0x1UL << RCC_APB2RSTR_TIM8RST_Pos)

0x00002000

◆ RCC_APB2RSTR_TIM8RST_Pos

#define RCC_APB2RSTR_TIM8RST_Pos (13U)

◆ RCC_APB2RSTR_USART1RST

#define RCC_APB2RSTR_USART1RST RCC_APB2RSTR_USART1RST_Msk

USART1 reset

◆ RCC_APB2RSTR_USART1RST_Msk

#define RCC_APB2RSTR_USART1RST_Msk (0x1UL << RCC_APB2RSTR_USART1RST_Pos)

0x00004000

◆ RCC_APB2RSTR_USART1RST_Pos

#define RCC_APB2RSTR_USART1RST_Pos (14U)

◆ RCC_BDCR_BDRST

#define RCC_BDCR_BDRST RCC_BDCR_BDRST_Msk

Backup domain software reset

◆ RCC_BDCR_BDRST_Msk

#define RCC_BDCR_BDRST_Msk (0x1UL << RCC_BDCR_BDRST_Pos)

0x00010000

◆ RCC_BDCR_BDRST_Pos

#define RCC_BDCR_BDRST_Pos (16U)

◆ RCC_BDCR_LSE

#define RCC_BDCR_LSE RCC_BDCR_LSE_Msk

External Low Speed oscillator [2:0] bits

◆ RCC_BDCR_LSE_Msk

#define RCC_BDCR_LSE_Msk (0x7UL << RCC_BDCR_LSE_Pos)

0x00000007

◆ RCC_BDCR_LSE_Pos

#define RCC_BDCR_LSE_Pos (0U)

◆ RCC_BDCR_LSEBYP

#define RCC_BDCR_LSEBYP RCC_BDCR_LSEBYP_Msk

External Low Speed oscillator Bypass

◆ RCC_BDCR_LSEBYP_Msk

#define RCC_BDCR_LSEBYP_Msk (0x1UL << RCC_BDCR_LSEBYP_Pos)

0x00000004

◆ RCC_BDCR_LSEBYP_Pos

#define RCC_BDCR_LSEBYP_Pos (2U)

◆ RCC_BDCR_LSEDRV

#define RCC_BDCR_LSEDRV RCC_BDCR_LSEDRV_Msk

LSEDRV[1:0] bits (LSE Osc. drive capability)

◆ RCC_BDCR_LSEDRV_0

#define RCC_BDCR_LSEDRV_0 (0x1UL << RCC_BDCR_LSEDRV_Pos)

0x00000008

◆ RCC_BDCR_LSEDRV_1

#define RCC_BDCR_LSEDRV_1 (0x2UL << RCC_BDCR_LSEDRV_Pos)

0x00000010

◆ RCC_BDCR_LSEDRV_Msk

#define RCC_BDCR_LSEDRV_Msk (0x3UL << RCC_BDCR_LSEDRV_Pos)

0x00000018

◆ RCC_BDCR_LSEDRV_Pos

#define RCC_BDCR_LSEDRV_Pos (3U)

◆ RCC_BDCR_LSEON

#define RCC_BDCR_LSEON RCC_BDCR_LSEON_Msk

External Low Speed oscillator enable

◆ RCC_BDCR_LSEON_Msk

#define RCC_BDCR_LSEON_Msk (0x1UL << RCC_BDCR_LSEON_Pos)

0x00000001

◆ RCC_BDCR_LSEON_Pos

#define RCC_BDCR_LSEON_Pos (0U)

◆ RCC_BDCR_LSERDY

#define RCC_BDCR_LSERDY RCC_BDCR_LSERDY_Msk

External Low Speed oscillator Ready

◆ RCC_BDCR_LSERDY_Msk

#define RCC_BDCR_LSERDY_Msk (0x1UL << RCC_BDCR_LSERDY_Pos)

0x00000002

◆ RCC_BDCR_LSERDY_Pos

#define RCC_BDCR_LSERDY_Pos (1U)

◆ RCC_BDCR_RTCEN

#define RCC_BDCR_RTCEN RCC_BDCR_RTCEN_Msk

RTC clock enable

◆ RCC_BDCR_RTCEN_Msk

#define RCC_BDCR_RTCEN_Msk (0x1UL << RCC_BDCR_RTCEN_Pos)

0x00008000

◆ RCC_BDCR_RTCEN_Pos

#define RCC_BDCR_RTCEN_Pos (15U)

◆ RCC_BDCR_RTCSEL

#define RCC_BDCR_RTCSEL RCC_BDCR_RTCSEL_Msk

RTCSEL[1:0] bits (RTC clock source selection)

◆ RCC_BDCR_RTCSEL_0

#define RCC_BDCR_RTCSEL_0 (0x1UL << RCC_BDCR_RTCSEL_Pos)

0x00000100

◆ RCC_BDCR_RTCSEL_1

#define RCC_BDCR_RTCSEL_1 (0x2UL << RCC_BDCR_RTCSEL_Pos)

0x00000200 RTC configuration

◆ RCC_BDCR_RTCSEL_HSE

#define RCC_BDCR_RTCSEL_HSE (0x00000300U)

HSE oscillator clock divided by 32 used as RTC clock

◆ RCC_BDCR_RTCSEL_LSE

#define RCC_BDCR_RTCSEL_LSE (0x00000100U)

LSE oscillator clock used as RTC clock

◆ RCC_BDCR_RTCSEL_LSI

#define RCC_BDCR_RTCSEL_LSI (0x00000200U)

LSI oscillator clock used as RTC clock

◆ RCC_BDCR_RTCSEL_Msk

#define RCC_BDCR_RTCSEL_Msk (0x3UL << RCC_BDCR_RTCSEL_Pos)

0x00000300

◆ RCC_BDCR_RTCSEL_NOCLOCK

#define RCC_BDCR_RTCSEL_NOCLOCK (0x00000000U)

No clock

◆ RCC_BDCR_RTCSEL_Pos

#define RCC_BDCR_RTCSEL_Pos (8U)

◆ RCC_CFGR2_ADCPRE12

#define RCC_CFGR2_ADCPRE12 RCC_CFGR2_ADCPRE12_Msk

ADCPRE12[8:4] bits

◆ RCC_CFGR2_ADCPRE12_0

#define RCC_CFGR2_ADCPRE12_0 (0x01UL << RCC_CFGR2_ADCPRE12_Pos)

0x00000010

◆ RCC_CFGR2_ADCPRE12_1

#define RCC_CFGR2_ADCPRE12_1 (0x02UL << RCC_CFGR2_ADCPRE12_Pos)

0x00000020

◆ RCC_CFGR2_ADCPRE12_2

#define RCC_CFGR2_ADCPRE12_2 (0x04UL << RCC_CFGR2_ADCPRE12_Pos)

0x00000040

◆ RCC_CFGR2_ADCPRE12_3

#define RCC_CFGR2_ADCPRE12_3 (0x08UL << RCC_CFGR2_ADCPRE12_Pos)

0x00000080

◆ RCC_CFGR2_ADCPRE12_4

#define RCC_CFGR2_ADCPRE12_4 (0x10UL << RCC_CFGR2_ADCPRE12_Pos)

0x00000100

◆ RCC_CFGR2_ADCPRE12_DIV1

#define RCC_CFGR2_ADCPRE12_DIV1 (0x00000100U)

ADC12 PLL clock divided by 1

◆ RCC_CFGR2_ADCPRE12_DIV10

#define RCC_CFGR2_ADCPRE12_DIV10 (0x00000150U)

ADC12 PLL clock divided by 10

◆ RCC_CFGR2_ADCPRE12_DIV12

#define RCC_CFGR2_ADCPRE12_DIV12 (0x00000160U)

ADC12 PLL clock divided by 12

◆ RCC_CFGR2_ADCPRE12_DIV128

#define RCC_CFGR2_ADCPRE12_DIV128 (0x000001A0U)

ADC12 PLL clock divided by 128

◆ RCC_CFGR2_ADCPRE12_DIV16

#define RCC_CFGR2_ADCPRE12_DIV16 (0x00000170U)

ADC12 PLL clock divided by 16

◆ RCC_CFGR2_ADCPRE12_DIV2

#define RCC_CFGR2_ADCPRE12_DIV2 (0x00000110U)

ADC12 PLL clock divided by 2

◆ RCC_CFGR2_ADCPRE12_DIV256

#define RCC_CFGR2_ADCPRE12_DIV256 (0x000001B0U)

ADC12 PLL clock divided by 256 ADCPRE34 configuration

◆ RCC_CFGR2_ADCPRE12_DIV32

#define RCC_CFGR2_ADCPRE12_DIV32 (0x00000180U)

ADC12 PLL clock divided by 32

◆ RCC_CFGR2_ADCPRE12_DIV4

#define RCC_CFGR2_ADCPRE12_DIV4 (0x00000120U)

ADC12 PLL clock divided by 4

◆ RCC_CFGR2_ADCPRE12_DIV6

#define RCC_CFGR2_ADCPRE12_DIV6 (0x00000130U)

ADC12 PLL clock divided by 6

◆ RCC_CFGR2_ADCPRE12_DIV64

#define RCC_CFGR2_ADCPRE12_DIV64 (0x00000190U)

ADC12 PLL clock divided by 64

◆ RCC_CFGR2_ADCPRE12_DIV8

#define RCC_CFGR2_ADCPRE12_DIV8 (0x00000140U)

ADC12 PLL clock divided by 8

◆ RCC_CFGR2_ADCPRE12_Msk

#define RCC_CFGR2_ADCPRE12_Msk (0x1FUL << RCC_CFGR2_ADCPRE12_Pos)

0x000001F0

◆ RCC_CFGR2_ADCPRE12_NO

#define RCC_CFGR2_ADCPRE12_NO (0x00000000U)

ADC12 clock disabled, ADC12 can use AHB clock

◆ RCC_CFGR2_ADCPRE12_Pos

#define RCC_CFGR2_ADCPRE12_Pos (4U)

◆ RCC_CFGR2_ADCPRE34

#define RCC_CFGR2_ADCPRE34 RCC_CFGR2_ADCPRE34_Msk

ADCPRE34[13:5] bits

◆ RCC_CFGR2_ADCPRE34_0

#define RCC_CFGR2_ADCPRE34_0 (0x01UL << RCC_CFGR2_ADCPRE34_Pos)

0x00000200

◆ RCC_CFGR2_ADCPRE34_1

#define RCC_CFGR2_ADCPRE34_1 (0x02UL << RCC_CFGR2_ADCPRE34_Pos)

0x00000400

◆ RCC_CFGR2_ADCPRE34_2

#define RCC_CFGR2_ADCPRE34_2 (0x04UL << RCC_CFGR2_ADCPRE34_Pos)

0x00000800

◆ RCC_CFGR2_ADCPRE34_3

#define RCC_CFGR2_ADCPRE34_3 (0x08UL << RCC_CFGR2_ADCPRE34_Pos)

0x00001000

◆ RCC_CFGR2_ADCPRE34_4

#define RCC_CFGR2_ADCPRE34_4 (0x10UL << RCC_CFGR2_ADCPRE34_Pos)

0x00002000

◆ RCC_CFGR2_ADCPRE34_DIV1

#define RCC_CFGR2_ADCPRE34_DIV1 (0x00002000U)

ADC34 PLL clock divided by 1

◆ RCC_CFGR2_ADCPRE34_DIV10

#define RCC_CFGR2_ADCPRE34_DIV10 (0x00002A00U)

ADC34 PLL clock divided by 10

◆ RCC_CFGR2_ADCPRE34_DIV12

#define RCC_CFGR2_ADCPRE34_DIV12 (0x00002C00U)

ADC34 PLL clock divided by 12

◆ RCC_CFGR2_ADCPRE34_DIV128

#define RCC_CFGR2_ADCPRE34_DIV128 (0x00003400U)

ADC34 PLL clock divided by 128

◆ RCC_CFGR2_ADCPRE34_DIV16

#define RCC_CFGR2_ADCPRE34_DIV16 (0x00002E00U)

ADC34 PLL clock divided by 16

◆ RCC_CFGR2_ADCPRE34_DIV2

#define RCC_CFGR2_ADCPRE34_DIV2 (0x00002200U)

ADC34 PLL clock divided by 2

◆ RCC_CFGR2_ADCPRE34_DIV256

#define RCC_CFGR2_ADCPRE34_DIV256 (0x00003600U)

ADC34 PLL clock divided by 256

◆ RCC_CFGR2_ADCPRE34_DIV32

#define RCC_CFGR2_ADCPRE34_DIV32 (0x00003000U)

ADC34 PLL clock divided by 32

◆ RCC_CFGR2_ADCPRE34_DIV4

#define RCC_CFGR2_ADCPRE34_DIV4 (0x00002400U)

ADC34 PLL clock divided by 4

◆ RCC_CFGR2_ADCPRE34_DIV6

#define RCC_CFGR2_ADCPRE34_DIV6 (0x00002600U)

ADC34 PLL clock divided by 6

◆ RCC_CFGR2_ADCPRE34_DIV64

#define RCC_CFGR2_ADCPRE34_DIV64 (0x00003200U)

ADC34 PLL clock divided by 64

◆ RCC_CFGR2_ADCPRE34_DIV8

#define RCC_CFGR2_ADCPRE34_DIV8 (0x00002800U)

ADC34 PLL clock divided by 8

◆ RCC_CFGR2_ADCPRE34_Msk

#define RCC_CFGR2_ADCPRE34_Msk (0x1FUL << RCC_CFGR2_ADCPRE34_Pos)

0x00003E00

◆ RCC_CFGR2_ADCPRE34_NO

#define RCC_CFGR2_ADCPRE34_NO (0x00000000U)

ADC34 clock disabled, ADC34 can use AHB clock

◆ RCC_CFGR2_ADCPRE34_Pos

#define RCC_CFGR2_ADCPRE34_Pos (9U)

◆ RCC_CFGR2_PREDIV

#define RCC_CFGR2_PREDIV RCC_CFGR2_PREDIV_Msk

PREDIV[3:0] bits

◆ RCC_CFGR2_PREDIV_0

#define RCC_CFGR2_PREDIV_0 (0x1UL << RCC_CFGR2_PREDIV_Pos)

0x00000001

◆ RCC_CFGR2_PREDIV_1

#define RCC_CFGR2_PREDIV_1 (0x2UL << RCC_CFGR2_PREDIV_Pos)

0x00000002

◆ RCC_CFGR2_PREDIV_2

#define RCC_CFGR2_PREDIV_2 (0x4UL << RCC_CFGR2_PREDIV_Pos)

0x00000004

◆ RCC_CFGR2_PREDIV_3

#define RCC_CFGR2_PREDIV_3 (0x8UL << RCC_CFGR2_PREDIV_Pos)

0x00000008

◆ RCC_CFGR2_PREDIV_DIV1

#define RCC_CFGR2_PREDIV_DIV1 (0x00000000U)

PREDIV input clock not divided

◆ RCC_CFGR2_PREDIV_DIV10

#define RCC_CFGR2_PREDIV_DIV10 (0x00000009U)

PREDIV input clock divided by 10

◆ RCC_CFGR2_PREDIV_DIV11

#define RCC_CFGR2_PREDIV_DIV11 (0x0000000AU)

PREDIV input clock divided by 11

◆ RCC_CFGR2_PREDIV_DIV12

#define RCC_CFGR2_PREDIV_DIV12 (0x0000000BU)

PREDIV input clock divided by 12

◆ RCC_CFGR2_PREDIV_DIV13

#define RCC_CFGR2_PREDIV_DIV13 (0x0000000CU)

PREDIV input clock divided by 13

◆ RCC_CFGR2_PREDIV_DIV14

#define RCC_CFGR2_PREDIV_DIV14 (0x0000000DU)

PREDIV input clock divided by 14

◆ RCC_CFGR2_PREDIV_DIV15

#define RCC_CFGR2_PREDIV_DIV15 (0x0000000EU)

PREDIV input clock divided by 15

◆ RCC_CFGR2_PREDIV_DIV16

#define RCC_CFGR2_PREDIV_DIV16 (0x0000000FU)

PREDIV input clock divided by 16 ADCPRE12 configuration

◆ RCC_CFGR2_PREDIV_DIV2

#define RCC_CFGR2_PREDIV_DIV2 (0x00000001U)

PREDIV input clock divided by 2

◆ RCC_CFGR2_PREDIV_DIV3

#define RCC_CFGR2_PREDIV_DIV3 (0x00000002U)

PREDIV input clock divided by 3

◆ RCC_CFGR2_PREDIV_DIV4

#define RCC_CFGR2_PREDIV_DIV4 (0x00000003U)

PREDIV input clock divided by 4

◆ RCC_CFGR2_PREDIV_DIV5

#define RCC_CFGR2_PREDIV_DIV5 (0x00000004U)

PREDIV input clock divided by 5

◆ RCC_CFGR2_PREDIV_DIV6

#define RCC_CFGR2_PREDIV_DIV6 (0x00000005U)

PREDIV input clock divided by 6

◆ RCC_CFGR2_PREDIV_DIV7

#define RCC_CFGR2_PREDIV_DIV7 (0x00000006U)

PREDIV input clock divided by 7

◆ RCC_CFGR2_PREDIV_DIV8

#define RCC_CFGR2_PREDIV_DIV8 (0x00000007U)

PREDIV input clock divided by 8

◆ RCC_CFGR2_PREDIV_DIV9

#define RCC_CFGR2_PREDIV_DIV9 (0x00000008U)

PREDIV input clock divided by 9

◆ RCC_CFGR2_PREDIV_Msk

#define RCC_CFGR2_PREDIV_Msk (0xFUL << RCC_CFGR2_PREDIV_Pos)

0x0000000F

◆ RCC_CFGR2_PREDIV_Pos

#define RCC_CFGR2_PREDIV_Pos (0U)

< PREDIV configuration

◆ RCC_CFGR3_I2C1SW

#define RCC_CFGR3_I2C1SW RCC_CFGR3_I2C1SW_Msk

I2C1SW bits

◆ RCC_CFGR3_I2C1SW_HSI

#define RCC_CFGR3_I2C1SW_HSI (0x00000000U)

HSI oscillator clock used as I2C1 clock source

◆ RCC_CFGR3_I2C1SW_Msk

#define RCC_CFGR3_I2C1SW_Msk (0x1UL << RCC_CFGR3_I2C1SW_Pos)

0x00000010

◆ RCC_CFGR3_I2C1SW_Pos

#define RCC_CFGR3_I2C1SW_Pos (4U)

◆ RCC_CFGR3_I2C1SW_SYSCLK

#define RCC_CFGR3_I2C1SW_SYSCLK RCC_CFGR3_I2C1SW_SYSCLK_Msk

System clock selected as I2C1 clock source

◆ RCC_CFGR3_I2C1SW_SYSCLK_Msk

#define RCC_CFGR3_I2C1SW_SYSCLK_Msk (0x1UL << RCC_CFGR3_I2C1SW_SYSCLK_Pos)

0x00000010

◆ RCC_CFGR3_I2C1SW_SYSCLK_Pos

#define RCC_CFGR3_I2C1SW_SYSCLK_Pos (4U)

◆ RCC_CFGR3_I2C2SW

#define RCC_CFGR3_I2C2SW RCC_CFGR3_I2C2SW_Msk

I2C2SW bits

◆ RCC_CFGR3_I2C2SW_HSI

#define RCC_CFGR3_I2C2SW_HSI (0x00000000U)

HSI oscillator clock used as I2C2 clock source

◆ RCC_CFGR3_I2C2SW_Msk

#define RCC_CFGR3_I2C2SW_Msk (0x1UL << RCC_CFGR3_I2C2SW_Pos)

0x00000020

◆ RCC_CFGR3_I2C2SW_Pos

#define RCC_CFGR3_I2C2SW_Pos (5U)

◆ RCC_CFGR3_I2C2SW_SYSCLK

#define RCC_CFGR3_I2C2SW_SYSCLK RCC_CFGR3_I2C2SW_SYSCLK_Msk

System clock selected as I2C2 clock source

◆ RCC_CFGR3_I2C2SW_SYSCLK_Msk

#define RCC_CFGR3_I2C2SW_SYSCLK_Msk (0x1UL << RCC_CFGR3_I2C2SW_SYSCLK_Pos)

0x00000020

◆ RCC_CFGR3_I2C2SW_SYSCLK_Pos

#define RCC_CFGR3_I2C2SW_SYSCLK_Pos (5U)

◆ RCC_CFGR3_I2C3SW

#define RCC_CFGR3_I2C3SW RCC_CFGR3_I2C3SW_Msk

I2C3SW bits

◆ RCC_CFGR3_I2C3SW_HSI

#define RCC_CFGR3_I2C3SW_HSI (0x00000000U)

HSI oscillator clock used as I2C3 clock source

◆ RCC_CFGR3_I2C3SW_Msk

#define RCC_CFGR3_I2C3SW_Msk (0x1UL << RCC_CFGR3_I2C3SW_Pos)

0x00000040

◆ RCC_CFGR3_I2C3SW_Pos

#define RCC_CFGR3_I2C3SW_Pos (6U)

◆ RCC_CFGR3_I2C3SW_SYSCLK

#define RCC_CFGR3_I2C3SW_SYSCLK RCC_CFGR3_I2C3SW_SYSCLK_Msk

System clock selected as I2C3 clock source

◆ RCC_CFGR3_I2C3SW_SYSCLK_Msk

#define RCC_CFGR3_I2C3SW_SYSCLK_Msk (0x1UL << RCC_CFGR3_I2C3SW_SYSCLK_Pos)

0x00000040

◆ RCC_CFGR3_I2C3SW_SYSCLK_Pos

#define RCC_CFGR3_I2C3SW_SYSCLK_Pos (6U)

◆ RCC_CFGR3_I2CSW

#define RCC_CFGR3_I2CSW RCC_CFGR3_I2CSW_Msk

I2CSW bits

◆ RCC_CFGR3_I2CSW_Msk

#define RCC_CFGR3_I2CSW_Msk (0x7UL << RCC_CFGR3_I2CSW_Pos)

0x00000070

◆ RCC_CFGR3_I2CSW_Pos

#define RCC_CFGR3_I2CSW_Pos (4U)

◆ RCC_CFGR3_TIM15SW

#define RCC_CFGR3_TIM15SW RCC_CFGR3_TIM15SW_Msk

TIM15SW bits

◆ RCC_CFGR3_TIM15SW_HCLK

#define RCC_CFGR3_TIM15SW_HCLK RCC_CFGR3_TIM15SW_PCLK2

◆ RCC_CFGR3_TIM15SW_Msk

#define RCC_CFGR3_TIM15SW_Msk (0x1UL << RCC_CFGR3_TIM15SW_Pos)

0x00000400

◆ RCC_CFGR3_TIM15SW_PCLK2

#define RCC_CFGR3_TIM15SW_PCLK2 (0x00000000U)

PCLK2 used as TIM15 clock source

◆ RCC_CFGR3_TIM15SW_PLL

#define RCC_CFGR3_TIM15SW_PLL RCC_CFGR3_TIM15SW_PLL_Msk

PLL clock used as TIM15 clock source

◆ RCC_CFGR3_TIM15SW_PLL_Msk

#define RCC_CFGR3_TIM15SW_PLL_Msk (0x1UL << RCC_CFGR3_TIM15SW_PLL_Pos)

0x00000400

◆ RCC_CFGR3_TIM15SW_PLL_Pos

#define RCC_CFGR3_TIM15SW_PLL_Pos (10U)

◆ RCC_CFGR3_TIM15SW_Pos

#define RCC_CFGR3_TIM15SW_Pos (10U)

◆ RCC_CFGR3_TIM16SW

#define RCC_CFGR3_TIM16SW RCC_CFGR3_TIM16SW_Msk

TIM16SW bits

◆ RCC_CFGR3_TIM16SW_HCLK

#define RCC_CFGR3_TIM16SW_HCLK RCC_CFGR3_TIM16SW_PCLK2

◆ RCC_CFGR3_TIM16SW_Msk

#define RCC_CFGR3_TIM16SW_Msk (0x1UL << RCC_CFGR3_TIM16SW_Pos)

0x00000800

◆ RCC_CFGR3_TIM16SW_PCLK2

#define RCC_CFGR3_TIM16SW_PCLK2 (0x00000000U)

PCLK2 used as TIM16 clock source

◆ RCC_CFGR3_TIM16SW_PLL

#define RCC_CFGR3_TIM16SW_PLL RCC_CFGR3_TIM16SW_PLL_Msk

PLL clock used as TIM16 clock source

◆ RCC_CFGR3_TIM16SW_PLL_Msk

#define RCC_CFGR3_TIM16SW_PLL_Msk (0x1UL << RCC_CFGR3_TIM16SW_PLL_Pos)

0x00000800

◆ RCC_CFGR3_TIM16SW_PLL_Pos

#define RCC_CFGR3_TIM16SW_PLL_Pos (11U)

◆ RCC_CFGR3_TIM16SW_Pos

#define RCC_CFGR3_TIM16SW_Pos (11U)

◆ RCC_CFGR3_TIM17SW

#define RCC_CFGR3_TIM17SW RCC_CFGR3_TIM17SW_Msk

TIM17SW bits

◆ RCC_CFGR3_TIM17SW_HCLK

#define RCC_CFGR3_TIM17SW_HCLK RCC_CFGR3_TIM17SW_PCLK2

◆ RCC_CFGR3_TIM17SW_Msk

#define RCC_CFGR3_TIM17SW_Msk (0x1UL << RCC_CFGR3_TIM17SW_Pos)

0x00002000

◆ RCC_CFGR3_TIM17SW_PCLK2

#define RCC_CFGR3_TIM17SW_PCLK2 (0x00000000U)

PCLK2 used as TIM17 clock source

◆ RCC_CFGR3_TIM17SW_PLL

#define RCC_CFGR3_TIM17SW_PLL RCC_CFGR3_TIM17SW_PLL_Msk

PLL clock used as TIM17 clock source

◆ RCC_CFGR3_TIM17SW_PLL_Msk

#define RCC_CFGR3_TIM17SW_PLL_Msk (0x1UL << RCC_CFGR3_TIM17SW_PLL_Pos)

0x00002000

◆ RCC_CFGR3_TIM17SW_PLL_Pos

#define RCC_CFGR3_TIM17SW_PLL_Pos (13U)

◆ RCC_CFGR3_TIM17SW_Pos

#define RCC_CFGR3_TIM17SW_Pos (13U)

◆ RCC_CFGR3_TIM1SW

#define RCC_CFGR3_TIM1SW RCC_CFGR3_TIM1SW_Msk

TIM1SW bits

◆ RCC_CFGR3_TIM1SW_HCLK

#define RCC_CFGR3_TIM1SW_HCLK RCC_CFGR3_TIM1SW_PCLK2

◆ RCC_CFGR3_TIM1SW_Msk

#define RCC_CFGR3_TIM1SW_Msk (0x1UL << RCC_CFGR3_TIM1SW_Pos)

0x00000100

◆ RCC_CFGR3_TIM1SW_PCLK2

#define RCC_CFGR3_TIM1SW_PCLK2 (0x00000000U)

PCLK2 used as TIM1 clock source

◆ RCC_CFGR3_TIM1SW_PLL

#define RCC_CFGR3_TIM1SW_PLL RCC_CFGR3_TIM1SW_PLL_Msk

PLL clock used as TIM1 clock source

◆ RCC_CFGR3_TIM1SW_PLL_Msk

#define RCC_CFGR3_TIM1SW_PLL_Msk (0x1UL << RCC_CFGR3_TIM1SW_PLL_Pos)

0x00000100

◆ RCC_CFGR3_TIM1SW_PLL_Pos

#define RCC_CFGR3_TIM1SW_PLL_Pos (8U)

◆ RCC_CFGR3_TIM1SW_Pos

#define RCC_CFGR3_TIM1SW_Pos (8U)

◆ RCC_CFGR3_TIM20SW

#define RCC_CFGR3_TIM20SW RCC_CFGR3_TIM20SW_Msk

TIM20SW bits

◆ RCC_CFGR3_TIM20SW_HCLK

#define RCC_CFGR3_TIM20SW_HCLK RCC_CFGR3_TIM20SW_PCLK2

◆ RCC_CFGR3_TIM20SW_Msk

#define RCC_CFGR3_TIM20SW_Msk (0x1UL << RCC_CFGR3_TIM20SW_Pos)

0x00008000

◆ RCC_CFGR3_TIM20SW_PCLK2

#define RCC_CFGR3_TIM20SW_PCLK2 (0x00000000U)

PCLK2 used as TIM20 clock source

◆ RCC_CFGR3_TIM20SW_PLL

#define RCC_CFGR3_TIM20SW_PLL RCC_CFGR3_TIM20SW_PLL_Msk

PLL clock used as TIM20 clock source

◆ RCC_CFGR3_TIM20SW_PLL_Msk

#define RCC_CFGR3_TIM20SW_PLL_Msk (0x1UL << RCC_CFGR3_TIM20SW_PLL_Pos)

0x00008000

◆ RCC_CFGR3_TIM20SW_PLL_Pos

#define RCC_CFGR3_TIM20SW_PLL_Pos (15U)

◆ RCC_CFGR3_TIM20SW_Pos

#define RCC_CFGR3_TIM20SW_Pos (15U)

◆ RCC_CFGR3_TIM2SW

#define RCC_CFGR3_TIM2SW RCC_CFGR3_TIM2SW_Msk

TIM2SW bits

◆ RCC_CFGR3_TIM2SW_HCLK

#define RCC_CFGR3_TIM2SW_HCLK RCC_CFGR3_TIM2SW_PCLK1

◆ RCC_CFGR3_TIM2SW_Msk

#define RCC_CFGR3_TIM2SW_Msk (0x1UL << RCC_CFGR3_TIM2SW_Pos)

0x01000000

◆ RCC_CFGR3_TIM2SW_PCLK1

#define RCC_CFGR3_TIM2SW_PCLK1 (0x00000000U)

PCLK1 used as TIM2 clock source

◆ RCC_CFGR3_TIM2SW_PLL

#define RCC_CFGR3_TIM2SW_PLL RCC_CFGR3_TIM2SW_PLL_Msk

PLL clock used as TIM2 clock source

◆ RCC_CFGR3_TIM2SW_PLL_Msk

#define RCC_CFGR3_TIM2SW_PLL_Msk (0x1UL << RCC_CFGR3_TIM2SW_PLL_Pos)

0x01000000

◆ RCC_CFGR3_TIM2SW_PLL_Pos

#define RCC_CFGR3_TIM2SW_PLL_Pos (24U)

◆ RCC_CFGR3_TIM2SW_Pos

#define RCC_CFGR3_TIM2SW_Pos (24U)

◆ RCC_CFGR3_TIM34SW

#define RCC_CFGR3_TIM34SW RCC_CFGR3_TIM34SW_Msk

TIM34SW bits

◆ RCC_CFGR3_TIM34SW_HCLK

#define RCC_CFGR3_TIM34SW_HCLK RCC_CFGR3_TIM34SW_PCLK1

◆ RCC_CFGR3_TIM34SW_Msk

#define RCC_CFGR3_TIM34SW_Msk (0x1UL << RCC_CFGR3_TIM34SW_Pos)

0x02000000

◆ RCC_CFGR3_TIM34SW_PCLK1

#define RCC_CFGR3_TIM34SW_PCLK1 (0x00000000U)

PCLK1 used as TIM3/TIM4 clock source

◆ RCC_CFGR3_TIM34SW_PLL

#define RCC_CFGR3_TIM34SW_PLL RCC_CFGR3_TIM34SW_PLL_Msk

PLL clock used as TIM3/TIM4 clock source

◆ RCC_CFGR3_TIM34SW_PLL_Msk

#define RCC_CFGR3_TIM34SW_PLL_Msk (0x1UL << RCC_CFGR3_TIM34SW_PLL_Pos)

0x02000000

◆ RCC_CFGR3_TIM34SW_PLL_Pos

#define RCC_CFGR3_TIM34SW_PLL_Pos (25U)

◆ RCC_CFGR3_TIM34SW_Pos

#define RCC_CFGR3_TIM34SW_Pos (25U)

◆ RCC_CFGR3_TIM8SW

#define RCC_CFGR3_TIM8SW RCC_CFGR3_TIM8SW_Msk

TIM8SW bits

◆ RCC_CFGR3_TIM8SW_HCLK

#define RCC_CFGR3_TIM8SW_HCLK RCC_CFGR3_TIM8SW_PCLK2

◆ RCC_CFGR3_TIM8SW_Msk

#define RCC_CFGR3_TIM8SW_Msk (0x1UL << RCC_CFGR3_TIM8SW_Pos)

0x00000200

◆ RCC_CFGR3_TIM8SW_PCLK2

#define RCC_CFGR3_TIM8SW_PCLK2 (0x00000000U)

PCLK2 used as TIM8 clock source

◆ RCC_CFGR3_TIM8SW_PLL

#define RCC_CFGR3_TIM8SW_PLL RCC_CFGR3_TIM8SW_PLL_Msk

PLL clock used as TIM8 clock source

◆ RCC_CFGR3_TIM8SW_PLL_Msk

#define RCC_CFGR3_TIM8SW_PLL_Msk (0x1UL << RCC_CFGR3_TIM8SW_PLL_Pos)

0x00000200

◆ RCC_CFGR3_TIM8SW_PLL_Pos

#define RCC_CFGR3_TIM8SW_PLL_Pos (9U)

◆ RCC_CFGR3_TIM8SW_Pos

#define RCC_CFGR3_TIM8SW_Pos (9U)

◆ RCC_CFGR3_TIMSW

#define RCC_CFGR3_TIMSW RCC_CFGR3_TIMSW_Msk

TIMSW bits

◆ RCC_CFGR3_TIMSW_Msk

#define RCC_CFGR3_TIMSW_Msk (0xAFUL << RCC_CFGR3_TIMSW_Pos)

0x0000AF00

◆ RCC_CFGR3_TIMSW_Pos

#define RCC_CFGR3_TIMSW_Pos (8U)

◆ RCC_CFGR3_UART4SW

#define RCC_CFGR3_UART4SW RCC_CFGR3_UART4SW_Msk

UART4SW[1:0] bits

◆ RCC_CFGR3_UART4SW_0

#define RCC_CFGR3_UART4SW_0 (0x1UL << RCC_CFGR3_UART4SW_Pos)

0x00100000

◆ RCC_CFGR3_UART4SW_1

#define RCC_CFGR3_UART4SW_1 (0x2UL << RCC_CFGR3_UART4SW_Pos)

0x00200000

◆ RCC_CFGR3_UART4SW_HSI

#define RCC_CFGR3_UART4SW_HSI (0x00300000U)

HSI oscillator clock used as UART4 clock source

◆ RCC_CFGR3_UART4SW_LSE

#define RCC_CFGR3_UART4SW_LSE (0x00200000U)

LSE oscillator clock used as UART4 clock source

◆ RCC_CFGR3_UART4SW_Msk

#define RCC_CFGR3_UART4SW_Msk (0x3UL << RCC_CFGR3_UART4SW_Pos)

0x00300000

◆ RCC_CFGR3_UART4SW_PCLK

#define RCC_CFGR3_UART4SW_PCLK (0x00000000U)

PCLK1 clock used as UART4 clock source

◆ RCC_CFGR3_UART4SW_Pos

#define RCC_CFGR3_UART4SW_Pos (20U)

◆ RCC_CFGR3_UART4SW_SYSCLK

#define RCC_CFGR3_UART4SW_SYSCLK (0x00100000U)

System clock selected as UART4 clock source

◆ RCC_CFGR3_UART5SW

#define RCC_CFGR3_UART5SW RCC_CFGR3_UART5SW_Msk

UART5SW[1:0] bits

◆ RCC_CFGR3_UART5SW_0

#define RCC_CFGR3_UART5SW_0 (0x1UL << RCC_CFGR3_UART5SW_Pos)

0x00400000

◆ RCC_CFGR3_UART5SW_1

#define RCC_CFGR3_UART5SW_1 (0x2UL << RCC_CFGR3_UART5SW_Pos)

0x00800000

◆ RCC_CFGR3_UART5SW_HSI

#define RCC_CFGR3_UART5SW_HSI (0x00C00000U)

HSI oscillator clock used as UART5 clock source

◆ RCC_CFGR3_UART5SW_LSE

#define RCC_CFGR3_UART5SW_LSE (0x00800000U)

LSE oscillator clock used as UART5 clock source

◆ RCC_CFGR3_UART5SW_Msk

#define RCC_CFGR3_UART5SW_Msk (0x3UL << RCC_CFGR3_UART5SW_Pos)

0x00C00000

◆ RCC_CFGR3_UART5SW_PCLK

#define RCC_CFGR3_UART5SW_PCLK (0x00000000U)

PCLK1 clock used as UART5 clock source

◆ RCC_CFGR3_UART5SW_Pos

#define RCC_CFGR3_UART5SW_Pos (22U)

◆ RCC_CFGR3_UART5SW_SYSCLK

#define RCC_CFGR3_UART5SW_SYSCLK (0x00400000U)

System clock selected as UART5 clock source

◆ RCC_CFGR3_USART1SW

#define RCC_CFGR3_USART1SW RCC_CFGR3_USART1SW_Msk

USART1SW[1:0] bits

◆ RCC_CFGR3_USART1SW_0

#define RCC_CFGR3_USART1SW_0 (0x1UL << RCC_CFGR3_USART1SW_Pos)

0x00000001

◆ RCC_CFGR3_USART1SW_1

#define RCC_CFGR3_USART1SW_1 (0x2UL << RCC_CFGR3_USART1SW_Pos)

0x00000002

◆ RCC_CFGR3_USART1SW_HSI

#define RCC_CFGR3_USART1SW_HSI (0x00000003U)

HSI oscillator clock used as USART1 clock source

◆ RCC_CFGR3_USART1SW_LSE

#define RCC_CFGR3_USART1SW_LSE (0x00000002U)

LSE oscillator clock used as USART1 clock source

◆ RCC_CFGR3_USART1SW_Msk

#define RCC_CFGR3_USART1SW_Msk (0x3UL << RCC_CFGR3_USART1SW_Pos)

0x00000003

◆ RCC_CFGR3_USART1SW_PCLK

#define RCC_CFGR3_USART1SW_PCLK RCC_CFGR3_USART1SW_PCLK2

◆ RCC_CFGR3_USART1SW_PCLK2

#define RCC_CFGR3_USART1SW_PCLK2 (0x00000000U)

PCLK2 clock used as USART1 clock source

◆ RCC_CFGR3_USART1SW_Pos

#define RCC_CFGR3_USART1SW_Pos (0U)

◆ RCC_CFGR3_USART1SW_SYSCLK

#define RCC_CFGR3_USART1SW_SYSCLK (0x00000001U)

System clock selected as USART1 clock source

◆ RCC_CFGR3_USART2SW

#define RCC_CFGR3_USART2SW RCC_CFGR3_USART2SW_Msk

USART2SW[1:0] bits

◆ RCC_CFGR3_USART2SW_0

#define RCC_CFGR3_USART2SW_0 (0x1UL << RCC_CFGR3_USART2SW_Pos)

0x00010000

◆ RCC_CFGR3_USART2SW_1

#define RCC_CFGR3_USART2SW_1 (0x2UL << RCC_CFGR3_USART2SW_Pos)

0x00020000

◆ RCC_CFGR3_USART2SW_HSI

#define RCC_CFGR3_USART2SW_HSI (0x00030000U)

HSI oscillator clock used as USART2 clock source

◆ RCC_CFGR3_USART2SW_LSE

#define RCC_CFGR3_USART2SW_LSE (0x00020000U)

LSE oscillator clock used as USART2 clock source

◆ RCC_CFGR3_USART2SW_Msk

#define RCC_CFGR3_USART2SW_Msk (0x3UL << RCC_CFGR3_USART2SW_Pos)

0x00030000

◆ RCC_CFGR3_USART2SW_PCLK

#define RCC_CFGR3_USART2SW_PCLK (0x00000000U)

PCLK1 clock used as USART2 clock source

◆ RCC_CFGR3_USART2SW_Pos

#define RCC_CFGR3_USART2SW_Pos (16U)

◆ RCC_CFGR3_USART2SW_SYSCLK

#define RCC_CFGR3_USART2SW_SYSCLK (0x00010000U)

System clock selected as USART2 clock source

◆ RCC_CFGR3_USART3SW

#define RCC_CFGR3_USART3SW RCC_CFGR3_USART3SW_Msk

USART3SW[1:0] bits

◆ RCC_CFGR3_USART3SW_0

#define RCC_CFGR3_USART3SW_0 (0x1UL << RCC_CFGR3_USART3SW_Pos)

0x00040000

◆ RCC_CFGR3_USART3SW_1

#define RCC_CFGR3_USART3SW_1 (0x2UL << RCC_CFGR3_USART3SW_Pos)

0x00080000

◆ RCC_CFGR3_USART3SW_HSI

#define RCC_CFGR3_USART3SW_HSI (0x000C0000U)

HSI oscillator clock used as USART3 clock source

◆ RCC_CFGR3_USART3SW_LSE

#define RCC_CFGR3_USART3SW_LSE (0x00080000U)

LSE oscillator clock used as USART3 clock source

◆ RCC_CFGR3_USART3SW_Msk

#define RCC_CFGR3_USART3SW_Msk (0x3UL << RCC_CFGR3_USART3SW_Pos)

0x000C0000

◆ RCC_CFGR3_USART3SW_PCLK

#define RCC_CFGR3_USART3SW_PCLK (0x00000000U)

PCLK1 clock used as USART3 clock source

◆ RCC_CFGR3_USART3SW_Pos

#define RCC_CFGR3_USART3SW_Pos (18U)

◆ RCC_CFGR3_USART3SW_SYSCLK

#define RCC_CFGR3_USART3SW_SYSCLK (0x00040000U)

System clock selected as USART3 clock source

◆ RCC_CFGR_HPRE

#define RCC_CFGR_HPRE RCC_CFGR_HPRE_Msk

HPRE[3:0] bits (AHB prescaler)

◆ RCC_CFGR_HPRE_0

#define RCC_CFGR_HPRE_0 (0x1UL << RCC_CFGR_HPRE_Pos)

0x00000010

◆ RCC_CFGR_HPRE_1

#define RCC_CFGR_HPRE_1 (0x2UL << RCC_CFGR_HPRE_Pos)

0x00000020

◆ RCC_CFGR_HPRE_2

#define RCC_CFGR_HPRE_2 (0x4UL << RCC_CFGR_HPRE_Pos)

0x00000040

◆ RCC_CFGR_HPRE_3

#define RCC_CFGR_HPRE_3 (0x8UL << RCC_CFGR_HPRE_Pos)

0x00000080

◆ RCC_CFGR_HPRE_DIV1

#define RCC_CFGR_HPRE_DIV1 (0x00000000U)

SYSCLK not divided

◆ RCC_CFGR_HPRE_DIV128

#define RCC_CFGR_HPRE_DIV128 (0x000000D0U)

SYSCLK divided by 128

◆ RCC_CFGR_HPRE_DIV16

#define RCC_CFGR_HPRE_DIV16 (0x000000B0U)

SYSCLK divided by 16

◆ RCC_CFGR_HPRE_DIV2

#define RCC_CFGR_HPRE_DIV2 (0x00000080U)

SYSCLK divided by 2

◆ RCC_CFGR_HPRE_DIV256

#define RCC_CFGR_HPRE_DIV256 (0x000000E0U)

SYSCLK divided by 256

◆ RCC_CFGR_HPRE_DIV4

#define RCC_CFGR_HPRE_DIV4 (0x00000090U)

SYSCLK divided by 4

◆ RCC_CFGR_HPRE_DIV512

#define RCC_CFGR_HPRE_DIV512 (0x000000F0U)

SYSCLK divided by 512 PPRE1 configuration

◆ RCC_CFGR_HPRE_DIV64

#define RCC_CFGR_HPRE_DIV64 (0x000000C0U)

SYSCLK divided by 64

◆ RCC_CFGR_HPRE_DIV8

#define RCC_CFGR_HPRE_DIV8 (0x000000A0U)

SYSCLK divided by 8

◆ RCC_CFGR_HPRE_Msk

#define RCC_CFGR_HPRE_Msk (0xFUL << RCC_CFGR_HPRE_Pos)

0x000000F0

◆ RCC_CFGR_HPRE_Pos

#define RCC_CFGR_HPRE_Pos (4U)

◆ RCC_CFGR_I2SSRC

#define RCC_CFGR_I2SSRC RCC_CFGR_I2SSRC_Msk

I2S external clock source selection

◆ RCC_CFGR_I2SSRC_EXT

#define RCC_CFGR_I2SSRC_EXT (0x00800000U)

External clock selected as I2S clock source MCO configuration

◆ RCC_CFGR_I2SSRC_Msk

#define RCC_CFGR_I2SSRC_Msk (0x1UL << RCC_CFGR_I2SSRC_Pos)

0x00800000

◆ RCC_CFGR_I2SSRC_Pos

#define RCC_CFGR_I2SSRC_Pos (23U)

◆ RCC_CFGR_I2SSRC_SYSCLK

#define RCC_CFGR_I2SSRC_SYSCLK (0x00000000U)

System clock selected as I2S clock source

◆ RCC_CFGR_MCO

#define RCC_CFGR_MCO RCC_CFGR_MCO_Msk

MCO[2:0] bits (Microcontroller Clock Output)

◆ RCC_CFGR_MCO_0

#define RCC_CFGR_MCO_0 (0x1UL << RCC_CFGR_MCO_Pos)

0x01000000

◆ RCC_CFGR_MCO_1

#define RCC_CFGR_MCO_1 (0x2UL << RCC_CFGR_MCO_Pos)

0x02000000

◆ RCC_CFGR_MCO_2

#define RCC_CFGR_MCO_2 (0x4UL << RCC_CFGR_MCO_Pos)

0x04000000

◆ RCC_CFGR_MCO_HSE

#define RCC_CFGR_MCO_HSE (0x06000000U)

HSE clock selected as MCO source

◆ RCC_CFGR_MCO_HSI

#define RCC_CFGR_MCO_HSI (0x05000000U)

HSI clock selected as MCO source

◆ RCC_CFGR_MCO_LSE

#define RCC_CFGR_MCO_LSE (0x03000000U)

LSE clock selected as MCO source

◆ RCC_CFGR_MCO_LSI

#define RCC_CFGR_MCO_LSI (0x02000000U)

LSI clock selected as MCO source

◆ RCC_CFGR_MCO_Msk

#define RCC_CFGR_MCO_Msk (0x7UL << RCC_CFGR_MCO_Pos)

0x07000000

◆ RCC_CFGR_MCO_NOCLOCK

#define RCC_CFGR_MCO_NOCLOCK (0x00000000U)

No clock

◆ RCC_CFGR_MCO_PLL

#define RCC_CFGR_MCO_PLL (0x07000000U)

PLL clock divided by 2 selected as MCO source

◆ RCC_CFGR_MCO_Pos

#define RCC_CFGR_MCO_Pos (24U)

◆ RCC_CFGR_MCO_SYSCLK

#define RCC_CFGR_MCO_SYSCLK (0x04000000U)

System clock selected as MCO source

◆ RCC_CFGR_MCOPRE

#define RCC_CFGR_MCOPRE RCC_CFGR_MCOPRE_Msk

MCOPRE[3:0] bits (Microcontroller Clock Output Prescaler)

◆ RCC_CFGR_MCOPRE_0

#define RCC_CFGR_MCOPRE_0 (0x1UL << RCC_CFGR_MCOPRE_Pos)

0x10000000

◆ RCC_CFGR_MCOPRE_1

#define RCC_CFGR_MCOPRE_1 (0x2UL << RCC_CFGR_MCOPRE_Pos)

0x20000000

◆ RCC_CFGR_MCOPRE_2

#define RCC_CFGR_MCOPRE_2 (0x4UL << RCC_CFGR_MCOPRE_Pos)

0x40000000

◆ RCC_CFGR_MCOPRE_DIV1

#define RCC_CFGR_MCOPRE_DIV1 (0x00000000U)

MCO is divided by 1

◆ RCC_CFGR_MCOPRE_DIV128

#define RCC_CFGR_MCOPRE_DIV128 (0x70000000U)

MCO is divided by 128

◆ RCC_CFGR_MCOPRE_DIV16

#define RCC_CFGR_MCOPRE_DIV16 (0x40000000U)

MCO is divided by 16

◆ RCC_CFGR_MCOPRE_DIV2

#define RCC_CFGR_MCOPRE_DIV2 (0x10000000U)

MCO is divided by 2

◆ RCC_CFGR_MCOPRE_DIV32

#define RCC_CFGR_MCOPRE_DIV32 (0x50000000U)

MCO is divided by 32

◆ RCC_CFGR_MCOPRE_DIV4

#define RCC_CFGR_MCOPRE_DIV4 (0x20000000U)

MCO is divided by 4

◆ RCC_CFGR_MCOPRE_DIV64

#define RCC_CFGR_MCOPRE_DIV64 (0x60000000U)

MCO is divided by 64

◆ RCC_CFGR_MCOPRE_DIV8

#define RCC_CFGR_MCOPRE_DIV8 (0x30000000U)

MCO is divided by 8

◆ RCC_CFGR_MCOPRE_Msk

#define RCC_CFGR_MCOPRE_Msk (0x7UL << RCC_CFGR_MCOPRE_Pos)

0x70000000

◆ RCC_CFGR_MCOPRE_Pos

#define RCC_CFGR_MCOPRE_Pos (28U)

◆ RCC_CFGR_MCOSEL

#define RCC_CFGR_MCOSEL RCC_CFGR_MCO

◆ RCC_CFGR_MCOSEL_0

#define RCC_CFGR_MCOSEL_0 RCC_CFGR_MCO_0

◆ RCC_CFGR_MCOSEL_1

#define RCC_CFGR_MCOSEL_1 RCC_CFGR_MCO_1

◆ RCC_CFGR_MCOSEL_2

#define RCC_CFGR_MCOSEL_2 RCC_CFGR_MCO_2

◆ RCC_CFGR_MCOSEL_HSE

#define RCC_CFGR_MCOSEL_HSE RCC_CFGR_MCO_HSE

◆ RCC_CFGR_MCOSEL_HSI

#define RCC_CFGR_MCOSEL_HSI RCC_CFGR_MCO_HSI

◆ RCC_CFGR_MCOSEL_LSE

#define RCC_CFGR_MCOSEL_LSE RCC_CFGR_MCO_LSE

◆ RCC_CFGR_MCOSEL_LSI

#define RCC_CFGR_MCOSEL_LSI RCC_CFGR_MCO_LSI

◆ RCC_CFGR_MCOSEL_NOCLOCK

#define RCC_CFGR_MCOSEL_NOCLOCK RCC_CFGR_MCO_NOCLOCK

◆ RCC_CFGR_MCOSEL_PLL_DIV2

#define RCC_CFGR_MCOSEL_PLL_DIV2 RCC_CFGR_MCO_PLL

◆ RCC_CFGR_MCOSEL_SYSCLK

#define RCC_CFGR_MCOSEL_SYSCLK RCC_CFGR_MCO_SYSCLK

◆ RCC_CFGR_PLLMUL

#define RCC_CFGR_PLLMUL RCC_CFGR_PLLMUL_Msk

PLLMUL[3:0] bits (PLL multiplication factor)

◆ RCC_CFGR_PLLMUL10

#define RCC_CFGR_PLLMUL10 (0x00200000U)

PLL input clock10

◆ RCC_CFGR_PLLMUL11

#define RCC_CFGR_PLLMUL11 (0x00240000U)

PLL input clock*11

◆ RCC_CFGR_PLLMUL12

#define RCC_CFGR_PLLMUL12 (0x00280000U)

PLL input clock*12

◆ RCC_CFGR_PLLMUL13

#define RCC_CFGR_PLLMUL13 (0x002C0000U)

PLL input clock*13

◆ RCC_CFGR_PLLMUL14

#define RCC_CFGR_PLLMUL14 (0x00300000U)

PLL input clock*14

◆ RCC_CFGR_PLLMUL15

#define RCC_CFGR_PLLMUL15 (0x00340000U)

PLL input clock*15

◆ RCC_CFGR_PLLMUL16

#define RCC_CFGR_PLLMUL16 (0x00380000U)

PLL input clock*16 USB configuration

◆ RCC_CFGR_PLLMUL2

#define RCC_CFGR_PLLMUL2 (0x00000000U)

PLL input clock*2

◆ RCC_CFGR_PLLMUL3

#define RCC_CFGR_PLLMUL3 (0x00040000U)

PLL input clock*3

◆ RCC_CFGR_PLLMUL4

#define RCC_CFGR_PLLMUL4 (0x00080000U)

PLL input clock*4

◆ RCC_CFGR_PLLMUL5

#define RCC_CFGR_PLLMUL5 (0x000C0000U)

PLL input clock*5

◆ RCC_CFGR_PLLMUL6

#define RCC_CFGR_PLLMUL6 (0x00100000U)

PLL input clock*6

◆ RCC_CFGR_PLLMUL7

#define RCC_CFGR_PLLMUL7 (0x00140000U)

PLL input clock*7

◆ RCC_CFGR_PLLMUL8

#define RCC_CFGR_PLLMUL8 (0x00180000U)

PLL input clock*8

◆ RCC_CFGR_PLLMUL9

#define RCC_CFGR_PLLMUL9 (0x001C0000U)

PLL input clock*9

◆ RCC_CFGR_PLLMUL_0

#define RCC_CFGR_PLLMUL_0 (0x1UL << RCC_CFGR_PLLMUL_Pos)

0x00040000

◆ RCC_CFGR_PLLMUL_1

#define RCC_CFGR_PLLMUL_1 (0x2UL << RCC_CFGR_PLLMUL_Pos)

0x00080000

◆ RCC_CFGR_PLLMUL_2

#define RCC_CFGR_PLLMUL_2 (0x4UL << RCC_CFGR_PLLMUL_Pos)

0x00100000

◆ RCC_CFGR_PLLMUL_3

#define RCC_CFGR_PLLMUL_3 (0x8UL << RCC_CFGR_PLLMUL_Pos)

0x00200000

◆ RCC_CFGR_PLLMUL_Msk

#define RCC_CFGR_PLLMUL_Msk (0xFUL << RCC_CFGR_PLLMUL_Pos)

0x003C0000

◆ RCC_CFGR_PLLMUL_Pos

#define RCC_CFGR_PLLMUL_Pos (18U)

◆ RCC_CFGR_PLLNODIV

#define RCC_CFGR_PLLNODIV RCC_CFGR_PLLNODIV_Msk

Do not divide PLL to MCO

◆ RCC_CFGR_PLLNODIV_Msk

#define RCC_CFGR_PLLNODIV_Msk (0x1UL << RCC_CFGR_PLLNODIV_Pos)

0x80000000

◆ RCC_CFGR_PLLNODIV_Pos

#define RCC_CFGR_PLLNODIV_Pos (31U)

◆ RCC_CFGR_PLLSRC

#define RCC_CFGR_PLLSRC RCC_CFGR_PLLSRC_Msk

PLL entry clock source

◆ RCC_CFGR_PLLSRC_HSE_PREDIV

#define RCC_CFGR_PLLSRC_HSE_PREDIV (0x00010000U)

HSE/PREDIV clock selected as PLL entry clock source

◆ RCC_CFGR_PLLSRC_HSI_PREDIV

#define RCC_CFGR_PLLSRC_HSI_PREDIV (0x00008000U)

HSI/PREDIV clock as PLL entry clock source

◆ RCC_CFGR_PLLSRC_Msk

#define RCC_CFGR_PLLSRC_Msk (0x3UL << RCC_CFGR_PLLSRC_Pos)

0x00018000

◆ RCC_CFGR_PLLSRC_Pos

#define RCC_CFGR_PLLSRC_Pos (15U)

◆ RCC_CFGR_PLLXTPRE

#define RCC_CFGR_PLLXTPRE RCC_CFGR_PLLXTPRE_Msk

HSE divider for PLL entry

◆ RCC_CFGR_PLLXTPRE_HSE_PREDIV_DIV1

#define RCC_CFGR_PLLXTPRE_HSE_PREDIV_DIV1 (0x00000000U)

HSE/PREDIV clock not divided for PLL entry

◆ RCC_CFGR_PLLXTPRE_HSE_PREDIV_DIV2

#define RCC_CFGR_PLLXTPRE_HSE_PREDIV_DIV2 (0x00020000U)

HSE/PREDIV clock divided by 2 for PLL entry PLLMUL configuration

◆ RCC_CFGR_PLLXTPRE_Msk

#define RCC_CFGR_PLLXTPRE_Msk (0x1UL << RCC_CFGR_PLLXTPRE_Pos)

0x00020000

◆ RCC_CFGR_PLLXTPRE_Pos

#define RCC_CFGR_PLLXTPRE_Pos (17U)

◆ RCC_CFGR_PPRE1

#define RCC_CFGR_PPRE1 RCC_CFGR_PPRE1_Msk

PRE1[2:0] bits (APB1 prescaler)

◆ RCC_CFGR_PPRE1_0

#define RCC_CFGR_PPRE1_0 (0x1UL << RCC_CFGR_PPRE1_Pos)

0x00000100

◆ RCC_CFGR_PPRE1_1

#define RCC_CFGR_PPRE1_1 (0x2UL << RCC_CFGR_PPRE1_Pos)

0x00000200

◆ RCC_CFGR_PPRE1_2

#define RCC_CFGR_PPRE1_2 (0x4UL << RCC_CFGR_PPRE1_Pos)

0x00000400

◆ RCC_CFGR_PPRE1_DIV1

#define RCC_CFGR_PPRE1_DIV1 (0x00000000U)

HCLK not divided

◆ RCC_CFGR_PPRE1_DIV16

#define RCC_CFGR_PPRE1_DIV16 (0x00000700U)

HCLK divided by 16 PPRE2 configuration

◆ RCC_CFGR_PPRE1_DIV2

#define RCC_CFGR_PPRE1_DIV2 (0x00000400U)

HCLK divided by 2

◆ RCC_CFGR_PPRE1_DIV4

#define RCC_CFGR_PPRE1_DIV4 (0x00000500U)

HCLK divided by 4

◆ RCC_CFGR_PPRE1_DIV8

#define RCC_CFGR_PPRE1_DIV8 (0x00000600U)

HCLK divided by 8

◆ RCC_CFGR_PPRE1_Msk

#define RCC_CFGR_PPRE1_Msk (0x7UL << RCC_CFGR_PPRE1_Pos)

0x00000700

◆ RCC_CFGR_PPRE1_Pos

#define RCC_CFGR_PPRE1_Pos (8U)

◆ RCC_CFGR_PPRE2

#define RCC_CFGR_PPRE2 RCC_CFGR_PPRE2_Msk

PRE2[2:0] bits (APB2 prescaler)

◆ RCC_CFGR_PPRE2_0

#define RCC_CFGR_PPRE2_0 (0x1UL << RCC_CFGR_PPRE2_Pos)

0x00000800

◆ RCC_CFGR_PPRE2_1

#define RCC_CFGR_PPRE2_1 (0x2UL << RCC_CFGR_PPRE2_Pos)

0x00001000

◆ RCC_CFGR_PPRE2_2

#define RCC_CFGR_PPRE2_2 (0x4UL << RCC_CFGR_PPRE2_Pos)

0x00002000

◆ RCC_CFGR_PPRE2_DIV1

#define RCC_CFGR_PPRE2_DIV1 (0x00000000U)

HCLK not divided

◆ RCC_CFGR_PPRE2_DIV16

#define RCC_CFGR_PPRE2_DIV16 (0x00003800U)

HCLK divided by 16

◆ RCC_CFGR_PPRE2_DIV2

#define RCC_CFGR_PPRE2_DIV2 (0x00002000U)

HCLK divided by 2

◆ RCC_CFGR_PPRE2_DIV4

#define RCC_CFGR_PPRE2_DIV4 (0x00002800U)

HCLK divided by 4

◆ RCC_CFGR_PPRE2_DIV8

#define RCC_CFGR_PPRE2_DIV8 (0x00003000U)

HCLK divided by 8

◆ RCC_CFGR_PPRE2_Msk

#define RCC_CFGR_PPRE2_Msk (0x7UL << RCC_CFGR_PPRE2_Pos)

0x00003800

◆ RCC_CFGR_PPRE2_Pos

#define RCC_CFGR_PPRE2_Pos (11U)

◆ RCC_CFGR_SW

#define RCC_CFGR_SW RCC_CFGR_SW_Msk

SW[1:0] bits (System clock Switch)

◆ RCC_CFGR_SW_0

#define RCC_CFGR_SW_0 (0x1UL << RCC_CFGR_SW_Pos)

0x00000001

◆ RCC_CFGR_SW_1

#define RCC_CFGR_SW_1 (0x2UL << RCC_CFGR_SW_Pos)

0x00000002

◆ RCC_CFGR_SW_HSE

#define RCC_CFGR_SW_HSE (0x00000001U)

HSE selected as system clock

◆ RCC_CFGR_SW_HSI

#define RCC_CFGR_SW_HSI (0x00000000U)

HSI selected as system clock

◆ RCC_CFGR_SW_Msk

#define RCC_CFGR_SW_Msk (0x3UL << RCC_CFGR_SW_Pos)

0x00000003

◆ RCC_CFGR_SW_PLL

#define RCC_CFGR_SW_PLL (0x00000002U)

PLL selected as system clock SWS configuration

◆ RCC_CFGR_SW_Pos

#define RCC_CFGR_SW_Pos (0U)

< SW configuration

◆ RCC_CFGR_SWS

#define RCC_CFGR_SWS RCC_CFGR_SWS_Msk

SWS[1:0] bits (System Clock Switch Status)

◆ RCC_CFGR_SWS_0

#define RCC_CFGR_SWS_0 (0x1UL << RCC_CFGR_SWS_Pos)

0x00000004

◆ RCC_CFGR_SWS_1

#define RCC_CFGR_SWS_1 (0x2UL << RCC_CFGR_SWS_Pos)

0x00000008

◆ RCC_CFGR_SWS_HSE

#define RCC_CFGR_SWS_HSE (0x00000004U)

HSE oscillator used as system clock

◆ RCC_CFGR_SWS_HSI

#define RCC_CFGR_SWS_HSI (0x00000000U)

HSI oscillator used as system clock

◆ RCC_CFGR_SWS_Msk

#define RCC_CFGR_SWS_Msk (0x3UL << RCC_CFGR_SWS_Pos)

0x0000000C

◆ RCC_CFGR_SWS_PLL

#define RCC_CFGR_SWS_PLL (0x00000008U)

PLL used as system clock HPRE configuration

◆ RCC_CFGR_SWS_Pos

#define RCC_CFGR_SWS_Pos (2U)

◆ RCC_CFGR_USBPRE

#define RCC_CFGR_USBPRE RCC_CFGR_USBPRE_Msk

USB prescaler

◆ RCC_CFGR_USBPRE_DIV1

#define RCC_CFGR_USBPRE_DIV1 (0x00400000U)

USB prescaler is PLL clock divided by 1 I2S configuration

◆ RCC_CFGR_USBPRE_DIV1_5

#define RCC_CFGR_USBPRE_DIV1_5 (0x00000000U)

USB prescaler is PLL clock divided by 1.5

◆ RCC_CFGR_USBPRE_Msk

#define RCC_CFGR_USBPRE_Msk (0x1UL << RCC_CFGR_USBPRE_Pos)

0x00400000

◆ RCC_CFGR_USBPRE_Pos

#define RCC_CFGR_USBPRE_Pos (22U)

◆ RCC_CIR_CSSC

#define RCC_CIR_CSSC RCC_CIR_CSSC_Msk

Clock Security System Interrupt Clear

◆ RCC_CIR_CSSC_Msk

#define RCC_CIR_CSSC_Msk (0x1UL << RCC_CIR_CSSC_Pos)

0x00800000

◆ RCC_CIR_CSSC_Pos

#define RCC_CIR_CSSC_Pos (23U)

◆ RCC_CIR_CSSF

#define RCC_CIR_CSSF RCC_CIR_CSSF_Msk

Clock Security System Interrupt flag

◆ RCC_CIR_CSSF_Msk

#define RCC_CIR_CSSF_Msk (0x1UL << RCC_CIR_CSSF_Pos)

0x00000080

◆ RCC_CIR_CSSF_Pos

#define RCC_CIR_CSSF_Pos (7U)

◆ RCC_CIR_HSERDYC

#define RCC_CIR_HSERDYC RCC_CIR_HSERDYC_Msk

HSE Ready Interrupt Clear

◆ RCC_CIR_HSERDYC_Msk

#define RCC_CIR_HSERDYC_Msk (0x1UL << RCC_CIR_HSERDYC_Pos)

0x00080000

◆ RCC_CIR_HSERDYC_Pos

#define RCC_CIR_HSERDYC_Pos (19U)

◆ RCC_CIR_HSERDYF

#define RCC_CIR_HSERDYF RCC_CIR_HSERDYF_Msk

HSE Ready Interrupt flag

◆ RCC_CIR_HSERDYF_Msk

#define RCC_CIR_HSERDYF_Msk (0x1UL << RCC_CIR_HSERDYF_Pos)

0x00000008

◆ RCC_CIR_HSERDYF_Pos

#define RCC_CIR_HSERDYF_Pos (3U)

◆ RCC_CIR_HSERDYIE

#define RCC_CIR_HSERDYIE RCC_CIR_HSERDYIE_Msk

HSE Ready Interrupt Enable

◆ RCC_CIR_HSERDYIE_Msk

#define RCC_CIR_HSERDYIE_Msk (0x1UL << RCC_CIR_HSERDYIE_Pos)

0x00000800

◆ RCC_CIR_HSERDYIE_Pos

#define RCC_CIR_HSERDYIE_Pos (11U)

◆ RCC_CIR_HSIRDYC

#define RCC_CIR_HSIRDYC RCC_CIR_HSIRDYC_Msk

HSI Ready Interrupt Clear

◆ RCC_CIR_HSIRDYC_Msk

#define RCC_CIR_HSIRDYC_Msk (0x1UL << RCC_CIR_HSIRDYC_Pos)

0x00040000

◆ RCC_CIR_HSIRDYC_Pos

#define RCC_CIR_HSIRDYC_Pos (18U)

◆ RCC_CIR_HSIRDYF

#define RCC_CIR_HSIRDYF RCC_CIR_HSIRDYF_Msk

HSI Ready Interrupt flag

◆ RCC_CIR_HSIRDYF_Msk

#define RCC_CIR_HSIRDYF_Msk (0x1UL << RCC_CIR_HSIRDYF_Pos)

0x00000004

◆ RCC_CIR_HSIRDYF_Pos

#define RCC_CIR_HSIRDYF_Pos (2U)

◆ RCC_CIR_HSIRDYIE

#define RCC_CIR_HSIRDYIE RCC_CIR_HSIRDYIE_Msk

HSI Ready Interrupt Enable

◆ RCC_CIR_HSIRDYIE_Msk

#define RCC_CIR_HSIRDYIE_Msk (0x1UL << RCC_CIR_HSIRDYIE_Pos)

0x00000400

◆ RCC_CIR_HSIRDYIE_Pos

#define RCC_CIR_HSIRDYIE_Pos (10U)

◆ RCC_CIR_LSERDYC

#define RCC_CIR_LSERDYC RCC_CIR_LSERDYC_Msk

LSE Ready Interrupt Clear

◆ RCC_CIR_LSERDYC_Msk

#define RCC_CIR_LSERDYC_Msk (0x1UL << RCC_CIR_LSERDYC_Pos)

0x00020000

◆ RCC_CIR_LSERDYC_Pos

#define RCC_CIR_LSERDYC_Pos (17U)

◆ RCC_CIR_LSERDYF

#define RCC_CIR_LSERDYF RCC_CIR_LSERDYF_Msk

LSE Ready Interrupt flag

◆ RCC_CIR_LSERDYF_Msk

#define RCC_CIR_LSERDYF_Msk (0x1UL << RCC_CIR_LSERDYF_Pos)

0x00000002

◆ RCC_CIR_LSERDYF_Pos

#define RCC_CIR_LSERDYF_Pos (1U)

◆ RCC_CIR_LSERDYIE

#define RCC_CIR_LSERDYIE RCC_CIR_LSERDYIE_Msk

LSE Ready Interrupt Enable

◆ RCC_CIR_LSERDYIE_Msk

#define RCC_CIR_LSERDYIE_Msk (0x1UL << RCC_CIR_LSERDYIE_Pos)

0x00000200

◆ RCC_CIR_LSERDYIE_Pos

#define RCC_CIR_LSERDYIE_Pos (9U)

◆ RCC_CIR_LSIRDYC

#define RCC_CIR_LSIRDYC RCC_CIR_LSIRDYC_Msk

LSI Ready Interrupt Clear

◆ RCC_CIR_LSIRDYC_Msk

#define RCC_CIR_LSIRDYC_Msk (0x1UL << RCC_CIR_LSIRDYC_Pos)

0x00010000

◆ RCC_CIR_LSIRDYC_Pos

#define RCC_CIR_LSIRDYC_Pos (16U)

◆ RCC_CIR_LSIRDYF

#define RCC_CIR_LSIRDYF RCC_CIR_LSIRDYF_Msk

LSI Ready Interrupt flag

◆ RCC_CIR_LSIRDYF_Msk

#define RCC_CIR_LSIRDYF_Msk (0x1UL << RCC_CIR_LSIRDYF_Pos)

0x00000001

◆ RCC_CIR_LSIRDYF_Pos

#define RCC_CIR_LSIRDYF_Pos (0U)

◆ RCC_CIR_LSIRDYIE

#define RCC_CIR_LSIRDYIE RCC_CIR_LSIRDYIE_Msk

LSI Ready Interrupt Enable

◆ RCC_CIR_LSIRDYIE_Msk

#define RCC_CIR_LSIRDYIE_Msk (0x1UL << RCC_CIR_LSIRDYIE_Pos)

0x00000100

◆ RCC_CIR_LSIRDYIE_Pos

#define RCC_CIR_LSIRDYIE_Pos (8U)

◆ RCC_CIR_PLLRDYC

#define RCC_CIR_PLLRDYC RCC_CIR_PLLRDYC_Msk

PLL Ready Interrupt Clear

◆ RCC_CIR_PLLRDYC_Msk

#define RCC_CIR_PLLRDYC_Msk (0x1UL << RCC_CIR_PLLRDYC_Pos)

0x00100000

◆ RCC_CIR_PLLRDYC_Pos

#define RCC_CIR_PLLRDYC_Pos (20U)

◆ RCC_CIR_PLLRDYF

#define RCC_CIR_PLLRDYF RCC_CIR_PLLRDYF_Msk

PLL Ready Interrupt flag

◆ RCC_CIR_PLLRDYF_Msk

#define RCC_CIR_PLLRDYF_Msk (0x1UL << RCC_CIR_PLLRDYF_Pos)

0x00000010

◆ RCC_CIR_PLLRDYF_Pos

#define RCC_CIR_PLLRDYF_Pos (4U)

◆ RCC_CIR_PLLRDYIE

#define RCC_CIR_PLLRDYIE RCC_CIR_PLLRDYIE_Msk

PLL Ready Interrupt Enable

◆ RCC_CIR_PLLRDYIE_Msk

#define RCC_CIR_PLLRDYIE_Msk (0x1UL << RCC_CIR_PLLRDYIE_Pos)

0x00001000

◆ RCC_CIR_PLLRDYIE_Pos

#define RCC_CIR_PLLRDYIE_Pos (12U)

◆ RCC_CR_CSSON

#define RCC_CR_CSSON RCC_CR_CSSON_Msk

◆ RCC_CR_CSSON_Msk

#define RCC_CR_CSSON_Msk (0x1UL << RCC_CR_CSSON_Pos)

0x00080000

◆ RCC_CR_CSSON_Pos

#define RCC_CR_CSSON_Pos (19U)

◆ RCC_CR_HSEBYP

#define RCC_CR_HSEBYP RCC_CR_HSEBYP_Msk

◆ RCC_CR_HSEBYP_Msk

#define RCC_CR_HSEBYP_Msk (0x1UL << RCC_CR_HSEBYP_Pos)

0x00040000

◆ RCC_CR_HSEBYP_Pos

#define RCC_CR_HSEBYP_Pos (18U)

◆ RCC_CR_HSEON

#define RCC_CR_HSEON RCC_CR_HSEON_Msk

◆ RCC_CR_HSEON_Msk

#define RCC_CR_HSEON_Msk (0x1UL << RCC_CR_HSEON_Pos)

0x00010000

◆ RCC_CR_HSEON_Pos

#define RCC_CR_HSEON_Pos (16U)

◆ RCC_CR_HSERDY

#define RCC_CR_HSERDY RCC_CR_HSERDY_Msk

◆ RCC_CR_HSERDY_Msk

#define RCC_CR_HSERDY_Msk (0x1UL << RCC_CR_HSERDY_Pos)

0x00020000

◆ RCC_CR_HSERDY_Pos

#define RCC_CR_HSERDY_Pos (17U)

◆ RCC_CR_HSICAL

#define RCC_CR_HSICAL RCC_CR_HSICAL_Msk

◆ RCC_CR_HSICAL_0

#define RCC_CR_HSICAL_0 (0x01UL << RCC_CR_HSICAL_Pos)

0x00000100

◆ RCC_CR_HSICAL_1

#define RCC_CR_HSICAL_1 (0x02UL << RCC_CR_HSICAL_Pos)

0x00000200

◆ RCC_CR_HSICAL_2

#define RCC_CR_HSICAL_2 (0x04UL << RCC_CR_HSICAL_Pos)

0x00000400

◆ RCC_CR_HSICAL_3

#define RCC_CR_HSICAL_3 (0x08UL << RCC_CR_HSICAL_Pos)

0x00000800

◆ RCC_CR_HSICAL_4

#define RCC_CR_HSICAL_4 (0x10UL << RCC_CR_HSICAL_Pos)

0x00001000

◆ RCC_CR_HSICAL_5

#define RCC_CR_HSICAL_5 (0x20UL << RCC_CR_HSICAL_Pos)

0x00002000

◆ RCC_CR_HSICAL_6

#define RCC_CR_HSICAL_6 (0x40UL << RCC_CR_HSICAL_Pos)

0x00004000

◆ RCC_CR_HSICAL_7

#define RCC_CR_HSICAL_7 (0x80UL << RCC_CR_HSICAL_Pos)

0x00008000

◆ RCC_CR_HSICAL_Msk

#define RCC_CR_HSICAL_Msk (0xFFUL << RCC_CR_HSICAL_Pos)

0x0000FF00

◆ RCC_CR_HSICAL_Pos

#define RCC_CR_HSICAL_Pos (8U)

◆ RCC_CR_HSION

#define RCC_CR_HSION RCC_CR_HSION_Msk

◆ RCC_CR_HSION_Msk

#define RCC_CR_HSION_Msk (0x1UL << RCC_CR_HSION_Pos)

0x00000001

◆ RCC_CR_HSION_Pos

#define RCC_CR_HSION_Pos (0U)

◆ RCC_CR_HSIRDY

#define RCC_CR_HSIRDY RCC_CR_HSIRDY_Msk

◆ RCC_CR_HSIRDY_Msk

#define RCC_CR_HSIRDY_Msk (0x1UL << RCC_CR_HSIRDY_Pos)

0x00000002

◆ RCC_CR_HSIRDY_Pos

#define RCC_CR_HSIRDY_Pos (1U)

◆ RCC_CR_HSITRIM

#define RCC_CR_HSITRIM RCC_CR_HSITRIM_Msk

◆ RCC_CR_HSITRIM_0

#define RCC_CR_HSITRIM_0 (0x01UL << RCC_CR_HSITRIM_Pos)

0x00000008

◆ RCC_CR_HSITRIM_1

#define RCC_CR_HSITRIM_1 (0x02UL << RCC_CR_HSITRIM_Pos)

0x00000010

◆ RCC_CR_HSITRIM_2

#define RCC_CR_HSITRIM_2 (0x04UL << RCC_CR_HSITRIM_Pos)

0x00000020

◆ RCC_CR_HSITRIM_3

#define RCC_CR_HSITRIM_3 (0x08UL << RCC_CR_HSITRIM_Pos)

0x00000040

◆ RCC_CR_HSITRIM_4

#define RCC_CR_HSITRIM_4 (0x10UL << RCC_CR_HSITRIM_Pos)

0x00000080

◆ RCC_CR_HSITRIM_Msk

#define RCC_CR_HSITRIM_Msk (0x1FUL << RCC_CR_HSITRIM_Pos)

0x000000F8

◆ RCC_CR_HSITRIM_Pos

#define RCC_CR_HSITRIM_Pos (3U)

◆ RCC_CR_PLLON

#define RCC_CR_PLLON RCC_CR_PLLON_Msk

◆ RCC_CR_PLLON_Msk

#define RCC_CR_PLLON_Msk (0x1UL << RCC_CR_PLLON_Pos)

0x01000000

◆ RCC_CR_PLLON_Pos

#define RCC_CR_PLLON_Pos (24U)

◆ RCC_CR_PLLRDY

#define RCC_CR_PLLRDY RCC_CR_PLLRDY_Msk

◆ RCC_CR_PLLRDY_Msk

#define RCC_CR_PLLRDY_Msk (0x1UL << RCC_CR_PLLRDY_Pos)

0x02000000

◆ RCC_CR_PLLRDY_Pos

#define RCC_CR_PLLRDY_Pos (25U)

◆ RCC_CSR_IWDGRSTF

#define RCC_CSR_IWDGRSTF RCC_CSR_IWDGRSTF_Msk

Independent Watchdog reset flag

◆ RCC_CSR_IWDGRSTF_Msk

#define RCC_CSR_IWDGRSTF_Msk (0x1UL << RCC_CSR_IWDGRSTF_Pos)

0x20000000

◆ RCC_CSR_IWDGRSTF_Pos

#define RCC_CSR_IWDGRSTF_Pos (29U)

◆ RCC_CSR_LPWRRSTF

#define RCC_CSR_LPWRRSTF RCC_CSR_LPWRRSTF_Msk

Low-Power reset flag

◆ RCC_CSR_LPWRRSTF_Msk

#define RCC_CSR_LPWRRSTF_Msk (0x1UL << RCC_CSR_LPWRRSTF_Pos)

0x80000000

◆ RCC_CSR_LPWRRSTF_Pos

#define RCC_CSR_LPWRRSTF_Pos (31U)

◆ RCC_CSR_LSION

#define RCC_CSR_LSION RCC_CSR_LSION_Msk

Internal Low Speed oscillator enable

◆ RCC_CSR_LSION_Msk

#define RCC_CSR_LSION_Msk (0x1UL << RCC_CSR_LSION_Pos)

0x00000001

◆ RCC_CSR_LSION_Pos

#define RCC_CSR_LSION_Pos (0U)

◆ RCC_CSR_LSIRDY

#define RCC_CSR_LSIRDY RCC_CSR_LSIRDY_Msk

Internal Low Speed oscillator Ready

◆ RCC_CSR_LSIRDY_Msk

#define RCC_CSR_LSIRDY_Msk (0x1UL << RCC_CSR_LSIRDY_Pos)

0x00000002

◆ RCC_CSR_LSIRDY_Pos

#define RCC_CSR_LSIRDY_Pos (1U)

◆ RCC_CSR_OBLRSTF

#define RCC_CSR_OBLRSTF RCC_CSR_OBLRSTF_Msk

OBL reset flag

◆ RCC_CSR_OBLRSTF_Msk

#define RCC_CSR_OBLRSTF_Msk (0x1UL << RCC_CSR_OBLRSTF_Pos)

0x02000000

◆ RCC_CSR_OBLRSTF_Pos

#define RCC_CSR_OBLRSTF_Pos (25U)

◆ RCC_CSR_PINRSTF

#define RCC_CSR_PINRSTF RCC_CSR_PINRSTF_Msk

PIN reset flag

◆ RCC_CSR_PINRSTF_Msk

#define RCC_CSR_PINRSTF_Msk (0x1UL << RCC_CSR_PINRSTF_Pos)

0x04000000

◆ RCC_CSR_PINRSTF_Pos

#define RCC_CSR_PINRSTF_Pos (26U)

◆ RCC_CSR_PORRSTF

#define RCC_CSR_PORRSTF RCC_CSR_PORRSTF_Msk

POR/PDR reset flag

◆ RCC_CSR_PORRSTF_Msk

#define RCC_CSR_PORRSTF_Msk (0x1UL << RCC_CSR_PORRSTF_Pos)

0x08000000

◆ RCC_CSR_PORRSTF_Pos

#define RCC_CSR_PORRSTF_Pos (27U)

◆ RCC_CSR_RMVF

#define RCC_CSR_RMVF RCC_CSR_RMVF_Msk

Remove reset flag

◆ RCC_CSR_RMVF_Msk

#define RCC_CSR_RMVF_Msk (0x1UL << RCC_CSR_RMVF_Pos)

0x01000000

◆ RCC_CSR_RMVF_Pos

#define RCC_CSR_RMVF_Pos (24U)

◆ RCC_CSR_SFTRSTF

#define RCC_CSR_SFTRSTF RCC_CSR_SFTRSTF_Msk

Software Reset flag

◆ RCC_CSR_SFTRSTF_Msk

#define RCC_CSR_SFTRSTF_Msk (0x1UL << RCC_CSR_SFTRSTF_Pos)

0x10000000

◆ RCC_CSR_SFTRSTF_Pos

#define RCC_CSR_SFTRSTF_Pos (28U)

◆ RCC_CSR_V18PWRRSTF

#define RCC_CSR_V18PWRRSTF RCC_CSR_V18PWRRSTF_Msk

V1.8 power domain reset flag

◆ RCC_CSR_V18PWRRSTF_Msk

#define RCC_CSR_V18PWRRSTF_Msk (0x1UL << RCC_CSR_V18PWRRSTF_Pos)

0x00800000

◆ RCC_CSR_V18PWRRSTF_Pos

#define RCC_CSR_V18PWRRSTF_Pos (23U)

◆ RCC_CSR_VREGRSTF

#define RCC_CSR_VREGRSTF RCC_CSR_V18PWRRSTF

◆ RCC_CSR_WWDGRSTF

#define RCC_CSR_WWDGRSTF RCC_CSR_WWDGRSTF_Msk

Window watchdog reset flag

◆ RCC_CSR_WWDGRSTF_Msk

#define RCC_CSR_WWDGRSTF_Msk (0x1UL << RCC_CSR_WWDGRSTF_Pos)

0x40000000

◆ RCC_CSR_WWDGRSTF_Pos

#define RCC_CSR_WWDGRSTF_Pos (30U)

◆ RCC_PLLSRC_PREDIV1_SUPPORT

#define RCC_PLLSRC_PREDIV1_SUPPORT

PREDIV support used as PLL source input

◆ RDP_KEY

#define RDP_KEY RDP_KEY_Msk

RDP Key

◆ RDP_KEY_Msk

#define RDP_KEY_Msk (0xA5UL << RDP_KEY_Pos)

0x000000A5

◆ RDP_KEY_Pos

#define RDP_KEY_Pos (0U)

◆ RTC_ALRMAR_DT

#define RTC_ALRMAR_DT RTC_ALRMAR_DT_Msk

◆ RTC_ALRMAR_DT_0

#define RTC_ALRMAR_DT_0 (0x1UL << RTC_ALRMAR_DT_Pos)

0x10000000

◆ RTC_ALRMAR_DT_1

#define RTC_ALRMAR_DT_1 (0x2UL << RTC_ALRMAR_DT_Pos)

0x20000000

◆ RTC_ALRMAR_DT_Msk

#define RTC_ALRMAR_DT_Msk (0x3UL << RTC_ALRMAR_DT_Pos)

0x30000000

◆ RTC_ALRMAR_DT_Pos

#define RTC_ALRMAR_DT_Pos (28U)

◆ RTC_ALRMAR_DU

#define RTC_ALRMAR_DU RTC_ALRMAR_DU_Msk

◆ RTC_ALRMAR_DU_0

#define RTC_ALRMAR_DU_0 (0x1UL << RTC_ALRMAR_DU_Pos)

0x01000000

◆ RTC_ALRMAR_DU_1

#define RTC_ALRMAR_DU_1 (0x2UL << RTC_ALRMAR_DU_Pos)

0x02000000

◆ RTC_ALRMAR_DU_2

#define RTC_ALRMAR_DU_2 (0x4UL << RTC_ALRMAR_DU_Pos)

0x04000000

◆ RTC_ALRMAR_DU_3

#define RTC_ALRMAR_DU_3 (0x8UL << RTC_ALRMAR_DU_Pos)

0x08000000

◆ RTC_ALRMAR_DU_Msk

#define RTC_ALRMAR_DU_Msk (0xFUL << RTC_ALRMAR_DU_Pos)

0x0F000000

◆ RTC_ALRMAR_DU_Pos

#define RTC_ALRMAR_DU_Pos (24U)

◆ RTC_ALRMAR_HT

#define RTC_ALRMAR_HT RTC_ALRMAR_HT_Msk

◆ RTC_ALRMAR_HT_0

#define RTC_ALRMAR_HT_0 (0x1UL << RTC_ALRMAR_HT_Pos)

0x00100000

◆ RTC_ALRMAR_HT_1

#define RTC_ALRMAR_HT_1 (0x2UL << RTC_ALRMAR_HT_Pos)

0x00200000

◆ RTC_ALRMAR_HT_Msk

#define RTC_ALRMAR_HT_Msk (0x3UL << RTC_ALRMAR_HT_Pos)

0x00300000

◆ RTC_ALRMAR_HT_Pos

#define RTC_ALRMAR_HT_Pos (20U)

◆ RTC_ALRMAR_HU

#define RTC_ALRMAR_HU RTC_ALRMAR_HU_Msk

◆ RTC_ALRMAR_HU_0

#define RTC_ALRMAR_HU_0 (0x1UL << RTC_ALRMAR_HU_Pos)

0x00010000

◆ RTC_ALRMAR_HU_1

#define RTC_ALRMAR_HU_1 (0x2UL << RTC_ALRMAR_HU_Pos)

0x00020000

◆ RTC_ALRMAR_HU_2

#define RTC_ALRMAR_HU_2 (0x4UL << RTC_ALRMAR_HU_Pos)

0x00040000

◆ RTC_ALRMAR_HU_3

#define RTC_ALRMAR_HU_3 (0x8UL << RTC_ALRMAR_HU_Pos)

0x00080000

◆ RTC_ALRMAR_HU_Msk

#define RTC_ALRMAR_HU_Msk (0xFUL << RTC_ALRMAR_HU_Pos)

0x000F0000

◆ RTC_ALRMAR_HU_Pos

#define RTC_ALRMAR_HU_Pos (16U)

◆ RTC_ALRMAR_MNT

#define RTC_ALRMAR_MNT RTC_ALRMAR_MNT_Msk

◆ RTC_ALRMAR_MNT_0

#define RTC_ALRMAR_MNT_0 (0x1UL << RTC_ALRMAR_MNT_Pos)

0x00001000

◆ RTC_ALRMAR_MNT_1

#define RTC_ALRMAR_MNT_1 (0x2UL << RTC_ALRMAR_MNT_Pos)

0x00002000

◆ RTC_ALRMAR_MNT_2

#define RTC_ALRMAR_MNT_2 (0x4UL << RTC_ALRMAR_MNT_Pos)

0x00004000

◆ RTC_ALRMAR_MNT_Msk

#define RTC_ALRMAR_MNT_Msk (0x7UL << RTC_ALRMAR_MNT_Pos)

0x00007000

◆ RTC_ALRMAR_MNT_Pos

#define RTC_ALRMAR_MNT_Pos (12U)

◆ RTC_ALRMAR_MNU

#define RTC_ALRMAR_MNU RTC_ALRMAR_MNU_Msk

◆ RTC_ALRMAR_MNU_0

#define RTC_ALRMAR_MNU_0 (0x1UL << RTC_ALRMAR_MNU_Pos)

0x00000100

◆ RTC_ALRMAR_MNU_1

#define RTC_ALRMAR_MNU_1 (0x2UL << RTC_ALRMAR_MNU_Pos)

0x00000200

◆ RTC_ALRMAR_MNU_2

#define RTC_ALRMAR_MNU_2 (0x4UL << RTC_ALRMAR_MNU_Pos)

0x00000400

◆ RTC_ALRMAR_MNU_3

#define RTC_ALRMAR_MNU_3 (0x8UL << RTC_ALRMAR_MNU_Pos)

0x00000800

◆ RTC_ALRMAR_MNU_Msk

#define RTC_ALRMAR_MNU_Msk (0xFUL << RTC_ALRMAR_MNU_Pos)

0x00000F00

◆ RTC_ALRMAR_MNU_Pos

#define RTC_ALRMAR_MNU_Pos (8U)

◆ RTC_ALRMAR_MSK1

#define RTC_ALRMAR_MSK1 RTC_ALRMAR_MSK1_Msk

◆ RTC_ALRMAR_MSK1_Msk

#define RTC_ALRMAR_MSK1_Msk (0x1UL << RTC_ALRMAR_MSK1_Pos)

0x00000080

◆ RTC_ALRMAR_MSK1_Pos

#define RTC_ALRMAR_MSK1_Pos (7U)

◆ RTC_ALRMAR_MSK2

#define RTC_ALRMAR_MSK2 RTC_ALRMAR_MSK2_Msk

◆ RTC_ALRMAR_MSK2_Msk

#define RTC_ALRMAR_MSK2_Msk (0x1UL << RTC_ALRMAR_MSK2_Pos)

0x00008000

◆ RTC_ALRMAR_MSK2_Pos

#define RTC_ALRMAR_MSK2_Pos (15U)

◆ RTC_ALRMAR_MSK3

#define RTC_ALRMAR_MSK3 RTC_ALRMAR_MSK3_Msk

◆ RTC_ALRMAR_MSK3_Msk

#define RTC_ALRMAR_MSK3_Msk (0x1UL << RTC_ALRMAR_MSK3_Pos)

0x00800000

◆ RTC_ALRMAR_MSK3_Pos

#define RTC_ALRMAR_MSK3_Pos (23U)

◆ RTC_ALRMAR_MSK4

#define RTC_ALRMAR_MSK4 RTC_ALRMAR_MSK4_Msk

◆ RTC_ALRMAR_MSK4_Msk

#define RTC_ALRMAR_MSK4_Msk (0x1UL << RTC_ALRMAR_MSK4_Pos)

0x80000000

◆ RTC_ALRMAR_MSK4_Pos

#define RTC_ALRMAR_MSK4_Pos (31U)

◆ RTC_ALRMAR_PM

#define RTC_ALRMAR_PM RTC_ALRMAR_PM_Msk

◆ RTC_ALRMAR_PM_Msk

#define RTC_ALRMAR_PM_Msk (0x1UL << RTC_ALRMAR_PM_Pos)

0x00400000

◆ RTC_ALRMAR_PM_Pos

#define RTC_ALRMAR_PM_Pos (22U)

◆ RTC_ALRMAR_ST

#define RTC_ALRMAR_ST RTC_ALRMAR_ST_Msk

◆ RTC_ALRMAR_ST_0

#define RTC_ALRMAR_ST_0 (0x1UL << RTC_ALRMAR_ST_Pos)

0x00000010

◆ RTC_ALRMAR_ST_1

#define RTC_ALRMAR_ST_1 (0x2UL << RTC_ALRMAR_ST_Pos)

0x00000020

◆ RTC_ALRMAR_ST_2

#define RTC_ALRMAR_ST_2 (0x4UL << RTC_ALRMAR_ST_Pos)

0x00000040

◆ RTC_ALRMAR_ST_Msk

#define RTC_ALRMAR_ST_Msk (0x7UL << RTC_ALRMAR_ST_Pos)

0x00000070

◆ RTC_ALRMAR_ST_Pos

#define RTC_ALRMAR_ST_Pos (4U)

◆ RTC_ALRMAR_SU

#define RTC_ALRMAR_SU RTC_ALRMAR_SU_Msk

◆ RTC_ALRMAR_SU_0

#define RTC_ALRMAR_SU_0 (0x1UL << RTC_ALRMAR_SU_Pos)

0x00000001

◆ RTC_ALRMAR_SU_1

#define RTC_ALRMAR_SU_1 (0x2UL << RTC_ALRMAR_SU_Pos)

0x00000002

◆ RTC_ALRMAR_SU_2

#define RTC_ALRMAR_SU_2 (0x4UL << RTC_ALRMAR_SU_Pos)

0x00000004

◆ RTC_ALRMAR_SU_3

#define RTC_ALRMAR_SU_3 (0x8UL << RTC_ALRMAR_SU_Pos)

0x00000008

◆ RTC_ALRMAR_SU_Msk

#define RTC_ALRMAR_SU_Msk (0xFUL << RTC_ALRMAR_SU_Pos)

0x0000000F

◆ RTC_ALRMAR_SU_Pos

#define RTC_ALRMAR_SU_Pos (0U)

◆ RTC_ALRMAR_WDSEL

#define RTC_ALRMAR_WDSEL RTC_ALRMAR_WDSEL_Msk

◆ RTC_ALRMAR_WDSEL_Msk

#define RTC_ALRMAR_WDSEL_Msk (0x1UL << RTC_ALRMAR_WDSEL_Pos)

0x40000000

◆ RTC_ALRMAR_WDSEL_Pos

#define RTC_ALRMAR_WDSEL_Pos (30U)

◆ RTC_ALRMASSR_MASKSS

#define RTC_ALRMASSR_MASKSS RTC_ALRMASSR_MASKSS_Msk

◆ RTC_ALRMASSR_MASKSS_0

#define RTC_ALRMASSR_MASKSS_0 (0x1UL << RTC_ALRMASSR_MASKSS_Pos)

0x01000000

◆ RTC_ALRMASSR_MASKSS_1

#define RTC_ALRMASSR_MASKSS_1 (0x2UL << RTC_ALRMASSR_MASKSS_Pos)

0x02000000

◆ RTC_ALRMASSR_MASKSS_2

#define RTC_ALRMASSR_MASKSS_2 (0x4UL << RTC_ALRMASSR_MASKSS_Pos)

0x04000000

◆ RTC_ALRMASSR_MASKSS_3

#define RTC_ALRMASSR_MASKSS_3 (0x8UL << RTC_ALRMASSR_MASKSS_Pos)

0x08000000

◆ RTC_ALRMASSR_MASKSS_Msk

#define RTC_ALRMASSR_MASKSS_Msk (0xFUL << RTC_ALRMASSR_MASKSS_Pos)

0x0F000000

◆ RTC_ALRMASSR_MASKSS_Pos

#define RTC_ALRMASSR_MASKSS_Pos (24U)

◆ RTC_ALRMASSR_SS

#define RTC_ALRMASSR_SS RTC_ALRMASSR_SS_Msk

◆ RTC_ALRMASSR_SS_Msk

#define RTC_ALRMASSR_SS_Msk (0x7FFFUL << RTC_ALRMASSR_SS_Pos)

0x00007FFF

◆ RTC_ALRMASSR_SS_Pos

#define RTC_ALRMASSR_SS_Pos (0U)

◆ RTC_ALRMBR_DT

#define RTC_ALRMBR_DT RTC_ALRMBR_DT_Msk

◆ RTC_ALRMBR_DT_0

#define RTC_ALRMBR_DT_0 (0x1UL << RTC_ALRMBR_DT_Pos)

0x10000000

◆ RTC_ALRMBR_DT_1

#define RTC_ALRMBR_DT_1 (0x2UL << RTC_ALRMBR_DT_Pos)

0x20000000

◆ RTC_ALRMBR_DT_Msk

#define RTC_ALRMBR_DT_Msk (0x3UL << RTC_ALRMBR_DT_Pos)

0x30000000

◆ RTC_ALRMBR_DT_Pos

#define RTC_ALRMBR_DT_Pos (28U)

◆ RTC_ALRMBR_DU

#define RTC_ALRMBR_DU RTC_ALRMBR_DU_Msk

◆ RTC_ALRMBR_DU_0

#define RTC_ALRMBR_DU_0 (0x1UL << RTC_ALRMBR_DU_Pos)

0x01000000

◆ RTC_ALRMBR_DU_1

#define RTC_ALRMBR_DU_1 (0x2UL << RTC_ALRMBR_DU_Pos)

0x02000000

◆ RTC_ALRMBR_DU_2

#define RTC_ALRMBR_DU_2 (0x4UL << RTC_ALRMBR_DU_Pos)

0x04000000

◆ RTC_ALRMBR_DU_3

#define RTC_ALRMBR_DU_3 (0x8UL << RTC_ALRMBR_DU_Pos)

0x08000000

◆ RTC_ALRMBR_DU_Msk

#define RTC_ALRMBR_DU_Msk (0xFUL << RTC_ALRMBR_DU_Pos)

0x0F000000

◆ RTC_ALRMBR_DU_Pos

#define RTC_ALRMBR_DU_Pos (24U)

◆ RTC_ALRMBR_HT

#define RTC_ALRMBR_HT RTC_ALRMBR_HT_Msk

◆ RTC_ALRMBR_HT_0

#define RTC_ALRMBR_HT_0 (0x1UL << RTC_ALRMBR_HT_Pos)

0x00100000

◆ RTC_ALRMBR_HT_1

#define RTC_ALRMBR_HT_1 (0x2UL << RTC_ALRMBR_HT_Pos)

0x00200000

◆ RTC_ALRMBR_HT_Msk

#define RTC_ALRMBR_HT_Msk (0x3UL << RTC_ALRMBR_HT_Pos)

0x00300000

◆ RTC_ALRMBR_HT_Pos

#define RTC_ALRMBR_HT_Pos (20U)

◆ RTC_ALRMBR_HU

#define RTC_ALRMBR_HU RTC_ALRMBR_HU_Msk

◆ RTC_ALRMBR_HU_0

#define RTC_ALRMBR_HU_0 (0x1UL << RTC_ALRMBR_HU_Pos)

0x00010000

◆ RTC_ALRMBR_HU_1

#define RTC_ALRMBR_HU_1 (0x2UL << RTC_ALRMBR_HU_Pos)

0x00020000

◆ RTC_ALRMBR_HU_2

#define RTC_ALRMBR_HU_2 (0x4UL << RTC_ALRMBR_HU_Pos)

0x00040000

◆ RTC_ALRMBR_HU_3

#define RTC_ALRMBR_HU_3 (0x8UL << RTC_ALRMBR_HU_Pos)

0x00080000

◆ RTC_ALRMBR_HU_Msk

#define RTC_ALRMBR_HU_Msk (0xFUL << RTC_ALRMBR_HU_Pos)

0x000F0000

◆ RTC_ALRMBR_HU_Pos

#define RTC_ALRMBR_HU_Pos (16U)

◆ RTC_ALRMBR_MNT

#define RTC_ALRMBR_MNT RTC_ALRMBR_MNT_Msk

◆ RTC_ALRMBR_MNT_0

#define RTC_ALRMBR_MNT_0 (0x1UL << RTC_ALRMBR_MNT_Pos)

0x00001000

◆ RTC_ALRMBR_MNT_1

#define RTC_ALRMBR_MNT_1 (0x2UL << RTC_ALRMBR_MNT_Pos)

0x00002000

◆ RTC_ALRMBR_MNT_2

#define RTC_ALRMBR_MNT_2 (0x4UL << RTC_ALRMBR_MNT_Pos)

0x00004000

◆ RTC_ALRMBR_MNT_Msk

#define RTC_ALRMBR_MNT_Msk (0x7UL << RTC_ALRMBR_MNT_Pos)

0x00007000

◆ RTC_ALRMBR_MNT_Pos

#define RTC_ALRMBR_MNT_Pos (12U)

◆ RTC_ALRMBR_MNU

#define RTC_ALRMBR_MNU RTC_ALRMBR_MNU_Msk

◆ RTC_ALRMBR_MNU_0

#define RTC_ALRMBR_MNU_0 (0x1UL << RTC_ALRMBR_MNU_Pos)

0x00000100

◆ RTC_ALRMBR_MNU_1

#define RTC_ALRMBR_MNU_1 (0x2UL << RTC_ALRMBR_MNU_Pos)

0x00000200

◆ RTC_ALRMBR_MNU_2

#define RTC_ALRMBR_MNU_2 (0x4UL << RTC_ALRMBR_MNU_Pos)

0x00000400

◆ RTC_ALRMBR_MNU_3

#define RTC_ALRMBR_MNU_3 (0x8UL << RTC_ALRMBR_MNU_Pos)

0x00000800

◆ RTC_ALRMBR_MNU_Msk

#define RTC_ALRMBR_MNU_Msk (0xFUL << RTC_ALRMBR_MNU_Pos)

0x00000F00

◆ RTC_ALRMBR_MNU_Pos

#define RTC_ALRMBR_MNU_Pos (8U)

◆ RTC_ALRMBR_MSK1

#define RTC_ALRMBR_MSK1 RTC_ALRMBR_MSK1_Msk

◆ RTC_ALRMBR_MSK1_Msk

#define RTC_ALRMBR_MSK1_Msk (0x1UL << RTC_ALRMBR_MSK1_Pos)

0x00000080

◆ RTC_ALRMBR_MSK1_Pos

#define RTC_ALRMBR_MSK1_Pos (7U)

◆ RTC_ALRMBR_MSK2

#define RTC_ALRMBR_MSK2 RTC_ALRMBR_MSK2_Msk

◆ RTC_ALRMBR_MSK2_Msk

#define RTC_ALRMBR_MSK2_Msk (0x1UL << RTC_ALRMBR_MSK2_Pos)

0x00008000

◆ RTC_ALRMBR_MSK2_Pos

#define RTC_ALRMBR_MSK2_Pos (15U)

◆ RTC_ALRMBR_MSK3

#define RTC_ALRMBR_MSK3 RTC_ALRMBR_MSK3_Msk

◆ RTC_ALRMBR_MSK3_Msk

#define RTC_ALRMBR_MSK3_Msk (0x1UL << RTC_ALRMBR_MSK3_Pos)

0x00800000

◆ RTC_ALRMBR_MSK3_Pos

#define RTC_ALRMBR_MSK3_Pos (23U)

◆ RTC_ALRMBR_MSK4

#define RTC_ALRMBR_MSK4 RTC_ALRMBR_MSK4_Msk

◆ RTC_ALRMBR_MSK4_Msk

#define RTC_ALRMBR_MSK4_Msk (0x1UL << RTC_ALRMBR_MSK4_Pos)

0x80000000

◆ RTC_ALRMBR_MSK4_Pos

#define RTC_ALRMBR_MSK4_Pos (31U)

◆ RTC_ALRMBR_PM

#define RTC_ALRMBR_PM RTC_ALRMBR_PM_Msk

◆ RTC_ALRMBR_PM_Msk

#define RTC_ALRMBR_PM_Msk (0x1UL << RTC_ALRMBR_PM_Pos)

0x00400000

◆ RTC_ALRMBR_PM_Pos

#define RTC_ALRMBR_PM_Pos (22U)

◆ RTC_ALRMBR_ST

#define RTC_ALRMBR_ST RTC_ALRMBR_ST_Msk

◆ RTC_ALRMBR_ST_0

#define RTC_ALRMBR_ST_0 (0x1UL << RTC_ALRMBR_ST_Pos)

0x00000010

◆ RTC_ALRMBR_ST_1

#define RTC_ALRMBR_ST_1 (0x2UL << RTC_ALRMBR_ST_Pos)

0x00000020

◆ RTC_ALRMBR_ST_2

#define RTC_ALRMBR_ST_2 (0x4UL << RTC_ALRMBR_ST_Pos)

0x00000040

◆ RTC_ALRMBR_ST_Msk

#define RTC_ALRMBR_ST_Msk (0x7UL << RTC_ALRMBR_ST_Pos)

0x00000070

◆ RTC_ALRMBR_ST_Pos

#define RTC_ALRMBR_ST_Pos (4U)

◆ RTC_ALRMBR_SU

#define RTC_ALRMBR_SU RTC_ALRMBR_SU_Msk

◆ RTC_ALRMBR_SU_0

#define RTC_ALRMBR_SU_0 (0x1UL << RTC_ALRMBR_SU_Pos)

0x00000001

◆ RTC_ALRMBR_SU_1

#define RTC_ALRMBR_SU_1 (0x2UL << RTC_ALRMBR_SU_Pos)

0x00000002

◆ RTC_ALRMBR_SU_2

#define RTC_ALRMBR_SU_2 (0x4UL << RTC_ALRMBR_SU_Pos)

0x00000004

◆ RTC_ALRMBR_SU_3

#define RTC_ALRMBR_SU_3 (0x8UL << RTC_ALRMBR_SU_Pos)

0x00000008

◆ RTC_ALRMBR_SU_Msk

#define RTC_ALRMBR_SU_Msk (0xFUL << RTC_ALRMBR_SU_Pos)

0x0000000F

◆ RTC_ALRMBR_SU_Pos

#define RTC_ALRMBR_SU_Pos (0U)

◆ RTC_ALRMBR_WDSEL

#define RTC_ALRMBR_WDSEL RTC_ALRMBR_WDSEL_Msk

◆ RTC_ALRMBR_WDSEL_Msk

#define RTC_ALRMBR_WDSEL_Msk (0x1UL << RTC_ALRMBR_WDSEL_Pos)

0x40000000

◆ RTC_ALRMBR_WDSEL_Pos

#define RTC_ALRMBR_WDSEL_Pos (30U)

◆ RTC_ALRMBSSR_MASKSS

#define RTC_ALRMBSSR_MASKSS RTC_ALRMBSSR_MASKSS_Msk

◆ RTC_ALRMBSSR_MASKSS_0

#define RTC_ALRMBSSR_MASKSS_0 (0x1UL << RTC_ALRMBSSR_MASKSS_Pos)

0x01000000

◆ RTC_ALRMBSSR_MASKSS_1

#define RTC_ALRMBSSR_MASKSS_1 (0x2UL << RTC_ALRMBSSR_MASKSS_Pos)

0x02000000

◆ RTC_ALRMBSSR_MASKSS_2

#define RTC_ALRMBSSR_MASKSS_2 (0x4UL << RTC_ALRMBSSR_MASKSS_Pos)

0x04000000

◆ RTC_ALRMBSSR_MASKSS_3

#define RTC_ALRMBSSR_MASKSS_3 (0x8UL << RTC_ALRMBSSR_MASKSS_Pos)

0x08000000

◆ RTC_ALRMBSSR_MASKSS_Msk

#define RTC_ALRMBSSR_MASKSS_Msk (0xFUL << RTC_ALRMBSSR_MASKSS_Pos)

0x0F000000

◆ RTC_ALRMBSSR_MASKSS_Pos

#define RTC_ALRMBSSR_MASKSS_Pos (24U)

◆ RTC_ALRMBSSR_SS

#define RTC_ALRMBSSR_SS RTC_ALRMBSSR_SS_Msk

◆ RTC_ALRMBSSR_SS_Msk

#define RTC_ALRMBSSR_SS_Msk (0x7FFFUL << RTC_ALRMBSSR_SS_Pos)

0x00007FFF

◆ RTC_ALRMBSSR_SS_Pos

#define RTC_ALRMBSSR_SS_Pos (0U)

◆ RTC_BACKUP_SUPPORT

#define RTC_BACKUP_SUPPORT

BACKUP register feature support

◆ RTC_BKP0R

#define RTC_BKP0R RTC_BKP0R_Msk

◆ RTC_BKP0R_Msk

#define RTC_BKP0R_Msk (0xFFFFFFFFUL << RTC_BKP0R_Pos)

0xFFFFFFFF

◆ RTC_BKP0R_Pos

#define RTC_BKP0R_Pos (0U)

◆ RTC_BKP10R

#define RTC_BKP10R RTC_BKP10R_Msk

◆ RTC_BKP10R_Msk

#define RTC_BKP10R_Msk (0xFFFFFFFFUL << RTC_BKP10R_Pos)

0xFFFFFFFF

◆ RTC_BKP10R_Pos

#define RTC_BKP10R_Pos (0U)

◆ RTC_BKP11R

#define RTC_BKP11R RTC_BKP11R_Msk

◆ RTC_BKP11R_Msk

#define RTC_BKP11R_Msk (0xFFFFFFFFUL << RTC_BKP11R_Pos)

0xFFFFFFFF

◆ RTC_BKP11R_Pos

#define RTC_BKP11R_Pos (0U)

◆ RTC_BKP12R

#define RTC_BKP12R RTC_BKP12R_Msk

◆ RTC_BKP12R_Msk

#define RTC_BKP12R_Msk (0xFFFFFFFFUL << RTC_BKP12R_Pos)

0xFFFFFFFF

◆ RTC_BKP12R_Pos

#define RTC_BKP12R_Pos (0U)

◆ RTC_BKP13R

#define RTC_BKP13R RTC_BKP13R_Msk

◆ RTC_BKP13R_Msk

#define RTC_BKP13R_Msk (0xFFFFFFFFUL << RTC_BKP13R_Pos)

0xFFFFFFFF

◆ RTC_BKP13R_Pos

#define RTC_BKP13R_Pos (0U)

◆ RTC_BKP14R

#define RTC_BKP14R RTC_BKP14R_Msk

◆ RTC_BKP14R_Msk

#define RTC_BKP14R_Msk (0xFFFFFFFFUL << RTC_BKP14R_Pos)

0xFFFFFFFF

◆ RTC_BKP14R_Pos

#define RTC_BKP14R_Pos (0U)

◆ RTC_BKP15R

#define RTC_BKP15R RTC_BKP15R_Msk

◆ RTC_BKP15R_Msk

#define RTC_BKP15R_Msk (0xFFFFFFFFUL << RTC_BKP15R_Pos)

0xFFFFFFFF

◆ RTC_BKP15R_Pos

#define RTC_BKP15R_Pos (0U)

◆ RTC_BKP1R

#define RTC_BKP1R RTC_BKP1R_Msk

◆ RTC_BKP1R_Msk

#define RTC_BKP1R_Msk (0xFFFFFFFFUL << RTC_BKP1R_Pos)

0xFFFFFFFF

◆ RTC_BKP1R_Pos

#define RTC_BKP1R_Pos (0U)

◆ RTC_BKP2R

#define RTC_BKP2R RTC_BKP2R_Msk

◆ RTC_BKP2R_Msk

#define RTC_BKP2R_Msk (0xFFFFFFFFUL << RTC_BKP2R_Pos)

0xFFFFFFFF

◆ RTC_BKP2R_Pos

#define RTC_BKP2R_Pos (0U)

◆ RTC_BKP3R

#define RTC_BKP3R RTC_BKP3R_Msk

◆ RTC_BKP3R_Msk

#define RTC_BKP3R_Msk (0xFFFFFFFFUL << RTC_BKP3R_Pos)

0xFFFFFFFF

◆ RTC_BKP3R_Pos

#define RTC_BKP3R_Pos (0U)

◆ RTC_BKP4R

#define RTC_BKP4R RTC_BKP4R_Msk

◆ RTC_BKP4R_Msk

#define RTC_BKP4R_Msk (0xFFFFFFFFUL << RTC_BKP4R_Pos)

0xFFFFFFFF

◆ RTC_BKP4R_Pos

#define RTC_BKP4R_Pos (0U)

◆ RTC_BKP5R

#define RTC_BKP5R RTC_BKP5R_Msk

◆ RTC_BKP5R_Msk

#define RTC_BKP5R_Msk (0xFFFFFFFFUL << RTC_BKP5R_Pos)

0xFFFFFFFF

◆ RTC_BKP5R_Pos

#define RTC_BKP5R_Pos (0U)

◆ RTC_BKP6R

#define RTC_BKP6R RTC_BKP6R_Msk

◆ RTC_BKP6R_Msk

#define RTC_BKP6R_Msk (0xFFFFFFFFUL << RTC_BKP6R_Pos)

0xFFFFFFFF

◆ RTC_BKP6R_Pos

#define RTC_BKP6R_Pos (0U)

◆ RTC_BKP7R

#define RTC_BKP7R RTC_BKP7R_Msk

◆ RTC_BKP7R_Msk

#define RTC_BKP7R_Msk (0xFFFFFFFFUL << RTC_BKP7R_Pos)

0xFFFFFFFF

◆ RTC_BKP7R_Pos

#define RTC_BKP7R_Pos (0U)

◆ RTC_BKP8R

#define RTC_BKP8R RTC_BKP8R_Msk

◆ RTC_BKP8R_Msk

#define RTC_BKP8R_Msk (0xFFFFFFFFUL << RTC_BKP8R_Pos)

0xFFFFFFFF

◆ RTC_BKP8R_Pos

#define RTC_BKP8R_Pos (0U)

◆ RTC_BKP9R

#define RTC_BKP9R RTC_BKP9R_Msk

◆ RTC_BKP9R_Msk

#define RTC_BKP9R_Msk (0xFFFFFFFFUL << RTC_BKP9R_Pos)

0xFFFFFFFF

◆ RTC_BKP9R_Pos

#define RTC_BKP9R_Pos (0U)

◆ RTC_BKP_NUMBER

#define RTC_BKP_NUMBER 16

◆ RTC_CALR_CALM

#define RTC_CALR_CALM RTC_CALR_CALM_Msk

◆ RTC_CALR_CALM_0

#define RTC_CALR_CALM_0 (0x001UL << RTC_CALR_CALM_Pos)

0x00000001

◆ RTC_CALR_CALM_1

#define RTC_CALR_CALM_1 (0x002UL << RTC_CALR_CALM_Pos)

0x00000002

◆ RTC_CALR_CALM_2

#define RTC_CALR_CALM_2 (0x004UL << RTC_CALR_CALM_Pos)

0x00000004

◆ RTC_CALR_CALM_3

#define RTC_CALR_CALM_3 (0x008UL << RTC_CALR_CALM_Pos)

0x00000008

◆ RTC_CALR_CALM_4

#define RTC_CALR_CALM_4 (0x010UL << RTC_CALR_CALM_Pos)

0x00000010

◆ RTC_CALR_CALM_5

#define RTC_CALR_CALM_5 (0x020UL << RTC_CALR_CALM_Pos)

0x00000020

◆ RTC_CALR_CALM_6

#define RTC_CALR_CALM_6 (0x040UL << RTC_CALR_CALM_Pos)

0x00000040

◆ RTC_CALR_CALM_7

#define RTC_CALR_CALM_7 (0x080UL << RTC_CALR_CALM_Pos)

0x00000080

◆ RTC_CALR_CALM_8

#define RTC_CALR_CALM_8 (0x100UL << RTC_CALR_CALM_Pos)

0x00000100

◆ RTC_CALR_CALM_Msk

#define RTC_CALR_CALM_Msk (0x1FFUL << RTC_CALR_CALM_Pos)

0x000001FF

◆ RTC_CALR_CALM_Pos

#define RTC_CALR_CALM_Pos (0U)

◆ RTC_CALR_CALP

#define RTC_CALR_CALP RTC_CALR_CALP_Msk

◆ RTC_CALR_CALP_Msk

#define RTC_CALR_CALP_Msk (0x1UL << RTC_CALR_CALP_Pos)

0x00008000

◆ RTC_CALR_CALP_Pos

#define RTC_CALR_CALP_Pos (15U)

◆ RTC_CALR_CALW16

#define RTC_CALR_CALW16 RTC_CALR_CALW16_Msk

◆ RTC_CALR_CALW16_Msk

#define RTC_CALR_CALW16_Msk (0x1UL << RTC_CALR_CALW16_Pos)

0x00002000

◆ RTC_CALR_CALW16_Pos

#define RTC_CALR_CALW16_Pos (13U)

◆ RTC_CALR_CALW8

#define RTC_CALR_CALW8 RTC_CALR_CALW8_Msk

◆ RTC_CALR_CALW8_Msk

#define RTC_CALR_CALW8_Msk (0x1UL << RTC_CALR_CALW8_Pos)

0x00004000

◆ RTC_CALR_CALW8_Pos

#define RTC_CALR_CALW8_Pos (14U)

◆ RTC_CR_ADD1H

#define RTC_CR_ADD1H RTC_CR_ADD1H_Msk

◆ RTC_CR_ADD1H_Msk

#define RTC_CR_ADD1H_Msk (0x1UL << RTC_CR_ADD1H_Pos)

0x00010000

◆ RTC_CR_ADD1H_Pos

#define RTC_CR_ADD1H_Pos (16U)

◆ RTC_CR_ALRAE

#define RTC_CR_ALRAE RTC_CR_ALRAE_Msk

◆ RTC_CR_ALRAE_Msk

#define RTC_CR_ALRAE_Msk (0x1UL << RTC_CR_ALRAE_Pos)

0x00000100

◆ RTC_CR_ALRAE_Pos

#define RTC_CR_ALRAE_Pos (8U)

◆ RTC_CR_ALRAIE

#define RTC_CR_ALRAIE RTC_CR_ALRAIE_Msk

◆ RTC_CR_ALRAIE_Msk

#define RTC_CR_ALRAIE_Msk (0x1UL << RTC_CR_ALRAIE_Pos)

0x00001000

◆ RTC_CR_ALRAIE_Pos

#define RTC_CR_ALRAIE_Pos (12U)

◆ RTC_CR_ALRBE

#define RTC_CR_ALRBE RTC_CR_ALRBE_Msk

◆ RTC_CR_ALRBE_Msk

#define RTC_CR_ALRBE_Msk (0x1UL << RTC_CR_ALRBE_Pos)

0x00000200

◆ RTC_CR_ALRBE_Pos

#define RTC_CR_ALRBE_Pos (9U)

◆ RTC_CR_ALRBIE

#define RTC_CR_ALRBIE RTC_CR_ALRBIE_Msk

◆ RTC_CR_ALRBIE_Msk

#define RTC_CR_ALRBIE_Msk (0x1UL << RTC_CR_ALRBIE_Pos)

0x00002000

◆ RTC_CR_ALRBIE_Pos

#define RTC_CR_ALRBIE_Pos (13U)

◆ RTC_CR_BCK

#define RTC_CR_BCK RTC_CR_BKP

◆ RTC_CR_BCK_Msk

#define RTC_CR_BCK_Msk RTC_CR_BKP_Msk

◆ RTC_CR_BCK_Pos

#define RTC_CR_BCK_Pos RTC_CR_BKP_Pos

◆ RTC_CR_BKP

#define RTC_CR_BKP RTC_CR_BKP_Msk

◆ RTC_CR_BKP_Msk

#define RTC_CR_BKP_Msk (0x1UL << RTC_CR_BKP_Pos)

0x00040000

◆ RTC_CR_BKP_Pos

#define RTC_CR_BKP_Pos (18U)

◆ RTC_CR_BYPSHAD

#define RTC_CR_BYPSHAD RTC_CR_BYPSHAD_Msk

◆ RTC_CR_BYPSHAD_Msk

#define RTC_CR_BYPSHAD_Msk (0x1UL << RTC_CR_BYPSHAD_Pos)

0x00000020

◆ RTC_CR_BYPSHAD_Pos

#define RTC_CR_BYPSHAD_Pos (5U)

◆ RTC_CR_COE

#define RTC_CR_COE RTC_CR_COE_Msk

◆ RTC_CR_COE_Msk

#define RTC_CR_COE_Msk (0x1UL << RTC_CR_COE_Pos)

0x00800000

◆ RTC_CR_COE_Pos

#define RTC_CR_COE_Pos (23U)

◆ RTC_CR_COSEL

#define RTC_CR_COSEL RTC_CR_COSEL_Msk

◆ RTC_CR_COSEL_Msk

#define RTC_CR_COSEL_Msk (0x1UL << RTC_CR_COSEL_Pos)

0x00080000

◆ RTC_CR_COSEL_Pos

#define RTC_CR_COSEL_Pos (19U)

◆ RTC_CR_FMT

#define RTC_CR_FMT RTC_CR_FMT_Msk

◆ RTC_CR_FMT_Msk

#define RTC_CR_FMT_Msk (0x1UL << RTC_CR_FMT_Pos)

0x00000040

◆ RTC_CR_FMT_Pos

#define RTC_CR_FMT_Pos (6U)

◆ RTC_CR_OSEL

#define RTC_CR_OSEL RTC_CR_OSEL_Msk

◆ RTC_CR_OSEL_0

#define RTC_CR_OSEL_0 (0x1UL << RTC_CR_OSEL_Pos)

0x00200000

◆ RTC_CR_OSEL_1

#define RTC_CR_OSEL_1 (0x2UL << RTC_CR_OSEL_Pos)

0x00400000

◆ RTC_CR_OSEL_Msk

#define RTC_CR_OSEL_Msk (0x3UL << RTC_CR_OSEL_Pos)

0x00600000

◆ RTC_CR_OSEL_Pos

#define RTC_CR_OSEL_Pos (21U)

◆ RTC_CR_POL

#define RTC_CR_POL RTC_CR_POL_Msk

◆ RTC_CR_POL_Msk

#define RTC_CR_POL_Msk (0x1UL << RTC_CR_POL_Pos)

0x00100000

◆ RTC_CR_POL_Pos

#define RTC_CR_POL_Pos (20U)

◆ RTC_CR_REFCKON

#define RTC_CR_REFCKON RTC_CR_REFCKON_Msk

◆ RTC_CR_REFCKON_Msk

#define RTC_CR_REFCKON_Msk (0x1UL << RTC_CR_REFCKON_Pos)

0x00000010

◆ RTC_CR_REFCKON_Pos

#define RTC_CR_REFCKON_Pos (4U)

◆ RTC_CR_SUB1H

#define RTC_CR_SUB1H RTC_CR_SUB1H_Msk

◆ RTC_CR_SUB1H_Msk

#define RTC_CR_SUB1H_Msk (0x1UL << RTC_CR_SUB1H_Pos)

0x00020000

◆ RTC_CR_SUB1H_Pos

#define RTC_CR_SUB1H_Pos (17U)

◆ RTC_CR_TSE

#define RTC_CR_TSE RTC_CR_TSE_Msk

◆ RTC_CR_TSE_Msk

#define RTC_CR_TSE_Msk (0x1UL << RTC_CR_TSE_Pos)

0x00000800

◆ RTC_CR_TSE_Pos

#define RTC_CR_TSE_Pos (11U)

◆ RTC_CR_TSEDGE

#define RTC_CR_TSEDGE RTC_CR_TSEDGE_Msk

◆ RTC_CR_TSEDGE_Msk

#define RTC_CR_TSEDGE_Msk (0x1UL << RTC_CR_TSEDGE_Pos)

0x00000008

◆ RTC_CR_TSEDGE_Pos

#define RTC_CR_TSEDGE_Pos (3U)

◆ RTC_CR_TSIE

#define RTC_CR_TSIE RTC_CR_TSIE_Msk

◆ RTC_CR_TSIE_Msk

#define RTC_CR_TSIE_Msk (0x1UL << RTC_CR_TSIE_Pos)

0x00008000

◆ RTC_CR_TSIE_Pos

#define RTC_CR_TSIE_Pos (15U)

◆ RTC_CR_WUCKSEL

#define RTC_CR_WUCKSEL RTC_CR_WUCKSEL_Msk

◆ RTC_CR_WUCKSEL_0

#define RTC_CR_WUCKSEL_0 (0x1UL << RTC_CR_WUCKSEL_Pos)

0x00000001

◆ RTC_CR_WUCKSEL_1

#define RTC_CR_WUCKSEL_1 (0x2UL << RTC_CR_WUCKSEL_Pos)

0x00000002

◆ RTC_CR_WUCKSEL_2

#define RTC_CR_WUCKSEL_2 (0x4UL << RTC_CR_WUCKSEL_Pos)

0x00000004

◆ RTC_CR_WUCKSEL_Msk

#define RTC_CR_WUCKSEL_Msk (0x7UL << RTC_CR_WUCKSEL_Pos)

0x00000007

◆ RTC_CR_WUCKSEL_Pos

#define RTC_CR_WUCKSEL_Pos (0U)

◆ RTC_CR_WUTE

#define RTC_CR_WUTE RTC_CR_WUTE_Msk

◆ RTC_CR_WUTE_Msk

#define RTC_CR_WUTE_Msk (0x1UL << RTC_CR_WUTE_Pos)

0x00000400

◆ RTC_CR_WUTE_Pos

#define RTC_CR_WUTE_Pos (10U)

◆ RTC_CR_WUTIE

#define RTC_CR_WUTIE RTC_CR_WUTIE_Msk

◆ RTC_CR_WUTIE_Msk

#define RTC_CR_WUTIE_Msk (0x1UL << RTC_CR_WUTIE_Pos)

0x00004000

◆ RTC_CR_WUTIE_Pos

#define RTC_CR_WUTIE_Pos (14U)

◆ RTC_DR_DT

#define RTC_DR_DT RTC_DR_DT_Msk

◆ RTC_DR_DT_0

#define RTC_DR_DT_0 (0x1UL << RTC_DR_DT_Pos)

0x00000010

◆ RTC_DR_DT_1

#define RTC_DR_DT_1 (0x2UL << RTC_DR_DT_Pos)

0x00000020

◆ RTC_DR_DT_Msk

#define RTC_DR_DT_Msk (0x3UL << RTC_DR_DT_Pos)

0x00000030

◆ RTC_DR_DT_Pos

#define RTC_DR_DT_Pos (4U)

◆ RTC_DR_DU

#define RTC_DR_DU RTC_DR_DU_Msk

◆ RTC_DR_DU_0

#define RTC_DR_DU_0 (0x1UL << RTC_DR_DU_Pos)

0x00000001

◆ RTC_DR_DU_1

#define RTC_DR_DU_1 (0x2UL << RTC_DR_DU_Pos)

0x00000002

◆ RTC_DR_DU_2

#define RTC_DR_DU_2 (0x4UL << RTC_DR_DU_Pos)

0x00000004

◆ RTC_DR_DU_3

#define RTC_DR_DU_3 (0x8UL << RTC_DR_DU_Pos)

0x00000008

◆ RTC_DR_DU_Msk

#define RTC_DR_DU_Msk (0xFUL << RTC_DR_DU_Pos)

0x0000000F

◆ RTC_DR_DU_Pos

#define RTC_DR_DU_Pos (0U)

◆ RTC_DR_MT

#define RTC_DR_MT RTC_DR_MT_Msk

◆ RTC_DR_MT_Msk

#define RTC_DR_MT_Msk (0x1UL << RTC_DR_MT_Pos)

0x00001000

◆ RTC_DR_MT_Pos

#define RTC_DR_MT_Pos (12U)

◆ RTC_DR_MU

#define RTC_DR_MU RTC_DR_MU_Msk

◆ RTC_DR_MU_0

#define RTC_DR_MU_0 (0x1UL << RTC_DR_MU_Pos)

0x00000100

◆ RTC_DR_MU_1

#define RTC_DR_MU_1 (0x2UL << RTC_DR_MU_Pos)

0x00000200

◆ RTC_DR_MU_2

#define RTC_DR_MU_2 (0x4UL << RTC_DR_MU_Pos)

0x00000400

◆ RTC_DR_MU_3

#define RTC_DR_MU_3 (0x8UL << RTC_DR_MU_Pos)

0x00000800

◆ RTC_DR_MU_Msk

#define RTC_DR_MU_Msk (0xFUL << RTC_DR_MU_Pos)

0x00000F00

◆ RTC_DR_MU_Pos

#define RTC_DR_MU_Pos (8U)

◆ RTC_DR_WDU

#define RTC_DR_WDU RTC_DR_WDU_Msk

◆ RTC_DR_WDU_0

#define RTC_DR_WDU_0 (0x1UL << RTC_DR_WDU_Pos)

0x00002000

◆ RTC_DR_WDU_1

#define RTC_DR_WDU_1 (0x2UL << RTC_DR_WDU_Pos)

0x00004000

◆ RTC_DR_WDU_2

#define RTC_DR_WDU_2 (0x4UL << RTC_DR_WDU_Pos)

0x00008000

◆ RTC_DR_WDU_Msk

#define RTC_DR_WDU_Msk (0x7UL << RTC_DR_WDU_Pos)

0x0000E000

◆ RTC_DR_WDU_Pos

#define RTC_DR_WDU_Pos (13U)

◆ RTC_DR_YT

#define RTC_DR_YT RTC_DR_YT_Msk

◆ RTC_DR_YT_0

#define RTC_DR_YT_0 (0x1UL << RTC_DR_YT_Pos)

0x00100000

◆ RTC_DR_YT_1

#define RTC_DR_YT_1 (0x2UL << RTC_DR_YT_Pos)

0x00200000

◆ RTC_DR_YT_2

#define RTC_DR_YT_2 (0x4UL << RTC_DR_YT_Pos)

0x00400000

◆ RTC_DR_YT_3

#define RTC_DR_YT_3 (0x8UL << RTC_DR_YT_Pos)

0x00800000

◆ RTC_DR_YT_Msk

#define RTC_DR_YT_Msk (0xFUL << RTC_DR_YT_Pos)

0x00F00000

◆ RTC_DR_YT_Pos

#define RTC_DR_YT_Pos (20U)

◆ RTC_DR_YU

#define RTC_DR_YU RTC_DR_YU_Msk

◆ RTC_DR_YU_0

#define RTC_DR_YU_0 (0x1UL << RTC_DR_YU_Pos)

0x00010000

◆ RTC_DR_YU_1

#define RTC_DR_YU_1 (0x2UL << RTC_DR_YU_Pos)

0x00020000

◆ RTC_DR_YU_2

#define RTC_DR_YU_2 (0x4UL << RTC_DR_YU_Pos)

0x00040000

◆ RTC_DR_YU_3

#define RTC_DR_YU_3 (0x8UL << RTC_DR_YU_Pos)

0x00080000

◆ RTC_DR_YU_Msk

#define RTC_DR_YU_Msk (0xFUL << RTC_DR_YU_Pos)

0x000F0000

◆ RTC_DR_YU_Pos

#define RTC_DR_YU_Pos (16U)

◆ RTC_ISR_ALRAF

#define RTC_ISR_ALRAF RTC_ISR_ALRAF_Msk

◆ RTC_ISR_ALRAF_Msk

#define RTC_ISR_ALRAF_Msk (0x1UL << RTC_ISR_ALRAF_Pos)

0x00000100

◆ RTC_ISR_ALRAF_Pos

#define RTC_ISR_ALRAF_Pos (8U)

◆ RTC_ISR_ALRAWF

#define RTC_ISR_ALRAWF RTC_ISR_ALRAWF_Msk

◆ RTC_ISR_ALRAWF_Msk

#define RTC_ISR_ALRAWF_Msk (0x1UL << RTC_ISR_ALRAWF_Pos)

0x00000001

◆ RTC_ISR_ALRAWF_Pos

#define RTC_ISR_ALRAWF_Pos (0U)

◆ RTC_ISR_ALRBF

#define RTC_ISR_ALRBF RTC_ISR_ALRBF_Msk

◆ RTC_ISR_ALRBF_Msk

#define RTC_ISR_ALRBF_Msk (0x1UL << RTC_ISR_ALRBF_Pos)

0x00000200

◆ RTC_ISR_ALRBF_Pos

#define RTC_ISR_ALRBF_Pos (9U)

◆ RTC_ISR_ALRBWF

#define RTC_ISR_ALRBWF RTC_ISR_ALRBWF_Msk

◆ RTC_ISR_ALRBWF_Msk

#define RTC_ISR_ALRBWF_Msk (0x1UL << RTC_ISR_ALRBWF_Pos)

0x00000002

◆ RTC_ISR_ALRBWF_Pos

#define RTC_ISR_ALRBWF_Pos (1U)

◆ RTC_ISR_INIT

#define RTC_ISR_INIT RTC_ISR_INIT_Msk

◆ RTC_ISR_INIT_Msk

#define RTC_ISR_INIT_Msk (0x1UL << RTC_ISR_INIT_Pos)

0x00000080

◆ RTC_ISR_INIT_Pos

#define RTC_ISR_INIT_Pos (7U)

◆ RTC_ISR_INITF

#define RTC_ISR_INITF RTC_ISR_INITF_Msk

◆ RTC_ISR_INITF_Msk

#define RTC_ISR_INITF_Msk (0x1UL << RTC_ISR_INITF_Pos)

0x00000040

◆ RTC_ISR_INITF_Pos

#define RTC_ISR_INITF_Pos (6U)

◆ RTC_ISR_INITS

#define RTC_ISR_INITS RTC_ISR_INITS_Msk

◆ RTC_ISR_INITS_Msk

#define RTC_ISR_INITS_Msk (0x1UL << RTC_ISR_INITS_Pos)

0x00000010

◆ RTC_ISR_INITS_Pos

#define RTC_ISR_INITS_Pos (4U)

◆ RTC_ISR_RECALPF

#define RTC_ISR_RECALPF RTC_ISR_RECALPF_Msk

◆ RTC_ISR_RECALPF_Msk

#define RTC_ISR_RECALPF_Msk (0x1UL << RTC_ISR_RECALPF_Pos)

0x00010000

◆ RTC_ISR_RECALPF_Pos

#define RTC_ISR_RECALPF_Pos (16U)

◆ RTC_ISR_RSF

#define RTC_ISR_RSF RTC_ISR_RSF_Msk

◆ RTC_ISR_RSF_Msk

#define RTC_ISR_RSF_Msk (0x1UL << RTC_ISR_RSF_Pos)

0x00000020

◆ RTC_ISR_RSF_Pos

#define RTC_ISR_RSF_Pos (5U)

◆ RTC_ISR_SHPF

#define RTC_ISR_SHPF RTC_ISR_SHPF_Msk

◆ RTC_ISR_SHPF_Msk

#define RTC_ISR_SHPF_Msk (0x1UL << RTC_ISR_SHPF_Pos)

0x00000008

◆ RTC_ISR_SHPF_Pos

#define RTC_ISR_SHPF_Pos (3U)

◆ RTC_ISR_TAMP1F

#define RTC_ISR_TAMP1F RTC_ISR_TAMP1F_Msk

◆ RTC_ISR_TAMP1F_Msk

#define RTC_ISR_TAMP1F_Msk (0x1UL << RTC_ISR_TAMP1F_Pos)

0x00002000

◆ RTC_ISR_TAMP1F_Pos

#define RTC_ISR_TAMP1F_Pos (13U)

◆ RTC_ISR_TAMP2F

#define RTC_ISR_TAMP2F RTC_ISR_TAMP2F_Msk

◆ RTC_ISR_TAMP2F_Msk

#define RTC_ISR_TAMP2F_Msk (0x1UL << RTC_ISR_TAMP2F_Pos)

0x00004000

◆ RTC_ISR_TAMP2F_Pos

#define RTC_ISR_TAMP2F_Pos (14U)

◆ RTC_ISR_TAMP3F

#define RTC_ISR_TAMP3F RTC_ISR_TAMP3F_Msk

◆ RTC_ISR_TAMP3F_Msk

#define RTC_ISR_TAMP3F_Msk (0x1UL << RTC_ISR_TAMP3F_Pos)

0x00008000

◆ RTC_ISR_TAMP3F_Pos

#define RTC_ISR_TAMP3F_Pos (15U)

◆ RTC_ISR_TSF

#define RTC_ISR_TSF RTC_ISR_TSF_Msk

◆ RTC_ISR_TSF_Msk

#define RTC_ISR_TSF_Msk (0x1UL << RTC_ISR_TSF_Pos)

0x00000800

◆ RTC_ISR_TSF_Pos

#define RTC_ISR_TSF_Pos (11U)

◆ RTC_ISR_TSOVF

#define RTC_ISR_TSOVF RTC_ISR_TSOVF_Msk

◆ RTC_ISR_TSOVF_Msk

#define RTC_ISR_TSOVF_Msk (0x1UL << RTC_ISR_TSOVF_Pos)

0x00001000

◆ RTC_ISR_TSOVF_Pos

#define RTC_ISR_TSOVF_Pos (12U)

◆ RTC_ISR_WUTF

#define RTC_ISR_WUTF RTC_ISR_WUTF_Msk

◆ RTC_ISR_WUTF_Msk

#define RTC_ISR_WUTF_Msk (0x1UL << RTC_ISR_WUTF_Pos)

0x00000400

◆ RTC_ISR_WUTF_Pos

#define RTC_ISR_WUTF_Pos (10U)

◆ RTC_ISR_WUTWF

#define RTC_ISR_WUTWF RTC_ISR_WUTWF_Msk

◆ RTC_ISR_WUTWF_Msk

#define RTC_ISR_WUTWF_Msk (0x1UL << RTC_ISR_WUTWF_Pos)

0x00000004

◆ RTC_ISR_WUTWF_Pos

#define RTC_ISR_WUTWF_Pos (2U)

◆ RTC_PRER_PREDIV_A

#define RTC_PRER_PREDIV_A RTC_PRER_PREDIV_A_Msk

◆ RTC_PRER_PREDIV_A_Msk

#define RTC_PRER_PREDIV_A_Msk (0x7FUL << RTC_PRER_PREDIV_A_Pos)

0x007F0000

◆ RTC_PRER_PREDIV_A_Pos

#define RTC_PRER_PREDIV_A_Pos (16U)

◆ RTC_PRER_PREDIV_S

#define RTC_PRER_PREDIV_S RTC_PRER_PREDIV_S_Msk

◆ RTC_PRER_PREDIV_S_Msk

#define RTC_PRER_PREDIV_S_Msk (0x7FFFUL << RTC_PRER_PREDIV_S_Pos)

0x00007FFF

◆ RTC_PRER_PREDIV_S_Pos

#define RTC_PRER_PREDIV_S_Pos (0U)

◆ RTC_SHIFTR_ADD1S

#define RTC_SHIFTR_ADD1S RTC_SHIFTR_ADD1S_Msk

◆ RTC_SHIFTR_ADD1S_Msk

#define RTC_SHIFTR_ADD1S_Msk (0x1UL << RTC_SHIFTR_ADD1S_Pos)

0x80000000

◆ RTC_SHIFTR_ADD1S_Pos

#define RTC_SHIFTR_ADD1S_Pos (31U)

◆ RTC_SHIFTR_SUBFS

#define RTC_SHIFTR_SUBFS RTC_SHIFTR_SUBFS_Msk

◆ RTC_SHIFTR_SUBFS_Msk

#define RTC_SHIFTR_SUBFS_Msk (0x7FFFUL << RTC_SHIFTR_SUBFS_Pos)

0x00007FFF

◆ RTC_SHIFTR_SUBFS_Pos

#define RTC_SHIFTR_SUBFS_Pos (0U)

◆ RTC_SSR_SS

#define RTC_SSR_SS RTC_SSR_SS_Msk

◆ RTC_SSR_SS_Msk

#define RTC_SSR_SS_Msk (0xFFFFUL << RTC_SSR_SS_Pos)

0x0000FFFF

◆ RTC_SSR_SS_Pos

#define RTC_SSR_SS_Pos (0U)

◆ RTC_TAFCR_ALARMOUTTYPE

#define RTC_TAFCR_ALARMOUTTYPE RTC_TAFCR_PC13VALUE

◆ RTC_TAFCR_PC13MODE

#define RTC_TAFCR_PC13MODE RTC_TAFCR_PC13MODE_Msk

◆ RTC_TAFCR_PC13MODE_Msk

#define RTC_TAFCR_PC13MODE_Msk (0x1UL << RTC_TAFCR_PC13MODE_Pos)

0x00080000

◆ RTC_TAFCR_PC13MODE_Pos

#define RTC_TAFCR_PC13MODE_Pos (19U)

◆ RTC_TAFCR_PC13VALUE

#define RTC_TAFCR_PC13VALUE RTC_TAFCR_PC13VALUE_Msk

◆ RTC_TAFCR_PC13VALUE_Msk

#define RTC_TAFCR_PC13VALUE_Msk (0x1UL << RTC_TAFCR_PC13VALUE_Pos)

0x00040000

◆ RTC_TAFCR_PC13VALUE_Pos

#define RTC_TAFCR_PC13VALUE_Pos (18U)

◆ RTC_TAFCR_PC14MODE

#define RTC_TAFCR_PC14MODE RTC_TAFCR_PC14MODE_Msk

◆ RTC_TAFCR_PC14MODE_Msk

#define RTC_TAFCR_PC14MODE_Msk (0x1UL << RTC_TAFCR_PC14MODE_Pos)

0x00200000

◆ RTC_TAFCR_PC14MODE_Pos

#define RTC_TAFCR_PC14MODE_Pos (21U)

◆ RTC_TAFCR_PC14VALUE

#define RTC_TAFCR_PC14VALUE RTC_TAFCR_PC14VALUE_Msk

◆ RTC_TAFCR_PC14VALUE_Msk

#define RTC_TAFCR_PC14VALUE_Msk (0x1UL << RTC_TAFCR_PC14VALUE_Pos)

0x00100000

◆ RTC_TAFCR_PC14VALUE_Pos

#define RTC_TAFCR_PC14VALUE_Pos (20U)

◆ RTC_TAFCR_PC15MODE

#define RTC_TAFCR_PC15MODE RTC_TAFCR_PC15MODE_Msk

◆ RTC_TAFCR_PC15MODE_Msk

#define RTC_TAFCR_PC15MODE_Msk (0x1UL << RTC_TAFCR_PC15MODE_Pos)

0x00800000

◆ RTC_TAFCR_PC15MODE_Pos

#define RTC_TAFCR_PC15MODE_Pos (23U)

◆ RTC_TAFCR_PC15VALUE

#define RTC_TAFCR_PC15VALUE RTC_TAFCR_PC15VALUE_Msk

◆ RTC_TAFCR_PC15VALUE_Msk

#define RTC_TAFCR_PC15VALUE_Msk (0x1UL << RTC_TAFCR_PC15VALUE_Pos)

0x00400000

◆ RTC_TAFCR_PC15VALUE_Pos

#define RTC_TAFCR_PC15VALUE_Pos (22U)

◆ RTC_TAFCR_TAMP1E

#define RTC_TAFCR_TAMP1E RTC_TAFCR_TAMP1E_Msk

◆ RTC_TAFCR_TAMP1E_Msk

#define RTC_TAFCR_TAMP1E_Msk (0x1UL << RTC_TAFCR_TAMP1E_Pos)

0x00000001

◆ RTC_TAFCR_TAMP1E_Pos

#define RTC_TAFCR_TAMP1E_Pos (0U)

◆ RTC_TAFCR_TAMP1TRG

#define RTC_TAFCR_TAMP1TRG RTC_TAFCR_TAMP1TRG_Msk

◆ RTC_TAFCR_TAMP1TRG_Msk

#define RTC_TAFCR_TAMP1TRG_Msk (0x1UL << RTC_TAFCR_TAMP1TRG_Pos)

0x00000002

◆ RTC_TAFCR_TAMP1TRG_Pos

#define RTC_TAFCR_TAMP1TRG_Pos (1U)

◆ RTC_TAFCR_TAMP2E

#define RTC_TAFCR_TAMP2E RTC_TAFCR_TAMP2E_Msk

◆ RTC_TAFCR_TAMP2E_Msk

#define RTC_TAFCR_TAMP2E_Msk (0x1UL << RTC_TAFCR_TAMP2E_Pos)

0x00000008

◆ RTC_TAFCR_TAMP2E_Pos

#define RTC_TAFCR_TAMP2E_Pos (3U)

◆ RTC_TAFCR_TAMP2TRG

#define RTC_TAFCR_TAMP2TRG RTC_TAFCR_TAMP2TRG_Msk

◆ RTC_TAFCR_TAMP2TRG_Msk

#define RTC_TAFCR_TAMP2TRG_Msk (0x1UL << RTC_TAFCR_TAMP2TRG_Pos)

0x00000010

◆ RTC_TAFCR_TAMP2TRG_Pos

#define RTC_TAFCR_TAMP2TRG_Pos (4U)

◆ RTC_TAFCR_TAMP3E

#define RTC_TAFCR_TAMP3E RTC_TAFCR_TAMP3E_Msk

◆ RTC_TAFCR_TAMP3E_Msk

#define RTC_TAFCR_TAMP3E_Msk (0x1UL << RTC_TAFCR_TAMP3E_Pos)

0x00000020

◆ RTC_TAFCR_TAMP3E_Pos

#define RTC_TAFCR_TAMP3E_Pos (5U)

◆ RTC_TAFCR_TAMP3TRG

#define RTC_TAFCR_TAMP3TRG RTC_TAFCR_TAMP3TRG_Msk

◆ RTC_TAFCR_TAMP3TRG_Msk

#define RTC_TAFCR_TAMP3TRG_Msk (0x1UL << RTC_TAFCR_TAMP3TRG_Pos)

0x00000040

◆ RTC_TAFCR_TAMP3TRG_Pos

#define RTC_TAFCR_TAMP3TRG_Pos (6U)

◆ RTC_TAFCR_TAMPFLT

#define RTC_TAFCR_TAMPFLT RTC_TAFCR_TAMPFLT_Msk

◆ RTC_TAFCR_TAMPFLT_0

#define RTC_TAFCR_TAMPFLT_0 (0x1UL << RTC_TAFCR_TAMPFLT_Pos)

0x00000800

◆ RTC_TAFCR_TAMPFLT_1

#define RTC_TAFCR_TAMPFLT_1 (0x2UL << RTC_TAFCR_TAMPFLT_Pos)

0x00001000

◆ RTC_TAFCR_TAMPFLT_Msk

#define RTC_TAFCR_TAMPFLT_Msk (0x3UL << RTC_TAFCR_TAMPFLT_Pos)

0x00001800

◆ RTC_TAFCR_TAMPFLT_Pos

#define RTC_TAFCR_TAMPFLT_Pos (11U)

◆ RTC_TAFCR_TAMPFREQ

#define RTC_TAFCR_TAMPFREQ RTC_TAFCR_TAMPFREQ_Msk

◆ RTC_TAFCR_TAMPFREQ_0

#define RTC_TAFCR_TAMPFREQ_0 (0x1UL << RTC_TAFCR_TAMPFREQ_Pos)

0x00000100

◆ RTC_TAFCR_TAMPFREQ_1

#define RTC_TAFCR_TAMPFREQ_1 (0x2UL << RTC_TAFCR_TAMPFREQ_Pos)

0x00000200

◆ RTC_TAFCR_TAMPFREQ_2

#define RTC_TAFCR_TAMPFREQ_2 (0x4UL << RTC_TAFCR_TAMPFREQ_Pos)

0x00000400

◆ RTC_TAFCR_TAMPFREQ_Msk

#define RTC_TAFCR_TAMPFREQ_Msk (0x7UL << RTC_TAFCR_TAMPFREQ_Pos)

0x00000700

◆ RTC_TAFCR_TAMPFREQ_Pos

#define RTC_TAFCR_TAMPFREQ_Pos (8U)

◆ RTC_TAFCR_TAMPIE

#define RTC_TAFCR_TAMPIE RTC_TAFCR_TAMPIE_Msk

◆ RTC_TAFCR_TAMPIE_Msk

#define RTC_TAFCR_TAMPIE_Msk (0x1UL << RTC_TAFCR_TAMPIE_Pos)

0x00000004

◆ RTC_TAFCR_TAMPIE_Pos

#define RTC_TAFCR_TAMPIE_Pos (2U)

◆ RTC_TAFCR_TAMPPRCH

#define RTC_TAFCR_TAMPPRCH RTC_TAFCR_TAMPPRCH_Msk

◆ RTC_TAFCR_TAMPPRCH_0

#define RTC_TAFCR_TAMPPRCH_0 (0x1UL << RTC_TAFCR_TAMPPRCH_Pos)

0x00002000

◆ RTC_TAFCR_TAMPPRCH_1

#define RTC_TAFCR_TAMPPRCH_1 (0x2UL << RTC_TAFCR_TAMPPRCH_Pos)

0x00004000

◆ RTC_TAFCR_TAMPPRCH_Msk

#define RTC_TAFCR_TAMPPRCH_Msk (0x3UL << RTC_TAFCR_TAMPPRCH_Pos)

0x00006000

◆ RTC_TAFCR_TAMPPRCH_Pos

#define RTC_TAFCR_TAMPPRCH_Pos (13U)

◆ RTC_TAFCR_TAMPPUDIS

#define RTC_TAFCR_TAMPPUDIS RTC_TAFCR_TAMPPUDIS_Msk

◆ RTC_TAFCR_TAMPPUDIS_Msk

#define RTC_TAFCR_TAMPPUDIS_Msk (0x1UL << RTC_TAFCR_TAMPPUDIS_Pos)

0x00008000

◆ RTC_TAFCR_TAMPPUDIS_Pos

#define RTC_TAFCR_TAMPPUDIS_Pos (15U)

◆ RTC_TAFCR_TAMPTS

#define RTC_TAFCR_TAMPTS RTC_TAFCR_TAMPTS_Msk

◆ RTC_TAFCR_TAMPTS_Msk

#define RTC_TAFCR_TAMPTS_Msk (0x1UL << RTC_TAFCR_TAMPTS_Pos)

0x00000080

◆ RTC_TAFCR_TAMPTS_Pos

#define RTC_TAFCR_TAMPTS_Pos (7U)

◆ RTC_TAMPER1_SUPPORT

#define RTC_TAMPER1_SUPPORT

TAMPER 1 feature support

◆ RTC_TAMPER2_SUPPORT

#define RTC_TAMPER2_SUPPORT

TAMPER 2 feature support

◆ RTC_TAMPER3_SUPPORT

#define RTC_TAMPER3_SUPPORT

TAMPER 3 feature support

◆ RTC_TR_HT

#define RTC_TR_HT RTC_TR_HT_Msk

◆ RTC_TR_HT_0

#define RTC_TR_HT_0 (0x1UL << RTC_TR_HT_Pos)

0x00100000

◆ RTC_TR_HT_1

#define RTC_TR_HT_1 (0x2UL << RTC_TR_HT_Pos)

0x00200000

◆ RTC_TR_HT_Msk

#define RTC_TR_HT_Msk (0x3UL << RTC_TR_HT_Pos)

0x00300000

◆ RTC_TR_HT_Pos

#define RTC_TR_HT_Pos (20U)

◆ RTC_TR_HU

#define RTC_TR_HU RTC_TR_HU_Msk

◆ RTC_TR_HU_0

#define RTC_TR_HU_0 (0x1UL << RTC_TR_HU_Pos)

0x00010000

◆ RTC_TR_HU_1

#define RTC_TR_HU_1 (0x2UL << RTC_TR_HU_Pos)

0x00020000

◆ RTC_TR_HU_2

#define RTC_TR_HU_2 (0x4UL << RTC_TR_HU_Pos)

0x00040000

◆ RTC_TR_HU_3

#define RTC_TR_HU_3 (0x8UL << RTC_TR_HU_Pos)

0x00080000

◆ RTC_TR_HU_Msk

#define RTC_TR_HU_Msk (0xFUL << RTC_TR_HU_Pos)

0x000F0000

◆ RTC_TR_HU_Pos

#define RTC_TR_HU_Pos (16U)

◆ RTC_TR_MNT

#define RTC_TR_MNT RTC_TR_MNT_Msk

◆ RTC_TR_MNT_0

#define RTC_TR_MNT_0 (0x1UL << RTC_TR_MNT_Pos)

0x00001000

◆ RTC_TR_MNT_1

#define RTC_TR_MNT_1 (0x2UL << RTC_TR_MNT_Pos)

0x00002000

◆ RTC_TR_MNT_2

#define RTC_TR_MNT_2 (0x4UL << RTC_TR_MNT_Pos)

0x00004000

◆ RTC_TR_MNT_Msk

#define RTC_TR_MNT_Msk (0x7UL << RTC_TR_MNT_Pos)

0x00007000

◆ RTC_TR_MNT_Pos

#define RTC_TR_MNT_Pos (12U)

◆ RTC_TR_MNU

#define RTC_TR_MNU RTC_TR_MNU_Msk

◆ RTC_TR_MNU_0

#define RTC_TR_MNU_0 (0x1UL << RTC_TR_MNU_Pos)

0x00000100

◆ RTC_TR_MNU_1

#define RTC_TR_MNU_1 (0x2UL << RTC_TR_MNU_Pos)

0x00000200

◆ RTC_TR_MNU_2

#define RTC_TR_MNU_2 (0x4UL << RTC_TR_MNU_Pos)

0x00000400

◆ RTC_TR_MNU_3

#define RTC_TR_MNU_3 (0x8UL << RTC_TR_MNU_Pos)

0x00000800

◆ RTC_TR_MNU_Msk

#define RTC_TR_MNU_Msk (0xFUL << RTC_TR_MNU_Pos)

0x00000F00

◆ RTC_TR_MNU_Pos

#define RTC_TR_MNU_Pos (8U)

◆ RTC_TR_PM

#define RTC_TR_PM RTC_TR_PM_Msk

◆ RTC_TR_PM_Msk

#define RTC_TR_PM_Msk (0x1UL << RTC_TR_PM_Pos)

0x00400000

◆ RTC_TR_PM_Pos

#define RTC_TR_PM_Pos (22U)

◆ RTC_TR_ST

#define RTC_TR_ST RTC_TR_ST_Msk

◆ RTC_TR_ST_0

#define RTC_TR_ST_0 (0x1UL << RTC_TR_ST_Pos)

0x00000010

◆ RTC_TR_ST_1

#define RTC_TR_ST_1 (0x2UL << RTC_TR_ST_Pos)

0x00000020

◆ RTC_TR_ST_2

#define RTC_TR_ST_2 (0x4UL << RTC_TR_ST_Pos)

0x00000040

◆ RTC_TR_ST_Msk

#define RTC_TR_ST_Msk (0x7UL << RTC_TR_ST_Pos)

0x00000070

◆ RTC_TR_ST_Pos

#define RTC_TR_ST_Pos (4U)

◆ RTC_TR_SU

#define RTC_TR_SU RTC_TR_SU_Msk

◆ RTC_TR_SU_0

#define RTC_TR_SU_0 (0x1UL << RTC_TR_SU_Pos)

0x00000001

◆ RTC_TR_SU_1

#define RTC_TR_SU_1 (0x2UL << RTC_TR_SU_Pos)

0x00000002

◆ RTC_TR_SU_2

#define RTC_TR_SU_2 (0x4UL << RTC_TR_SU_Pos)

0x00000004

◆ RTC_TR_SU_3

#define RTC_TR_SU_3 (0x8UL << RTC_TR_SU_Pos)

0x00000008

◆ RTC_TR_SU_Msk

#define RTC_TR_SU_Msk (0xFUL << RTC_TR_SU_Pos)

0x0000000F

◆ RTC_TR_SU_Pos

#define RTC_TR_SU_Pos (0U)

◆ RTC_TSDR_DT

#define RTC_TSDR_DT RTC_TSDR_DT_Msk

◆ RTC_TSDR_DT_0

#define RTC_TSDR_DT_0 (0x1UL << RTC_TSDR_DT_Pos)

0x00000010

◆ RTC_TSDR_DT_1

#define RTC_TSDR_DT_1 (0x2UL << RTC_TSDR_DT_Pos)

0x00000020

◆ RTC_TSDR_DT_Msk

#define RTC_TSDR_DT_Msk (0x3UL << RTC_TSDR_DT_Pos)

0x00000030

◆ RTC_TSDR_DT_Pos

#define RTC_TSDR_DT_Pos (4U)

◆ RTC_TSDR_DU

#define RTC_TSDR_DU RTC_TSDR_DU_Msk

◆ RTC_TSDR_DU_0

#define RTC_TSDR_DU_0 (0x1UL << RTC_TSDR_DU_Pos)

0x00000001

◆ RTC_TSDR_DU_1

#define RTC_TSDR_DU_1 (0x2UL << RTC_TSDR_DU_Pos)

0x00000002

◆ RTC_TSDR_DU_2

#define RTC_TSDR_DU_2 (0x4UL << RTC_TSDR_DU_Pos)

0x00000004

◆ RTC_TSDR_DU_3

#define RTC_TSDR_DU_3 (0x8UL << RTC_TSDR_DU_Pos)

0x00000008

◆ RTC_TSDR_DU_Msk

#define RTC_TSDR_DU_Msk (0xFUL << RTC_TSDR_DU_Pos)

0x0000000F

◆ RTC_TSDR_DU_Pos

#define RTC_TSDR_DU_Pos (0U)

◆ RTC_TSDR_MT

#define RTC_TSDR_MT RTC_TSDR_MT_Msk

◆ RTC_TSDR_MT_Msk

#define RTC_TSDR_MT_Msk (0x1UL << RTC_TSDR_MT_Pos)

0x00001000

◆ RTC_TSDR_MT_Pos

#define RTC_TSDR_MT_Pos (12U)

◆ RTC_TSDR_MU

#define RTC_TSDR_MU RTC_TSDR_MU_Msk

◆ RTC_TSDR_MU_0

#define RTC_TSDR_MU_0 (0x1UL << RTC_TSDR_MU_Pos)

0x00000100

◆ RTC_TSDR_MU_1

#define RTC_TSDR_MU_1 (0x2UL << RTC_TSDR_MU_Pos)

0x00000200

◆ RTC_TSDR_MU_2

#define RTC_TSDR_MU_2 (0x4UL << RTC_TSDR_MU_Pos)

0x00000400

◆ RTC_TSDR_MU_3

#define RTC_TSDR_MU_3 (0x8UL << RTC_TSDR_MU_Pos)

0x00000800

◆ RTC_TSDR_MU_Msk

#define RTC_TSDR_MU_Msk (0xFUL << RTC_TSDR_MU_Pos)

0x00000F00

◆ RTC_TSDR_MU_Pos

#define RTC_TSDR_MU_Pos (8U)

◆ RTC_TSDR_WDU

#define RTC_TSDR_WDU RTC_TSDR_WDU_Msk

◆ RTC_TSDR_WDU_0

#define RTC_TSDR_WDU_0 (0x1UL << RTC_TSDR_WDU_Pos)

0x00002000

◆ RTC_TSDR_WDU_1

#define RTC_TSDR_WDU_1 (0x2UL << RTC_TSDR_WDU_Pos)

0x00004000

◆ RTC_TSDR_WDU_2

#define RTC_TSDR_WDU_2 (0x4UL << RTC_TSDR_WDU_Pos)

0x00008000

◆ RTC_TSDR_WDU_Msk

#define RTC_TSDR_WDU_Msk (0x7UL << RTC_TSDR_WDU_Pos)

0x0000E000

◆ RTC_TSDR_WDU_Pos

#define RTC_TSDR_WDU_Pos (13U)

◆ RTC_TSSSR_SS

#define RTC_TSSSR_SS RTC_TSSSR_SS_Msk

◆ RTC_TSSSR_SS_Msk

#define RTC_TSSSR_SS_Msk (0xFFFFUL << RTC_TSSSR_SS_Pos)

0x0000FFFF

◆ RTC_TSSSR_SS_Pos

#define RTC_TSSSR_SS_Pos (0U)

◆ RTC_TSTR_HT

#define RTC_TSTR_HT RTC_TSTR_HT_Msk

◆ RTC_TSTR_HT_0

#define RTC_TSTR_HT_0 (0x1UL << RTC_TSTR_HT_Pos)

0x00100000

◆ RTC_TSTR_HT_1

#define RTC_TSTR_HT_1 (0x2UL << RTC_TSTR_HT_Pos)

0x00200000

◆ RTC_TSTR_HT_Msk

#define RTC_TSTR_HT_Msk (0x3UL << RTC_TSTR_HT_Pos)

0x00300000

◆ RTC_TSTR_HT_Pos

#define RTC_TSTR_HT_Pos (20U)

◆ RTC_TSTR_HU

#define RTC_TSTR_HU RTC_TSTR_HU_Msk

◆ RTC_TSTR_HU_0

#define RTC_TSTR_HU_0 (0x1UL << RTC_TSTR_HU_Pos)

0x00010000

◆ RTC_TSTR_HU_1

#define RTC_TSTR_HU_1 (0x2UL << RTC_TSTR_HU_Pos)

0x00020000

◆ RTC_TSTR_HU_2

#define RTC_TSTR_HU_2 (0x4UL << RTC_TSTR_HU_Pos)

0x00040000

◆ RTC_TSTR_HU_3

#define RTC_TSTR_HU_3 (0x8UL << RTC_TSTR_HU_Pos)

0x00080000

◆ RTC_TSTR_HU_Msk

#define RTC_TSTR_HU_Msk (0xFUL << RTC_TSTR_HU_Pos)

0x000F0000

◆ RTC_TSTR_HU_Pos

#define RTC_TSTR_HU_Pos (16U)

◆ RTC_TSTR_MNT

#define RTC_TSTR_MNT RTC_TSTR_MNT_Msk

◆ RTC_TSTR_MNT_0

#define RTC_TSTR_MNT_0 (0x1UL << RTC_TSTR_MNT_Pos)

0x00001000

◆ RTC_TSTR_MNT_1

#define RTC_TSTR_MNT_1 (0x2UL << RTC_TSTR_MNT_Pos)

0x00002000

◆ RTC_TSTR_MNT_2

#define RTC_TSTR_MNT_2 (0x4UL << RTC_TSTR_MNT_Pos)

0x00004000

◆ RTC_TSTR_MNT_Msk

#define RTC_TSTR_MNT_Msk (0x7UL << RTC_TSTR_MNT_Pos)

0x00007000

◆ RTC_TSTR_MNT_Pos

#define RTC_TSTR_MNT_Pos (12U)

◆ RTC_TSTR_MNU

#define RTC_TSTR_MNU RTC_TSTR_MNU_Msk

◆ RTC_TSTR_MNU_0

#define RTC_TSTR_MNU_0 (0x1UL << RTC_TSTR_MNU_Pos)

0x00000100

◆ RTC_TSTR_MNU_1

#define RTC_TSTR_MNU_1 (0x2UL << RTC_TSTR_MNU_Pos)

0x00000200

◆ RTC_TSTR_MNU_2

#define RTC_TSTR_MNU_2 (0x4UL << RTC_TSTR_MNU_Pos)

0x00000400

◆ RTC_TSTR_MNU_3

#define RTC_TSTR_MNU_3 (0x8UL << RTC_TSTR_MNU_Pos)

0x00000800

◆ RTC_TSTR_MNU_Msk

#define RTC_TSTR_MNU_Msk (0xFUL << RTC_TSTR_MNU_Pos)

0x00000F00

◆ RTC_TSTR_MNU_Pos

#define RTC_TSTR_MNU_Pos (8U)

◆ RTC_TSTR_PM

#define RTC_TSTR_PM RTC_TSTR_PM_Msk

◆ RTC_TSTR_PM_Msk

#define RTC_TSTR_PM_Msk (0x1UL << RTC_TSTR_PM_Pos)

0x00400000

◆ RTC_TSTR_PM_Pos

#define RTC_TSTR_PM_Pos (22U)

◆ RTC_TSTR_ST

#define RTC_TSTR_ST RTC_TSTR_ST_Msk

◆ RTC_TSTR_ST_0

#define RTC_TSTR_ST_0 (0x1UL << RTC_TSTR_ST_Pos)

0x00000010

◆ RTC_TSTR_ST_1

#define RTC_TSTR_ST_1 (0x2UL << RTC_TSTR_ST_Pos)

0x00000020

◆ RTC_TSTR_ST_2

#define RTC_TSTR_ST_2 (0x4UL << RTC_TSTR_ST_Pos)

0x00000040

◆ RTC_TSTR_ST_Msk

#define RTC_TSTR_ST_Msk (0x7UL << RTC_TSTR_ST_Pos)

0x00000070

◆ RTC_TSTR_ST_Pos

#define RTC_TSTR_ST_Pos (4U)

◆ RTC_TSTR_SU

#define RTC_TSTR_SU RTC_TSTR_SU_Msk

◆ RTC_TSTR_SU_0

#define RTC_TSTR_SU_0 (0x1UL << RTC_TSTR_SU_Pos)

0x00000001

◆ RTC_TSTR_SU_1

#define RTC_TSTR_SU_1 (0x2UL << RTC_TSTR_SU_Pos)

0x00000002

◆ RTC_TSTR_SU_2

#define RTC_TSTR_SU_2 (0x4UL << RTC_TSTR_SU_Pos)

0x00000004

◆ RTC_TSTR_SU_3

#define RTC_TSTR_SU_3 (0x8UL << RTC_TSTR_SU_Pos)

0x00000008

◆ RTC_TSTR_SU_Msk

#define RTC_TSTR_SU_Msk (0xFUL << RTC_TSTR_SU_Pos)

0x0000000F

◆ RTC_TSTR_SU_Pos

#define RTC_TSTR_SU_Pos (0U)

◆ RTC_WAKEUP_SUPPORT

#define RTC_WAKEUP_SUPPORT

WAKEUP feature support

◆ RTC_WPR_KEY

#define RTC_WPR_KEY RTC_WPR_KEY_Msk

◆ RTC_WPR_KEY_Msk

#define RTC_WPR_KEY_Msk (0xFFUL << RTC_WPR_KEY_Pos)

0x000000FF

◆ RTC_WPR_KEY_Pos

#define RTC_WPR_KEY_Pos (0U)

◆ RTC_WUTR_WUT

#define RTC_WUTR_WUT RTC_WUTR_WUT_Msk

◆ RTC_WUTR_WUT_Msk

#define RTC_WUTR_WUT_Msk (0xFFFFUL << RTC_WUTR_WUT_Pos)

0x0000FFFF

◆ RTC_WUTR_WUT_Pos

#define RTC_WUTR_WUT_Pos (0U)

◆ SPI_CR1_BIDIMODE

#define SPI_CR1_BIDIMODE SPI_CR1_BIDIMODE_Msk

Bidirectional data mode enable

◆ SPI_CR1_BIDIMODE_Msk

#define SPI_CR1_BIDIMODE_Msk (0x1UL << SPI_CR1_BIDIMODE_Pos)

0x00008000

◆ SPI_CR1_BIDIMODE_Pos

#define SPI_CR1_BIDIMODE_Pos (15U)

◆ SPI_CR1_BIDIOE

#define SPI_CR1_BIDIOE SPI_CR1_BIDIOE_Msk

Output enable in bidirectional mode

◆ SPI_CR1_BIDIOE_Msk

#define SPI_CR1_BIDIOE_Msk (0x1UL << SPI_CR1_BIDIOE_Pos)

0x00004000

◆ SPI_CR1_BIDIOE_Pos

#define SPI_CR1_BIDIOE_Pos (14U)

◆ SPI_CR1_BR

#define SPI_CR1_BR SPI_CR1_BR_Msk

BR[2:0] bits (Baud Rate Control)

◆ SPI_CR1_BR_0

#define SPI_CR1_BR_0 (0x1UL << SPI_CR1_BR_Pos)

0x00000008

◆ SPI_CR1_BR_1

#define SPI_CR1_BR_1 (0x2UL << SPI_CR1_BR_Pos)

0x00000010

◆ SPI_CR1_BR_2

#define SPI_CR1_BR_2 (0x4UL << SPI_CR1_BR_Pos)

0x00000020

◆ SPI_CR1_BR_Msk

#define SPI_CR1_BR_Msk (0x7UL << SPI_CR1_BR_Pos)

0x00000038

◆ SPI_CR1_BR_Pos

#define SPI_CR1_BR_Pos (3U)

◆ SPI_CR1_CPHA

#define SPI_CR1_CPHA SPI_CR1_CPHA_Msk

Clock Phase

◆ SPI_CR1_CPHA_Msk

#define SPI_CR1_CPHA_Msk (0x1UL << SPI_CR1_CPHA_Pos)

0x00000001

◆ SPI_CR1_CPHA_Pos

#define SPI_CR1_CPHA_Pos (0U)

◆ SPI_CR1_CPOL

#define SPI_CR1_CPOL SPI_CR1_CPOL_Msk

Clock Polarity

◆ SPI_CR1_CPOL_Msk

#define SPI_CR1_CPOL_Msk (0x1UL << SPI_CR1_CPOL_Pos)

0x00000002

◆ SPI_CR1_CPOL_Pos

#define SPI_CR1_CPOL_Pos (1U)

◆ SPI_CR1_CRCEN

#define SPI_CR1_CRCEN SPI_CR1_CRCEN_Msk

Hardware CRC calculation enable

◆ SPI_CR1_CRCEN_Msk

#define SPI_CR1_CRCEN_Msk (0x1UL << SPI_CR1_CRCEN_Pos)

0x00002000

◆ SPI_CR1_CRCEN_Pos

#define SPI_CR1_CRCEN_Pos (13U)

◆ SPI_CR1_CRCL

#define SPI_CR1_CRCL SPI_CR1_CRCL_Msk

CRC Length

◆ SPI_CR1_CRCL_Msk

#define SPI_CR1_CRCL_Msk (0x1UL << SPI_CR1_CRCL_Pos)

0x00000800

◆ SPI_CR1_CRCL_Pos

#define SPI_CR1_CRCL_Pos (11U)

◆ SPI_CR1_CRCNEXT

#define SPI_CR1_CRCNEXT SPI_CR1_CRCNEXT_Msk

Transmit CRC next

◆ SPI_CR1_CRCNEXT_Msk

#define SPI_CR1_CRCNEXT_Msk (0x1UL << SPI_CR1_CRCNEXT_Pos)

0x00001000

◆ SPI_CR1_CRCNEXT_Pos

#define SPI_CR1_CRCNEXT_Pos (12U)

◆ SPI_CR1_LSBFIRST

#define SPI_CR1_LSBFIRST SPI_CR1_LSBFIRST_Msk

Frame Format

◆ SPI_CR1_LSBFIRST_Msk

#define SPI_CR1_LSBFIRST_Msk (0x1UL << SPI_CR1_LSBFIRST_Pos)

0x00000080

◆ SPI_CR1_LSBFIRST_Pos

#define SPI_CR1_LSBFIRST_Pos (7U)

◆ SPI_CR1_MSTR

#define SPI_CR1_MSTR SPI_CR1_MSTR_Msk

Master Selection

◆ SPI_CR1_MSTR_Msk

#define SPI_CR1_MSTR_Msk (0x1UL << SPI_CR1_MSTR_Pos)

0x00000004

◆ SPI_CR1_MSTR_Pos

#define SPI_CR1_MSTR_Pos (2U)

◆ SPI_CR1_RXONLY

#define SPI_CR1_RXONLY SPI_CR1_RXONLY_Msk

Receive only

◆ SPI_CR1_RXONLY_Msk

#define SPI_CR1_RXONLY_Msk (0x1UL << SPI_CR1_RXONLY_Pos)

0x00000400

◆ SPI_CR1_RXONLY_Pos

#define SPI_CR1_RXONLY_Pos (10U)

◆ SPI_CR1_SPE

#define SPI_CR1_SPE SPI_CR1_SPE_Msk

SPI Enable

◆ SPI_CR1_SPE_Msk

#define SPI_CR1_SPE_Msk (0x1UL << SPI_CR1_SPE_Pos)

0x00000040

◆ SPI_CR1_SPE_Pos

#define SPI_CR1_SPE_Pos (6U)

◆ SPI_CR1_SSI

#define SPI_CR1_SSI SPI_CR1_SSI_Msk

Internal slave select

◆ SPI_CR1_SSI_Msk

#define SPI_CR1_SSI_Msk (0x1UL << SPI_CR1_SSI_Pos)

0x00000100

◆ SPI_CR1_SSI_Pos

#define SPI_CR1_SSI_Pos (8U)

◆ SPI_CR1_SSM

#define SPI_CR1_SSM SPI_CR1_SSM_Msk

Software slave management

◆ SPI_CR1_SSM_Msk

#define SPI_CR1_SSM_Msk (0x1UL << SPI_CR1_SSM_Pos)

0x00000200

◆ SPI_CR1_SSM_Pos

#define SPI_CR1_SSM_Pos (9U)

◆ SPI_CR2_DS

#define SPI_CR2_DS SPI_CR2_DS_Msk

DS[3:0] Data Size

◆ SPI_CR2_DS_0

#define SPI_CR2_DS_0 (0x1UL << SPI_CR2_DS_Pos)

0x00000100

◆ SPI_CR2_DS_1

#define SPI_CR2_DS_1 (0x2UL << SPI_CR2_DS_Pos)

0x00000200

◆ SPI_CR2_DS_2

#define SPI_CR2_DS_2 (0x4UL << SPI_CR2_DS_Pos)

0x00000400

◆ SPI_CR2_DS_3

#define SPI_CR2_DS_3 (0x8UL << SPI_CR2_DS_Pos)

0x00000800

◆ SPI_CR2_DS_Msk

#define SPI_CR2_DS_Msk (0xFUL << SPI_CR2_DS_Pos)

0x00000F00

◆ SPI_CR2_DS_Pos

#define SPI_CR2_DS_Pos (8U)

◆ SPI_CR2_ERRIE

#define SPI_CR2_ERRIE SPI_CR2_ERRIE_Msk

Error Interrupt Enable

◆ SPI_CR2_ERRIE_Msk

#define SPI_CR2_ERRIE_Msk (0x1UL << SPI_CR2_ERRIE_Pos)

0x00000020

◆ SPI_CR2_ERRIE_Pos

#define SPI_CR2_ERRIE_Pos (5U)

◆ SPI_CR2_FRF

#define SPI_CR2_FRF SPI_CR2_FRF_Msk

Frame Format Enable

◆ SPI_CR2_FRF_Msk

#define SPI_CR2_FRF_Msk (0x1UL << SPI_CR2_FRF_Pos)

0x00000010

◆ SPI_CR2_FRF_Pos

#define SPI_CR2_FRF_Pos (4U)

◆ SPI_CR2_FRXTH

#define SPI_CR2_FRXTH SPI_CR2_FRXTH_Msk

FIFO reception Threshold

◆ SPI_CR2_FRXTH_Msk

#define SPI_CR2_FRXTH_Msk (0x1UL << SPI_CR2_FRXTH_Pos)

0x00001000

◆ SPI_CR2_FRXTH_Pos

#define SPI_CR2_FRXTH_Pos (12U)

◆ SPI_CR2_LDMARX

#define SPI_CR2_LDMARX SPI_CR2_LDMARX_Msk

Last DMA transfer for reception

◆ SPI_CR2_LDMARX_Msk

#define SPI_CR2_LDMARX_Msk (0x1UL << SPI_CR2_LDMARX_Pos)

0x00002000

◆ SPI_CR2_LDMARX_Pos

#define SPI_CR2_LDMARX_Pos (13U)

◆ SPI_CR2_LDMATX

#define SPI_CR2_LDMATX SPI_CR2_LDMATX_Msk

Last DMA transfer for transmission

◆ SPI_CR2_LDMATX_Msk

#define SPI_CR2_LDMATX_Msk (0x1UL << SPI_CR2_LDMATX_Pos)

0x00004000

◆ SPI_CR2_LDMATX_Pos

#define SPI_CR2_LDMATX_Pos (14U)

◆ SPI_CR2_NSSP

#define SPI_CR2_NSSP SPI_CR2_NSSP_Msk

NSS pulse management Enable

◆ SPI_CR2_NSSP_Msk

#define SPI_CR2_NSSP_Msk (0x1UL << SPI_CR2_NSSP_Pos)

0x00000008

◆ SPI_CR2_NSSP_Pos

#define SPI_CR2_NSSP_Pos (3U)

◆ SPI_CR2_RXDMAEN

#define SPI_CR2_RXDMAEN SPI_CR2_RXDMAEN_Msk

Rx Buffer DMA Enable

◆ SPI_CR2_RXDMAEN_Msk

#define SPI_CR2_RXDMAEN_Msk (0x1UL << SPI_CR2_RXDMAEN_Pos)

0x00000001

◆ SPI_CR2_RXDMAEN_Pos

#define SPI_CR2_RXDMAEN_Pos (0U)

◆ SPI_CR2_RXNEIE

#define SPI_CR2_RXNEIE SPI_CR2_RXNEIE_Msk

RX buffer Not Empty Interrupt Enable

◆ SPI_CR2_RXNEIE_Msk

#define SPI_CR2_RXNEIE_Msk (0x1UL << SPI_CR2_RXNEIE_Pos)

0x00000040

◆ SPI_CR2_RXNEIE_Pos

#define SPI_CR2_RXNEIE_Pos (6U)

◆ SPI_CR2_SSOE

#define SPI_CR2_SSOE SPI_CR2_SSOE_Msk

SS Output Enable

◆ SPI_CR2_SSOE_Msk

#define SPI_CR2_SSOE_Msk (0x1UL << SPI_CR2_SSOE_Pos)

0x00000004

◆ SPI_CR2_SSOE_Pos

#define SPI_CR2_SSOE_Pos (2U)

◆ SPI_CR2_TXDMAEN

#define SPI_CR2_TXDMAEN SPI_CR2_TXDMAEN_Msk

Tx Buffer DMA Enable

◆ SPI_CR2_TXDMAEN_Msk

#define SPI_CR2_TXDMAEN_Msk (0x1UL << SPI_CR2_TXDMAEN_Pos)

0x00000002

◆ SPI_CR2_TXDMAEN_Pos

#define SPI_CR2_TXDMAEN_Pos (1U)

◆ SPI_CR2_TXEIE

#define SPI_CR2_TXEIE SPI_CR2_TXEIE_Msk

Tx buffer Empty Interrupt Enable

◆ SPI_CR2_TXEIE_Msk

#define SPI_CR2_TXEIE_Msk (0x1UL << SPI_CR2_TXEIE_Pos)

0x00000080

◆ SPI_CR2_TXEIE_Pos

#define SPI_CR2_TXEIE_Pos (7U)

◆ SPI_CRCPR_CRCPOLY

#define SPI_CRCPR_CRCPOLY SPI_CRCPR_CRCPOLY_Msk

CRC polynomial register

◆ SPI_CRCPR_CRCPOLY_Msk

#define SPI_CRCPR_CRCPOLY_Msk (0xFFFFUL << SPI_CRCPR_CRCPOLY_Pos)

0x0000FFFF

◆ SPI_CRCPR_CRCPOLY_Pos

#define SPI_CRCPR_CRCPOLY_Pos (0U)

◆ SPI_DR_DR

#define SPI_DR_DR SPI_DR_DR_Msk

Data Register

◆ SPI_DR_DR_Msk

#define SPI_DR_DR_Msk (0xFFFFUL << SPI_DR_DR_Pos)

0x0000FFFF

◆ SPI_DR_DR_Pos

#define SPI_DR_DR_Pos (0U)

◆ SPI_I2S_FULLDUPLEX_SUPPORT

#define SPI_I2S_FULLDUPLEX_SUPPORT

I2S Full-Duplex support

◆ SPI_I2S_SUPPORT

#define SPI_I2S_SUPPORT

I2S support

◆ SPI_I2SCFGR_CHLEN

#define SPI_I2SCFGR_CHLEN SPI_I2SCFGR_CHLEN_Msk

Channel length (number of bits per audio channel)

◆ SPI_I2SCFGR_CHLEN_Msk

#define SPI_I2SCFGR_CHLEN_Msk (0x1UL << SPI_I2SCFGR_CHLEN_Pos)

0x00000001

◆ SPI_I2SCFGR_CHLEN_Pos

#define SPI_I2SCFGR_CHLEN_Pos (0U)

◆ SPI_I2SCFGR_CKPOL

#define SPI_I2SCFGR_CKPOL SPI_I2SCFGR_CKPOL_Msk

steady state clock polarity

◆ SPI_I2SCFGR_CKPOL_Msk

#define SPI_I2SCFGR_CKPOL_Msk (0x1UL << SPI_I2SCFGR_CKPOL_Pos)

0x00000008

◆ SPI_I2SCFGR_CKPOL_Pos

#define SPI_I2SCFGR_CKPOL_Pos (3U)

◆ SPI_I2SCFGR_DATLEN

#define SPI_I2SCFGR_DATLEN SPI_I2SCFGR_DATLEN_Msk

DATLEN[1:0] bits (Data length to be transferred)

◆ SPI_I2SCFGR_DATLEN_0

#define SPI_I2SCFGR_DATLEN_0 (0x1UL << SPI_I2SCFGR_DATLEN_Pos)

0x00000002

◆ SPI_I2SCFGR_DATLEN_1

#define SPI_I2SCFGR_DATLEN_1 (0x2UL << SPI_I2SCFGR_DATLEN_Pos)

0x00000004

◆ SPI_I2SCFGR_DATLEN_Msk

#define SPI_I2SCFGR_DATLEN_Msk (0x3UL << SPI_I2SCFGR_DATLEN_Pos)

0x00000006

◆ SPI_I2SCFGR_DATLEN_Pos

#define SPI_I2SCFGR_DATLEN_Pos (1U)

◆ SPI_I2SCFGR_I2SCFG

#define SPI_I2SCFGR_I2SCFG SPI_I2SCFGR_I2SCFG_Msk

I2SCFG[1:0] bits (I2S configuration mode)

◆ SPI_I2SCFGR_I2SCFG_0

#define SPI_I2SCFGR_I2SCFG_0 (0x1UL << SPI_I2SCFGR_I2SCFG_Pos)

0x00000100

◆ SPI_I2SCFGR_I2SCFG_1

#define SPI_I2SCFGR_I2SCFG_1 (0x2UL << SPI_I2SCFGR_I2SCFG_Pos)

0x00000200

◆ SPI_I2SCFGR_I2SCFG_Msk

#define SPI_I2SCFGR_I2SCFG_Msk (0x3UL << SPI_I2SCFGR_I2SCFG_Pos)

0x00000300

◆ SPI_I2SCFGR_I2SCFG_Pos

#define SPI_I2SCFGR_I2SCFG_Pos (8U)

◆ SPI_I2SCFGR_I2SE

#define SPI_I2SCFGR_I2SE SPI_I2SCFGR_I2SE_Msk

I2S Enable

◆ SPI_I2SCFGR_I2SE_Msk

#define SPI_I2SCFGR_I2SE_Msk (0x1UL << SPI_I2SCFGR_I2SE_Pos)

0x00000400

◆ SPI_I2SCFGR_I2SE_Pos

#define SPI_I2SCFGR_I2SE_Pos (10U)

◆ SPI_I2SCFGR_I2SMOD

#define SPI_I2SCFGR_I2SMOD SPI_I2SCFGR_I2SMOD_Msk

I2S mode selection

◆ SPI_I2SCFGR_I2SMOD_Msk

#define SPI_I2SCFGR_I2SMOD_Msk (0x1UL << SPI_I2SCFGR_I2SMOD_Pos)

0x00000800

◆ SPI_I2SCFGR_I2SMOD_Pos

#define SPI_I2SCFGR_I2SMOD_Pos (11U)

◆ SPI_I2SCFGR_I2SSTD

#define SPI_I2SCFGR_I2SSTD SPI_I2SCFGR_I2SSTD_Msk

I2SSTD[1:0] bits (I2S standard selection)

◆ SPI_I2SCFGR_I2SSTD_0

#define SPI_I2SCFGR_I2SSTD_0 (0x1UL << SPI_I2SCFGR_I2SSTD_Pos)

0x00000010

◆ SPI_I2SCFGR_I2SSTD_1

#define SPI_I2SCFGR_I2SSTD_1 (0x2UL << SPI_I2SCFGR_I2SSTD_Pos)

0x00000020

◆ SPI_I2SCFGR_I2SSTD_Msk

#define SPI_I2SCFGR_I2SSTD_Msk (0x3UL << SPI_I2SCFGR_I2SSTD_Pos)

0x00000030

◆ SPI_I2SCFGR_I2SSTD_Pos

#define SPI_I2SCFGR_I2SSTD_Pos (4U)

◆ SPI_I2SCFGR_PCMSYNC

#define SPI_I2SCFGR_PCMSYNC SPI_I2SCFGR_PCMSYNC_Msk

PCM frame synchronization

◆ SPI_I2SCFGR_PCMSYNC_Msk

#define SPI_I2SCFGR_PCMSYNC_Msk (0x1UL << SPI_I2SCFGR_PCMSYNC_Pos)

0x00000080

◆ SPI_I2SCFGR_PCMSYNC_Pos

#define SPI_I2SCFGR_PCMSYNC_Pos (7U)

◆ SPI_I2SPR_I2SDIV

#define SPI_I2SPR_I2SDIV SPI_I2SPR_I2SDIV_Msk

I2S Linear prescaler

◆ SPI_I2SPR_I2SDIV_Msk

#define SPI_I2SPR_I2SDIV_Msk (0xFFUL << SPI_I2SPR_I2SDIV_Pos)

0x000000FF

◆ SPI_I2SPR_I2SDIV_Pos

#define SPI_I2SPR_I2SDIV_Pos (0U)

◆ SPI_I2SPR_MCKOE

#define SPI_I2SPR_MCKOE SPI_I2SPR_MCKOE_Msk

Master Clock Output Enable

◆ SPI_I2SPR_MCKOE_Msk

#define SPI_I2SPR_MCKOE_Msk (0x1UL << SPI_I2SPR_MCKOE_Pos)

0x00000200

◆ SPI_I2SPR_MCKOE_Pos

#define SPI_I2SPR_MCKOE_Pos (9U)

◆ SPI_I2SPR_ODD

#define SPI_I2SPR_ODD SPI_I2SPR_ODD_Msk

Odd factor for the prescaler

◆ SPI_I2SPR_ODD_Msk

#define SPI_I2SPR_ODD_Msk (0x1UL << SPI_I2SPR_ODD_Pos)

0x00000100

◆ SPI_I2SPR_ODD_Pos

#define SPI_I2SPR_ODD_Pos (8U)

◆ SPI_RXCRCR_RXCRC

#define SPI_RXCRCR_RXCRC SPI_RXCRCR_RXCRC_Msk

Rx CRC Register

◆ SPI_RXCRCR_RXCRC_Msk

#define SPI_RXCRCR_RXCRC_Msk (0xFFFFUL << SPI_RXCRCR_RXCRC_Pos)

0x0000FFFF

◆ SPI_RXCRCR_RXCRC_Pos

#define SPI_RXCRCR_RXCRC_Pos (0U)

◆ SPI_SR_BSY

#define SPI_SR_BSY SPI_SR_BSY_Msk

Busy flag

◆ SPI_SR_BSY_Msk

#define SPI_SR_BSY_Msk (0x1UL << SPI_SR_BSY_Pos)

0x00000080

◆ SPI_SR_BSY_Pos

#define SPI_SR_BSY_Pos (7U)

◆ SPI_SR_CHSIDE

#define SPI_SR_CHSIDE SPI_SR_CHSIDE_Msk

Channel side

◆ SPI_SR_CHSIDE_Msk

#define SPI_SR_CHSIDE_Msk (0x1UL << SPI_SR_CHSIDE_Pos)

0x00000004

◆ SPI_SR_CHSIDE_Pos

#define SPI_SR_CHSIDE_Pos (2U)

◆ SPI_SR_CRCERR

#define SPI_SR_CRCERR SPI_SR_CRCERR_Msk

CRC Error flag

◆ SPI_SR_CRCERR_Msk

#define SPI_SR_CRCERR_Msk (0x1UL << SPI_SR_CRCERR_Pos)

0x00000010

◆ SPI_SR_CRCERR_Pos

#define SPI_SR_CRCERR_Pos (4U)

◆ SPI_SR_FRE

#define SPI_SR_FRE SPI_SR_FRE_Msk

TI frame format error

◆ SPI_SR_FRE_Msk

#define SPI_SR_FRE_Msk (0x1UL << SPI_SR_FRE_Pos)

0x00000100

◆ SPI_SR_FRE_Pos

#define SPI_SR_FRE_Pos (8U)

◆ SPI_SR_FRLVL

#define SPI_SR_FRLVL SPI_SR_FRLVL_Msk

FIFO Reception Level

◆ SPI_SR_FRLVL_0

#define SPI_SR_FRLVL_0 (0x1UL << SPI_SR_FRLVL_Pos)

0x00000200

◆ SPI_SR_FRLVL_1

#define SPI_SR_FRLVL_1 (0x2UL << SPI_SR_FRLVL_Pos)

0x00000400

◆ SPI_SR_FRLVL_Msk

#define SPI_SR_FRLVL_Msk (0x3UL << SPI_SR_FRLVL_Pos)

0x00000600

◆ SPI_SR_FRLVL_Pos

#define SPI_SR_FRLVL_Pos (9U)

◆ SPI_SR_FTLVL

#define SPI_SR_FTLVL SPI_SR_FTLVL_Msk

FIFO Transmission Level

◆ SPI_SR_FTLVL_0

#define SPI_SR_FTLVL_0 (0x1UL << SPI_SR_FTLVL_Pos)

0x00000800

◆ SPI_SR_FTLVL_1

#define SPI_SR_FTLVL_1 (0x2UL << SPI_SR_FTLVL_Pos)

0x00001000

◆ SPI_SR_FTLVL_Msk

#define SPI_SR_FTLVL_Msk (0x3UL << SPI_SR_FTLVL_Pos)

0x00001800

◆ SPI_SR_FTLVL_Pos

#define SPI_SR_FTLVL_Pos (11U)

◆ SPI_SR_MODF

#define SPI_SR_MODF SPI_SR_MODF_Msk

Mode fault

◆ SPI_SR_MODF_Msk

#define SPI_SR_MODF_Msk (0x1UL << SPI_SR_MODF_Pos)

0x00000020

◆ SPI_SR_MODF_Pos

#define SPI_SR_MODF_Pos (5U)

◆ SPI_SR_OVR

#define SPI_SR_OVR SPI_SR_OVR_Msk

Overrun flag

◆ SPI_SR_OVR_Msk

#define SPI_SR_OVR_Msk (0x1UL << SPI_SR_OVR_Pos)

0x00000040

◆ SPI_SR_OVR_Pos

#define SPI_SR_OVR_Pos (6U)

◆ SPI_SR_RXNE

#define SPI_SR_RXNE SPI_SR_RXNE_Msk

Receive buffer Not Empty

◆ SPI_SR_RXNE_Msk

#define SPI_SR_RXNE_Msk (0x1UL << SPI_SR_RXNE_Pos)

0x00000001

◆ SPI_SR_RXNE_Pos

#define SPI_SR_RXNE_Pos (0U)

◆ SPI_SR_TXE

#define SPI_SR_TXE SPI_SR_TXE_Msk

Transmit buffer Empty

◆ SPI_SR_TXE_Msk

#define SPI_SR_TXE_Msk (0x1UL << SPI_SR_TXE_Pos)

0x00000002

◆ SPI_SR_TXE_Pos

#define SPI_SR_TXE_Pos (1U)

◆ SPI_SR_UDR

#define SPI_SR_UDR SPI_SR_UDR_Msk

Underrun flag

◆ SPI_SR_UDR_Msk

#define SPI_SR_UDR_Msk (0x1UL << SPI_SR_UDR_Pos)

0x00000008

◆ SPI_SR_UDR_Pos

#define SPI_SR_UDR_Pos (3U)

◆ SPI_TXCRCR_TXCRC

#define SPI_TXCRCR_TXCRC SPI_TXCRCR_TXCRC_Msk

Tx CRC Register

◆ SPI_TXCRCR_TXCRC_Msk

#define SPI_TXCRCR_TXCRC_Msk (0xFFFFUL << SPI_TXCRCR_TXCRC_Pos)

0x0000FFFF

◆ SPI_TXCRCR_TXCRC_Pos

#define SPI_TXCRCR_TXCRC_Pos (0U)

◆ SYSCFG_CFGR1_ADC24_DMA_RMP

#define SYSCFG_CFGR1_ADC24_DMA_RMP SYSCFG_CFGR1_ADC24_DMA_RMP_Msk

ADC2 and ADC4 DMA remap

◆ SYSCFG_CFGR1_ADC24_DMA_RMP_Msk

#define SYSCFG_CFGR1_ADC24_DMA_RMP_Msk (0x1UL << SYSCFG_CFGR1_ADC24_DMA_RMP_Pos)

0x00000100

◆ SYSCFG_CFGR1_ADC24_DMA_RMP_Pos

#define SYSCFG_CFGR1_ADC24_DMA_RMP_Pos (8U)

◆ SYSCFG_CFGR1_DAC1_TRIG1_RMP

#define SYSCFG_CFGR1_DAC1_TRIG1_RMP SYSCFG_CFGR1_DAC1_TRIG1_RMP_Msk

DAC1 Trigger1 remap

◆ SYSCFG_CFGR1_DAC1_TRIG1_RMP_Msk

#define SYSCFG_CFGR1_DAC1_TRIG1_RMP_Msk (0x1UL << SYSCFG_CFGR1_DAC1_TRIG1_RMP_Pos)

0x00000080

◆ SYSCFG_CFGR1_DAC1_TRIG1_RMP_Pos

#define SYSCFG_CFGR1_DAC1_TRIG1_RMP_Pos (7U)

◆ SYSCFG_CFGR1_DMA_RMP

#define SYSCFG_CFGR1_DMA_RMP SYSCFG_CFGR1_DMA_RMP_Msk

DMA remap mask

◆ SYSCFG_CFGR1_DMA_RMP_Msk

#define SYSCFG_CFGR1_DMA_RMP_Msk (0x79UL << SYSCFG_CFGR1_DMA_RMP_Pos)

0x00007900

◆ SYSCFG_CFGR1_DMA_RMP_Pos

#define SYSCFG_CFGR1_DMA_RMP_Pos (8U)

◆ SYSCFG_CFGR1_ENCODER_MODE

#define SYSCFG_CFGR1_ENCODER_MODE SYSCFG_CFGR1_ENCODER_MODE_Msk

Encoder Mode

◆ SYSCFG_CFGR1_ENCODER_MODE_0

#define SYSCFG_CFGR1_ENCODER_MODE_0 (0x1UL << SYSCFG_CFGR1_ENCODER_MODE_Pos)

0x00400000

◆ SYSCFG_CFGR1_ENCODER_MODE_1

#define SYSCFG_CFGR1_ENCODER_MODE_1 (0x2UL << SYSCFG_CFGR1_ENCODER_MODE_Pos)

0x00800000

◆ SYSCFG_CFGR1_ENCODER_MODE_Msk

#define SYSCFG_CFGR1_ENCODER_MODE_Msk (0x3UL << SYSCFG_CFGR1_ENCODER_MODE_Pos)

0x00C00000

◆ SYSCFG_CFGR1_ENCODER_MODE_Pos

#define SYSCFG_CFGR1_ENCODER_MODE_Pos (22U)

◆ SYSCFG_CFGR1_ENCODER_MODE_TIM2

#define SYSCFG_CFGR1_ENCODER_MODE_TIM2 SYSCFG_CFGR1_ENCODER_MODE_TIM2_Msk

TIM2 IC1 and TIM2 IC2 are connected to TIM15 IC1 and TIM15 IC2 respectively

◆ SYSCFG_CFGR1_ENCODER_MODE_TIM2_Msk

#define SYSCFG_CFGR1_ENCODER_MODE_TIM2_Msk (0x1UL << SYSCFG_CFGR1_ENCODER_MODE_TIM2_Pos)

0x00400000

◆ SYSCFG_CFGR1_ENCODER_MODE_TIM2_Pos

#define SYSCFG_CFGR1_ENCODER_MODE_TIM2_Pos (22U)

◆ SYSCFG_CFGR1_ENCODER_MODE_TIM3

#define SYSCFG_CFGR1_ENCODER_MODE_TIM3 SYSCFG_CFGR1_ENCODER_MODE_TIM3_Msk

TIM3 IC1 and TIM3 IC2 are connected to TIM15 IC1 and TIM15 IC2 respectively

◆ SYSCFG_CFGR1_ENCODER_MODE_TIM3_Msk

#define SYSCFG_CFGR1_ENCODER_MODE_TIM3_Msk (0x1UL << SYSCFG_CFGR1_ENCODER_MODE_TIM3_Pos)

0x00800000

◆ SYSCFG_CFGR1_ENCODER_MODE_TIM3_Pos

#define SYSCFG_CFGR1_ENCODER_MODE_TIM3_Pos (23U)

◆ SYSCFG_CFGR1_FPU_IE

#define SYSCFG_CFGR1_FPU_IE SYSCFG_CFGR1_FPU_IE_Msk

Floating Point Unit Interrupt Enable

◆ SYSCFG_CFGR1_FPU_IE_0

#define SYSCFG_CFGR1_FPU_IE_0 (0x01UL << SYSCFG_CFGR1_FPU_IE_Pos)

0x04000000

◆ SYSCFG_CFGR1_FPU_IE_1

#define SYSCFG_CFGR1_FPU_IE_1 (0x02UL << SYSCFG_CFGR1_FPU_IE_Pos)

0x08000000

◆ SYSCFG_CFGR1_FPU_IE_2

#define SYSCFG_CFGR1_FPU_IE_2 (0x04UL << SYSCFG_CFGR1_FPU_IE_Pos)

0x10000000

◆ SYSCFG_CFGR1_FPU_IE_3

#define SYSCFG_CFGR1_FPU_IE_3 (0x08UL << SYSCFG_CFGR1_FPU_IE_Pos)

0x20000000

◆ SYSCFG_CFGR1_FPU_IE_4

#define SYSCFG_CFGR1_FPU_IE_4 (0x10UL << SYSCFG_CFGR1_FPU_IE_Pos)

0x40000000

◆ SYSCFG_CFGR1_FPU_IE_5

#define SYSCFG_CFGR1_FPU_IE_5 (0x20UL << SYSCFG_CFGR1_FPU_IE_Pos)

0x80000000

◆ SYSCFG_CFGR1_FPU_IE_Msk

#define SYSCFG_CFGR1_FPU_IE_Msk (0x3FUL << SYSCFG_CFGR1_FPU_IE_Pos)

0xFC000000

◆ SYSCFG_CFGR1_FPU_IE_Pos

#define SYSCFG_CFGR1_FPU_IE_Pos (26U)

◆ SYSCFG_CFGR1_I2C1_FMP

#define SYSCFG_CFGR1_I2C1_FMP SYSCFG_CFGR1_I2C1_FMP_Msk

I2C1 Fast mode plus

◆ SYSCFG_CFGR1_I2C1_FMP_Msk

#define SYSCFG_CFGR1_I2C1_FMP_Msk (0x1UL << SYSCFG_CFGR1_I2C1_FMP_Pos)

0x00100000

◆ SYSCFG_CFGR1_I2C1_FMP_Pos

#define SYSCFG_CFGR1_I2C1_FMP_Pos (20U)

◆ SYSCFG_CFGR1_I2C2_FMP

#define SYSCFG_CFGR1_I2C2_FMP SYSCFG_CFGR1_I2C2_FMP_Msk

I2C2 Fast mode plus

◆ SYSCFG_CFGR1_I2C2_FMP_Msk

#define SYSCFG_CFGR1_I2C2_FMP_Msk (0x1UL << SYSCFG_CFGR1_I2C2_FMP_Pos)

0x00200000

◆ SYSCFG_CFGR1_I2C2_FMP_Pos

#define SYSCFG_CFGR1_I2C2_FMP_Pos (21U)

◆ SYSCFG_CFGR1_I2C3_FMP

#define SYSCFG_CFGR1_I2C3_FMP SYSCFG_CFGR1_I2C3_FMP_Msk

I2C3 Fast mode plus

◆ SYSCFG_CFGR1_I2C3_FMP_Msk

#define SYSCFG_CFGR1_I2C3_FMP_Msk (0x1UL << SYSCFG_CFGR1_I2C3_FMP_Pos)

0x01000000

◆ SYSCFG_CFGR1_I2C3_FMP_Pos

#define SYSCFG_CFGR1_I2C3_FMP_Pos (24U)

◆ SYSCFG_CFGR1_I2C_PB6_FMP

#define SYSCFG_CFGR1_I2C_PB6_FMP SYSCFG_CFGR1_I2C_PB6_FMP_Msk

I2C PB6 Fast mode plus

◆ SYSCFG_CFGR1_I2C_PB6_FMP_Msk

#define SYSCFG_CFGR1_I2C_PB6_FMP_Msk (0x1UL << SYSCFG_CFGR1_I2C_PB6_FMP_Pos)

0x00010000

◆ SYSCFG_CFGR1_I2C_PB6_FMP_Pos

#define SYSCFG_CFGR1_I2C_PB6_FMP_Pos (16U)

◆ SYSCFG_CFGR1_I2C_PB7_FMP

#define SYSCFG_CFGR1_I2C_PB7_FMP SYSCFG_CFGR1_I2C_PB7_FMP_Msk

I2C PB7 Fast mode plus

◆ SYSCFG_CFGR1_I2C_PB7_FMP_Msk

#define SYSCFG_CFGR1_I2C_PB7_FMP_Msk (0x1UL << SYSCFG_CFGR1_I2C_PB7_FMP_Pos)

0x00020000

◆ SYSCFG_CFGR1_I2C_PB7_FMP_Pos

#define SYSCFG_CFGR1_I2C_PB7_FMP_Pos (17U)

◆ SYSCFG_CFGR1_I2C_PB8_FMP

#define SYSCFG_CFGR1_I2C_PB8_FMP SYSCFG_CFGR1_I2C_PB8_FMP_Msk

I2C PB8 Fast mode plus

◆ SYSCFG_CFGR1_I2C_PB8_FMP_Msk

#define SYSCFG_CFGR1_I2C_PB8_FMP_Msk (0x1UL << SYSCFG_CFGR1_I2C_PB8_FMP_Pos)

0x00040000

◆ SYSCFG_CFGR1_I2C_PB8_FMP_Pos

#define SYSCFG_CFGR1_I2C_PB8_FMP_Pos (18U)

◆ SYSCFG_CFGR1_I2C_PB9_FMP

#define SYSCFG_CFGR1_I2C_PB9_FMP SYSCFG_CFGR1_I2C_PB9_FMP_Msk

I2C PB9 Fast mode plus

◆ SYSCFG_CFGR1_I2C_PB9_FMP_Msk

#define SYSCFG_CFGR1_I2C_PB9_FMP_Msk (0x1UL << SYSCFG_CFGR1_I2C_PB9_FMP_Pos)

0x00080000

◆ SYSCFG_CFGR1_I2C_PB9_FMP_Pos

#define SYSCFG_CFGR1_I2C_PB9_FMP_Pos (19U)

◆ SYSCFG_CFGR1_MEM_MODE

#define SYSCFG_CFGR1_MEM_MODE SYSCFG_CFGR1_MEM_MODE_Msk

SYSCFG_Memory Remap Config

◆ SYSCFG_CFGR1_MEM_MODE_0

#define SYSCFG_CFGR1_MEM_MODE_0 (0x00000001U)

Bit 0

◆ SYSCFG_CFGR1_MEM_MODE_1

#define SYSCFG_CFGR1_MEM_MODE_1 (0x00000002U)

Bit 1

◆ SYSCFG_CFGR1_MEM_MODE_2

#define SYSCFG_CFGR1_MEM_MODE_2 (0x00000004U)

Bit 2

◆ SYSCFG_CFGR1_MEM_MODE_Msk

#define SYSCFG_CFGR1_MEM_MODE_Msk (0x7UL << SYSCFG_CFGR1_MEM_MODE_Pos)

0x00000007

◆ SYSCFG_CFGR1_MEM_MODE_Pos

#define SYSCFG_CFGR1_MEM_MODE_Pos (0U)

◆ SYSCFG_CFGR1_TIM16_DMA_RMP

#define SYSCFG_CFGR1_TIM16_DMA_RMP SYSCFG_CFGR1_TIM16_DMA_RMP_Msk

Timer 16 DMA remap

◆ SYSCFG_CFGR1_TIM16_DMA_RMP_Msk

#define SYSCFG_CFGR1_TIM16_DMA_RMP_Msk (0x1UL << SYSCFG_CFGR1_TIM16_DMA_RMP_Pos)

0x00000800

◆ SYSCFG_CFGR1_TIM16_DMA_RMP_Pos

#define SYSCFG_CFGR1_TIM16_DMA_RMP_Pos (11U)

◆ SYSCFG_CFGR1_TIM17_DMA_RMP

#define SYSCFG_CFGR1_TIM17_DMA_RMP SYSCFG_CFGR1_TIM17_DMA_RMP_Msk

Timer 17 DMA remap

◆ SYSCFG_CFGR1_TIM17_DMA_RMP_Msk

#define SYSCFG_CFGR1_TIM17_DMA_RMP_Msk (0x1UL << SYSCFG_CFGR1_TIM17_DMA_RMP_Pos)

0x00001000

◆ SYSCFG_CFGR1_TIM17_DMA_RMP_Pos

#define SYSCFG_CFGR1_TIM17_DMA_RMP_Pos (12U)

◆ SYSCFG_CFGR1_TIM1_ITR3_RMP

#define SYSCFG_CFGR1_TIM1_ITR3_RMP SYSCFG_CFGR1_TIM1_ITR3_RMP_Msk

Timer 1 ITR3 selection

◆ SYSCFG_CFGR1_TIM1_ITR3_RMP_Msk

#define SYSCFG_CFGR1_TIM1_ITR3_RMP_Msk (0x1UL << SYSCFG_CFGR1_TIM1_ITR3_RMP_Pos)

0x00000040

◆ SYSCFG_CFGR1_TIM1_ITR3_RMP_Pos

#define SYSCFG_CFGR1_TIM1_ITR3_RMP_Pos (6U)

◆ SYSCFG_CFGR1_TIM6DAC1Ch1_DMA_RMP

#define SYSCFG_CFGR1_TIM6DAC1Ch1_DMA_RMP SYSCFG_CFGR1_TIM6DAC1Ch1_DMA_RMP_Msk

Timer 6 / DAC1 Ch1 DMA remap

◆ SYSCFG_CFGR1_TIM6DAC1Ch1_DMA_RMP_Msk

#define SYSCFG_CFGR1_TIM6DAC1Ch1_DMA_RMP_Msk (0x1UL << SYSCFG_CFGR1_TIM6DAC1Ch1_DMA_RMP_Pos)

0x00002000

◆ SYSCFG_CFGR1_TIM6DAC1Ch1_DMA_RMP_Pos

#define SYSCFG_CFGR1_TIM6DAC1Ch1_DMA_RMP_Pos (13U)

◆ SYSCFG_CFGR1_TIM7DAC1Ch2_DMA_RMP

#define SYSCFG_CFGR1_TIM7DAC1Ch2_DMA_RMP SYSCFG_CFGR1_TIM7DAC1Ch2_DMA_RMP_Msk

Timer 7 / DAC1 Ch2 DMA remap

◆ SYSCFG_CFGR1_TIM7DAC1Ch2_DMA_RMP_Msk

#define SYSCFG_CFGR1_TIM7DAC1Ch2_DMA_RMP_Msk (0x1UL << SYSCFG_CFGR1_TIM7DAC1Ch2_DMA_RMP_Pos)

0x00004000

◆ SYSCFG_CFGR1_TIM7DAC1Ch2_DMA_RMP_Pos

#define SYSCFG_CFGR1_TIM7DAC1Ch2_DMA_RMP_Pos (14U)

◆ SYSCFG_CFGR1_USB_IT_RMP

#define SYSCFG_CFGR1_USB_IT_RMP SYSCFG_CFGR1_USB_IT_RMP_Msk

USB interrupt remap

◆ SYSCFG_CFGR1_USB_IT_RMP_Msk

#define SYSCFG_CFGR1_USB_IT_RMP_Msk (0x1UL << SYSCFG_CFGR1_USB_IT_RMP_Pos)

0x00000020

◆ SYSCFG_CFGR1_USB_IT_RMP_Pos

#define SYSCFG_CFGR1_USB_IT_RMP_Pos (5U)

◆ SYSCFG_CFGR2_BYP_ADDR_PAR

#define SYSCFG_CFGR2_BYP_ADDR_PAR SYSCFG_CFGR2_BYP_ADDR_PAR_Msk

Disables the address parity check on RAM

◆ SYSCFG_CFGR2_BYP_ADDR_PAR_Msk

#define SYSCFG_CFGR2_BYP_ADDR_PAR_Msk (0x1UL << SYSCFG_CFGR2_BYP_ADDR_PAR_Pos)

0x00000010

◆ SYSCFG_CFGR2_BYP_ADDR_PAR_Pos

#define SYSCFG_CFGR2_BYP_ADDR_PAR_Pos (4U)

◆ SYSCFG_CFGR2_LOCKUP_LOCK

#define SYSCFG_CFGR2_LOCKUP_LOCK SYSCFG_CFGR2_LOCKUP_LOCK_Msk

Enables and locks the LOCKUP (Hardfault) output of CortexM4 with Break Input of TIMx

◆ SYSCFG_CFGR2_LOCKUP_LOCK_Msk

#define SYSCFG_CFGR2_LOCKUP_LOCK_Msk (0x1UL << SYSCFG_CFGR2_LOCKUP_LOCK_Pos)

0x00000001

◆ SYSCFG_CFGR2_LOCKUP_LOCK_Pos

#define SYSCFG_CFGR2_LOCKUP_LOCK_Pos (0U)

◆ SYSCFG_CFGR2_PVD_LOCK

#define SYSCFG_CFGR2_PVD_LOCK SYSCFG_CFGR2_PVD_LOCK_Msk

Enables and locks the PVD connection with TIMx Break Input, as well as the PVDE and PLS[2:0] in the PWR_CR register

◆ SYSCFG_CFGR2_PVD_LOCK_Msk

#define SYSCFG_CFGR2_PVD_LOCK_Msk (0x1UL << SYSCFG_CFGR2_PVD_LOCK_Pos)

0x00000004

◆ SYSCFG_CFGR2_PVD_LOCK_Pos

#define SYSCFG_CFGR2_PVD_LOCK_Pos (2U)

◆ SYSCFG_CFGR2_SRAM_PARITY_LOCK

#define SYSCFG_CFGR2_SRAM_PARITY_LOCK SYSCFG_CFGR2_SRAM_PARITY_LOCK_Msk

Enables and locks the SRAM_PARITY error signal with Break Input of TIMx

◆ SYSCFG_CFGR2_SRAM_PARITY_LOCK_Msk

#define SYSCFG_CFGR2_SRAM_PARITY_LOCK_Msk (0x1UL << SYSCFG_CFGR2_SRAM_PARITY_LOCK_Pos)

0x00000002

◆ SYSCFG_CFGR2_SRAM_PARITY_LOCK_Pos

#define SYSCFG_CFGR2_SRAM_PARITY_LOCK_Pos (1U)

◆ SYSCFG_CFGR2_SRAM_PE

#define SYSCFG_CFGR2_SRAM_PE SYSCFG_CFGR2_SRAM_PE_Msk

SRAM Parity error flag

◆ SYSCFG_CFGR2_SRAM_PE_Msk

#define SYSCFG_CFGR2_SRAM_PE_Msk (0x1UL << SYSCFG_CFGR2_SRAM_PE_Pos)

0x00000100

◆ SYSCFG_CFGR2_SRAM_PE_Pos

#define SYSCFG_CFGR2_SRAM_PE_Pos (8U)

◆ SYSCFG_CFGR4_ADC12_EXT13_RMP

#define SYSCFG_CFGR4_ADC12_EXT13_RMP SYSCFG_CFGR4_ADC12_EXT13_RMP_Msk

ADC12 regular channel EXT13 remap

◆ SYSCFG_CFGR4_ADC12_EXT13_RMP_Msk

#define SYSCFG_CFGR4_ADC12_EXT13_RMP_Msk (0x1UL << SYSCFG_CFGR4_ADC12_EXT13_RMP_Pos)

0x00000008

◆ SYSCFG_CFGR4_ADC12_EXT13_RMP_Pos

#define SYSCFG_CFGR4_ADC12_EXT13_RMP_Pos (3U)

◆ SYSCFG_CFGR4_ADC12_EXT15_RMP

#define SYSCFG_CFGR4_ADC12_EXT15_RMP SYSCFG_CFGR4_ADC12_EXT15_RMP_Msk

ADC12 regular channel EXT15 remap

◆ SYSCFG_CFGR4_ADC12_EXT15_RMP_Msk

#define SYSCFG_CFGR4_ADC12_EXT15_RMP_Msk (0x1UL << SYSCFG_CFGR4_ADC12_EXT15_RMP_Pos)

0x00000010

◆ SYSCFG_CFGR4_ADC12_EXT15_RMP_Pos

#define SYSCFG_CFGR4_ADC12_EXT15_RMP_Pos (4U)

◆ SYSCFG_CFGR4_ADC12_EXT2_RMP

#define SYSCFG_CFGR4_ADC12_EXT2_RMP SYSCFG_CFGR4_ADC12_EXT2_RMP_Msk

ADC12 regular channel EXT2 remap

◆ SYSCFG_CFGR4_ADC12_EXT2_RMP_Msk

#define SYSCFG_CFGR4_ADC12_EXT2_RMP_Msk (0x1UL << SYSCFG_CFGR4_ADC12_EXT2_RMP_Pos)

0x00000001

◆ SYSCFG_CFGR4_ADC12_EXT2_RMP_Pos

#define SYSCFG_CFGR4_ADC12_EXT2_RMP_Pos (0U)

◆ SYSCFG_CFGR4_ADC12_EXT3_RMP

#define SYSCFG_CFGR4_ADC12_EXT3_RMP SYSCFG_CFGR4_ADC12_EXT3_RMP_Msk

ADC12 regular channel EXT3 remap

◆ SYSCFG_CFGR4_ADC12_EXT3_RMP_Msk

#define SYSCFG_CFGR4_ADC12_EXT3_RMP_Msk (0x1UL << SYSCFG_CFGR4_ADC12_EXT3_RMP_Pos)

0x00000002

◆ SYSCFG_CFGR4_ADC12_EXT3_RMP_Pos

#define SYSCFG_CFGR4_ADC12_EXT3_RMP_Pos (1U)

◆ SYSCFG_CFGR4_ADC12_EXT5_RMP

#define SYSCFG_CFGR4_ADC12_EXT5_RMP SYSCFG_CFGR4_ADC12_EXT5_RMP_Msk

ADC12 regular channel EXT5 remap

◆ SYSCFG_CFGR4_ADC12_EXT5_RMP_Msk

#define SYSCFG_CFGR4_ADC12_EXT5_RMP_Msk (0x1UL << SYSCFG_CFGR4_ADC12_EXT5_RMP_Pos)

0x00000004

◆ SYSCFG_CFGR4_ADC12_EXT5_RMP_Pos

#define SYSCFG_CFGR4_ADC12_EXT5_RMP_Pos (2U)

◆ SYSCFG_CFGR4_ADC12_JEXT13_RMP

#define SYSCFG_CFGR4_ADC12_JEXT13_RMP SYSCFG_CFGR4_ADC12_JEXT13_RMP_Msk

ADC12 injected channel JEXT13 remap

◆ SYSCFG_CFGR4_ADC12_JEXT13_RMP_Msk

#define SYSCFG_CFGR4_ADC12_JEXT13_RMP_Msk (0x1UL << SYSCFG_CFGR4_ADC12_JEXT13_RMP_Pos)

0x00000080

◆ SYSCFG_CFGR4_ADC12_JEXT13_RMP_Pos

#define SYSCFG_CFGR4_ADC12_JEXT13_RMP_Pos (7U)

◆ SYSCFG_CFGR4_ADC12_JEXT3_RMP

#define SYSCFG_CFGR4_ADC12_JEXT3_RMP SYSCFG_CFGR4_ADC12_JEXT3_RMP_Msk

ADC12 injected channel JEXT3 remap

◆ SYSCFG_CFGR4_ADC12_JEXT3_RMP_Msk

#define SYSCFG_CFGR4_ADC12_JEXT3_RMP_Msk (0x1UL << SYSCFG_CFGR4_ADC12_JEXT3_RMP_Pos)

0x00000020

◆ SYSCFG_CFGR4_ADC12_JEXT3_RMP_Pos

#define SYSCFG_CFGR4_ADC12_JEXT3_RMP_Pos (5U)

◆ SYSCFG_CFGR4_ADC12_JEXT6_RMP

#define SYSCFG_CFGR4_ADC12_JEXT6_RMP SYSCFG_CFGR4_ADC12_JEXT6_RMP_Msk

ADC12 injected channel JEXT6 remap

◆ SYSCFG_CFGR4_ADC12_JEXT6_RMP_Msk

#define SYSCFG_CFGR4_ADC12_JEXT6_RMP_Msk (0x1UL << SYSCFG_CFGR4_ADC12_JEXT6_RMP_Pos)

0x00000040

◆ SYSCFG_CFGR4_ADC12_JEXT6_RMP_Pos

#define SYSCFG_CFGR4_ADC12_JEXT6_RMP_Pos (6U)

◆ SYSCFG_CFGR4_ADC34_EXT15_RMP

#define SYSCFG_CFGR4_ADC34_EXT15_RMP SYSCFG_CFGR4_ADC34_EXT15_RMP_Msk

ADC34 regular channel EXT15 remap

◆ SYSCFG_CFGR4_ADC34_EXT15_RMP_Msk

#define SYSCFG_CFGR4_ADC34_EXT15_RMP_Msk (0x1UL << SYSCFG_CFGR4_ADC34_EXT15_RMP_Pos)

0x00000400

◆ SYSCFG_CFGR4_ADC34_EXT15_RMP_Pos

#define SYSCFG_CFGR4_ADC34_EXT15_RMP_Pos (10U)

◆ SYSCFG_CFGR4_ADC34_EXT5_RMP

#define SYSCFG_CFGR4_ADC34_EXT5_RMP SYSCFG_CFGR4_ADC34_EXT5_RMP_Msk

ADC34 regular channel EXT5 remap

◆ SYSCFG_CFGR4_ADC34_EXT5_RMP_Msk

#define SYSCFG_CFGR4_ADC34_EXT5_RMP_Msk (0x1UL << SYSCFG_CFGR4_ADC34_EXT5_RMP_Pos)

0x00000100

◆ SYSCFG_CFGR4_ADC34_EXT5_RMP_Pos

#define SYSCFG_CFGR4_ADC34_EXT5_RMP_Pos (8U)

◆ SYSCFG_CFGR4_ADC34_EXT6_RMP

#define SYSCFG_CFGR4_ADC34_EXT6_RMP SYSCFG_CFGR4_ADC34_EXT6_RMP_Msk

ADC34 regular channel EXT6 remap

◆ SYSCFG_CFGR4_ADC34_EXT6_RMP_Msk

#define SYSCFG_CFGR4_ADC34_EXT6_RMP_Msk (0x1UL << SYSCFG_CFGR4_ADC34_EXT6_RMP_Pos)

0x00000200

◆ SYSCFG_CFGR4_ADC34_EXT6_RMP_Pos

#define SYSCFG_CFGR4_ADC34_EXT6_RMP_Pos (9U)

◆ SYSCFG_CFGR4_ADC34_JEXT11_RMP

#define SYSCFG_CFGR4_ADC34_JEXT11_RMP SYSCFG_CFGR4_ADC34_JEXT11_RMP_Msk

ADC34 injected channel JEXT11 remap

◆ SYSCFG_CFGR4_ADC34_JEXT11_RMP_Msk

#define SYSCFG_CFGR4_ADC34_JEXT11_RMP_Msk (0x1UL << SYSCFG_CFGR4_ADC34_JEXT11_RMP_Pos)

0x00001000

◆ SYSCFG_CFGR4_ADC34_JEXT11_RMP_Pos

#define SYSCFG_CFGR4_ADC34_JEXT11_RMP_Pos (12U)

◆ SYSCFG_CFGR4_ADC34_JEXT14_RMP

#define SYSCFG_CFGR4_ADC34_JEXT14_RMP SYSCFG_CFGR4_ADC34_JEXT14_RMP_Msk

ADC34 injected channel JEXT14 remap

◆ SYSCFG_CFGR4_ADC34_JEXT14_RMP_Msk

#define SYSCFG_CFGR4_ADC34_JEXT14_RMP_Msk (0x1UL << SYSCFG_CFGR4_ADC34_JEXT14_RMP_Pos)

0x00002000

◆ SYSCFG_CFGR4_ADC34_JEXT14_RMP_Pos

#define SYSCFG_CFGR4_ADC34_JEXT14_RMP_Pos (13U)

◆ SYSCFG_CFGR4_ADC34_JEXT5_RMP

#define SYSCFG_CFGR4_ADC34_JEXT5_RMP SYSCFG_CFGR4_ADC34_JEXT5_RMP_Msk

ADC34 injected channel JEXT5 remap

◆ SYSCFG_CFGR4_ADC34_JEXT5_RMP_Msk

#define SYSCFG_CFGR4_ADC34_JEXT5_RMP_Msk (0x1UL << SYSCFG_CFGR4_ADC34_JEXT5_RMP_Pos)

0x00000800

◆ SYSCFG_CFGR4_ADC34_JEXT5_RMP_Pos

#define SYSCFG_CFGR4_ADC34_JEXT5_RMP_Pos (11U)

◆ SYSCFG_EXTICR1_EXTI0

#define SYSCFG_EXTICR1_EXTI0 SYSCFG_EXTICR1_EXTI0_Msk

EXTI 0 configuration

◆ SYSCFG_EXTICR1_EXTI0_Msk

#define SYSCFG_EXTICR1_EXTI0_Msk (0xFUL << SYSCFG_EXTICR1_EXTI0_Pos)

0x0000000F

◆ SYSCFG_EXTICR1_EXTI0_PA

#define SYSCFG_EXTICR1_EXTI0_PA (0x00000000U)

PA[0] pin

◆ SYSCFG_EXTICR1_EXTI0_PB

#define SYSCFG_EXTICR1_EXTI0_PB (0x00000001U)

PB[0] pin

◆ SYSCFG_EXTICR1_EXTI0_PC

#define SYSCFG_EXTICR1_EXTI0_PC (0x00000002U)

PC[0] pin

◆ SYSCFG_EXTICR1_EXTI0_PD

#define SYSCFG_EXTICR1_EXTI0_PD (0x00000003U)

PD[0] pin

◆ SYSCFG_EXTICR1_EXTI0_PE

#define SYSCFG_EXTICR1_EXTI0_PE (0x00000004U)

PE[0] pin

◆ SYSCFG_EXTICR1_EXTI0_PF

#define SYSCFG_EXTICR1_EXTI0_PF (0x00000005U)

PF[0] pin

◆ SYSCFG_EXTICR1_EXTI0_PG

#define SYSCFG_EXTICR1_EXTI0_PG (0x00000006U)

PG[0] pin

◆ SYSCFG_EXTICR1_EXTI0_PH

#define SYSCFG_EXTICR1_EXTI0_PH (0x00000007U)

EXTI1 configuration.

PH[0] pin

◆ SYSCFG_EXTICR1_EXTI0_Pos

#define SYSCFG_EXTICR1_EXTI0_Pos (0U)

◆ SYSCFG_EXTICR1_EXTI1

#define SYSCFG_EXTICR1_EXTI1 SYSCFG_EXTICR1_EXTI1_Msk

EXTI 1 configuration

◆ SYSCFG_EXTICR1_EXTI1_Msk

#define SYSCFG_EXTICR1_EXTI1_Msk (0xFUL << SYSCFG_EXTICR1_EXTI1_Pos)

0x000000F0

◆ SYSCFG_EXTICR1_EXTI1_PA

#define SYSCFG_EXTICR1_EXTI1_PA (0x00000000U)

PA[1] pin

◆ SYSCFG_EXTICR1_EXTI1_PB

#define SYSCFG_EXTICR1_EXTI1_PB (0x00000010U)

PB[1] pin

◆ SYSCFG_EXTICR1_EXTI1_PC

#define SYSCFG_EXTICR1_EXTI1_PC (0x00000020U)

PC[1] pin

◆ SYSCFG_EXTICR1_EXTI1_PD

#define SYSCFG_EXTICR1_EXTI1_PD (0x00000030U)

PD[1] pin

◆ SYSCFG_EXTICR1_EXTI1_PE

#define SYSCFG_EXTICR1_EXTI1_PE (0x00000040U)

PE[1] pin

◆ SYSCFG_EXTICR1_EXTI1_PF

#define SYSCFG_EXTICR1_EXTI1_PF (0x00000050U)

PF[1] pin

◆ SYSCFG_EXTICR1_EXTI1_PG

#define SYSCFG_EXTICR1_EXTI1_PG (0x00000060U)

PG[1] pin

◆ SYSCFG_EXTICR1_EXTI1_PH

#define SYSCFG_EXTICR1_EXTI1_PH (0x00000070U)

EXTI2 configuration.

PH[1] pin

◆ SYSCFG_EXTICR1_EXTI1_Pos

#define SYSCFG_EXTICR1_EXTI1_Pos (4U)

◆ SYSCFG_EXTICR1_EXTI2

#define SYSCFG_EXTICR1_EXTI2 SYSCFG_EXTICR1_EXTI2_Msk

EXTI 2 configuration

◆ SYSCFG_EXTICR1_EXTI2_Msk

#define SYSCFG_EXTICR1_EXTI2_Msk (0xFUL << SYSCFG_EXTICR1_EXTI2_Pos)

0x00000F00

◆ SYSCFG_EXTICR1_EXTI2_PA

#define SYSCFG_EXTICR1_EXTI2_PA (0x00000000U)

PA[2] pin

◆ SYSCFG_EXTICR1_EXTI2_PB

#define SYSCFG_EXTICR1_EXTI2_PB (0x00000100U)

PB[2] pin

◆ SYSCFG_EXTICR1_EXTI2_PC

#define SYSCFG_EXTICR1_EXTI2_PC (0x00000200U)

PC[2] pin

◆ SYSCFG_EXTICR1_EXTI2_PD

#define SYSCFG_EXTICR1_EXTI2_PD (0x00000300U)

PD[2] pin

◆ SYSCFG_EXTICR1_EXTI2_PE

#define SYSCFG_EXTICR1_EXTI2_PE (0x00000400U)

PE[2] pin

◆ SYSCFG_EXTICR1_EXTI2_PF

#define SYSCFG_EXTICR1_EXTI2_PF (0x00000500U)

PF[2] pin

◆ SYSCFG_EXTICR1_EXTI2_PG

#define SYSCFG_EXTICR1_EXTI2_PG (0x00000600U)

EXTI3 configuration.

PG[2] pin

◆ SYSCFG_EXTICR1_EXTI2_Pos

#define SYSCFG_EXTICR1_EXTI2_Pos (8U)

◆ SYSCFG_EXTICR1_EXTI3

#define SYSCFG_EXTICR1_EXTI3 SYSCFG_EXTICR1_EXTI3_Msk

EXTI0 configuration.

EXTI 3 configuration

◆ SYSCFG_EXTICR1_EXTI3_Msk

#define SYSCFG_EXTICR1_EXTI3_Msk (0xFUL << SYSCFG_EXTICR1_EXTI3_Pos)

0x0000F000

◆ SYSCFG_EXTICR1_EXTI3_PA

#define SYSCFG_EXTICR1_EXTI3_PA (0x00000000U)

PA[3] pin

◆ SYSCFG_EXTICR1_EXTI3_PB

#define SYSCFG_EXTICR1_EXTI3_PB (0x00001000U)

PB[3] pin

◆ SYSCFG_EXTICR1_EXTI3_PC

#define SYSCFG_EXTICR1_EXTI3_PC (0x00002000U)

PC[3] pin

◆ SYSCFG_EXTICR1_EXTI3_PD

#define SYSCFG_EXTICR1_EXTI3_PD (0x00003000U)

PD[3] pin

◆ SYSCFG_EXTICR1_EXTI3_PE

#define SYSCFG_EXTICR1_EXTI3_PE (0x00004000U)

PE[3] pin

◆ SYSCFG_EXTICR1_EXTI3_PF

#define SYSCFG_EXTICR1_EXTI3_PF (0x00005000U)

PE[3] pin

◆ SYSCFG_EXTICR1_EXTI3_PG

#define SYSCFG_EXTICR1_EXTI3_PG (0x00006000U)

PG[3] pin

◆ SYSCFG_EXTICR1_EXTI3_Pos

#define SYSCFG_EXTICR1_EXTI3_Pos (12U)

◆ SYSCFG_EXTICR2_EXTI4

#define SYSCFG_EXTICR2_EXTI4 SYSCFG_EXTICR2_EXTI4_Msk

EXTI 4 configuration

◆ SYSCFG_EXTICR2_EXTI4_Msk

#define SYSCFG_EXTICR2_EXTI4_Msk (0xFUL << SYSCFG_EXTICR2_EXTI4_Pos)

0x0000000F

◆ SYSCFG_EXTICR2_EXTI4_PA

#define SYSCFG_EXTICR2_EXTI4_PA (0x00000000U)

PA[4] pin

◆ SYSCFG_EXTICR2_EXTI4_PB

#define SYSCFG_EXTICR2_EXTI4_PB (0x00000001U)

PB[4] pin

◆ SYSCFG_EXTICR2_EXTI4_PC

#define SYSCFG_EXTICR2_EXTI4_PC (0x00000002U)

PC[4] pin

◆ SYSCFG_EXTICR2_EXTI4_PD

#define SYSCFG_EXTICR2_EXTI4_PD (0x00000003U)

PD[4] pin

◆ SYSCFG_EXTICR2_EXTI4_PE

#define SYSCFG_EXTICR2_EXTI4_PE (0x00000004U)

PE[4] pin

◆ SYSCFG_EXTICR2_EXTI4_PF

#define SYSCFG_EXTICR2_EXTI4_PF (0x00000005U)

PF[4] pin

◆ SYSCFG_EXTICR2_EXTI4_PG

#define SYSCFG_EXTICR2_EXTI4_PG (0x00000006U)

PG[4] pin

◆ SYSCFG_EXTICR2_EXTI4_PH

#define SYSCFG_EXTICR2_EXTI4_PH (0x00000007U)

EXTI5 configuration.

PH[4] pin

◆ SYSCFG_EXTICR2_EXTI4_Pos

#define SYSCFG_EXTICR2_EXTI4_Pos (0U)

◆ SYSCFG_EXTICR2_EXTI5

#define SYSCFG_EXTICR2_EXTI5 SYSCFG_EXTICR2_EXTI5_Msk

EXTI 5 configuration

◆ SYSCFG_EXTICR2_EXTI5_Msk

#define SYSCFG_EXTICR2_EXTI5_Msk (0xFUL << SYSCFG_EXTICR2_EXTI5_Pos)

0x000000F0

◆ SYSCFG_EXTICR2_EXTI5_PA

#define SYSCFG_EXTICR2_EXTI5_PA (0x00000000U)

PA[5] pin

◆ SYSCFG_EXTICR2_EXTI5_PB

#define SYSCFG_EXTICR2_EXTI5_PB (0x00000010U)

PB[5] pin

◆ SYSCFG_EXTICR2_EXTI5_PC

#define SYSCFG_EXTICR2_EXTI5_PC (0x00000020U)

PC[5] pin

◆ SYSCFG_EXTICR2_EXTI5_PD

#define SYSCFG_EXTICR2_EXTI5_PD (0x00000030U)

PD[5] pin

◆ SYSCFG_EXTICR2_EXTI5_PE

#define SYSCFG_EXTICR2_EXTI5_PE (0x00000040U)

PE[5] pin

◆ SYSCFG_EXTICR2_EXTI5_PF

#define SYSCFG_EXTICR2_EXTI5_PF (0x00000050U)

PF[5] pin

◆ SYSCFG_EXTICR2_EXTI5_PG

#define SYSCFG_EXTICR2_EXTI5_PG (0x00000060U)

EXTI6 configuration.

PG[5] pin

◆ SYSCFG_EXTICR2_EXTI5_Pos

#define SYSCFG_EXTICR2_EXTI5_Pos (4U)

◆ SYSCFG_EXTICR2_EXTI6

#define SYSCFG_EXTICR2_EXTI6 SYSCFG_EXTICR2_EXTI6_Msk

EXTI 6 configuration

◆ SYSCFG_EXTICR2_EXTI6_Msk

#define SYSCFG_EXTICR2_EXTI6_Msk (0xFUL << SYSCFG_EXTICR2_EXTI6_Pos)

0x00000F00

◆ SYSCFG_EXTICR2_EXTI6_PA

#define SYSCFG_EXTICR2_EXTI6_PA (0x00000000U)

PA[6] pin

◆ SYSCFG_EXTICR2_EXTI6_PB

#define SYSCFG_EXTICR2_EXTI6_PB (0x00000100U)

PB[6] pin

◆ SYSCFG_EXTICR2_EXTI6_PC

#define SYSCFG_EXTICR2_EXTI6_PC (0x00000200U)

PC[6] pin

◆ SYSCFG_EXTICR2_EXTI6_PD

#define SYSCFG_EXTICR2_EXTI6_PD (0x00000300U)

PD[6] pin

◆ SYSCFG_EXTICR2_EXTI6_PE

#define SYSCFG_EXTICR2_EXTI6_PE (0x00000400U)

PE[6] pin

◆ SYSCFG_EXTICR2_EXTI6_PF

#define SYSCFG_EXTICR2_EXTI6_PF (0x00000500U)

PF[6] pin

◆ SYSCFG_EXTICR2_EXTI6_PG

#define SYSCFG_EXTICR2_EXTI6_PG (0x00000600U)

EXTI7 configuration.

PG[6] pin

◆ SYSCFG_EXTICR2_EXTI6_Pos

#define SYSCFG_EXTICR2_EXTI6_Pos (8U)

◆ SYSCFG_EXTICR2_EXTI7

#define SYSCFG_EXTICR2_EXTI7 SYSCFG_EXTICR2_EXTI7_Msk

EXTI4 configuration.

EXTI 7 configuration

◆ SYSCFG_EXTICR2_EXTI7_Msk

#define SYSCFG_EXTICR2_EXTI7_Msk (0xFUL << SYSCFG_EXTICR2_EXTI7_Pos)

0x0000F000

◆ SYSCFG_EXTICR2_EXTI7_PA

#define SYSCFG_EXTICR2_EXTI7_PA (0x00000000U)

PA[7] pin

◆ SYSCFG_EXTICR2_EXTI7_PB

#define SYSCFG_EXTICR2_EXTI7_PB (0x00001000U)

PB[7] pin

◆ SYSCFG_EXTICR2_EXTI7_PC

#define SYSCFG_EXTICR2_EXTI7_PC (0x00002000U)

PC[7] pin

◆ SYSCFG_EXTICR2_EXTI7_PD

#define SYSCFG_EXTICR2_EXTI7_PD (0x00003000U)

PD[7] pin

◆ SYSCFG_EXTICR2_EXTI7_PE

#define SYSCFG_EXTICR2_EXTI7_PE (0x00004000U)

PE[7] pin

◆ SYSCFG_EXTICR2_EXTI7_PF

#define SYSCFG_EXTICR2_EXTI7_PF (0x00005000U)

PF[7] pin

◆ SYSCFG_EXTICR2_EXTI7_PG

#define SYSCFG_EXTICR2_EXTI7_PG (0x00006000U)

PG[7] pin

◆ SYSCFG_EXTICR2_EXTI7_Pos

#define SYSCFG_EXTICR2_EXTI7_Pos (12U)

◆ SYSCFG_EXTICR3_EXTI10

#define SYSCFG_EXTICR3_EXTI10 SYSCFG_EXTICR3_EXTI10_Msk

EXTI 10 configuration

◆ SYSCFG_EXTICR3_EXTI10_Msk

#define SYSCFG_EXTICR3_EXTI10_Msk (0xFUL << SYSCFG_EXTICR3_EXTI10_Pos)

0x00000F00

◆ SYSCFG_EXTICR3_EXTI10_PA

#define SYSCFG_EXTICR3_EXTI10_PA (0x00000000U)

PA[10] pin

◆ SYSCFG_EXTICR3_EXTI10_PB

#define SYSCFG_EXTICR3_EXTI10_PB (0x00000100U)

PB[10] pin

◆ SYSCFG_EXTICR3_EXTI10_PC

#define SYSCFG_EXTICR3_EXTI10_PC (0x00000200U)

PC[10] pin

◆ SYSCFG_EXTICR3_EXTI10_PD

#define SYSCFG_EXTICR3_EXTI10_PD (0x00000300U)

PD[10] pin

◆ SYSCFG_EXTICR3_EXTI10_PE

#define SYSCFG_EXTICR3_EXTI10_PE (0x00000400U)

PE[10] pin

◆ SYSCFG_EXTICR3_EXTI10_PF

#define SYSCFG_EXTICR3_EXTI10_PF (0x00000500U)

PF[10] pin

◆ SYSCFG_EXTICR3_EXTI10_PG

#define SYSCFG_EXTICR3_EXTI10_PG (0x00000600U)

EXTI11 configuration.

PG[10] pin

◆ SYSCFG_EXTICR3_EXTI10_Pos

#define SYSCFG_EXTICR3_EXTI10_Pos (8U)

◆ SYSCFG_EXTICR3_EXTI11

#define SYSCFG_EXTICR3_EXTI11 SYSCFG_EXTICR3_EXTI11_Msk

EXTI8 configuration.

EXTI 11 configuration

◆ SYSCFG_EXTICR3_EXTI11_Msk

#define SYSCFG_EXTICR3_EXTI11_Msk (0xFUL << SYSCFG_EXTICR3_EXTI11_Pos)

0x0000F000

◆ SYSCFG_EXTICR3_EXTI11_PA

#define SYSCFG_EXTICR3_EXTI11_PA (0x00000000U)

PA[11] pin

◆ SYSCFG_EXTICR3_EXTI11_PB

#define SYSCFG_EXTICR3_EXTI11_PB (0x00001000U)

PB[11] pin

◆ SYSCFG_EXTICR3_EXTI11_PC

#define SYSCFG_EXTICR3_EXTI11_PC (0x00002000U)

PC[11] pin

◆ SYSCFG_EXTICR3_EXTI11_PD

#define SYSCFG_EXTICR3_EXTI11_PD (0x00003000U)

PD[11] pin

◆ SYSCFG_EXTICR3_EXTI11_PE

#define SYSCFG_EXTICR3_EXTI11_PE (0x00004000U)

PE[11] pin

◆ SYSCFG_EXTICR3_EXTI11_PF

#define SYSCFG_EXTICR3_EXTI11_PF (0x00005000U)

PF[11] pin

◆ SYSCFG_EXTICR3_EXTI11_PG

#define SYSCFG_EXTICR3_EXTI11_PG (0x00006000U)

PG[11] pin

◆ SYSCFG_EXTICR3_EXTI11_Pos

#define SYSCFG_EXTICR3_EXTI11_Pos (12U)

◆ SYSCFG_EXTICR3_EXTI8

#define SYSCFG_EXTICR3_EXTI8 SYSCFG_EXTICR3_EXTI8_Msk

EXTI 8 configuration

◆ SYSCFG_EXTICR3_EXTI8_Msk

#define SYSCFG_EXTICR3_EXTI8_Msk (0xFUL << SYSCFG_EXTICR3_EXTI8_Pos)

0x0000000F

◆ SYSCFG_EXTICR3_EXTI8_PA

#define SYSCFG_EXTICR3_EXTI8_PA (0x00000000U)

PA[8] pin

◆ SYSCFG_EXTICR3_EXTI8_PB

#define SYSCFG_EXTICR3_EXTI8_PB (0x00000001U)

PB[8] pin

◆ SYSCFG_EXTICR3_EXTI8_PC

#define SYSCFG_EXTICR3_EXTI8_PC (0x00000002U)

PC[8] pin

◆ SYSCFG_EXTICR3_EXTI8_PD

#define SYSCFG_EXTICR3_EXTI8_PD (0x00000003U)

PD[8] pin

◆ SYSCFG_EXTICR3_EXTI8_PE

#define SYSCFG_EXTICR3_EXTI8_PE (0x00000004U)

PE[8] pin

◆ SYSCFG_EXTICR3_EXTI8_PF

#define SYSCFG_EXTICR3_EXTI8_PF (0x00000005U)

PF[8] pin

◆ SYSCFG_EXTICR3_EXTI8_PG

#define SYSCFG_EXTICR3_EXTI8_PG (0x00000006U)

EXTI9 configuration.

PG[8] pin

◆ SYSCFG_EXTICR3_EXTI8_Pos

#define SYSCFG_EXTICR3_EXTI8_Pos (0U)

◆ SYSCFG_EXTICR3_EXTI9

#define SYSCFG_EXTICR3_EXTI9 SYSCFG_EXTICR3_EXTI9_Msk

EXTI 9 configuration

◆ SYSCFG_EXTICR3_EXTI9_Msk

#define SYSCFG_EXTICR3_EXTI9_Msk (0xFUL << SYSCFG_EXTICR3_EXTI9_Pos)

0x000000F0

◆ SYSCFG_EXTICR3_EXTI9_PA

#define SYSCFG_EXTICR3_EXTI9_PA (0x00000000U)

PA[9] pin

◆ SYSCFG_EXTICR3_EXTI9_PB

#define SYSCFG_EXTICR3_EXTI9_PB (0x00000010U)

PB[9] pin

◆ SYSCFG_EXTICR3_EXTI9_PC

#define SYSCFG_EXTICR3_EXTI9_PC (0x00000020U)

PC[9] pin

◆ SYSCFG_EXTICR3_EXTI9_PD

#define SYSCFG_EXTICR3_EXTI9_PD (0x00000030U)

PD[9] pin

◆ SYSCFG_EXTICR3_EXTI9_PE

#define SYSCFG_EXTICR3_EXTI9_PE (0x00000040U)

PE[9] pin

◆ SYSCFG_EXTICR3_EXTI9_PF

#define SYSCFG_EXTICR3_EXTI9_PF (0x00000050U)

PF[9] pin

◆ SYSCFG_EXTICR3_EXTI9_PG

#define SYSCFG_EXTICR3_EXTI9_PG (0x00000060U)

EXTI10 configuration.

PG[9] pin

◆ SYSCFG_EXTICR3_EXTI9_Pos

#define SYSCFG_EXTICR3_EXTI9_Pos (4U)

◆ SYSCFG_EXTICR4_EXTI12

#define SYSCFG_EXTICR4_EXTI12 SYSCFG_EXTICR4_EXTI12_Msk

EXTI 12 configuration

◆ SYSCFG_EXTICR4_EXTI12_Msk

#define SYSCFG_EXTICR4_EXTI12_Msk (0xFUL << SYSCFG_EXTICR4_EXTI12_Pos)

0x0000000F

◆ SYSCFG_EXTICR4_EXTI12_PA

#define SYSCFG_EXTICR4_EXTI12_PA (0x00000000U)

PA[12] pin

◆ SYSCFG_EXTICR4_EXTI12_PB

#define SYSCFG_EXTICR4_EXTI12_PB (0x00000001U)

PB[12] pin

◆ SYSCFG_EXTICR4_EXTI12_PC

#define SYSCFG_EXTICR4_EXTI12_PC (0x00000002U)

PC[12] pin

◆ SYSCFG_EXTICR4_EXTI12_PD

#define SYSCFG_EXTICR4_EXTI12_PD (0x00000003U)

PD[12] pin

◆ SYSCFG_EXTICR4_EXTI12_PE

#define SYSCFG_EXTICR4_EXTI12_PE (0x00000004U)

PE[12] pin

◆ SYSCFG_EXTICR4_EXTI12_PF

#define SYSCFG_EXTICR4_EXTI12_PF (0x00000005U)

PF[12] pin

◆ SYSCFG_EXTICR4_EXTI12_PG

#define SYSCFG_EXTICR4_EXTI12_PG (0x00000006U)

EXTI13 configuration.

PG[12] pin

◆ SYSCFG_EXTICR4_EXTI12_Pos

#define SYSCFG_EXTICR4_EXTI12_Pos (0U)

◆ SYSCFG_EXTICR4_EXTI13

#define SYSCFG_EXTICR4_EXTI13 SYSCFG_EXTICR4_EXTI13_Msk

EXTI 13 configuration

◆ SYSCFG_EXTICR4_EXTI13_Msk

#define SYSCFG_EXTICR4_EXTI13_Msk (0xFUL << SYSCFG_EXTICR4_EXTI13_Pos)

0x000000F0

◆ SYSCFG_EXTICR4_EXTI13_PA

#define SYSCFG_EXTICR4_EXTI13_PA (0x00000000U)

PA[13] pin

◆ SYSCFG_EXTICR4_EXTI13_PB

#define SYSCFG_EXTICR4_EXTI13_PB (0x00000010U)

PB[13] pin

◆ SYSCFG_EXTICR4_EXTI13_PC

#define SYSCFG_EXTICR4_EXTI13_PC (0x00000020U)

PC[13] pin

◆ SYSCFG_EXTICR4_EXTI13_PD

#define SYSCFG_EXTICR4_EXTI13_PD (0x00000030U)

PD[13] pin

◆ SYSCFG_EXTICR4_EXTI13_PE

#define SYSCFG_EXTICR4_EXTI13_PE (0x00000040U)

PE[13] pin

◆ SYSCFG_EXTICR4_EXTI13_PF

#define SYSCFG_EXTICR4_EXTI13_PF (0x00000050U)

PF[13] pin

◆ SYSCFG_EXTICR4_EXTI13_PG

#define SYSCFG_EXTICR4_EXTI13_PG (0x00000060U)

EXTI14 configuration.

PG[13] pin

◆ SYSCFG_EXTICR4_EXTI13_Pos

#define SYSCFG_EXTICR4_EXTI13_Pos (4U)

◆ SYSCFG_EXTICR4_EXTI14

#define SYSCFG_EXTICR4_EXTI14 SYSCFG_EXTICR4_EXTI14_Msk

EXTI 14 configuration

◆ SYSCFG_EXTICR4_EXTI14_Msk

#define SYSCFG_EXTICR4_EXTI14_Msk (0xFUL << SYSCFG_EXTICR4_EXTI14_Pos)

0x00000F00

◆ SYSCFG_EXTICR4_EXTI14_PA

#define SYSCFG_EXTICR4_EXTI14_PA (0x00000000U)

PA[14] pin

◆ SYSCFG_EXTICR4_EXTI14_PB

#define SYSCFG_EXTICR4_EXTI14_PB (0x00000100U)

PB[14] pin

◆ SYSCFG_EXTICR4_EXTI14_PC

#define SYSCFG_EXTICR4_EXTI14_PC (0x00000200U)

PC[14] pin

◆ SYSCFG_EXTICR4_EXTI14_PD

#define SYSCFG_EXTICR4_EXTI14_PD (0x00000300U)

PD[14] pin

◆ SYSCFG_EXTICR4_EXTI14_PE

#define SYSCFG_EXTICR4_EXTI14_PE (0x00000400U)

PE[14] pin

◆ SYSCFG_EXTICR4_EXTI14_PF

#define SYSCFG_EXTICR4_EXTI14_PF (0x00000500U)

PF[14] pin

◆ SYSCFG_EXTICR4_EXTI14_PG

#define SYSCFG_EXTICR4_EXTI14_PG (0x00000600U)

EXTI15 configuration.

PG[14] pin

◆ SYSCFG_EXTICR4_EXTI14_Pos

#define SYSCFG_EXTICR4_EXTI14_Pos (8U)

◆ SYSCFG_EXTICR4_EXTI15

#define SYSCFG_EXTICR4_EXTI15 SYSCFG_EXTICR4_EXTI15_Msk

EXTI12 configuration.

EXTI 15 configuration

◆ SYSCFG_EXTICR4_EXTI15_Msk

#define SYSCFG_EXTICR4_EXTI15_Msk (0xFUL << SYSCFG_EXTICR4_EXTI15_Pos)

0x0000F000

◆ SYSCFG_EXTICR4_EXTI15_PA

#define SYSCFG_EXTICR4_EXTI15_PA (0x00000000U)

PA[15] pin

◆ SYSCFG_EXTICR4_EXTI15_PB

#define SYSCFG_EXTICR4_EXTI15_PB (0x00001000U)

PB[15] pin

◆ SYSCFG_EXTICR4_EXTI15_PC

#define SYSCFG_EXTICR4_EXTI15_PC (0x00002000U)

PC[15] pin

◆ SYSCFG_EXTICR4_EXTI15_PD

#define SYSCFG_EXTICR4_EXTI15_PD (0x00003000U)

PD[15] pin

◆ SYSCFG_EXTICR4_EXTI15_PE

#define SYSCFG_EXTICR4_EXTI15_PE (0x00004000U)

PE[15] pin

◆ SYSCFG_EXTICR4_EXTI15_PF

#define SYSCFG_EXTICR4_EXTI15_PF (0x00005000U)

PF[15] pin

◆ SYSCFG_EXTICR4_EXTI15_PG

#define SYSCFG_EXTICR4_EXTI15_PG (0x00006000U)

PG[15] pin

◆ SYSCFG_EXTICR4_EXTI15_Pos

#define SYSCFG_EXTICR4_EXTI15_Pos (12U)

◆ SYSCFG_RCR_PAGE0

#define SYSCFG_RCR_PAGE0 SYSCFG_RCR_PAGE0_Msk

ICODE SRAM Write protection page 0

◆ SYSCFG_RCR_PAGE0_Msk

#define SYSCFG_RCR_PAGE0_Msk (0x1UL << SYSCFG_RCR_PAGE0_Pos)

0x00000001

◆ SYSCFG_RCR_PAGE0_Pos

#define SYSCFG_RCR_PAGE0_Pos (0U)

◆ SYSCFG_RCR_PAGE1

#define SYSCFG_RCR_PAGE1 SYSCFG_RCR_PAGE1_Msk

ICODE SRAM Write protection page 1

◆ SYSCFG_RCR_PAGE10

#define SYSCFG_RCR_PAGE10 SYSCFG_RCR_PAGE10_Msk

ICODE SRAM Write protection page 10

◆ SYSCFG_RCR_PAGE10_Msk

#define SYSCFG_RCR_PAGE10_Msk (0x1UL << SYSCFG_RCR_PAGE10_Pos)

0x00000400

◆ SYSCFG_RCR_PAGE10_Pos

#define SYSCFG_RCR_PAGE10_Pos (10U)

◆ SYSCFG_RCR_PAGE11

#define SYSCFG_RCR_PAGE11 SYSCFG_RCR_PAGE11_Msk

ICODE SRAM Write protection page 11

◆ SYSCFG_RCR_PAGE11_Msk

#define SYSCFG_RCR_PAGE11_Msk (0x1UL << SYSCFG_RCR_PAGE11_Pos)

0x00000800

◆ SYSCFG_RCR_PAGE11_Pos

#define SYSCFG_RCR_PAGE11_Pos (11U)

◆ SYSCFG_RCR_PAGE12

#define SYSCFG_RCR_PAGE12 SYSCFG_RCR_PAGE12_Msk

ICODE SRAM Write protection page 12

◆ SYSCFG_RCR_PAGE12_Msk

#define SYSCFG_RCR_PAGE12_Msk (0x1UL << SYSCFG_RCR_PAGE12_Pos)

0x00001000

◆ SYSCFG_RCR_PAGE12_Pos

#define SYSCFG_RCR_PAGE12_Pos (12U)

◆ SYSCFG_RCR_PAGE13

#define SYSCFG_RCR_PAGE13 SYSCFG_RCR_PAGE13_Msk

ICODE SRAM Write protection page 13

◆ SYSCFG_RCR_PAGE13_Msk

#define SYSCFG_RCR_PAGE13_Msk (0x1UL << SYSCFG_RCR_PAGE13_Pos)

0x00002000

◆ SYSCFG_RCR_PAGE13_Pos

#define SYSCFG_RCR_PAGE13_Pos (13U)

◆ SYSCFG_RCR_PAGE14

#define SYSCFG_RCR_PAGE14 SYSCFG_RCR_PAGE14_Msk

ICODE SRAM Write protection page 14

◆ SYSCFG_RCR_PAGE14_Msk

#define SYSCFG_RCR_PAGE14_Msk (0x1UL << SYSCFG_RCR_PAGE14_Pos)

0x00004000

◆ SYSCFG_RCR_PAGE14_Pos

#define SYSCFG_RCR_PAGE14_Pos (14U)

◆ SYSCFG_RCR_PAGE15

#define SYSCFG_RCR_PAGE15 SYSCFG_RCR_PAGE15_Msk

ICODE SRAM Write protection page 15

◆ SYSCFG_RCR_PAGE15_Msk

#define SYSCFG_RCR_PAGE15_Msk (0x1UL << SYSCFG_RCR_PAGE15_Pos)

0x00008000

◆ SYSCFG_RCR_PAGE15_Pos

#define SYSCFG_RCR_PAGE15_Pos (15U)

◆ SYSCFG_RCR_PAGE1_Msk

#define SYSCFG_RCR_PAGE1_Msk (0x1UL << SYSCFG_RCR_PAGE1_Pos)

0x00000002

◆ SYSCFG_RCR_PAGE1_Pos

#define SYSCFG_RCR_PAGE1_Pos (1U)

◆ SYSCFG_RCR_PAGE2

#define SYSCFG_RCR_PAGE2 SYSCFG_RCR_PAGE2_Msk

ICODE SRAM Write protection page 2

◆ SYSCFG_RCR_PAGE2_Msk

#define SYSCFG_RCR_PAGE2_Msk (0x1UL << SYSCFG_RCR_PAGE2_Pos)

0x00000004

◆ SYSCFG_RCR_PAGE2_Pos

#define SYSCFG_RCR_PAGE2_Pos (2U)

◆ SYSCFG_RCR_PAGE3

#define SYSCFG_RCR_PAGE3 SYSCFG_RCR_PAGE3_Msk

ICODE SRAM Write protection page 3

◆ SYSCFG_RCR_PAGE3_Msk

#define SYSCFG_RCR_PAGE3_Msk (0x1UL << SYSCFG_RCR_PAGE3_Pos)

0x00000008

◆ SYSCFG_RCR_PAGE3_Pos

#define SYSCFG_RCR_PAGE3_Pos (3U)

◆ SYSCFG_RCR_PAGE4

#define SYSCFG_RCR_PAGE4 SYSCFG_RCR_PAGE4_Msk

ICODE SRAM Write protection page 4

◆ SYSCFG_RCR_PAGE4_Msk

#define SYSCFG_RCR_PAGE4_Msk (0x1UL << SYSCFG_RCR_PAGE4_Pos)

0x00000010

◆ SYSCFG_RCR_PAGE4_Pos

#define SYSCFG_RCR_PAGE4_Pos (4U)

◆ SYSCFG_RCR_PAGE5

#define SYSCFG_RCR_PAGE5 SYSCFG_RCR_PAGE5_Msk

ICODE SRAM Write protection page 5

◆ SYSCFG_RCR_PAGE5_Msk

#define SYSCFG_RCR_PAGE5_Msk (0x1UL << SYSCFG_RCR_PAGE5_Pos)

0x00000020

◆ SYSCFG_RCR_PAGE5_Pos

#define SYSCFG_RCR_PAGE5_Pos (5U)

◆ SYSCFG_RCR_PAGE6

#define SYSCFG_RCR_PAGE6 SYSCFG_RCR_PAGE6_Msk

ICODE SRAM Write protection page 6

◆ SYSCFG_RCR_PAGE6_Msk

#define SYSCFG_RCR_PAGE6_Msk (0x1UL << SYSCFG_RCR_PAGE6_Pos)

0x00000040

◆ SYSCFG_RCR_PAGE6_Pos

#define SYSCFG_RCR_PAGE6_Pos (6U)

◆ SYSCFG_RCR_PAGE7

#define SYSCFG_RCR_PAGE7 SYSCFG_RCR_PAGE7_Msk

ICODE SRAM Write protection page 7

◆ SYSCFG_RCR_PAGE7_Msk

#define SYSCFG_RCR_PAGE7_Msk (0x1UL << SYSCFG_RCR_PAGE7_Pos)

0x00000080

◆ SYSCFG_RCR_PAGE7_Pos

#define SYSCFG_RCR_PAGE7_Pos (7U)

◆ SYSCFG_RCR_PAGE8

#define SYSCFG_RCR_PAGE8 SYSCFG_RCR_PAGE8_Msk

ICODE SRAM Write protection page 8

◆ SYSCFG_RCR_PAGE8_Msk

#define SYSCFG_RCR_PAGE8_Msk (0x1UL << SYSCFG_RCR_PAGE8_Pos)

0x00000100

◆ SYSCFG_RCR_PAGE8_Pos

#define SYSCFG_RCR_PAGE8_Pos (8U)

◆ SYSCFG_RCR_PAGE9

#define SYSCFG_RCR_PAGE9 SYSCFG_RCR_PAGE9_Msk

ICODE SRAM Write protection page 9

◆ SYSCFG_RCR_PAGE9_Msk

#define SYSCFG_RCR_PAGE9_Msk (0x1UL << SYSCFG_RCR_PAGE9_Pos)

0x00000200

◆ SYSCFG_RCR_PAGE9_Pos

#define SYSCFG_RCR_PAGE9_Pos (9U)

◆ TIM16_OR_TI1_RMP

#define TIM16_OR_TI1_RMP TIM16_OR_TI1_RMP_Msk

TI1_RMP[1:0] bits (TIM16 Input 1 remap)

◆ TIM16_OR_TI1_RMP_0

#define TIM16_OR_TI1_RMP_0 (0x1UL << TIM16_OR_TI1_RMP_Pos)

0x00000001

◆ TIM16_OR_TI1_RMP_1

#define TIM16_OR_TI1_RMP_1 (0x2UL << TIM16_OR_TI1_RMP_Pos)

0x00000002

◆ TIM16_OR_TI1_RMP_Msk

#define TIM16_OR_TI1_RMP_Msk (0x3UL << TIM16_OR_TI1_RMP_Pos)

0x00000003

◆ TIM16_OR_TI1_RMP_Pos

#define TIM16_OR_TI1_RMP_Pos (0U)

◆ TIM1_OR_ETR_RMP

#define TIM1_OR_ETR_RMP TIM1_OR_ETR_RMP_Msk

ETR_RMP[3:0] bits (TIM1 ETR remap)

◆ TIM1_OR_ETR_RMP_0

#define TIM1_OR_ETR_RMP_0 (0x1UL << TIM1_OR_ETR_RMP_Pos)

0x00000001

◆ TIM1_OR_ETR_RMP_1

#define TIM1_OR_ETR_RMP_1 (0x2UL << TIM1_OR_ETR_RMP_Pos)

0x00000002

◆ TIM1_OR_ETR_RMP_2

#define TIM1_OR_ETR_RMP_2 (0x4UL << TIM1_OR_ETR_RMP_Pos)

0x00000004

◆ TIM1_OR_ETR_RMP_3

#define TIM1_OR_ETR_RMP_3 (0x8UL << TIM1_OR_ETR_RMP_Pos)

0x00000008

◆ TIM1_OR_ETR_RMP_Msk

#define TIM1_OR_ETR_RMP_Msk (0xFUL << TIM1_OR_ETR_RMP_Pos)

0x0000000F

◆ TIM1_OR_ETR_RMP_Pos

#define TIM1_OR_ETR_RMP_Pos (0U)

◆ TIM20_OR_ETR_RMP

#define TIM20_OR_ETR_RMP TIM20_OR_ETR_RMP_Msk

ETR_RMP[3:0] bits (TIM20 ETR remap)

◆ TIM20_OR_ETR_RMP_0

#define TIM20_OR_ETR_RMP_0 (0x1UL << TIM20_OR_ETR_RMP_Pos)

0x00000001

◆ TIM20_OR_ETR_RMP_1

#define TIM20_OR_ETR_RMP_1 (0x2UL << TIM20_OR_ETR_RMP_Pos)

0x00000002

◆ TIM20_OR_ETR_RMP_2

#define TIM20_OR_ETR_RMP_2 (0x4UL << TIM20_OR_ETR_RMP_Pos)

0x00000004

◆ TIM20_OR_ETR_RMP_3

#define TIM20_OR_ETR_RMP_3 (0x8UL << TIM20_OR_ETR_RMP_Pos)

0x00000008

◆ TIM20_OR_ETR_RMP_Msk

#define TIM20_OR_ETR_RMP_Msk (0xFUL << TIM20_OR_ETR_RMP_Pos)

0x0000000F

◆ TIM20_OR_ETR_RMP_Pos

#define TIM20_OR_ETR_RMP_Pos (0U)

◆ TIM8_OR_ETR_RMP

#define TIM8_OR_ETR_RMP TIM8_OR_ETR_RMP_Msk

ETR_RMP[3:0] bits (TIM8 ETR remap)

◆ TIM8_OR_ETR_RMP_0

#define TIM8_OR_ETR_RMP_0 (0x1UL << TIM8_OR_ETR_RMP_Pos)

0x00000001

◆ TIM8_OR_ETR_RMP_1

#define TIM8_OR_ETR_RMP_1 (0x2UL << TIM8_OR_ETR_RMP_Pos)

0x00000002

◆ TIM8_OR_ETR_RMP_2

#define TIM8_OR_ETR_RMP_2 (0x4UL << TIM8_OR_ETR_RMP_Pos)

0x00000004

◆ TIM8_OR_ETR_RMP_3

#define TIM8_OR_ETR_RMP_3 (0x8UL << TIM8_OR_ETR_RMP_Pos)

0x00000008

◆ TIM8_OR_ETR_RMP_Msk

#define TIM8_OR_ETR_RMP_Msk (0xFUL << TIM8_OR_ETR_RMP_Pos)

0x0000000F

◆ TIM8_OR_ETR_RMP_Pos

#define TIM8_OR_ETR_RMP_Pos (0U)

◆ TIM_ARR_ARR

#define TIM_ARR_ARR TIM_ARR_ARR_Msk

actual auto-reload Value

◆ TIM_ARR_ARR_Msk

#define TIM_ARR_ARR_Msk (0xFFFFFFFFUL << TIM_ARR_ARR_Pos)

0xFFFFFFFF

◆ TIM_ARR_ARR_Pos

#define TIM_ARR_ARR_Pos (0U)

◆ TIM_BDTR_AOE

#define TIM_BDTR_AOE TIM_BDTR_AOE_Msk

Automatic Output enable

◆ TIM_BDTR_AOE_Msk

#define TIM_BDTR_AOE_Msk (0x1UL << TIM_BDTR_AOE_Pos)

0x00004000

◆ TIM_BDTR_AOE_Pos

#define TIM_BDTR_AOE_Pos (14U)

◆ TIM_BDTR_BK2E

#define TIM_BDTR_BK2E TIM_BDTR_BK2E_Msk

Break enable for Break2

◆ TIM_BDTR_BK2E_Msk

#define TIM_BDTR_BK2E_Msk (0x1UL << TIM_BDTR_BK2E_Pos)

0x01000000

◆ TIM_BDTR_BK2E_Pos

#define TIM_BDTR_BK2E_Pos (24U)

◆ TIM_BDTR_BK2F

#define TIM_BDTR_BK2F TIM_BDTR_BK2F_Msk

Break Filter for Break2

◆ TIM_BDTR_BK2F_Msk

#define TIM_BDTR_BK2F_Msk (0xFUL << TIM_BDTR_BK2F_Pos)

0x00F00000

◆ TIM_BDTR_BK2F_Pos

#define TIM_BDTR_BK2F_Pos (20U)

◆ TIM_BDTR_BK2P

#define TIM_BDTR_BK2P TIM_BDTR_BK2P_Msk

Break Polarity for Break2

◆ TIM_BDTR_BK2P_Msk

#define TIM_BDTR_BK2P_Msk (0x1UL << TIM_BDTR_BK2P_Pos)

0x02000000

◆ TIM_BDTR_BK2P_Pos

#define TIM_BDTR_BK2P_Pos (25U)

◆ TIM_BDTR_BKE

#define TIM_BDTR_BKE TIM_BDTR_BKE_Msk

Break enable for Break1

◆ TIM_BDTR_BKE_Msk

#define TIM_BDTR_BKE_Msk (0x1UL << TIM_BDTR_BKE_Pos)

0x00001000

◆ TIM_BDTR_BKE_Pos

#define TIM_BDTR_BKE_Pos (12U)

◆ TIM_BDTR_BKF

#define TIM_BDTR_BKF TIM_BDTR_BKF_Msk

Break Filter for Break1

◆ TIM_BDTR_BKF_Msk

#define TIM_BDTR_BKF_Msk (0xFUL << TIM_BDTR_BKF_Pos)

0x000F0000

◆ TIM_BDTR_BKF_Pos

#define TIM_BDTR_BKF_Pos (16U)

◆ TIM_BDTR_BKP

#define TIM_BDTR_BKP TIM_BDTR_BKP_Msk

Break Polarity for Break1

◆ TIM_BDTR_BKP_Msk

#define TIM_BDTR_BKP_Msk (0x1UL << TIM_BDTR_BKP_Pos)

0x00002000

◆ TIM_BDTR_BKP_Pos

#define TIM_BDTR_BKP_Pos (13U)

◆ TIM_BDTR_DTG

#define TIM_BDTR_DTG TIM_BDTR_DTG_Msk

DTG[0:7] bits (Dead-Time Generator set-up)

◆ TIM_BDTR_DTG_0

#define TIM_BDTR_DTG_0 (0x01UL << TIM_BDTR_DTG_Pos)

0x00000001

◆ TIM_BDTR_DTG_1

#define TIM_BDTR_DTG_1 (0x02UL << TIM_BDTR_DTG_Pos)

0x00000002

◆ TIM_BDTR_DTG_2

#define TIM_BDTR_DTG_2 (0x04UL << TIM_BDTR_DTG_Pos)

0x00000004

◆ TIM_BDTR_DTG_3

#define TIM_BDTR_DTG_3 (0x08UL << TIM_BDTR_DTG_Pos)

0x00000008

◆ TIM_BDTR_DTG_4

#define TIM_BDTR_DTG_4 (0x10UL << TIM_BDTR_DTG_Pos)

0x00000010

◆ TIM_BDTR_DTG_5

#define TIM_BDTR_DTG_5 (0x20UL << TIM_BDTR_DTG_Pos)

0x00000020

◆ TIM_BDTR_DTG_6

#define TIM_BDTR_DTG_6 (0x40UL << TIM_BDTR_DTG_Pos)

0x00000040

◆ TIM_BDTR_DTG_7

#define TIM_BDTR_DTG_7 (0x80UL << TIM_BDTR_DTG_Pos)

0x00000080

◆ TIM_BDTR_DTG_Msk

#define TIM_BDTR_DTG_Msk (0xFFUL << TIM_BDTR_DTG_Pos)

0x000000FF

◆ TIM_BDTR_DTG_Pos

#define TIM_BDTR_DTG_Pos (0U)

◆ TIM_BDTR_LOCK

#define TIM_BDTR_LOCK TIM_BDTR_LOCK_Msk

LOCK[1:0] bits (Lock Configuration)

◆ TIM_BDTR_LOCK_0

#define TIM_BDTR_LOCK_0 (0x1UL << TIM_BDTR_LOCK_Pos)

0x00000100

◆ TIM_BDTR_LOCK_1

#define TIM_BDTR_LOCK_1 (0x2UL << TIM_BDTR_LOCK_Pos)

0x00000200

◆ TIM_BDTR_LOCK_Msk

#define TIM_BDTR_LOCK_Msk (0x3UL << TIM_BDTR_LOCK_Pos)

0x00000300

◆ TIM_BDTR_LOCK_Pos

#define TIM_BDTR_LOCK_Pos (8U)

◆ TIM_BDTR_MOE

#define TIM_BDTR_MOE TIM_BDTR_MOE_Msk

Main Output enable

◆ TIM_BDTR_MOE_Msk

#define TIM_BDTR_MOE_Msk (0x1UL << TIM_BDTR_MOE_Pos)

0x00008000

◆ TIM_BDTR_MOE_Pos

#define TIM_BDTR_MOE_Pos (15U)

◆ TIM_BDTR_OSSI

#define TIM_BDTR_OSSI TIM_BDTR_OSSI_Msk

Off-State Selection for Idle mode

◆ TIM_BDTR_OSSI_Msk

#define TIM_BDTR_OSSI_Msk (0x1UL << TIM_BDTR_OSSI_Pos)

0x00000400

◆ TIM_BDTR_OSSI_Pos

#define TIM_BDTR_OSSI_Pos (10U)

◆ TIM_BDTR_OSSR

#define TIM_BDTR_OSSR TIM_BDTR_OSSR_Msk

Off-State Selection for Run mode

◆ TIM_BDTR_OSSR_Msk

#define TIM_BDTR_OSSR_Msk (0x1UL << TIM_BDTR_OSSR_Pos)

0x00000800

◆ TIM_BDTR_OSSR_Pos

#define TIM_BDTR_OSSR_Pos (11U)

◆ TIM_CCER_CC1E

#define TIM_CCER_CC1E TIM_CCER_CC1E_Msk

Capture/Compare 1 output enable

◆ TIM_CCER_CC1E_Msk

#define TIM_CCER_CC1E_Msk (0x1UL << TIM_CCER_CC1E_Pos)

0x00000001

◆ TIM_CCER_CC1E_Pos

#define TIM_CCER_CC1E_Pos (0U)

◆ TIM_CCER_CC1NE

#define TIM_CCER_CC1NE TIM_CCER_CC1NE_Msk

Capture/Compare 1 Complementary output enable

◆ TIM_CCER_CC1NE_Msk

#define TIM_CCER_CC1NE_Msk (0x1UL << TIM_CCER_CC1NE_Pos)

0x00000004

◆ TIM_CCER_CC1NE_Pos

#define TIM_CCER_CC1NE_Pos (2U)

◆ TIM_CCER_CC1NP

#define TIM_CCER_CC1NP TIM_CCER_CC1NP_Msk

Capture/Compare 1 Complementary output Polarity

◆ TIM_CCER_CC1NP_Msk

#define TIM_CCER_CC1NP_Msk (0x1UL << TIM_CCER_CC1NP_Pos)

0x00000008

◆ TIM_CCER_CC1NP_Pos

#define TIM_CCER_CC1NP_Pos (3U)

◆ TIM_CCER_CC1P

#define TIM_CCER_CC1P TIM_CCER_CC1P_Msk

Capture/Compare 1 output Polarity

◆ TIM_CCER_CC1P_Msk

#define TIM_CCER_CC1P_Msk (0x1UL << TIM_CCER_CC1P_Pos)

0x00000002

◆ TIM_CCER_CC1P_Pos

#define TIM_CCER_CC1P_Pos (1U)

◆ TIM_CCER_CC2E

#define TIM_CCER_CC2E TIM_CCER_CC2E_Msk

Capture/Compare 2 output enable

◆ TIM_CCER_CC2E_Msk

#define TIM_CCER_CC2E_Msk (0x1UL << TIM_CCER_CC2E_Pos)

0x00000010

◆ TIM_CCER_CC2E_Pos

#define TIM_CCER_CC2E_Pos (4U)

◆ TIM_CCER_CC2NE

#define TIM_CCER_CC2NE TIM_CCER_CC2NE_Msk

Capture/Compare 2 Complementary output enable

◆ TIM_CCER_CC2NE_Msk

#define TIM_CCER_CC2NE_Msk (0x1UL << TIM_CCER_CC2NE_Pos)

0x00000040

◆ TIM_CCER_CC2NE_Pos

#define TIM_CCER_CC2NE_Pos (6U)

◆ TIM_CCER_CC2NP

#define TIM_CCER_CC2NP TIM_CCER_CC2NP_Msk

Capture/Compare 2 Complementary output Polarity

◆ TIM_CCER_CC2NP_Msk

#define TIM_CCER_CC2NP_Msk (0x1UL << TIM_CCER_CC2NP_Pos)

0x00000080

◆ TIM_CCER_CC2NP_Pos

#define TIM_CCER_CC2NP_Pos (7U)

◆ TIM_CCER_CC2P

#define TIM_CCER_CC2P TIM_CCER_CC2P_Msk

Capture/Compare 2 output Polarity

◆ TIM_CCER_CC2P_Msk

#define TIM_CCER_CC2P_Msk (0x1UL << TIM_CCER_CC2P_Pos)

0x00000020

◆ TIM_CCER_CC2P_Pos

#define TIM_CCER_CC2P_Pos (5U)

◆ TIM_CCER_CC3E

#define TIM_CCER_CC3E TIM_CCER_CC3E_Msk

Capture/Compare 3 output enable

◆ TIM_CCER_CC3E_Msk

#define TIM_CCER_CC3E_Msk (0x1UL << TIM_CCER_CC3E_Pos)

0x00000100

◆ TIM_CCER_CC3E_Pos

#define TIM_CCER_CC3E_Pos (8U)

◆ TIM_CCER_CC3NE

#define TIM_CCER_CC3NE TIM_CCER_CC3NE_Msk

Capture/Compare 3 Complementary output enable

◆ TIM_CCER_CC3NE_Msk

#define TIM_CCER_CC3NE_Msk (0x1UL << TIM_CCER_CC3NE_Pos)

0x00000400

◆ TIM_CCER_CC3NE_Pos

#define TIM_CCER_CC3NE_Pos (10U)

◆ TIM_CCER_CC3NP

#define TIM_CCER_CC3NP TIM_CCER_CC3NP_Msk

Capture/Compare 3 Complementary output Polarity

◆ TIM_CCER_CC3NP_Msk

#define TIM_CCER_CC3NP_Msk (0x1UL << TIM_CCER_CC3NP_Pos)

0x00000800

◆ TIM_CCER_CC3NP_Pos

#define TIM_CCER_CC3NP_Pos (11U)

◆ TIM_CCER_CC3P

#define TIM_CCER_CC3P TIM_CCER_CC3P_Msk

Capture/Compare 3 output Polarity

◆ TIM_CCER_CC3P_Msk

#define TIM_CCER_CC3P_Msk (0x1UL << TIM_CCER_CC3P_Pos)

0x00000200

◆ TIM_CCER_CC3P_Pos

#define TIM_CCER_CC3P_Pos (9U)

◆ TIM_CCER_CC4E

#define TIM_CCER_CC4E TIM_CCER_CC4E_Msk

Capture/Compare 4 output enable

◆ TIM_CCER_CC4E_Msk

#define TIM_CCER_CC4E_Msk (0x1UL << TIM_CCER_CC4E_Pos)

0x00001000

◆ TIM_CCER_CC4E_Pos

#define TIM_CCER_CC4E_Pos (12U)

◆ TIM_CCER_CC4NP

#define TIM_CCER_CC4NP TIM_CCER_CC4NP_Msk

Capture/Compare 4 Complementary output Polarity

◆ TIM_CCER_CC4NP_Msk

#define TIM_CCER_CC4NP_Msk (0x1UL << TIM_CCER_CC4NP_Pos)

0x00008000

◆ TIM_CCER_CC4NP_Pos

#define TIM_CCER_CC4NP_Pos (15U)

◆ TIM_CCER_CC4P

#define TIM_CCER_CC4P TIM_CCER_CC4P_Msk

Capture/Compare 4 output Polarity

◆ TIM_CCER_CC4P_Msk

#define TIM_CCER_CC4P_Msk (0x1UL << TIM_CCER_CC4P_Pos)

0x00002000

◆ TIM_CCER_CC4P_Pos

#define TIM_CCER_CC4P_Pos (13U)

◆ TIM_CCER_CC5E

#define TIM_CCER_CC5E TIM_CCER_CC5E_Msk

Capture/Compare 5 output enable

◆ TIM_CCER_CC5E_Msk

#define TIM_CCER_CC5E_Msk (0x1UL << TIM_CCER_CC5E_Pos)

0x00010000

◆ TIM_CCER_CC5E_Pos

#define TIM_CCER_CC5E_Pos (16U)

◆ TIM_CCER_CC5P

#define TIM_CCER_CC5P TIM_CCER_CC5P_Msk

Capture/Compare 5 output Polarity

◆ TIM_CCER_CC5P_Msk

#define TIM_CCER_CC5P_Msk (0x1UL << TIM_CCER_CC5P_Pos)

0x00020000

◆ TIM_CCER_CC5P_Pos

#define TIM_CCER_CC5P_Pos (17U)

◆ TIM_CCER_CC6E

#define TIM_CCER_CC6E TIM_CCER_CC6E_Msk

Capture/Compare 6 output enable

◆ TIM_CCER_CC6E_Msk

#define TIM_CCER_CC6E_Msk (0x1UL << TIM_CCER_CC6E_Pos)

0x00100000

◆ TIM_CCER_CC6E_Pos

#define TIM_CCER_CC6E_Pos (20U)

◆ TIM_CCER_CC6P

#define TIM_CCER_CC6P TIM_CCER_CC6P_Msk

Capture/Compare 6 output Polarity

◆ TIM_CCER_CC6P_Msk

#define TIM_CCER_CC6P_Msk (0x1UL << TIM_CCER_CC6P_Pos)

0x00200000

◆ TIM_CCER_CC6P_Pos

#define TIM_CCER_CC6P_Pos (21U)

◆ TIM_CCMR1_CC1S

#define TIM_CCMR1_CC1S TIM_CCMR1_CC1S_Msk

CC1S[1:0] bits (Capture/Compare 1 Selection)

◆ TIM_CCMR1_CC1S_0

#define TIM_CCMR1_CC1S_0 (0x1UL << TIM_CCMR1_CC1S_Pos)

0x00000001

◆ TIM_CCMR1_CC1S_1

#define TIM_CCMR1_CC1S_1 (0x2UL << TIM_CCMR1_CC1S_Pos)

0x00000002

◆ TIM_CCMR1_CC1S_Msk

#define TIM_CCMR1_CC1S_Msk (0x3UL << TIM_CCMR1_CC1S_Pos)

0x00000003

◆ TIM_CCMR1_CC1S_Pos

#define TIM_CCMR1_CC1S_Pos (0U)

◆ TIM_CCMR1_CC2S

#define TIM_CCMR1_CC2S TIM_CCMR1_CC2S_Msk

CC2S[1:0] bits (Capture/Compare 2 Selection)

◆ TIM_CCMR1_CC2S_0

#define TIM_CCMR1_CC2S_0 (0x1UL << TIM_CCMR1_CC2S_Pos)

0x00000100

◆ TIM_CCMR1_CC2S_1

#define TIM_CCMR1_CC2S_1 (0x2UL << TIM_CCMR1_CC2S_Pos)

0x00000200

◆ TIM_CCMR1_CC2S_Msk

#define TIM_CCMR1_CC2S_Msk (0x3UL << TIM_CCMR1_CC2S_Pos)

0x00000300

◆ TIM_CCMR1_CC2S_Pos

#define TIM_CCMR1_CC2S_Pos (8U)

◆ TIM_CCMR1_IC1F

#define TIM_CCMR1_IC1F TIM_CCMR1_IC1F_Msk

IC1F[3:0] bits (Input Capture 1 Filter)

◆ TIM_CCMR1_IC1F_0

#define TIM_CCMR1_IC1F_0 (0x1UL << TIM_CCMR1_IC1F_Pos)

0x00000010

◆ TIM_CCMR1_IC1F_1

#define TIM_CCMR1_IC1F_1 (0x2UL << TIM_CCMR1_IC1F_Pos)

0x00000020

◆ TIM_CCMR1_IC1F_2

#define TIM_CCMR1_IC1F_2 (0x4UL << TIM_CCMR1_IC1F_Pos)

0x00000040

◆ TIM_CCMR1_IC1F_3

#define TIM_CCMR1_IC1F_3 (0x8UL << TIM_CCMR1_IC1F_Pos)

0x00000080

◆ TIM_CCMR1_IC1F_Msk

#define TIM_CCMR1_IC1F_Msk (0xFUL << TIM_CCMR1_IC1F_Pos)

0x000000F0

◆ TIM_CCMR1_IC1F_Pos

#define TIM_CCMR1_IC1F_Pos (4U)

◆ TIM_CCMR1_IC1PSC

#define TIM_CCMR1_IC1PSC TIM_CCMR1_IC1PSC_Msk

IC1PSC[1:0] bits (Input Capture 1 Prescaler)

◆ TIM_CCMR1_IC1PSC_0

#define TIM_CCMR1_IC1PSC_0 (0x1UL << TIM_CCMR1_IC1PSC_Pos)

0x00000004

◆ TIM_CCMR1_IC1PSC_1

#define TIM_CCMR1_IC1PSC_1 (0x2UL << TIM_CCMR1_IC1PSC_Pos)

0x00000008

◆ TIM_CCMR1_IC1PSC_Msk

#define TIM_CCMR1_IC1PSC_Msk (0x3UL << TIM_CCMR1_IC1PSC_Pos)

0x0000000C

◆ TIM_CCMR1_IC1PSC_Pos

#define TIM_CCMR1_IC1PSC_Pos (2U)

◆ TIM_CCMR1_IC2F

#define TIM_CCMR1_IC2F TIM_CCMR1_IC2F_Msk

IC2F[3:0] bits (Input Capture 2 Filter)

◆ TIM_CCMR1_IC2F_0

#define TIM_CCMR1_IC2F_0 (0x1UL << TIM_CCMR1_IC2F_Pos)

0x00001000

◆ TIM_CCMR1_IC2F_1

#define TIM_CCMR1_IC2F_1 (0x2UL << TIM_CCMR1_IC2F_Pos)

0x00002000

◆ TIM_CCMR1_IC2F_2

#define TIM_CCMR1_IC2F_2 (0x4UL << TIM_CCMR1_IC2F_Pos)

0x00004000

◆ TIM_CCMR1_IC2F_3

#define TIM_CCMR1_IC2F_3 (0x8UL << TIM_CCMR1_IC2F_Pos)

0x00008000

◆ TIM_CCMR1_IC2F_Msk

#define TIM_CCMR1_IC2F_Msk (0xFUL << TIM_CCMR1_IC2F_Pos)

0x0000F000

◆ TIM_CCMR1_IC2F_Pos

#define TIM_CCMR1_IC2F_Pos (12U)

◆ TIM_CCMR1_IC2PSC

#define TIM_CCMR1_IC2PSC TIM_CCMR1_IC2PSC_Msk

IC2PSC[1:0] bits (Input Capture 2 Prescaler)

◆ TIM_CCMR1_IC2PSC_0

#define TIM_CCMR1_IC2PSC_0 (0x1UL << TIM_CCMR1_IC2PSC_Pos)

0x00000400

◆ TIM_CCMR1_IC2PSC_1

#define TIM_CCMR1_IC2PSC_1 (0x2UL << TIM_CCMR1_IC2PSC_Pos)

0x00000800

◆ TIM_CCMR1_IC2PSC_Msk

#define TIM_CCMR1_IC2PSC_Msk (0x3UL << TIM_CCMR1_IC2PSC_Pos)

0x00000C00

◆ TIM_CCMR1_IC2PSC_Pos

#define TIM_CCMR1_IC2PSC_Pos (10U)

◆ TIM_CCMR1_OC1CE

#define TIM_CCMR1_OC1CE TIM_CCMR1_OC1CE_Msk

Output Compare 1Clear Enable

◆ TIM_CCMR1_OC1CE_Msk

#define TIM_CCMR1_OC1CE_Msk (0x1UL << TIM_CCMR1_OC1CE_Pos)

0x00000080

◆ TIM_CCMR1_OC1CE_Pos

#define TIM_CCMR1_OC1CE_Pos (7U)

◆ TIM_CCMR1_OC1FE

#define TIM_CCMR1_OC1FE TIM_CCMR1_OC1FE_Msk

Output Compare 1 Fast enable

◆ TIM_CCMR1_OC1FE_Msk

#define TIM_CCMR1_OC1FE_Msk (0x1UL << TIM_CCMR1_OC1FE_Pos)

0x00000004

◆ TIM_CCMR1_OC1FE_Pos

#define TIM_CCMR1_OC1FE_Pos (2U)

◆ TIM_CCMR1_OC1M

#define TIM_CCMR1_OC1M TIM_CCMR1_OC1M_Msk

OC1M[2:0] bits (Output Compare 1 Mode)

◆ TIM_CCMR1_OC1M_0

#define TIM_CCMR1_OC1M_0 (0x00000010U)

Bit 0

◆ TIM_CCMR1_OC1M_1

#define TIM_CCMR1_OC1M_1 (0x00000020U)

Bit 1

◆ TIM_CCMR1_OC1M_2

#define TIM_CCMR1_OC1M_2 (0x00000040U)

Bit 2

◆ TIM_CCMR1_OC1M_3

#define TIM_CCMR1_OC1M_3 (0x00010000U)

Bit 3

◆ TIM_CCMR1_OC1M_Msk

#define TIM_CCMR1_OC1M_Msk (0x1007UL << TIM_CCMR1_OC1M_Pos)

0x00010070

◆ TIM_CCMR1_OC1M_Pos

#define TIM_CCMR1_OC1M_Pos (4U)

◆ TIM_CCMR1_OC1PE

#define TIM_CCMR1_OC1PE TIM_CCMR1_OC1PE_Msk

Output Compare 1 Preload enable

◆ TIM_CCMR1_OC1PE_Msk

#define TIM_CCMR1_OC1PE_Msk (0x1UL << TIM_CCMR1_OC1PE_Pos)

0x00000008

◆ TIM_CCMR1_OC1PE_Pos

#define TIM_CCMR1_OC1PE_Pos (3U)

◆ TIM_CCMR1_OC2CE

#define TIM_CCMR1_OC2CE TIM_CCMR1_OC2CE_Msk

Output Compare 2 Clear Enable

◆ TIM_CCMR1_OC2CE_Msk

#define TIM_CCMR1_OC2CE_Msk (0x1UL << TIM_CCMR1_OC2CE_Pos)

0x00008000

◆ TIM_CCMR1_OC2CE_Pos

#define TIM_CCMR1_OC2CE_Pos (15U)

◆ TIM_CCMR1_OC2FE

#define TIM_CCMR1_OC2FE TIM_CCMR1_OC2FE_Msk

Output Compare 2 Fast enable

◆ TIM_CCMR1_OC2FE_Msk

#define TIM_CCMR1_OC2FE_Msk (0x1UL << TIM_CCMR1_OC2FE_Pos)

0x00000400

◆ TIM_CCMR1_OC2FE_Pos

#define TIM_CCMR1_OC2FE_Pos (10U)

◆ TIM_CCMR1_OC2M

#define TIM_CCMR1_OC2M TIM_CCMR1_OC2M_Msk

OC2M[2:0] bits (Output Compare 2 Mode)

◆ TIM_CCMR1_OC2M_0

#define TIM_CCMR1_OC2M_0 (0x00001000U)

Bit 0

◆ TIM_CCMR1_OC2M_1

#define TIM_CCMR1_OC2M_1 (0x00002000U)

Bit 1

◆ TIM_CCMR1_OC2M_2

#define TIM_CCMR1_OC2M_2 (0x00004000U)

Bit 2

◆ TIM_CCMR1_OC2M_3

#define TIM_CCMR1_OC2M_3 (0x01000000U)

Bit 3

◆ TIM_CCMR1_OC2M_Msk

#define TIM_CCMR1_OC2M_Msk (0x1007UL << TIM_CCMR1_OC2M_Pos)

0x01007000

◆ TIM_CCMR1_OC2M_Pos

#define TIM_CCMR1_OC2M_Pos (12U)

◆ TIM_CCMR1_OC2PE

#define TIM_CCMR1_OC2PE TIM_CCMR1_OC2PE_Msk

Output Compare 2 Preload enable

◆ TIM_CCMR1_OC2PE_Msk

#define TIM_CCMR1_OC2PE_Msk (0x1UL << TIM_CCMR1_OC2PE_Pos)

0x00000800

◆ TIM_CCMR1_OC2PE_Pos

#define TIM_CCMR1_OC2PE_Pos (11U)

◆ TIM_CCMR2_CC3S

#define TIM_CCMR2_CC3S TIM_CCMR2_CC3S_Msk

CC3S[1:0] bits (Capture/Compare 3 Selection)

◆ TIM_CCMR2_CC3S_0

#define TIM_CCMR2_CC3S_0 (0x1UL << TIM_CCMR2_CC3S_Pos)

0x00000001

◆ TIM_CCMR2_CC3S_1

#define TIM_CCMR2_CC3S_1 (0x2UL << TIM_CCMR2_CC3S_Pos)

0x00000002

◆ TIM_CCMR2_CC3S_Msk

#define TIM_CCMR2_CC3S_Msk (0x3UL << TIM_CCMR2_CC3S_Pos)

0x00000003

◆ TIM_CCMR2_CC3S_Pos

#define TIM_CCMR2_CC3S_Pos (0U)

◆ TIM_CCMR2_CC4S

#define TIM_CCMR2_CC4S TIM_CCMR2_CC4S_Msk

CC4S[1:0] bits (Capture/Compare 4 Selection)

◆ TIM_CCMR2_CC4S_0

#define TIM_CCMR2_CC4S_0 (0x1UL << TIM_CCMR2_CC4S_Pos)

0x00000100

◆ TIM_CCMR2_CC4S_1

#define TIM_CCMR2_CC4S_1 (0x2UL << TIM_CCMR2_CC4S_Pos)

0x00000200

◆ TIM_CCMR2_CC4S_Msk

#define TIM_CCMR2_CC4S_Msk (0x3UL << TIM_CCMR2_CC4S_Pos)

0x00000300

◆ TIM_CCMR2_CC4S_Pos

#define TIM_CCMR2_CC4S_Pos (8U)

◆ TIM_CCMR2_IC3F

#define TIM_CCMR2_IC3F TIM_CCMR2_IC3F_Msk

IC3F[3:0] bits (Input Capture 3 Filter)

◆ TIM_CCMR2_IC3F_0

#define TIM_CCMR2_IC3F_0 (0x1UL << TIM_CCMR2_IC3F_Pos)

0x00000010

◆ TIM_CCMR2_IC3F_1

#define TIM_CCMR2_IC3F_1 (0x2UL << TIM_CCMR2_IC3F_Pos)

0x00000020

◆ TIM_CCMR2_IC3F_2

#define TIM_CCMR2_IC3F_2 (0x4UL << TIM_CCMR2_IC3F_Pos)

0x00000040

◆ TIM_CCMR2_IC3F_3

#define TIM_CCMR2_IC3F_3 (0x8UL << TIM_CCMR2_IC3F_Pos)

0x00000080

◆ TIM_CCMR2_IC3F_Msk

#define TIM_CCMR2_IC3F_Msk (0xFUL << TIM_CCMR2_IC3F_Pos)

0x000000F0

◆ TIM_CCMR2_IC3F_Pos

#define TIM_CCMR2_IC3F_Pos (4U)

◆ TIM_CCMR2_IC3PSC

#define TIM_CCMR2_IC3PSC TIM_CCMR2_IC3PSC_Msk

IC3PSC[1:0] bits (Input Capture 3 Prescaler)

◆ TIM_CCMR2_IC3PSC_0

#define TIM_CCMR2_IC3PSC_0 (0x1UL << TIM_CCMR2_IC3PSC_Pos)

0x00000004

◆ TIM_CCMR2_IC3PSC_1

#define TIM_CCMR2_IC3PSC_1 (0x2UL << TIM_CCMR2_IC3PSC_Pos)

0x00000008

◆ TIM_CCMR2_IC3PSC_Msk

#define TIM_CCMR2_IC3PSC_Msk (0x3UL << TIM_CCMR2_IC3PSC_Pos)

0x0000000C

◆ TIM_CCMR2_IC3PSC_Pos

#define TIM_CCMR2_IC3PSC_Pos (2U)

◆ TIM_CCMR2_IC4F

#define TIM_CCMR2_IC4F TIM_CCMR2_IC4F_Msk

IC4F[3:0] bits (Input Capture 4 Filter)

◆ TIM_CCMR2_IC4F_0

#define TIM_CCMR2_IC4F_0 (0x1UL << TIM_CCMR2_IC4F_Pos)

0x00001000

◆ TIM_CCMR2_IC4F_1

#define TIM_CCMR2_IC4F_1 (0x2UL << TIM_CCMR2_IC4F_Pos)

0x00002000

◆ TIM_CCMR2_IC4F_2

#define TIM_CCMR2_IC4F_2 (0x4UL << TIM_CCMR2_IC4F_Pos)

0x00004000

◆ TIM_CCMR2_IC4F_3

#define TIM_CCMR2_IC4F_3 (0x8UL << TIM_CCMR2_IC4F_Pos)

0x00008000

◆ TIM_CCMR2_IC4F_Msk

#define TIM_CCMR2_IC4F_Msk (0xFUL << TIM_CCMR2_IC4F_Pos)

0x0000F000

◆ TIM_CCMR2_IC4F_Pos

#define TIM_CCMR2_IC4F_Pos (12U)

◆ TIM_CCMR2_IC4PSC

#define TIM_CCMR2_IC4PSC TIM_CCMR2_IC4PSC_Msk

IC4PSC[1:0] bits (Input Capture 4 Prescaler)

◆ TIM_CCMR2_IC4PSC_0

#define TIM_CCMR2_IC4PSC_0 (0x1UL << TIM_CCMR2_IC4PSC_Pos)

0x00000400

◆ TIM_CCMR2_IC4PSC_1

#define TIM_CCMR2_IC4PSC_1 (0x2UL << TIM_CCMR2_IC4PSC_Pos)

0x00000800

◆ TIM_CCMR2_IC4PSC_Msk

#define TIM_CCMR2_IC4PSC_Msk (0x3UL << TIM_CCMR2_IC4PSC_Pos)

0x00000C00

◆ TIM_CCMR2_IC4PSC_Pos

#define TIM_CCMR2_IC4PSC_Pos (10U)

◆ TIM_CCMR2_OC3CE

#define TIM_CCMR2_OC3CE TIM_CCMR2_OC3CE_Msk

Output Compare 3 Clear Enable

◆ TIM_CCMR2_OC3CE_Msk

#define TIM_CCMR2_OC3CE_Msk (0x1UL << TIM_CCMR2_OC3CE_Pos)

0x00000080

◆ TIM_CCMR2_OC3CE_Pos

#define TIM_CCMR2_OC3CE_Pos (7U)

◆ TIM_CCMR2_OC3FE

#define TIM_CCMR2_OC3FE TIM_CCMR2_OC3FE_Msk

Output Compare 3 Fast enable

◆ TIM_CCMR2_OC3FE_Msk

#define TIM_CCMR2_OC3FE_Msk (0x1UL << TIM_CCMR2_OC3FE_Pos)

0x00000004

◆ TIM_CCMR2_OC3FE_Pos

#define TIM_CCMR2_OC3FE_Pos (2U)

◆ TIM_CCMR2_OC3M

#define TIM_CCMR2_OC3M TIM_CCMR2_OC3M_Msk

OC3M[2:0] bits (Output Compare 3 Mode)

◆ TIM_CCMR2_OC3M_0

#define TIM_CCMR2_OC3M_0 (0x00000010U)

Bit 0

◆ TIM_CCMR2_OC3M_1

#define TIM_CCMR2_OC3M_1 (0x00000020U)

Bit 1

◆ TIM_CCMR2_OC3M_2

#define TIM_CCMR2_OC3M_2 (0x00000040U)

Bit 2

◆ TIM_CCMR2_OC3M_3

#define TIM_CCMR2_OC3M_3 (0x00010000U)

Bit 3

◆ TIM_CCMR2_OC3M_Msk

#define TIM_CCMR2_OC3M_Msk (0x1007UL << TIM_CCMR2_OC3M_Pos)

0x00010070

◆ TIM_CCMR2_OC3M_Pos

#define TIM_CCMR2_OC3M_Pos (4U)

◆ TIM_CCMR2_OC3PE

#define TIM_CCMR2_OC3PE TIM_CCMR2_OC3PE_Msk

Output Compare 3 Preload enable

◆ TIM_CCMR2_OC3PE_Msk

#define TIM_CCMR2_OC3PE_Msk (0x1UL << TIM_CCMR2_OC3PE_Pos)

0x00000008

◆ TIM_CCMR2_OC3PE_Pos

#define TIM_CCMR2_OC3PE_Pos (3U)

◆ TIM_CCMR2_OC4CE

#define TIM_CCMR2_OC4CE TIM_CCMR2_OC4CE_Msk

Output Compare 4 Clear Enable

◆ TIM_CCMR2_OC4CE_Msk

#define TIM_CCMR2_OC4CE_Msk (0x1UL << TIM_CCMR2_OC4CE_Pos)

0x00008000

◆ TIM_CCMR2_OC4CE_Pos

#define TIM_CCMR2_OC4CE_Pos (15U)

◆ TIM_CCMR2_OC4FE

#define TIM_CCMR2_OC4FE TIM_CCMR2_OC4FE_Msk

Output Compare 4 Fast enable

◆ TIM_CCMR2_OC4FE_Msk

#define TIM_CCMR2_OC4FE_Msk (0x1UL << TIM_CCMR2_OC4FE_Pos)

0x00000400

◆ TIM_CCMR2_OC4FE_Pos

#define TIM_CCMR2_OC4FE_Pos (10U)

◆ TIM_CCMR2_OC4M

#define TIM_CCMR2_OC4M TIM_CCMR2_OC4M_Msk

OC4M[2:0] bits (Output Compare 4 Mode)

◆ TIM_CCMR2_OC4M_0

#define TIM_CCMR2_OC4M_0 (0x00001000U)

Bit 0

◆ TIM_CCMR2_OC4M_1

#define TIM_CCMR2_OC4M_1 (0x00002000U)

Bit 1

◆ TIM_CCMR2_OC4M_2

#define TIM_CCMR2_OC4M_2 (0x00004000U)

Bit 2

◆ TIM_CCMR2_OC4M_3

#define TIM_CCMR2_OC4M_3 (0x01000000U)

Bit 3

◆ TIM_CCMR2_OC4M_Msk

#define TIM_CCMR2_OC4M_Msk (0x1007UL << TIM_CCMR2_OC4M_Pos)

0x01007000

◆ TIM_CCMR2_OC4M_Pos

#define TIM_CCMR2_OC4M_Pos (12U)

◆ TIM_CCMR2_OC4PE

#define TIM_CCMR2_OC4PE TIM_CCMR2_OC4PE_Msk

Output Compare 4 Preload enable

◆ TIM_CCMR2_OC4PE_Msk

#define TIM_CCMR2_OC4PE_Msk (0x1UL << TIM_CCMR2_OC4PE_Pos)

0x00000800

◆ TIM_CCMR2_OC4PE_Pos

#define TIM_CCMR2_OC4PE_Pos (11U)

◆ TIM_CCMR3_OC5CE

#define TIM_CCMR3_OC5CE TIM_CCMR3_OC5CE_Msk

Output Compare 5 Clear Enable

◆ TIM_CCMR3_OC5CE_Msk

#define TIM_CCMR3_OC5CE_Msk (0x1UL << TIM_CCMR3_OC5CE_Pos)

0x00000080

◆ TIM_CCMR3_OC5CE_Pos

#define TIM_CCMR3_OC5CE_Pos (7U)

◆ TIM_CCMR3_OC5FE

#define TIM_CCMR3_OC5FE TIM_CCMR3_OC5FE_Msk

Output Compare 5 Fast enable

◆ TIM_CCMR3_OC5FE_Msk

#define TIM_CCMR3_OC5FE_Msk (0x1UL << TIM_CCMR3_OC5FE_Pos)

0x00000004

◆ TIM_CCMR3_OC5FE_Pos

#define TIM_CCMR3_OC5FE_Pos (2U)

◆ TIM_CCMR3_OC5M

#define TIM_CCMR3_OC5M TIM_CCMR3_OC5M_Msk

OC5M[2:0] bits (Output Compare 5 Mode)

◆ TIM_CCMR3_OC5M_0

#define TIM_CCMR3_OC5M_0 (0x0001UL << TIM_CCMR3_OC5M_Pos)

0x00000010

◆ TIM_CCMR3_OC5M_1

#define TIM_CCMR3_OC5M_1 (0x0002UL << TIM_CCMR3_OC5M_Pos)

0x00000020

◆ TIM_CCMR3_OC5M_2

#define TIM_CCMR3_OC5M_2 (0x0004UL << TIM_CCMR3_OC5M_Pos)

0x00000040

◆ TIM_CCMR3_OC5M_3

#define TIM_CCMR3_OC5M_3 (0x1000UL << TIM_CCMR3_OC5M_Pos)

0x00010000

◆ TIM_CCMR3_OC5M_Msk

#define TIM_CCMR3_OC5M_Msk (0x1007UL << TIM_CCMR3_OC5M_Pos)

0x00010070

◆ TIM_CCMR3_OC5M_Pos

#define TIM_CCMR3_OC5M_Pos (4U)

◆ TIM_CCMR3_OC5PE

#define TIM_CCMR3_OC5PE TIM_CCMR3_OC5PE_Msk

Output Compare 5 Preload enable

◆ TIM_CCMR3_OC5PE_Msk

#define TIM_CCMR3_OC5PE_Msk (0x1UL << TIM_CCMR3_OC5PE_Pos)

0x00000008

◆ TIM_CCMR3_OC5PE_Pos

#define TIM_CCMR3_OC5PE_Pos (3U)

◆ TIM_CCMR3_OC6CE

#define TIM_CCMR3_OC6CE TIM_CCMR3_OC6CE_Msk

Output Compare 6 Clear Enable

◆ TIM_CCMR3_OC6CE_Msk

#define TIM_CCMR3_OC6CE_Msk (0x1UL << TIM_CCMR3_OC6CE_Pos)

0x00008000

◆ TIM_CCMR3_OC6CE_Pos

#define TIM_CCMR3_OC6CE_Pos (15U)

◆ TIM_CCMR3_OC6FE

#define TIM_CCMR3_OC6FE TIM_CCMR3_OC6FE_Msk

Output Compare 6 Fast enable

◆ TIM_CCMR3_OC6FE_Msk

#define TIM_CCMR3_OC6FE_Msk (0x1UL << TIM_CCMR3_OC6FE_Pos)

0x00000400

◆ TIM_CCMR3_OC6FE_Pos

#define TIM_CCMR3_OC6FE_Pos (10U)

◆ TIM_CCMR3_OC6M

#define TIM_CCMR3_OC6M TIM_CCMR3_OC6M_Msk

OC6M[2:0] bits (Output Compare 6 Mode)

◆ TIM_CCMR3_OC6M_0

#define TIM_CCMR3_OC6M_0 (0x0001UL << TIM_CCMR3_OC6M_Pos)

0x00001000

◆ TIM_CCMR3_OC6M_1

#define TIM_CCMR3_OC6M_1 (0x0002UL << TIM_CCMR3_OC6M_Pos)

0x00002000

◆ TIM_CCMR3_OC6M_2

#define TIM_CCMR3_OC6M_2 (0x0004UL << TIM_CCMR3_OC6M_Pos)

0x00004000

◆ TIM_CCMR3_OC6M_3

#define TIM_CCMR3_OC6M_3 (0x1000UL << TIM_CCMR3_OC6M_Pos)

0x01000000

◆ TIM_CCMR3_OC6M_Msk

#define TIM_CCMR3_OC6M_Msk (0x1007UL << TIM_CCMR3_OC6M_Pos)

0x01007000

◆ TIM_CCMR3_OC6M_Pos

#define TIM_CCMR3_OC6M_Pos (12U)

◆ TIM_CCMR3_OC6PE

#define TIM_CCMR3_OC6PE TIM_CCMR3_OC6PE_Msk

Output Compare 6 Preload enable

◆ TIM_CCMR3_OC6PE_Msk

#define TIM_CCMR3_OC6PE_Msk (0x1UL << TIM_CCMR3_OC6PE_Pos)

0x00000800

◆ TIM_CCMR3_OC6PE_Pos

#define TIM_CCMR3_OC6PE_Pos (11U)

◆ TIM_CCR1_CCR1

#define TIM_CCR1_CCR1 TIM_CCR1_CCR1_Msk

Capture/Compare 1 Value

◆ TIM_CCR1_CCR1_Msk

#define TIM_CCR1_CCR1_Msk (0xFFFFUL << TIM_CCR1_CCR1_Pos)

0x0000FFFF

◆ TIM_CCR1_CCR1_Pos

#define TIM_CCR1_CCR1_Pos (0U)

◆ TIM_CCR2_CCR2

#define TIM_CCR2_CCR2 TIM_CCR2_CCR2_Msk

Capture/Compare 2 Value

◆ TIM_CCR2_CCR2_Msk

#define TIM_CCR2_CCR2_Msk (0xFFFFUL << TIM_CCR2_CCR2_Pos)

0x0000FFFF

◆ TIM_CCR2_CCR2_Pos

#define TIM_CCR2_CCR2_Pos (0U)

◆ TIM_CCR3_CCR3

#define TIM_CCR3_CCR3 TIM_CCR3_CCR3_Msk

Capture/Compare 3 Value

◆ TIM_CCR3_CCR3_Msk

#define TIM_CCR3_CCR3_Msk (0xFFFFUL << TIM_CCR3_CCR3_Pos)

0x0000FFFF

◆ TIM_CCR3_CCR3_Pos

#define TIM_CCR3_CCR3_Pos (0U)

◆ TIM_CCR4_CCR4

#define TIM_CCR4_CCR4 TIM_CCR4_CCR4_Msk

Capture/Compare 4 Value

◆ TIM_CCR4_CCR4_Msk

#define TIM_CCR4_CCR4_Msk (0xFFFFUL << TIM_CCR4_CCR4_Pos)

0x0000FFFF

◆ TIM_CCR4_CCR4_Pos

#define TIM_CCR4_CCR4_Pos (0U)

◆ TIM_CCR5_CCR5

#define TIM_CCR5_CCR5 TIM_CCR5_CCR5_Msk

Capture/Compare 5 Value

◆ TIM_CCR5_CCR5_Msk

#define TIM_CCR5_CCR5_Msk (0xFFFFFFFFUL << TIM_CCR5_CCR5_Pos)

0xFFFFFFFF

◆ TIM_CCR5_CCR5_Pos

#define TIM_CCR5_CCR5_Pos (0U)

◆ TIM_CCR5_GC5C1

#define TIM_CCR5_GC5C1 TIM_CCR5_GC5C1_Msk

Group Channel 5 and Channel 1

◆ TIM_CCR5_GC5C1_Msk

#define TIM_CCR5_GC5C1_Msk (0x1UL << TIM_CCR5_GC5C1_Pos)

0x20000000

◆ TIM_CCR5_GC5C1_Pos

#define TIM_CCR5_GC5C1_Pos (29U)

◆ TIM_CCR5_GC5C2

#define TIM_CCR5_GC5C2 TIM_CCR5_GC5C2_Msk

Group Channel 5 and Channel 2

◆ TIM_CCR5_GC5C2_Msk

#define TIM_CCR5_GC5C2_Msk (0x1UL << TIM_CCR5_GC5C2_Pos)

0x40000000

◆ TIM_CCR5_GC5C2_Pos

#define TIM_CCR5_GC5C2_Pos (30U)

◆ TIM_CCR5_GC5C3

#define TIM_CCR5_GC5C3 TIM_CCR5_GC5C3_Msk

Group Channel 5 and Channel 3

◆ TIM_CCR5_GC5C3_Msk

#define TIM_CCR5_GC5C3_Msk (0x1UL << TIM_CCR5_GC5C3_Pos)

0x80000000

◆ TIM_CCR5_GC5C3_Pos

#define TIM_CCR5_GC5C3_Pos (31U)

◆ TIM_CCR6_CCR6

#define TIM_CCR6_CCR6 TIM_CCR6_CCR6_Msk

Capture/Compare 6 Value

◆ TIM_CCR6_CCR6_Msk

#define TIM_CCR6_CCR6_Msk (0xFFFFUL << TIM_CCR6_CCR6_Pos)

0x0000FFFF

◆ TIM_CCR6_CCR6_Pos

#define TIM_CCR6_CCR6_Pos (0U)

◆ TIM_CNT_CNT

#define TIM_CNT_CNT TIM_CNT_CNT_Msk

Counter Value

◆ TIM_CNT_CNT_Msk

#define TIM_CNT_CNT_Msk (0xFFFFFFFFUL << TIM_CNT_CNT_Pos)

0xFFFFFFFF

◆ TIM_CNT_CNT_Pos

#define TIM_CNT_CNT_Pos (0U)

◆ TIM_CNT_UIFCPY

#define TIM_CNT_UIFCPY TIM_CNT_UIFCPY_Msk

Update interrupt flag copy

◆ TIM_CNT_UIFCPY_Msk

#define TIM_CNT_UIFCPY_Msk (0x1UL << TIM_CNT_UIFCPY_Pos)

0x80000000

◆ TIM_CNT_UIFCPY_Pos

#define TIM_CNT_UIFCPY_Pos (31U)

◆ TIM_CR1_ARPE

#define TIM_CR1_ARPE TIM_CR1_ARPE_Msk

Auto-reload preload enable

◆ TIM_CR1_ARPE_Msk

#define TIM_CR1_ARPE_Msk (0x1UL << TIM_CR1_ARPE_Pos)

0x00000080

◆ TIM_CR1_ARPE_Pos

#define TIM_CR1_ARPE_Pos (7U)

◆ TIM_CR1_CEN

#define TIM_CR1_CEN TIM_CR1_CEN_Msk

Counter enable

◆ TIM_CR1_CEN_Msk

#define TIM_CR1_CEN_Msk (0x1UL << TIM_CR1_CEN_Pos)

0x00000001

◆ TIM_CR1_CEN_Pos

#define TIM_CR1_CEN_Pos (0U)

◆ TIM_CR1_CKD

#define TIM_CR1_CKD TIM_CR1_CKD_Msk

CKD[1:0] bits (clock division)

◆ TIM_CR1_CKD_0

#define TIM_CR1_CKD_0 (0x1UL << TIM_CR1_CKD_Pos)

0x00000100

◆ TIM_CR1_CKD_1

#define TIM_CR1_CKD_1 (0x2UL << TIM_CR1_CKD_Pos)

0x00000200

◆ TIM_CR1_CKD_Msk

#define TIM_CR1_CKD_Msk (0x3UL << TIM_CR1_CKD_Pos)

0x00000300

◆ TIM_CR1_CKD_Pos

#define TIM_CR1_CKD_Pos (8U)

◆ TIM_CR1_CMS

#define TIM_CR1_CMS TIM_CR1_CMS_Msk

CMS[1:0] bits (Center-aligned mode selection)

◆ TIM_CR1_CMS_0

#define TIM_CR1_CMS_0 (0x1UL << TIM_CR1_CMS_Pos)

0x00000020

◆ TIM_CR1_CMS_1

#define TIM_CR1_CMS_1 (0x2UL << TIM_CR1_CMS_Pos)

0x00000040

◆ TIM_CR1_CMS_Msk

#define TIM_CR1_CMS_Msk (0x3UL << TIM_CR1_CMS_Pos)

0x00000060

◆ TIM_CR1_CMS_Pos

#define TIM_CR1_CMS_Pos (5U)

◆ TIM_CR1_DIR

#define TIM_CR1_DIR TIM_CR1_DIR_Msk

Direction

◆ TIM_CR1_DIR_Msk

#define TIM_CR1_DIR_Msk (0x1UL << TIM_CR1_DIR_Pos)

0x00000010

◆ TIM_CR1_DIR_Pos

#define TIM_CR1_DIR_Pos (4U)

◆ TIM_CR1_OPM

#define TIM_CR1_OPM TIM_CR1_OPM_Msk

One pulse mode

◆ TIM_CR1_OPM_Msk

#define TIM_CR1_OPM_Msk (0x1UL << TIM_CR1_OPM_Pos)

0x00000008

◆ TIM_CR1_OPM_Pos

#define TIM_CR1_OPM_Pos (3U)

◆ TIM_CR1_UDIS

#define TIM_CR1_UDIS TIM_CR1_UDIS_Msk

Update disable

◆ TIM_CR1_UDIS_Msk

#define TIM_CR1_UDIS_Msk (0x1UL << TIM_CR1_UDIS_Pos)

0x00000002

◆ TIM_CR1_UDIS_Pos

#define TIM_CR1_UDIS_Pos (1U)

◆ TIM_CR1_UIFREMAP

#define TIM_CR1_UIFREMAP TIM_CR1_UIFREMAP_Msk

Update interrupt flag remap

◆ TIM_CR1_UIFREMAP_Msk

#define TIM_CR1_UIFREMAP_Msk (0x1UL << TIM_CR1_UIFREMAP_Pos)

0x00000800

◆ TIM_CR1_UIFREMAP_Pos

#define TIM_CR1_UIFREMAP_Pos (11U)

◆ TIM_CR1_URS

#define TIM_CR1_URS TIM_CR1_URS_Msk

Update request source

◆ TIM_CR1_URS_Msk

#define TIM_CR1_URS_Msk (0x1UL << TIM_CR1_URS_Pos)

0x00000004

◆ TIM_CR1_URS_Pos

#define TIM_CR1_URS_Pos (2U)

◆ TIM_CR2_CCDS

#define TIM_CR2_CCDS TIM_CR2_CCDS_Msk

Capture/Compare DMA Selection

◆ TIM_CR2_CCDS_Msk

#define TIM_CR2_CCDS_Msk (0x1UL << TIM_CR2_CCDS_Pos)

0x00000008

◆ TIM_CR2_CCDS_Pos

#define TIM_CR2_CCDS_Pos (3U)

◆ TIM_CR2_CCPC

#define TIM_CR2_CCPC TIM_CR2_CCPC_Msk

Capture/Compare Preloaded Control

◆ TIM_CR2_CCPC_Msk

#define TIM_CR2_CCPC_Msk (0x1UL << TIM_CR2_CCPC_Pos)

0x00000001

◆ TIM_CR2_CCPC_Pos

#define TIM_CR2_CCPC_Pos (0U)

◆ TIM_CR2_CCUS

#define TIM_CR2_CCUS TIM_CR2_CCUS_Msk

Capture/Compare Control Update Selection

◆ TIM_CR2_CCUS_Msk

#define TIM_CR2_CCUS_Msk (0x1UL << TIM_CR2_CCUS_Pos)

0x00000004

◆ TIM_CR2_CCUS_Pos

#define TIM_CR2_CCUS_Pos (2U)

◆ TIM_CR2_MMS

#define TIM_CR2_MMS TIM_CR2_MMS_Msk

MMS[2:0] bits (Master Mode Selection)

◆ TIM_CR2_MMS2

#define TIM_CR2_MMS2 TIM_CR2_MMS2_Msk

MMS[2:0] bits (Master Mode Selection)

◆ TIM_CR2_MMS2_0

#define TIM_CR2_MMS2_0 (0x1UL << TIM_CR2_MMS2_Pos)

0x00100000

◆ TIM_CR2_MMS2_1

#define TIM_CR2_MMS2_1 (0x2UL << TIM_CR2_MMS2_Pos)

0x00200000

◆ TIM_CR2_MMS2_2

#define TIM_CR2_MMS2_2 (0x4UL << TIM_CR2_MMS2_Pos)

0x00400000

◆ TIM_CR2_MMS2_3

#define TIM_CR2_MMS2_3 (0x8UL << TIM_CR2_MMS2_Pos)

0x00800000

◆ TIM_CR2_MMS2_Msk

#define TIM_CR2_MMS2_Msk (0xFUL << TIM_CR2_MMS2_Pos)

0x00F00000

◆ TIM_CR2_MMS2_Pos

#define TIM_CR2_MMS2_Pos (20U)

◆ TIM_CR2_MMS_0

#define TIM_CR2_MMS_0 (0x1UL << TIM_CR2_MMS_Pos)

0x00000010

◆ TIM_CR2_MMS_1

#define TIM_CR2_MMS_1 (0x2UL << TIM_CR2_MMS_Pos)

0x00000020

◆ TIM_CR2_MMS_2

#define TIM_CR2_MMS_2 (0x4UL << TIM_CR2_MMS_Pos)

0x00000040

◆ TIM_CR2_MMS_Msk

#define TIM_CR2_MMS_Msk (0x7UL << TIM_CR2_MMS_Pos)

0x00000070

◆ TIM_CR2_MMS_Pos

#define TIM_CR2_MMS_Pos (4U)

◆ TIM_CR2_OIS1

#define TIM_CR2_OIS1 TIM_CR2_OIS1_Msk

Output Idle state 1 (OC1 output)

◆ TIM_CR2_OIS1_Msk

#define TIM_CR2_OIS1_Msk (0x1UL << TIM_CR2_OIS1_Pos)

0x00000100

◆ TIM_CR2_OIS1_Pos

#define TIM_CR2_OIS1_Pos (8U)

◆ TIM_CR2_OIS1N

#define TIM_CR2_OIS1N TIM_CR2_OIS1N_Msk

Output Idle state 1 (OC1N output)

◆ TIM_CR2_OIS1N_Msk

#define TIM_CR2_OIS1N_Msk (0x1UL << TIM_CR2_OIS1N_Pos)

0x00000200

◆ TIM_CR2_OIS1N_Pos

#define TIM_CR2_OIS1N_Pos (9U)

◆ TIM_CR2_OIS2

#define TIM_CR2_OIS2 TIM_CR2_OIS2_Msk

Output Idle state 2 (OC2 output)

◆ TIM_CR2_OIS2_Msk

#define TIM_CR2_OIS2_Msk (0x1UL << TIM_CR2_OIS2_Pos)

0x00000400

◆ TIM_CR2_OIS2_Pos

#define TIM_CR2_OIS2_Pos (10U)

◆ TIM_CR2_OIS2N

#define TIM_CR2_OIS2N TIM_CR2_OIS2N_Msk

Output Idle state 2 (OC2N output)

◆ TIM_CR2_OIS2N_Msk

#define TIM_CR2_OIS2N_Msk (0x1UL << TIM_CR2_OIS2N_Pos)

0x00000800

◆ TIM_CR2_OIS2N_Pos

#define TIM_CR2_OIS2N_Pos (11U)

◆ TIM_CR2_OIS3

#define TIM_CR2_OIS3 TIM_CR2_OIS3_Msk

Output Idle state 3 (OC3 output)

◆ TIM_CR2_OIS3_Msk

#define TIM_CR2_OIS3_Msk (0x1UL << TIM_CR2_OIS3_Pos)

0x00001000

◆ TIM_CR2_OIS3_Pos

#define TIM_CR2_OIS3_Pos (12U)

◆ TIM_CR2_OIS3N

#define TIM_CR2_OIS3N TIM_CR2_OIS3N_Msk

Output Idle state 3 (OC3N output)

◆ TIM_CR2_OIS3N_Msk

#define TIM_CR2_OIS3N_Msk (0x1UL << TIM_CR2_OIS3N_Pos)

0x00002000

◆ TIM_CR2_OIS3N_Pos

#define TIM_CR2_OIS3N_Pos (13U)

◆ TIM_CR2_OIS4

#define TIM_CR2_OIS4 TIM_CR2_OIS4_Msk

Output Idle state 4 (OC4 output)

◆ TIM_CR2_OIS4_Msk

#define TIM_CR2_OIS4_Msk (0x1UL << TIM_CR2_OIS4_Pos)

0x00004000

◆ TIM_CR2_OIS4_Pos

#define TIM_CR2_OIS4_Pos (14U)

◆ TIM_CR2_OIS5

#define TIM_CR2_OIS5 TIM_CR2_OIS5_Msk

Output Idle state 4 (OC4 output)

◆ TIM_CR2_OIS5_Msk

#define TIM_CR2_OIS5_Msk (0x1UL << TIM_CR2_OIS5_Pos)

0x00010000

◆ TIM_CR2_OIS5_Pos

#define TIM_CR2_OIS5_Pos (16U)

◆ TIM_CR2_OIS6

#define TIM_CR2_OIS6 TIM_CR2_OIS6_Msk

Output Idle state 4 (OC4 output)

◆ TIM_CR2_OIS6_Msk

#define TIM_CR2_OIS6_Msk (0x1UL << TIM_CR2_OIS6_Pos)

0x00040000

◆ TIM_CR2_OIS6_Pos

#define TIM_CR2_OIS6_Pos (18U)

◆ TIM_CR2_TI1S

#define TIM_CR2_TI1S TIM_CR2_TI1S_Msk

TI1 Selection

◆ TIM_CR2_TI1S_Msk

#define TIM_CR2_TI1S_Msk (0x1UL << TIM_CR2_TI1S_Pos)

0x00000080

◆ TIM_CR2_TI1S_Pos

#define TIM_CR2_TI1S_Pos (7U)

◆ TIM_DCR_DBA

#define TIM_DCR_DBA TIM_DCR_DBA_Msk

DBA[4:0] bits (DMA Base Address)

◆ TIM_DCR_DBA_0

#define TIM_DCR_DBA_0 (0x01UL << TIM_DCR_DBA_Pos)

0x00000001

◆ TIM_DCR_DBA_1

#define TIM_DCR_DBA_1 (0x02UL << TIM_DCR_DBA_Pos)

0x00000002

◆ TIM_DCR_DBA_2

#define TIM_DCR_DBA_2 (0x04UL << TIM_DCR_DBA_Pos)

0x00000004

◆ TIM_DCR_DBA_3

#define TIM_DCR_DBA_3 (0x08UL << TIM_DCR_DBA_Pos)

0x00000008

◆ TIM_DCR_DBA_4

#define TIM_DCR_DBA_4 (0x10UL << TIM_DCR_DBA_Pos)

0x00000010

◆ TIM_DCR_DBA_Msk

#define TIM_DCR_DBA_Msk (0x1FUL << TIM_DCR_DBA_Pos)

0x0000001F

◆ TIM_DCR_DBA_Pos

#define TIM_DCR_DBA_Pos (0U)

◆ TIM_DCR_DBL

#define TIM_DCR_DBL TIM_DCR_DBL_Msk

DBL[4:0] bits (DMA Burst Length)

◆ TIM_DCR_DBL_0

#define TIM_DCR_DBL_0 (0x01UL << TIM_DCR_DBL_Pos)

0x00000100

◆ TIM_DCR_DBL_1

#define TIM_DCR_DBL_1 (0x02UL << TIM_DCR_DBL_Pos)

0x00000200

◆ TIM_DCR_DBL_2

#define TIM_DCR_DBL_2 (0x04UL << TIM_DCR_DBL_Pos)

0x00000400

◆ TIM_DCR_DBL_3

#define TIM_DCR_DBL_3 (0x08UL << TIM_DCR_DBL_Pos)

0x00000800

◆ TIM_DCR_DBL_4

#define TIM_DCR_DBL_4 (0x10UL << TIM_DCR_DBL_Pos)

0x00001000

◆ TIM_DCR_DBL_Msk

#define TIM_DCR_DBL_Msk (0x1FUL << TIM_DCR_DBL_Pos)

0x00001F00

◆ TIM_DCR_DBL_Pos

#define TIM_DCR_DBL_Pos (8U)

◆ TIM_DIER_BIE

#define TIM_DIER_BIE TIM_DIER_BIE_Msk

Break interrupt enable

◆ TIM_DIER_BIE_Msk

#define TIM_DIER_BIE_Msk (0x1UL << TIM_DIER_BIE_Pos)

0x00000080

◆ TIM_DIER_BIE_Pos

#define TIM_DIER_BIE_Pos (7U)

◆ TIM_DIER_CC1DE

#define TIM_DIER_CC1DE TIM_DIER_CC1DE_Msk

Capture/Compare 1 DMA request enable

◆ TIM_DIER_CC1DE_Msk

#define TIM_DIER_CC1DE_Msk (0x1UL << TIM_DIER_CC1DE_Pos)

0x00000200

◆ TIM_DIER_CC1DE_Pos

#define TIM_DIER_CC1DE_Pos (9U)

◆ TIM_DIER_CC1IE

#define TIM_DIER_CC1IE TIM_DIER_CC1IE_Msk

Capture/Compare 1 interrupt enable

◆ TIM_DIER_CC1IE_Msk

#define TIM_DIER_CC1IE_Msk (0x1UL << TIM_DIER_CC1IE_Pos)

0x00000002

◆ TIM_DIER_CC1IE_Pos

#define TIM_DIER_CC1IE_Pos (1U)

◆ TIM_DIER_CC2DE

#define TIM_DIER_CC2DE TIM_DIER_CC2DE_Msk

Capture/Compare 2 DMA request enable

◆ TIM_DIER_CC2DE_Msk

#define TIM_DIER_CC2DE_Msk (0x1UL << TIM_DIER_CC2DE_Pos)

0x00000400

◆ TIM_DIER_CC2DE_Pos

#define TIM_DIER_CC2DE_Pos (10U)

◆ TIM_DIER_CC2IE

#define TIM_DIER_CC2IE TIM_DIER_CC2IE_Msk

Capture/Compare 2 interrupt enable

◆ TIM_DIER_CC2IE_Msk

#define TIM_DIER_CC2IE_Msk (0x1UL << TIM_DIER_CC2IE_Pos)

0x00000004

◆ TIM_DIER_CC2IE_Pos

#define TIM_DIER_CC2IE_Pos (2U)

◆ TIM_DIER_CC3DE

#define TIM_DIER_CC3DE TIM_DIER_CC3DE_Msk

Capture/Compare 3 DMA request enable

◆ TIM_DIER_CC3DE_Msk

#define TIM_DIER_CC3DE_Msk (0x1UL << TIM_DIER_CC3DE_Pos)

0x00000800

◆ TIM_DIER_CC3DE_Pos

#define TIM_DIER_CC3DE_Pos (11U)

◆ TIM_DIER_CC3IE

#define TIM_DIER_CC3IE TIM_DIER_CC3IE_Msk

Capture/Compare 3 interrupt enable

◆ TIM_DIER_CC3IE_Msk

#define TIM_DIER_CC3IE_Msk (0x1UL << TIM_DIER_CC3IE_Pos)

0x00000008

◆ TIM_DIER_CC3IE_Pos

#define TIM_DIER_CC3IE_Pos (3U)

◆ TIM_DIER_CC4DE

#define TIM_DIER_CC4DE TIM_DIER_CC4DE_Msk

Capture/Compare 4 DMA request enable

◆ TIM_DIER_CC4DE_Msk

#define TIM_DIER_CC4DE_Msk (0x1UL << TIM_DIER_CC4DE_Pos)

0x00001000

◆ TIM_DIER_CC4DE_Pos

#define TIM_DIER_CC4DE_Pos (12U)

◆ TIM_DIER_CC4IE

#define TIM_DIER_CC4IE TIM_DIER_CC4IE_Msk

Capture/Compare 4 interrupt enable

◆ TIM_DIER_CC4IE_Msk

#define TIM_DIER_CC4IE_Msk (0x1UL << TIM_DIER_CC4IE_Pos)

0x00000010

◆ TIM_DIER_CC4IE_Pos

#define TIM_DIER_CC4IE_Pos (4U)

◆ TIM_DIER_COMDE

#define TIM_DIER_COMDE TIM_DIER_COMDE_Msk

COM DMA request enable

◆ TIM_DIER_COMDE_Msk

#define TIM_DIER_COMDE_Msk (0x1UL << TIM_DIER_COMDE_Pos)

0x00002000

◆ TIM_DIER_COMDE_Pos

#define TIM_DIER_COMDE_Pos (13U)

◆ TIM_DIER_COMIE

#define TIM_DIER_COMIE TIM_DIER_COMIE_Msk

COM interrupt enable

◆ TIM_DIER_COMIE_Msk

#define TIM_DIER_COMIE_Msk (0x1UL << TIM_DIER_COMIE_Pos)

0x00000020

◆ TIM_DIER_COMIE_Pos

#define TIM_DIER_COMIE_Pos (5U)

◆ TIM_DIER_TDE

#define TIM_DIER_TDE TIM_DIER_TDE_Msk

Trigger DMA request enable

◆ TIM_DIER_TDE_Msk

#define TIM_DIER_TDE_Msk (0x1UL << TIM_DIER_TDE_Pos)

0x00004000

◆ TIM_DIER_TDE_Pos

#define TIM_DIER_TDE_Pos (14U)

◆ TIM_DIER_TIE

#define TIM_DIER_TIE TIM_DIER_TIE_Msk

Trigger interrupt enable

◆ TIM_DIER_TIE_Msk

#define TIM_DIER_TIE_Msk (0x1UL << TIM_DIER_TIE_Pos)

0x00000040

◆ TIM_DIER_TIE_Pos

#define TIM_DIER_TIE_Pos (6U)

◆ TIM_DIER_UDE

#define TIM_DIER_UDE TIM_DIER_UDE_Msk

Update DMA request enable

◆ TIM_DIER_UDE_Msk

#define TIM_DIER_UDE_Msk (0x1UL << TIM_DIER_UDE_Pos)

0x00000100

◆ TIM_DIER_UDE_Pos

#define TIM_DIER_UDE_Pos (8U)

◆ TIM_DIER_UIE

#define TIM_DIER_UIE TIM_DIER_UIE_Msk

Update interrupt enable

◆ TIM_DIER_UIE_Msk

#define TIM_DIER_UIE_Msk (0x1UL << TIM_DIER_UIE_Pos)

0x00000001

◆ TIM_DIER_UIE_Pos

#define TIM_DIER_UIE_Pos (0U)

◆ TIM_DMAR_DMAB

#define TIM_DMAR_DMAB TIM_DMAR_DMAB_Msk

DMA register for burst accesses

◆ TIM_DMAR_DMAB_Msk

#define TIM_DMAR_DMAB_Msk (0xFFFFUL << TIM_DMAR_DMAB_Pos)

0x0000FFFF

◆ TIM_DMAR_DMAB_Pos

#define TIM_DMAR_DMAB_Pos (0U)

◆ TIM_EGR_B2G

#define TIM_EGR_B2G TIM_EGR_B2G_Msk

Break Generation

◆ TIM_EGR_B2G_Msk

#define TIM_EGR_B2G_Msk (0x1UL << TIM_EGR_B2G_Pos)

0x00000100

◆ TIM_EGR_B2G_Pos

#define TIM_EGR_B2G_Pos (8U)

◆ TIM_EGR_BG

#define TIM_EGR_BG TIM_EGR_BG_Msk

Break Generation

◆ TIM_EGR_BG_Msk

#define TIM_EGR_BG_Msk (0x1UL << TIM_EGR_BG_Pos)

0x00000080

◆ TIM_EGR_BG_Pos

#define TIM_EGR_BG_Pos (7U)

◆ TIM_EGR_CC1G

#define TIM_EGR_CC1G TIM_EGR_CC1G_Msk

Capture/Compare 1 Generation

◆ TIM_EGR_CC1G_Msk

#define TIM_EGR_CC1G_Msk (0x1UL << TIM_EGR_CC1G_Pos)

0x00000002

◆ TIM_EGR_CC1G_Pos

#define TIM_EGR_CC1G_Pos (1U)

◆ TIM_EGR_CC2G

#define TIM_EGR_CC2G TIM_EGR_CC2G_Msk

Capture/Compare 2 Generation

◆ TIM_EGR_CC2G_Msk

#define TIM_EGR_CC2G_Msk (0x1UL << TIM_EGR_CC2G_Pos)

0x00000004

◆ TIM_EGR_CC2G_Pos

#define TIM_EGR_CC2G_Pos (2U)

◆ TIM_EGR_CC3G

#define TIM_EGR_CC3G TIM_EGR_CC3G_Msk

Capture/Compare 3 Generation

◆ TIM_EGR_CC3G_Msk

#define TIM_EGR_CC3G_Msk (0x1UL << TIM_EGR_CC3G_Pos)

0x00000008

◆ TIM_EGR_CC3G_Pos

#define TIM_EGR_CC3G_Pos (3U)

◆ TIM_EGR_CC4G

#define TIM_EGR_CC4G TIM_EGR_CC4G_Msk

Capture/Compare 4 Generation

◆ TIM_EGR_CC4G_Msk

#define TIM_EGR_CC4G_Msk (0x1UL << TIM_EGR_CC4G_Pos)

0x00000010

◆ TIM_EGR_CC4G_Pos

#define TIM_EGR_CC4G_Pos (4U)

◆ TIM_EGR_COMG

#define TIM_EGR_COMG TIM_EGR_COMG_Msk

Capture/Compare Control Update Generation

◆ TIM_EGR_COMG_Msk

#define TIM_EGR_COMG_Msk (0x1UL << TIM_EGR_COMG_Pos)

0x00000020

◆ TIM_EGR_COMG_Pos

#define TIM_EGR_COMG_Pos (5U)

◆ TIM_EGR_TG

#define TIM_EGR_TG TIM_EGR_TG_Msk

Trigger Generation

◆ TIM_EGR_TG_Msk

#define TIM_EGR_TG_Msk (0x1UL << TIM_EGR_TG_Pos)

0x00000040

◆ TIM_EGR_TG_Pos

#define TIM_EGR_TG_Pos (6U)

◆ TIM_EGR_UG

#define TIM_EGR_UG TIM_EGR_UG_Msk

Update Generation

◆ TIM_EGR_UG_Msk

#define TIM_EGR_UG_Msk (0x1UL << TIM_EGR_UG_Pos)

0x00000001

◆ TIM_EGR_UG_Pos

#define TIM_EGR_UG_Pos (0U)

◆ TIM_PSC_PSC

#define TIM_PSC_PSC TIM_PSC_PSC_Msk

Prescaler Value

◆ TIM_PSC_PSC_Msk

#define TIM_PSC_PSC_Msk (0xFFFFUL << TIM_PSC_PSC_Pos)

0x0000FFFF

◆ TIM_PSC_PSC_Pos

#define TIM_PSC_PSC_Pos (0U)

◆ TIM_RCR_REP

#define TIM_RCR_REP TIM_RCR_REP_Msk

Repetition Counter Value

◆ TIM_RCR_REP_Msk

#define TIM_RCR_REP_Msk (0xFFFFUL << TIM_RCR_REP_Pos)

0x0000FFFF

◆ TIM_RCR_REP_Pos

#define TIM_RCR_REP_Pos (0U)

◆ TIM_SMCR_ECE

#define TIM_SMCR_ECE TIM_SMCR_ECE_Msk

External clock enable

◆ TIM_SMCR_ECE_Msk

#define TIM_SMCR_ECE_Msk (0x1UL << TIM_SMCR_ECE_Pos)

0x00004000

◆ TIM_SMCR_ECE_Pos

#define TIM_SMCR_ECE_Pos (14U)

◆ TIM_SMCR_ETF

#define TIM_SMCR_ETF TIM_SMCR_ETF_Msk

ETF[3:0] bits (External trigger filter)

◆ TIM_SMCR_ETF_0

#define TIM_SMCR_ETF_0 (0x1UL << TIM_SMCR_ETF_Pos)

0x00000100

◆ TIM_SMCR_ETF_1

#define TIM_SMCR_ETF_1 (0x2UL << TIM_SMCR_ETF_Pos)

0x00000200

◆ TIM_SMCR_ETF_2

#define TIM_SMCR_ETF_2 (0x4UL << TIM_SMCR_ETF_Pos)

0x00000400

◆ TIM_SMCR_ETF_3

#define TIM_SMCR_ETF_3 (0x8UL << TIM_SMCR_ETF_Pos)

0x00000800

◆ TIM_SMCR_ETF_Msk

#define TIM_SMCR_ETF_Msk (0xFUL << TIM_SMCR_ETF_Pos)

0x00000F00

◆ TIM_SMCR_ETF_Pos

#define TIM_SMCR_ETF_Pos (8U)

◆ TIM_SMCR_ETP

#define TIM_SMCR_ETP TIM_SMCR_ETP_Msk

External trigger polarity

◆ TIM_SMCR_ETP_Msk

#define TIM_SMCR_ETP_Msk (0x1UL << TIM_SMCR_ETP_Pos)

0x00008000

◆ TIM_SMCR_ETP_Pos

#define TIM_SMCR_ETP_Pos (15U)

◆ TIM_SMCR_ETPS

#define TIM_SMCR_ETPS TIM_SMCR_ETPS_Msk

ETPS[1:0] bits (External trigger prescaler)

◆ TIM_SMCR_ETPS_0

#define TIM_SMCR_ETPS_0 (0x1UL << TIM_SMCR_ETPS_Pos)

0x00001000

◆ TIM_SMCR_ETPS_1

#define TIM_SMCR_ETPS_1 (0x2UL << TIM_SMCR_ETPS_Pos)

0x00002000

◆ TIM_SMCR_ETPS_Msk

#define TIM_SMCR_ETPS_Msk (0x3UL << TIM_SMCR_ETPS_Pos)

0x00003000

◆ TIM_SMCR_ETPS_Pos

#define TIM_SMCR_ETPS_Pos (12U)

◆ TIM_SMCR_MSM

#define TIM_SMCR_MSM TIM_SMCR_MSM_Msk

Master/slave mode

◆ TIM_SMCR_MSM_Msk

#define TIM_SMCR_MSM_Msk (0x1UL << TIM_SMCR_MSM_Pos)

0x00000080

◆ TIM_SMCR_MSM_Pos

#define TIM_SMCR_MSM_Pos (7U)

◆ TIM_SMCR_OCCS

#define TIM_SMCR_OCCS TIM_SMCR_OCCS_Msk

OCREF clear selection

◆ TIM_SMCR_OCCS_Msk

#define TIM_SMCR_OCCS_Msk (0x1UL << TIM_SMCR_OCCS_Pos)

0x00000008

◆ TIM_SMCR_OCCS_Pos

#define TIM_SMCR_OCCS_Pos (3U)

◆ TIM_SMCR_SMS

#define TIM_SMCR_SMS TIM_SMCR_SMS_Msk

SMS[2:0] bits (Slave mode selection)

◆ TIM_SMCR_SMS_0

#define TIM_SMCR_SMS_0 (0x00000001U)

Bit 0

◆ TIM_SMCR_SMS_1

#define TIM_SMCR_SMS_1 (0x00000002U)

Bit 1

◆ TIM_SMCR_SMS_2

#define TIM_SMCR_SMS_2 (0x00000004U)

Bit 2

◆ TIM_SMCR_SMS_3

#define TIM_SMCR_SMS_3 (0x00010000U)

Bit 3

◆ TIM_SMCR_SMS_Msk

#define TIM_SMCR_SMS_Msk (0x10007UL << TIM_SMCR_SMS_Pos)

0x00010007

◆ TIM_SMCR_SMS_Pos

#define TIM_SMCR_SMS_Pos (0U)

◆ TIM_SMCR_TS

#define TIM_SMCR_TS TIM_SMCR_TS_Msk

TS[2:0] bits (Trigger selection)

◆ TIM_SMCR_TS_0

#define TIM_SMCR_TS_0 (0x1UL << TIM_SMCR_TS_Pos)

0x00000010

◆ TIM_SMCR_TS_1

#define TIM_SMCR_TS_1 (0x2UL << TIM_SMCR_TS_Pos)

0x00000020

◆ TIM_SMCR_TS_2

#define TIM_SMCR_TS_2 (0x4UL << TIM_SMCR_TS_Pos)

0x00000040

◆ TIM_SMCR_TS_Msk

#define TIM_SMCR_TS_Msk (0x7UL << TIM_SMCR_TS_Pos)

0x00000070

◆ TIM_SMCR_TS_Pos

#define TIM_SMCR_TS_Pos (4U)

◆ TIM_SR_B2IF

#define TIM_SR_B2IF TIM_SR_B2IF_Msk

Break2 interrupt Flag

◆ TIM_SR_B2IF_Msk

#define TIM_SR_B2IF_Msk (0x1UL << TIM_SR_B2IF_Pos)

0x00000100

◆ TIM_SR_B2IF_Pos

#define TIM_SR_B2IF_Pos (8U)

◆ TIM_SR_BIF

#define TIM_SR_BIF TIM_SR_BIF_Msk

Break interrupt Flag

◆ TIM_SR_BIF_Msk

#define TIM_SR_BIF_Msk (0x1UL << TIM_SR_BIF_Pos)

0x00000080

◆ TIM_SR_BIF_Pos

#define TIM_SR_BIF_Pos (7U)

◆ TIM_SR_CC1IF

#define TIM_SR_CC1IF TIM_SR_CC1IF_Msk

Capture/Compare 1 interrupt Flag

◆ TIM_SR_CC1IF_Msk

#define TIM_SR_CC1IF_Msk (0x1UL << TIM_SR_CC1IF_Pos)

0x00000002

◆ TIM_SR_CC1IF_Pos

#define TIM_SR_CC1IF_Pos (1U)

◆ TIM_SR_CC1OF

#define TIM_SR_CC1OF TIM_SR_CC1OF_Msk

Capture/Compare 1 Overcapture Flag

◆ TIM_SR_CC1OF_Msk

#define TIM_SR_CC1OF_Msk (0x1UL << TIM_SR_CC1OF_Pos)

0x00000200

◆ TIM_SR_CC1OF_Pos

#define TIM_SR_CC1OF_Pos (9U)

◆ TIM_SR_CC2IF

#define TIM_SR_CC2IF TIM_SR_CC2IF_Msk

Capture/Compare 2 interrupt Flag

◆ TIM_SR_CC2IF_Msk

#define TIM_SR_CC2IF_Msk (0x1UL << TIM_SR_CC2IF_Pos)

0x00000004

◆ TIM_SR_CC2IF_Pos

#define TIM_SR_CC2IF_Pos (2U)

◆ TIM_SR_CC2OF

#define TIM_SR_CC2OF TIM_SR_CC2OF_Msk

Capture/Compare 2 Overcapture Flag

◆ TIM_SR_CC2OF_Msk

#define TIM_SR_CC2OF_Msk (0x1UL << TIM_SR_CC2OF_Pos)

0x00000400

◆ TIM_SR_CC2OF_Pos

#define TIM_SR_CC2OF_Pos (10U)

◆ TIM_SR_CC3IF

#define TIM_SR_CC3IF TIM_SR_CC3IF_Msk

Capture/Compare 3 interrupt Flag

◆ TIM_SR_CC3IF_Msk

#define TIM_SR_CC3IF_Msk (0x1UL << TIM_SR_CC3IF_Pos)

0x00000008

◆ TIM_SR_CC3IF_Pos

#define TIM_SR_CC3IF_Pos (3U)

◆ TIM_SR_CC3OF

#define TIM_SR_CC3OF TIM_SR_CC3OF_Msk

Capture/Compare 3 Overcapture Flag

◆ TIM_SR_CC3OF_Msk

#define TIM_SR_CC3OF_Msk (0x1UL << TIM_SR_CC3OF_Pos)

0x00000800

◆ TIM_SR_CC3OF_Pos

#define TIM_SR_CC3OF_Pos (11U)

◆ TIM_SR_CC4IF

#define TIM_SR_CC4IF TIM_SR_CC4IF_Msk

Capture/Compare 4 interrupt Flag

◆ TIM_SR_CC4IF_Msk

#define TIM_SR_CC4IF_Msk (0x1UL << TIM_SR_CC4IF_Pos)

0x00000010

◆ TIM_SR_CC4IF_Pos

#define TIM_SR_CC4IF_Pos (4U)

◆ TIM_SR_CC4OF

#define TIM_SR_CC4OF TIM_SR_CC4OF_Msk

Capture/Compare 4 Overcapture Flag

◆ TIM_SR_CC4OF_Msk

#define TIM_SR_CC4OF_Msk (0x1UL << TIM_SR_CC4OF_Pos)

0x00001000

◆ TIM_SR_CC4OF_Pos

#define TIM_SR_CC4OF_Pos (12U)

◆ TIM_SR_CC5IF

#define TIM_SR_CC5IF TIM_SR_CC5IF_Msk

Capture/Compare 5 interrupt Flag

◆ TIM_SR_CC5IF_Msk

#define TIM_SR_CC5IF_Msk (0x1UL << TIM_SR_CC5IF_Pos)

0x00010000

◆ TIM_SR_CC5IF_Pos

#define TIM_SR_CC5IF_Pos (16U)

◆ TIM_SR_CC6IF

#define TIM_SR_CC6IF TIM_SR_CC6IF_Msk

Capture/Compare 6 interrupt Flag

◆ TIM_SR_CC6IF_Msk

#define TIM_SR_CC6IF_Msk (0x1UL << TIM_SR_CC6IF_Pos)

0x00020000

◆ TIM_SR_CC6IF_Pos

#define TIM_SR_CC6IF_Pos (17U)

◆ TIM_SR_COMIF

#define TIM_SR_COMIF TIM_SR_COMIF_Msk

COM interrupt Flag

◆ TIM_SR_COMIF_Msk

#define TIM_SR_COMIF_Msk (0x1UL << TIM_SR_COMIF_Pos)

0x00000020

◆ TIM_SR_COMIF_Pos

#define TIM_SR_COMIF_Pos (5U)

◆ TIM_SR_TIF

#define TIM_SR_TIF TIM_SR_TIF_Msk

Trigger interrupt Flag

◆ TIM_SR_TIF_Msk

#define TIM_SR_TIF_Msk (0x1UL << TIM_SR_TIF_Pos)

0x00000040

◆ TIM_SR_TIF_Pos

#define TIM_SR_TIF_Pos (6U)

◆ TIM_SR_UIF

#define TIM_SR_UIF TIM_SR_UIF_Msk

Update interrupt Flag

◆ TIM_SR_UIF_Msk

#define TIM_SR_UIF_Msk (0x1UL << TIM_SR_UIF_Pos)

0x00000001

◆ TIM_SR_UIF_Pos

#define TIM_SR_UIF_Pos (0U)

◆ TSC_CR_AM

#define TSC_CR_AM TSC_CR_AM_Msk

Acquisition mode

◆ TSC_CR_AM_Msk

#define TSC_CR_AM_Msk (0x1UL << TSC_CR_AM_Pos)

0x00000004

◆ TSC_CR_AM_Pos

#define TSC_CR_AM_Pos (2U)

◆ TSC_CR_CTPH

#define TSC_CR_CTPH TSC_CR_CTPH_Msk

CTPH[3:0] bits (Charge Transfer pulse high)

◆ TSC_CR_CTPH_0

#define TSC_CR_CTPH_0 (0x1UL << TSC_CR_CTPH_Pos)

0x10000000

◆ TSC_CR_CTPH_1

#define TSC_CR_CTPH_1 (0x2UL << TSC_CR_CTPH_Pos)

0x20000000

◆ TSC_CR_CTPH_2

#define TSC_CR_CTPH_2 (0x4UL << TSC_CR_CTPH_Pos)

0x40000000

◆ TSC_CR_CTPH_3

#define TSC_CR_CTPH_3 (0x8UL << TSC_CR_CTPH_Pos)

0x80000000

◆ TSC_CR_CTPH_Msk

#define TSC_CR_CTPH_Msk (0xFUL << TSC_CR_CTPH_Pos)

0xF0000000

◆ TSC_CR_CTPH_Pos

#define TSC_CR_CTPH_Pos (28U)

◆ TSC_CR_CTPL

#define TSC_CR_CTPL TSC_CR_CTPL_Msk

CTPL[3:0] bits (Charge Transfer pulse low)

◆ TSC_CR_CTPL_0

#define TSC_CR_CTPL_0 (0x1UL << TSC_CR_CTPL_Pos)

0x01000000

◆ TSC_CR_CTPL_1

#define TSC_CR_CTPL_1 (0x2UL << TSC_CR_CTPL_Pos)

0x02000000

◆ TSC_CR_CTPL_2

#define TSC_CR_CTPL_2 (0x4UL << TSC_CR_CTPL_Pos)

0x04000000

◆ TSC_CR_CTPL_3

#define TSC_CR_CTPL_3 (0x8UL << TSC_CR_CTPL_Pos)

0x08000000

◆ TSC_CR_CTPL_Msk

#define TSC_CR_CTPL_Msk (0xFUL << TSC_CR_CTPL_Pos)

0x0F000000

◆ TSC_CR_CTPL_Pos

#define TSC_CR_CTPL_Pos (24U)

◆ TSC_CR_IODEF

#define TSC_CR_IODEF TSC_CR_IODEF_Msk

IO default mode

◆ TSC_CR_IODEF_Msk

#define TSC_CR_IODEF_Msk (0x1UL << TSC_CR_IODEF_Pos)

0x00000010

◆ TSC_CR_IODEF_Pos

#define TSC_CR_IODEF_Pos (4U)

◆ TSC_CR_MCV

#define TSC_CR_MCV TSC_CR_MCV_Msk

MCV[2:0] bits (Max Count Value)

◆ TSC_CR_MCV_0

#define TSC_CR_MCV_0 (0x1UL << TSC_CR_MCV_Pos)

0x00000020

◆ TSC_CR_MCV_1

#define TSC_CR_MCV_1 (0x2UL << TSC_CR_MCV_Pos)

0x00000040

◆ TSC_CR_MCV_2

#define TSC_CR_MCV_2 (0x4UL << TSC_CR_MCV_Pos)

0x00000080

◆ TSC_CR_MCV_Msk

#define TSC_CR_MCV_Msk (0x7UL << TSC_CR_MCV_Pos)

0x000000E0

◆ TSC_CR_MCV_Pos

#define TSC_CR_MCV_Pos (5U)

◆ TSC_CR_PGPSC

#define TSC_CR_PGPSC TSC_CR_PGPSC_Msk

PGPSC[2:0] bits (Pulse Generator Prescaler)

◆ TSC_CR_PGPSC_0

#define TSC_CR_PGPSC_0 (0x1UL << TSC_CR_PGPSC_Pos)

0x00001000

◆ TSC_CR_PGPSC_1

#define TSC_CR_PGPSC_1 (0x2UL << TSC_CR_PGPSC_Pos)

0x00002000

◆ TSC_CR_PGPSC_2

#define TSC_CR_PGPSC_2 (0x4UL << TSC_CR_PGPSC_Pos)

0x00004000

◆ TSC_CR_PGPSC_Msk

#define TSC_CR_PGPSC_Msk (0x7UL << TSC_CR_PGPSC_Pos)

0x00007000

◆ TSC_CR_PGPSC_Pos

#define TSC_CR_PGPSC_Pos (12U)

◆ TSC_CR_SSD

#define TSC_CR_SSD TSC_CR_SSD_Msk

SSD[6:0] bits (Spread Spectrum Deviation)

◆ TSC_CR_SSD_0

#define TSC_CR_SSD_0 (0x01UL << TSC_CR_SSD_Pos)

0x00020000

◆ TSC_CR_SSD_1

#define TSC_CR_SSD_1 (0x02UL << TSC_CR_SSD_Pos)

0x00040000

◆ TSC_CR_SSD_2

#define TSC_CR_SSD_2 (0x04UL << TSC_CR_SSD_Pos)

0x00080000

◆ TSC_CR_SSD_3

#define TSC_CR_SSD_3 (0x08UL << TSC_CR_SSD_Pos)

0x00100000

◆ TSC_CR_SSD_4

#define TSC_CR_SSD_4 (0x10UL << TSC_CR_SSD_Pos)

0x00200000

◆ TSC_CR_SSD_5

#define TSC_CR_SSD_5 (0x20UL << TSC_CR_SSD_Pos)

0x00400000

◆ TSC_CR_SSD_6

#define TSC_CR_SSD_6 (0x40UL << TSC_CR_SSD_Pos)

0x00800000

◆ TSC_CR_SSD_Msk

#define TSC_CR_SSD_Msk (0x7FUL << TSC_CR_SSD_Pos)

0x00FE0000

◆ TSC_CR_SSD_Pos

#define TSC_CR_SSD_Pos (17U)

◆ TSC_CR_SSE

#define TSC_CR_SSE TSC_CR_SSE_Msk

Spread Spectrum Enable

◆ TSC_CR_SSE_Msk

#define TSC_CR_SSE_Msk (0x1UL << TSC_CR_SSE_Pos)

0x00010000

◆ TSC_CR_SSE_Pos

#define TSC_CR_SSE_Pos (16U)

◆ TSC_CR_SSPSC

#define TSC_CR_SSPSC TSC_CR_SSPSC_Msk

Spread Spectrum Prescaler

◆ TSC_CR_SSPSC_Msk

#define TSC_CR_SSPSC_Msk (0x1UL << TSC_CR_SSPSC_Pos)

0x00008000

◆ TSC_CR_SSPSC_Pos

#define TSC_CR_SSPSC_Pos (15U)

◆ TSC_CR_START

#define TSC_CR_START TSC_CR_START_Msk

Start acquisition

◆ TSC_CR_START_Msk

#define TSC_CR_START_Msk (0x1UL << TSC_CR_START_Pos)

0x00000002

◆ TSC_CR_START_Pos

#define TSC_CR_START_Pos (1U)

◆ TSC_CR_SYNCPOL

#define TSC_CR_SYNCPOL TSC_CR_SYNCPOL_Msk

Synchronization pin polarity

◆ TSC_CR_SYNCPOL_Msk

#define TSC_CR_SYNCPOL_Msk (0x1UL << TSC_CR_SYNCPOL_Pos)

0x00000008

◆ TSC_CR_SYNCPOL_Pos

#define TSC_CR_SYNCPOL_Pos (3U)

◆ TSC_CR_TSCE

#define TSC_CR_TSCE TSC_CR_TSCE_Msk

Touch sensing controller enable

◆ TSC_CR_TSCE_Msk

#define TSC_CR_TSCE_Msk (0x1UL << TSC_CR_TSCE_Pos)

0x00000001

◆ TSC_CR_TSCE_Pos

#define TSC_CR_TSCE_Pos (0U)

◆ TSC_ICR_EOAIC

#define TSC_ICR_EOAIC TSC_ICR_EOAIC_Msk

End of acquisition interrupt clear

◆ TSC_ICR_EOAIC_Msk

#define TSC_ICR_EOAIC_Msk (0x1UL << TSC_ICR_EOAIC_Pos)

0x00000001

◆ TSC_ICR_EOAIC_Pos

#define TSC_ICR_EOAIC_Pos (0U)

◆ TSC_ICR_MCEIC

#define TSC_ICR_MCEIC TSC_ICR_MCEIC_Msk

Max count error interrupt clear

◆ TSC_ICR_MCEIC_Msk

#define TSC_ICR_MCEIC_Msk (0x1UL << TSC_ICR_MCEIC_Pos)

0x00000002

◆ TSC_ICR_MCEIC_Pos

#define TSC_ICR_MCEIC_Pos (1U)

◆ TSC_IER_EOAIE

#define TSC_IER_EOAIE TSC_IER_EOAIE_Msk

End of acquisition interrupt enable

◆ TSC_IER_EOAIE_Msk

#define TSC_IER_EOAIE_Msk (0x1UL << TSC_IER_EOAIE_Pos)

0x00000001

◆ TSC_IER_EOAIE_Pos

#define TSC_IER_EOAIE_Pos (0U)

◆ TSC_IER_MCEIE

#define TSC_IER_MCEIE TSC_IER_MCEIE_Msk

Max count error interrupt enable

◆ TSC_IER_MCEIE_Msk

#define TSC_IER_MCEIE_Msk (0x1UL << TSC_IER_MCEIE_Pos)

0x00000002

◆ TSC_IER_MCEIE_Pos

#define TSC_IER_MCEIE_Pos (1U)

◆ TSC_IOASCR_G1_IO1

#define TSC_IOASCR_G1_IO1 TSC_IOASCR_G1_IO1_Msk

GROUP1_IO1 analog switch enable

◆ TSC_IOASCR_G1_IO1_Msk

#define TSC_IOASCR_G1_IO1_Msk (0x1UL << TSC_IOASCR_G1_IO1_Pos)

0x00000001

◆ TSC_IOASCR_G1_IO1_Pos

#define TSC_IOASCR_G1_IO1_Pos (0U)

◆ TSC_IOASCR_G1_IO2

#define TSC_IOASCR_G1_IO2 TSC_IOASCR_G1_IO2_Msk

GROUP1_IO2 analog switch enable

◆ TSC_IOASCR_G1_IO2_Msk

#define TSC_IOASCR_G1_IO2_Msk (0x1UL << TSC_IOASCR_G1_IO2_Pos)

0x00000002

◆ TSC_IOASCR_G1_IO2_Pos

#define TSC_IOASCR_G1_IO2_Pos (1U)

◆ TSC_IOASCR_G1_IO3

#define TSC_IOASCR_G1_IO3 TSC_IOASCR_G1_IO3_Msk

GROUP1_IO3 analog switch enable

◆ TSC_IOASCR_G1_IO3_Msk

#define TSC_IOASCR_G1_IO3_Msk (0x1UL << TSC_IOASCR_G1_IO3_Pos)

0x00000004

◆ TSC_IOASCR_G1_IO3_Pos

#define TSC_IOASCR_G1_IO3_Pos (2U)

◆ TSC_IOASCR_G1_IO4

#define TSC_IOASCR_G1_IO4 TSC_IOASCR_G1_IO4_Msk

GROUP1_IO4 analog switch enable

◆ TSC_IOASCR_G1_IO4_Msk

#define TSC_IOASCR_G1_IO4_Msk (0x1UL << TSC_IOASCR_G1_IO4_Pos)

0x00000008

◆ TSC_IOASCR_G1_IO4_Pos

#define TSC_IOASCR_G1_IO4_Pos (3U)

◆ TSC_IOASCR_G2_IO1

#define TSC_IOASCR_G2_IO1 TSC_IOASCR_G2_IO1_Msk

GROUP2_IO1 analog switch enable

◆ TSC_IOASCR_G2_IO1_Msk

#define TSC_IOASCR_G2_IO1_Msk (0x1UL << TSC_IOASCR_G2_IO1_Pos)

0x00000010

◆ TSC_IOASCR_G2_IO1_Pos

#define TSC_IOASCR_G2_IO1_Pos (4U)

◆ TSC_IOASCR_G2_IO2

#define TSC_IOASCR_G2_IO2 TSC_IOASCR_G2_IO2_Msk

GROUP2_IO2 analog switch enable

◆ TSC_IOASCR_G2_IO2_Msk

#define TSC_IOASCR_G2_IO2_Msk (0x1UL << TSC_IOASCR_G2_IO2_Pos)

0x00000020

◆ TSC_IOASCR_G2_IO2_Pos

#define TSC_IOASCR_G2_IO2_Pos (5U)

◆ TSC_IOASCR_G2_IO3

#define TSC_IOASCR_G2_IO3 TSC_IOASCR_G2_IO3_Msk

GROUP2_IO3 analog switch enable

◆ TSC_IOASCR_G2_IO3_Msk

#define TSC_IOASCR_G2_IO3_Msk (0x1UL << TSC_IOASCR_G2_IO3_Pos)

0x00000040

◆ TSC_IOASCR_G2_IO3_Pos

#define TSC_IOASCR_G2_IO3_Pos (6U)

◆ TSC_IOASCR_G2_IO4

#define TSC_IOASCR_G2_IO4 TSC_IOASCR_G2_IO4_Msk

GROUP2_IO4 analog switch enable

◆ TSC_IOASCR_G2_IO4_Msk

#define TSC_IOASCR_G2_IO4_Msk (0x1UL << TSC_IOASCR_G2_IO4_Pos)

0x00000080

◆ TSC_IOASCR_G2_IO4_Pos

#define TSC_IOASCR_G2_IO4_Pos (7U)

◆ TSC_IOASCR_G3_IO1

#define TSC_IOASCR_G3_IO1 TSC_IOASCR_G3_IO1_Msk

GROUP3_IO1 analog switch enable

◆ TSC_IOASCR_G3_IO1_Msk

#define TSC_IOASCR_G3_IO1_Msk (0x1UL << TSC_IOASCR_G3_IO1_Pos)

0x00000100

◆ TSC_IOASCR_G3_IO1_Pos

#define TSC_IOASCR_G3_IO1_Pos (8U)

◆ TSC_IOASCR_G3_IO2

#define TSC_IOASCR_G3_IO2 TSC_IOASCR_G3_IO2_Msk

GROUP3_IO2 analog switch enable

◆ TSC_IOASCR_G3_IO2_Msk

#define TSC_IOASCR_G3_IO2_Msk (0x1UL << TSC_IOASCR_G3_IO2_Pos)

0x00000200

◆ TSC_IOASCR_G3_IO2_Pos

#define TSC_IOASCR_G3_IO2_Pos (9U)

◆ TSC_IOASCR_G3_IO3

#define TSC_IOASCR_G3_IO3 TSC_IOASCR_G3_IO3_Msk

GROUP3_IO3 analog switch enable

◆ TSC_IOASCR_G3_IO3_Msk

#define TSC_IOASCR_G3_IO3_Msk (0x1UL << TSC_IOASCR_G3_IO3_Pos)

0x00000400

◆ TSC_IOASCR_G3_IO3_Pos

#define TSC_IOASCR_G3_IO3_Pos (10U)

◆ TSC_IOASCR_G3_IO4

#define TSC_IOASCR_G3_IO4 TSC_IOASCR_G3_IO4_Msk

GROUP3_IO4 analog switch enable

◆ TSC_IOASCR_G3_IO4_Msk

#define TSC_IOASCR_G3_IO4_Msk (0x1UL << TSC_IOASCR_G3_IO4_Pos)

0x00000800

◆ TSC_IOASCR_G3_IO4_Pos

#define TSC_IOASCR_G3_IO4_Pos (11U)

◆ TSC_IOASCR_G4_IO1

#define TSC_IOASCR_G4_IO1 TSC_IOASCR_G4_IO1_Msk

GROUP4_IO1 analog switch enable

◆ TSC_IOASCR_G4_IO1_Msk

#define TSC_IOASCR_G4_IO1_Msk (0x1UL << TSC_IOASCR_G4_IO1_Pos)

0x00001000

◆ TSC_IOASCR_G4_IO1_Pos

#define TSC_IOASCR_G4_IO1_Pos (12U)

◆ TSC_IOASCR_G4_IO2

#define TSC_IOASCR_G4_IO2 TSC_IOASCR_G4_IO2_Msk

GROUP4_IO2 analog switch enable

◆ TSC_IOASCR_G4_IO2_Msk

#define TSC_IOASCR_G4_IO2_Msk (0x1UL << TSC_IOASCR_G4_IO2_Pos)

0x00002000

◆ TSC_IOASCR_G4_IO2_Pos

#define TSC_IOASCR_G4_IO2_Pos (13U)

◆ TSC_IOASCR_G4_IO3

#define TSC_IOASCR_G4_IO3 TSC_IOASCR_G4_IO3_Msk

GROUP4_IO3 analog switch enable

◆ TSC_IOASCR_G4_IO3_Msk

#define TSC_IOASCR_G4_IO3_Msk (0x1UL << TSC_IOASCR_G4_IO3_Pos)

0x00004000

◆ TSC_IOASCR_G4_IO3_Pos

#define TSC_IOASCR_G4_IO3_Pos (14U)

◆ TSC_IOASCR_G4_IO4

#define TSC_IOASCR_G4_IO4 TSC_IOASCR_G4_IO4_Msk

GROUP4_IO4 analog switch enable

◆ TSC_IOASCR_G4_IO4_Msk

#define TSC_IOASCR_G4_IO4_Msk (0x1UL << TSC_IOASCR_G4_IO4_Pos)

0x00008000

◆ TSC_IOASCR_G4_IO4_Pos

#define TSC_IOASCR_G4_IO4_Pos (15U)

◆ TSC_IOASCR_G5_IO1

#define TSC_IOASCR_G5_IO1 TSC_IOASCR_G5_IO1_Msk

GROUP5_IO1 analog switch enable

◆ TSC_IOASCR_G5_IO1_Msk

#define TSC_IOASCR_G5_IO1_Msk (0x1UL << TSC_IOASCR_G5_IO1_Pos)

0x00010000

◆ TSC_IOASCR_G5_IO1_Pos

#define TSC_IOASCR_G5_IO1_Pos (16U)

◆ TSC_IOASCR_G5_IO2

#define TSC_IOASCR_G5_IO2 TSC_IOASCR_G5_IO2_Msk

GROUP5_IO2 analog switch enable

◆ TSC_IOASCR_G5_IO2_Msk

#define TSC_IOASCR_G5_IO2_Msk (0x1UL << TSC_IOASCR_G5_IO2_Pos)

0x00020000

◆ TSC_IOASCR_G5_IO2_Pos

#define TSC_IOASCR_G5_IO2_Pos (17U)

◆ TSC_IOASCR_G5_IO3

#define TSC_IOASCR_G5_IO3 TSC_IOASCR_G5_IO3_Msk

GROUP5_IO3 analog switch enable

◆ TSC_IOASCR_G5_IO3_Msk

#define TSC_IOASCR_G5_IO3_Msk (0x1UL << TSC_IOASCR_G5_IO3_Pos)

0x00040000

◆ TSC_IOASCR_G5_IO3_Pos

#define TSC_IOASCR_G5_IO3_Pos (18U)

◆ TSC_IOASCR_G5_IO4

#define TSC_IOASCR_G5_IO4 TSC_IOASCR_G5_IO4_Msk

GROUP5_IO4 analog switch enable

◆ TSC_IOASCR_G5_IO4_Msk

#define TSC_IOASCR_G5_IO4_Msk (0x1UL << TSC_IOASCR_G5_IO4_Pos)

0x00080000

◆ TSC_IOASCR_G5_IO4_Pos

#define TSC_IOASCR_G5_IO4_Pos (19U)

◆ TSC_IOASCR_G6_IO1

#define TSC_IOASCR_G6_IO1 TSC_IOASCR_G6_IO1_Msk

GROUP6_IO1 analog switch enable

◆ TSC_IOASCR_G6_IO1_Msk

#define TSC_IOASCR_G6_IO1_Msk (0x1UL << TSC_IOASCR_G6_IO1_Pos)

0x00100000

◆ TSC_IOASCR_G6_IO1_Pos

#define TSC_IOASCR_G6_IO1_Pos (20U)

◆ TSC_IOASCR_G6_IO2

#define TSC_IOASCR_G6_IO2 TSC_IOASCR_G6_IO2_Msk

GROUP6_IO2 analog switch enable

◆ TSC_IOASCR_G6_IO2_Msk

#define TSC_IOASCR_G6_IO2_Msk (0x1UL << TSC_IOASCR_G6_IO2_Pos)

0x00200000

◆ TSC_IOASCR_G6_IO2_Pos

#define TSC_IOASCR_G6_IO2_Pos (21U)

◆ TSC_IOASCR_G6_IO3

#define TSC_IOASCR_G6_IO3 TSC_IOASCR_G6_IO3_Msk

GROUP6_IO3 analog switch enable

◆ TSC_IOASCR_G6_IO3_Msk

#define TSC_IOASCR_G6_IO3_Msk (0x1UL << TSC_IOASCR_G6_IO3_Pos)

0x00400000

◆ TSC_IOASCR_G6_IO3_Pos

#define TSC_IOASCR_G6_IO3_Pos (22U)

◆ TSC_IOASCR_G6_IO4

#define TSC_IOASCR_G6_IO4 TSC_IOASCR_G6_IO4_Msk

GROUP6_IO4 analog switch enable

◆ TSC_IOASCR_G6_IO4_Msk

#define TSC_IOASCR_G6_IO4_Msk (0x1UL << TSC_IOASCR_G6_IO4_Pos)

0x00800000

◆ TSC_IOASCR_G6_IO4_Pos

#define TSC_IOASCR_G6_IO4_Pos (23U)

◆ TSC_IOASCR_G7_IO1

#define TSC_IOASCR_G7_IO1 TSC_IOASCR_G7_IO1_Msk

GROUP7_IO1 analog switch enable

◆ TSC_IOASCR_G7_IO1_Msk

#define TSC_IOASCR_G7_IO1_Msk (0x1UL << TSC_IOASCR_G7_IO1_Pos)

0x01000000

◆ TSC_IOASCR_G7_IO1_Pos

#define TSC_IOASCR_G7_IO1_Pos (24U)

◆ TSC_IOASCR_G7_IO2

#define TSC_IOASCR_G7_IO2 TSC_IOASCR_G7_IO2_Msk

GROUP7_IO2 analog switch enable

◆ TSC_IOASCR_G7_IO2_Msk

#define TSC_IOASCR_G7_IO2_Msk (0x1UL << TSC_IOASCR_G7_IO2_Pos)

0x02000000

◆ TSC_IOASCR_G7_IO2_Pos

#define TSC_IOASCR_G7_IO2_Pos (25U)

◆ TSC_IOASCR_G7_IO3

#define TSC_IOASCR_G7_IO3 TSC_IOASCR_G7_IO3_Msk

GROUP7_IO3 analog switch enable

◆ TSC_IOASCR_G7_IO3_Msk

#define TSC_IOASCR_G7_IO3_Msk (0x1UL << TSC_IOASCR_G7_IO3_Pos)

0x04000000

◆ TSC_IOASCR_G7_IO3_Pos

#define TSC_IOASCR_G7_IO3_Pos (26U)

◆ TSC_IOASCR_G7_IO4

#define TSC_IOASCR_G7_IO4 TSC_IOASCR_G7_IO4_Msk

GROUP7_IO4 analog switch enable

◆ TSC_IOASCR_G7_IO4_Msk

#define TSC_IOASCR_G7_IO4_Msk (0x1UL << TSC_IOASCR_G7_IO4_Pos)

0x08000000

◆ TSC_IOASCR_G7_IO4_Pos

#define TSC_IOASCR_G7_IO4_Pos (27U)

◆ TSC_IOASCR_G8_IO1

#define TSC_IOASCR_G8_IO1 TSC_IOASCR_G8_IO1_Msk

GROUP8_IO1 analog switch enable

◆ TSC_IOASCR_G8_IO1_Msk

#define TSC_IOASCR_G8_IO1_Msk (0x1UL << TSC_IOASCR_G8_IO1_Pos)

0x10000000

◆ TSC_IOASCR_G8_IO1_Pos

#define TSC_IOASCR_G8_IO1_Pos (28U)

◆ TSC_IOASCR_G8_IO2

#define TSC_IOASCR_G8_IO2 TSC_IOASCR_G8_IO2_Msk

GROUP8_IO2 analog switch enable

◆ TSC_IOASCR_G8_IO2_Msk

#define TSC_IOASCR_G8_IO2_Msk (0x1UL << TSC_IOASCR_G8_IO2_Pos)

0x20000000

◆ TSC_IOASCR_G8_IO2_Pos

#define TSC_IOASCR_G8_IO2_Pos (29U)

◆ TSC_IOASCR_G8_IO3

#define TSC_IOASCR_G8_IO3 TSC_IOASCR_G8_IO3_Msk

GROUP8_IO3 analog switch enable

◆ TSC_IOASCR_G8_IO3_Msk

#define TSC_IOASCR_G8_IO3_Msk (0x1UL << TSC_IOASCR_G8_IO3_Pos)

0x40000000

◆ TSC_IOASCR_G8_IO3_Pos

#define TSC_IOASCR_G8_IO3_Pos (30U)

◆ TSC_IOASCR_G8_IO4

#define TSC_IOASCR_G8_IO4 TSC_IOASCR_G8_IO4_Msk

GROUP8_IO4 analog switch enable

◆ TSC_IOASCR_G8_IO4_Msk

#define TSC_IOASCR_G8_IO4_Msk (0x1UL << TSC_IOASCR_G8_IO4_Pos)

0x80000000

◆ TSC_IOASCR_G8_IO4_Pos

#define TSC_IOASCR_G8_IO4_Pos (31U)

◆ TSC_IOCCR_G1_IO1

#define TSC_IOCCR_G1_IO1 TSC_IOCCR_G1_IO1_Msk

GROUP1_IO1 channel mode

◆ TSC_IOCCR_G1_IO1_Msk

#define TSC_IOCCR_G1_IO1_Msk (0x1UL << TSC_IOCCR_G1_IO1_Pos)

0x00000001

◆ TSC_IOCCR_G1_IO1_Pos

#define TSC_IOCCR_G1_IO1_Pos (0U)

◆ TSC_IOCCR_G1_IO2

#define TSC_IOCCR_G1_IO2 TSC_IOCCR_G1_IO2_Msk

GROUP1_IO2 channel mode

◆ TSC_IOCCR_G1_IO2_Msk

#define TSC_IOCCR_G1_IO2_Msk (0x1UL << TSC_IOCCR_G1_IO2_Pos)

0x00000002

◆ TSC_IOCCR_G1_IO2_Pos

#define TSC_IOCCR_G1_IO2_Pos (1U)

◆ TSC_IOCCR_G1_IO3

#define TSC_IOCCR_G1_IO3 TSC_IOCCR_G1_IO3_Msk

GROUP1_IO3 channel mode

◆ TSC_IOCCR_G1_IO3_Msk

#define TSC_IOCCR_G1_IO3_Msk (0x1UL << TSC_IOCCR_G1_IO3_Pos)

0x00000004

◆ TSC_IOCCR_G1_IO3_Pos

#define TSC_IOCCR_G1_IO3_Pos (2U)

◆ TSC_IOCCR_G1_IO4

#define TSC_IOCCR_G1_IO4 TSC_IOCCR_G1_IO4_Msk

GROUP1_IO4 channel mode

◆ TSC_IOCCR_G1_IO4_Msk

#define TSC_IOCCR_G1_IO4_Msk (0x1UL << TSC_IOCCR_G1_IO4_Pos)

0x00000008

◆ TSC_IOCCR_G1_IO4_Pos

#define TSC_IOCCR_G1_IO4_Pos (3U)

◆ TSC_IOCCR_G2_IO1

#define TSC_IOCCR_G2_IO1 TSC_IOCCR_G2_IO1_Msk

GROUP2_IO1 channel mode

◆ TSC_IOCCR_G2_IO1_Msk

#define TSC_IOCCR_G2_IO1_Msk (0x1UL << TSC_IOCCR_G2_IO1_Pos)

0x00000010

◆ TSC_IOCCR_G2_IO1_Pos

#define TSC_IOCCR_G2_IO1_Pos (4U)

◆ TSC_IOCCR_G2_IO2

#define TSC_IOCCR_G2_IO2 TSC_IOCCR_G2_IO2_Msk

GROUP2_IO2 channel mode

◆ TSC_IOCCR_G2_IO2_Msk

#define TSC_IOCCR_G2_IO2_Msk (0x1UL << TSC_IOCCR_G2_IO2_Pos)

0x00000020

◆ TSC_IOCCR_G2_IO2_Pos

#define TSC_IOCCR_G2_IO2_Pos (5U)

◆ TSC_IOCCR_G2_IO3

#define TSC_IOCCR_G2_IO3 TSC_IOCCR_G2_IO3_Msk

GROUP2_IO3 channel mode

◆ TSC_IOCCR_G2_IO3_Msk

#define TSC_IOCCR_G2_IO3_Msk (0x1UL << TSC_IOCCR_G2_IO3_Pos)

0x00000040

◆ TSC_IOCCR_G2_IO3_Pos

#define TSC_IOCCR_G2_IO3_Pos (6U)

◆ TSC_IOCCR_G2_IO4

#define TSC_IOCCR_G2_IO4 TSC_IOCCR_G2_IO4_Msk

GROUP2_IO4 channel mode

◆ TSC_IOCCR_G2_IO4_Msk

#define TSC_IOCCR_G2_IO4_Msk (0x1UL << TSC_IOCCR_G2_IO4_Pos)

0x00000080

◆ TSC_IOCCR_G2_IO4_Pos

#define TSC_IOCCR_G2_IO4_Pos (7U)

◆ TSC_IOCCR_G3_IO1

#define TSC_IOCCR_G3_IO1 TSC_IOCCR_G3_IO1_Msk

GROUP3_IO1 channel mode

◆ TSC_IOCCR_G3_IO1_Msk

#define TSC_IOCCR_G3_IO1_Msk (0x1UL << TSC_IOCCR_G3_IO1_Pos)

0x00000100

◆ TSC_IOCCR_G3_IO1_Pos

#define TSC_IOCCR_G3_IO1_Pos (8U)

◆ TSC_IOCCR_G3_IO2

#define TSC_IOCCR_G3_IO2 TSC_IOCCR_G3_IO2_Msk

GROUP3_IO2 channel mode

◆ TSC_IOCCR_G3_IO2_Msk

#define TSC_IOCCR_G3_IO2_Msk (0x1UL << TSC_IOCCR_G3_IO2_Pos)

0x00000200

◆ TSC_IOCCR_G3_IO2_Pos

#define TSC_IOCCR_G3_IO2_Pos (9U)

◆ TSC_IOCCR_G3_IO3

#define TSC_IOCCR_G3_IO3 TSC_IOCCR_G3_IO3_Msk

GROUP3_IO3 channel mode

◆ TSC_IOCCR_G3_IO3_Msk

#define TSC_IOCCR_G3_IO3_Msk (0x1UL << TSC_IOCCR_G3_IO3_Pos)

0x00000400

◆ TSC_IOCCR_G3_IO3_Pos

#define TSC_IOCCR_G3_IO3_Pos (10U)

◆ TSC_IOCCR_G3_IO4

#define TSC_IOCCR_G3_IO4 TSC_IOCCR_G3_IO4_Msk

GROUP3_IO4 channel mode

◆ TSC_IOCCR_G3_IO4_Msk

#define TSC_IOCCR_G3_IO4_Msk (0x1UL << TSC_IOCCR_G3_IO4_Pos)

0x00000800

◆ TSC_IOCCR_G3_IO4_Pos

#define TSC_IOCCR_G3_IO4_Pos (11U)

◆ TSC_IOCCR_G4_IO1

#define TSC_IOCCR_G4_IO1 TSC_IOCCR_G4_IO1_Msk

GROUP4_IO1 channel mode

◆ TSC_IOCCR_G4_IO1_Msk

#define TSC_IOCCR_G4_IO1_Msk (0x1UL << TSC_IOCCR_G4_IO1_Pos)

0x00001000

◆ TSC_IOCCR_G4_IO1_Pos

#define TSC_IOCCR_G4_IO1_Pos (12U)

◆ TSC_IOCCR_G4_IO2

#define TSC_IOCCR_G4_IO2 TSC_IOCCR_G4_IO2_Msk

GROUP4_IO2 channel mode

◆ TSC_IOCCR_G4_IO2_Msk

#define TSC_IOCCR_G4_IO2_Msk (0x1UL << TSC_IOCCR_G4_IO2_Pos)

0x00002000

◆ TSC_IOCCR_G4_IO2_Pos

#define TSC_IOCCR_G4_IO2_Pos (13U)

◆ TSC_IOCCR_G4_IO3

#define TSC_IOCCR_G4_IO3 TSC_IOCCR_G4_IO3_Msk

GROUP4_IO3 channel mode

◆ TSC_IOCCR_G4_IO3_Msk

#define TSC_IOCCR_G4_IO3_Msk (0x1UL << TSC_IOCCR_G4_IO3_Pos)

0x00004000

◆ TSC_IOCCR_G4_IO3_Pos

#define TSC_IOCCR_G4_IO3_Pos (14U)

◆ TSC_IOCCR_G4_IO4

#define TSC_IOCCR_G4_IO4 TSC_IOCCR_G4_IO4_Msk

GROUP4_IO4 channel mode

◆ TSC_IOCCR_G4_IO4_Msk

#define TSC_IOCCR_G4_IO4_Msk (0x1UL << TSC_IOCCR_G4_IO4_Pos)

0x00008000

◆ TSC_IOCCR_G4_IO4_Pos

#define TSC_IOCCR_G4_IO4_Pos (15U)

◆ TSC_IOCCR_G5_IO1

#define TSC_IOCCR_G5_IO1 TSC_IOCCR_G5_IO1_Msk

GROUP5_IO1 channel mode

◆ TSC_IOCCR_G5_IO1_Msk

#define TSC_IOCCR_G5_IO1_Msk (0x1UL << TSC_IOCCR_G5_IO1_Pos)

0x00010000

◆ TSC_IOCCR_G5_IO1_Pos

#define TSC_IOCCR_G5_IO1_Pos (16U)

◆ TSC_IOCCR_G5_IO2

#define TSC_IOCCR_G5_IO2 TSC_IOCCR_G5_IO2_Msk

GROUP5_IO2 channel mode

◆ TSC_IOCCR_G5_IO2_Msk

#define TSC_IOCCR_G5_IO2_Msk (0x1UL << TSC_IOCCR_G5_IO2_Pos)

0x00020000

◆ TSC_IOCCR_G5_IO2_Pos

#define TSC_IOCCR_G5_IO2_Pos (17U)

◆ TSC_IOCCR_G5_IO3

#define TSC_IOCCR_G5_IO3 TSC_IOCCR_G5_IO3_Msk

GROUP5_IO3 channel mode

◆ TSC_IOCCR_G5_IO3_Msk

#define TSC_IOCCR_G5_IO3_Msk (0x1UL << TSC_IOCCR_G5_IO3_Pos)

0x00040000

◆ TSC_IOCCR_G5_IO3_Pos

#define TSC_IOCCR_G5_IO3_Pos (18U)

◆ TSC_IOCCR_G5_IO4

#define TSC_IOCCR_G5_IO4 TSC_IOCCR_G5_IO4_Msk

GROUP5_IO4 channel mode

◆ TSC_IOCCR_G5_IO4_Msk

#define TSC_IOCCR_G5_IO4_Msk (0x1UL << TSC_IOCCR_G5_IO4_Pos)

0x00080000

◆ TSC_IOCCR_G5_IO4_Pos

#define TSC_IOCCR_G5_IO4_Pos (19U)

◆ TSC_IOCCR_G6_IO1

#define TSC_IOCCR_G6_IO1 TSC_IOCCR_G6_IO1_Msk

GROUP6_IO1 channel mode

◆ TSC_IOCCR_G6_IO1_Msk

#define TSC_IOCCR_G6_IO1_Msk (0x1UL << TSC_IOCCR_G6_IO1_Pos)

0x00100000

◆ TSC_IOCCR_G6_IO1_Pos

#define TSC_IOCCR_G6_IO1_Pos (20U)

◆ TSC_IOCCR_G6_IO2

#define TSC_IOCCR_G6_IO2 TSC_IOCCR_G6_IO2_Msk

GROUP6_IO2 channel mode

◆ TSC_IOCCR_G6_IO2_Msk

#define TSC_IOCCR_G6_IO2_Msk (0x1UL << TSC_IOCCR_G6_IO2_Pos)

0x00200000

◆ TSC_IOCCR_G6_IO2_Pos

#define TSC_IOCCR_G6_IO2_Pos (21U)

◆ TSC_IOCCR_G6_IO3

#define TSC_IOCCR_G6_IO3 TSC_IOCCR_G6_IO3_Msk

GROUP6_IO3 channel mode

◆ TSC_IOCCR_G6_IO3_Msk

#define TSC_IOCCR_G6_IO3_Msk (0x1UL << TSC_IOCCR_G6_IO3_Pos)

0x00400000

◆ TSC_IOCCR_G6_IO3_Pos

#define TSC_IOCCR_G6_IO3_Pos (22U)

◆ TSC_IOCCR_G6_IO4

#define TSC_IOCCR_G6_IO4 TSC_IOCCR_G6_IO4_Msk

GROUP6_IO4 channel mode

◆ TSC_IOCCR_G6_IO4_Msk

#define TSC_IOCCR_G6_IO4_Msk (0x1UL << TSC_IOCCR_G6_IO4_Pos)

0x00800000

◆ TSC_IOCCR_G6_IO4_Pos

#define TSC_IOCCR_G6_IO4_Pos (23U)

◆ TSC_IOCCR_G7_IO1

#define TSC_IOCCR_G7_IO1 TSC_IOCCR_G7_IO1_Msk

GROUP7_IO1 channel mode

◆ TSC_IOCCR_G7_IO1_Msk

#define TSC_IOCCR_G7_IO1_Msk (0x1UL << TSC_IOCCR_G7_IO1_Pos)

0x01000000

◆ TSC_IOCCR_G7_IO1_Pos

#define TSC_IOCCR_G7_IO1_Pos (24U)

◆ TSC_IOCCR_G7_IO2

#define TSC_IOCCR_G7_IO2 TSC_IOCCR_G7_IO2_Msk

GROUP7_IO2 channel mode

◆ TSC_IOCCR_G7_IO2_Msk

#define TSC_IOCCR_G7_IO2_Msk (0x1UL << TSC_IOCCR_G7_IO2_Pos)

0x02000000

◆ TSC_IOCCR_G7_IO2_Pos

#define TSC_IOCCR_G7_IO2_Pos (25U)

◆ TSC_IOCCR_G7_IO3

#define TSC_IOCCR_G7_IO3 TSC_IOCCR_G7_IO3_Msk

GROUP7_IO3 channel mode

◆ TSC_IOCCR_G7_IO3_Msk

#define TSC_IOCCR_G7_IO3_Msk (0x1UL << TSC_IOCCR_G7_IO3_Pos)

0x04000000

◆ TSC_IOCCR_G7_IO3_Pos

#define TSC_IOCCR_G7_IO3_Pos (26U)

◆ TSC_IOCCR_G7_IO4

#define TSC_IOCCR_G7_IO4 TSC_IOCCR_G7_IO4_Msk

GROUP7_IO4 channel mode

◆ TSC_IOCCR_G7_IO4_Msk

#define TSC_IOCCR_G7_IO4_Msk (0x1UL << TSC_IOCCR_G7_IO4_Pos)

0x08000000

◆ TSC_IOCCR_G7_IO4_Pos

#define TSC_IOCCR_G7_IO4_Pos (27U)

◆ TSC_IOCCR_G8_IO1

#define TSC_IOCCR_G8_IO1 TSC_IOCCR_G8_IO1_Msk

GROUP8_IO1 channel mode

◆ TSC_IOCCR_G8_IO1_Msk

#define TSC_IOCCR_G8_IO1_Msk (0x1UL << TSC_IOCCR_G8_IO1_Pos)

0x10000000

◆ TSC_IOCCR_G8_IO1_Pos

#define TSC_IOCCR_G8_IO1_Pos (28U)

◆ TSC_IOCCR_G8_IO2

#define TSC_IOCCR_G8_IO2 TSC_IOCCR_G8_IO2_Msk

GROUP8_IO2 channel mode

◆ TSC_IOCCR_G8_IO2_Msk

#define TSC_IOCCR_G8_IO2_Msk (0x1UL << TSC_IOCCR_G8_IO2_Pos)

0x20000000

◆ TSC_IOCCR_G8_IO2_Pos

#define TSC_IOCCR_G8_IO2_Pos (29U)

◆ TSC_IOCCR_G8_IO3

#define TSC_IOCCR_G8_IO3 TSC_IOCCR_G8_IO3_Msk

GROUP8_IO3 channel mode

◆ TSC_IOCCR_G8_IO3_Msk

#define TSC_IOCCR_G8_IO3_Msk (0x1UL << TSC_IOCCR_G8_IO3_Pos)

0x40000000

◆ TSC_IOCCR_G8_IO3_Pos

#define TSC_IOCCR_G8_IO3_Pos (30U)

◆ TSC_IOCCR_G8_IO4

#define TSC_IOCCR_G8_IO4 TSC_IOCCR_G8_IO4_Msk

GROUP8_IO4 channel mode

◆ TSC_IOCCR_G8_IO4_Msk

#define TSC_IOCCR_G8_IO4_Msk (0x1UL << TSC_IOCCR_G8_IO4_Pos)

0x80000000

◆ TSC_IOCCR_G8_IO4_Pos

#define TSC_IOCCR_G8_IO4_Pos (31U)

◆ TSC_IOGCSR_G1E

#define TSC_IOGCSR_G1E TSC_IOGCSR_G1E_Msk

Analog IO GROUP1 enable

◆ TSC_IOGCSR_G1E_Msk

#define TSC_IOGCSR_G1E_Msk (0x1UL << TSC_IOGCSR_G1E_Pos)

0x00000001

◆ TSC_IOGCSR_G1E_Pos

#define TSC_IOGCSR_G1E_Pos (0U)

◆ TSC_IOGCSR_G1S

#define TSC_IOGCSR_G1S TSC_IOGCSR_G1S_Msk

Analog IO GROUP1 status

◆ TSC_IOGCSR_G1S_Msk

#define TSC_IOGCSR_G1S_Msk (0x1UL << TSC_IOGCSR_G1S_Pos)

0x00010000

◆ TSC_IOGCSR_G1S_Pos

#define TSC_IOGCSR_G1S_Pos (16U)

◆ TSC_IOGCSR_G2E

#define TSC_IOGCSR_G2E TSC_IOGCSR_G2E_Msk

Analog IO GROUP2 enable

◆ TSC_IOGCSR_G2E_Msk

#define TSC_IOGCSR_G2E_Msk (0x1UL << TSC_IOGCSR_G2E_Pos)

0x00000002

◆ TSC_IOGCSR_G2E_Pos

#define TSC_IOGCSR_G2E_Pos (1U)

◆ TSC_IOGCSR_G2S

#define TSC_IOGCSR_G2S TSC_IOGCSR_G2S_Msk

Analog IO GROUP2 status

◆ TSC_IOGCSR_G2S_Msk

#define TSC_IOGCSR_G2S_Msk (0x1UL << TSC_IOGCSR_G2S_Pos)

0x00020000

◆ TSC_IOGCSR_G2S_Pos

#define TSC_IOGCSR_G2S_Pos (17U)

◆ TSC_IOGCSR_G3E

#define TSC_IOGCSR_G3E TSC_IOGCSR_G3E_Msk

Analog IO GROUP3 enable

◆ TSC_IOGCSR_G3E_Msk

#define TSC_IOGCSR_G3E_Msk (0x1UL << TSC_IOGCSR_G3E_Pos)

0x00000004

◆ TSC_IOGCSR_G3E_Pos

#define TSC_IOGCSR_G3E_Pos (2U)

◆ TSC_IOGCSR_G3S

#define TSC_IOGCSR_G3S TSC_IOGCSR_G3S_Msk

Analog IO GROUP3 status

◆ TSC_IOGCSR_G3S_Msk

#define TSC_IOGCSR_G3S_Msk (0x1UL << TSC_IOGCSR_G3S_Pos)

0x00040000

◆ TSC_IOGCSR_G3S_Pos

#define TSC_IOGCSR_G3S_Pos (18U)

◆ TSC_IOGCSR_G4E

#define TSC_IOGCSR_G4E TSC_IOGCSR_G4E_Msk

Analog IO GROUP4 enable

◆ TSC_IOGCSR_G4E_Msk

#define TSC_IOGCSR_G4E_Msk (0x1UL << TSC_IOGCSR_G4E_Pos)

0x00000008

◆ TSC_IOGCSR_G4E_Pos

#define TSC_IOGCSR_G4E_Pos (3U)

◆ TSC_IOGCSR_G4S

#define TSC_IOGCSR_G4S TSC_IOGCSR_G4S_Msk

Analog IO GROUP4 status

◆ TSC_IOGCSR_G4S_Msk

#define TSC_IOGCSR_G4S_Msk (0x1UL << TSC_IOGCSR_G4S_Pos)

0x00080000

◆ TSC_IOGCSR_G4S_Pos

#define TSC_IOGCSR_G4S_Pos (19U)

◆ TSC_IOGCSR_G5E

#define TSC_IOGCSR_G5E TSC_IOGCSR_G5E_Msk

Analog IO GROUP5 enable

◆ TSC_IOGCSR_G5E_Msk

#define TSC_IOGCSR_G5E_Msk (0x1UL << TSC_IOGCSR_G5E_Pos)

0x00000010

◆ TSC_IOGCSR_G5E_Pos

#define TSC_IOGCSR_G5E_Pos (4U)

◆ TSC_IOGCSR_G5S

#define TSC_IOGCSR_G5S TSC_IOGCSR_G5S_Msk

Analog IO GROUP5 status

◆ TSC_IOGCSR_G5S_Msk

#define TSC_IOGCSR_G5S_Msk (0x1UL << TSC_IOGCSR_G5S_Pos)

0x00100000

◆ TSC_IOGCSR_G5S_Pos

#define TSC_IOGCSR_G5S_Pos (20U)

◆ TSC_IOGCSR_G6E

#define TSC_IOGCSR_G6E TSC_IOGCSR_G6E_Msk

Analog IO GROUP6 enable

◆ TSC_IOGCSR_G6E_Msk

#define TSC_IOGCSR_G6E_Msk (0x1UL << TSC_IOGCSR_G6E_Pos)

0x00000020

◆ TSC_IOGCSR_G6E_Pos

#define TSC_IOGCSR_G6E_Pos (5U)

◆ TSC_IOGCSR_G6S

#define TSC_IOGCSR_G6S TSC_IOGCSR_G6S_Msk

Analog IO GROUP6 status

◆ TSC_IOGCSR_G6S_Msk

#define TSC_IOGCSR_G6S_Msk (0x1UL << TSC_IOGCSR_G6S_Pos)

0x00200000

◆ TSC_IOGCSR_G6S_Pos

#define TSC_IOGCSR_G6S_Pos (21U)

◆ TSC_IOGCSR_G7E

#define TSC_IOGCSR_G7E TSC_IOGCSR_G7E_Msk

Analog IO GROUP7 enable

◆ TSC_IOGCSR_G7E_Msk

#define TSC_IOGCSR_G7E_Msk (0x1UL << TSC_IOGCSR_G7E_Pos)

0x00000040

◆ TSC_IOGCSR_G7E_Pos

#define TSC_IOGCSR_G7E_Pos (6U)

◆ TSC_IOGCSR_G7S

#define TSC_IOGCSR_G7S TSC_IOGCSR_G7S_Msk

Analog IO GROUP7 status

◆ TSC_IOGCSR_G7S_Msk

#define TSC_IOGCSR_G7S_Msk (0x1UL << TSC_IOGCSR_G7S_Pos)

0x00400000

◆ TSC_IOGCSR_G7S_Pos

#define TSC_IOGCSR_G7S_Pos (22U)

◆ TSC_IOGCSR_G8E

#define TSC_IOGCSR_G8E TSC_IOGCSR_G8E_Msk

Analog IO GROUP8 enable

◆ TSC_IOGCSR_G8E_Msk

#define TSC_IOGCSR_G8E_Msk (0x1UL << TSC_IOGCSR_G8E_Pos)

0x00000080

◆ TSC_IOGCSR_G8E_Pos

#define TSC_IOGCSR_G8E_Pos (7U)

◆ TSC_IOGCSR_G8S

#define TSC_IOGCSR_G8S TSC_IOGCSR_G8S_Msk

Analog IO GROUP8 status

◆ TSC_IOGCSR_G8S_Msk

#define TSC_IOGCSR_G8S_Msk (0x1UL << TSC_IOGCSR_G8S_Pos)

0x00800000

◆ TSC_IOGCSR_G8S_Pos

#define TSC_IOGCSR_G8S_Pos (23U)

◆ TSC_IOGXCR_CNT

#define TSC_IOGXCR_CNT TSC_IOGXCR_CNT_Msk

CNT[13:0] bits (Counter value)

◆ TSC_IOGXCR_CNT_Msk

#define TSC_IOGXCR_CNT_Msk (0x3FFFUL << TSC_IOGXCR_CNT_Pos)

0x00003FFF

◆ TSC_IOGXCR_CNT_Pos

#define TSC_IOGXCR_CNT_Pos (0U)

◆ TSC_IOHCR_G1_IO1

#define TSC_IOHCR_G1_IO1 TSC_IOHCR_G1_IO1_Msk

GROUP1_IO1 schmitt trigger hysteresis mode

◆ TSC_IOHCR_G1_IO1_Msk

#define TSC_IOHCR_G1_IO1_Msk (0x1UL << TSC_IOHCR_G1_IO1_Pos)

0x00000001

◆ TSC_IOHCR_G1_IO1_Pos

#define TSC_IOHCR_G1_IO1_Pos (0U)

◆ TSC_IOHCR_G1_IO2

#define TSC_IOHCR_G1_IO2 TSC_IOHCR_G1_IO2_Msk

GROUP1_IO2 schmitt trigger hysteresis mode

◆ TSC_IOHCR_G1_IO2_Msk

#define TSC_IOHCR_G1_IO2_Msk (0x1UL << TSC_IOHCR_G1_IO2_Pos)

0x00000002

◆ TSC_IOHCR_G1_IO2_Pos

#define TSC_IOHCR_G1_IO2_Pos (1U)

◆ TSC_IOHCR_G1_IO3

#define TSC_IOHCR_G1_IO3 TSC_IOHCR_G1_IO3_Msk

GROUP1_IO3 schmitt trigger hysteresis mode

◆ TSC_IOHCR_G1_IO3_Msk

#define TSC_IOHCR_G1_IO3_Msk (0x1UL << TSC_IOHCR_G1_IO3_Pos)

0x00000004

◆ TSC_IOHCR_G1_IO3_Pos

#define TSC_IOHCR_G1_IO3_Pos (2U)

◆ TSC_IOHCR_G1_IO4

#define TSC_IOHCR_G1_IO4 TSC_IOHCR_G1_IO4_Msk

GROUP1_IO4 schmitt trigger hysteresis mode

◆ TSC_IOHCR_G1_IO4_Msk

#define TSC_IOHCR_G1_IO4_Msk (0x1UL << TSC_IOHCR_G1_IO4_Pos)

0x00000008

◆ TSC_IOHCR_G1_IO4_Pos

#define TSC_IOHCR_G1_IO4_Pos (3U)

◆ TSC_IOHCR_G2_IO1

#define TSC_IOHCR_G2_IO1 TSC_IOHCR_G2_IO1_Msk

GROUP2_IO1 schmitt trigger hysteresis mode

◆ TSC_IOHCR_G2_IO1_Msk

#define TSC_IOHCR_G2_IO1_Msk (0x1UL << TSC_IOHCR_G2_IO1_Pos)

0x00000010

◆ TSC_IOHCR_G2_IO1_Pos

#define TSC_IOHCR_G2_IO1_Pos (4U)

◆ TSC_IOHCR_G2_IO2

#define TSC_IOHCR_G2_IO2 TSC_IOHCR_G2_IO2_Msk

GROUP2_IO2 schmitt trigger hysteresis mode

◆ TSC_IOHCR_G2_IO2_Msk

#define TSC_IOHCR_G2_IO2_Msk (0x1UL << TSC_IOHCR_G2_IO2_Pos)

0x00000020

◆ TSC_IOHCR_G2_IO2_Pos

#define TSC_IOHCR_G2_IO2_Pos (5U)

◆ TSC_IOHCR_G2_IO3

#define TSC_IOHCR_G2_IO3 TSC_IOHCR_G2_IO3_Msk

GROUP2_IO3 schmitt trigger hysteresis mode

◆ TSC_IOHCR_G2_IO3_Msk

#define TSC_IOHCR_G2_IO3_Msk (0x1UL << TSC_IOHCR_G2_IO3_Pos)

0x00000040

◆ TSC_IOHCR_G2_IO3_Pos

#define TSC_IOHCR_G2_IO3_Pos (6U)

◆ TSC_IOHCR_G2_IO4

#define TSC_IOHCR_G2_IO4 TSC_IOHCR_G2_IO4_Msk

GROUP2_IO4 schmitt trigger hysteresis mode

◆ TSC_IOHCR_G2_IO4_Msk

#define TSC_IOHCR_G2_IO4_Msk (0x1UL << TSC_IOHCR_G2_IO4_Pos)

0x00000080

◆ TSC_IOHCR_G2_IO4_Pos

#define TSC_IOHCR_G2_IO4_Pos (7U)

◆ TSC_IOHCR_G3_IO1

#define TSC_IOHCR_G3_IO1 TSC_IOHCR_G3_IO1_Msk

GROUP3_IO1 schmitt trigger hysteresis mode

◆ TSC_IOHCR_G3_IO1_Msk

#define TSC_IOHCR_G3_IO1_Msk (0x1UL << TSC_IOHCR_G3_IO1_Pos)

0x00000100

◆ TSC_IOHCR_G3_IO1_Pos

#define TSC_IOHCR_G3_IO1_Pos (8U)

◆ TSC_IOHCR_G3_IO2

#define TSC_IOHCR_G3_IO2 TSC_IOHCR_G3_IO2_Msk

GROUP3_IO2 schmitt trigger hysteresis mode

◆ TSC_IOHCR_G3_IO2_Msk

#define TSC_IOHCR_G3_IO2_Msk (0x1UL << TSC_IOHCR_G3_IO2_Pos)

0x00000200

◆ TSC_IOHCR_G3_IO2_Pos

#define TSC_IOHCR_G3_IO2_Pos (9U)

◆ TSC_IOHCR_G3_IO3

#define TSC_IOHCR_G3_IO3 TSC_IOHCR_G3_IO3_Msk

GROUP3_IO3 schmitt trigger hysteresis mode

◆ TSC_IOHCR_G3_IO3_Msk

#define TSC_IOHCR_G3_IO3_Msk (0x1UL << TSC_IOHCR_G3_IO3_Pos)

0x00000400

◆ TSC_IOHCR_G3_IO3_Pos

#define TSC_IOHCR_G3_IO3_Pos (10U)

◆ TSC_IOHCR_G3_IO4

#define TSC_IOHCR_G3_IO4 TSC_IOHCR_G3_IO4_Msk

GROUP3_IO4 schmitt trigger hysteresis mode

◆ TSC_IOHCR_G3_IO4_Msk

#define TSC_IOHCR_G3_IO4_Msk (0x1UL << TSC_IOHCR_G3_IO4_Pos)

0x00000800

◆ TSC_IOHCR_G3_IO4_Pos

#define TSC_IOHCR_G3_IO4_Pos (11U)

◆ TSC_IOHCR_G4_IO1

#define TSC_IOHCR_G4_IO1 TSC_IOHCR_G4_IO1_Msk

GROUP4_IO1 schmitt trigger hysteresis mode

◆ TSC_IOHCR_G4_IO1_Msk

#define TSC_IOHCR_G4_IO1_Msk (0x1UL << TSC_IOHCR_G4_IO1_Pos)

0x00001000

◆ TSC_IOHCR_G4_IO1_Pos

#define TSC_IOHCR_G4_IO1_Pos (12U)

◆ TSC_IOHCR_G4_IO2

#define TSC_IOHCR_G4_IO2 TSC_IOHCR_G4_IO2_Msk

GROUP4_IO2 schmitt trigger hysteresis mode

◆ TSC_IOHCR_G4_IO2_Msk

#define TSC_IOHCR_G4_IO2_Msk (0x1UL << TSC_IOHCR_G4_IO2_Pos)

0x00002000

◆ TSC_IOHCR_G4_IO2_Pos

#define TSC_IOHCR_G4_IO2_Pos (13U)

◆ TSC_IOHCR_G4_IO3

#define TSC_IOHCR_G4_IO3 TSC_IOHCR_G4_IO3_Msk

GROUP4_IO3 schmitt trigger hysteresis mode

◆ TSC_IOHCR_G4_IO3_Msk

#define TSC_IOHCR_G4_IO3_Msk (0x1UL << TSC_IOHCR_G4_IO3_Pos)

0x00004000

◆ TSC_IOHCR_G4_IO3_Pos

#define TSC_IOHCR_G4_IO3_Pos (14U)

◆ TSC_IOHCR_G4_IO4

#define TSC_IOHCR_G4_IO4 TSC_IOHCR_G4_IO4_Msk

GROUP4_IO4 schmitt trigger hysteresis mode

◆ TSC_IOHCR_G4_IO4_Msk

#define TSC_IOHCR_G4_IO4_Msk (0x1UL << TSC_IOHCR_G4_IO4_Pos)

0x00008000

◆ TSC_IOHCR_G4_IO4_Pos

#define TSC_IOHCR_G4_IO4_Pos (15U)

◆ TSC_IOHCR_G5_IO1

#define TSC_IOHCR_G5_IO1 TSC_IOHCR_G5_IO1_Msk

GROUP5_IO1 schmitt trigger hysteresis mode

◆ TSC_IOHCR_G5_IO1_Msk

#define TSC_IOHCR_G5_IO1_Msk (0x1UL << TSC_IOHCR_G5_IO1_Pos)

0x00010000

◆ TSC_IOHCR_G5_IO1_Pos

#define TSC_IOHCR_G5_IO1_Pos (16U)

◆ TSC_IOHCR_G5_IO2

#define TSC_IOHCR_G5_IO2 TSC_IOHCR_G5_IO2_Msk

GROUP5_IO2 schmitt trigger hysteresis mode

◆ TSC_IOHCR_G5_IO2_Msk

#define TSC_IOHCR_G5_IO2_Msk (0x1UL << TSC_IOHCR_G5_IO2_Pos)

0x00020000

◆ TSC_IOHCR_G5_IO2_Pos

#define TSC_IOHCR_G5_IO2_Pos (17U)

◆ TSC_IOHCR_G5_IO3

#define TSC_IOHCR_G5_IO3 TSC_IOHCR_G5_IO3_Msk

GROUP5_IO3 schmitt trigger hysteresis mode

◆ TSC_IOHCR_G5_IO3_Msk

#define TSC_IOHCR_G5_IO3_Msk (0x1UL << TSC_IOHCR_G5_IO3_Pos)

0x00040000

◆ TSC_IOHCR_G5_IO3_Pos

#define TSC_IOHCR_G5_IO3_Pos (18U)

◆ TSC_IOHCR_G5_IO4

#define TSC_IOHCR_G5_IO4 TSC_IOHCR_G5_IO4_Msk

GROUP5_IO4 schmitt trigger hysteresis mode

◆ TSC_IOHCR_G5_IO4_Msk

#define TSC_IOHCR_G5_IO4_Msk (0x1UL << TSC_IOHCR_G5_IO4_Pos)

0x00080000

◆ TSC_IOHCR_G5_IO4_Pos

#define TSC_IOHCR_G5_IO4_Pos (19U)

◆ TSC_IOHCR_G6_IO1

#define TSC_IOHCR_G6_IO1 TSC_IOHCR_G6_IO1_Msk

GROUP6_IO1 schmitt trigger hysteresis mode

◆ TSC_IOHCR_G6_IO1_Msk

#define TSC_IOHCR_G6_IO1_Msk (0x1UL << TSC_IOHCR_G6_IO1_Pos)

0x00100000

◆ TSC_IOHCR_G6_IO1_Pos

#define TSC_IOHCR_G6_IO1_Pos (20U)

◆ TSC_IOHCR_G6_IO2

#define TSC_IOHCR_G6_IO2 TSC_IOHCR_G6_IO2_Msk

GROUP6_IO2 schmitt trigger hysteresis mode

◆ TSC_IOHCR_G6_IO2_Msk

#define TSC_IOHCR_G6_IO2_Msk (0x1UL << TSC_IOHCR_G6_IO2_Pos)

0x00200000

◆ TSC_IOHCR_G6_IO2_Pos

#define TSC_IOHCR_G6_IO2_Pos (21U)

◆ TSC_IOHCR_G6_IO3

#define TSC_IOHCR_G6_IO3 TSC_IOHCR_G6_IO3_Msk

GROUP6_IO3 schmitt trigger hysteresis mode

◆ TSC_IOHCR_G6_IO3_Msk

#define TSC_IOHCR_G6_IO3_Msk (0x1UL << TSC_IOHCR_G6_IO3_Pos)

0x00400000

◆ TSC_IOHCR_G6_IO3_Pos

#define TSC_IOHCR_G6_IO3_Pos (22U)

◆ TSC_IOHCR_G6_IO4

#define TSC_IOHCR_G6_IO4 TSC_IOHCR_G6_IO4_Msk

GROUP6_IO4 schmitt trigger hysteresis mode

◆ TSC_IOHCR_G6_IO4_Msk

#define TSC_IOHCR_G6_IO4_Msk (0x1UL << TSC_IOHCR_G6_IO4_Pos)

0x00800000

◆ TSC_IOHCR_G6_IO4_Pos

#define TSC_IOHCR_G6_IO4_Pos (23U)

◆ TSC_IOHCR_G7_IO1

#define TSC_IOHCR_G7_IO1 TSC_IOHCR_G7_IO1_Msk

GROUP7_IO1 schmitt trigger hysteresis mode

◆ TSC_IOHCR_G7_IO1_Msk

#define TSC_IOHCR_G7_IO1_Msk (0x1UL << TSC_IOHCR_G7_IO1_Pos)

0x01000000

◆ TSC_IOHCR_G7_IO1_Pos

#define TSC_IOHCR_G7_IO1_Pos (24U)

◆ TSC_IOHCR_G7_IO2

#define TSC_IOHCR_G7_IO2 TSC_IOHCR_G7_IO2_Msk

GROUP7_IO2 schmitt trigger hysteresis mode

◆ TSC_IOHCR_G7_IO2_Msk

#define TSC_IOHCR_G7_IO2_Msk (0x1UL << TSC_IOHCR_G7_IO2_Pos)

0x02000000

◆ TSC_IOHCR_G7_IO2_Pos

#define TSC_IOHCR_G7_IO2_Pos (25U)

◆ TSC_IOHCR_G7_IO3

#define TSC_IOHCR_G7_IO3 TSC_IOHCR_G7_IO3_Msk

GROUP7_IO3 schmitt trigger hysteresis mode

◆ TSC_IOHCR_G7_IO3_Msk

#define TSC_IOHCR_G7_IO3_Msk (0x1UL << TSC_IOHCR_G7_IO3_Pos)

0x04000000

◆ TSC_IOHCR_G7_IO3_Pos

#define TSC_IOHCR_G7_IO3_Pos (26U)

◆ TSC_IOHCR_G7_IO4

#define TSC_IOHCR_G7_IO4 TSC_IOHCR_G7_IO4_Msk

GROUP7_IO4 schmitt trigger hysteresis mode

◆ TSC_IOHCR_G7_IO4_Msk

#define TSC_IOHCR_G7_IO4_Msk (0x1UL << TSC_IOHCR_G7_IO4_Pos)

0x08000000

◆ TSC_IOHCR_G7_IO4_Pos

#define TSC_IOHCR_G7_IO4_Pos (27U)

◆ TSC_IOHCR_G8_IO1

#define TSC_IOHCR_G8_IO1 TSC_IOHCR_G8_IO1_Msk

GROUP8_IO1 schmitt trigger hysteresis mode

◆ TSC_IOHCR_G8_IO1_Msk

#define TSC_IOHCR_G8_IO1_Msk (0x1UL << TSC_IOHCR_G8_IO1_Pos)

0x10000000

◆ TSC_IOHCR_G8_IO1_Pos

#define TSC_IOHCR_G8_IO1_Pos (28U)

◆ TSC_IOHCR_G8_IO2

#define TSC_IOHCR_G8_IO2 TSC_IOHCR_G8_IO2_Msk

GROUP8_IO2 schmitt trigger hysteresis mode

◆ TSC_IOHCR_G8_IO2_Msk

#define TSC_IOHCR_G8_IO2_Msk (0x1UL << TSC_IOHCR_G8_IO2_Pos)

0x20000000

◆ TSC_IOHCR_G8_IO2_Pos

#define TSC_IOHCR_G8_IO2_Pos (29U)

◆ TSC_IOHCR_G8_IO3

#define TSC_IOHCR_G8_IO3 TSC_IOHCR_G8_IO3_Msk

GROUP8_IO3 schmitt trigger hysteresis mode

◆ TSC_IOHCR_G8_IO3_Msk

#define TSC_IOHCR_G8_IO3_Msk (0x1UL << TSC_IOHCR_G8_IO3_Pos)

0x40000000

◆ TSC_IOHCR_G8_IO3_Pos

#define TSC_IOHCR_G8_IO3_Pos (30U)

◆ TSC_IOHCR_G8_IO4

#define TSC_IOHCR_G8_IO4 TSC_IOHCR_G8_IO4_Msk

GROUP8_IO4 schmitt trigger hysteresis mode

◆ TSC_IOHCR_G8_IO4_Msk

#define TSC_IOHCR_G8_IO4_Msk (0x1UL << TSC_IOHCR_G8_IO4_Pos)

0x80000000

◆ TSC_IOHCR_G8_IO4_Pos

#define TSC_IOHCR_G8_IO4_Pos (31U)

◆ TSC_IOSCR_G1_IO1

#define TSC_IOSCR_G1_IO1 TSC_IOSCR_G1_IO1_Msk

GROUP1_IO1 sampling mode

◆ TSC_IOSCR_G1_IO1_Msk

#define TSC_IOSCR_G1_IO1_Msk (0x1UL << TSC_IOSCR_G1_IO1_Pos)

0x00000001

◆ TSC_IOSCR_G1_IO1_Pos

#define TSC_IOSCR_G1_IO1_Pos (0U)

◆ TSC_IOSCR_G1_IO2

#define TSC_IOSCR_G1_IO2 TSC_IOSCR_G1_IO2_Msk

GROUP1_IO2 sampling mode

◆ TSC_IOSCR_G1_IO2_Msk

#define TSC_IOSCR_G1_IO2_Msk (0x1UL << TSC_IOSCR_G1_IO2_Pos)

0x00000002

◆ TSC_IOSCR_G1_IO2_Pos

#define TSC_IOSCR_G1_IO2_Pos (1U)

◆ TSC_IOSCR_G1_IO3

#define TSC_IOSCR_G1_IO3 TSC_IOSCR_G1_IO3_Msk

GROUP1_IO3 sampling mode

◆ TSC_IOSCR_G1_IO3_Msk

#define TSC_IOSCR_G1_IO3_Msk (0x1UL << TSC_IOSCR_G1_IO3_Pos)

0x00000004

◆ TSC_IOSCR_G1_IO3_Pos

#define TSC_IOSCR_G1_IO3_Pos (2U)

◆ TSC_IOSCR_G1_IO4

#define TSC_IOSCR_G1_IO4 TSC_IOSCR_G1_IO4_Msk

GROUP1_IO4 sampling mode

◆ TSC_IOSCR_G1_IO4_Msk

#define TSC_IOSCR_G1_IO4_Msk (0x1UL << TSC_IOSCR_G1_IO4_Pos)

0x00000008

◆ TSC_IOSCR_G1_IO4_Pos

#define TSC_IOSCR_G1_IO4_Pos (3U)

◆ TSC_IOSCR_G2_IO1

#define TSC_IOSCR_G2_IO1 TSC_IOSCR_G2_IO1_Msk

GROUP2_IO1 sampling mode

◆ TSC_IOSCR_G2_IO1_Msk

#define TSC_IOSCR_G2_IO1_Msk (0x1UL << TSC_IOSCR_G2_IO1_Pos)

0x00000010

◆ TSC_IOSCR_G2_IO1_Pos

#define TSC_IOSCR_G2_IO1_Pos (4U)

◆ TSC_IOSCR_G2_IO2

#define TSC_IOSCR_G2_IO2 TSC_IOSCR_G2_IO2_Msk

GROUP2_IO2 sampling mode

◆ TSC_IOSCR_G2_IO2_Msk

#define TSC_IOSCR_G2_IO2_Msk (0x1UL << TSC_IOSCR_G2_IO2_Pos)

0x00000020

◆ TSC_IOSCR_G2_IO2_Pos

#define TSC_IOSCR_G2_IO2_Pos (5U)

◆ TSC_IOSCR_G2_IO3

#define TSC_IOSCR_G2_IO3 TSC_IOSCR_G2_IO3_Msk

GROUP2_IO3 sampling mode

◆ TSC_IOSCR_G2_IO3_Msk

#define TSC_IOSCR_G2_IO3_Msk (0x1UL << TSC_IOSCR_G2_IO3_Pos)

0x00000040

◆ TSC_IOSCR_G2_IO3_Pos

#define TSC_IOSCR_G2_IO3_Pos (6U)

◆ TSC_IOSCR_G2_IO4

#define TSC_IOSCR_G2_IO4 TSC_IOSCR_G2_IO4_Msk

GROUP2_IO4 sampling mode

◆ TSC_IOSCR_G2_IO4_Msk

#define TSC_IOSCR_G2_IO4_Msk (0x1UL << TSC_IOSCR_G2_IO4_Pos)

0x00000080

◆ TSC_IOSCR_G2_IO4_Pos

#define TSC_IOSCR_G2_IO4_Pos (7U)

◆ TSC_IOSCR_G3_IO1

#define TSC_IOSCR_G3_IO1 TSC_IOSCR_G3_IO1_Msk

GROUP3_IO1 sampling mode

◆ TSC_IOSCR_G3_IO1_Msk

#define TSC_IOSCR_G3_IO1_Msk (0x1UL << TSC_IOSCR_G3_IO1_Pos)

0x00000100

◆ TSC_IOSCR_G3_IO1_Pos

#define TSC_IOSCR_G3_IO1_Pos (8U)

◆ TSC_IOSCR_G3_IO2

#define TSC_IOSCR_G3_IO2 TSC_IOSCR_G3_IO2_Msk

GROUP3_IO2 sampling mode

◆ TSC_IOSCR_G3_IO2_Msk

#define TSC_IOSCR_G3_IO2_Msk (0x1UL << TSC_IOSCR_G3_IO2_Pos)

0x00000200

◆ TSC_IOSCR_G3_IO2_Pos

#define TSC_IOSCR_G3_IO2_Pos (9U)

◆ TSC_IOSCR_G3_IO3

#define TSC_IOSCR_G3_IO3 TSC_IOSCR_G3_IO3_Msk

GROUP3_IO3 sampling mode

◆ TSC_IOSCR_G3_IO3_Msk

#define TSC_IOSCR_G3_IO3_Msk (0x1UL << TSC_IOSCR_G3_IO3_Pos)

0x00000400

◆ TSC_IOSCR_G3_IO3_Pos

#define TSC_IOSCR_G3_IO3_Pos (10U)

◆ TSC_IOSCR_G3_IO4

#define TSC_IOSCR_G3_IO4 TSC_IOSCR_G3_IO4_Msk

GROUP3_IO4 sampling mode

◆ TSC_IOSCR_G3_IO4_Msk

#define TSC_IOSCR_G3_IO4_Msk (0x1UL << TSC_IOSCR_G3_IO4_Pos)

0x00000800

◆ TSC_IOSCR_G3_IO4_Pos

#define TSC_IOSCR_G3_IO4_Pos (11U)

◆ TSC_IOSCR_G4_IO1

#define TSC_IOSCR_G4_IO1 TSC_IOSCR_G4_IO1_Msk

GROUP4_IO1 sampling mode

◆ TSC_IOSCR_G4_IO1_Msk

#define TSC_IOSCR_G4_IO1_Msk (0x1UL << TSC_IOSCR_G4_IO1_Pos)

0x00001000

◆ TSC_IOSCR_G4_IO1_Pos

#define TSC_IOSCR_G4_IO1_Pos (12U)

◆ TSC_IOSCR_G4_IO2

#define TSC_IOSCR_G4_IO2 TSC_IOSCR_G4_IO2_Msk

GROUP4_IO2 sampling mode

◆ TSC_IOSCR_G4_IO2_Msk

#define TSC_IOSCR_G4_IO2_Msk (0x1UL << TSC_IOSCR_G4_IO2_Pos)

0x00002000

◆ TSC_IOSCR_G4_IO2_Pos

#define TSC_IOSCR_G4_IO2_Pos (13U)

◆ TSC_IOSCR_G4_IO3

#define TSC_IOSCR_G4_IO3 TSC_IOSCR_G4_IO3_Msk

GROUP4_IO3 sampling mode

◆ TSC_IOSCR_G4_IO3_Msk

#define TSC_IOSCR_G4_IO3_Msk (0x1UL << TSC_IOSCR_G4_IO3_Pos)

0x00004000

◆ TSC_IOSCR_G4_IO3_Pos

#define TSC_IOSCR_G4_IO3_Pos (14U)

◆ TSC_IOSCR_G4_IO4

#define TSC_IOSCR_G4_IO4 TSC_IOSCR_G4_IO4_Msk

GROUP4_IO4 sampling mode

◆ TSC_IOSCR_G4_IO4_Msk

#define TSC_IOSCR_G4_IO4_Msk (0x1UL << TSC_IOSCR_G4_IO4_Pos)

0x00008000

◆ TSC_IOSCR_G4_IO4_Pos

#define TSC_IOSCR_G4_IO4_Pos (15U)

◆ TSC_IOSCR_G5_IO1

#define TSC_IOSCR_G5_IO1 TSC_IOSCR_G5_IO1_Msk

GROUP5_IO1 sampling mode

◆ TSC_IOSCR_G5_IO1_Msk

#define TSC_IOSCR_G5_IO1_Msk (0x1UL << TSC_IOSCR_G5_IO1_Pos)

0x00010000

◆ TSC_IOSCR_G5_IO1_Pos

#define TSC_IOSCR_G5_IO1_Pos (16U)

◆ TSC_IOSCR_G5_IO2

#define TSC_IOSCR_G5_IO2 TSC_IOSCR_G5_IO2_Msk

GROUP5_IO2 sampling mode

◆ TSC_IOSCR_G5_IO2_Msk

#define TSC_IOSCR_G5_IO2_Msk (0x1UL << TSC_IOSCR_G5_IO2_Pos)

0x00020000

◆ TSC_IOSCR_G5_IO2_Pos

#define TSC_IOSCR_G5_IO2_Pos (17U)

◆ TSC_IOSCR_G5_IO3

#define TSC_IOSCR_G5_IO3 TSC_IOSCR_G5_IO3_Msk

GROUP5_IO3 sampling mode

◆ TSC_IOSCR_G5_IO3_Msk

#define TSC_IOSCR_G5_IO3_Msk (0x1UL << TSC_IOSCR_G5_IO3_Pos)

0x00040000

◆ TSC_IOSCR_G5_IO3_Pos

#define TSC_IOSCR_G5_IO3_Pos (18U)

◆ TSC_IOSCR_G5_IO4

#define TSC_IOSCR_G5_IO4 TSC_IOSCR_G5_IO4_Msk

GROUP5_IO4 sampling mode

◆ TSC_IOSCR_G5_IO4_Msk

#define TSC_IOSCR_G5_IO4_Msk (0x1UL << TSC_IOSCR_G5_IO4_Pos)

0x00080000

◆ TSC_IOSCR_G5_IO4_Pos

#define TSC_IOSCR_G5_IO4_Pos (19U)

◆ TSC_IOSCR_G6_IO1

#define TSC_IOSCR_G6_IO1 TSC_IOSCR_G6_IO1_Msk

GROUP6_IO1 sampling mode

◆ TSC_IOSCR_G6_IO1_Msk

#define TSC_IOSCR_G6_IO1_Msk (0x1UL << TSC_IOSCR_G6_IO1_Pos)

0x00100000

◆ TSC_IOSCR_G6_IO1_Pos

#define TSC_IOSCR_G6_IO1_Pos (20U)

◆ TSC_IOSCR_G6_IO2

#define TSC_IOSCR_G6_IO2 TSC_IOSCR_G6_IO2_Msk

GROUP6_IO2 sampling mode

◆ TSC_IOSCR_G6_IO2_Msk

#define TSC_IOSCR_G6_IO2_Msk (0x1UL << TSC_IOSCR_G6_IO2_Pos)

0x00200000

◆ TSC_IOSCR_G6_IO2_Pos

#define TSC_IOSCR_G6_IO2_Pos (21U)

◆ TSC_IOSCR_G6_IO3

#define TSC_IOSCR_G6_IO3 TSC_IOSCR_G6_IO3_Msk

GROUP6_IO3 sampling mode

◆ TSC_IOSCR_G6_IO3_Msk

#define TSC_IOSCR_G6_IO3_Msk (0x1UL << TSC_IOSCR_G6_IO3_Pos)

0x00400000

◆ TSC_IOSCR_G6_IO3_Pos

#define TSC_IOSCR_G6_IO3_Pos (22U)

◆ TSC_IOSCR_G6_IO4

#define TSC_IOSCR_G6_IO4 TSC_IOSCR_G6_IO4_Msk

GROUP6_IO4 sampling mode

◆ TSC_IOSCR_G6_IO4_Msk

#define TSC_IOSCR_G6_IO4_Msk (0x1UL << TSC_IOSCR_G6_IO4_Pos)

0x00800000

◆ TSC_IOSCR_G6_IO4_Pos

#define TSC_IOSCR_G6_IO4_Pos (23U)

◆ TSC_IOSCR_G7_IO1

#define TSC_IOSCR_G7_IO1 TSC_IOSCR_G7_IO1_Msk

GROUP7_IO1 sampling mode

◆ TSC_IOSCR_G7_IO1_Msk

#define TSC_IOSCR_G7_IO1_Msk (0x1UL << TSC_IOSCR_G7_IO1_Pos)

0x01000000

◆ TSC_IOSCR_G7_IO1_Pos

#define TSC_IOSCR_G7_IO1_Pos (24U)

◆ TSC_IOSCR_G7_IO2

#define TSC_IOSCR_G7_IO2 TSC_IOSCR_G7_IO2_Msk

GROUP7_IO2 sampling mode

◆ TSC_IOSCR_G7_IO2_Msk

#define TSC_IOSCR_G7_IO2_Msk (0x1UL << TSC_IOSCR_G7_IO2_Pos)

0x02000000

◆ TSC_IOSCR_G7_IO2_Pos

#define TSC_IOSCR_G7_IO2_Pos (25U)

◆ TSC_IOSCR_G7_IO3

#define TSC_IOSCR_G7_IO3 TSC_IOSCR_G7_IO3_Msk

GROUP7_IO3 sampling mode

◆ TSC_IOSCR_G7_IO3_Msk

#define TSC_IOSCR_G7_IO3_Msk (0x1UL << TSC_IOSCR_G7_IO3_Pos)

0x04000000

◆ TSC_IOSCR_G7_IO3_Pos

#define TSC_IOSCR_G7_IO3_Pos (26U)

◆ TSC_IOSCR_G7_IO4

#define TSC_IOSCR_G7_IO4 TSC_IOSCR_G7_IO4_Msk

GROUP7_IO4 sampling mode

◆ TSC_IOSCR_G7_IO4_Msk

#define TSC_IOSCR_G7_IO4_Msk (0x1UL << TSC_IOSCR_G7_IO4_Pos)

0x08000000

◆ TSC_IOSCR_G7_IO4_Pos

#define TSC_IOSCR_G7_IO4_Pos (27U)

◆ TSC_IOSCR_G8_IO1

#define TSC_IOSCR_G8_IO1 TSC_IOSCR_G8_IO1_Msk

GROUP8_IO1 sampling mode

◆ TSC_IOSCR_G8_IO1_Msk

#define TSC_IOSCR_G8_IO1_Msk (0x1UL << TSC_IOSCR_G8_IO1_Pos)

0x10000000

◆ TSC_IOSCR_G8_IO1_Pos

#define TSC_IOSCR_G8_IO1_Pos (28U)

◆ TSC_IOSCR_G8_IO2

#define TSC_IOSCR_G8_IO2 TSC_IOSCR_G8_IO2_Msk

GROUP8_IO2 sampling mode

◆ TSC_IOSCR_G8_IO2_Msk

#define TSC_IOSCR_G8_IO2_Msk (0x1UL << TSC_IOSCR_G8_IO2_Pos)

0x20000000

◆ TSC_IOSCR_G8_IO2_Pos

#define TSC_IOSCR_G8_IO2_Pos (29U)

◆ TSC_IOSCR_G8_IO3

#define TSC_IOSCR_G8_IO3 TSC_IOSCR_G8_IO3_Msk

GROUP8_IO3 sampling mode

◆ TSC_IOSCR_G8_IO3_Msk

#define TSC_IOSCR_G8_IO3_Msk (0x1UL << TSC_IOSCR_G8_IO3_Pos)

0x40000000

◆ TSC_IOSCR_G8_IO3_Pos

#define TSC_IOSCR_G8_IO3_Pos (30U)

◆ TSC_IOSCR_G8_IO4

#define TSC_IOSCR_G8_IO4 TSC_IOSCR_G8_IO4_Msk

GROUP8_IO4 sampling mode

◆ TSC_IOSCR_G8_IO4_Msk

#define TSC_IOSCR_G8_IO4_Msk (0x1UL << TSC_IOSCR_G8_IO4_Pos)

0x80000000

◆ TSC_IOSCR_G8_IO4_Pos

#define TSC_IOSCR_G8_IO4_Pos (31U)

◆ TSC_ISR_EOAF

#define TSC_ISR_EOAF TSC_ISR_EOAF_Msk

End of acquisition flag

◆ TSC_ISR_EOAF_Msk

#define TSC_ISR_EOAF_Msk (0x1UL << TSC_ISR_EOAF_Pos)

0x00000001

◆ TSC_ISR_EOAF_Pos

#define TSC_ISR_EOAF_Pos (0U)

◆ TSC_ISR_MCEF

#define TSC_ISR_MCEF TSC_ISR_MCEF_Msk

Max count error flag

◆ TSC_ISR_MCEF_Msk

#define TSC_ISR_MCEF_Msk (0x1UL << TSC_ISR_MCEF_Pos)

0x00000002

◆ TSC_ISR_MCEF_Pos

#define TSC_ISR_MCEF_Pos (1U)

◆ USART_7BITS_SUPPORT

#define USART_7BITS_SUPPORT

◆ USART_BRR_DIV_FRACTION

#define USART_BRR_DIV_FRACTION USART_BRR_DIV_FRACTION_Msk

Fraction of USARTDIV

◆ USART_BRR_DIV_FRACTION_Msk

#define USART_BRR_DIV_FRACTION_Msk (0xFUL << USART_BRR_DIV_FRACTION_Pos)

0x0000000F

◆ USART_BRR_DIV_FRACTION_Pos

#define USART_BRR_DIV_FRACTION_Pos (0U)

◆ USART_BRR_DIV_MANTISSA

#define USART_BRR_DIV_MANTISSA USART_BRR_DIV_MANTISSA_Msk

Mantissa of USARTDIV

◆ USART_BRR_DIV_MANTISSA_Msk

#define USART_BRR_DIV_MANTISSA_Msk (0xFFFUL << USART_BRR_DIV_MANTISSA_Pos)

0x0000FFF0

◆ USART_BRR_DIV_MANTISSA_Pos

#define USART_BRR_DIV_MANTISSA_Pos (4U)

◆ USART_CR1_CMIE

#define USART_CR1_CMIE USART_CR1_CMIE_Msk

Character match interrupt enable

◆ USART_CR1_CMIE_Msk

#define USART_CR1_CMIE_Msk (0x1UL << USART_CR1_CMIE_Pos)

0x00004000

◆ USART_CR1_CMIE_Pos

#define USART_CR1_CMIE_Pos (14U)

◆ USART_CR1_DEAT

#define USART_CR1_DEAT USART_CR1_DEAT_Msk

DEAT[4:0] bits (Driver Enable Assertion Time)

◆ USART_CR1_DEAT_0

#define USART_CR1_DEAT_0 (0x01UL << USART_CR1_DEAT_Pos)

0x00200000

◆ USART_CR1_DEAT_1

#define USART_CR1_DEAT_1 (0x02UL << USART_CR1_DEAT_Pos)

0x00400000

◆ USART_CR1_DEAT_2

#define USART_CR1_DEAT_2 (0x04UL << USART_CR1_DEAT_Pos)

0x00800000

◆ USART_CR1_DEAT_3

#define USART_CR1_DEAT_3 (0x08UL << USART_CR1_DEAT_Pos)

0x01000000

◆ USART_CR1_DEAT_4

#define USART_CR1_DEAT_4 (0x10UL << USART_CR1_DEAT_Pos)

0x02000000

◆ USART_CR1_DEAT_Msk

#define USART_CR1_DEAT_Msk (0x1FUL << USART_CR1_DEAT_Pos)

0x03E00000

◆ USART_CR1_DEAT_Pos

#define USART_CR1_DEAT_Pos (21U)

◆ USART_CR1_DEDT

#define USART_CR1_DEDT USART_CR1_DEDT_Msk

DEDT[4:0] bits (Driver Enable Deassertion Time)

◆ USART_CR1_DEDT_0

#define USART_CR1_DEDT_0 (0x01UL << USART_CR1_DEDT_Pos)

0x00010000

◆ USART_CR1_DEDT_1

#define USART_CR1_DEDT_1 (0x02UL << USART_CR1_DEDT_Pos)

0x00020000

◆ USART_CR1_DEDT_2

#define USART_CR1_DEDT_2 (0x04UL << USART_CR1_DEDT_Pos)

0x00040000

◆ USART_CR1_DEDT_3

#define USART_CR1_DEDT_3 (0x08UL << USART_CR1_DEDT_Pos)

0x00080000

◆ USART_CR1_DEDT_4

#define USART_CR1_DEDT_4 (0x10UL << USART_CR1_DEDT_Pos)

0x00100000

◆ USART_CR1_DEDT_Msk

#define USART_CR1_DEDT_Msk (0x1FUL << USART_CR1_DEDT_Pos)

0x001F0000

◆ USART_CR1_DEDT_Pos

#define USART_CR1_DEDT_Pos (16U)

◆ USART_CR1_EOBIE

#define USART_CR1_EOBIE USART_CR1_EOBIE_Msk

End of Block interrupt enable

◆ USART_CR1_EOBIE_Msk

#define USART_CR1_EOBIE_Msk (0x1UL << USART_CR1_EOBIE_Pos)

0x08000000

◆ USART_CR1_EOBIE_Pos

#define USART_CR1_EOBIE_Pos (27U)

◆ USART_CR1_IDLEIE

#define USART_CR1_IDLEIE USART_CR1_IDLEIE_Msk

IDLE Interrupt Enable

◆ USART_CR1_IDLEIE_Msk

#define USART_CR1_IDLEIE_Msk (0x1UL << USART_CR1_IDLEIE_Pos)

0x00000010

◆ USART_CR1_IDLEIE_Pos

#define USART_CR1_IDLEIE_Pos (4U)

◆ USART_CR1_M

#define USART_CR1_M USART_CR1_M_Msk

[M1:M0] Word length

◆ USART_CR1_M0

#define USART_CR1_M0 USART_CR1_M0_Msk

Word length bit 0

◆ USART_CR1_M0_Msk

#define USART_CR1_M0_Msk (0x1UL << USART_CR1_M0_Pos)

0x00001000

◆ USART_CR1_M0_Pos

#define USART_CR1_M0_Pos (12U)

◆ USART_CR1_M1

#define USART_CR1_M1 USART_CR1_M1_Msk

Word length bit 1

◆ USART_CR1_M1_Msk

#define USART_CR1_M1_Msk (0x1UL << USART_CR1_M1_Pos)

0x10000000

◆ USART_CR1_M1_Pos

#define USART_CR1_M1_Pos (28U)

◆ USART_CR1_M_Msk

#define USART_CR1_M_Msk (0x10001UL << USART_CR1_M_Pos)

0x10001000

◆ USART_CR1_M_Pos

#define USART_CR1_M_Pos (12U)

◆ USART_CR1_MME

#define USART_CR1_MME USART_CR1_MME_Msk

Mute Mode Enable

◆ USART_CR1_MME_Msk

#define USART_CR1_MME_Msk (0x1UL << USART_CR1_MME_Pos)

0x00002000

◆ USART_CR1_MME_Pos

#define USART_CR1_MME_Pos (13U)

◆ USART_CR1_OVER8

#define USART_CR1_OVER8 USART_CR1_OVER8_Msk

Oversampling by 8-bit or 16-bit mode

◆ USART_CR1_OVER8_Msk

#define USART_CR1_OVER8_Msk (0x1UL << USART_CR1_OVER8_Pos)

0x00008000

◆ USART_CR1_OVER8_Pos

#define USART_CR1_OVER8_Pos (15U)

◆ USART_CR1_PCE

#define USART_CR1_PCE USART_CR1_PCE_Msk

Parity Control Enable

◆ USART_CR1_PCE_Msk

#define USART_CR1_PCE_Msk (0x1UL << USART_CR1_PCE_Pos)

0x00000400

◆ USART_CR1_PCE_Pos

#define USART_CR1_PCE_Pos (10U)

◆ USART_CR1_PEIE

#define USART_CR1_PEIE USART_CR1_PEIE_Msk

PE Interrupt Enable

◆ USART_CR1_PEIE_Msk

#define USART_CR1_PEIE_Msk (0x1UL << USART_CR1_PEIE_Pos)

0x00000100

◆ USART_CR1_PEIE_Pos

#define USART_CR1_PEIE_Pos (8U)

◆ USART_CR1_PS

#define USART_CR1_PS USART_CR1_PS_Msk

Parity Selection

◆ USART_CR1_PS_Msk

#define USART_CR1_PS_Msk (0x1UL << USART_CR1_PS_Pos)

0x00000200

◆ USART_CR1_PS_Pos

#define USART_CR1_PS_Pos (9U)

◆ USART_CR1_RE

#define USART_CR1_RE USART_CR1_RE_Msk

Receiver Enable

◆ USART_CR1_RE_Msk

#define USART_CR1_RE_Msk (0x1UL << USART_CR1_RE_Pos)

0x00000004

◆ USART_CR1_RE_Pos

#define USART_CR1_RE_Pos (2U)

◆ USART_CR1_RTOIE

#define USART_CR1_RTOIE USART_CR1_RTOIE_Msk

Receive Time Out interrupt enable

◆ USART_CR1_RTOIE_Msk

#define USART_CR1_RTOIE_Msk (0x1UL << USART_CR1_RTOIE_Pos)

0x04000000

◆ USART_CR1_RTOIE_Pos

#define USART_CR1_RTOIE_Pos (26U)

◆ USART_CR1_RXNEIE

#define USART_CR1_RXNEIE USART_CR1_RXNEIE_Msk

RXNE Interrupt Enable

◆ USART_CR1_RXNEIE_Msk

#define USART_CR1_RXNEIE_Msk (0x1UL << USART_CR1_RXNEIE_Pos)

0x00000020

◆ USART_CR1_RXNEIE_Pos

#define USART_CR1_RXNEIE_Pos (5U)

◆ USART_CR1_TCIE

#define USART_CR1_TCIE USART_CR1_TCIE_Msk

Transmission Complete Interrupt Enable

◆ USART_CR1_TCIE_Msk

#define USART_CR1_TCIE_Msk (0x1UL << USART_CR1_TCIE_Pos)

0x00000040

◆ USART_CR1_TCIE_Pos

#define USART_CR1_TCIE_Pos (6U)

◆ USART_CR1_TE

#define USART_CR1_TE USART_CR1_TE_Msk

Transmitter Enable

◆ USART_CR1_TE_Msk

#define USART_CR1_TE_Msk (0x1UL << USART_CR1_TE_Pos)

0x00000008

◆ USART_CR1_TE_Pos

#define USART_CR1_TE_Pos (3U)

◆ USART_CR1_TXEIE

#define USART_CR1_TXEIE USART_CR1_TXEIE_Msk

TXE Interrupt Enable

◆ USART_CR1_TXEIE_Msk

#define USART_CR1_TXEIE_Msk (0x1UL << USART_CR1_TXEIE_Pos)

0x00000080

◆ USART_CR1_TXEIE_Pos

#define USART_CR1_TXEIE_Pos (7U)

◆ USART_CR1_UE

#define USART_CR1_UE USART_CR1_UE_Msk

USART Enable

◆ USART_CR1_UE_Msk

#define USART_CR1_UE_Msk (0x1UL << USART_CR1_UE_Pos)

0x00000001

◆ USART_CR1_UE_Pos

#define USART_CR1_UE_Pos (0U)

◆ USART_CR1_UESM

#define USART_CR1_UESM USART_CR1_UESM_Msk

USART Enable in STOP Mode

◆ USART_CR1_UESM_Msk

#define USART_CR1_UESM_Msk (0x1UL << USART_CR1_UESM_Pos)

0x00000002

◆ USART_CR1_UESM_Pos

#define USART_CR1_UESM_Pos (1U)

◆ USART_CR1_WAKE

#define USART_CR1_WAKE USART_CR1_WAKE_Msk

Receiver Wakeup method

◆ USART_CR1_WAKE_Msk

#define USART_CR1_WAKE_Msk (0x1UL << USART_CR1_WAKE_Pos)

0x00000800

◆ USART_CR1_WAKE_Pos

#define USART_CR1_WAKE_Pos (11U)

◆ USART_CR2_ABREN

#define USART_CR2_ABREN USART_CR2_ABREN_Msk

Auto Baud-Rate Enable

◆ USART_CR2_ABREN_Msk

#define USART_CR2_ABREN_Msk (0x1UL << USART_CR2_ABREN_Pos)

0x00100000

◆ USART_CR2_ABREN_Pos

#define USART_CR2_ABREN_Pos (20U)

◆ USART_CR2_ABRMODE

#define USART_CR2_ABRMODE USART_CR2_ABRMODE_Msk

ABRMOD[1:0] bits (Auto Baud-Rate Mode)

◆ USART_CR2_ABRMODE_0

#define USART_CR2_ABRMODE_0 (0x1UL << USART_CR2_ABRMODE_Pos)

0x00200000

◆ USART_CR2_ABRMODE_1

#define USART_CR2_ABRMODE_1 (0x2UL << USART_CR2_ABRMODE_Pos)

0x00400000

◆ USART_CR2_ABRMODE_Msk

#define USART_CR2_ABRMODE_Msk (0x3UL << USART_CR2_ABRMODE_Pos)

0x00600000

◆ USART_CR2_ABRMODE_Pos

#define USART_CR2_ABRMODE_Pos (21U)

◆ USART_CR2_ADD

#define USART_CR2_ADD USART_CR2_ADD_Msk

Address of the USART node

◆ USART_CR2_ADD_Msk

#define USART_CR2_ADD_Msk (0xFFUL << USART_CR2_ADD_Pos)

0xFF000000

◆ USART_CR2_ADD_Pos

#define USART_CR2_ADD_Pos (24U)

◆ USART_CR2_ADDM7

#define USART_CR2_ADDM7 USART_CR2_ADDM7_Msk

7-bit or 4-bit Address Detection

◆ USART_CR2_ADDM7_Msk

#define USART_CR2_ADDM7_Msk (0x1UL << USART_CR2_ADDM7_Pos)

0x00000010

◆ USART_CR2_ADDM7_Pos

#define USART_CR2_ADDM7_Pos (4U)

◆ USART_CR2_CLKEN

#define USART_CR2_CLKEN USART_CR2_CLKEN_Msk

Clock Enable

◆ USART_CR2_CLKEN_Msk

#define USART_CR2_CLKEN_Msk (0x1UL << USART_CR2_CLKEN_Pos)

0x00000800

◆ USART_CR2_CLKEN_Pos

#define USART_CR2_CLKEN_Pos (11U)

◆ USART_CR2_CPHA

#define USART_CR2_CPHA USART_CR2_CPHA_Msk

Clock Phase

◆ USART_CR2_CPHA_Msk

#define USART_CR2_CPHA_Msk (0x1UL << USART_CR2_CPHA_Pos)

0x00000200

◆ USART_CR2_CPHA_Pos

#define USART_CR2_CPHA_Pos (9U)

◆ USART_CR2_CPOL

#define USART_CR2_CPOL USART_CR2_CPOL_Msk

Clock Polarity

◆ USART_CR2_CPOL_Msk

#define USART_CR2_CPOL_Msk (0x1UL << USART_CR2_CPOL_Pos)

0x00000400

◆ USART_CR2_CPOL_Pos

#define USART_CR2_CPOL_Pos (10U)

◆ USART_CR2_DATAINV

#define USART_CR2_DATAINV USART_CR2_DATAINV_Msk

Binary data inversion

◆ USART_CR2_DATAINV_Msk

#define USART_CR2_DATAINV_Msk (0x1UL << USART_CR2_DATAINV_Pos)

0x00040000

◆ USART_CR2_DATAINV_Pos

#define USART_CR2_DATAINV_Pos (18U)

◆ USART_CR2_LBCL

#define USART_CR2_LBCL USART_CR2_LBCL_Msk

Last Bit Clock pulse

◆ USART_CR2_LBCL_Msk

#define USART_CR2_LBCL_Msk (0x1UL << USART_CR2_LBCL_Pos)

0x00000100

◆ USART_CR2_LBCL_Pos

#define USART_CR2_LBCL_Pos (8U)

◆ USART_CR2_LBDIE

#define USART_CR2_LBDIE USART_CR2_LBDIE_Msk

LIN Break Detection Interrupt Enable

◆ USART_CR2_LBDIE_Msk

#define USART_CR2_LBDIE_Msk (0x1UL << USART_CR2_LBDIE_Pos)

0x00000040

◆ USART_CR2_LBDIE_Pos

#define USART_CR2_LBDIE_Pos (6U)

◆ USART_CR2_LBDL

#define USART_CR2_LBDL USART_CR2_LBDL_Msk

LIN Break Detection Length

◆ USART_CR2_LBDL_Msk

#define USART_CR2_LBDL_Msk (0x1UL << USART_CR2_LBDL_Pos)

0x00000020

◆ USART_CR2_LBDL_Pos

#define USART_CR2_LBDL_Pos (5U)

◆ USART_CR2_LINEN

#define USART_CR2_LINEN USART_CR2_LINEN_Msk

LIN mode enable

◆ USART_CR2_LINEN_Msk

#define USART_CR2_LINEN_Msk (0x1UL << USART_CR2_LINEN_Pos)

0x00004000

◆ USART_CR2_LINEN_Pos

#define USART_CR2_LINEN_Pos (14U)

◆ USART_CR2_MSBFIRST

#define USART_CR2_MSBFIRST USART_CR2_MSBFIRST_Msk

Most Significant Bit First

◆ USART_CR2_MSBFIRST_Msk

#define USART_CR2_MSBFIRST_Msk (0x1UL << USART_CR2_MSBFIRST_Pos)

0x00080000

◆ USART_CR2_MSBFIRST_Pos

#define USART_CR2_MSBFIRST_Pos (19U)

◆ USART_CR2_RTOEN

#define USART_CR2_RTOEN USART_CR2_RTOEN_Msk

Receiver Time-Out enable

◆ USART_CR2_RTOEN_Msk

#define USART_CR2_RTOEN_Msk (0x1UL << USART_CR2_RTOEN_Pos)

0x00800000

◆ USART_CR2_RTOEN_Pos

#define USART_CR2_RTOEN_Pos (23U)

◆ USART_CR2_RXINV

#define USART_CR2_RXINV USART_CR2_RXINV_Msk

RX pin active level inversion

◆ USART_CR2_RXINV_Msk

#define USART_CR2_RXINV_Msk (0x1UL << USART_CR2_RXINV_Pos)

0x00010000

◆ USART_CR2_RXINV_Pos

#define USART_CR2_RXINV_Pos (16U)

◆ USART_CR2_STOP

#define USART_CR2_STOP USART_CR2_STOP_Msk

STOP[1:0] bits (STOP bits)

◆ USART_CR2_STOP_0

#define USART_CR2_STOP_0 (0x1UL << USART_CR2_STOP_Pos)

0x00001000

◆ USART_CR2_STOP_1

#define USART_CR2_STOP_1 (0x2UL << USART_CR2_STOP_Pos)

0x00002000

◆ USART_CR2_STOP_Msk

#define USART_CR2_STOP_Msk (0x3UL << USART_CR2_STOP_Pos)

0x00003000

◆ USART_CR2_STOP_Pos

#define USART_CR2_STOP_Pos (12U)

◆ USART_CR2_SWAP

#define USART_CR2_SWAP USART_CR2_SWAP_Msk

SWAP TX/RX pins

◆ USART_CR2_SWAP_Msk

#define USART_CR2_SWAP_Msk (0x1UL << USART_CR2_SWAP_Pos)

0x00008000

◆ USART_CR2_SWAP_Pos

#define USART_CR2_SWAP_Pos (15U)

◆ USART_CR2_TXINV

#define USART_CR2_TXINV USART_CR2_TXINV_Msk

TX pin active level inversion

◆ USART_CR2_TXINV_Msk

#define USART_CR2_TXINV_Msk (0x1UL << USART_CR2_TXINV_Pos)

0x00020000

◆ USART_CR2_TXINV_Pos

#define USART_CR2_TXINV_Pos (17U)

◆ USART_CR3_CTSE

#define USART_CR3_CTSE USART_CR3_CTSE_Msk

CTS Enable

◆ USART_CR3_CTSE_Msk

#define USART_CR3_CTSE_Msk (0x1UL << USART_CR3_CTSE_Pos)

0x00000200

◆ USART_CR3_CTSE_Pos

#define USART_CR3_CTSE_Pos (9U)

◆ USART_CR3_CTSIE

#define USART_CR3_CTSIE USART_CR3_CTSIE_Msk

CTS Interrupt Enable

◆ USART_CR3_CTSIE_Msk

#define USART_CR3_CTSIE_Msk (0x1UL << USART_CR3_CTSIE_Pos)

0x00000400

◆ USART_CR3_CTSIE_Pos

#define USART_CR3_CTSIE_Pos (10U)

◆ USART_CR3_DDRE

#define USART_CR3_DDRE USART_CR3_DDRE_Msk

DMA Disable on Reception Error

◆ USART_CR3_DDRE_Msk

#define USART_CR3_DDRE_Msk (0x1UL << USART_CR3_DDRE_Pos)

0x00002000

◆ USART_CR3_DDRE_Pos

#define USART_CR3_DDRE_Pos (13U)

◆ USART_CR3_DEM

#define USART_CR3_DEM USART_CR3_DEM_Msk

Driver Enable Mode

◆ USART_CR3_DEM_Msk

#define USART_CR3_DEM_Msk (0x1UL << USART_CR3_DEM_Pos)

0x00004000

◆ USART_CR3_DEM_Pos

#define USART_CR3_DEM_Pos (14U)

◆ USART_CR3_DEP

#define USART_CR3_DEP USART_CR3_DEP_Msk

Driver Enable Polarity Selection

◆ USART_CR3_DEP_Msk

#define USART_CR3_DEP_Msk (0x1UL << USART_CR3_DEP_Pos)

0x00008000

◆ USART_CR3_DEP_Pos

#define USART_CR3_DEP_Pos (15U)

◆ USART_CR3_DMAR

#define USART_CR3_DMAR USART_CR3_DMAR_Msk

DMA Enable Receiver

◆ USART_CR3_DMAR_Msk

#define USART_CR3_DMAR_Msk (0x1UL << USART_CR3_DMAR_Pos)

0x00000040

◆ USART_CR3_DMAR_Pos

#define USART_CR3_DMAR_Pos (6U)

◆ USART_CR3_DMAT

#define USART_CR3_DMAT USART_CR3_DMAT_Msk

DMA Enable Transmitter

◆ USART_CR3_DMAT_Msk

#define USART_CR3_DMAT_Msk (0x1UL << USART_CR3_DMAT_Pos)

0x00000080

◆ USART_CR3_DMAT_Pos

#define USART_CR3_DMAT_Pos (7U)

◆ USART_CR3_EIE

#define USART_CR3_EIE USART_CR3_EIE_Msk

Error Interrupt Enable

◆ USART_CR3_EIE_Msk

#define USART_CR3_EIE_Msk (0x1UL << USART_CR3_EIE_Pos)

0x00000001

◆ USART_CR3_EIE_Pos

#define USART_CR3_EIE_Pos (0U)

◆ USART_CR3_HDSEL

#define USART_CR3_HDSEL USART_CR3_HDSEL_Msk

Half-Duplex Selection

◆ USART_CR3_HDSEL_Msk

#define USART_CR3_HDSEL_Msk (0x1UL << USART_CR3_HDSEL_Pos)

0x00000008

◆ USART_CR3_HDSEL_Pos

#define USART_CR3_HDSEL_Pos (3U)

◆ USART_CR3_IREN

#define USART_CR3_IREN USART_CR3_IREN_Msk

IrDA mode Enable

◆ USART_CR3_IREN_Msk

#define USART_CR3_IREN_Msk (0x1UL << USART_CR3_IREN_Pos)

0x00000002

◆ USART_CR3_IREN_Pos

#define USART_CR3_IREN_Pos (1U)

◆ USART_CR3_IRLP

#define USART_CR3_IRLP USART_CR3_IRLP_Msk

IrDA Low-Power

◆ USART_CR3_IRLP_Msk

#define USART_CR3_IRLP_Msk (0x1UL << USART_CR3_IRLP_Pos)

0x00000004

◆ USART_CR3_IRLP_Pos

#define USART_CR3_IRLP_Pos (2U)

◆ USART_CR3_NACK

#define USART_CR3_NACK USART_CR3_NACK_Msk

SmartCard NACK enable

◆ USART_CR3_NACK_Msk

#define USART_CR3_NACK_Msk (0x1UL << USART_CR3_NACK_Pos)

0x00000010

◆ USART_CR3_NACK_Pos

#define USART_CR3_NACK_Pos (4U)

◆ USART_CR3_ONEBIT

#define USART_CR3_ONEBIT USART_CR3_ONEBIT_Msk

One sample bit method enable

◆ USART_CR3_ONEBIT_Msk

#define USART_CR3_ONEBIT_Msk (0x1UL << USART_CR3_ONEBIT_Pos)

0x00000800

◆ USART_CR3_ONEBIT_Pos

#define USART_CR3_ONEBIT_Pos (11U)

◆ USART_CR3_OVRDIS

#define USART_CR3_OVRDIS USART_CR3_OVRDIS_Msk

Overrun Disable

◆ USART_CR3_OVRDIS_Msk

#define USART_CR3_OVRDIS_Msk (0x1UL << USART_CR3_OVRDIS_Pos)

0x00001000

◆ USART_CR3_OVRDIS_Pos

#define USART_CR3_OVRDIS_Pos (12U)

◆ USART_CR3_RTSE

#define USART_CR3_RTSE USART_CR3_RTSE_Msk

RTS Enable

◆ USART_CR3_RTSE_Msk

#define USART_CR3_RTSE_Msk (0x1UL << USART_CR3_RTSE_Pos)

0x00000100

◆ USART_CR3_RTSE_Pos

#define USART_CR3_RTSE_Pos (8U)

◆ USART_CR3_SCARCNT

#define USART_CR3_SCARCNT USART_CR3_SCARCNT_Msk

SCARCNT[2:0] bits (SmartCard Auto-Retry Count)

◆ USART_CR3_SCARCNT_0

#define USART_CR3_SCARCNT_0 (0x1UL << USART_CR3_SCARCNT_Pos)

0x00020000

◆ USART_CR3_SCARCNT_1

#define USART_CR3_SCARCNT_1 (0x2UL << USART_CR3_SCARCNT_Pos)

0x00040000

◆ USART_CR3_SCARCNT_2

#define USART_CR3_SCARCNT_2 (0x4UL << USART_CR3_SCARCNT_Pos)

0x00080000

◆ USART_CR3_SCARCNT_Msk

#define USART_CR3_SCARCNT_Msk (0x7UL << USART_CR3_SCARCNT_Pos)

0x000E0000

◆ USART_CR3_SCARCNT_Pos

#define USART_CR3_SCARCNT_Pos (17U)

◆ USART_CR3_SCEN

#define USART_CR3_SCEN USART_CR3_SCEN_Msk

SmartCard mode enable

◆ USART_CR3_SCEN_Msk

#define USART_CR3_SCEN_Msk (0x1UL << USART_CR3_SCEN_Pos)

0x00000020

◆ USART_CR3_SCEN_Pos

#define USART_CR3_SCEN_Pos (5U)

◆ USART_CR3_WUFIE

#define USART_CR3_WUFIE USART_CR3_WUFIE_Msk

Wake Up Interrupt Enable

◆ USART_CR3_WUFIE_Msk

#define USART_CR3_WUFIE_Msk (0x1UL << USART_CR3_WUFIE_Pos)

0x00400000

◆ USART_CR3_WUFIE_Pos

#define USART_CR3_WUFIE_Pos (22U)

◆ USART_CR3_WUS

#define USART_CR3_WUS USART_CR3_WUS_Msk

WUS[1:0] bits (Wake UP Interrupt Flag Selection)

◆ USART_CR3_WUS_0

#define USART_CR3_WUS_0 (0x1UL << USART_CR3_WUS_Pos)

0x00100000

◆ USART_CR3_WUS_1

#define USART_CR3_WUS_1 (0x2UL << USART_CR3_WUS_Pos)

0x00200000

◆ USART_CR3_WUS_Msk

#define USART_CR3_WUS_Msk (0x3UL << USART_CR3_WUS_Pos)

0x00300000

◆ USART_CR3_WUS_Pos

#define USART_CR3_WUS_Pos (20U)

◆ USART_GTPR_GT

#define USART_GTPR_GT USART_GTPR_GT_Msk

GT[7:0] bits (Guard time value)

◆ USART_GTPR_GT_Msk

#define USART_GTPR_GT_Msk (0xFFUL << USART_GTPR_GT_Pos)

0x0000FF00

◆ USART_GTPR_GT_Pos

#define USART_GTPR_GT_Pos (8U)

◆ USART_GTPR_PSC

#define USART_GTPR_PSC USART_GTPR_PSC_Msk

PSC[7:0] bits (Prescaler value)

◆ USART_GTPR_PSC_Msk

#define USART_GTPR_PSC_Msk (0xFFUL << USART_GTPR_PSC_Pos)

0x000000FF

◆ USART_GTPR_PSC_Pos

#define USART_GTPR_PSC_Pos (0U)

◆ USART_ICR_CMCF

#define USART_ICR_CMCF USART_ICR_CMCF_Msk

Character Match Clear Flag

◆ USART_ICR_CMCF_Msk

#define USART_ICR_CMCF_Msk (0x1UL << USART_ICR_CMCF_Pos)

0x00020000

◆ USART_ICR_CMCF_Pos

#define USART_ICR_CMCF_Pos (17U)

◆ USART_ICR_CTSCF

#define USART_ICR_CTSCF USART_ICR_CTSCF_Msk

CTS Interrupt Clear Flag

◆ USART_ICR_CTSCF_Msk

#define USART_ICR_CTSCF_Msk (0x1UL << USART_ICR_CTSCF_Pos)

0x00000200

◆ USART_ICR_CTSCF_Pos

#define USART_ICR_CTSCF_Pos (9U)

◆ USART_ICR_EOBCF

#define USART_ICR_EOBCF USART_ICR_EOBCF_Msk

End Of Block Clear Flag

◆ USART_ICR_EOBCF_Msk

#define USART_ICR_EOBCF_Msk (0x1UL << USART_ICR_EOBCF_Pos)

0x00001000

◆ USART_ICR_EOBCF_Pos

#define USART_ICR_EOBCF_Pos (12U)

◆ USART_ICR_FECF

#define USART_ICR_FECF USART_ICR_FECF_Msk

Framing Error Clear Flag

◆ USART_ICR_FECF_Msk

#define USART_ICR_FECF_Msk (0x1UL << USART_ICR_FECF_Pos)

0x00000002

◆ USART_ICR_FECF_Pos

#define USART_ICR_FECF_Pos (1U)

◆ USART_ICR_IDLECF

#define USART_ICR_IDLECF USART_ICR_IDLECF_Msk

IDLE line detected Clear Flag

◆ USART_ICR_IDLECF_Msk

#define USART_ICR_IDLECF_Msk (0x1UL << USART_ICR_IDLECF_Pos)

0x00000010

◆ USART_ICR_IDLECF_Pos

#define USART_ICR_IDLECF_Pos (4U)

◆ USART_ICR_LBDCF

#define USART_ICR_LBDCF USART_ICR_LBDCF_Msk

LIN Break Detection Clear Flag

◆ USART_ICR_LBDCF_Msk

#define USART_ICR_LBDCF_Msk (0x1UL << USART_ICR_LBDCF_Pos)

0x00000100

◆ USART_ICR_LBDCF_Pos

#define USART_ICR_LBDCF_Pos (8U)

◆ USART_ICR_NCF

#define USART_ICR_NCF USART_ICR_NCF_Msk

Noise detected Clear Flag

◆ USART_ICR_NCF_Msk

#define USART_ICR_NCF_Msk (0x1UL << USART_ICR_NCF_Pos)

0x00000004

◆ USART_ICR_NCF_Pos

#define USART_ICR_NCF_Pos (2U)

◆ USART_ICR_ORECF

#define USART_ICR_ORECF USART_ICR_ORECF_Msk

OverRun Error Clear Flag

◆ USART_ICR_ORECF_Msk

#define USART_ICR_ORECF_Msk (0x1UL << USART_ICR_ORECF_Pos)

0x00000008

◆ USART_ICR_ORECF_Pos

#define USART_ICR_ORECF_Pos (3U)

◆ USART_ICR_PECF

#define USART_ICR_PECF USART_ICR_PECF_Msk

Parity Error Clear Flag

◆ USART_ICR_PECF_Msk

#define USART_ICR_PECF_Msk (0x1UL << USART_ICR_PECF_Pos)

0x00000001

◆ USART_ICR_PECF_Pos

#define USART_ICR_PECF_Pos (0U)

◆ USART_ICR_RTOCF

#define USART_ICR_RTOCF USART_ICR_RTOCF_Msk

Receiver Time Out Clear Flag

◆ USART_ICR_RTOCF_Msk

#define USART_ICR_RTOCF_Msk (0x1UL << USART_ICR_RTOCF_Pos)

0x00000800

◆ USART_ICR_RTOCF_Pos

#define USART_ICR_RTOCF_Pos (11U)

◆ USART_ICR_TCCF

#define USART_ICR_TCCF USART_ICR_TCCF_Msk

Transmission Complete Clear Flag

◆ USART_ICR_TCCF_Msk

#define USART_ICR_TCCF_Msk (0x1UL << USART_ICR_TCCF_Pos)

0x00000040

◆ USART_ICR_TCCF_Pos

#define USART_ICR_TCCF_Pos (6U)

◆ USART_ICR_WUCF

#define USART_ICR_WUCF USART_ICR_WUCF_Msk

Wake Up from stop mode Clear Flag

◆ USART_ICR_WUCF_Msk

#define USART_ICR_WUCF_Msk (0x1UL << USART_ICR_WUCF_Pos)

0x00100000

◆ USART_ICR_WUCF_Pos

#define USART_ICR_WUCF_Pos (20U)

◆ USART_ISR_ABRE

#define USART_ISR_ABRE USART_ISR_ABRE_Msk

Auto-Baud Rate Error

◆ USART_ISR_ABRE_Msk

#define USART_ISR_ABRE_Msk (0x1UL << USART_ISR_ABRE_Pos)

0x00004000

◆ USART_ISR_ABRE_Pos

#define USART_ISR_ABRE_Pos (14U)

◆ USART_ISR_ABRF

#define USART_ISR_ABRF USART_ISR_ABRF_Msk

Auto-Baud Rate Flag

◆ USART_ISR_ABRF_Msk

#define USART_ISR_ABRF_Msk (0x1UL << USART_ISR_ABRF_Pos)

0x00008000

◆ USART_ISR_ABRF_Pos

#define USART_ISR_ABRF_Pos (15U)

◆ USART_ISR_BUSY

#define USART_ISR_BUSY USART_ISR_BUSY_Msk

Busy Flag

◆ USART_ISR_BUSY_Msk

#define USART_ISR_BUSY_Msk (0x1UL << USART_ISR_BUSY_Pos)

0x00010000

◆ USART_ISR_BUSY_Pos

#define USART_ISR_BUSY_Pos (16U)

◆ USART_ISR_CMF

#define USART_ISR_CMF USART_ISR_CMF_Msk

Character Match Flag

◆ USART_ISR_CMF_Msk

#define USART_ISR_CMF_Msk (0x1UL << USART_ISR_CMF_Pos)

0x00020000

◆ USART_ISR_CMF_Pos

#define USART_ISR_CMF_Pos (17U)

◆ USART_ISR_CTS

#define USART_ISR_CTS USART_ISR_CTS_Msk

CTS flag

◆ USART_ISR_CTS_Msk

#define USART_ISR_CTS_Msk (0x1UL << USART_ISR_CTS_Pos)

0x00000400

◆ USART_ISR_CTS_Pos

#define USART_ISR_CTS_Pos (10U)

◆ USART_ISR_CTSIF

#define USART_ISR_CTSIF USART_ISR_CTSIF_Msk

CTS interrupt flag

◆ USART_ISR_CTSIF_Msk

#define USART_ISR_CTSIF_Msk (0x1UL << USART_ISR_CTSIF_Pos)

0x00000200

◆ USART_ISR_CTSIF_Pos

#define USART_ISR_CTSIF_Pos (9U)

◆ USART_ISR_EOBF

#define USART_ISR_EOBF USART_ISR_EOBF_Msk

End Of Block Flag

◆ USART_ISR_EOBF_Msk

#define USART_ISR_EOBF_Msk (0x1UL << USART_ISR_EOBF_Pos)

0x00001000

◆ USART_ISR_EOBF_Pos

#define USART_ISR_EOBF_Pos (12U)

◆ USART_ISR_FE

#define USART_ISR_FE USART_ISR_FE_Msk

Framing Error

◆ USART_ISR_FE_Msk

#define USART_ISR_FE_Msk (0x1UL << USART_ISR_FE_Pos)

0x00000002

◆ USART_ISR_FE_Pos

#define USART_ISR_FE_Pos (1U)

◆ USART_ISR_IDLE

#define USART_ISR_IDLE USART_ISR_IDLE_Msk

IDLE line detected

◆ USART_ISR_IDLE_Msk

#define USART_ISR_IDLE_Msk (0x1UL << USART_ISR_IDLE_Pos)

0x00000010

◆ USART_ISR_IDLE_Pos

#define USART_ISR_IDLE_Pos (4U)

◆ USART_ISR_LBDF

#define USART_ISR_LBDF USART_ISR_LBDF_Msk

LIN Break Detection Flag

◆ USART_ISR_LBDF_Msk

#define USART_ISR_LBDF_Msk (0x1UL << USART_ISR_LBDF_Pos)

0x00000100

◆ USART_ISR_LBDF_Pos

#define USART_ISR_LBDF_Pos (8U)

◆ USART_ISR_NE

#define USART_ISR_NE USART_ISR_NE_Msk

Noise detected Flag

◆ USART_ISR_NE_Msk

#define USART_ISR_NE_Msk (0x1UL << USART_ISR_NE_Pos)

0x00000004

◆ USART_ISR_NE_Pos

#define USART_ISR_NE_Pos (2U)

◆ USART_ISR_ORE

#define USART_ISR_ORE USART_ISR_ORE_Msk

OverRun Error

◆ USART_ISR_ORE_Msk

#define USART_ISR_ORE_Msk (0x1UL << USART_ISR_ORE_Pos)

0x00000008

◆ USART_ISR_ORE_Pos

#define USART_ISR_ORE_Pos (3U)

◆ USART_ISR_PE

#define USART_ISR_PE USART_ISR_PE_Msk

Parity Error

◆ USART_ISR_PE_Msk

#define USART_ISR_PE_Msk (0x1UL << USART_ISR_PE_Pos)

0x00000001

◆ USART_ISR_PE_Pos

#define USART_ISR_PE_Pos (0U)

◆ USART_ISR_REACK

#define USART_ISR_REACK USART_ISR_REACK_Msk

Receive Enable Acknowledge Flag

◆ USART_ISR_REACK_Msk

#define USART_ISR_REACK_Msk (0x1UL << USART_ISR_REACK_Pos)

0x00400000

◆ USART_ISR_REACK_Pos

#define USART_ISR_REACK_Pos (22U)

◆ USART_ISR_RTOF

#define USART_ISR_RTOF USART_ISR_RTOF_Msk

Receiver Time Out

◆ USART_ISR_RTOF_Msk

#define USART_ISR_RTOF_Msk (0x1UL << USART_ISR_RTOF_Pos)

0x00000800

◆ USART_ISR_RTOF_Pos

#define USART_ISR_RTOF_Pos (11U)

◆ USART_ISR_RWU

#define USART_ISR_RWU USART_ISR_RWU_Msk

Receive Wake Up from mute mode Flag

◆ USART_ISR_RWU_Msk

#define USART_ISR_RWU_Msk (0x1UL << USART_ISR_RWU_Pos)

0x00080000

◆ USART_ISR_RWU_Pos

#define USART_ISR_RWU_Pos (19U)

◆ USART_ISR_RXNE

#define USART_ISR_RXNE USART_ISR_RXNE_Msk

Read Data Register Not Empty

◆ USART_ISR_RXNE_Msk

#define USART_ISR_RXNE_Msk (0x1UL << USART_ISR_RXNE_Pos)

0x00000020

◆ USART_ISR_RXNE_Pos

#define USART_ISR_RXNE_Pos (5U)

◆ USART_ISR_SBKF

#define USART_ISR_SBKF USART_ISR_SBKF_Msk

Send Break Flag

◆ USART_ISR_SBKF_Msk

#define USART_ISR_SBKF_Msk (0x1UL << USART_ISR_SBKF_Pos)

0x00040000

◆ USART_ISR_SBKF_Pos

#define USART_ISR_SBKF_Pos (18U)

◆ USART_ISR_TC

#define USART_ISR_TC USART_ISR_TC_Msk

Transmission Complete

◆ USART_ISR_TC_Msk

#define USART_ISR_TC_Msk (0x1UL << USART_ISR_TC_Pos)

0x00000040

◆ USART_ISR_TC_Pos

#define USART_ISR_TC_Pos (6U)

◆ USART_ISR_TEACK

#define USART_ISR_TEACK USART_ISR_TEACK_Msk

Transmit Enable Acknowledge Flag

◆ USART_ISR_TEACK_Msk

#define USART_ISR_TEACK_Msk (0x1UL << USART_ISR_TEACK_Pos)

0x00200000

◆ USART_ISR_TEACK_Pos

#define USART_ISR_TEACK_Pos (21U)

◆ USART_ISR_TXE

#define USART_ISR_TXE USART_ISR_TXE_Msk

Transmit Data Register Empty

◆ USART_ISR_TXE_Msk

#define USART_ISR_TXE_Msk (0x1UL << USART_ISR_TXE_Pos)

0x00000080

◆ USART_ISR_TXE_Pos

#define USART_ISR_TXE_Pos (7U)

◆ USART_ISR_WUF

#define USART_ISR_WUF USART_ISR_WUF_Msk

Wake Up from stop mode Flag

◆ USART_ISR_WUF_Msk

#define USART_ISR_WUF_Msk (0x1UL << USART_ISR_WUF_Pos)

0x00100000

◆ USART_ISR_WUF_Pos

#define USART_ISR_WUF_Pos (20U)

◆ USART_RDR_RDR

#define USART_RDR_RDR USART_RDR_RDR_Msk

RDR[8:0] bits (Receive Data value)

◆ USART_RDR_RDR_Msk

#define USART_RDR_RDR_Msk (0x1FFUL << USART_RDR_RDR_Pos)

0x000001FF

◆ USART_RDR_RDR_Pos

#define USART_RDR_RDR_Pos (0U)

◆ USART_RQR_ABRRQ

#define USART_RQR_ABRRQ USART_RQR_ABRRQ_Msk

Auto-Baud Rate Request

◆ USART_RQR_ABRRQ_Msk

#define USART_RQR_ABRRQ_Msk (0x1UL << USART_RQR_ABRRQ_Pos)

0x00000001

◆ USART_RQR_ABRRQ_Pos

#define USART_RQR_ABRRQ_Pos (0U)

◆ USART_RQR_MMRQ

#define USART_RQR_MMRQ USART_RQR_MMRQ_Msk

Mute Mode Request

◆ USART_RQR_MMRQ_Msk

#define USART_RQR_MMRQ_Msk (0x1UL << USART_RQR_MMRQ_Pos)

0x00000004

◆ USART_RQR_MMRQ_Pos

#define USART_RQR_MMRQ_Pos (2U)

◆ USART_RQR_RXFRQ

#define USART_RQR_RXFRQ USART_RQR_RXFRQ_Msk

Receive Data flush Request

◆ USART_RQR_RXFRQ_Msk

#define USART_RQR_RXFRQ_Msk (0x1UL << USART_RQR_RXFRQ_Pos)

0x00000008

◆ USART_RQR_RXFRQ_Pos

#define USART_RQR_RXFRQ_Pos (3U)

◆ USART_RQR_SBKRQ

#define USART_RQR_SBKRQ USART_RQR_SBKRQ_Msk

Send Break Request

◆ USART_RQR_SBKRQ_Msk

#define USART_RQR_SBKRQ_Msk (0x1UL << USART_RQR_SBKRQ_Pos)

0x00000002

◆ USART_RQR_SBKRQ_Pos

#define USART_RQR_SBKRQ_Pos (1U)

◆ USART_RQR_TXFRQ

#define USART_RQR_TXFRQ USART_RQR_TXFRQ_Msk

Transmit data flush Request

◆ USART_RQR_TXFRQ_Msk

#define USART_RQR_TXFRQ_Msk (0x1UL << USART_RQR_TXFRQ_Pos)

0x00000010

◆ USART_RQR_TXFRQ_Pos

#define USART_RQR_TXFRQ_Pos (4U)

◆ USART_RTOR_BLEN

#define USART_RTOR_BLEN USART_RTOR_BLEN_Msk

Block Length

◆ USART_RTOR_BLEN_Msk

#define USART_RTOR_BLEN_Msk (0xFFUL << USART_RTOR_BLEN_Pos)

0xFF000000

◆ USART_RTOR_BLEN_Pos

#define USART_RTOR_BLEN_Pos (24U)

◆ USART_RTOR_RTO

#define USART_RTOR_RTO USART_RTOR_RTO_Msk

Receiver Time Out Value

◆ USART_RTOR_RTO_Msk

#define USART_RTOR_RTO_Msk (0xFFFFFFUL << USART_RTOR_RTO_Pos)

0x00FFFFFF

◆ USART_RTOR_RTO_Pos

#define USART_RTOR_RTO_Pos (0U)

◆ USART_TDR_TDR

#define USART_TDR_TDR USART_TDR_TDR_Msk

TDR[8:0] bits (Transmit Data value)

◆ USART_TDR_TDR_Msk

#define USART_TDR_TDR_Msk (0x1FFUL << USART_TDR_TDR_Pos)

0x000001FF

◆ USART_TDR_TDR_Pos

#define USART_TDR_TDR_Pos (0U)

◆ USB_BTABLE

#define USB_BTABLE (USB_BASE + 0x50U)

Buffer Table address register

◆ USB_CLR_CTR

#define USB_CLR_CTR (~USB_ISTR_CTR)

clear Correct TRansfer bit

◆ USB_CLR_ERR

#define USB_CLR_ERR (~USB_ISTR_ERR)

clear ERRor bit

◆ USB_CLR_ESOF

#define USB_CLR_ESOF (~USB_ISTR_ESOF)

clear Expected Start Of Frame bit

◆ USB_CLR_L1REQ

#define USB_CLR_L1REQ (~USB_ISTR_L1REQ)

clear LPM L1 bit

◆ USB_CLR_PMAOVR

#define USB_CLR_PMAOVR (~USB_ISTR_PMAOVR)

clear DMA OVeR/underrun bit

◆ USB_CLR_PMAOVRM

#define USB_CLR_PMAOVRM USB_CLR_PMAOVR

◆ USB_CLR_RESET

#define USB_CLR_RESET (~USB_ISTR_RESET)

clear RESET bit

◆ USB_CLR_SOF

#define USB_CLR_SOF (~USB_ISTR_SOF)

clear Start Of Frame bit

◆ USB_CLR_SUSP

#define USB_CLR_SUSP (~USB_ISTR_SUSP)

clear SUSPend bit

◆ USB_CLR_WKUP

#define USB_CLR_WKUP (~USB_ISTR_WKUP)

clear WaKe UP bit

◆ USB_CNTR

#define USB_CNTR (USB_BASE + 0x40U)

Control register

◆ USB_CNTR_CTRM

#define USB_CNTR_CTRM ((uint16_t)0x8000U)

Correct TRansfer Mask

◆ USB_CNTR_ERRM

#define USB_CNTR_ERRM ((uint16_t)0x2000U)

ERRor Mask

◆ USB_CNTR_ESOFM

#define USB_CNTR_ESOFM ((uint16_t)0x0100U)

Expected Start Of Frame Mask

◆ USB_CNTR_FRES

#define USB_CNTR_FRES ((uint16_t)0x0001U)

Force USB RESet

◆ USB_CNTR_FSUSP

#define USB_CNTR_FSUSP ((uint16_t)0x0008U)

Force SUSPend

◆ USB_CNTR_L1REQM

#define USB_CNTR_L1REQM ((uint16_t)0x0080U)

LPM L1 state request interrupt mask

◆ USB_CNTR_L1RESUME

#define USB_CNTR_L1RESUME ((uint16_t)0x0020U)

LPM L1 Resume request

◆ USB_CNTR_LP_MODE

#define USB_CNTR_LP_MODE USB_CNTR_LPMODE

◆ USB_CNTR_LPMODE

#define USB_CNTR_LPMODE ((uint16_t)0x0004U)

Low-power MODE

◆ USB_CNTR_PDWN

#define USB_CNTR_PDWN ((uint16_t)0x0002U)

Power DoWN

◆ USB_CNTR_PMAOVR

#define USB_CNTR_PMAOVR ((uint16_t)0x4000U)

DMA OVeR/underrun Mask

◆ USB_CNTR_PMAOVRM

#define USB_CNTR_PMAOVRM USB_CNTR_PMAOVR

◆ USB_CNTR_RESETM

#define USB_CNTR_RESETM ((uint16_t)0x0400U)

RESET Mask

◆ USB_CNTR_RESUME

#define USB_CNTR_RESUME ((uint16_t)0x0010U)

RESUME request

◆ USB_CNTR_SOFM

#define USB_CNTR_SOFM ((uint16_t)0x0200U)

Start Of Frame Mask

◆ USB_CNTR_SUSPM

#define USB_CNTR_SUSPM ((uint16_t)0x0800U)

SUSPend Mask

◆ USB_CNTR_WKUPM

#define USB_CNTR_WKUPM ((uint16_t)0x1000U)

WaKe UP Mask

◆ USB_DADDR

#define USB_DADDR (USB_BASE + 0x4CU)

Device address register

◆ USB_DADDR_ADD

#define USB_DADDR_ADD ((uint8_t)0x7FU)

USB device address

◆ USB_DADDR_EF

#define USB_DADDR_EF ((uint8_t)0x80U)

USB device address Enable Function

◆ USB_EP0R

#define USB_EP0R USB_BASE

endpoint 0 register address

◆ USB_EP1R

#define USB_EP1R (USB_BASE + 0x04U)

endpoint 1 register address

◆ USB_EP2R

#define USB_EP2R (USB_BASE + 0x08U)

endpoint 2 register address

◆ USB_EP3R

#define USB_EP3R (USB_BASE + 0x0CU)

endpoint 3 register address

◆ USB_EP4R

#define USB_EP4R (USB_BASE + 0x10U)

endpoint 4 register address

◆ USB_EP5R

#define USB_EP5R (USB_BASE + 0x14U)

endpoint 5 register address

◆ USB_EP6R

#define USB_EP6R (USB_BASE + 0x18U)

endpoint 6 register address

◆ USB_EP7R

#define USB_EP7R (USB_BASE + 0x1CU)

endpoint 7 register address

◆ USB_EP_BULK

#define USB_EP_BULK ((uint16_t)0x0000U)

EndPoint BULK

◆ USB_EP_CONTROL

#define USB_EP_CONTROL ((uint16_t)0x0200U)

EndPoint CONTROL

◆ USB_EP_CTR_RX

#define USB_EP_CTR_RX ((uint16_t)0x8000U)

EndPoint Correct TRansfer RX

◆ USB_EP_CTR_TX

#define USB_EP_CTR_TX ((uint16_t)0x0080U)

EndPoint Correct TRansfer TX

◆ USB_EP_DTOG_RX

#define USB_EP_DTOG_RX ((uint16_t)0x4000U)

EndPoint Data TOGGLE RX

◆ USB_EP_DTOG_TX

#define USB_EP_DTOG_TX ((uint16_t)0x0040U)

EndPoint Data TOGGLE TX

◆ USB_EP_INTERRUPT

#define USB_EP_INTERRUPT ((uint16_t)0x0600U)

EndPoint INTERRUPT

◆ USB_EP_ISOCHRONOUS

#define USB_EP_ISOCHRONOUS ((uint16_t)0x0400U)

EndPoint ISOCHRONOUS

◆ USB_EP_KIND

#define USB_EP_KIND ((uint16_t)0x0100U)

EndPoint KIND

◆ USB_EP_RX_DIS

#define USB_EP_RX_DIS ((uint16_t)0x0000U)

EndPoint RX DISabled

◆ USB_EP_RX_NAK

#define USB_EP_RX_NAK ((uint16_t)0x2000U)

EndPoint RX NAKed

◆ USB_EP_RX_STALL

#define USB_EP_RX_STALL ((uint16_t)0x1000U)

EndPoint RX STALLed

◆ USB_EP_RX_VALID

#define USB_EP_RX_VALID ((uint16_t)0x3000U)

EndPoint RX VALID

◆ USB_EP_SETUP

#define USB_EP_SETUP ((uint16_t)0x0800U)

EndPoint SETUP

◆ USB_EP_T_FIELD

#define USB_EP_T_FIELD ((uint16_t)0x0600U)

EndPoint TYPE

◆ USB_EP_T_MASK

#define USB_EP_T_MASK ((uint16_t) ~USB_EP_T_FIELD & USB_EPREG_MASK)

◆ USB_EP_TX_DIS

#define USB_EP_TX_DIS ((uint16_t)0x0000U)

EndPoint TX DISabled

◆ USB_EP_TX_NAK

#define USB_EP_TX_NAK ((uint16_t)0x0020U)

EndPoint TX NAKed

◆ USB_EP_TX_STALL

#define USB_EP_TX_STALL ((uint16_t)0x0010U)

EndPoint TX STALLed

◆ USB_EP_TX_VALID

#define USB_EP_TX_VALID ((uint16_t)0x0030U)

EndPoint TX VALID

◆ USB_EP_TYPE_MASK

#define USB_EP_TYPE_MASK ((uint16_t)0x0600U)

EndPoint TYPE Mask

◆ USB_EPADDR_FIELD

#define USB_EPADDR_FIELD ((uint16_t)0x000FU)

EndPoint ADDRess FIELD

◆ USB_EPKIND_MASK

#define USB_EPKIND_MASK ((uint16_t) ~USB_EP_KIND & USB_EPREG_MASK)

EP_KIND EndPoint KIND STAT_TX[1:0] STATus for TX transfer

◆ USB_EPREG_MASK

EP_TYPE[1:0] EndPoint TYPE

◆ USB_EPRX_DTOG1

#define USB_EPRX_DTOG1 ((uint16_t)0x1000U)

EndPoint RX Data TOGgle bit1

◆ USB_EPRX_DTOG2

#define USB_EPRX_DTOG2 ((uint16_t)0x2000U)

EndPoint RX Data TOGgle bit1

◆ USB_EPRX_DTOGMASK

#define USB_EPRX_DTOGMASK (USB_EPRX_STAT|USB_EPREG_MASK)

◆ USB_EPRX_STAT

#define USB_EPRX_STAT ((uint16_t)0x3000U)

EndPoint RX STATus bit field

◆ USB_EPTX_DTOG1

#define USB_EPTX_DTOG1 ((uint16_t)0x0010U)

EndPoint TX Data TOGgle bit1

◆ USB_EPTX_DTOG2

#define USB_EPTX_DTOG2 ((uint16_t)0x0020U)

EndPoint TX Data TOGgle bit2

◆ USB_EPTX_DTOGMASK

#define USB_EPTX_DTOGMASK (USB_EPTX_STAT|USB_EPREG_MASK)

STAT_RX[1:0] STATus for RX transfer

◆ USB_EPTX_STAT

#define USB_EPTX_STAT ((uint16_t)0x0030U)

EndPoint TX STATus bit field

◆ USB_FNR

#define USB_FNR (USB_BASE + 0x48U)

Frame number register

◆ USB_FNR_FN

#define USB_FNR_FN ((uint16_t)0x07FFU)

Frame Number

◆ USB_FNR_LCK

#define USB_FNR_LCK ((uint16_t)0x2000U)

LoCKed

◆ USB_FNR_LSOF

#define USB_FNR_LSOF ((uint16_t)0x1800U)

Lost SOF

◆ USB_FNR_RXDM

#define USB_FNR_RXDM ((uint16_t)0x4000U)

status of D- data line

◆ USB_FNR_RXDP

#define USB_FNR_RXDP ((uint16_t)0x8000U)

status of D+ data line

◆ USB_ISTR

#define USB_ISTR (USB_BASE + 0x44U)

Interrupt status register

◆ USB_ISTR_CTR

#define USB_ISTR_CTR ((uint16_t)0x8000U)

Correct TRansfer (clear-only bit)

◆ USB_ISTR_DIR

#define USB_ISTR_DIR ((uint16_t)0x0010U)

DIRection of transaction (read-only bit)

◆ USB_ISTR_EP_ID

#define USB_ISTR_EP_ID ((uint16_t)0x000FU)

EndPoint IDentifier (read-only bit)

◆ USB_ISTR_ERR

#define USB_ISTR_ERR ((uint16_t)0x2000U)

ERRor (clear-only bit)

◆ USB_ISTR_ESOF

#define USB_ISTR_ESOF ((uint16_t)0x0100U)

Expected Start Of Frame (clear-only bit)

◆ USB_ISTR_L1REQ

#define USB_ISTR_L1REQ ((uint16_t)0x0080U)

LPM L1 state request

◆ USB_ISTR_PMAOVR

#define USB_ISTR_PMAOVR ((uint16_t)0x4000U)

DMA OVeR/underrun (clear-only bit)

◆ USB_ISTR_PMAOVRM

#define USB_ISTR_PMAOVRM USB_ISTR_PMAOVR

◆ USB_ISTR_RESET

#define USB_ISTR_RESET ((uint16_t)0x0400U)

RESET (clear-only bit)

◆ USB_ISTR_SOF

#define USB_ISTR_SOF ((uint16_t)0x0200U)

Start Of Frame (clear-only bit)

◆ USB_ISTR_SUSP

#define USB_ISTR_SUSP ((uint16_t)0x0800U)

SUSPend (clear-only bit)

◆ USB_ISTR_WKUP

#define USB_ISTR_WKUP ((uint16_t)0x1000U)

WaKe UP (clear-only bit)

◆ USB_LPMCSR

#define USB_LPMCSR (USB_BASE + 0x54U)

LPM Control and Status register

◆ USB_LPMCSR_BESL

#define USB_LPMCSR_BESL ((uint16_t)0x00F0U)

BESL value received with last ACKed LPM Token

◆ USB_LPMCSR_LMPEN

#define USB_LPMCSR_LMPEN ((uint16_t)0x0001U)

LPM support enable

◆ USB_LPMCSR_LPMACK

#define USB_LPMCSR_LPMACK ((uint16_t)0x0002U)

LPM Token acknowledge enable

◆ USB_LPMCSR_REMWAKE

#define USB_LPMCSR_REMWAKE ((uint16_t)0x0008U)

bRemoteWake value received with last ACKed LPM Token

◆ WWDG_CFR_EWI

#define WWDG_CFR_EWI WWDG_CFR_EWI_Msk

Early Wakeup Interrupt

◆ WWDG_CFR_EWI_Msk

#define WWDG_CFR_EWI_Msk (0x1UL << WWDG_CFR_EWI_Pos)

0x00000200

◆ WWDG_CFR_EWI_Pos

#define WWDG_CFR_EWI_Pos (9U)

◆ WWDG_CFR_W

#define WWDG_CFR_W WWDG_CFR_W_Msk

W[6:0] bits (7-bit window value)

◆ WWDG_CFR_W0

#define WWDG_CFR_W0 WWDG_CFR_W_0

◆ WWDG_CFR_W1

#define WWDG_CFR_W1 WWDG_CFR_W_1

◆ WWDG_CFR_W2

#define WWDG_CFR_W2 WWDG_CFR_W_2

◆ WWDG_CFR_W3

#define WWDG_CFR_W3 WWDG_CFR_W_3

◆ WWDG_CFR_W4

#define WWDG_CFR_W4 WWDG_CFR_W_4

◆ WWDG_CFR_W5

#define WWDG_CFR_W5 WWDG_CFR_W_5

◆ WWDG_CFR_W6

#define WWDG_CFR_W6 WWDG_CFR_W_6

◆ WWDG_CFR_W_0

#define WWDG_CFR_W_0 (0x01UL << WWDG_CFR_W_Pos)

0x00000001

◆ WWDG_CFR_W_1

#define WWDG_CFR_W_1 (0x02UL << WWDG_CFR_W_Pos)

0x00000002

◆ WWDG_CFR_W_2

#define WWDG_CFR_W_2 (0x04UL << WWDG_CFR_W_Pos)

0x00000004

◆ WWDG_CFR_W_3

#define WWDG_CFR_W_3 (0x08UL << WWDG_CFR_W_Pos)

0x00000008

◆ WWDG_CFR_W_4

#define WWDG_CFR_W_4 (0x10UL << WWDG_CFR_W_Pos)

0x00000010

◆ WWDG_CFR_W_5

#define WWDG_CFR_W_5 (0x20UL << WWDG_CFR_W_Pos)

0x00000020

◆ WWDG_CFR_W_6

#define WWDG_CFR_W_6 (0x40UL << WWDG_CFR_W_Pos)

0x00000040

◆ WWDG_CFR_W_Msk

#define WWDG_CFR_W_Msk (0x7FUL << WWDG_CFR_W_Pos)

0x0000007F

◆ WWDG_CFR_W_Pos

#define WWDG_CFR_W_Pos (0U)

◆ WWDG_CFR_WDGTB

#define WWDG_CFR_WDGTB WWDG_CFR_WDGTB_Msk

WDGTB[1:0] bits (Timer Base)

◆ WWDG_CFR_WDGTB0

#define WWDG_CFR_WDGTB0 WWDG_CFR_WDGTB_0

◆ WWDG_CFR_WDGTB1

#define WWDG_CFR_WDGTB1 WWDG_CFR_WDGTB_1

◆ WWDG_CFR_WDGTB_0

#define WWDG_CFR_WDGTB_0 (0x1UL << WWDG_CFR_WDGTB_Pos)

0x00000080

◆ WWDG_CFR_WDGTB_1

#define WWDG_CFR_WDGTB_1 (0x2UL << WWDG_CFR_WDGTB_Pos)

0x00000100

◆ WWDG_CFR_WDGTB_Msk

#define WWDG_CFR_WDGTB_Msk (0x3UL << WWDG_CFR_WDGTB_Pos)

0x00000180

◆ WWDG_CFR_WDGTB_Pos

#define WWDG_CFR_WDGTB_Pos (7U)

◆ WWDG_CR_T

#define WWDG_CR_T WWDG_CR_T_Msk

T[6:0] bits (7-Bit counter (MSB to LSB))

◆ WWDG_CR_T0

#define WWDG_CR_T0 WWDG_CR_T_0

◆ WWDG_CR_T1

#define WWDG_CR_T1 WWDG_CR_T_1

◆ WWDG_CR_T2

#define WWDG_CR_T2 WWDG_CR_T_2

◆ WWDG_CR_T3

#define WWDG_CR_T3 WWDG_CR_T_3

◆ WWDG_CR_T4

#define WWDG_CR_T4 WWDG_CR_T_4

◆ WWDG_CR_T5

#define WWDG_CR_T5 WWDG_CR_T_5

◆ WWDG_CR_T6

#define WWDG_CR_T6 WWDG_CR_T_6

◆ WWDG_CR_T_0

#define WWDG_CR_T_0 (0x01UL << WWDG_CR_T_Pos)

0x00000001

◆ WWDG_CR_T_1

#define WWDG_CR_T_1 (0x02UL << WWDG_CR_T_Pos)

0x00000002

◆ WWDG_CR_T_2

#define WWDG_CR_T_2 (0x04UL << WWDG_CR_T_Pos)

0x00000004

◆ WWDG_CR_T_3

#define WWDG_CR_T_3 (0x08UL << WWDG_CR_T_Pos)

0x00000008

◆ WWDG_CR_T_4

#define WWDG_CR_T_4 (0x10UL << WWDG_CR_T_Pos)

0x00000010

◆ WWDG_CR_T_5

#define WWDG_CR_T_5 (0x20UL << WWDG_CR_T_Pos)

0x00000020

◆ WWDG_CR_T_6

#define WWDG_CR_T_6 (0x40UL << WWDG_CR_T_Pos)

0x00000040

◆ WWDG_CR_T_Msk

#define WWDG_CR_T_Msk (0x7FUL << WWDG_CR_T_Pos)

0x0000007F

◆ WWDG_CR_T_Pos

#define WWDG_CR_T_Pos (0U)

◆ WWDG_CR_WDGA

#define WWDG_CR_WDGA WWDG_CR_WDGA_Msk

Activation bit

◆ WWDG_CR_WDGA_Msk

#define WWDG_CR_WDGA_Msk (0x1UL << WWDG_CR_WDGA_Pos)

0x00000080

◆ WWDG_CR_WDGA_Pos

#define WWDG_CR_WDGA_Pos (7U)

◆ WWDG_SR_EWIF

#define WWDG_SR_EWIF WWDG_SR_EWIF_Msk

Early Wakeup Interrupt Flag

◆ WWDG_SR_EWIF_Msk

#define WWDG_SR_EWIF_Msk (0x1UL << WWDG_SR_EWIF_Pos)

0x00000001

◆ WWDG_SR_EWIF_Pos

#define WWDG_SR_EWIF_Pos (0U)

Macros

Detailed Description

Macro Definition Documentation

◆ ADC12_CCR_CKMODE

◆ ADC12_CCR_CKMODE_0

◆ ADC12_CCR_CKMODE_1

◆ ADC12_CCR_CKMODE_Msk

◆ ADC12_CCR_CKMODE_Pos

◆ ADC12_CCR_DELAY

◆ ADC12_CCR_DELAY_0

◆ ADC12_CCR_DELAY_1

◆ ADC12_CCR_DELAY_2

◆ ADC12_CCR_DELAY_3

◆ ADC12_CCR_DELAY_Msk

◆ ADC12_CCR_DELAY_Pos

◆ ADC12_CCR_DMACFG

◆ ADC12_CCR_DMACFG_Msk

◆ ADC12_CCR_DMACFG_Pos

◆ ADC12_CCR_MDMA

◆ ADC12_CCR_MDMA_0

◆ ADC12_CCR_MDMA_1

◆ ADC12_CCR_MDMA_Msk

◆ ADC12_CCR_MDMA_Pos

◆ ADC12_CCR_MULTI

◆ ADC12_CCR_MULTI_0

◆ ADC12_CCR_MULTI_1

◆ ADC12_CCR_MULTI_2

◆ ADC12_CCR_MULTI_3

◆ ADC12_CCR_MULTI_4

◆ ADC12_CCR_MULTI_Msk

◆ ADC12_CCR_MULTI_Pos

◆ ADC12_CCR_TSEN

◆ ADC12_CCR_TSEN_Msk

◆ ADC12_CCR_TSEN_Pos

◆ ADC12_CCR_VBATEN

◆ ADC12_CCR_VBATEN_Msk

◆ ADC12_CCR_VBATEN_Pos

◆ ADC12_CCR_VREFEN

◆ ADC12_CCR_VREFEN_Msk

◆ ADC12_CCR_VREFEN_Pos

◆ ADC12_CDR_RDATA_MST

◆ ADC12_CDR_RDATA_MST_0

◆ ADC12_CDR_RDATA_MST_1

◆ ADC12_CDR_RDATA_MST_10

◆ ADC12_CDR_RDATA_MST_11

◆ ADC12_CDR_RDATA_MST_12

◆ ADC12_CDR_RDATA_MST_13

◆ ADC12_CDR_RDATA_MST_14

◆ ADC12_CDR_RDATA_MST_15

◆ ADC12_CDR_RDATA_MST_2

◆ ADC12_CDR_RDATA_MST_3

◆ ADC12_CDR_RDATA_MST_4

◆ ADC12_CDR_RDATA_MST_5

◆ ADC12_CDR_RDATA_MST_6

◆ ADC12_CDR_RDATA_MST_7

◆ ADC12_CDR_RDATA_MST_8

◆ ADC12_CDR_RDATA_MST_9

◆ ADC12_CDR_RDATA_MST_Msk

◆ ADC12_CDR_RDATA_MST_Pos

◆ ADC12_CDR_RDATA_SLV

◆ ADC12_CDR_RDATA_SLV_0

◆ ADC12_CDR_RDATA_SLV_1

◆ ADC12_CDR_RDATA_SLV_10

◆ ADC12_CDR_RDATA_SLV_11

◆ ADC12_CDR_RDATA_SLV_12

◆ ADC12_CDR_RDATA_SLV_13

◆ ADC12_CDR_RDATA_SLV_14

◆ ADC12_CDR_RDATA_SLV_15

◆ ADC12_CDR_RDATA_SLV_2

◆ ADC12_CDR_RDATA_SLV_3

◆ ADC12_CDR_RDATA_SLV_4

◆ ADC12_CDR_RDATA_SLV_5

◆ ADC12_CDR_RDATA_SLV_6

◆ ADC12_CDR_RDATA_SLV_7

◆ ADC12_CDR_RDATA_SLV_8

◆ ADC12_CDR_RDATA_SLV_9

◆ ADC12_CDR_RDATA_SLV_Msk

◆ ADC12_CDR_RDATA_SLV_Pos

◆ ADC12_CSR_ADRDY_EOC_MST

◆ ADC12_CSR_ADRDY_EOC_MST_Msk