AHB Clock Source

Macros
#define	RCC_SYSCLK_DIV1   RCC_CFGR_HPRE_DIV1
#define	RCC_SYSCLK_DIV2   RCC_CFGR_HPRE_DIV2
#define	RCC_SYSCLK_DIV4   RCC_CFGR_HPRE_DIV4
#define	RCC_SYSCLK_DIV8   RCC_CFGR_HPRE_DIV8
#define	RCC_SYSCLK_DIV16   RCC_CFGR_HPRE_DIV16
#define	RCC_SYSCLK_DIV64   RCC_CFGR_HPRE_DIV64
#define	RCC_SYSCLK_DIV128   RCC_CFGR_HPRE_DIV128
#define	RCC_SYSCLK_DIV256   RCC_CFGR_HPRE_DIV256
#define	RCC_SYSCLK_DIV512   RCC_CFGR_HPRE_DIV512

Detailed Description

Macro Definition Documentation

RCC_SYSCLK_DIV1

#define RCC_SYSCLK_DIV1   RCC_CFGR_HPRE_DIV1

SYSCLK not divided

RCC_SYSCLK_DIV128

#define RCC_SYSCLK_DIV128   RCC_CFGR_HPRE_DIV128

SYSCLK divided by 128

RCC_SYSCLK_DIV16

#define RCC_SYSCLK_DIV16   RCC_CFGR_HPRE_DIV16

SYSCLK divided by 16

RCC_SYSCLK_DIV2

#define RCC_SYSCLK_DIV2   RCC_CFGR_HPRE_DIV2

SYSCLK divided by 2

RCC_SYSCLK_DIV256

#define RCC_SYSCLK_DIV256   RCC_CFGR_HPRE_DIV256

SYSCLK divided by 256

RCC_SYSCLK_DIV4

#define RCC_SYSCLK_DIV4   RCC_CFGR_HPRE_DIV4

SYSCLK divided by 4

RCC_SYSCLK_DIV512

#define RCC_SYSCLK_DIV512   RCC_CFGR_HPRE_DIV512

SYSCLK divided by 512

RCC_SYSCLK_DIV64

#define RCC_SYSCLK_DIV64   RCC_CFGR_HPRE_DIV64

SYSCLK divided by 64

RCC_SYSCLK_DIV8

#define RCC_SYSCLK_DIV8   RCC_CFGR_HPRE_DIV8

SYSCLK divided by 8