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APB1 APB2 Clock Source

Macros

#define RCC_HCLK_DIV1   RCC_CFGR_PPRE1_DIV1
 
#define RCC_HCLK_DIV2   RCC_CFGR_PPRE1_DIV2
 
#define RCC_HCLK_DIV4   RCC_CFGR_PPRE1_DIV4
 
#define RCC_HCLK_DIV8   RCC_CFGR_PPRE1_DIV8
 
#define RCC_HCLK_DIV16   RCC_CFGR_PPRE1_DIV16
 

Detailed Description

Macro Definition Documentation

◆ RCC_HCLK_DIV1

#define RCC_HCLK_DIV1   RCC_CFGR_PPRE1_DIV1

HCLK not divided

◆ RCC_HCLK_DIV16

#define RCC_HCLK_DIV16   RCC_CFGR_PPRE1_DIV16

HCLK divided by 16

◆ RCC_HCLK_DIV2

#define RCC_HCLK_DIV2   RCC_CFGR_PPRE1_DIV2

HCLK divided by 2

◆ RCC_HCLK_DIV4

#define RCC_HCLK_DIV4   RCC_CFGR_PPRE1_DIV4

HCLK divided by 4

◆ RCC_HCLK_DIV8

#define RCC_HCLK_DIV8   RCC_CFGR_PPRE1_DIV8

HCLK divided by 8