APB1 Peripheral Clock Enable Disable Status

Get the enable or disable status of the APB1 peripheral clock. More...

Macros
#define	__HAL_RCC_TIM2_IS_CLK_ENABLED()   ((RCC->APB1ENR & (RCC_APB1ENR_TIM2EN)) != RESET)
#define	__HAL_RCC_TIM6_IS_CLK_ENABLED()   ((RCC->APB1ENR & (RCC_APB1ENR_TIM6EN)) != RESET)
#define	__HAL_RCC_WWDG_IS_CLK_ENABLED()   ((RCC->APB1ENR & (RCC_APB1ENR_WWDGEN)) != RESET)
#define	__HAL_RCC_USART2_IS_CLK_ENABLED()   ((RCC->APB1ENR & (RCC_APB1ENR_USART2EN)) != RESET)
#define	__HAL_RCC_USART3_IS_CLK_ENABLED()   ((RCC->APB1ENR & (RCC_APB1ENR_USART3EN)) != RESET)
#define	__HAL_RCC_I2C1_IS_CLK_ENABLED()   ((RCC->APB1ENR & (RCC_APB1ENR_I2C1EN)) != RESET)
#define	__HAL_RCC_PWR_IS_CLK_ENABLED()   ((RCC->APB1ENR & (RCC_APB1ENR_PWREN)) != RESET)
#define	__HAL_RCC_DAC1_IS_CLK_ENABLED()   ((RCC->APB1ENR & (RCC_APB1ENR_DAC1EN)) != RESET)
#define	__HAL_RCC_TIM2_IS_CLK_DISABLED()   ((RCC->APB1ENR & (RCC_APB1ENR_TIM2EN)) == RESET)
#define	__HAL_RCC_TIM6_IS_CLK_DISABLED()   ((RCC->APB1ENR & (RCC_APB1ENR_TIM6EN)) == RESET)
#define	__HAL_RCC_WWDG_IS_CLK_DISABLED()   ((RCC->APB1ENR & (RCC_APB1ENR_WWDGEN)) == RESET)
#define	__HAL_RCC_USART2_IS_CLK_DISABLED()   ((RCC->APB1ENR & (RCC_APB1ENR_USART2EN)) == RESET)
#define	__HAL_RCC_USART3_IS_CLK_DISABLED()   ((RCC->APB1ENR & (RCC_APB1ENR_USART3EN)) == RESET)
#define	__HAL_RCC_I2C1_IS_CLK_DISABLED()   ((RCC->APB1ENR & (RCC_APB1ENR_I2C1EN)) == RESET)
#define	__HAL_RCC_PWR_IS_CLK_DISABLED()   ((RCC->APB1ENR & (RCC_APB1ENR_PWREN)) == RESET)
#define	__HAL_RCC_DAC1_IS_CLK_DISABLED()   ((RCC->APB1ENR & (RCC_APB1ENR_DAC1EN)) == RESET)

Detailed Description

Get the enable or disable status of the APB1 peripheral clock.

Note

After reset, the peripheral clock (used for registers read/write access) is disabled and the application software has to enable this clock before using it.

Macro Definition Documentation

__HAL_RCC_DAC1_IS_CLK_DISABLED

#define __HAL_RCC_DAC1_IS_CLK_DISABLED

(

)

((RCC->APB1ENR & (RCC_APB1ENR_DAC1EN)) == RESET)

__HAL_RCC_DAC1_IS_CLK_ENABLED

#define __HAL_RCC_DAC1_IS_CLK_ENABLED

(

)

((RCC->APB1ENR & (RCC_APB1ENR_DAC1EN)) != RESET)

__HAL_RCC_I2C1_IS_CLK_DISABLED

#define __HAL_RCC_I2C1_IS_CLK_DISABLED

(

)

((RCC->APB1ENR & (RCC_APB1ENR_I2C1EN)) == RESET)

__HAL_RCC_I2C1_IS_CLK_ENABLED

#define __HAL_RCC_I2C1_IS_CLK_ENABLED

(

)

((RCC->APB1ENR & (RCC_APB1ENR_I2C1EN)) != RESET)

__HAL_RCC_PWR_IS_CLK_DISABLED

#define __HAL_RCC_PWR_IS_CLK_DISABLED

(

)

((RCC->APB1ENR & (RCC_APB1ENR_PWREN)) == RESET)

__HAL_RCC_PWR_IS_CLK_ENABLED

#define __HAL_RCC_PWR_IS_CLK_ENABLED

(

)

((RCC->APB1ENR & (RCC_APB1ENR_PWREN)) != RESET)

__HAL_RCC_TIM2_IS_CLK_DISABLED

#define __HAL_RCC_TIM2_IS_CLK_DISABLED

(

)

((RCC->APB1ENR & (RCC_APB1ENR_TIM2EN)) == RESET)

__HAL_RCC_TIM2_IS_CLK_ENABLED

#define __HAL_RCC_TIM2_IS_CLK_ENABLED

(

)

((RCC->APB1ENR & (RCC_APB1ENR_TIM2EN)) != RESET)

__HAL_RCC_TIM6_IS_CLK_DISABLED

#define __HAL_RCC_TIM6_IS_CLK_DISABLED

(

)

((RCC->APB1ENR & (RCC_APB1ENR_TIM6EN)) == RESET)

__HAL_RCC_TIM6_IS_CLK_ENABLED

#define __HAL_RCC_TIM6_IS_CLK_ENABLED

(

)

((RCC->APB1ENR & (RCC_APB1ENR_TIM6EN)) != RESET)

__HAL_RCC_USART2_IS_CLK_DISABLED

#define __HAL_RCC_USART2_IS_CLK_DISABLED

(

)

((RCC->APB1ENR & (RCC_APB1ENR_USART2EN)) == RESET)

__HAL_RCC_USART2_IS_CLK_ENABLED

#define __HAL_RCC_USART2_IS_CLK_ENABLED

(

)

((RCC->APB1ENR & (RCC_APB1ENR_USART2EN)) != RESET)

__HAL_RCC_USART3_IS_CLK_DISABLED

#define __HAL_RCC_USART3_IS_CLK_DISABLED

(

)

((RCC->APB1ENR & (RCC_APB1ENR_USART3EN)) == RESET)

__HAL_RCC_USART3_IS_CLK_ENABLED

#define __HAL_RCC_USART3_IS_CLK_ENABLED

(

)

((RCC->APB1ENR & (RCC_APB1ENR_USART3EN)) != RESET)

__HAL_RCC_WWDG_IS_CLK_DISABLED

#define __HAL_RCC_WWDG_IS_CLK_DISABLED

(

)

((RCC->APB1ENR & (RCC_APB1ENR_WWDGEN)) == RESET)

__HAL_RCC_WWDG_IS_CLK_ENABLED

#define __HAL_RCC_WWDG_IS_CLK_ENABLED

(

)

((RCC->APB1ENR & (RCC_APB1ENR_WWDGEN)) != RESET)