CTPulse Low Length

Macros
#define	TSC_CTPL_1CYCLE   0x00000000UL
#define	TSC_CTPL_2CYCLES   TSC_CR_CTPL_0
#define	TSC_CTPL_3CYCLES   TSC_CR_CTPL_1
#define	TSC_CTPL_4CYCLES   (TSC_CR_CTPL_1 | TSC_CR_CTPL_0)
#define	TSC_CTPL_5CYCLES   TSC_CR_CTPL_2
#define	TSC_CTPL_6CYCLES   (TSC_CR_CTPL_2 | TSC_CR_CTPL_0)
#define	TSC_CTPL_7CYCLES   (TSC_CR_CTPL_2 | TSC_CR_CTPL_1)
#define	TSC_CTPL_8CYCLES   (TSC_CR_CTPL_2 | TSC_CR_CTPL_1 | TSC_CR_CTPL_0)
#define	TSC_CTPL_9CYCLES   TSC_CR_CTPL_3
#define	TSC_CTPL_10CYCLES   (TSC_CR_CTPL_3 | TSC_CR_CTPL_0)
#define	TSC_CTPL_11CYCLES   (TSC_CR_CTPL_3 | TSC_CR_CTPL_1)
#define	TSC_CTPL_12CYCLES   (TSC_CR_CTPL_3 | TSC_CR_CTPL_1 | TSC_CR_CTPL_0)
#define	TSC_CTPL_13CYCLES   (TSC_CR_CTPL_3 | TSC_CR_CTPL_2)
#define	TSC_CTPL_14CYCLES   (TSC_CR_CTPL_3 | TSC_CR_CTPL_2 | TSC_CR_CTPL_0)
#define	TSC_CTPL_15CYCLES   (TSC_CR_CTPL_3 | TSC_CR_CTPL_2 | TSC_CR_CTPL_1)
#define	TSC_CTPL_16CYCLES   (TSC_CR_CTPL_3 | TSC_CR_CTPL_2 | TSC_CR_CTPL_1 | TSC_CR_CTPL_0)

Detailed Description

Macro Definition Documentation

TSC_CTPL_10CYCLES

#define TSC_CTPL_10CYCLES   (TSC_CR_CTPL_3 | TSC_CR_CTPL_0)

Charge transfer pulse low during 10 cycles (PGCLK)

TSC_CTPL_11CYCLES

#define TSC_CTPL_11CYCLES   (TSC_CR_CTPL_3 | TSC_CR_CTPL_1)

Charge transfer pulse low during 11 cycles (PGCLK)

TSC_CTPL_12CYCLES

#define TSC_CTPL_12CYCLES   (TSC_CR_CTPL_3 | TSC_CR_CTPL_1 | TSC_CR_CTPL_0)

Charge transfer pulse low during 12 cycles (PGCLK)

TSC_CTPL_13CYCLES

#define TSC_CTPL_13CYCLES   (TSC_CR_CTPL_3 | TSC_CR_CTPL_2)

Charge transfer pulse low during 13 cycles (PGCLK)

TSC_CTPL_14CYCLES

#define TSC_CTPL_14CYCLES   (TSC_CR_CTPL_3 | TSC_CR_CTPL_2 | TSC_CR_CTPL_0)

Charge transfer pulse low during 14 cycles (PGCLK)

TSC_CTPL_15CYCLES

#define TSC_CTPL_15CYCLES   (TSC_CR_CTPL_3 | TSC_CR_CTPL_2 | TSC_CR_CTPL_1)

Charge transfer pulse low during 15 cycles (PGCLK)

TSC_CTPL_16CYCLES

#define TSC_CTPL_16CYCLES   (TSC_CR_CTPL_3 | TSC_CR_CTPL_2 | TSC_CR_CTPL_1 | TSC_CR_CTPL_0)

Charge transfer pulse low during 16 cycles (PGCLK)

TSC_CTPL_1CYCLE

#define TSC_CTPL_1CYCLE   0x00000000UL

Charge transfer pulse low during 1 cycle (PGCLK)

TSC_CTPL_2CYCLES

#define TSC_CTPL_2CYCLES   TSC_CR_CTPL_0

Charge transfer pulse low during 2 cycles (PGCLK)

TSC_CTPL_3CYCLES

#define TSC_CTPL_3CYCLES   TSC_CR_CTPL_1

Charge transfer pulse low during 3 cycles (PGCLK)

TSC_CTPL_4CYCLES

#define TSC_CTPL_4CYCLES   (TSC_CR_CTPL_1 | TSC_CR_CTPL_0)

Charge transfer pulse low during 4 cycles (PGCLK)

TSC_CTPL_5CYCLES

#define TSC_CTPL_5CYCLES   TSC_CR_CTPL_2

Charge transfer pulse low during 5 cycles (PGCLK)

TSC_CTPL_6CYCLES

#define TSC_CTPL_6CYCLES   (TSC_CR_CTPL_2 | TSC_CR_CTPL_0)

Charge transfer pulse low during 6 cycles (PGCLK)

TSC_CTPL_7CYCLES

#define TSC_CTPL_7CYCLES   (TSC_CR_CTPL_2 | TSC_CR_CTPL_1)

Charge transfer pulse low during 7 cycles (PGCLK)

TSC_CTPL_8CYCLES

#define TSC_CTPL_8CYCLES   (TSC_CR_CTPL_2 | TSC_CR_CTPL_1 | TSC_CR_CTPL_0)

Charge transfer pulse low during 8 cycles (PGCLK)

TSC_CTPL_9CYCLES

#define TSC_CTPL_9CYCLES   TSC_CR_CTPL_3

Charge transfer pulse low during 9 cycles (PGCLK)