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stm32f3xx_hal_rcc_ex.h
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1
18/* Define to prevent recursive inclusion -------------------------------------*/
19#ifndef __STM32F3xx_HAL_RCC_EX_H
20#define __STM32F3xx_HAL_RCC_EX_H
21
22#ifdef __cplusplus
23 extern "C" {
24#endif
25
26/* Includes ------------------------------------------------------------------*/
27#include "stm32f3xx_hal_def.h"
28
41#if defined(RCC_CFGR_PLLNODIV)
42#define IS_RCC_MCO1SOURCE(SOURCE) (((SOURCE) == RCC_MCO1SOURCE_NOCLOCK) || \
43 ((SOURCE) == RCC_MCO1SOURCE_LSI) || \
44 ((SOURCE) == RCC_MCO1SOURCE_LSE) || \
45 ((SOURCE) == RCC_MCO1SOURCE_SYSCLK) || \
46 ((SOURCE) == RCC_MCO1SOURCE_HSI) || \
47 ((SOURCE) == RCC_MCO1SOURCE_HSE) || \
48 ((SOURCE) == RCC_MCO1SOURCE_PLLCLK) || \
49 ((SOURCE) == RCC_MCO1SOURCE_PLLCLK_DIV2))
50#else
51#define IS_RCC_MCO1SOURCE(SOURCE) (((SOURCE) == RCC_MCO1SOURCE_NOCLOCK) || \
52 ((SOURCE) == RCC_MCO1SOURCE_LSI) || \
53 ((SOURCE) == RCC_MCO1SOURCE_LSE) || \
54 ((SOURCE) == RCC_MCO1SOURCE_SYSCLK) || \
55 ((SOURCE) == RCC_MCO1SOURCE_HSI) || \
56 ((SOURCE) == RCC_MCO1SOURCE_HSE) || \
57 ((SOURCE) == RCC_MCO1SOURCE_PLLCLK_DIV2))
58#endif /* RCC_CFGR_PLLNODIV */
59
60#if defined(STM32F301x8) || defined(STM32F318xx)
61#define IS_RCC_PERIPHCLOCK(SELECTION) ((SELECTION) <= (RCC_PERIPHCLK_USART1 | \
62 RCC_PERIPHCLK_I2C1 | RCC_PERIPHCLK_I2C2 | \
63 RCC_PERIPHCLK_ADC1 | RCC_PERIPHCLK_I2S | \
64 RCC_PERIPHCLK_I2C3 | RCC_PERIPHCLK_TIM1 | \
65 RCC_PERIPHCLK_TIM15 | RCC_PERIPHCLK_TIM16 | \
66 RCC_PERIPHCLK_TIM17 | RCC_PERIPHCLK_RTC))
67#endif /* STM32F301x8 || STM32F318xx */
68#if defined(STM32F302x8)
69#define IS_RCC_PERIPHCLOCK(SELECTION) ((SELECTION) <= (RCC_PERIPHCLK_USART1 | \
70 RCC_PERIPHCLK_I2C1 | RCC_PERIPHCLK_I2C2 | \
71 RCC_PERIPHCLK_ADC1 | RCC_PERIPHCLK_I2S | \
72 RCC_PERIPHCLK_I2C3 | RCC_PERIPHCLK_TIM1 | \
73 RCC_PERIPHCLK_RTC | RCC_PERIPHCLK_USB | \
74 RCC_PERIPHCLK_TIM15 | RCC_PERIPHCLK_TIM16 | \
75 RCC_PERIPHCLK_TIM17))
76#endif /* STM32F302x8 */
77#if defined(STM32F302xC)
78#define IS_RCC_PERIPHCLOCK(SELECTION) ((SELECTION) <= (RCC_PERIPHCLK_USART1 | RCC_PERIPHCLK_USART2 | RCC_PERIPHCLK_USART3 | \
79 RCC_PERIPHCLK_UART4 | RCC_PERIPHCLK_UART5 | \
80 RCC_PERIPHCLK_I2C1 | RCC_PERIPHCLK_I2C2 | \
81 RCC_PERIPHCLK_ADC12 | RCC_PERIPHCLK_I2S | \
82 RCC_PERIPHCLK_TIM1 | RCC_PERIPHCLK_RTC | \
83 RCC_PERIPHCLK_USB))
84#endif /* STM32F302xC */
85#if defined(STM32F303xC)
86#define IS_RCC_PERIPHCLOCK(SELECTION) ((SELECTION) <= (RCC_PERIPHCLK_USART1 | RCC_PERIPHCLK_USART2 | RCC_PERIPHCLK_USART3 | \
87 RCC_PERIPHCLK_UART4 | RCC_PERIPHCLK_UART5 | \
88 RCC_PERIPHCLK_I2C1 | RCC_PERIPHCLK_I2C2 | \
89 RCC_PERIPHCLK_ADC12 | RCC_PERIPHCLK_ADC34 | \
90 RCC_PERIPHCLK_I2S | RCC_PERIPHCLK_TIM1 | \
91 RCC_PERIPHCLK_TIM8 | RCC_PERIPHCLK_RTC | \
92 RCC_PERIPHCLK_USB))
93#endif /* STM32F303xC */
94#if defined(STM32F302xE)
95#define IS_RCC_PERIPHCLOCK(SELECTION) ((SELECTION) <= (RCC_PERIPHCLK_USART1 | RCC_PERIPHCLK_USART2 | RCC_PERIPHCLK_USART3 | \
96 RCC_PERIPHCLK_UART4 | RCC_PERIPHCLK_UART5 | \
97 RCC_PERIPHCLK_I2C1 | RCC_PERIPHCLK_I2C2 | \
98 RCC_PERIPHCLK_ADC12 | RCC_PERIPHCLK_I2S | \
99 RCC_PERIPHCLK_TIM1 | RCC_PERIPHCLK_RTC | \
100 RCC_PERIPHCLK_USB | RCC_PERIPHCLK_I2C3 | \
101 RCC_PERIPHCLK_TIM2 | RCC_PERIPHCLK_TIM34 | \
102 RCC_PERIPHCLK_TIM15 | RCC_PERIPHCLK_TIM16 | \
103 RCC_PERIPHCLK_TIM17))
104#endif /* STM32F302xE */
105#if defined(STM32F303xE)
106#define IS_RCC_PERIPHCLOCK(SELECTION) ((SELECTION) <= (RCC_PERIPHCLK_USART1 | RCC_PERIPHCLK_USART2 | RCC_PERIPHCLK_USART3 | \
107 RCC_PERIPHCLK_UART4 | RCC_PERIPHCLK_UART5 | \
108 RCC_PERIPHCLK_I2C1 | RCC_PERIPHCLK_I2C2 | \
109 RCC_PERIPHCLK_ADC12 | RCC_PERIPHCLK_ADC34 | \
110 RCC_PERIPHCLK_I2S | RCC_PERIPHCLK_TIM1 | \
111 RCC_PERIPHCLK_TIM8 | RCC_PERIPHCLK_RTC | \
112 RCC_PERIPHCLK_USB | RCC_PERIPHCLK_I2C3 | \
113 RCC_PERIPHCLK_TIM2 | RCC_PERIPHCLK_TIM34 | \
114 RCC_PERIPHCLK_TIM15 | RCC_PERIPHCLK_TIM16 | \
115 RCC_PERIPHCLK_TIM17 | RCC_PERIPHCLK_TIM20))
116#endif /* STM32F303xE */
117#if defined(STM32F398xx)
118#define IS_RCC_PERIPHCLOCK(SELECTION) ((SELECTION) <= (RCC_PERIPHCLK_USART1 | RCC_PERIPHCLK_USART2 | RCC_PERIPHCLK_USART3 | \
119 RCC_PERIPHCLK_UART4 | RCC_PERIPHCLK_UART5 | \
120 RCC_PERIPHCLK_I2C1 | RCC_PERIPHCLK_I2C2 | \
121 RCC_PERIPHCLK_ADC12 | RCC_PERIPHCLK_ADC34 | \
122 RCC_PERIPHCLK_I2S | RCC_PERIPHCLK_TIM1 | \
123 RCC_PERIPHCLK_TIM8 | RCC_PERIPHCLK_RTC | \
124 RCC_PERIPHCLK_I2C3 | RCC_PERIPHCLK_TIM2 | \
125 RCC_PERIPHCLK_TIM34 | RCC_PERIPHCLK_TIM15 | \
126 RCC_PERIPHCLK_TIM16 | RCC_PERIPHCLK_TIM17 | \
127 RCC_PERIPHCLK_TIM20))
128#endif /* STM32F398xx */
129#if defined(STM32F358xx)
130#define IS_RCC_PERIPHCLOCK(SELECTION) ((SELECTION) <= (RCC_PERIPHCLK_USART1 | RCC_PERIPHCLK_USART2 | RCC_PERIPHCLK_USART3 | \
131 RCC_PERIPHCLK_UART4 | RCC_PERIPHCLK_UART5 | \
132 RCC_PERIPHCLK_I2C1 | RCC_PERIPHCLK_I2C2 | \
133 RCC_PERIPHCLK_ADC12 | RCC_PERIPHCLK_ADC34 | \
134 RCC_PERIPHCLK_I2S | RCC_PERIPHCLK_TIM1 | \
135 RCC_PERIPHCLK_TIM8 | RCC_PERIPHCLK_RTC))
136#endif /* STM32F358xx */
137#if defined(STM32F303x8)
138#define IS_RCC_PERIPHCLOCK(SELECTION) ((SELECTION) <= (RCC_PERIPHCLK_USART1 | \
139 RCC_PERIPHCLK_I2C1 | RCC_PERIPHCLK_ADC12 | \
140 RCC_PERIPHCLK_TIM1 | RCC_PERIPHCLK_RTC))
141#endif /* STM32F303x8 */
142#if defined(STM32F334x8)
143#define IS_RCC_PERIPHCLOCK(SELECTION) ((SELECTION) <= (RCC_PERIPHCLK_USART1 | \
144 RCC_PERIPHCLK_I2C1 | RCC_PERIPHCLK_ADC12 | \
145 RCC_PERIPHCLK_TIM1 | RCC_PERIPHCLK_HRTIM1 | \
146 RCC_PERIPHCLK_RTC))
147#endif /* STM32F334x8 */
148#if defined(STM32F328xx)
149#define IS_RCC_PERIPHCLOCK(SELECTION) ((SELECTION) <= (RCC_PERIPHCLK_USART1 | \
150 RCC_PERIPHCLK_I2C1 | RCC_PERIPHCLK_ADC12 | \
151 RCC_PERIPHCLK_TIM1 | RCC_PERIPHCLK_RTC))
152#endif /* STM32F328xx */
153#if defined(STM32F373xC)
154#define IS_RCC_PERIPHCLOCK(SELECTION) ((SELECTION) <= (RCC_PERIPHCLK_USART1 | RCC_PERIPHCLK_USART2 | RCC_PERIPHCLK_USART3 | \
155 RCC_PERIPHCLK_I2C1 | RCC_PERIPHCLK_I2C2 | \
156 RCC_PERIPHCLK_ADC1 | RCC_PERIPHCLK_SDADC | \
157 RCC_PERIPHCLK_CEC | RCC_PERIPHCLK_RTC | \
158 RCC_PERIPHCLK_USB))
159#endif /* STM32F373xC */
160#if defined(STM32F378xx)
161#define IS_RCC_PERIPHCLOCK(SELECTION) ((SELECTION) <= (RCC_PERIPHCLK_USART1 | RCC_PERIPHCLK_USART2 | RCC_PERIPHCLK_USART3 | \
162 RCC_PERIPHCLK_I2C1 | RCC_PERIPHCLK_I2C2 | \
163 RCC_PERIPHCLK_ADC1 | RCC_PERIPHCLK_SDADC | \
164 RCC_PERIPHCLK_CEC | RCC_PERIPHCLK_RTC))
165#endif /* STM32F378xx */
166
167#if defined(STM32F301x8) || defined(STM32F302x8) || defined(STM32F318xx)
168#define IS_RCC_USART1CLKSOURCE(SOURCE) (((SOURCE) == RCC_USART1CLKSOURCE_PCLK1) || \
169 ((SOURCE) == RCC_USART1CLKSOURCE_SYSCLK) || \
170 ((SOURCE) == RCC_USART1CLKSOURCE_LSE) || \
171 ((SOURCE) == RCC_USART1CLKSOURCE_HSI))
172#define IS_RCC_I2C2CLKSOURCE(SOURCE) (((SOURCE) == RCC_I2C2CLKSOURCE_HSI) || \
173 ((SOURCE) == RCC_I2C2CLKSOURCE_SYSCLK))
174#define IS_RCC_I2C3CLKSOURCE(SOURCE) (((SOURCE) == RCC_I2C3CLKSOURCE_HSI) || \
175 ((SOURCE) == RCC_I2C3CLKSOURCE_SYSCLK))
176#define IS_RCC_ADC1PLLCLK_DIV(ADCCLK) (((ADCCLK) == RCC_ADC1PLLCLK_OFF) || ((ADCCLK) == RCC_ADC1PLLCLK_DIV1) || \
177 ((ADCCLK) == RCC_ADC1PLLCLK_DIV2) || ((ADCCLK) == RCC_ADC1PLLCLK_DIV4) || \
178 ((ADCCLK) == RCC_ADC1PLLCLK_DIV6) || ((ADCCLK) == RCC_ADC1PLLCLK_DIV8) || \
179 ((ADCCLK) == RCC_ADC1PLLCLK_DIV10) || ((ADCCLK) == RCC_ADC1PLLCLK_DIV12) || \
180 ((ADCCLK) == RCC_ADC1PLLCLK_DIV16) || ((ADCCLK) == RCC_ADC1PLLCLK_DIV32) || \
181 ((ADCCLK) == RCC_ADC1PLLCLK_DIV64) || ((ADCCLK) == RCC_ADC1PLLCLK_DIV128) || \
182 ((ADCCLK) == RCC_ADC1PLLCLK_DIV256))
183#define IS_RCC_I2SCLKSOURCE(SOURCE) (((SOURCE) == RCC_I2SCLKSOURCE_SYSCLK) || \
184 ((SOURCE) == RCC_I2SCLKSOURCE_EXT))
185#define IS_RCC_TIM1CLKSOURCE(SOURCE) (((SOURCE) == RCC_TIM1CLK_HCLK) || \
186 ((SOURCE) == RCC_TIM1CLK_PLLCLK))
187#define IS_RCC_TIM15CLKSOURCE(SOURCE) (((SOURCE) == RCC_TIM15CLK_HCLK) || \
188 ((SOURCE) == RCC_TIM15CLK_PLLCLK))
189#define IS_RCC_TIM16CLKSOURCE(SOURCE) (((SOURCE) == RCC_TIM16CLK_HCLK) || \
190 ((SOURCE) == RCC_TIM16CLK_PLLCLK))
191#define IS_RCC_TIM17CLKSOURCE(SOURCE) (((SOURCE) == RCC_TIM17CLK_HCLK) || \
192 ((SOURCE) == RCC_TIM17CLK_PLLCLK))
193#endif /* STM32F301x8 || STM32F302x8 || STM32F318xx */
194#if defined(STM32F302xC) || defined(STM32F303xC) || defined(STM32F358xx)
195#define IS_RCC_USART1CLKSOURCE(SOURCE) (((SOURCE) == RCC_USART1CLKSOURCE_PCLK2) || \
196 ((SOURCE) == RCC_USART1CLKSOURCE_SYSCLK) || \
197 ((SOURCE) == RCC_USART1CLKSOURCE_LSE) || \
198 ((SOURCE) == RCC_USART1CLKSOURCE_HSI))
199#define IS_RCC_I2C2CLKSOURCE(SOURCE) (((SOURCE) == RCC_I2C2CLKSOURCE_HSI) || \
200 ((SOURCE) == RCC_I2C2CLKSOURCE_SYSCLK))
201#define IS_RCC_ADC12PLLCLK_DIV(ADCCLK) (((ADCCLK) == RCC_ADC12PLLCLK_OFF) || ((ADCCLK) == RCC_ADC12PLLCLK_DIV1) || \
202 ((ADCCLK) == RCC_ADC12PLLCLK_DIV2) || ((ADCCLK) == RCC_ADC12PLLCLK_DIV4) || \
203 ((ADCCLK) == RCC_ADC12PLLCLK_DIV6) || ((ADCCLK) == RCC_ADC12PLLCLK_DIV8) || \
204 ((ADCCLK) == RCC_ADC12PLLCLK_DIV10) || ((ADCCLK) == RCC_ADC12PLLCLK_DIV12) || \
205 ((ADCCLK) == RCC_ADC12PLLCLK_DIV16) || ((ADCCLK) == RCC_ADC12PLLCLK_DIV32) || \
206 ((ADCCLK) == RCC_ADC12PLLCLK_DIV64) || ((ADCCLK) == RCC_ADC12PLLCLK_DIV128) || \
207 ((ADCCLK) == RCC_ADC12PLLCLK_DIV256))
208#define IS_RCC_I2SCLKSOURCE(SOURCE) (((SOURCE) == RCC_I2SCLKSOURCE_SYSCLK) || \
209 ((SOURCE) == RCC_I2SCLKSOURCE_EXT))
210#define IS_RCC_TIM1CLKSOURCE(SOURCE) (((SOURCE) == RCC_TIM1CLK_HCLK) || \
211 ((SOURCE) == RCC_TIM1CLK_PLLCLK))
212#define IS_RCC_UART4CLKSOURCE(SOURCE) (((SOURCE) == RCC_UART4CLKSOURCE_PCLK1) || \
213 ((SOURCE) == RCC_UART4CLKSOURCE_SYSCLK) || \
214 ((SOURCE) == RCC_UART4CLKSOURCE_LSE) || \
215 ((SOURCE) == RCC_UART4CLKSOURCE_HSI))
216#define IS_RCC_UART5CLKSOURCE(SOURCE) (((SOURCE) == RCC_UART5CLKSOURCE_PCLK1) || \
217 ((SOURCE) == RCC_UART5CLKSOURCE_SYSCLK) || \
218 ((SOURCE) == RCC_UART5CLKSOURCE_LSE) || \
219 ((SOURCE) == RCC_UART5CLKSOURCE_HSI))
220#endif /* STM32F302xC || STM32F303xC || STM32F358xx */
221#if defined(STM32F302xE) || defined(STM32F303xE) || defined(STM32F398xx)
222#define IS_RCC_USART1CLKSOURCE(SOURCE) (((SOURCE) == RCC_USART1CLKSOURCE_PCLK2) || \
223 ((SOURCE) == RCC_USART1CLKSOURCE_SYSCLK) || \
224 ((SOURCE) == RCC_USART1CLKSOURCE_LSE) || \
225 ((SOURCE) == RCC_USART1CLKSOURCE_HSI))
226#define IS_RCC_I2C2CLKSOURCE(SOURCE) (((SOURCE) == RCC_I2C2CLKSOURCE_HSI) || \
227 ((SOURCE) == RCC_I2C2CLKSOURCE_SYSCLK))
228#define IS_RCC_I2C3CLKSOURCE(SOURCE) (((SOURCE) == RCC_I2C3CLKSOURCE_HSI) || \
229 ((SOURCE) == RCC_I2C3CLKSOURCE_SYSCLK))
230#define IS_RCC_ADC12PLLCLK_DIV(ADCCLK) (((ADCCLK) == RCC_ADC12PLLCLK_OFF) || ((ADCCLK) == RCC_ADC12PLLCLK_DIV1) || \
231 ((ADCCLK) == RCC_ADC12PLLCLK_DIV2) || ((ADCCLK) == RCC_ADC12PLLCLK_DIV4) || \
232 ((ADCCLK) == RCC_ADC12PLLCLK_DIV6) || ((ADCCLK) == RCC_ADC12PLLCLK_DIV8) || \
233 ((ADCCLK) == RCC_ADC12PLLCLK_DIV10) || ((ADCCLK) == RCC_ADC12PLLCLK_DIV12) || \
234 ((ADCCLK) == RCC_ADC12PLLCLK_DIV16) || ((ADCCLK) == RCC_ADC12PLLCLK_DIV32) || \
235 ((ADCCLK) == RCC_ADC12PLLCLK_DIV64) || ((ADCCLK) == RCC_ADC12PLLCLK_DIV128) || \
236 ((ADCCLK) == RCC_ADC12PLLCLK_DIV256))
237#define IS_RCC_I2SCLKSOURCE(SOURCE) (((SOURCE) == RCC_I2SCLKSOURCE_SYSCLK) || \
238 ((SOURCE) == RCC_I2SCLKSOURCE_EXT))
239#define IS_RCC_TIM1CLKSOURCE(SOURCE) (((SOURCE) == RCC_TIM1CLK_HCLK) || \
240 ((SOURCE) == RCC_TIM1CLK_PLLCLK))
241#define IS_RCC_TIM2CLKSOURCE(SOURCE) (((SOURCE) == RCC_TIM2CLK_HCLK) || \
242 ((SOURCE) == RCC_TIM2CLK_PLLCLK))
243#define IS_RCC_TIM3CLKSOURCE(SOURCE) (((SOURCE) == RCC_TIM34CLK_HCLK) || \
244 ((SOURCE) == RCC_TIM34CLK_PLLCLK))
245#define IS_RCC_TIM15CLKSOURCE(SOURCE) (((SOURCE) == RCC_TIM15CLK_HCLK) || \
246 ((SOURCE) == RCC_TIM15CLK_PLLCLK))
247#define IS_RCC_TIM16CLKSOURCE(SOURCE) (((SOURCE) == RCC_TIM16CLK_HCLK) || \
248 ((SOURCE) == RCC_TIM16CLK_PLLCLK))
249#define IS_RCC_TIM17CLKSOURCE(SOURCE) (((SOURCE) == RCC_TIM17CLK_HCLK) || \
250 ((SOURCE) == RCC_TIM17CLK_PLLCLK))
251#define IS_RCC_UART4CLKSOURCE(SOURCE) (((SOURCE) == RCC_UART4CLKSOURCE_PCLK1) || \
252 ((SOURCE) == RCC_UART4CLKSOURCE_SYSCLK) || \
253 ((SOURCE) == RCC_UART4CLKSOURCE_LSE) || \
254 ((SOURCE) == RCC_UART4CLKSOURCE_HSI))
255#define IS_RCC_UART5CLKSOURCE(SOURCE) (((SOURCE) == RCC_UART5CLKSOURCE_PCLK1) || \
256 ((SOURCE) == RCC_UART5CLKSOURCE_SYSCLK) || \
257 ((SOURCE) == RCC_UART5CLKSOURCE_LSE) || \
258 ((SOURCE) == RCC_UART5CLKSOURCE_HSI))
259#endif /* STM32F302xE || STM32F303xE || STM32F398xx */
260#if defined(STM32F303xE) || defined(STM32F398xx)
261#define IS_RCC_TIM20CLKSOURCE(SOURCE) (((SOURCE) == RCC_TIM20CLK_HCLK) || \
262 ((SOURCE) == RCC_TIM20CLK_PLLCLK))
263#endif /* STM32F303xE || STM32F398xx */
264#if defined(STM32F303xE) || defined(STM32F398xx)\
265 || defined(STM32F303xC) || defined(STM32F358xx)
266#define IS_RCC_ADC34PLLCLK_DIV(ADCCLK) (((ADCCLK) == RCC_ADC34PLLCLK_OFF) || ((ADCCLK) == RCC_ADC34PLLCLK_DIV1) || \
267 ((ADCCLK) == RCC_ADC34PLLCLK_DIV2) || ((ADCCLK) == RCC_ADC34PLLCLK_DIV4) || \
268 ((ADCCLK) == RCC_ADC34PLLCLK_DIV6) || ((ADCCLK) == RCC_ADC34PLLCLK_DIV8) || \
269 ((ADCCLK) == RCC_ADC34PLLCLK_DIV10) || ((ADCCLK) == RCC_ADC34PLLCLK_DIV12) || \
270 ((ADCCLK) == RCC_ADC34PLLCLK_DIV16) || ((ADCCLK) == RCC_ADC34PLLCLK_DIV32) || \
271 ((ADCCLK) == RCC_ADC34PLLCLK_DIV64) || ((ADCCLK) == RCC_ADC34PLLCLK_DIV128) || \
272 ((ADCCLK) == RCC_ADC34PLLCLK_DIV256))
273#define IS_RCC_TIM8CLKSOURCE(SOURCE) (((SOURCE) == RCC_TIM8CLK_HCLK) || \
274 ((SOURCE) == RCC_TIM8CLK_PLLCLK))
275#endif /* STM32F303xC || STM32F303xE || STM32F398xx || STM32F358xx */
276#if defined(STM32F303x8) || defined(STM32F334x8) || defined(STM32F328xx)
277#define IS_RCC_USART1CLKSOURCE(SOURCE) (((SOURCE) == RCC_USART1CLKSOURCE_PCLK1) || \
278 ((SOURCE) == RCC_USART1CLKSOURCE_SYSCLK) || \
279 ((SOURCE) == RCC_USART1CLKSOURCE_LSE) || \
280 ((SOURCE) == RCC_USART1CLKSOURCE_HSI))
281#define IS_RCC_ADC12PLLCLK_DIV(ADCCLK) (((ADCCLK) == RCC_ADC12PLLCLK_OFF) || ((ADCCLK) == RCC_ADC12PLLCLK_DIV1) || \
282 ((ADCCLK) == RCC_ADC12PLLCLK_DIV2) || ((ADCCLK) == RCC_ADC12PLLCLK_DIV4) || \
283 ((ADCCLK) == RCC_ADC12PLLCLK_DIV6) || ((ADCCLK) == RCC_ADC12PLLCLK_DIV8) || \
284 ((ADCCLK) == RCC_ADC12PLLCLK_DIV10) || ((ADCCLK) == RCC_ADC12PLLCLK_DIV12) || \
285 ((ADCCLK) == RCC_ADC12PLLCLK_DIV16) || ((ADCCLK) == RCC_ADC12PLLCLK_DIV32) || \
286 ((ADCCLK) == RCC_ADC12PLLCLK_DIV64) || ((ADCCLK) == RCC_ADC12PLLCLK_DIV128) || \
287 ((ADCCLK) == RCC_ADC12PLLCLK_DIV256))
288#define IS_RCC_TIM1CLKSOURCE(SOURCE) (((SOURCE) == RCC_TIM1CLK_HCLK) || \
289 ((SOURCE) == RCC_TIM1CLK_PLLCLK))
290#endif /* STM32F303x8 || STM32F334x8 || STM32F328xx */
291#if defined(STM32F334x8)
292#define IS_RCC_HRTIM1CLKSOURCE(SOURCE) (((SOURCE) == RCC_HRTIM1CLK_HCLK) || \
293 ((SOURCE) == RCC_HRTIM1CLK_PLLCLK))
294#endif /* STM32F334x8 */
295#if defined(STM32F373xC) || defined(STM32F378xx)
296#define IS_RCC_USART1CLKSOURCE(SOURCE) (((SOURCE) == RCC_USART1CLKSOURCE_PCLK2) || \
297 ((SOURCE) == RCC_USART1CLKSOURCE_SYSCLK) || \
298 ((SOURCE) == RCC_USART1CLKSOURCE_LSE) || \
299 ((SOURCE) == RCC_USART1CLKSOURCE_HSI))
300#define IS_RCC_I2C2CLKSOURCE(SOURCE) (((SOURCE) == RCC_I2C2CLKSOURCE_HSI) || \
301 ((SOURCE) == RCC_I2C2CLKSOURCE_SYSCLK))
302#define IS_RCC_ADC1PCLK2_DIV(ADCCLK) (((ADCCLK) == RCC_ADC1PCLK2_DIV2) || ((ADCCLK) == RCC_ADC1PCLK2_DIV4) || \
303 ((ADCCLK) == RCC_ADC1PCLK2_DIV6) || ((ADCCLK) == RCC_ADC1PCLK2_DIV8))
304#define IS_RCC_CECCLKSOURCE(SOURCE) (((SOURCE) == RCC_CECCLKSOURCE_HSI) || \
305 ((SOURCE) == RCC_CECCLKSOURCE_LSE))
306#define IS_RCC_SDADCSYSCLK_DIV(DIV) (((DIV) == RCC_SDADCSYSCLK_DIV1) || ((DIV) == RCC_SDADCSYSCLK_DIV2) || \
307 ((DIV) == RCC_SDADCSYSCLK_DIV4) || ((DIV) == RCC_SDADCSYSCLK_DIV6) || \
308 ((DIV) == RCC_SDADCSYSCLK_DIV8) || ((DIV) == RCC_SDADCSYSCLK_DIV10) || \
309 ((DIV) == RCC_SDADCSYSCLK_DIV12) || ((DIV) == RCC_SDADCSYSCLK_DIV14) || \
310 ((DIV) == RCC_SDADCSYSCLK_DIV16) || ((DIV) == RCC_SDADCSYSCLK_DIV20) || \
311 ((DIV) == RCC_SDADCSYSCLK_DIV24) || ((DIV) == RCC_SDADCSYSCLK_DIV28) || \
312 ((DIV) == RCC_SDADCSYSCLK_DIV32) || ((DIV) == RCC_SDADCSYSCLK_DIV36) || \
313 ((DIV) == RCC_SDADCSYSCLK_DIV40) || ((DIV) == RCC_SDADCSYSCLK_DIV44) || \
314 ((DIV) == RCC_SDADCSYSCLK_DIV48))
315#endif /* STM32F373xC || STM32F378xx */
316#if defined(STM32F302xE) || defined(STM32F303xE)\
317 || defined(STM32F302xC) || defined(STM32F303xC)\
318 || defined(STM32F302x8) \
319 || defined(STM32F373xC)
320#define IS_RCC_USBCLKSOURCE(SOURCE) (((SOURCE) == RCC_USBCLKSOURCE_PLL) || \
321 ((SOURCE) == RCC_USBCLKSOURCE_PLL_DIV1_5))
322#endif /* STM32F302xE || STM32F303xE || */
323 /* STM32F302xC || STM32F303xC || */
324 /* STM32F302x8 || */
325 /* STM32F373xC */
326#if defined(RCC_CFGR_MCOPRE)
327#define IS_RCC_MCODIV(DIV) (((DIV) == RCC_MCODIV_1) || ((DIV) == RCC_MCODIV_2) || \
328 ((DIV) == RCC_MCODIV_4) || ((DIV) == RCC_MCODIV_8) || \
329 ((DIV) == RCC_MCODIV_16) || ((DIV) == RCC_MCODIV_32) || \
330 ((DIV) == RCC_MCODIV_64) || ((DIV) == RCC_MCODIV_128))
331#else
332#define IS_RCC_MCODIV(DIV) (((DIV) == RCC_MCODIV_1))
333#endif /* RCC_CFGR_MCOPRE */
334
335#define IS_RCC_LSE_DRIVE(__DRIVE__) (((__DRIVE__) == RCC_LSEDRIVE_LOW) || \
336 ((__DRIVE__) == RCC_LSEDRIVE_MEDIUMLOW) || \
337 ((__DRIVE__) == RCC_LSEDRIVE_MEDIUMHIGH) || \
338 ((__DRIVE__) == RCC_LSEDRIVE_HIGH))
339
344/* Exported types ------------------------------------------------------------*/
352#if defined(STM32F301x8) || defined(STM32F318xx)
353typedef struct
354{
355 uint32_t PeriphClockSelection;
358 uint32_t RTCClockSelection;
361 uint32_t Usart1ClockSelection;
364 uint32_t I2c1ClockSelection;
367 uint32_t I2c2ClockSelection;
370 uint32_t I2c3ClockSelection;
373 uint32_t Adc1ClockSelection;
376 uint32_t I2sClockSelection;
379 uint32_t Tim1ClockSelection;
382 uint32_t Tim15ClockSelection;
385 uint32_t Tim16ClockSelection;
388 uint32_t Tim17ClockSelection;
390}RCC_PeriphCLKInitTypeDef;
391#endif /* STM32F301x8 || STM32F318xx */
392
393#if defined(STM32F302x8)
394typedef struct
395{
396 uint32_t PeriphClockSelection;
399 uint32_t RTCClockSelection;
402 uint32_t Usart1ClockSelection;
405 uint32_t I2c1ClockSelection;
408 uint32_t I2c2ClockSelection;
411 uint32_t I2c3ClockSelection;
414 uint32_t Adc1ClockSelection;
417 uint32_t I2sClockSelection;
420 uint32_t Tim1ClockSelection;
423 uint32_t Tim15ClockSelection;
426 uint32_t Tim16ClockSelection;
429 uint32_t Tim17ClockSelection;
432 uint32_t USBClockSelection;
435}RCC_PeriphCLKInitTypeDef;
436#endif /* STM32F302x8 */
437
438#if defined(STM32F302xC)
439typedef struct
440{
441 uint32_t PeriphClockSelection;
444 uint32_t RTCClockSelection;
447 uint32_t Usart1ClockSelection;
450 uint32_t Usart2ClockSelection;
453 uint32_t Usart3ClockSelection;
456 uint32_t Uart4ClockSelection;
459 uint32_t Uart5ClockSelection;
462 uint32_t I2c1ClockSelection;
465 uint32_t I2c2ClockSelection;
468 uint32_t Adc12ClockSelection;
471 uint32_t I2sClockSelection;
474 uint32_t Tim1ClockSelection;
477 uint32_t USBClockSelection;
480}RCC_PeriphCLKInitTypeDef;
481#endif /* STM32F302xC */
482
483#if defined(STM32F303xC)
484typedef struct
485{
486 uint32_t PeriphClockSelection;
489 uint32_t RTCClockSelection;
492 uint32_t Usart1ClockSelection;
495 uint32_t Usart2ClockSelection;
498 uint32_t Usart3ClockSelection;
501 uint32_t Uart4ClockSelection;
504 uint32_t Uart5ClockSelection;
507 uint32_t I2c1ClockSelection;
510 uint32_t I2c2ClockSelection;
513 uint32_t Adc12ClockSelection;
516 uint32_t Adc34ClockSelection;
519 uint32_t I2sClockSelection;
522 uint32_t Tim1ClockSelection;
525 uint32_t Tim8ClockSelection;
528 uint32_t USBClockSelection;
531}RCC_PeriphCLKInitTypeDef;
532#endif /* STM32F303xC */
533
534#if defined(STM32F302xE)
535typedef struct
536{
537 uint32_t PeriphClockSelection;
540 uint32_t RTCClockSelection;
543 uint32_t Usart1ClockSelection;
546 uint32_t Usart2ClockSelection;
549 uint32_t Usart3ClockSelection;
552 uint32_t Uart4ClockSelection;
555 uint32_t Uart5ClockSelection;
558 uint32_t I2c1ClockSelection;
561 uint32_t I2c2ClockSelection;
564 uint32_t I2c3ClockSelection;
567 uint32_t Adc12ClockSelection;
570 uint32_t I2sClockSelection;
573 uint32_t Tim1ClockSelection;
576 uint32_t Tim2ClockSelection;
579 uint32_t Tim34ClockSelection;
582 uint32_t Tim15ClockSelection;
585 uint32_t Tim16ClockSelection;
588 uint32_t Tim17ClockSelection;
591 uint32_t USBClockSelection;
594}RCC_PeriphCLKInitTypeDef;
595#endif /* STM32F302xE */
596
597#if defined(STM32F303xE)
598typedef struct
599{
600 uint32_t PeriphClockSelection;
603 uint32_t RTCClockSelection;
606 uint32_t Usart1ClockSelection;
609 uint32_t Usart2ClockSelection;
612 uint32_t Usart3ClockSelection;
615 uint32_t Uart4ClockSelection;
618 uint32_t Uart5ClockSelection;
621 uint32_t I2c1ClockSelection;
624 uint32_t I2c2ClockSelection;
627 uint32_t I2c3ClockSelection;
630 uint32_t Adc12ClockSelection;
633 uint32_t Adc34ClockSelection;
636 uint32_t I2sClockSelection;
639 uint32_t Tim1ClockSelection;
642 uint32_t Tim2ClockSelection;
645 uint32_t Tim34ClockSelection;
648 uint32_t Tim8ClockSelection;
651 uint32_t Tim15ClockSelection;
654 uint32_t Tim16ClockSelection;
657 uint32_t Tim17ClockSelection;
660 uint32_t Tim20ClockSelection;
663 uint32_t USBClockSelection;
666}RCC_PeriphCLKInitTypeDef;
667#endif /* STM32F303xE */
668
669#if defined(STM32F398xx)
670typedef struct
671{
672 uint32_t PeriphClockSelection;
675 uint32_t RTCClockSelection;
678 uint32_t Usart1ClockSelection;
681 uint32_t Usart2ClockSelection;
684 uint32_t Usart3ClockSelection;
687 uint32_t Uart4ClockSelection;
690 uint32_t Uart5ClockSelection;
693 uint32_t I2c1ClockSelection;
696 uint32_t I2c2ClockSelection;
699 uint32_t I2c3ClockSelection;
702 uint32_t Adc12ClockSelection;
705 uint32_t Adc34ClockSelection;
708 uint32_t I2sClockSelection;
711 uint32_t Tim1ClockSelection;
714 uint32_t Tim2ClockSelection;
717 uint32_t Tim34ClockSelection;
720 uint32_t Tim8ClockSelection;
723 uint32_t Tim15ClockSelection;
726 uint32_t Tim16ClockSelection;
729 uint32_t Tim17ClockSelection;
732 uint32_t Tim20ClockSelection;
735}RCC_PeriphCLKInitTypeDef;
736#endif /* STM32F398xx */
737
738#if defined(STM32F358xx)
739typedef struct
740{
741 uint32_t PeriphClockSelection;
744 uint32_t RTCClockSelection;
747 uint32_t Usart1ClockSelection;
750 uint32_t Usart2ClockSelection;
753 uint32_t Usart3ClockSelection;
756 uint32_t Uart4ClockSelection;
759 uint32_t Uart5ClockSelection;
762 uint32_t I2c1ClockSelection;
765 uint32_t I2c2ClockSelection;
768 uint32_t Adc12ClockSelection;
771 uint32_t Adc34ClockSelection;
774 uint32_t I2sClockSelection;
777 uint32_t Tim1ClockSelection;
780 uint32_t Tim8ClockSelection;
783}RCC_PeriphCLKInitTypeDef;
784#endif /* STM32F358xx */
785
786#if defined(STM32F303x8)
787typedef struct
788{
789 uint32_t PeriphClockSelection;
792 uint32_t RTCClockSelection;
795 uint32_t Usart1ClockSelection;
798 uint32_t I2c1ClockSelection;
801 uint32_t Adc12ClockSelection;
804 uint32_t Tim1ClockSelection;
807}RCC_PeriphCLKInitTypeDef;
808#endif /* STM32F303x8 */
809
810#if defined(STM32F334x8)
811typedef struct
812{
813 uint32_t PeriphClockSelection;
816 uint32_t RTCClockSelection;
819 uint32_t Usart1ClockSelection;
822 uint32_t I2c1ClockSelection;
825 uint32_t Adc12ClockSelection;
828 uint32_t Tim1ClockSelection;
831 uint32_t Hrtim1ClockSelection;
834}RCC_PeriphCLKInitTypeDef;
835#endif /* STM32F334x8 */
836
837#if defined(STM32F328xx)
838typedef struct
839{
840 uint32_t PeriphClockSelection;
843 uint32_t RTCClockSelection;
846 uint32_t Usart1ClockSelection;
849 uint32_t I2c1ClockSelection;
852 uint32_t Adc12ClockSelection;
855 uint32_t Tim1ClockSelection;
858}RCC_PeriphCLKInitTypeDef;
859#endif /* STM32F328xx */
860
861#if defined(STM32F373xC)
862typedef struct
863{
864 uint32_t PeriphClockSelection;
867 uint32_t RTCClockSelection;
870 uint32_t Usart1ClockSelection;
873 uint32_t Usart2ClockSelection;
876 uint32_t Usart3ClockSelection;
879 uint32_t I2c1ClockSelection;
882 uint32_t I2c2ClockSelection;
885 uint32_t Adc1ClockSelection;
888 uint32_t SdadcClockSelection;
891 uint32_t CecClockSelection;
894 uint32_t USBClockSelection;
897}RCC_PeriphCLKInitTypeDef;
898#endif /* STM32F373xC */
899
900#if defined(STM32F378xx)
901typedef struct
902{
903 uint32_t PeriphClockSelection;
906 uint32_t RTCClockSelection;
909 uint32_t Usart1ClockSelection;
912 uint32_t Usart2ClockSelection;
915 uint32_t Usart3ClockSelection;
918 uint32_t I2c1ClockSelection;
921 uint32_t I2c2ClockSelection;
924 uint32_t Adc1ClockSelection;
927 uint32_t SdadcClockSelection;
930 uint32_t CecClockSelection;
933}RCC_PeriphCLKInitTypeDef;
934#endif /* STM32F378xx */
935
940/* Exported constants --------------------------------------------------------*/
947#define RCC_MCO1SOURCE_NOCLOCK RCC_CFGR_MCO_NOCLOCK
948#define RCC_MCO1SOURCE_LSI RCC_CFGR_MCO_LSI
949#define RCC_MCO1SOURCE_LSE RCC_CFGR_MCO_LSE
950#define RCC_MCO1SOURCE_SYSCLK RCC_CFGR_MCO_SYSCLK
951#define RCC_MCO1SOURCE_HSI RCC_CFGR_MCO_HSI
952#define RCC_MCO1SOURCE_HSE RCC_CFGR_MCO_HSE
953#if defined(RCC_CFGR_PLLNODIV)
954#define RCC_MCO1SOURCE_PLLCLK (RCC_CFGR_PLLNODIV | RCC_CFGR_MCO_PLL)
955#endif /* RCC_CFGR_PLLNODIV */
956#define RCC_MCO1SOURCE_PLLCLK_DIV2 RCC_CFGR_MCO_PLL
957
965#if defined(STM32F301x8) || defined(STM32F318xx)
966#define RCC_PERIPHCLK_USART1 (0x00000001U)
967#define RCC_PERIPHCLK_I2C1 (0x00000020U)
968#define RCC_PERIPHCLK_I2C2 (0x00000040U)
969#define RCC_PERIPHCLK_ADC1 (0x00000080U)
970#define RCC_PERIPHCLK_I2S (0x00000200U)
971#define RCC_PERIPHCLK_TIM1 (0x00001000U)
972#define RCC_PERIPHCLK_I2C3 (0x00008000U)
973#define RCC_PERIPHCLK_RTC (0x00010000U)
974#define RCC_PERIPHCLK_TIM15 (0x00040000U)
975#define RCC_PERIPHCLK_TIM16 (0x00080000U)
976#define RCC_PERIPHCLK_TIM17 (0x00100000U)
977
978#endif /* STM32F301x8 || STM32F318xx */
979
980#if defined(STM32F302x8)
981#define RCC_PERIPHCLK_USART1 (0x00000001U)
982#define RCC_PERIPHCLK_I2C1 (0x00000020U)
983#define RCC_PERIPHCLK_I2C2 (0x00000040U)
984#define RCC_PERIPHCLK_ADC1 (0x00000080U)
985#define RCC_PERIPHCLK_I2S (0x00000200U)
986#define RCC_PERIPHCLK_TIM1 (0x00001000U)
987#define RCC_PERIPHCLK_I2C3 (0x00008000U)
988#define RCC_PERIPHCLK_RTC (0x00010000U)
989#define RCC_PERIPHCLK_USB (0x00020000U)
990#define RCC_PERIPHCLK_TIM15 (0x00040000U)
991#define RCC_PERIPHCLK_TIM16 (0x00080000U)
992#define RCC_PERIPHCLK_TIM17 (0x00100000U)
993
994
995#endif /* STM32F302x8 */
996
997#if defined(STM32F302xC)
998#define RCC_PERIPHCLK_USART1 (0x00000001U)
999#define RCC_PERIPHCLK_USART2 (0x00000002U)
1000#define RCC_PERIPHCLK_USART3 (0x00000004U)
1001#define RCC_PERIPHCLK_UART4 (0x00000008U)
1002#define RCC_PERIPHCLK_UART5 (0x00000010U)
1003#define RCC_PERIPHCLK_I2C1 (0x00000020U)
1004#define RCC_PERIPHCLK_I2C2 (0x00000040U)
1005#define RCC_PERIPHCLK_ADC12 (0x00000080U)
1006#define RCC_PERIPHCLK_I2S (0x00000200U)
1007#define RCC_PERIPHCLK_TIM1 (0x00001000U)
1008#define RCC_PERIPHCLK_RTC (0x00010000U)
1009#define RCC_PERIPHCLK_USB (0x00020000U)
1010
1011#endif /* STM32F302xC */
1012
1013#if defined(STM32F303xC)
1014#define RCC_PERIPHCLK_USART1 (0x00000001U)
1015#define RCC_PERIPHCLK_USART2 (0x00000002U)
1016#define RCC_PERIPHCLK_USART3 (0x00000004U)
1017#define RCC_PERIPHCLK_UART4 (0x00000008U)
1018#define RCC_PERIPHCLK_UART5 (0x00000010U)
1019#define RCC_PERIPHCLK_I2C1 (0x00000020U)
1020#define RCC_PERIPHCLK_I2C2 (0x00000040U)
1021#define RCC_PERIPHCLK_ADC12 (0x00000080U)
1022#define RCC_PERIPHCLK_ADC34 (0x00000100U)
1023#define RCC_PERIPHCLK_I2S (0x00000200U)
1024#define RCC_PERIPHCLK_TIM1 (0x00001000U)
1025#define RCC_PERIPHCLK_TIM8 (0x00002000U)
1026#define RCC_PERIPHCLK_RTC (0x00010000U)
1027#define RCC_PERIPHCLK_USB (0x00020000U)
1028
1029#endif /* STM32F303xC */
1030
1031#if defined(STM32F302xE)
1032#define RCC_PERIPHCLK_USART1 (0x00000001U)
1033#define RCC_PERIPHCLK_USART2 (0x00000002U)
1034#define RCC_PERIPHCLK_USART3 (0x00000004U)
1035#define RCC_PERIPHCLK_UART4 (0x00000008U)
1036#define RCC_PERIPHCLK_UART5 (0x00000010U)
1037#define RCC_PERIPHCLK_I2C1 (0x00000020U)
1038#define RCC_PERIPHCLK_I2C2 (0x00000040U)
1039#define RCC_PERIPHCLK_ADC12 (0x00000080U)
1040#define RCC_PERIPHCLK_I2S (0x00000200U)
1041#define RCC_PERIPHCLK_TIM1 (0x00001000U)
1042#define RCC_PERIPHCLK_RTC (0x00010000U)
1043#define RCC_PERIPHCLK_USB (0x00020000U)
1044#define RCC_PERIPHCLK_I2C3 (0x00040000U)
1045#define RCC_PERIPHCLK_TIM2 (0x00100000U)
1046#define RCC_PERIPHCLK_TIM34 (0x00200000U)
1047#define RCC_PERIPHCLK_TIM15 (0x00400000U)
1048#define RCC_PERIPHCLK_TIM16 (0x00800000U)
1049#define RCC_PERIPHCLK_TIM17 (0x01000000U)
1050
1051#endif /* STM32F302xE */
1052
1053#if defined(STM32F303xE)
1054#define RCC_PERIPHCLK_USART1 (0x00000001U)
1055#define RCC_PERIPHCLK_USART2 (0x00000002U)
1056#define RCC_PERIPHCLK_USART3 (0x00000004U)
1057#define RCC_PERIPHCLK_UART4 (0x00000008U)
1058#define RCC_PERIPHCLK_UART5 (0x00000010U)
1059#define RCC_PERIPHCLK_I2C1 (0x00000020U)
1060#define RCC_PERIPHCLK_I2C2 (0x00000040U)
1061#define RCC_PERIPHCLK_ADC12 (0x00000080U)
1062#define RCC_PERIPHCLK_ADC34 (0x00000100U)
1063#define RCC_PERIPHCLK_I2S (0x00000200U)
1064#define RCC_PERIPHCLK_TIM1 (0x00001000U)
1065#define RCC_PERIPHCLK_TIM8 (0x00002000U)
1066#define RCC_PERIPHCLK_RTC (0x00010000U)
1067#define RCC_PERIPHCLK_USB (0x00020000U)
1068#define RCC_PERIPHCLK_I2C3 (0x00040000U)
1069#define RCC_PERIPHCLK_TIM2 (0x00100000U)
1070#define RCC_PERIPHCLK_TIM34 (0x00200000U)
1071#define RCC_PERIPHCLK_TIM15 (0x00400000U)
1072#define RCC_PERIPHCLK_TIM16 (0x00800000U)
1073#define RCC_PERIPHCLK_TIM17 (0x01000000U)
1074#define RCC_PERIPHCLK_TIM20 (0x02000000U)
1075
1076#endif /* STM32F303xE */
1077
1078#if defined(STM32F398xx)
1079#define RCC_PERIPHCLK_USART1 (0x00000001U)
1080#define RCC_PERIPHCLK_USART2 (0x00000002U)
1081#define RCC_PERIPHCLK_USART3 (0x00000004U)
1082#define RCC_PERIPHCLK_UART4 (0x00000008U)
1083#define RCC_PERIPHCLK_UART5 (0x00000010U)
1084#define RCC_PERIPHCLK_I2C1 (0x00000020U)
1085#define RCC_PERIPHCLK_I2C2 (0x00000040U)
1086#define RCC_PERIPHCLK_ADC12 (0x00000080U)
1087#define RCC_PERIPHCLK_ADC34 (0x00000100U)
1088#define RCC_PERIPHCLK_I2S (0x00000200U)
1089#define RCC_PERIPHCLK_TIM1 (0x00001000U)
1090#define RCC_PERIPHCLK_TIM8 (0x00002000U)
1091#define RCC_PERIPHCLK_RTC (0x00010000U)
1092#define RCC_PERIPHCLK_I2C3 (0x00040000U)
1093#define RCC_PERIPHCLK_TIM2 (0x00100000U)
1094#define RCC_PERIPHCLK_TIM34 (0x00200000U)
1095#define RCC_PERIPHCLK_TIM15 (0x00400000U)
1096#define RCC_PERIPHCLK_TIM16 (0x00800000U)
1097#define RCC_PERIPHCLK_TIM17 (0x01000000U)
1098#define RCC_PERIPHCLK_TIM20 (0x02000000U)
1099
1100
1101#endif /* STM32F398xx */
1102
1103#if defined(STM32F358xx)
1104#define RCC_PERIPHCLK_USART1 (0x00000001U)
1105#define RCC_PERIPHCLK_USART2 (0x00000002U)
1106#define RCC_PERIPHCLK_USART3 (0x00000004U)
1107#define RCC_PERIPHCLK_UART4 (0x00000008U)
1108#define RCC_PERIPHCLK_UART5 (0x00000010U)
1109#define RCC_PERIPHCLK_I2C1 (0x00000020U)
1110#define RCC_PERIPHCLK_I2C2 (0x00000040U)
1111#define RCC_PERIPHCLK_ADC12 (0x00000080U)
1112#define RCC_PERIPHCLK_ADC34 (0x00000100U)
1113#define RCC_PERIPHCLK_I2S (0x00000200U)
1114#define RCC_PERIPHCLK_TIM1 (0x00001000U)
1115#define RCC_PERIPHCLK_TIM8 (0x00002000U)
1116#define RCC_PERIPHCLK_RTC (0x00010000U)
1117
1118#endif /* STM32F358xx */
1119
1120#if defined(STM32F303x8)
1121#define RCC_PERIPHCLK_USART1 (0x00000001U)
1122#define RCC_PERIPHCLK_I2C1 (0x00000020U)
1123#define RCC_PERIPHCLK_ADC12 (0x00000080U)
1124#define RCC_PERIPHCLK_TIM1 (0x00001000U)
1125#define RCC_PERIPHCLK_RTC (0x00010000U)
1126
1127#endif /* STM32F303x8 */
1128
1129#if defined(STM32F334x8)
1130#define RCC_PERIPHCLK_USART1 (0x00000001U)
1131#define RCC_PERIPHCLK_I2C1 (0x00000020U)
1132#define RCC_PERIPHCLK_ADC12 (0x00000080U)
1133#define RCC_PERIPHCLK_TIM1 (0x00001000U)
1134#define RCC_PERIPHCLK_HRTIM1 (0x00004000U)
1135#define RCC_PERIPHCLK_RTC (0x00010000U)
1136
1137
1138#endif /* STM32F334x8 */
1139
1140#if defined(STM32F328xx)
1141#define RCC_PERIPHCLK_USART1 (0x00000001U)
1142#define RCC_PERIPHCLK_I2C1 (0x00000020U)
1143#define RCC_PERIPHCLK_ADC12 (0x00000080U)
1144#define RCC_PERIPHCLK_TIM1 (0x00001000U)
1145#define RCC_PERIPHCLK_RTC (0x00010000U)
1146
1147#endif /* STM32F328xx */
1148
1149#if defined(STM32F373xC)
1150#define RCC_PERIPHCLK_USART1 (0x00000001U)
1151#define RCC_PERIPHCLK_USART2 (0x00000002U)
1152#define RCC_PERIPHCLK_USART3 (0x00000004U)
1153#define RCC_PERIPHCLK_I2C1 (0x00000020U)
1154#define RCC_PERIPHCLK_I2C2 (0x00000040U)
1155#define RCC_PERIPHCLK_ADC1 (0x00000080U)
1156#define RCC_PERIPHCLK_CEC (0x00000400U)
1157#define RCC_PERIPHCLK_SDADC (0x00000800U)
1158#define RCC_PERIPHCLK_RTC (0x00010000U)
1159#define RCC_PERIPHCLK_USB (0x00020000U)
1160
1161#endif /* STM32F373xC */
1162
1163#if defined(STM32F378xx)
1164#define RCC_PERIPHCLK_USART1 (0x00000001U)
1165#define RCC_PERIPHCLK_USART2 (0x00000002U)
1166#define RCC_PERIPHCLK_USART3 (0x00000004U)
1167#define RCC_PERIPHCLK_I2C1 (0x00000020U)
1168#define RCC_PERIPHCLK_I2C2 (0x00000040U)
1169#define RCC_PERIPHCLK_ADC1 (0x00000080U)
1170#define RCC_PERIPHCLK_CEC (0x00000400U)
1171#define RCC_PERIPHCLK_SDADC (0x00000800U)
1172#define RCC_PERIPHCLK_RTC (0x00010000U)
1173
1174#endif /* STM32F378xx */
1179#if defined(STM32F301x8) || defined(STM32F302x8) || defined(STM32F318xx)
1180
1184#define RCC_USART1CLKSOURCE_PCLK1 RCC_CFGR3_USART1SW_PCLK1
1185#define RCC_USART1CLKSOURCE_SYSCLK RCC_CFGR3_USART1SW_SYSCLK
1186#define RCC_USART1CLKSOURCE_LSE RCC_CFGR3_USART1SW_LSE
1187#define RCC_USART1CLKSOURCE_HSI RCC_CFGR3_USART1SW_HSI
1188
1196#define RCC_I2C2CLKSOURCE_HSI RCC_CFGR3_I2C2SW_HSI
1197#define RCC_I2C2CLKSOURCE_SYSCLK RCC_CFGR3_I2C2SW_SYSCLK
1198
1206#define RCC_I2C3CLKSOURCE_HSI RCC_CFGR3_I2C3SW_HSI
1207#define RCC_I2C3CLKSOURCE_SYSCLK RCC_CFGR3_I2C3SW_SYSCLK
1208
1216#define RCC_ADC1PLLCLK_OFF RCC_CFGR2_ADC1PRES_NO
1217#define RCC_ADC1PLLCLK_DIV1 RCC_CFGR2_ADC1PRES_DIV1
1218#define RCC_ADC1PLLCLK_DIV2 RCC_CFGR2_ADC1PRES_DIV2
1219#define RCC_ADC1PLLCLK_DIV4 RCC_CFGR2_ADC1PRES_DIV4
1220#define RCC_ADC1PLLCLK_DIV6 RCC_CFGR2_ADC1PRES_DIV6
1221#define RCC_ADC1PLLCLK_DIV8 RCC_CFGR2_ADC1PRES_DIV8
1222#define RCC_ADC1PLLCLK_DIV10 RCC_CFGR2_ADC1PRES_DIV10
1223#define RCC_ADC1PLLCLK_DIV12 RCC_CFGR2_ADC1PRES_DIV12
1224#define RCC_ADC1PLLCLK_DIV16 RCC_CFGR2_ADC1PRES_DIV16
1225#define RCC_ADC1PLLCLK_DIV32 RCC_CFGR2_ADC1PRES_DIV32
1226#define RCC_ADC1PLLCLK_DIV64 RCC_CFGR2_ADC1PRES_DIV64
1227#define RCC_ADC1PLLCLK_DIV128 RCC_CFGR2_ADC1PRES_DIV128
1228#define RCC_ADC1PLLCLK_DIV256 RCC_CFGR2_ADC1PRES_DIV256
1229
1237#define RCC_I2SCLKSOURCE_SYSCLK RCC_CFGR_I2SSRC_SYSCLK
1238#define RCC_I2SCLKSOURCE_EXT RCC_CFGR_I2SSRC_EXT
1239
1247#define RCC_TIM1CLK_HCLK RCC_CFGR3_TIM1SW_HCLK
1248#define RCC_TIM1CLK_PLLCLK RCC_CFGR3_TIM1SW_PLL
1249
1257#define RCC_TIM15CLK_HCLK RCC_CFGR3_TIM15SW_HCLK
1258#define RCC_TIM15CLK_PLLCLK RCC_CFGR3_TIM15SW_PLL
1259
1267#define RCC_TIM16CLK_HCLK RCC_CFGR3_TIM16SW_HCLK
1268#define RCC_TIM16CLK_PLLCLK RCC_CFGR3_TIM16SW_PLL
1269
1277#define RCC_TIM17CLK_HCLK RCC_CFGR3_TIM17SW_HCLK
1278#define RCC_TIM17CLK_PLLCLK RCC_CFGR3_TIM17SW_PLL
1279
1284#endif /* STM32F301x8 || STM32F302x8 || STM32F318xx */
1285
1286#if defined(STM32F302xC) || defined(STM32F303xC) || defined(STM32F358xx)
1287
1291#define RCC_USART1CLKSOURCE_PCLK2 RCC_CFGR3_USART1SW_PCLK2
1292#define RCC_USART1CLKSOURCE_SYSCLK RCC_CFGR3_USART1SW_SYSCLK
1293#define RCC_USART1CLKSOURCE_LSE RCC_CFGR3_USART1SW_LSE
1294#define RCC_USART1CLKSOURCE_HSI RCC_CFGR3_USART1SW_HSI
1295
1303#define RCC_I2C2CLKSOURCE_HSI RCC_CFGR3_I2C2SW_HSI
1304#define RCC_I2C2CLKSOURCE_SYSCLK RCC_CFGR3_I2C2SW_SYSCLK
1305
1314/* ADC1 & ADC2 */
1315#define RCC_ADC12PLLCLK_OFF RCC_CFGR2_ADCPRE12_NO
1316#define RCC_ADC12PLLCLK_DIV1 RCC_CFGR2_ADCPRE12_DIV1
1317#define RCC_ADC12PLLCLK_DIV2 RCC_CFGR2_ADCPRE12_DIV2
1318#define RCC_ADC12PLLCLK_DIV4 RCC_CFGR2_ADCPRE12_DIV4
1319#define RCC_ADC12PLLCLK_DIV6 RCC_CFGR2_ADCPRE12_DIV6
1320#define RCC_ADC12PLLCLK_DIV8 RCC_CFGR2_ADCPRE12_DIV8
1321#define RCC_ADC12PLLCLK_DIV10 RCC_CFGR2_ADCPRE12_DIV10
1322#define RCC_ADC12PLLCLK_DIV12 RCC_CFGR2_ADCPRE12_DIV12
1323#define RCC_ADC12PLLCLK_DIV16 RCC_CFGR2_ADCPRE12_DIV16
1324#define RCC_ADC12PLLCLK_DIV32 RCC_CFGR2_ADCPRE12_DIV32
1325#define RCC_ADC12PLLCLK_DIV64 RCC_CFGR2_ADCPRE12_DIV64
1326#define RCC_ADC12PLLCLK_DIV128 RCC_CFGR2_ADCPRE12_DIV128
1327#define RCC_ADC12PLLCLK_DIV256 RCC_CFGR2_ADCPRE12_DIV256
1328
1336#define RCC_I2SCLKSOURCE_SYSCLK RCC_CFGR_I2SSRC_SYSCLK
1337#define RCC_I2SCLKSOURCE_EXT RCC_CFGR_I2SSRC_EXT
1338
1345#define RCC_TIM1CLK_HCLK RCC_CFGR3_TIM1SW_HCLK
1346#define RCC_TIM1CLK_PLLCLK RCC_CFGR3_TIM1SW_PLL
1347
1355#define RCC_UART4CLKSOURCE_PCLK1 RCC_CFGR3_UART4SW_PCLK
1356#define RCC_UART4CLKSOURCE_SYSCLK RCC_CFGR3_UART4SW_SYSCLK
1357#define RCC_UART4CLKSOURCE_LSE RCC_CFGR3_UART4SW_LSE
1358#define RCC_UART4CLKSOURCE_HSI RCC_CFGR3_UART4SW_HSI
1359
1367#define RCC_UART5CLKSOURCE_PCLK1 RCC_CFGR3_UART5SW_PCLK
1368#define RCC_UART5CLKSOURCE_SYSCLK RCC_CFGR3_UART5SW_SYSCLK
1369#define RCC_UART5CLKSOURCE_LSE RCC_CFGR3_UART5SW_LSE
1370#define RCC_UART5CLKSOURCE_HSI RCC_CFGR3_UART5SW_HSI
1371
1376#endif /* STM32F302xC || STM32F303xC || STM32F358xx */
1377
1378#if defined(STM32F302xE) || defined(STM32F303xE) || defined(STM32F398xx)
1379
1383#define RCC_USART1CLKSOURCE_PCLK2 RCC_CFGR3_USART1SW_PCLK2
1384#define RCC_USART1CLKSOURCE_SYSCLK RCC_CFGR3_USART1SW_SYSCLK
1385#define RCC_USART1CLKSOURCE_LSE RCC_CFGR3_USART1SW_LSE
1386#define RCC_USART1CLKSOURCE_HSI RCC_CFGR3_USART1SW_HSI
1387
1395#define RCC_I2C2CLKSOURCE_HSI RCC_CFGR3_I2C2SW_HSI
1396#define RCC_I2C2CLKSOURCE_SYSCLK RCC_CFGR3_I2C2SW_SYSCLK
1397
1405#define RCC_I2C3CLKSOURCE_HSI RCC_CFGR3_I2C3SW_HSI
1406#define RCC_I2C3CLKSOURCE_SYSCLK RCC_CFGR3_I2C3SW_SYSCLK
1407
1416/* ADC1 & ADC2 */
1417#define RCC_ADC12PLLCLK_OFF RCC_CFGR2_ADCPRE12_NO
1418#define RCC_ADC12PLLCLK_DIV1 RCC_CFGR2_ADCPRE12_DIV1
1419#define RCC_ADC12PLLCLK_DIV2 RCC_CFGR2_ADCPRE12_DIV2
1420#define RCC_ADC12PLLCLK_DIV4 RCC_CFGR2_ADCPRE12_DIV4
1421#define RCC_ADC12PLLCLK_DIV6 RCC_CFGR2_ADCPRE12_DIV6
1422#define RCC_ADC12PLLCLK_DIV8 RCC_CFGR2_ADCPRE12_DIV8
1423#define RCC_ADC12PLLCLK_DIV10 RCC_CFGR2_ADCPRE12_DIV10
1424#define RCC_ADC12PLLCLK_DIV12 RCC_CFGR2_ADCPRE12_DIV12
1425#define RCC_ADC12PLLCLK_DIV16 RCC_CFGR2_ADCPRE12_DIV16
1426#define RCC_ADC12PLLCLK_DIV32 RCC_CFGR2_ADCPRE12_DIV32
1427#define RCC_ADC12PLLCLK_DIV64 RCC_CFGR2_ADCPRE12_DIV64
1428#define RCC_ADC12PLLCLK_DIV128 RCC_CFGR2_ADCPRE12_DIV128
1429#define RCC_ADC12PLLCLK_DIV256 RCC_CFGR2_ADCPRE12_DIV256
1430
1438#define RCC_I2SCLKSOURCE_SYSCLK RCC_CFGR_I2SSRC_SYSCLK
1439#define RCC_I2SCLKSOURCE_EXT RCC_CFGR_I2SSRC_EXT
1440
1448#define RCC_TIM1CLK_HCLK RCC_CFGR3_TIM1SW_HCLK
1449#define RCC_TIM1CLK_PLLCLK RCC_CFGR3_TIM1SW_PLL
1450
1458#define RCC_TIM2CLK_HCLK RCC_CFGR3_TIM2SW_HCLK
1459#define RCC_TIM2CLK_PLLCLK RCC_CFGR3_TIM2SW_PLL
1460
1468#define RCC_TIM34CLK_HCLK RCC_CFGR3_TIM34SW_HCLK
1469#define RCC_TIM34CLK_PLLCLK RCC_CFGR3_TIM34SW_PLL
1470
1478#define RCC_TIM15CLK_HCLK RCC_CFGR3_TIM15SW_HCLK
1479#define RCC_TIM15CLK_PLLCLK RCC_CFGR3_TIM15SW_PLL
1480
1488#define RCC_TIM16CLK_HCLK RCC_CFGR3_TIM16SW_HCLK
1489#define RCC_TIM16CLK_PLLCLK RCC_CFGR3_TIM16SW_PLL
1490
1498#define RCC_TIM17CLK_HCLK RCC_CFGR3_TIM17SW_HCLK
1499#define RCC_TIM17CLK_PLLCLK RCC_CFGR3_TIM17SW_PLL
1500
1508#define RCC_UART4CLKSOURCE_PCLK1 RCC_CFGR3_UART4SW_PCLK
1509#define RCC_UART4CLKSOURCE_SYSCLK RCC_CFGR3_UART4SW_SYSCLK
1510#define RCC_UART4CLKSOURCE_LSE RCC_CFGR3_UART4SW_LSE
1511#define RCC_UART4CLKSOURCE_HSI RCC_CFGR3_UART4SW_HSI
1512
1520#define RCC_UART5CLKSOURCE_PCLK1 RCC_CFGR3_UART5SW_PCLK
1521#define RCC_UART5CLKSOURCE_SYSCLK RCC_CFGR3_UART5SW_SYSCLK
1522#define RCC_UART5CLKSOURCE_LSE RCC_CFGR3_UART5SW_LSE
1523#define RCC_UART5CLKSOURCE_HSI RCC_CFGR3_UART5SW_HSI
1524
1529#endif /* STM32F302xE || STM32F303xE || STM32F398xx */
1530
1531#if defined(STM32F303xE) || defined(STM32F398xx)
1535#define RCC_TIM20CLK_HCLK RCC_CFGR3_TIM20SW_HCLK
1536#define RCC_TIM20CLK_PLLCLK RCC_CFGR3_TIM20SW_PLL
1537
1541#endif /* STM32F303xE || STM32F398xx */
1542
1543#if defined(STM32F303xE) || defined(STM32F398xx)\
1544 || defined(STM32F303xC) || defined(STM32F358xx)
1545
1550/* ADC3 & ADC4 */
1551#define RCC_ADC34PLLCLK_OFF RCC_CFGR2_ADCPRE34_NO
1552#define RCC_ADC34PLLCLK_DIV1 RCC_CFGR2_ADCPRE34_DIV1
1553#define RCC_ADC34PLLCLK_DIV2 RCC_CFGR2_ADCPRE34_DIV2
1554#define RCC_ADC34PLLCLK_DIV4 RCC_CFGR2_ADCPRE34_DIV4
1555#define RCC_ADC34PLLCLK_DIV6 RCC_CFGR2_ADCPRE34_DIV6
1556#define RCC_ADC34PLLCLK_DIV8 RCC_CFGR2_ADCPRE34_DIV8
1557#define RCC_ADC34PLLCLK_DIV10 RCC_CFGR2_ADCPRE34_DIV10
1558#define RCC_ADC34PLLCLK_DIV12 RCC_CFGR2_ADCPRE34_DIV12
1559#define RCC_ADC34PLLCLK_DIV16 RCC_CFGR2_ADCPRE34_DIV16
1560#define RCC_ADC34PLLCLK_DIV32 RCC_CFGR2_ADCPRE34_DIV32
1561#define RCC_ADC34PLLCLK_DIV64 RCC_CFGR2_ADCPRE34_DIV64
1562#define RCC_ADC34PLLCLK_DIV128 RCC_CFGR2_ADCPRE34_DIV128
1563#define RCC_ADC34PLLCLK_DIV256 RCC_CFGR2_ADCPRE34_DIV256
1564
1572#define RCC_TIM8CLK_HCLK RCC_CFGR3_TIM8SW_HCLK
1573#define RCC_TIM8CLK_PLLCLK RCC_CFGR3_TIM8SW_PLL
1574
1579#endif /* STM32F303xC || STM32F303xE || STM32F398xx || STM32F358xx */
1580
1581#if defined(STM32F303x8) || defined(STM32F334x8) || defined(STM32F328xx)
1582
1586#define RCC_USART1CLKSOURCE_PCLK1 RCC_CFGR3_USART1SW_PCLK1
1587#define RCC_USART1CLKSOURCE_SYSCLK RCC_CFGR3_USART1SW_SYSCLK
1588#define RCC_USART1CLKSOURCE_LSE RCC_CFGR3_USART1SW_LSE
1589#define RCC_USART1CLKSOURCE_HSI RCC_CFGR3_USART1SW_HSI
1590
1598/* ADC1 & ADC2 */
1599#define RCC_ADC12PLLCLK_OFF RCC_CFGR2_ADCPRE12_NO
1600#define RCC_ADC12PLLCLK_DIV1 RCC_CFGR2_ADCPRE12_DIV1
1601#define RCC_ADC12PLLCLK_DIV2 RCC_CFGR2_ADCPRE12_DIV2
1602#define RCC_ADC12PLLCLK_DIV4 RCC_CFGR2_ADCPRE12_DIV4
1603#define RCC_ADC12PLLCLK_DIV6 RCC_CFGR2_ADCPRE12_DIV6
1604#define RCC_ADC12PLLCLK_DIV8 RCC_CFGR2_ADCPRE12_DIV8
1605#define RCC_ADC12PLLCLK_DIV10 RCC_CFGR2_ADCPRE12_DIV10
1606#define RCC_ADC12PLLCLK_DIV12 RCC_CFGR2_ADCPRE12_DIV12
1607#define RCC_ADC12PLLCLK_DIV16 RCC_CFGR2_ADCPRE12_DIV16
1608#define RCC_ADC12PLLCLK_DIV32 RCC_CFGR2_ADCPRE12_DIV32
1609#define RCC_ADC12PLLCLK_DIV64 RCC_CFGR2_ADCPRE12_DIV64
1610#define RCC_ADC12PLLCLK_DIV128 RCC_CFGR2_ADCPRE12_DIV128
1611#define RCC_ADC12PLLCLK_DIV256 RCC_CFGR2_ADCPRE12_DIV256
1612
1620#define RCC_TIM1CLK_HCLK RCC_CFGR3_TIM1SW_HCLK
1621#define RCC_TIM1CLK_PLLCLK RCC_CFGR3_TIM1SW_PLL
1622
1627#endif /* STM32F303x8 || STM32F334x8 || STM32F328xx */
1628
1629#if defined(STM32F334x8)
1630
1634#define RCC_HRTIM1CLK_HCLK RCC_CFGR3_HRTIM1SW_HCLK
1635#define RCC_HRTIM1CLK_PLLCLK RCC_CFGR3_HRTIM1SW_PLL
1636
1641#endif /* STM32F334x8 */
1642
1643#if defined(STM32F373xC) || defined(STM32F378xx)
1644
1648#define RCC_USART1CLKSOURCE_PCLK2 RCC_CFGR3_USART1SW_PCLK2
1649#define RCC_USART1CLKSOURCE_SYSCLK RCC_CFGR3_USART1SW_SYSCLK
1650#define RCC_USART1CLKSOURCE_LSE RCC_CFGR3_USART1SW_LSE
1651#define RCC_USART1CLKSOURCE_HSI RCC_CFGR3_USART1SW_HSI
1652
1660#define RCC_I2C2CLKSOURCE_HSI RCC_CFGR3_I2C2SW_HSI
1661#define RCC_I2C2CLKSOURCE_SYSCLK RCC_CFGR3_I2C2SW_SYSCLK
1662
1671/* ADC1 */
1672#define RCC_ADC1PCLK2_DIV2 RCC_CFGR_ADCPRE_DIV2
1673#define RCC_ADC1PCLK2_DIV4 RCC_CFGR_ADCPRE_DIV4
1674#define RCC_ADC1PCLK2_DIV6 RCC_CFGR_ADCPRE_DIV6
1675#define RCC_ADC1PCLK2_DIV8 RCC_CFGR_ADCPRE_DIV8
1676
1684#define RCC_CECCLKSOURCE_HSI RCC_CFGR3_CECSW_HSI_DIV244
1685#define RCC_CECCLKSOURCE_LSE RCC_CFGR3_CECSW_LSE
1686
1694#define RCC_SDADCSYSCLK_DIV1 RCC_CFGR_SDPRE_DIV1
1695#define RCC_SDADCSYSCLK_DIV2 RCC_CFGR_SDPRE_DIV2
1696#define RCC_SDADCSYSCLK_DIV4 RCC_CFGR_SDPRE_DIV4
1697#define RCC_SDADCSYSCLK_DIV6 RCC_CFGR_SDPRE_DIV6
1698#define RCC_SDADCSYSCLK_DIV8 RCC_CFGR_SDPRE_DIV8
1699#define RCC_SDADCSYSCLK_DIV10 RCC_CFGR_SDPRE_DIV10
1700#define RCC_SDADCSYSCLK_DIV12 RCC_CFGR_SDPRE_DIV12
1701#define RCC_SDADCSYSCLK_DIV14 RCC_CFGR_SDPRE_DIV14
1702#define RCC_SDADCSYSCLK_DIV16 RCC_CFGR_SDPRE_DIV16
1703#define RCC_SDADCSYSCLK_DIV20 RCC_CFGR_SDPRE_DIV20
1704#define RCC_SDADCSYSCLK_DIV24 RCC_CFGR_SDPRE_DIV24
1705#define RCC_SDADCSYSCLK_DIV28 RCC_CFGR_SDPRE_DIV28
1706#define RCC_SDADCSYSCLK_DIV32 RCC_CFGR_SDPRE_DIV32
1707#define RCC_SDADCSYSCLK_DIV36 RCC_CFGR_SDPRE_DIV36
1708#define RCC_SDADCSYSCLK_DIV40 RCC_CFGR_SDPRE_DIV40
1709#define RCC_SDADCSYSCLK_DIV44 RCC_CFGR_SDPRE_DIV44
1710#define RCC_SDADCSYSCLK_DIV48 RCC_CFGR_SDPRE_DIV48
1711
1716#endif /* STM32F373xC || STM32F378xx */
1717
1718#if defined(STM32F302xE) || defined(STM32F303xE)\
1719 || defined(STM32F302xC) || defined(STM32F303xC)\
1720 || defined(STM32F302x8) \
1721 || defined(STM32F373xC)
1726#define RCC_USBCLKSOURCE_PLL RCC_CFGR_USBPRE_DIV1
1727#define RCC_USBCLKSOURCE_PLL_DIV1_5 RCC_CFGR_USBPRE_DIV1_5
1728
1733#endif /* STM32F302xE || STM32F303xE || */
1734 /* STM32F302xC || STM32F303xC || */
1735 /* STM32F302x8 || */
1736 /* STM32F373xC */
1737
1738
1742#if defined(RCC_CFGR_MCOPRE)
1743
1744#define RCC_MCODIV_1 (0x00000000U)
1745#define RCC_MCODIV_2 (0x10000000U)
1746#define RCC_MCODIV_4 (0x20000000U)
1747#define RCC_MCODIV_8 (0x30000000U)
1748#define RCC_MCODIV_16 (0x40000000U)
1749#define RCC_MCODIV_32 (0x50000000U)
1750#define RCC_MCODIV_64 (0x60000000U)
1751#define RCC_MCODIV_128 (0x70000000U)
1752
1753#else
1754
1755#define RCC_MCODIV_1 (0x00000000U)
1756
1757#endif /* RCC_CFGR_MCOPRE */
1758
1767#define RCC_LSEDRIVE_LOW (0x00000000U)
1768#define RCC_LSEDRIVE_MEDIUMLOW RCC_BDCR_LSEDRV_1
1769#define RCC_LSEDRIVE_MEDIUMHIGH RCC_BDCR_LSEDRV_0
1770#define RCC_LSEDRIVE_HIGH RCC_BDCR_LSEDRV
1780/* Exported macro ------------------------------------------------------------*/
1788#if defined(STM32F302xE) || defined(STM32F303xE) || defined(STM32F398xx)
1802#define __HAL_RCC_PLL_CONFIG(__RCC_PLLSource__ , __PREDIV__, __PLLMUL__) \
1803 do { \
1804 MODIFY_REG(RCC->CFGR2, RCC_CFGR2_PREDIV, (__PREDIV__)); \
1805 MODIFY_REG(RCC->CFGR, RCC_CFGR_PLLMUL | RCC_CFGR_PLLSRC, (uint32_t)((__PLLMUL__)|(__RCC_PLLSource__))); \
1806 } while(0U)
1807#endif /* STM32F302xE || STM32F303xE || STM32F398xx */
1808
1809#if defined(STM32F302xC) || defined(STM32F303xC) || defined(STM32F358xx)\
1810 || defined(STM32F303x8) || defined(STM32F334x8) || defined(STM32F328xx)\
1811 || defined(STM32F301x8) || defined(STM32F302x8) || defined(STM32F318xx)\
1812 || defined(STM32F373xC) || defined(STM32F378xx)
1824#define __HAL_RCC_PLL_CONFIG(__RCC_PLLSource__ , __PLLMUL__) \
1825 MODIFY_REG(RCC->CFGR, RCC_CFGR_PLLMUL | RCC_CFGR_PLLSRC, (uint32_t)((__PLLMUL__)|(__RCC_PLLSource__)))
1826#endif /* STM32F302xC || STM32F303xC || STM32F358xx || */
1827 /* STM32F303x8 || STM32F334x8 || STM32F328xx || */
1828 /* STM32F301x8 || STM32F302x8 || STM32F318xx */
1829 /* STM32F373xC || STM32F378xx */
1834#if defined(STM32F302xC) || defined(STM32F303xC) || defined(STM32F358xx)\
1835 || defined(STM32F303x8) || defined(STM32F334x8) || defined(STM32F328xx)\
1836 || defined(STM32F301x8) || defined(STM32F302x8) || defined(STM32F318xx)\
1837 || defined(STM32F373xC) || defined(STM32F378xx)
1850#define __HAL_RCC_HSE_PREDIV_CONFIG(__HSE_PREDIV_VALUE__) \
1851 MODIFY_REG(RCC->CFGR2, RCC_CFGR2_PREDIV, (uint32_t)(__HSE_PREDIV_VALUE__))
1852
1856#define __HAL_RCC_HSE_GET_PREDIV() READ_BIT(RCC->CFGR2, RCC_CFGR2_PREDIV)
1857
1861#endif /* STM32F302xC || STM32F303xC || STM32F358xx || */
1862 /* STM32F303x8 || STM32F334x8 || STM32F328xx || */
1863 /* STM32F301x8 || STM32F302x8 || STM32F318xx */
1864 /* STM32F373xC || STM32F378xx */
1865
1873#if defined(STM32F301x8) || defined(STM32F302x8) || defined(STM32F318xx)
1874#define __HAL_RCC_ADC1_CLK_ENABLE() do { \
1875 __IO uint32_t tmpreg; \
1876 SET_BIT(RCC->AHBENR, RCC_AHBENR_ADC1EN);\
1877 /* Delay after an RCC peripheral clock enabling */ \
1878 tmpreg = READ_BIT(RCC->AHBENR, RCC_AHBENR_ADC1EN);\
1879 UNUSED(tmpreg); \
1880 } while(0U)
1881
1882#define __HAL_RCC_ADC1_CLK_DISABLE() (RCC->AHBENR &= ~(RCC_AHBENR_ADC1EN))
1883#endif /* STM32F301x8 || STM32F302x8 || STM32F318xx */
1884
1885#if defined(STM32F302xE) || defined(STM32F303xE) || defined(STM32F398xx)\
1886 || defined(STM32F302xC) || defined(STM32F303xC) || defined(STM32F358xx)
1887#define __HAL_RCC_DMA2_CLK_ENABLE() do { \
1888 __IO uint32_t tmpreg; \
1889 SET_BIT(RCC->AHBENR, RCC_AHBENR_DMA2EN);\
1890 /* Delay after an RCC peripheral clock enabling */ \
1891 tmpreg = READ_BIT(RCC->AHBENR, RCC_AHBENR_DMA2EN);\
1892 UNUSED(tmpreg); \
1893 } while(0U)
1894#define __HAL_RCC_GPIOE_CLK_ENABLE() do { \
1895 __IO uint32_t tmpreg; \
1896 SET_BIT(RCC->AHBENR, RCC_AHBENR_GPIOEEN);\
1897 /* Delay after an RCC peripheral clock enabling */ \
1898 tmpreg = READ_BIT(RCC->AHBENR, RCC_AHBENR_GPIOEEN);\
1899 UNUSED(tmpreg); \
1900 } while(0U)
1901#define __HAL_RCC_ADC12_CLK_ENABLE() do { \
1902 __IO uint32_t tmpreg; \
1903 SET_BIT(RCC->AHBENR, RCC_AHBENR_ADC12EN);\
1904 /* Delay after an RCC peripheral clock enabling */ \
1905 tmpreg = READ_BIT(RCC->AHBENR, RCC_AHBENR_ADC12EN);\
1906 UNUSED(tmpreg); \
1907 } while(0U)
1908/* Aliases for STM32 F3 compatibility */
1909#define __HAL_RCC_ADC1_CLK_ENABLE() __HAL_RCC_ADC12_CLK_ENABLE()
1910#define __HAL_RCC_ADC2_CLK_ENABLE() __HAL_RCC_ADC12_CLK_ENABLE()
1911
1912#define __HAL_RCC_DMA2_CLK_DISABLE() (RCC->AHBENR &= ~(RCC_AHBENR_DMA2EN))
1913#define __HAL_RCC_GPIOE_CLK_DISABLE() (RCC->AHBENR &= ~(RCC_AHBENR_GPIOEEN))
1914#define __HAL_RCC_ADC12_CLK_DISABLE() (RCC->AHBENR &= ~(RCC_AHBENR_ADC12EN))
1915/* Aliases for STM32 F3 compatibility */
1916#define __HAL_RCC_ADC1_CLK_DISABLE() __HAL_RCC_ADC12_CLK_DISABLE()
1917#define __HAL_RCC_ADC2_CLK_DISABLE() __HAL_RCC_ADC12_CLK_DISABLE()
1918#endif /* STM32F302xE || STM32F303xE || STM32F398xx || */
1919 /* STM32F302xC || STM32F303xC || STM32F358xx */
1920
1921#if defined(STM32F303xE) || defined(STM32F398xx)\
1922 || defined(STM32F303xC) || defined(STM32F358xx)
1923#define __HAL_RCC_ADC34_CLK_ENABLE() do { \
1924 __IO uint32_t tmpreg; \
1925 SET_BIT(RCC->AHBENR, RCC_AHBENR_ADC34EN);\
1926 /* Delay after an RCC peripheral clock enabling */ \
1927 tmpreg = READ_BIT(RCC->AHBENR, RCC_AHBENR_ADC34EN);\
1928 UNUSED(tmpreg); \
1929 } while(0U)
1930#define __HAL_RCC_ADC34_CLK_DISABLE() (RCC->AHBENR &= ~(RCC_AHBENR_ADC34EN))
1931#endif /* STM32F303xE || STM32F398xx || */
1932 /* STM32F303xC || STM32F358xx */
1933
1934#if defined(STM32F303x8) || defined(STM32F334x8) || defined(STM32F328xx)
1935#define __HAL_RCC_ADC12_CLK_ENABLE() do { \
1936 __IO uint32_t tmpreg; \
1937 SET_BIT(RCC->AHBENR, RCC_AHBENR_ADC12EN);\
1938 /* Delay after an RCC peripheral clock enabling */ \
1939 tmpreg = READ_BIT(RCC->AHBENR, RCC_AHBENR_ADC12EN);\
1940 UNUSED(tmpreg); \
1941 } while(0U)
1942/* Aliases for STM32 F3 compatibility */
1943#define __HAL_RCC_ADC1_CLK_ENABLE() __HAL_RCC_ADC12_CLK_ENABLE()
1944#define __HAL_RCC_ADC2_CLK_ENABLE() __HAL_RCC_ADC12_CLK_ENABLE()
1945
1946#define __HAL_RCC_ADC12_CLK_DISABLE() (RCC->AHBENR &= ~(RCC_AHBENR_ADC12EN))
1947/* Aliases for STM32 F3 compatibility */
1948#define __HAL_RCC_ADC1_CLK_DISABLE() __HAL_RCC_ADC12_CLK_DISABLE()
1949#define __HAL_RCC_ADC2_CLK_DISABLE() __HAL_RCC_ADC12_CLK_DISABLE()
1950#endif /* STM32F303x8 || STM32F334x8 || STM32F328xx */
1951
1952#if defined(STM32F373xC) || defined(STM32F378xx)
1953#define __HAL_RCC_DMA2_CLK_ENABLE() do { \
1954 __IO uint32_t tmpreg; \
1955 SET_BIT(RCC->AHBENR, RCC_AHBENR_DMA2EN);\
1956 /* Delay after an RCC peripheral clock enabling */ \
1957 tmpreg = READ_BIT(RCC->AHBENR, RCC_AHBENR_DMA2EN);\
1958 UNUSED(tmpreg); \
1959 } while(0U)
1960#define __HAL_RCC_GPIOE_CLK_ENABLE() do { \
1961 __IO uint32_t tmpreg; \
1962 SET_BIT(RCC->AHBENR, RCC_AHBENR_GPIOEEN);\
1963 /* Delay after an RCC peripheral clock enabling */ \
1964 tmpreg = READ_BIT(RCC->AHBENR, RCC_AHBENR_GPIOEEN);\
1965 UNUSED(tmpreg); \
1966 } while(0U)
1967
1968#define __HAL_RCC_DMA2_CLK_DISABLE() (RCC->AHBENR &= ~(RCC_AHBENR_DMA2EN))
1969#define __HAL_RCC_GPIOE_CLK_DISABLE() (RCC->AHBENR &= ~(RCC_AHBENR_GPIOEEN))
1970#endif /* STM32F373xC || STM32F378xx */
1971
1972#if defined(STM32F302xE) || defined(STM32F303xE) || defined(STM32F398xx)
1973#define __HAL_RCC_FMC_CLK_ENABLE() do { \
1974 __IO uint32_t tmpreg; \
1975 SET_BIT(RCC->AHBENR, RCC_AHBENR_FMCEN);\
1976 /* Delay after an RCC peripheral clock enabling */ \
1977 tmpreg = READ_BIT(RCC->AHBENR, RCC_AHBENR_FMCEN);\
1978 UNUSED(tmpreg); \
1979 } while(0U)
1980#define __HAL_RCC_GPIOG_CLK_ENABLE() do { \
1981 __IO uint32_t tmpreg; \
1982 SET_BIT(RCC->AHBENR, RCC_AHBENR_GPIOGEN);\
1983 /* Delay after an RCC peripheral clock enabling */ \
1984 tmpreg = READ_BIT(RCC->AHBENR, RCC_AHBENR_GPIOGEN);\
1985 UNUSED(tmpreg); \
1986 } while(0U)
1987#define __HAL_RCC_GPIOH_CLK_ENABLE() do { \
1988 __IO uint32_t tmpreg; \
1989 SET_BIT(RCC->AHBENR, RCC_AHBENR_GPIOHEN);\
1990 /* Delay after an RCC peripheral clock enabling */ \
1991 tmpreg = READ_BIT(RCC->AHBENR, RCC_AHBENR_GPIOHEN);\
1992 UNUSED(tmpreg); \
1993 } while(0U)
1994
1995#define __HAL_RCC_FMC_CLK_DISABLE() (RCC->AHBENR &= ~(RCC_AHBENR_FMCEN))
1996#define __HAL_RCC_GPIOG_CLK_DISABLE() (RCC->AHBENR &= ~(RCC_AHBENR_GPIOGEN))
1997#define __HAL_RCC_GPIOH_CLK_DISABLE() (RCC->AHBENR &= ~(RCC_AHBENR_GPIOHEN))
1998#endif /* STM32F302xE || STM32F303xE || STM32F398xx */
2010#if defined(STM32F301x8) || defined(STM32F302x8) || defined(STM32F318xx)
2011#define __HAL_RCC_SPI2_CLK_ENABLE() do { \
2012 __IO uint32_t tmpreg; \
2013 SET_BIT(RCC->APB1ENR, RCC_APB1ENR_SPI2EN);\
2014 /* Delay after an RCC peripheral clock enabling */ \
2015 tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_SPI2EN);\
2016 UNUSED(tmpreg); \
2017 } while(0U)
2018#define __HAL_RCC_SPI3_CLK_ENABLE() do { \
2019 __IO uint32_t tmpreg; \
2020 SET_BIT(RCC->APB1ENR, RCC_APB1ENR_SPI3EN);\
2021 /* Delay after an RCC peripheral clock enabling */ \
2022 tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_SPI3EN);\
2023 UNUSED(tmpreg); \
2024 } while(0U)
2025#define __HAL_RCC_I2C2_CLK_ENABLE() do { \
2026 __IO uint32_t tmpreg; \
2027 SET_BIT(RCC->APB1ENR, RCC_APB1ENR_I2C2EN);\
2028 /* Delay after an RCC peripheral clock enabling */ \
2029 tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_I2C2EN);\
2030 UNUSED(tmpreg); \
2031 } while(0U)
2032#define __HAL_RCC_I2C3_CLK_ENABLE() do { \
2033 __IO uint32_t tmpreg; \
2034 SET_BIT(RCC->APB1ENR, RCC_APB1ENR_I2C3EN);\
2035 /* Delay after an RCC peripheral clock enabling */ \
2036 tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_I2C3EN);\
2037 UNUSED(tmpreg); \
2038 } while(0U)
2039
2040#define __HAL_RCC_SPI2_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_SPI2EN))
2041#define __HAL_RCC_SPI3_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_SPI3EN))
2042#define __HAL_RCC_I2C2_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_I2C2EN))
2043#define __HAL_RCC_I2C3_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_I2C3EN))
2044#endif /* STM32F301x8 || STM32F302x8 || STM32F318xx */
2045
2046#if defined(STM32F302xE) || defined(STM32F303xE) || defined(STM32F398xx)\
2047 || defined(STM32F302xC) || defined(STM32F303xC) || defined(STM32F358xx)
2048#define __HAL_RCC_TIM3_CLK_ENABLE() do { \
2049 __IO uint32_t tmpreg; \
2050 SET_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM3EN);\
2051 /* Delay after an RCC peripheral clock enabling */ \
2052 tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM3EN);\
2053 UNUSED(tmpreg); \
2054 } while(0U)
2055#define __HAL_RCC_TIM4_CLK_ENABLE() do { \
2056 __IO uint32_t tmpreg; \
2057 SET_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM4EN);\
2058 /* Delay after an RCC peripheral clock enabling */ \
2059 tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM4EN);\
2060 UNUSED(tmpreg); \
2061 } while(0U)
2062#define __HAL_RCC_SPI2_CLK_ENABLE() do { \
2063 __IO uint32_t tmpreg; \
2064 SET_BIT(RCC->APB1ENR, RCC_APB1ENR_SPI2EN);\
2065 /* Delay after an RCC peripheral clock enabling */ \
2066 tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_SPI2EN);\
2067 UNUSED(tmpreg); \
2068 } while(0U)
2069#define __HAL_RCC_SPI3_CLK_ENABLE() do { \
2070 __IO uint32_t tmpreg; \
2071 SET_BIT(RCC->APB1ENR, RCC_APB1ENR_SPI3EN);\
2072 /* Delay after an RCC peripheral clock enabling */ \
2073 tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_SPI3EN);\
2074 UNUSED(tmpreg); \
2075 } while(0U)
2076#define __HAL_RCC_UART4_CLK_ENABLE() do { \
2077 __IO uint32_t tmpreg; \
2078 SET_BIT(RCC->APB1ENR, RCC_APB1ENR_UART4EN);\
2079 /* Delay after an RCC peripheral clock enabling */ \
2080 tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_UART4EN);\
2081 UNUSED(tmpreg); \
2082 } while(0U)
2083#define __HAL_RCC_UART5_CLK_ENABLE() do { \
2084 __IO uint32_t tmpreg; \
2085 SET_BIT(RCC->APB1ENR, RCC_APB1ENR_UART5EN);\
2086 /* Delay after an RCC peripheral clock enabling */ \
2087 tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_UART5EN);\
2088 UNUSED(tmpreg); \
2089 } while(0U)
2090#define __HAL_RCC_I2C2_CLK_ENABLE() do { \
2091 __IO uint32_t tmpreg; \
2092 SET_BIT(RCC->APB1ENR, RCC_APB1ENR_I2C2EN);\
2093 /* Delay after an RCC peripheral clock enabling */ \
2094 tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_I2C2EN);\
2095 UNUSED(tmpreg); \
2096 } while(0U)
2097
2098#define __HAL_RCC_TIM3_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM3EN))
2099#define __HAL_RCC_TIM4_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM4EN))
2100#define __HAL_RCC_SPI2_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_SPI2EN))
2101#define __HAL_RCC_SPI3_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_SPI3EN))
2102#define __HAL_RCC_UART4_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_UART4EN))
2103#define __HAL_RCC_UART5_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_UART5EN))
2104#define __HAL_RCC_I2C2_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_I2C2EN))
2105#endif /* STM32F302xE || STM32F303xE || STM32F398xx || */
2106 /* STM32F302xC || STM32F303xC || STM32F358xx */
2107
2108#if defined(STM32F303x8) || defined(STM32F334x8) || defined(STM32F328xx)
2109#define __HAL_RCC_TIM3_CLK_ENABLE() do { \
2110 __IO uint32_t tmpreg; \
2111 SET_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM3EN);\
2112 /* Delay after an RCC peripheral clock enabling */ \
2113 tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM3EN);\
2114 UNUSED(tmpreg); \
2115 } while(0U)
2116#define __HAL_RCC_DAC2_CLK_ENABLE() do { \
2117 __IO uint32_t tmpreg; \
2118 SET_BIT(RCC->APB1ENR, RCC_APB1ENR_DAC2EN);\
2119 /* Delay after an RCC peripheral clock enabling */ \
2120 tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_DAC2EN);\
2121 UNUSED(tmpreg); \
2122 } while(0U)
2123
2124#define __HAL_RCC_TIM3_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM3EN))
2125#define __HAL_RCC_DAC2_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_DAC2EN))
2126#endif /* STM32F303x8 || STM32F334x8 || STM32F328xx */
2127
2128#if defined(STM32F373xC) || defined(STM32F378xx)
2129#define __HAL_RCC_TIM3_CLK_ENABLE() do { \
2130 __IO uint32_t tmpreg; \
2131 SET_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM3EN);\
2132 /* Delay after an RCC peripheral clock enabling */ \
2133 tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM3EN);\
2134 UNUSED(tmpreg); \
2135 } while(0U)
2136#define __HAL_RCC_TIM4_CLK_ENABLE() do { \
2137 __IO uint32_t tmpreg; \
2138 SET_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM4EN);\
2139 /* Delay after an RCC peripheral clock enabling */ \
2140 tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM4EN);\
2141 UNUSED(tmpreg); \
2142 } while(0U)
2143#define __HAL_RCC_TIM5_CLK_ENABLE() do { \
2144 __IO uint32_t tmpreg; \
2145 SET_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM5EN);\
2146 /* Delay after an RCC peripheral clock enabling */ \
2147 tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM5EN);\
2148 UNUSED(tmpreg); \
2149 } while(0U)
2150#define __HAL_RCC_TIM12_CLK_ENABLE() do { \
2151 __IO uint32_t tmpreg; \
2152 SET_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM12EN);\
2153 /* Delay after an RCC peripheral clock enabling */ \
2154 tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM12EN);\
2155 UNUSED(tmpreg); \
2156 } while(0U)
2157#define __HAL_RCC_TIM13_CLK_ENABLE() do { \
2158 __IO uint32_t tmpreg; \
2159 SET_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM13EN);\
2160 /* Delay after an RCC peripheral clock enabling */ \
2161 tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM13EN);\
2162 UNUSED(tmpreg); \
2163 } while(0U)
2164#define __HAL_RCC_TIM14_CLK_ENABLE() do { \
2165 __IO uint32_t tmpreg; \
2166 SET_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM14EN);\
2167 /* Delay after an RCC peripheral clock enabling */ \
2168 tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM14EN);\
2169 UNUSED(tmpreg); \
2170 } while(0U)
2171#define __HAL_RCC_TIM18_CLK_ENABLE() do { \
2172 __IO uint32_t tmpreg; \
2173 SET_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM18EN);\
2174 /* Delay after an RCC peripheral clock enabling */ \
2175 tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM18EN);\
2176 UNUSED(tmpreg); \
2177 } while(0U)
2178#define __HAL_RCC_SPI2_CLK_ENABLE() do { \
2179 __IO uint32_t tmpreg; \
2180 SET_BIT(RCC->APB1ENR, RCC_APB1ENR_SPI2EN);\
2181 /* Delay after an RCC peripheral clock enabling */ \
2182 tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_SPI2EN);\
2183 UNUSED(tmpreg); \
2184 } while(0U)
2185#define __HAL_RCC_SPI3_CLK_ENABLE() do { \
2186 __IO uint32_t tmpreg; \
2187 SET_BIT(RCC->APB1ENR, RCC_APB1ENR_SPI3EN);\
2188 /* Delay after an RCC peripheral clock enabling */ \
2189 tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_SPI3EN);\
2190 UNUSED(tmpreg); \
2191 } while(0U)
2192#define __HAL_RCC_I2C2_CLK_ENABLE() do { \
2193 __IO uint32_t tmpreg; \
2194 SET_BIT(RCC->APB1ENR, RCC_APB1ENR_I2C2EN);\
2195 /* Delay after an RCC peripheral clock enabling */ \
2196 tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_I2C2EN);\
2197 UNUSED(tmpreg); \
2198 } while(0U)
2199#define __HAL_RCC_DAC2_CLK_ENABLE() do { \
2200 __IO uint32_t tmpreg; \
2201 SET_BIT(RCC->APB1ENR, RCC_APB1ENR_DAC2EN);\
2202 /* Delay after an RCC peripheral clock enabling */ \
2203 tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_DAC2EN);\
2204 UNUSED(tmpreg); \
2205 } while(0U)
2206#define __HAL_RCC_CEC_CLK_ENABLE() do { \
2207 __IO uint32_t tmpreg; \
2208 SET_BIT(RCC->APB1ENR, RCC_APB1ENR_CECEN);\
2209 /* Delay after an RCC peripheral clock enabling */ \
2210 tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_CECEN);\
2211 UNUSED(tmpreg); \
2212 } while(0U)
2213
2214#define __HAL_RCC_TIM3_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM3EN))
2215#define __HAL_RCC_TIM4_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM4EN))
2216#define __HAL_RCC_TIM5_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM5EN))
2217#define __HAL_RCC_TIM12_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM12EN))
2218#define __HAL_RCC_TIM13_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM13EN))
2219#define __HAL_RCC_TIM14_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM14EN))
2220#define __HAL_RCC_TIM18_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM18EN))
2221#define __HAL_RCC_SPI2_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_SPI2EN))
2222#define __HAL_RCC_SPI3_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_SPI3EN))
2223#define __HAL_RCC_I2C2_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_I2C2EN))
2224#define __HAL_RCC_DAC2_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_DAC2EN))
2225#define __HAL_RCC_CEC_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_CECEN))
2226#endif /* STM32F373xC || STM32F378xx */
2227
2228#if defined(STM32F303xE) || defined(STM32F398xx) \
2229 || defined(STM32F303xC) || defined(STM32F358xx) \
2230 || defined(STM32F303x8) || defined(STM32F334x8) || defined(STM32F328xx)\
2231 || defined(STM32F373xC) || defined(STM32F378xx)
2232#define __HAL_RCC_TIM7_CLK_ENABLE() do { \
2233 __IO uint32_t tmpreg; \
2234 SET_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM7EN);\
2235 /* Delay after an RCC peripheral clock enabling */ \
2236 tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM7EN);\
2237 UNUSED(tmpreg); \
2238 } while(0U)
2239
2240#define __HAL_RCC_TIM7_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM7EN))
2241#endif /* STM32F303xE || STM32F398xx || */
2242 /* STM32F303xC || STM32F358xx || */
2243 /* STM32F303x8 || STM32F334x8 || STM32F328xx || */
2244 /* STM32F373xC || STM32F378xx */
2245
2246#if defined(STM32F302xE) || defined(STM32F303xE)\
2247 || defined(STM32F302xC) || defined(STM32F303xC)\
2248 || defined(STM32F302x8) \
2249 || defined(STM32F373xC)
2250#define __HAL_RCC_USB_CLK_ENABLE() do { \
2251 __IO uint32_t tmpreg; \
2252 SET_BIT(RCC->APB1ENR, RCC_APB1ENR_USBEN);\
2253 /* Delay after an RCC peripheral clock enabling */ \
2254 tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_USBEN);\
2255 UNUSED(tmpreg); \
2256 } while(0U)
2257
2258#define __HAL_RCC_USB_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_USBEN))
2259#endif /* STM32F302xE || STM32F303xE || */
2260 /* STM32F302xC || STM32F303xC || */
2261 /* STM32F302x8 || */
2262 /* STM32F373xC */
2263
2264#if !defined(STM32F301x8)
2265#define __HAL_RCC_CAN1_CLK_ENABLE() do { \
2266 __IO uint32_t tmpreg; \
2267 SET_BIT(RCC->APB1ENR, RCC_APB1ENR_CANEN);\
2268 /* Delay after an RCC peripheral clock enabling */ \
2269 tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_CANEN);\
2270 UNUSED(tmpreg); \
2271 } while(0U)
2272
2273#define __HAL_RCC_CAN1_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_CANEN))
2274#endif /* STM32F301x8*/
2275
2276#if defined(STM32F302xE) || defined(STM32F303xE) || defined(STM32F398xx)
2277#define __HAL_RCC_I2C3_CLK_ENABLE() do { \
2278 __IO uint32_t tmpreg; \
2279 SET_BIT(RCC->APB1ENR, RCC_APB1ENR_I2C3EN);\
2280 /* Delay after an RCC peripheral clock enabling */ \
2281 tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_I2C3EN);\
2282 UNUSED(tmpreg); \
2283 } while(0U)
2284
2285#define __HAL_RCC_I2C3_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_I2C3EN))
2286#endif /* STM32F302xE || STM32F303xE || STM32F398xx */
2298#if defined(STM32F302xE) || defined(STM32F303xE) || defined(STM32F398xx)\
2299 || defined(STM32F302xC) || defined(STM32F303xC) || defined(STM32F358xx)
2300#define __HAL_RCC_SPI1_CLK_ENABLE() do { \
2301 __IO uint32_t tmpreg; \
2302 SET_BIT(RCC->APB2ENR, RCC_APB2ENR_SPI1EN);\
2303 /* Delay after an RCC peripheral clock enabling */ \
2304 tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_SPI1EN);\
2305 UNUSED(tmpreg); \
2306 } while(0U)
2307
2308#define __HAL_RCC_SPI1_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_SPI1EN))
2309#endif /* STM32F302xE || STM32F303xE || STM32F398xx || */
2310 /* STM32F302xC || STM32F303xC || STM32F358xx */
2311
2312#if defined(STM32F303xE) || defined(STM32F398xx)\
2313 || defined(STM32F303xC) || defined(STM32F358xx)
2314#define __HAL_RCC_TIM8_CLK_ENABLE() do { \
2315 __IO uint32_t tmpreg; \
2316 SET_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM8EN);\
2317 /* Delay after an RCC peripheral clock enabling */ \
2318 tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM8EN);\
2319 UNUSED(tmpreg); \
2320 } while(0U)
2321
2322#define __HAL_RCC_TIM8_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_TIM8EN))
2323#endif /* STM32F303xE || STM32F398xx || */
2324 /* STM32F303xC || STM32F358xx */
2325
2326#if defined(STM32F303x8) || defined(STM32F334x8) || defined(STM32F328xx)
2327#define __HAL_RCC_SPI1_CLK_ENABLE() do { \
2328 __IO uint32_t tmpreg; \
2329 SET_BIT(RCC->APB2ENR, RCC_APB2ENR_SPI1EN);\
2330 /* Delay after an RCC peripheral clock enabling */ \
2331 tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_SPI1EN);\
2332 UNUSED(tmpreg); \
2333 } while(0U)
2334
2335#define __HAL_RCC_SPI1_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_SPI1EN))
2336#endif /* STM32F303x8 || STM32F334x8 || STM32F328xx */
2337
2338#if defined(STM32F334x8)
2339#define __HAL_RCC_HRTIM1_CLK_ENABLE() do { \
2340 __IO uint32_t tmpreg; \
2341 SET_BIT(RCC->APB2ENR, RCC_APB2ENR_HRTIM1EN);\
2342 /* Delay after an RCC peripheral clock enabling */ \
2343 tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_HRTIM1EN);\
2344 UNUSED(tmpreg); \
2345 } while(0U)
2346
2347#define __HAL_RCC_HRTIM1_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_HRTIM1EN))
2348#endif /* STM32F334x8 */
2349
2350#if defined(STM32F373xC) || defined(STM32F378xx)
2351#define __HAL_RCC_ADC1_CLK_ENABLE() do { \
2352 __IO uint32_t tmpreg; \
2353 SET_BIT(RCC->APB2ENR, RCC_APB2ENR_ADC1EN);\
2354 /* Delay after an RCC peripheral clock enabling */ \
2355 tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_ADC1EN);\
2356 UNUSED(tmpreg); \
2357 } while(0U)
2358#define __HAL_RCC_SPI1_CLK_ENABLE() do { \
2359 __IO uint32_t tmpreg; \
2360 SET_BIT(RCC->APB2ENR, RCC_APB2ENR_SPI1EN);\
2361 /* Delay after an RCC peripheral clock enabling */ \
2362 tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_SPI1EN);\
2363 UNUSED(tmpreg); \
2364 } while(0U)
2365#define __HAL_RCC_TIM19_CLK_ENABLE() do { \
2366 __IO uint32_t tmpreg; \
2367 SET_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM19EN);\
2368 /* Delay after an RCC peripheral clock enabling */ \
2369 tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM19EN);\
2370 UNUSED(tmpreg); \
2371 } while(0U)
2372#define __HAL_RCC_SDADC1_CLK_ENABLE() do { \
2373 __IO uint32_t tmpreg; \
2374 SET_BIT(RCC->APB2ENR, RCC_APB2ENR_SDADC1EN);\
2375 /* Delay after an RCC peripheral clock enabling */ \
2376 tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_SDADC1EN);\
2377 UNUSED(tmpreg); \
2378 } while(0U)
2379#define __HAL_RCC_SDADC2_CLK_ENABLE() do { \
2380 __IO uint32_t tmpreg; \
2381 SET_BIT(RCC->APB2ENR, RCC_APB2ENR_SDADC2EN);\
2382 /* Delay after an RCC peripheral clock enabling */ \
2383 tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_SDADC2EN);\
2384 UNUSED(tmpreg); \
2385 } while(0U)
2386#define __HAL_RCC_SDADC3_CLK_ENABLE() do { \
2387 __IO uint32_t tmpreg; \
2388 SET_BIT(RCC->APB2ENR, RCC_APB2ENR_SDADC3EN);\
2389 /* Delay after an RCC peripheral clock enabling */ \
2390 tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_SDADC3EN);\
2391 UNUSED(tmpreg); \
2392 } while(0U)
2393
2394#define __HAL_RCC_ADC1_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_ADC1EN))
2395#define __HAL_RCC_SPI1_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_SPI1EN))
2396#define __HAL_RCC_TIM19_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_TIM19EN))
2397#define __HAL_RCC_SDADC1_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_SDADC1EN))
2398#define __HAL_RCC_SDADC2_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_SDADC2EN))
2399#define __HAL_RCC_SDADC3_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_SDADC3EN))
2400#endif /* STM32F373xC || STM32F378xx */
2401
2402#if defined(STM32F302xE) || defined(STM32F303xE) || defined(STM32F398xx)\
2403 || defined(STM32F302xC) || defined(STM32F303xC) || defined(STM32F358xx)\
2404 || defined(STM32F303x8) || defined(STM32F334x8) || defined(STM32F328xx)\
2405 || defined(STM32F301x8) || defined(STM32F302x8) || defined(STM32F318xx)
2406#define __HAL_RCC_TIM1_CLK_ENABLE() do { \
2407 __IO uint32_t tmpreg; \
2408 SET_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM1EN);\
2409 /* Delay after an RCC peripheral clock enabling */ \
2410 tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM1EN);\
2411 UNUSED(tmpreg); \
2412 } while(0U)
2413
2414#define __HAL_RCC_TIM1_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_TIM1EN))
2415#endif /* STM32F302xE || STM32F303xE || STM32F398xx || */
2416 /* STM32F302xC || STM32F303xC || STM32F358xx || */
2417 /* STM32F303x8 || STM32F334x8 || STM32F328xx || */
2418 /* STM32F301x8 || STM32F302x8 || STM32F318xx */
2419
2420#if defined(STM32F302xE) || defined(STM32F303xE) || defined(STM32F398xx)
2421#define __HAL_RCC_SPI4_CLK_ENABLE() do { \
2422 __IO uint32_t tmpreg; \
2423 SET_BIT(RCC->APB2ENR, RCC_APB2ENR_SPI4EN);\
2424 /* Delay after an RCC peripheral clock enabling */ \
2425 tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_SPI4EN);\
2426 UNUSED(tmpreg); \
2427 } while(0U)
2428
2429#define __HAL_RCC_SPI4_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_SPI4EN))
2430#endif /* STM32F302xE || STM32F303xE || STM32F398xx */
2431
2432#if defined(STM32F303xE) || defined(STM32F398xx)
2433#define __HAL_RCC_TIM20_CLK_ENABLE() do { \
2434 __IO uint32_t tmpreg; \
2435 SET_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM20EN);\
2436 /* Delay after an RCC peripheral clock enabling */ \
2437 tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM20EN);\
2438 UNUSED(tmpreg); \
2439 } while(0U)
2440#define __HAL_RCC_TIM20_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_TIM20EN))
2441#endif /* STM32F303xE || STM32F398xx */
2442
2454#if defined(STM32F301x8) || defined(STM32F302x8) || defined(STM32F318xx)
2455#define __HAL_RCC_ADC1_IS_CLK_ENABLED() ((RCC->AHBENR & (RCC_AHBENR_ADC1EN)) != RESET)
2456
2457#define __HAL_RCC_ADC1_IS_CLK_DISABLED() ((RCC->AHBENR & (RCC_AHBENR_ADC1EN)) == RESET)
2458#endif /* STM32F301x8 || STM32F302x8 || STM32F318xx */
2459
2460#if defined(STM32F302xE) || defined(STM32F303xE) || defined(STM32F398xx)\
2461 || defined(STM32F302xC) || defined(STM32F303xC) || defined(STM32F358xx)
2462#define __HAL_RCC_DMA2_IS_CLK_ENABLED() ((RCC->AHBENR & (RCC_AHBENR_DMA2EN)) != RESET)
2463#define __HAL_RCC_GPIOE_IS_CLK_ENABLED() ((RCC->AHBENR & (RCC_AHBENR_GPIOEEN)) != RESET)
2464#define __HAL_RCC_ADC12_IS_CLK_ENABLED() ((RCC->AHBENR & (RCC_AHBENR_ADC12EN)) != RESET)
2465
2466#define __HAL_RCC_DMA2_IS_CLK_DISABLED() ((RCC->AHBENR & (RCC_AHBENR_DMA2EN)) == RESET)
2467#define __HAL_RCC_GPIOE_IS_CLK_DISABLED() ((RCC->AHBENR & (RCC_AHBENR_GPIOEEN)) == RESET)
2468#define __HAL_RCC_ADC12_IS_CLK_DISABLED() ((RCC->AHBENR & (RCC_AHBENR_ADC12EN)) == RESET)
2469#endif /* STM32F302xE || STM32F303xE || STM32F398xx || */
2470 /* STM32F302xC || STM32F303xC || STM32F358xx */
2471
2472#if defined(STM32F303xE) || defined(STM32F398xx)\
2473 || defined(STM32F303xC) || defined(STM32F358xx)
2474#define __HAL_RCC_ADC34_IS_CLK_ENABLED() ((RCC->AHBENR & (RCC_AHBENR_ADC34EN)) != RESET)
2475
2476#define __HAL_RCC_ADC34_IS_CLK_DISABLED() ((RCC->AHBENR & (RCC_AHBENR_ADC34EN)) == RESET)
2477#endif /* STM32F303xE || STM32F398xx || */
2478 /* STM32F303xC || STM32F358xx */
2479
2480#if defined(STM32F303x8) || defined(STM32F334x8) || defined(STM32F328xx)
2481#define __HAL_RCC_ADC12_IS_CLK_ENABLED() ((RCC->AHBENR & (RCC_AHBENR_ADC12EN)) != RESET)
2482
2483#define __HAL_RCC_ADC12_IS_CLK_DISABLED() ((RCC->AHBENR & (RCC_AHBENR_ADC12EN)) == RESET)
2484#endif /* STM32F303x8 || STM32F334x8 || STM32F328xx */
2485
2486#if defined(STM32F373xC) || defined(STM32F378xx)
2487#define __HAL_RCC_DMA2_IS_CLK_ENABLED() ((RCC->AHBENR & (RCC_AHBENR_DMA2EN)) != RESET)
2488#define __HAL_RCC_GPIOE_IS_CLK_ENABLED() ((RCC->AHBENR & (RCC_AHBENR_GPIOEEN)) != RESET)
2489
2490#define __HAL_RCC_DMA2_IS_CLK_DISABLED() ((RCC->AHBENR & (RCC_AHBENR_DMA2EN)) == RESET)
2491#define __HAL_RCC_GPIOE_IS_CLK_DISABLED() ((RCC->AHBENR & (RCC_AHBENR_GPIOEEN)) == RESET)
2492#endif /* STM32F373xC || STM32F378xx */
2493
2494#if defined(STM32F302xE) || defined(STM32F303xE) || defined(STM32F398xx)
2495#define __HAL_RCC_FMC_IS_CLK_ENABLED() ((RCC->AHBENR & (RCC_AHBENR_FMCEN)) != RESET)
2496#define __HAL_RCC_GPIOG_IS_CLK_ENABLED() ((RCC->AHBENR & (RCC_AHBENR_GPIOGEN)) != RESET)
2497#define __HAL_RCC_GPIOH_IS_CLK_ENABLED() ((RCC->AHBENR & (RCC_AHBENR_GPIOHEN)) != RESET)
2498
2499#define __HAL_RCC_FMC_IS_CLK_DISABLED() ((RCC->AHBENR & (RCC_AHBENR_FMCEN)) == RESET)
2500#define __HAL_RCC_GPIOG_IS_CLK_DISABLED() ((RCC->AHBENR & (RCC_AHBENR_GPIOGEN)) == RESET)
2501#define __HAL_RCC_GPIOH_IS_CLK_DISABLED() ((RCC->AHBENR & (RCC_AHBENR_GPIOHEN)) == RESET)
2502#endif /* STM32F302xE || STM32F303xE || STM32F398xx */
2514#if defined(STM32F301x8) || defined(STM32F302x8) || defined(STM32F318xx)
2515#define __HAL_RCC_SPI2_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_SPI2EN)) != RESET)
2516#define __HAL_RCC_SPI3_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_SPI3EN)) != RESET)
2517#define __HAL_RCC_I2C2_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_I2C2EN)) != RESET)
2518#define __HAL_RCC_I2C3_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_I2C3EN)) != RESET)
2519
2520#define __HAL_RCC_SPI2_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_SPI2EN)) == RESET)
2521#define __HAL_RCC_SPI3_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_SPI3EN)) == RESET)
2522#define __HAL_RCC_I2C2_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_I2C2EN)) == RESET)
2523#define __HAL_RCC_I2C3_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_I2C3EN)) == RESET)
2524#endif /* STM32F301x8 || STM32F302x8 || STM32F318xx */
2525
2526#if defined(STM32F302xE) || defined(STM32F303xE) || defined(STM32F398xx)\
2527 || defined(STM32F302xC) || defined(STM32F303xC) || defined(STM32F358xx)
2528#define __HAL_RCC_TIM3_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM3EN)) != RESET)
2529#define __HAL_RCC_TIM4_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM4EN)) != RESET)
2530#define __HAL_RCC_SPI2_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_SPI2EN)) != RESET)
2531#define __HAL_RCC_SPI3_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_SPI3EN)) != RESET)
2532#define __HAL_RCC_UART4_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_UART4EN)) != RESET)
2533#define __HAL_RCC_UART5_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_UART5EN)) != RESET)
2534#define __HAL_RCC_I2C2_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_I2C2EN)) != RESET)
2535
2536#define __HAL_RCC_TIM3_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM3EN)) == RESET)
2537#define __HAL_RCC_TIM4_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM4EN)) == RESET)
2538#define __HAL_RCC_SPI2_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_SPI2EN)) == RESET)
2539#define __HAL_RCC_SPI3_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_SPI3EN)) == RESET)
2540#define __HAL_RCC_UART4_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_UART4EN)) == RESET)
2541#define __HAL_RCC_UART5_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_UART5EN)) == RESET)
2542#define __HAL_RCC_I2C2_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_I2C2EN)) == RESET)
2543#endif /* STM32F302xE || STM32F303xE || STM32F398xx || */
2544 /* STM32F302xC || STM32F303xC || STM32F358xx */
2545
2546#if defined(STM32F303x8) || defined(STM32F334x8) || defined(STM32F328xx)
2547#define __HAL_RCC_TIM3_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM3EN)) != RESET)
2548#define __HAL_RCC_DAC2_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_DAC2EN)) != RESET)
2549
2550#define __HAL_RCC_TIM3_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM3EN)) == RESET)
2551#define __HAL_RCC_DAC2_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_DAC2EN)) == RESET)
2552#endif /* STM32F303x8 || STM32F334x8 || STM32F328xx */
2553
2554#if defined(STM32F373xC) || defined(STM32F378xx)
2555#define __HAL_RCC_TIM3_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM3EN)) != RESET)
2556#define __HAL_RCC_TIM4_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM4EN)) != RESET)
2557#define __HAL_RCC_TIM5_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM5EN)) != RESET)
2558#define __HAL_RCC_TIM12_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM12EN)) != RESET)
2559#define __HAL_RCC_TIM13_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM13EN)) != RESET)
2560#define __HAL_RCC_TIM14_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM14EN)) != RESET)
2561#define __HAL_RCC_TIM18_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM18EN)) != RESET)
2562#define __HAL_RCC_SPI2_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_SPI2EN)) != RESET)
2563#define __HAL_RCC_SPI3_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_SPI3EN)) != RESET)
2564#define __HAL_RCC_I2C2_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_I2C2EN)) != RESET)
2565#define __HAL_RCC_DAC2_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_DAC2EN)) != RESET)
2566#define __HAL_RCC_CEC_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_CECEN)) != RESET)
2567
2568#define __HAL_RCC_TIM3_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM3EN)) == RESET)
2569#define __HAL_RCC_TIM4_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM4EN)) == RESET)
2570#define __HAL_RCC_TIM5_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM5EN)) == RESET)
2571#define __HAL_RCC_TIM12_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM12EN)) == RESET)
2572#define __HAL_RCC_TIM13_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM13EN)) == RESET)
2573#define __HAL_RCC_TIM14_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM14EN)) == RESET)
2574#define __HAL_RCC_TIM18_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM18EN)) == RESET)
2575#define __HAL_RCC_SPI2_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_SPI2EN)) == RESET)
2576#define __HAL_RCC_SPI3_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_SPI3EN)) == RESET)
2577#define __HAL_RCC_I2C2_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_I2C2EN)) == RESET)
2578#define __HAL_RCC_DAC2_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_DAC2EN)) == RESET)
2579#define __HAL_RCC_CEC_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_CECEN)) == RESET)
2580#endif /* STM32F373xC || STM32F378xx */
2581
2582#if defined(STM32F303xE) || defined(STM32F398xx) \
2583 || defined(STM32F303xC) || defined(STM32F358xx) \
2584 || defined(STM32F303x8) || defined(STM32F334x8) || defined(STM32F328xx)\
2585 || defined(STM32F373xC) || defined(STM32F378xx)
2586#define __HAL_RCC_TIM7_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM7EN)) != RESET)
2587
2588#define __HAL_RCC_TIM7_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM7EN)) == RESET)
2589#endif /* STM32F303xE || STM32F398xx || */
2590 /* STM32F303xC || STM32F358xx || */
2591 /* STM32F303x8 || STM32F334x8 || STM32F328xx || */
2592 /* STM32F373xC || STM32F378xx */
2593
2594#if defined(STM32F302xE) || defined(STM32F303xE)\
2595 || defined(STM32F302xC) || defined(STM32F303xC)\
2596 || defined(STM32F302x8) \
2597 || defined(STM32F373xC)
2598#define __HAL_RCC_USB_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_USBEN)) != RESET)
2599
2600#define __HAL_RCC_USB_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_USBEN)) == RESET)
2601#endif /* STM32F302xE || STM32F303xE || */
2602 /* STM32F302xC || STM32F303xC || */
2603 /* STM32F302x8 || */
2604 /* STM32F373xC */
2605
2606#if !defined(STM32F301x8)
2607#define __HAL_RCC_CAN1_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_CANEN)) != RESET)
2608
2609#define __HAL_RCC_CAN1_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_CANEN)) == RESET)
2610#endif /* STM32F301x8*/
2611
2612#if defined(STM32F302xE) || defined(STM32F303xE) || defined(STM32F398xx)
2613#define __HAL_RCC_I2C3_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_I2C3EN)) != RESET)
2614
2615#define __HAL_RCC_I2C3_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_I2C3EN)) == RESET)
2616#endif /* STM32F302xE || STM32F303xE || STM32F398xx */
2628#if defined(STM32F302xE) || defined(STM32F303xE) || defined(STM32F398xx)\
2629 || defined(STM32F302xC) || defined(STM32F303xC) || defined(STM32F358xx)
2630#define __HAL_RCC_SPI1_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_SPI1EN)) != RESET)
2631
2632#define __HAL_RCC_SPI1_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_SPI1EN)) == RESET)
2633#endif /* STM32F302xE || STM32F303xE || STM32F398xx || */
2634 /* STM32F302xC || STM32F303xC || STM32F358xx */
2635
2636#if defined(STM32F303xE) || defined(STM32F398xx)\
2637 || defined(STM32F303xC) || defined(STM32F358xx)
2638#define __HAL_RCC_TIM8_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_TIM8EN)) != RESET)
2639
2640#define __HAL_RCC_TIM8_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_TIM8EN)) == RESET)
2641#endif /* STM32F303xE || STM32F398xx || */
2642 /* STM32F303xC || STM32F358xx */
2643
2644#if defined(STM32F303x8) || defined(STM32F334x8) || defined(STM32F328xx)
2645#define __HAL_RCC_SPI1_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_SPI1EN)) != RESET)
2646
2647#define __HAL_RCC_SPI1_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_SPI1EN)) == RESET)
2648#endif /* STM32F303x8 || STM32F334x8 || STM32F328xx */
2649
2650#if defined(STM32F334x8)
2651#define __HAL_RCC_HRTIM1_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_HRTIM1EN)) != RESET)
2652
2653#define __HAL_RCC_HRTIM1_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_HRTIM1EN)) == RESET)
2654#endif /* STM32F334x8 */
2655
2656#if defined(STM32F373xC) || defined(STM32F378xx)
2657#define __HAL_RCC_ADC1_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_ADC1EN)) != RESET)
2658#define __HAL_RCC_SPI1_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_SPI1EN)) != RESET)
2659#define __HAL_RCC_TIM19_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_TIM19EN)) != RESET)
2660#define __HAL_RCC_SDADC1_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_SDADC1EN)) != RESET)
2661#define __HAL_RCC_SDADC2_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_SDADC2EN)) != RESET)
2662#define __HAL_RCC_SDADC3_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_SDADC3EN)) != RESET)
2663
2664#define __HAL_RCC_ADC1_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_ADC1EN)) == RESET)
2665#define __HAL_RCC_SPI1_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_SPI1EN)) == RESET)
2666#define __HAL_RCC_TIM19_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_TIM19EN)) == RESET)
2667#define __HAL_RCC_SDADC1_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_SDADC1EN)) == RESET)
2668#define __HAL_RCC_SDADC2_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_SDADC2EN)) == RESET)
2669#define __HAL_RCC_SDADC3_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_SDADC3EN)) == RESET)
2670#endif /* STM32F373xC || STM32F378xx */
2671
2672#if defined(STM32F302xE) || defined(STM32F303xE) || defined(STM32F398xx)\
2673 || defined(STM32F302xC) || defined(STM32F303xC) || defined(STM32F358xx)\
2674 || defined(STM32F303x8) || defined(STM32F334x8) || defined(STM32F328xx)\
2675 || defined(STM32F301x8) || defined(STM32F302x8) || defined(STM32F318xx)
2676#define __HAL_RCC_TIM1_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_TIM1EN)) != RESET)
2677
2678#define __HAL_RCC_TIM1_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_TIM1EN)) == RESET)
2679#endif /* STM32F302xE || STM32F303xE || STM32F398xx || */
2680 /* STM32F302xC || STM32F303xC || STM32F358xx || */
2681 /* STM32F303x8 || STM32F334x8 || STM32F328xx || */
2682 /* STM32F301x8 || STM32F302x8 || STM32F318xx */
2683
2684#if defined(STM32F302xE) || defined(STM32F303xE) || defined(STM32F398xx)
2685#define __HAL_RCC_SPI4_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_SPI4EN)) != RESET)
2686
2687#define __HAL_RCC_SPI4_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_SPI4EN)) == RESET)
2688#endif /* STM32F302xE || STM32F303xE || STM32F398xx */
2689
2690#if defined(STM32F303xE) || defined(STM32F398xx)
2691#define __HAL_RCC_TIM20_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_TIM20EN)) != RESET)
2692
2693#define __HAL_RCC_TIM20_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_TIM20EN)) == RESET)
2694#endif /* STM32F303xE || STM32F398xx */
2703#if defined(STM32F301x8) || defined(STM32F302x8) || defined(STM32F318xx)
2704#define __HAL_RCC_ADC1_FORCE_RESET() (RCC->AHBRSTR |= (RCC_AHBRSTR_ADC1RST))
2705
2706#define __HAL_RCC_ADC1_RELEASE_RESET() (RCC->AHBRSTR &= ~(RCC_AHBRSTR_ADC1RST))
2707#endif /* STM32F301x8 || STM32F302x8 || STM32F318xx */
2708
2709#if defined(STM32F302xE) || defined(STM32F303xE) || defined(STM32F398xx)\
2710 || defined(STM32F302xC) || defined(STM32F303xC) || defined(STM32F358xx)
2711#define __HAL_RCC_GPIOE_FORCE_RESET() (RCC->AHBRSTR |= (RCC_AHBRSTR_GPIOERST))
2712#define __HAL_RCC_ADC12_FORCE_RESET() (RCC->AHBRSTR |= (RCC_AHBRSTR_ADC12RST))
2713/* Aliases for STM32 F3 compatibility */
2714#define __HAL_RCC_ADC1_FORCE_RESET() __HAL_RCC_ADC12_FORCE_RESET()
2715#define __HAL_RCC_ADC2_FORCE_RESET() __HAL_RCC_ADC12_FORCE_RESET()
2716
2717#define __HAL_RCC_GPIOE_RELEASE_RESET() (RCC->AHBRSTR &= ~(RCC_AHBRSTR_GPIOERST))
2718#define __HAL_RCC_ADC12_RELEASE_RESET() (RCC->AHBRSTR &= ~(RCC_AHBRSTR_ADC12RST))
2719/* Aliases for STM32 F3 compatibility */
2720#define __HAL_RCC_ADC1_RELEASE_RESET() __HAL_RCC_ADC12_RELEASE_RESET()
2721#define __HAL_RCC_ADC2_RELEASE_RESET() __HAL_RCC_ADC12_RELEASE_RESET()
2722#endif /* STM32F302xE || STM32F303xE || STM32F398xx || */
2723 /* STM32F302xC || STM32F303xC || STM32F358xx */
2724
2725#if defined(STM32F303xE) || defined(STM32F398xx)\
2726 || defined(STM32F303xC) || defined(STM32F358xx)
2727#define __HAL_RCC_ADC34_FORCE_RESET() (RCC->AHBRSTR |= (RCC_AHBRSTR_ADC34RST))
2728
2729#define __HAL_RCC_ADC34_RELEASE_RESET() (RCC->AHBRSTR &= ~(RCC_AHBRSTR_ADC34RST))
2730#endif /* STM32F303xE || STM32F398xx || */
2731 /* STM32F303xC || STM32F358xx */
2732
2733#if defined(STM32F303x8) || defined(STM32F334x8) || defined(STM32F328xx)
2734#define __HAL_RCC_ADC12_FORCE_RESET() (RCC->AHBRSTR |= (RCC_AHBRSTR_ADC12RST))
2735/* Aliases for STM32 F3 compatibility */
2736#define __HAL_RCC_ADC1_FORCE_RESET() __HAL_RCC_ADC12_FORCE_RESET()
2737#define __HAL_RCC_ADC2_FORCE_RESET() __HAL_RCC_ADC12_FORCE_RESET()
2738
2739#define __HAL_RCC_ADC12_RELEASE_RESET() (RCC->AHBRSTR &= ~(RCC_AHBRSTR_ADC12RST))
2740/* Aliases for STM32 F3 compatibility */
2741#define __HAL_RCC_ADC1_RELEASE_RESET() __HAL_RCC_ADC12_RELEASE_RESET()
2742#define __HAL_RCC_ADC2_RELEASE_RESET() __HAL_RCC_ADC12_RELEASE_RESET()
2743#endif /* STM32F303x8 || STM32F334x8 || STM32F328xx */
2744
2745#if defined(STM32F373xC) || defined(STM32F378xx)
2746#define __HAL_RCC_GPIOE_FORCE_RESET() (RCC->AHBRSTR |= (RCC_AHBRSTR_GPIOERST))
2747
2748#define __HAL_RCC_GPIOE_RELEASE_RESET() (RCC->AHBRSTR &= ~(RCC_AHBRSTR_GPIOERST))
2749#endif /* STM32F373xC || STM32F378xx */
2750
2751#if defined(STM32F302xE) || defined(STM32F303xE) || defined(STM32F398xx)
2752#define __HAL_RCC_FMC_FORCE_RESET() (RCC->AHBRSTR |= (RCC_AHBRSTR_FMCRST))
2753#define __HAL_RCC_GPIOG_FORCE_RESET() (RCC->AHBRSTR |= (RCC_AHBRSTR_GPIOGRST))
2754#define __HAL_RCC_GPIOH_FORCE_RESET() (RCC->AHBRSTR |= (RCC_AHBRSTR_GPIOHRST))
2755
2756#define __HAL_RCC_FMC_RELEASE_RESET() (RCC->AHBRSTR &= ~(RCC_AHBRSTR_FMCRST))
2757#define __HAL_RCC_GPIOG_RELEASE_RESET() (RCC->AHBRSTR &= ~(RCC_AHBRSTR_GPIOGRST))
2758#define __HAL_RCC_GPIOH_RELEASE_RESET() (RCC->AHBRSTR &= ~(RCC_AHBRSTR_GPIOHRST))
2759#endif /* STM32F302xE || STM32F303xE || STM32F398xx */
2768#if defined(STM32F301x8) || defined(STM32F302x8) || defined(STM32F318xx)
2769#define __HAL_RCC_SPI2_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_SPI2RST))
2770#define __HAL_RCC_SPI3_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_SPI3RST))
2771#define __HAL_RCC_I2C2_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_I2C2RST))
2772#define __HAL_RCC_I2C3_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_I2C3RST))
2773
2774#define __HAL_RCC_SPI2_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_SPI2RST))
2775#define __HAL_RCC_SPI3_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_SPI3RST))
2776#define __HAL_RCC_I2C2_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_I2C2RST))
2777#define __HAL_RCC_I2C3_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_I2C3RST))
2778#endif /* STM32F301x8 || STM32F302x8 || STM32F318xx */
2779
2780#if defined(STM32F302xE) || defined(STM32F303xE) || defined(STM32F398xx)\
2781 || defined(STM32F302xC) || defined(STM32F303xC) || defined(STM32F358xx)
2782#define __HAL_RCC_TIM3_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_TIM3RST))
2783#define __HAL_RCC_TIM4_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_TIM4RST))
2784#define __HAL_RCC_SPI2_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_SPI2RST))
2785#define __HAL_RCC_SPI3_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_SPI3RST))
2786#define __HAL_RCC_UART4_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_UART4RST))
2787#define __HAL_RCC_UART5_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_UART5RST))
2788#define __HAL_RCC_I2C2_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_I2C2RST))
2789
2790#define __HAL_RCC_TIM3_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM3RST))
2791#define __HAL_RCC_TIM4_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM4RST))
2792#define __HAL_RCC_SPI2_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_SPI2RST))
2793#define __HAL_RCC_SPI3_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_SPI3RST))
2794#define __HAL_RCC_UART4_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_UART4RST))
2795#define __HAL_RCC_UART5_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_UART5RST))
2796#define __HAL_RCC_I2C2_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_I2C2RST))
2797#endif /* STM32F302xE || STM32F303xE || STM32F398xx || */
2798 /* STM32F302xC || STM32F303xC || STM32F358xx */
2799
2800#if defined(STM32F303x8) || defined(STM32F334x8) || defined(STM32F328xx)
2801#define __HAL_RCC_TIM3_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_TIM3RST))
2802#define __HAL_RCC_DAC2_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_DAC2RST))
2803
2804#define __HAL_RCC_TIM3_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM3RST))
2805#define __HAL_RCC_DAC2_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_DAC2RST))
2806#endif /* STM32F303x8 || STM32F334x8 || STM32F328xx */
2807
2808#if defined(STM32F373xC) || defined(STM32F378xx)
2809#define __HAL_RCC_TIM3_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_TIM3RST))
2810#define __HAL_RCC_TIM4_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_TIM4RST))
2811#define __HAL_RCC_TIM5_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_TIM5RST))
2812#define __HAL_RCC_TIM12_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_TIM12RST))
2813#define __HAL_RCC_TIM13_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_TIM13RST))
2814#define __HAL_RCC_TIM14_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_TIM14RST))
2815#define __HAL_RCC_TIM18_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_TIM18RST))
2816#define __HAL_RCC_SPI2_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_SPI2RST))
2817#define __HAL_RCC_SPI3_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_SPI3RST))
2818#define __HAL_RCC_I2C2_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_I2C2RST))
2819#define __HAL_RCC_DAC2_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_DAC2RST))
2820#define __HAL_RCC_CEC_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_CECRST))
2821
2822#define __HAL_RCC_TIM3_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM3RST))
2823#define __HAL_RCC_TIM4_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM4RST))
2824#define __HAL_RCC_TIM5_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM5RST))
2825#define __HAL_RCC_TIM12_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM12RST))
2826#define __HAL_RCC_TIM13_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM13RST))
2827#define __HAL_RCC_TIM14_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM14RST))
2828#define __HAL_RCC_TIM18_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM18RST))
2829#define __HAL_RCC_SPI2_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_SPI2RST))
2830#define __HAL_RCC_SPI3_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_SPI3RST))
2831#define __HAL_RCC_I2C2_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_I2C2RST))
2832#define __HAL_RCC_DAC2_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_DAC2RST))
2833#define __HAL_RCC_CEC_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_CECRST))
2834#endif /* STM32F373xC || STM32F378xx */
2835
2836#if defined(STM32F303xE) || defined(STM32F398xx)\
2837 || defined(STM32F303xC) || defined(STM32F358xx)\
2838 || defined(STM32F303x8) || defined(STM32F334x8) || defined(STM32F328xx)\
2839 || defined(STM32F373xC) || defined(STM32F378xx)
2840#define __HAL_RCC_TIM7_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_TIM7RST))
2841
2842#define __HAL_RCC_TIM7_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM7RST))
2843#endif /* STM32F303xE || STM32F398xx || */
2844 /* STM32F303xC || STM32F358xx || */
2845 /* STM32F303x8 || STM32F334x8 || STM32F328xx || */
2846 /* STM32F373xC || STM32F378xx */
2847
2848#if defined(STM32F302xE) || defined(STM32F303xE)\
2849 || defined(STM32F302xC) || defined(STM32F303xC)\
2850 || defined(STM32F302x8) \
2851 || defined(STM32F373xC)
2852#define __HAL_RCC_USB_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_USBRST))
2853
2854#define __HAL_RCC_USB_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_USBRST))
2855#endif /* STM32F302xE || STM32F303xE || */
2856 /* STM32F302xC || STM32F303xC || */
2857 /* STM32F302x8 || */
2858 /* STM32F373xC */
2859
2860#if !defined(STM32F301x8)
2861#define __HAL_RCC_CAN1_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_CANRST))
2862
2863#define __HAL_RCC_CAN1_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_CANRST))
2864#endif /* STM32F301x8*/
2865
2866#if defined(STM32F302xE) || defined(STM32F303xE) || defined(STM32F398xx)
2867#define __HAL_RCC_I2C3_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_I2C3RST))
2868
2869#define __HAL_RCC_I2C3_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_I2C3RST))
2870#endif /* STM32F302xE || STM32F303xE || STM32F398xx */
2879#if defined(STM32F302xE) || defined(STM32F303xE) || defined(STM32F398xx)\
2880 || defined(STM32F302xC) || defined(STM32F303xC) || defined(STM32F358xx)
2881#define __HAL_RCC_SPI1_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_SPI1RST))
2882
2883#define __HAL_RCC_SPI1_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_SPI1RST))
2884#endif /* STM32F302xE || STM32F303xE || STM32F398xx || */
2885 /* STM32F302xC || STM32F303xC || STM32F358xx */
2886
2887#if defined(STM32F303xE) || defined(STM32F398xx)\
2888 || defined(STM32F303xC) || defined(STM32F358xx)
2889#define __HAL_RCC_TIM8_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_TIM8RST))
2890
2891#define __HAL_RCC_TIM8_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_TIM8RST))
2892#endif /* STM32F303xE || STM32F398xx || */
2893 /* STM32F303xC || STM32F358xx */
2894
2895#if defined(STM32F303x8) || defined(STM32F334x8) || defined(STM32F328xx)
2896#define __HAL_RCC_SPI1_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_SPI1RST))
2897
2898#define __HAL_RCC_SPI1_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_SPI1RST))
2899#endif /* STM32F303x8 || STM32F334x8 || STM32F328xx */
2900
2901#if defined(STM32F334x8)
2902#define __HAL_RCC_HRTIM1_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_HRTIM1RST))
2903
2904#define __HAL_RCC_HRTIM1_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_HRTIM1RST))
2905#endif /* STM32F334x8 */
2906
2907#if defined(STM32F373xC) || defined(STM32F378xx)
2908#define __HAL_RCC_ADC1_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_ADC1RST))
2909#define __HAL_RCC_SPI1_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_SPI1RST))
2910#define __HAL_RCC_TIM19_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_TIM19RST))
2911#define __HAL_RCC_SDADC1_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_SDADC1RST))
2912#define __HAL_RCC_SDADC2_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_SDADC2RST))
2913#define __HAL_RCC_SDADC3_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_SDADC3RST))
2914
2915#define __HAL_RCC_ADC1_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_ADC1RST))
2916#define __HAL_RCC_SPI1_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_SPI1RST))
2917#define __HAL_RCC_TIM19_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_TIM19RST))
2918#define __HAL_RCC_SDADC1_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_SDADC1RST))
2919#define __HAL_RCC_SDADC2_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_SDADC2RST))
2920#define __HAL_RCC_SDADC3_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_SDADC3RST))
2921#endif /* STM32F373xC || STM32F378xx */
2922
2923#if defined(STM32F302xE) || defined(STM32F303xE) || defined(STM32F398xx)\
2924 || defined(STM32F302xC) || defined(STM32F303xC) || defined(STM32F358xx)\
2925 || defined(STM32F303x8) || defined(STM32F334x8) || defined(STM32F328xx)\
2926 || defined(STM32F301x8) || defined(STM32F302x8) || defined(STM32F318xx)
2927#define __HAL_RCC_TIM1_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_TIM1RST))
2928
2929#define __HAL_RCC_TIM1_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_TIM1RST))
2930#endif /* STM32F302xE || STM32F303xE || STM32F398xx || */
2931 /* STM32F302xC || STM32F303xC || STM32F358xx || */
2932 /* STM32F303x8 || STM32F334x8 || STM32F328xx || */
2933 /* STM32F301x8 || STM32F302x8 || STM32F318xx */
2934
2935#if defined(STM32F302xE) || defined(STM32F303xE) || defined(STM32F398xx)
2936#define __HAL_RCC_SPI4_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_SPI4RST))
2937
2938#define __HAL_RCC_SPI4_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_SPI4RST))
2939#endif /* STM32F302xE || STM32F303xE || STM32F398xx */
2940
2941#if defined(STM32F303xE) || defined(STM32F398xx)
2942#define __HAL_RCC_TIM20_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_TIM20RST))
2943
2944#define __HAL_RCC_TIM20_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_TIM20RST))
2945#endif /* STM32F303xE || STM32F398xx */
2946
2951#if defined(STM32F301x8) || defined(STM32F302x8) || defined(STM32F318xx)
2962#define __HAL_RCC_I2C2_CONFIG(__I2C2CLKSource__) \
2963 MODIFY_REG(RCC->CFGR3, RCC_CFGR3_I2C2SW, (uint32_t)(__I2C2CLKSource__))
2964
2970#define __HAL_RCC_GET_I2C2_SOURCE() ((uint32_t)(READ_BIT(RCC->CFGR3, RCC_CFGR3_I2C2SW)))
2971
2978#define __HAL_RCC_I2C3_CONFIG(__I2C3CLKSource__) \
2979 MODIFY_REG(RCC->CFGR3, RCC_CFGR3_I2C3SW, (uint32_t)(__I2C3CLKSource__))
2980
2986#define __HAL_RCC_GET_I2C3_SOURCE() ((uint32_t)(READ_BIT(RCC->CFGR3, RCC_CFGR3_I2C3SW)))
2987
3001#define __HAL_RCC_TIM1_CONFIG(__TIM1CLKSource__) \
3002 MODIFY_REG(RCC->CFGR3, RCC_CFGR3_TIM1SW, (uint32_t)(__TIM1CLKSource__))
3003
3009#define __HAL_RCC_GET_TIM1_SOURCE() ((uint32_t)(READ_BIT(RCC->CFGR3, RCC_CFGR3_TIM1SW)))
3010
3017#define __HAL_RCC_TIM15_CONFIG(__TIM15CLKSource__) \
3018 MODIFY_REG(RCC->CFGR3, RCC_CFGR3_TIM15SW, (uint32_t)(__TIM15CLKSource__))
3019
3025#define __HAL_RCC_GET_TIM15_SOURCE() ((uint32_t)(READ_BIT(RCC->CFGR3, RCC_CFGR3_TIM15SW)))
3026
3033#define __HAL_RCC_TIM16_CONFIG(__TIM16CLKSource__) \
3034 MODIFY_REG(RCC->CFGR3, RCC_CFGR3_TIM16SW, (uint32_t)(__TIM16CLKSource__))
3035
3041#define __HAL_RCC_GET_TIM16_SOURCE() ((uint32_t)(READ_BIT(RCC->CFGR3, RCC_CFGR3_TIM16SW)))
3042
3049#define __HAL_RCC_TIM17_CONFIG(__TIM17CLKSource__) \
3050 MODIFY_REG(RCC->CFGR3, RCC_CFGR3_TIM17SW, (uint32_t)(__TIM17CLKSource__))
3051
3057#define __HAL_RCC_GET_TIM17_SOURCE() ((uint32_t)(READ_BIT(RCC->CFGR3, RCC_CFGR3_TIM17SW)))
3058
3074#define __HAL_RCC_I2S_CONFIG(__I2SCLKSource__) \
3075 MODIFY_REG(RCC->CFGR, RCC_CFGR_I2SSRC, (uint32_t)(__I2SCLKSource__))
3076
3083#define __HAL_RCC_GET_I2S_SOURCE() ((uint32_t)(READ_BIT(RCC->CFGR, RCC_CFGR_I2SSRC)))
3109#define __HAL_RCC_ADC1_CONFIG(__ADC1CLKSource__) \
3110 MODIFY_REG(RCC->CFGR2, RCC_CFGR2_ADC1PRES, (uint32_t)(__ADC1CLKSource__))
3111
3128#define __HAL_RCC_GET_ADC1_SOURCE() ((uint32_t)(READ_BIT(RCC->CFGR2, RCC_CFGR2_ADC1PRES)))
3133#endif /* STM32F301x8 || STM32F302x8 || STM32F318xx */
3134
3135#if defined(STM32F302xE) || defined(STM32F303xE) || defined(STM32F398xx)\
3136 || defined(STM32F302xC) || defined(STM32F303xC) || defined(STM32F358xx)
3147#define __HAL_RCC_I2C2_CONFIG(__I2C2CLKSource__) \
3148 MODIFY_REG(RCC->CFGR3, RCC_CFGR3_I2C2SW, (uint32_t)(__I2C2CLKSource__))
3149
3155#define __HAL_RCC_GET_I2C2_SOURCE() ((uint32_t)(READ_BIT(RCC->CFGR3, RCC_CFGR3_I2C2SW)))
3181#define __HAL_RCC_ADC12_CONFIG(__ADC12CLKSource__) \
3182 MODIFY_REG(RCC->CFGR2, RCC_CFGR2_ADCPRE12, (uint32_t)(__ADC12CLKSource__))
3183
3200#define __HAL_RCC_GET_ADC12_SOURCE() ((uint32_t)(READ_BIT(RCC->CFGR2, RCC_CFGR2_ADCPRE12)))
3215#define __HAL_RCC_TIM1_CONFIG(__TIM1CLKSource__) \
3216 MODIFY_REG(RCC->CFGR3, RCC_CFGR3_TIM1SW, (uint32_t)(__TIM1CLKSource__))
3217
3223#define __HAL_RCC_GET_TIM1_SOURCE() ((uint32_t)(READ_BIT(RCC->CFGR3, RCC_CFGR3_TIM1SW)))
3240#define __HAL_RCC_I2S_CONFIG(__I2SCLKSource__) \
3241 MODIFY_REG(RCC->CFGR, RCC_CFGR_I2SSRC, (uint32_t)(__I2SCLKSource__))
3242
3249#define __HAL_RCC_GET_I2S_SOURCE() ((uint32_t)(READ_BIT(RCC->CFGR, RCC_CFGR_I2SSRC)))
3266#define __HAL_RCC_UART4_CONFIG(__UART4CLKSource__) \
3267 MODIFY_REG(RCC->CFGR3, RCC_CFGR3_UART4SW, (uint32_t)(__UART4CLKSource__))
3268
3276#define __HAL_RCC_GET_UART4_SOURCE() ((uint32_t)(READ_BIT(RCC->CFGR3, RCC_CFGR3_UART4SW)))
3277
3286#define __HAL_RCC_UART5_CONFIG(__UART5CLKSource__) \
3287 MODIFY_REG(RCC->CFGR3, RCC_CFGR3_UART5SW, (uint32_t)(__UART5CLKSource__))
3288
3296#define __HAL_RCC_GET_UART5_SOURCE() ((uint32_t)(READ_BIT(RCC->CFGR3, RCC_CFGR3_UART5SW)))
3300#endif /* STM32F302xE || STM32F303xE || STM32F398xx || */
3301 /* STM32F302xC || STM32F303xC || STM32F358xx */
3302
3303#if defined(STM32F303xE) || defined(STM32F398xx)\
3304 || defined(STM32F303xC) || defined(STM32F358xx)
3326#define __HAL_RCC_ADC34_CONFIG(__ADC34CLKSource__) \
3327 MODIFY_REG(RCC->CFGR2, RCC_CFGR2_ADCPRE34, (uint32_t)(__ADC34CLKSource__))
3328
3345#define __HAL_RCC_GET_ADC34_SOURCE() ((uint32_t)(READ_BIT(RCC->CFGR2, RCC_CFGR2_ADCPRE34)))
3360#define __HAL_RCC_TIM8_CONFIG(__TIM8CLKSource__) \
3361 MODIFY_REG(RCC->CFGR3, RCC_CFGR3_TIM8SW, (uint32_t)(__TIM8CLKSource__))
3362
3368#define __HAL_RCC_GET_TIM8_SOURCE() ((uint32_t)(READ_BIT(RCC->CFGR3, RCC_CFGR3_TIM8SW)))
3369
3373#endif /* STM32F303xE || STM32F398xx || */
3374 /* STM32F303xC || STM32F358xx */
3375
3376#if defined(STM32F303x8) || defined(STM32F334x8) || defined(STM32F328xx)
3398#define __HAL_RCC_ADC12_CONFIG(__ADC12CLKSource__) \
3399 MODIFY_REG(RCC->CFGR2, RCC_CFGR2_ADCPRE12, (uint32_t)(__ADC12CLKSource__))
3400
3417#define __HAL_RCC_GET_ADC12_SOURCE() ((uint32_t)(READ_BIT(RCC->CFGR2, RCC_CFGR2_ADCPRE12)))
3431#define __HAL_RCC_TIM1_CONFIG(__TIM1CLKSource__) \
3432 MODIFY_REG(RCC->CFGR3, RCC_CFGR3_TIM1SW, (uint32_t)(__TIM1CLKSource__))
3433
3439#define __HAL_RCC_GET_TIM1_SOURCE() ((uint32_t)(READ_BIT(RCC->CFGR3, RCC_CFGR3_TIM1SW)))
3443#endif /* STM32F303x8 || STM32F334x8 || STM32F328xx */
3444
3445#if defined(STM32F334x8)
3455#define __HAL_RCC_HRTIM1_CONFIG(__HRTIM1CLKSource__) \
3456 MODIFY_REG(RCC->CFGR3, RCC_CFGR3_HRTIM1SW, (uint32_t)(__HRTIM1CLKSource__))
3457
3463#define __HAL_RCC_GET_HRTIM1_SOURCE() ((uint32_t)(READ_BIT(RCC->CFGR3, RCC_CFGR3_HRTIM1SW)))
3467#endif /* STM32F334x8 */
3468
3469#if defined(STM32F373xC) || defined(STM32F378xx)
3479#define __HAL_RCC_I2C2_CONFIG(__I2C2CLKSource__) \
3480 MODIFY_REG(RCC->CFGR3, RCC_CFGR3_I2C2SW, (uint32_t)(__I2C2CLKSource__))
3481
3487#define __HAL_RCC_GET_I2C2_SOURCE() ((uint32_t)(READ_BIT(RCC->CFGR3, RCC_CFGR3_I2C2SW)))
3503#define __HAL_RCC_ADC1_CONFIG(__ADC1CLKSource__) \
3504 MODIFY_REG(RCC->CFGR, RCC_CFGR_ADCPRE, (uint32_t)(__ADC1CLKSource__))
3505
3513#define __HAL_RCC_GET_ADC1_SOURCE() ((uint32_t)(READ_BIT(RCC->CFGR, RCC_CFGR_ADCPRE)))
3542#define __HAL_RCC_SDADC_CONFIG(__SDADCPrescaler__) \
3543 MODIFY_REG(RCC->CFGR, RCC_CFGR_SDPRE, (uint32_t)(__SDADCPrescaler__))
3544
3565#define __HAL_RCC_GET_SDADC_SOURCE() ((uint32_t)(READ_BIT(RCC->CFGR, RCC_CFGR_SDPRE)))
3579#define __HAL_RCC_CEC_CONFIG(__CECCLKSource__) \
3580 MODIFY_REG(RCC->CFGR3, RCC_CFGR3_CECSW, (uint32_t)(__CECCLKSource__))
3581
3587#define __HAL_RCC_GET_CEC_SOURCE() ((uint32_t)(READ_BIT(RCC->CFGR3, RCC_CFGR3_CECSW)))
3592#endif /* STM32F373xC || STM32F378xx */
3593
3594#if defined(STM32F302xE) || defined(STM32F303xE)\
3595 || defined(STM32F302xC) || defined(STM32F303xC)\
3596 || defined(STM32F302x8) \
3597 || defined(STM32F373xC)
3598
3608#define __HAL_RCC_USB_CONFIG(__USBCLKSource__) \
3609 MODIFY_REG(RCC->CFGR, RCC_CFGR_USBPRE, (uint32_t)(__USBCLKSource__))
3610
3616#define __HAL_RCC_GET_USB_SOURCE() ((uint32_t)(READ_BIT(RCC->CFGR, RCC_CFGR_USBPRE)))
3621#endif /* STM32F302xE || STM32F303xE || */
3622 /* STM32F302xC || STM32F303xC || */
3623 /* STM32F302x8 || */
3624 /* STM32F373xC */
3625
3626#if defined(STM32F302xE) || defined(STM32F303xE) || defined(STM32F398xx)
3627
3637#define __HAL_RCC_I2C3_CONFIG(__I2C3CLKSource__) \
3638 MODIFY_REG(RCC->CFGR3, RCC_CFGR3_I2C3SW, (uint32_t)(__I2C3CLKSource__))
3639
3645#define __HAL_RCC_GET_I2C3_SOURCE() ((uint32_t)(READ_BIT(RCC->CFGR3, RCC_CFGR3_I2C3SW)))
3659#define __HAL_RCC_TIM2_CONFIG(__TIM2CLKSource__) \
3660 MODIFY_REG(RCC->CFGR3, RCC_CFGR3_TIM2SW, (uint32_t)(__TIM2CLKSource__))
3661
3667#define __HAL_RCC_GET_TIM2_SOURCE() ((uint32_t)(READ_BIT(RCC->CFGR3, RCC_CFGR3_TIM2SW)))
3668
3675#define __HAL_RCC_TIM34_CONFIG(__TIM34CLKSource__) \
3676 MODIFY_REG(RCC->CFGR3, RCC_CFGR3_TIM34SW, (uint32_t)(__TIM34CLKSource__))
3677
3683#define __HAL_RCC_GET_TIM34_SOURCE() ((uint32_t)(READ_BIT(RCC->CFGR3, RCC_CFGR3_TIM34SW)))
3684
3691#define __HAL_RCC_TIM15_CONFIG(__TIM15CLKSource__) \
3692 MODIFY_REG(RCC->CFGR3, RCC_CFGR3_TIM15SW, (uint32_t)(__TIM15CLKSource__))
3693
3699#define __HAL_RCC_GET_TIM15_SOURCE() ((uint32_t)(READ_BIT(RCC->CFGR3, RCC_CFGR3_TIM15SW)))
3700
3707#define __HAL_RCC_TIM16_CONFIG(__TIM16CLKSource__) \
3708 MODIFY_REG(RCC->CFGR3, RCC_CFGR3_TIM16SW, (uint32_t)(__TIM16CLKSource__))
3709
3715#define __HAL_RCC_GET_TIM16_SOURCE() ((uint32_t)(READ_BIT(RCC->CFGR3, RCC_CFGR3_TIM16SW)))
3716
3723#define __HAL_RCC_TIM17_CONFIG(__TIM17CLKSource__) \
3724 MODIFY_REG(RCC->CFGR3, RCC_CFGR3_TIM17SW, (uint32_t)(__TIM17CLKSource__))
3725
3731#define __HAL_RCC_GET_TIM17_SOURCE() ((uint32_t)(READ_BIT(RCC->CFGR3, RCC_CFGR3_TIM17SW)))
3732
3737#endif /* STM32f302xE || STM32f303xE || STM32F398xx */
3738
3739#if defined(STM32F303xE) || defined(STM32F398xx)
3749#define __HAL_RCC_TIM20_CONFIG(__TIM20CLKSource__) \
3750 MODIFY_REG(RCC->CFGR3, RCC_CFGR3_TIM20SW, (uint32_t)(__TIM20CLKSource__))
3751
3757#define __HAL_RCC_GET_TIM20_SOURCE() ((uint32_t)(READ_BIT(RCC->CFGR3, RCC_CFGR3_TIM20SW)))
3758
3762#endif /* STM32f303xE || STM32F398xx */
3763
3778#define __HAL_RCC_LSEDRIVE_CONFIG(__RCC_LSEDRIVE__) (MODIFY_REG(RCC->BDCR,\
3779 RCC_BDCR_LSEDRV, (uint32_t)(__RCC_LSEDRIVE__) ))
3780
3789/* Exported functions --------------------------------------------------------*/
3798HAL_StatusTypeDef HAL_RCCEx_PeriphCLKConfig(RCC_PeriphCLKInitTypeDef *PeriphClkInit);
3799void HAL_RCCEx_GetPeriphCLKConfig(RCC_PeriphCLKInitTypeDef *PeriphClkInit);
3800uint32_t HAL_RCCEx_GetPeriphCLKFreq(uint32_t PeriphClk);
3801
3818#ifdef __cplusplus
3819}
3820#endif
3821
3822#endif /* __STM32F3xx_HAL_RCC_EX_H */
3823
3824
HAL_RCCEx_PeriphCLKConfig
HAL_StatusTypeDef HAL_RCCEx_PeriphCLKConfig(RCC_PeriphCLKInitTypeDef *PeriphClkInit)
HAL_RCCEx_GetPeriphCLKFreq
uint32_t HAL_RCCEx_GetPeriphCLKFreq(uint32_t PeriphClk)
HAL_RCCEx_GetPeriphCLKConfig
void HAL_RCCEx_GetPeriphCLKConfig(RCC_PeriphCLKInitTypeDef *PeriphClkInit)
stm32f3xx_hal_def.h
This file contains HAL common defines, enumeration, macros and structures definitions.
HAL_StatusTypeDef
HAL_StatusTypeDef
HAL Status structures definition
Definition: stm32f3xx_hal_def.h:39