Enable or disable the Low Speed APB (APB1) peripheral clock.
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Enable or disable the Low Speed APB (APB1) peripheral clock.
- Note
- After reset, the peripheral clock (used for registers read/write access) is disabled and the application software has to enable this clock before using it.
◆ __HAL_RCC_CAN1_CLK_DISABLE
◆ __HAL_RCC_CAN1_CLK_ENABLE
#define __HAL_RCC_CAN1_CLK_ENABLE |
( |
| ) |
|
Value: do { \
\
UNUSED(tmpreg); \
} while(0U)
#define __IO
Definition: core_armv8mbl.h:196
#define READ_BIT(REG, BIT)
Definition: stm32f3xx.h:194
#define RCC_APB1ENR_CANEN
Definition: stm32f303xe.h:11203
#define RCC
Definition: stm32f303xe.h:977