My Project
Loading...
Searching...
No Matches
stm32f3xx_hal_tsc.h
Go to the documentation of this file.
1
19/* Define to prevent recursive inclusion -------------------------------------*/
20#ifndef STM32F3xx_HAL_TSC_H
21#define STM32F3xx_HAL_TSC_H
22
23#ifdef __cplusplus
24extern "C" {
25#endif
26
27/* Includes ------------------------------------------------------------------*/
28#include "stm32f3xx_hal_def.h"
29
30
39/* Exported types ------------------------------------------------------------*/
47typedef enum
48{
49 HAL_TSC_STATE_RESET = 0x00UL,
50 HAL_TSC_STATE_READY = 0x01UL,
51 HAL_TSC_STATE_BUSY = 0x02UL,
52 HAL_TSC_STATE_ERROR = 0x03UL
53} HAL_TSC_StateTypeDef;
54
58typedef enum
59{
60 TSC_GROUP_ONGOING = 0x00UL,
61 TSC_GROUP_COMPLETED = 0x01UL
62} TSC_GroupStatusTypeDef;
63
67typedef struct
68{
69 uint32_t CTPulseHighLength;
71 uint32_t CTPulseLowLength;
73 FunctionalState SpreadSpectrum;
75 uint32_t SpreadSpectrumDeviation;
77 uint32_t SpreadSpectrumPrescaler;
79 uint32_t PulseGeneratorPrescaler;
81 uint32_t MaxCountValue;
83 uint32_t IODefaultMode;
85 uint32_t SynchroPinPolarity;
87 uint32_t AcquisitionMode;
89 FunctionalState MaxCountInterrupt;
91 uint32_t ChannelIOs;
92 uint32_t ShieldIOs;
93 uint32_t SamplingIOs;
94} TSC_InitTypeDef;
95
99typedef struct
100{
101 uint32_t ChannelIOs;
102 uint32_t ShieldIOs;
103 uint32_t SamplingIOs;
104} TSC_IOConfigTypeDef;
105
109#if (USE_HAL_TSC_REGISTER_CALLBACKS == 1)
110typedef struct __TSC_HandleTypeDef
111#else
112typedef struct
113#endif /* USE_HAL_TSC_REGISTER_CALLBACKS */
114{
115 TSC_TypeDef *Instance;
116 TSC_InitTypeDef Init;
117 __IO HAL_TSC_StateTypeDef State;
118 HAL_LockTypeDef Lock;
119 __IO uint32_t ErrorCode;
121#if (USE_HAL_TSC_REGISTER_CALLBACKS == 1)
122 void (* ConvCpltCallback)(struct __TSC_HandleTypeDef *htsc);
123 void (* ErrorCallback)(struct __TSC_HandleTypeDef *htsc);
125 void (* MspInitCallback)(struct __TSC_HandleTypeDef *htsc);
126 void (* MspDeInitCallback)(struct __TSC_HandleTypeDef *htsc);
128#endif /* USE_HAL_TSC_REGISTER_CALLBACKS */
129} TSC_HandleTypeDef;
130
131enum
132{
133 TSC_GROUP1_IDX = 0x00UL,
134 TSC_GROUP2_IDX,
135 TSC_GROUP3_IDX,
136 TSC_GROUP4_IDX,
137 TSC_GROUP5_IDX,
138 TSC_GROUP6_IDX,
139 TSC_GROUP7_IDX,
140 TSC_GROUP8_IDX,
141 TSC_NB_OF_GROUPS
142};
143
144#if (USE_HAL_TSC_REGISTER_CALLBACKS == 1)
148typedef enum
149{
150 HAL_TSC_CONV_COMPLETE_CB_ID = 0x00UL,
151 HAL_TSC_ERROR_CB_ID = 0x01UL,
153 HAL_TSC_MSPINIT_CB_ID = 0x02UL,
154 HAL_TSC_MSPDEINIT_CB_ID = 0x03UL
156} HAL_TSC_CallbackIDTypeDef;
157
161typedef void (*pTSC_CallbackTypeDef)(TSC_HandleTypeDef *htsc);
163#endif /* USE_HAL_TSC_REGISTER_CALLBACKS */
164
169/* Exported constants --------------------------------------------------------*/
178#define HAL_TSC_ERROR_NONE 0x00000000UL
179#if (USE_HAL_TSC_REGISTER_CALLBACKS == 1)
180#define HAL_TSC_ERROR_INVALID_CALLBACK 0x00000001UL
181#endif /* USE_HAL_TSC_REGISTER_CALLBACKS */
189#define TSC_CTPH_1CYCLE 0x00000000UL
191#define TSC_CTPH_2CYCLES TSC_CR_CTPH_0
193#define TSC_CTPH_3CYCLES TSC_CR_CTPH_1
195#define TSC_CTPH_4CYCLES (TSC_CR_CTPH_1 | TSC_CR_CTPH_0)
197#define TSC_CTPH_5CYCLES TSC_CR_CTPH_2
199#define TSC_CTPH_6CYCLES (TSC_CR_CTPH_2 | TSC_CR_CTPH_0)
201#define TSC_CTPH_7CYCLES (TSC_CR_CTPH_2 | TSC_CR_CTPH_1)
203#define TSC_CTPH_8CYCLES (TSC_CR_CTPH_2 | TSC_CR_CTPH_1 | TSC_CR_CTPH_0)
205#define TSC_CTPH_9CYCLES TSC_CR_CTPH_3
207#define TSC_CTPH_10CYCLES (TSC_CR_CTPH_3 | TSC_CR_CTPH_0)
209#define TSC_CTPH_11CYCLES (TSC_CR_CTPH_3 | TSC_CR_CTPH_1)
211#define TSC_CTPH_12CYCLES (TSC_CR_CTPH_3 | TSC_CR_CTPH_1 | TSC_CR_CTPH_0)
213#define TSC_CTPH_13CYCLES (TSC_CR_CTPH_3 | TSC_CR_CTPH_2)
215#define TSC_CTPH_14CYCLES (TSC_CR_CTPH_3 | TSC_CR_CTPH_2 | TSC_CR_CTPH_0)
217#define TSC_CTPH_15CYCLES (TSC_CR_CTPH_3 | TSC_CR_CTPH_2 | TSC_CR_CTPH_1)
219#define TSC_CTPH_16CYCLES (TSC_CR_CTPH_3 | TSC_CR_CTPH_2 | TSC_CR_CTPH_1 | TSC_CR_CTPH_0)
228#define TSC_CTPL_1CYCLE 0x00000000UL
230#define TSC_CTPL_2CYCLES TSC_CR_CTPL_0
232#define TSC_CTPL_3CYCLES TSC_CR_CTPL_1
234#define TSC_CTPL_4CYCLES (TSC_CR_CTPL_1 | TSC_CR_CTPL_0)
236#define TSC_CTPL_5CYCLES TSC_CR_CTPL_2
238#define TSC_CTPL_6CYCLES (TSC_CR_CTPL_2 | TSC_CR_CTPL_0)
240#define TSC_CTPL_7CYCLES (TSC_CR_CTPL_2 | TSC_CR_CTPL_1)
242#define TSC_CTPL_8CYCLES (TSC_CR_CTPL_2 | TSC_CR_CTPL_1 | TSC_CR_CTPL_0)
244#define TSC_CTPL_9CYCLES TSC_CR_CTPL_3
246#define TSC_CTPL_10CYCLES (TSC_CR_CTPL_3 | TSC_CR_CTPL_0)
248#define TSC_CTPL_11CYCLES (TSC_CR_CTPL_3 | TSC_CR_CTPL_1)
250#define TSC_CTPL_12CYCLES (TSC_CR_CTPL_3 | TSC_CR_CTPL_1 | TSC_CR_CTPL_0)
252#define TSC_CTPL_13CYCLES (TSC_CR_CTPL_3 | TSC_CR_CTPL_2)
254#define TSC_CTPL_14CYCLES (TSC_CR_CTPL_3 | TSC_CR_CTPL_2 | TSC_CR_CTPL_0)
256#define TSC_CTPL_15CYCLES (TSC_CR_CTPL_3 | TSC_CR_CTPL_2 | TSC_CR_CTPL_1)
258#define TSC_CTPL_16CYCLES (TSC_CR_CTPL_3 | TSC_CR_CTPL_2 | TSC_CR_CTPL_1 | TSC_CR_CTPL_0)
267#define TSC_SS_PRESC_DIV1 0x00000000UL
268#define TSC_SS_PRESC_DIV2 TSC_CR_SSPSC
276#define TSC_PG_PRESC_DIV1 0x00000000UL
277#define TSC_PG_PRESC_DIV2 TSC_CR_PGPSC_0
278#define TSC_PG_PRESC_DIV4 TSC_CR_PGPSC_1
279#define TSC_PG_PRESC_DIV8 (TSC_CR_PGPSC_1 | TSC_CR_PGPSC_0)
280#define TSC_PG_PRESC_DIV16 TSC_CR_PGPSC_2
281#define TSC_PG_PRESC_DIV32 (TSC_CR_PGPSC_2 | TSC_CR_PGPSC_0)
282#define TSC_PG_PRESC_DIV64 (TSC_CR_PGPSC_2 | TSC_CR_PGPSC_1)
283#define TSC_PG_PRESC_DIV128 (TSC_CR_PGPSC_2 | TSC_CR_PGPSC_1 | TSC_CR_PGPSC_0)
291#define TSC_MCV_255 0x00000000UL
292#define TSC_MCV_511 TSC_CR_MCV_0
293#define TSC_MCV_1023 TSC_CR_MCV_1
294#define TSC_MCV_2047 (TSC_CR_MCV_1 | TSC_CR_MCV_0)
295#define TSC_MCV_4095 TSC_CR_MCV_2
296#define TSC_MCV_8191 (TSC_CR_MCV_2 | TSC_CR_MCV_0)
297#define TSC_MCV_16383 (TSC_CR_MCV_2 | TSC_CR_MCV_1)
305#define TSC_IODEF_OUT_PP_LOW 0x00000000UL
306#define TSC_IODEF_IN_FLOAT TSC_CR_IODEF
314#define TSC_SYNC_POLARITY_FALLING 0x00000000UL
315#define TSC_SYNC_POLARITY_RISING TSC_CR_SYNCPOL
323#define TSC_ACQ_MODE_NORMAL 0x00000000UL
325#define TSC_ACQ_MODE_SYNCHRO TSC_CR_AM
335#define TSC_IT_EOA TSC_IER_EOAIE
336#define TSC_IT_MCE TSC_IER_MCEIE
344#define TSC_FLAG_EOA TSC_ISR_EOAF
345#define TSC_FLAG_MCE TSC_ISR_MCEF
353#define TSC_GROUP1 (0x1UL << TSC_GROUP1_IDX)
354#define TSC_GROUP2 (0x1UL << TSC_GROUP2_IDX)
355#define TSC_GROUP3 (0x1UL << TSC_GROUP3_IDX)
356#define TSC_GROUP4 (0x1UL << TSC_GROUP4_IDX)
357#define TSC_GROUP5 (0x1UL << TSC_GROUP5_IDX)
358#define TSC_GROUP6 (0x1UL << TSC_GROUP6_IDX)
359#define TSC_GROUP7 (0x1UL << TSC_GROUP7_IDX)
360#define TSC_GROUP8 (0x1UL << TSC_GROUP8_IDX)
361
362#define TSC_GROUP1_IO1 TSC_IOCCR_G1_IO1
363#define TSC_GROUP1_IO2 TSC_IOCCR_G1_IO2
364#define TSC_GROUP1_IO3 TSC_IOCCR_G1_IO3
365#define TSC_GROUP1_IO4 TSC_IOCCR_G1_IO4
367#define TSC_GROUP2_IO1 TSC_IOCCR_G2_IO1
368#define TSC_GROUP2_IO2 TSC_IOCCR_G2_IO2
369#define TSC_GROUP2_IO3 TSC_IOCCR_G2_IO3
370#define TSC_GROUP2_IO4 TSC_IOCCR_G2_IO4
372#define TSC_GROUP3_IO1 TSC_IOCCR_G3_IO1
373#define TSC_GROUP3_IO2 TSC_IOCCR_G3_IO2
374#define TSC_GROUP3_IO3 TSC_IOCCR_G3_IO3
375#define TSC_GROUP3_IO4 TSC_IOCCR_G3_IO4
377#define TSC_GROUP4_IO1 TSC_IOCCR_G4_IO1
378#define TSC_GROUP4_IO2 TSC_IOCCR_G4_IO2
379#define TSC_GROUP4_IO3 TSC_IOCCR_G4_IO3
380#define TSC_GROUP4_IO4 TSC_IOCCR_G4_IO4
382#define TSC_GROUP5_IO1 TSC_IOCCR_G5_IO1
383#define TSC_GROUP5_IO2 TSC_IOCCR_G5_IO2
384#define TSC_GROUP5_IO3 TSC_IOCCR_G5_IO3
385#define TSC_GROUP5_IO4 TSC_IOCCR_G5_IO4
387#define TSC_GROUP6_IO1 TSC_IOCCR_G6_IO1
388#define TSC_GROUP6_IO2 TSC_IOCCR_G6_IO2
389#define TSC_GROUP6_IO3 TSC_IOCCR_G6_IO3
390#define TSC_GROUP6_IO4 TSC_IOCCR_G6_IO4
392#define TSC_GROUP7_IO1 TSC_IOCCR_G7_IO1
393#define TSC_GROUP7_IO2 TSC_IOCCR_G7_IO2
394#define TSC_GROUP7_IO3 TSC_IOCCR_G7_IO3
395#define TSC_GROUP7_IO4 TSC_IOCCR_G7_IO4
397#define TSC_GROUP8_IO1 TSC_IOCCR_G8_IO1
398#define TSC_GROUP8_IO2 TSC_IOCCR_G8_IO2
399#define TSC_GROUP8_IO3 TSC_IOCCR_G8_IO3
400#define TSC_GROUP8_IO4 TSC_IOCCR_G8_IO4
409/* Exported macros -----------------------------------------------------------*/
410
419#if (USE_HAL_TSC_REGISTER_CALLBACKS == 1)
420#define __HAL_TSC_RESET_HANDLE_STATE(__HANDLE__) do{ \
421 (__HANDLE__)->State = HAL_TSC_STATE_RESET; \
422 (__HANDLE__)->MspInitCallback = NULL; \
423 (__HANDLE__)->MspDeInitCallback = NULL; \
424 } while(0)
425#else
426#define __HAL_TSC_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_TSC_STATE_RESET)
427#endif /* (USE_HAL_TSC_REGISTER_CALLBACKS == 1) */
428
434#define __HAL_TSC_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->CR |= TSC_CR_TSCE)
435
441#define __HAL_TSC_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->CR &= (~TSC_CR_TSCE))
442
448#define __HAL_TSC_START_ACQ(__HANDLE__) ((__HANDLE__)->Instance->CR |= TSC_CR_START)
449
455#define __HAL_TSC_STOP_ACQ(__HANDLE__) ((__HANDLE__)->Instance->CR &= (~TSC_CR_START))
456
462#define __HAL_TSC_SET_IODEF_OUTPPLOW(__HANDLE__) ((__HANDLE__)->Instance->CR &= (~TSC_CR_IODEF))
463
469#define __HAL_TSC_SET_IODEF_INFLOAT(__HANDLE__) ((__HANDLE__)->Instance->CR |= TSC_CR_IODEF)
470
476#define __HAL_TSC_SET_SYNC_POL_FALL(__HANDLE__) ((__HANDLE__)->Instance->CR &= (~TSC_CR_SYNCPOL))
477
483#define __HAL_TSC_SET_SYNC_POL_RISE_HIGH(__HANDLE__) ((__HANDLE__)->Instance->CR |= TSC_CR_SYNCPOL)
484
491#define __HAL_TSC_ENABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->IER |= (__INTERRUPT__))
492
499#define __HAL_TSC_DISABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->IER &= (~(__INTERRUPT__)))
500
506#define __HAL_TSC_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) ((((__HANDLE__)->Instance->IER\
507 & (__INTERRUPT__)) == (__INTERRUPT__)) ? SET :\
508 RESET)
509
516#define __HAL_TSC_GET_FLAG(__HANDLE__, __FLAG__) ((((__HANDLE__)->Instance->ISR\
517 & (__FLAG__)) == (__FLAG__)) ? SET : RESET)
518
525#define __HAL_TSC_CLEAR_FLAG(__HANDLE__, __FLAG__) ((__HANDLE__)->Instance->ICR = (__FLAG__))
526
533#define __HAL_TSC_ENABLE_HYSTERESIS(__HANDLE__, __GX_IOY_MASK__) ((__HANDLE__)->Instance->IOHCR |= (__GX_IOY_MASK__))
534
541#define __HAL_TSC_DISABLE_HYSTERESIS(__HANDLE__, __GX_IOY_MASK__) ((__HANDLE__)->Instance->IOHCR\
542 &= (~(__GX_IOY_MASK__)))
543
550#define __HAL_TSC_OPEN_ANALOG_SWITCH(__HANDLE__, __GX_IOY_MASK__) ((__HANDLE__)->Instance->IOASCR\
551 &= (~(__GX_IOY_MASK__)))
552
559#define __HAL_TSC_CLOSE_ANALOG_SWITCH(__HANDLE__, __GX_IOY_MASK__) ((__HANDLE__)->Instance->IOASCR |= (__GX_IOY_MASK__))
560
567#define __HAL_TSC_ENABLE_CHANNEL(__HANDLE__, __GX_IOY_MASK__) ((__HANDLE__)->Instance->IOCCR |= (__GX_IOY_MASK__))
568
575#define __HAL_TSC_DISABLE_CHANNEL(__HANDLE__, __GX_IOY_MASK__) ((__HANDLE__)->Instance->IOCCR\
576 &= (~(__GX_IOY_MASK__)))
577
584#define __HAL_TSC_ENABLE_SAMPLING(__HANDLE__, __GX_IOY_MASK__) ((__HANDLE__)->Instance->IOSCR |= (__GX_IOY_MASK__))
585
592#define __HAL_TSC_DISABLE_SAMPLING(__HANDLE__, __GX_IOY_MASK__) ((__HANDLE__)->Instance->IOSCR &= (~(__GX_IOY_MASK__)))
593
600#define __HAL_TSC_ENABLE_GROUP(__HANDLE__, __GX_MASK__) ((__HANDLE__)->Instance->IOGCSR |= (__GX_MASK__))
601
608#define __HAL_TSC_DISABLE_GROUP(__HANDLE__, __GX_MASK__) ((__HANDLE__)->Instance->IOGCSR &= (~(__GX_MASK__)))
609
615#define __HAL_TSC_GET_GROUP_STATUS(__HANDLE__, __GX_INDEX__) \
616 ((((__HANDLE__)->Instance->IOGCSR & (uint32_t)(1UL << (((__GX_INDEX__) & 0xFUL) + 16UL))) == \
617 (uint32_t)(1UL << (((__GX_INDEX__) & 0xFUL) + 16UL))) ? TSC_GROUP_COMPLETED : TSC_GROUP_ONGOING)
618
623/* Private macros ------------------------------------------------------------*/
624
629#define IS_TSC_CTPH(__VALUE__) (((__VALUE__) == TSC_CTPH_1CYCLE) || \
630 ((__VALUE__) == TSC_CTPH_2CYCLES) || \
631 ((__VALUE__) == TSC_CTPH_3CYCLES) || \
632 ((__VALUE__) == TSC_CTPH_4CYCLES) || \
633 ((__VALUE__) == TSC_CTPH_5CYCLES) || \
634 ((__VALUE__) == TSC_CTPH_6CYCLES) || \
635 ((__VALUE__) == TSC_CTPH_7CYCLES) || \
636 ((__VALUE__) == TSC_CTPH_8CYCLES) || \
637 ((__VALUE__) == TSC_CTPH_9CYCLES) || \
638 ((__VALUE__) == TSC_CTPH_10CYCLES) || \
639 ((__VALUE__) == TSC_CTPH_11CYCLES) || \
640 ((__VALUE__) == TSC_CTPH_12CYCLES) || \
641 ((__VALUE__) == TSC_CTPH_13CYCLES) || \
642 ((__VALUE__) == TSC_CTPH_14CYCLES) || \
643 ((__VALUE__) == TSC_CTPH_15CYCLES) || \
644 ((__VALUE__) == TSC_CTPH_16CYCLES))
645
646#define IS_TSC_CTPL(__VALUE__) (((__VALUE__) == TSC_CTPL_1CYCLE) || \
647 ((__VALUE__) == TSC_CTPL_2CYCLES) || \
648 ((__VALUE__) == TSC_CTPL_3CYCLES) || \
649 ((__VALUE__) == TSC_CTPL_4CYCLES) || \
650 ((__VALUE__) == TSC_CTPL_5CYCLES) || \
651 ((__VALUE__) == TSC_CTPL_6CYCLES) || \
652 ((__VALUE__) == TSC_CTPL_7CYCLES) || \
653 ((__VALUE__) == TSC_CTPL_8CYCLES) || \
654 ((__VALUE__) == TSC_CTPL_9CYCLES) || \
655 ((__VALUE__) == TSC_CTPL_10CYCLES) || \
656 ((__VALUE__) == TSC_CTPL_11CYCLES) || \
657 ((__VALUE__) == TSC_CTPL_12CYCLES) || \
658 ((__VALUE__) == TSC_CTPL_13CYCLES) || \
659 ((__VALUE__) == TSC_CTPL_14CYCLES) || \
660 ((__VALUE__) == TSC_CTPL_15CYCLES) || \
661 ((__VALUE__) == TSC_CTPL_16CYCLES))
662
663#define IS_TSC_SS(__VALUE__) (((FunctionalState)(__VALUE__) == DISABLE)\
664 || ((FunctionalState)(__VALUE__) == ENABLE))
665
666#define IS_TSC_SSD(__VALUE__) (((__VALUE__) == 0UL) || (((__VALUE__) > 0UL) && ((__VALUE__) < 128UL)))
667
668#define IS_TSC_SS_PRESC(__VALUE__) (((__VALUE__) == TSC_SS_PRESC_DIV1) || ((__VALUE__) == TSC_SS_PRESC_DIV2))
669
670#define IS_TSC_PG_PRESC(__VALUE__) (((__VALUE__) == TSC_PG_PRESC_DIV1) || \
671 ((__VALUE__) == TSC_PG_PRESC_DIV2) || \
672 ((__VALUE__) == TSC_PG_PRESC_DIV4) || \
673 ((__VALUE__) == TSC_PG_PRESC_DIV8) || \
674 ((__VALUE__) == TSC_PG_PRESC_DIV16) || \
675 ((__VALUE__) == TSC_PG_PRESC_DIV32) || \
676 ((__VALUE__) == TSC_PG_PRESC_DIV64) || \
677 ((__VALUE__) == TSC_PG_PRESC_DIV128))
678
679#define IS_TSC_PG_PRESC_VS_CTPL(__PGPSC__, __CTPL__) ((((__PGPSC__) == TSC_PG_PRESC_DIV1) && \
680 ((__CTPL__) > TSC_CTPL_2CYCLES)) || \
681 (((__PGPSC__) == TSC_PG_PRESC_DIV2) && \
682 ((__CTPL__) > TSC_CTPL_1CYCLE)) || \
683 (((__PGPSC__) > TSC_PG_PRESC_DIV2) && \
684 (((__CTPL__) == TSC_CTPL_1CYCLE) || \
685 ((__CTPL__) > TSC_CTPL_1CYCLE))))
686
687#define IS_TSC_MCV(__VALUE__) (((__VALUE__) == TSC_MCV_255) || \
688 ((__VALUE__) == TSC_MCV_511) || \
689 ((__VALUE__) == TSC_MCV_1023) || \
690 ((__VALUE__) == TSC_MCV_2047) || \
691 ((__VALUE__) == TSC_MCV_4095) || \
692 ((__VALUE__) == TSC_MCV_8191) || \
693 ((__VALUE__) == TSC_MCV_16383))
694
695#define IS_TSC_IODEF(__VALUE__) (((__VALUE__) == TSC_IODEF_OUT_PP_LOW) || ((__VALUE__) == TSC_IODEF_IN_FLOAT))
696
697#define IS_TSC_SYNC_POL(__VALUE__) (((__VALUE__) == TSC_SYNC_POLARITY_FALLING)\
698 || ((__VALUE__) == TSC_SYNC_POLARITY_RISING))
699
700#define IS_TSC_ACQ_MODE(__VALUE__) (((__VALUE__) == TSC_ACQ_MODE_NORMAL) || ((__VALUE__) == TSC_ACQ_MODE_SYNCHRO))
701
702#define IS_TSC_MCE_IT(__VALUE__) (((FunctionalState)(__VALUE__) == DISABLE)\
703 || ((FunctionalState)(__VALUE__) == ENABLE))
704
705#define IS_TSC_GROUP_INDEX(__VALUE__) (((__VALUE__) == 0UL)\
706 || (((__VALUE__) > 0UL) && ((__VALUE__) < (uint32_t)TSC_NB_OF_GROUPS)))
707
708#define IS_TSC_GROUP(__VALUE__) (((__VALUE__) == 0UL) ||\
709 (((__VALUE__) & TSC_GROUP1_IO1) == TSC_GROUP1_IO1) ||\
710 (((__VALUE__) & TSC_GROUP1_IO2) == TSC_GROUP1_IO2) ||\
711 (((__VALUE__) & TSC_GROUP1_IO3) == TSC_GROUP1_IO3) ||\
712 (((__VALUE__) & TSC_GROUP1_IO4) == TSC_GROUP1_IO4) ||\
713 (((__VALUE__) & TSC_GROUP2_IO1) == TSC_GROUP2_IO1) ||\
714 (((__VALUE__) & TSC_GROUP2_IO2) == TSC_GROUP2_IO2) ||\
715 (((__VALUE__) & TSC_GROUP2_IO3) == TSC_GROUP2_IO3) ||\
716 (((__VALUE__) & TSC_GROUP2_IO4) == TSC_GROUP2_IO4) ||\
717 (((__VALUE__) & TSC_GROUP3_IO1) == TSC_GROUP3_IO1) ||\
718 (((__VALUE__) & TSC_GROUP3_IO2) == TSC_GROUP3_IO2) ||\
719 (((__VALUE__) & TSC_GROUP3_IO3) == TSC_GROUP3_IO3) ||\
720 (((__VALUE__) & TSC_GROUP3_IO4) == TSC_GROUP3_IO4) ||\
721 (((__VALUE__) & TSC_GROUP4_IO1) == TSC_GROUP4_IO1) ||\
722 (((__VALUE__) & TSC_GROUP4_IO2) == TSC_GROUP4_IO2) ||\
723 (((__VALUE__) & TSC_GROUP4_IO3) == TSC_GROUP4_IO3) ||\
724 (((__VALUE__) & TSC_GROUP4_IO4) == TSC_GROUP4_IO4) ||\
725 (((__VALUE__) & TSC_GROUP5_IO1) == TSC_GROUP5_IO1) ||\
726 (((__VALUE__) & TSC_GROUP5_IO2) == TSC_GROUP5_IO2) ||\
727 (((__VALUE__) & TSC_GROUP5_IO3) == TSC_GROUP5_IO3) ||\
728 (((__VALUE__) & TSC_GROUP5_IO4) == TSC_GROUP5_IO4) ||\
729 (((__VALUE__) & TSC_GROUP6_IO1) == TSC_GROUP6_IO1) ||\
730 (((__VALUE__) & TSC_GROUP6_IO2) == TSC_GROUP6_IO2) ||\
731 (((__VALUE__) & TSC_GROUP6_IO3) == TSC_GROUP6_IO3) ||\
732 (((__VALUE__) & TSC_GROUP6_IO4) == TSC_GROUP6_IO4) ||\
733 (((__VALUE__) & TSC_GROUP7_IO1) == TSC_GROUP7_IO1) ||\
734 (((__VALUE__) & TSC_GROUP7_IO2) == TSC_GROUP7_IO2) ||\
735 (((__VALUE__) & TSC_GROUP7_IO3) == TSC_GROUP7_IO3) ||\
736 (((__VALUE__) & TSC_GROUP7_IO4) == TSC_GROUP7_IO4) ||\
737 (((__VALUE__) & TSC_GROUP8_IO1) == TSC_GROUP8_IO1) ||\
738 (((__VALUE__) & TSC_GROUP8_IO2) == TSC_GROUP8_IO2) ||\
739 (((__VALUE__) & TSC_GROUP8_IO3) == TSC_GROUP8_IO3) ||\
740 (((__VALUE__) & TSC_GROUP8_IO4) == TSC_GROUP8_IO4))
745/* Exported functions --------------------------------------------------------*/
753/* Initialization and de-initialization functions *****************************/
754HAL_StatusTypeDef HAL_TSC_Init(TSC_HandleTypeDef *htsc);
755HAL_StatusTypeDef HAL_TSC_DeInit(TSC_HandleTypeDef *htsc);
756void HAL_TSC_MspInit(TSC_HandleTypeDef *htsc);
757void HAL_TSC_MspDeInit(TSC_HandleTypeDef *htsc);
758
759/* Callbacks Register/UnRegister functions ***********************************/
760#if (USE_HAL_TSC_REGISTER_CALLBACKS == 1)
761HAL_StatusTypeDef HAL_TSC_RegisterCallback(TSC_HandleTypeDef *htsc, HAL_TSC_CallbackIDTypeDef CallbackID,
762 pTSC_CallbackTypeDef pCallback);
763HAL_StatusTypeDef HAL_TSC_UnRegisterCallback(TSC_HandleTypeDef *htsc, HAL_TSC_CallbackIDTypeDef CallbackID);
764#endif /* USE_HAL_TSC_REGISTER_CALLBACKS */
772/* IO operation functions *****************************************************/
773HAL_StatusTypeDef HAL_TSC_Start(TSC_HandleTypeDef *htsc);
774HAL_StatusTypeDef HAL_TSC_Start_IT(TSC_HandleTypeDef *htsc);
775HAL_StatusTypeDef HAL_TSC_Stop(TSC_HandleTypeDef *htsc);
776HAL_StatusTypeDef HAL_TSC_Stop_IT(TSC_HandleTypeDef *htsc);
777HAL_StatusTypeDef HAL_TSC_PollForAcquisition(TSC_HandleTypeDef *htsc);
778TSC_GroupStatusTypeDef HAL_TSC_GroupGetStatus(const TSC_HandleTypeDef *htsc, uint32_t gx_index);
779uint32_t HAL_TSC_GroupGetValue(const TSC_HandleTypeDef *htsc, uint32_t gx_index);
787/* Peripheral Control functions ***********************************************/
788HAL_StatusTypeDef HAL_TSC_IOConfig(TSC_HandleTypeDef *htsc, const TSC_IOConfigTypeDef *config);
789HAL_StatusTypeDef HAL_TSC_IODischarge(TSC_HandleTypeDef *htsc, FunctionalState choice);
797/* Peripheral State and Error functions ***************************************/
798HAL_TSC_StateTypeDef HAL_TSC_GetState(TSC_HandleTypeDef *htsc);
806/******* TSC IRQHandler and Callbacks used in Interrupt mode */
807void HAL_TSC_IRQHandler(TSC_HandleTypeDef *htsc);
808void HAL_TSC_ConvCpltCallback(TSC_HandleTypeDef *htsc);
809void HAL_TSC_ErrorCallback(TSC_HandleTypeDef *htsc);
826#ifdef __cplusplus
827}
828#endif
829
830#endif /* STM32F3xx_HAL_TSC_H */
__IO
#define __IO
Definition: core_armv8mbl.h:196
FunctionalState
FunctionalState
Definition: stm32f3xx.h:170
HAL_TSC_MspDeInit
void HAL_TSC_MspDeInit(TSC_HandleTypeDef *htsc)
TSC MSP De-Initialization This function freeze the hardware resources used in this example.
Definition: stm32f3xx_hal_msp.c:170
HAL_TSC_Init
HAL_StatusTypeDef HAL_TSC_Init(TSC_HandleTypeDef *htsc)
HAL_TSC_DeInit
HAL_StatusTypeDef HAL_TSC_DeInit(TSC_HandleTypeDef *htsc)
HAL_TSC_MspInit
void HAL_TSC_MspInit(TSC_HandleTypeDef *htsc)
TSC MSP Initialization This function configures the hardware resources used in this example.
Definition: stm32f3xx_hal_msp.c:85
HAL_TSC_GroupGetStatus
TSC_GroupStatusTypeDef HAL_TSC_GroupGetStatus(const TSC_HandleTypeDef *htsc, uint32_t gx_index)
HAL_TSC_PollForAcquisition
HAL_StatusTypeDef HAL_TSC_PollForAcquisition(TSC_HandleTypeDef *htsc)
HAL_TSC_Stop_IT
HAL_StatusTypeDef HAL_TSC_Stop_IT(TSC_HandleTypeDef *htsc)
HAL_TSC_Start_IT
HAL_StatusTypeDef HAL_TSC_Start_IT(TSC_HandleTypeDef *htsc)
HAL_TSC_Start
HAL_StatusTypeDef HAL_TSC_Start(TSC_HandleTypeDef *htsc)
HAL_TSC_Stop
HAL_StatusTypeDef HAL_TSC_Stop(TSC_HandleTypeDef *htsc)
HAL_TSC_GroupGetValue
uint32_t HAL_TSC_GroupGetValue(const TSC_HandleTypeDef *htsc, uint32_t gx_index)
HAL_TSC_IOConfig
HAL_StatusTypeDef HAL_TSC_IOConfig(TSC_HandleTypeDef *htsc, const TSC_IOConfigTypeDef *config)
HAL_TSC_IODischarge
HAL_StatusTypeDef HAL_TSC_IODischarge(TSC_HandleTypeDef *htsc, FunctionalState choice)
HAL_TSC_GetState
HAL_TSC_StateTypeDef HAL_TSC_GetState(TSC_HandleTypeDef *htsc)
HAL_TSC_StateTypeDef
HAL_TSC_StateTypeDef
TSC state structure definition.
Definition: stm32f3xx_hal_tsc.h:48
TSC_GroupStatusTypeDef
TSC_GroupStatusTypeDef
TSC group status structure definition.
Definition: stm32f3xx_hal_tsc.h:59
HAL_TSC_STATE_ERROR
@ HAL_TSC_STATE_ERROR
Definition: stm32f3xx_hal_tsc.h:52
HAL_TSC_STATE_BUSY
@ HAL_TSC_STATE_BUSY
Definition: stm32f3xx_hal_tsc.h:51
HAL_TSC_STATE_RESET
@ HAL_TSC_STATE_RESET
Definition: stm32f3xx_hal_tsc.h:49
HAL_TSC_STATE_READY
@ HAL_TSC_STATE_READY
Definition: stm32f3xx_hal_tsc.h:50
TSC_GROUP4_IDX
@ TSC_GROUP4_IDX
Definition: stm32f3xx_hal_tsc.h:136
TSC_GROUP7_IDX
@ TSC_GROUP7_IDX
Definition: stm32f3xx_hal_tsc.h:139
TSC_GROUP2_IDX
@ TSC_GROUP2_IDX
Definition: stm32f3xx_hal_tsc.h:134
TSC_GROUP6_IDX
@ TSC_GROUP6_IDX
Definition: stm32f3xx_hal_tsc.h:138
TSC_GROUP3_IDX
@ TSC_GROUP3_IDX
Definition: stm32f3xx_hal_tsc.h:135
TSC_GROUP8_IDX
@ TSC_GROUP8_IDX
Definition: stm32f3xx_hal_tsc.h:140
TSC_GROUP5_IDX
@ TSC_GROUP5_IDX
Definition: stm32f3xx_hal_tsc.h:137
TSC_GROUP1_IDX
@ TSC_GROUP1_IDX
Definition: stm32f3xx_hal_tsc.h:133
TSC_NB_OF_GROUPS
@ TSC_NB_OF_GROUPS
Definition: stm32f3xx_hal_tsc.h:141
TSC_GROUP_ONGOING
@ TSC_GROUP_ONGOING
Definition: stm32f3xx_hal_tsc.h:60
TSC_GROUP_COMPLETED
@ TSC_GROUP_COMPLETED
Definition: stm32f3xx_hal_tsc.h:61
HAL_TSC_ErrorCallback
void HAL_TSC_ErrorCallback(TSC_HandleTypeDef *htsc)
HAL_TSC_IRQHandler
void HAL_TSC_IRQHandler(TSC_HandleTypeDef *htsc)
HAL_TSC_ConvCpltCallback
void HAL_TSC_ConvCpltCallback(TSC_HandleTypeDef *htsc)
htsc
TSC_HandleTypeDef htsc
Definition: main.cpp:68
stm32f3xx_hal_def.h
This file contains HAL common defines, enumeration, macros and structures definitions.
HAL_StatusTypeDef
HAL_StatusTypeDef
HAL Status structures definition
Definition: stm32f3xx_hal_def.h:39
HAL_LockTypeDef
HAL_LockTypeDef
HAL Lock structures definition
Definition: stm32f3xx_hal_def.h:50
TSC_HandleTypeDef
TSC handle Structure definition.
Definition: stm32f3xx_hal_tsc.h:114
TSC_HandleTypeDef::Lock
HAL_LockTypeDef Lock
Definition: stm32f3xx_hal_tsc.h:118
TSC_HandleTypeDef::ErrorCode
__IO uint32_t ErrorCode
Definition: stm32f3xx_hal_tsc.h:119
TSC_HandleTypeDef::State
__IO HAL_TSC_StateTypeDef State
Definition: stm32f3xx_hal_tsc.h:117
TSC_HandleTypeDef::Instance
TSC_TypeDef * Instance
Definition: stm32f3xx_hal_tsc.h:115
TSC_HandleTypeDef::Init
TSC_InitTypeDef Init
Definition: stm32f3xx_hal_tsc.h:116
TSC_IOConfigTypeDef
TSC IOs configuration structure definition.
Definition: stm32f3xx_hal_tsc.h:100
TSC_IOConfigTypeDef::SamplingIOs
uint32_t SamplingIOs
Definition: stm32f3xx_hal_tsc.h:103
TSC_IOConfigTypeDef::ChannelIOs
uint32_t ChannelIOs
Definition: stm32f3xx_hal_tsc.h:101
TSC_IOConfigTypeDef::ShieldIOs
uint32_t ShieldIOs
Definition: stm32f3xx_hal_tsc.h:102
TSC_InitTypeDef
TSC init structure definition.
Definition: stm32f3xx_hal_tsc.h:68
TSC_InitTypeDef::SamplingIOs
uint32_t SamplingIOs
Definition: stm32f3xx_hal_tsc.h:93
TSC_InitTypeDef::SpreadSpectrum
FunctionalState SpreadSpectrum
Definition: stm32f3xx_hal_tsc.h:73
TSC_InitTypeDef::SynchroPinPolarity
uint32_t SynchroPinPolarity
Definition: stm32f3xx_hal_tsc.h:85
TSC_InitTypeDef::MaxCountInterrupt
FunctionalState MaxCountInterrupt
Definition: stm32f3xx_hal_tsc.h:89
TSC_InitTypeDef::CTPulseHighLength
uint32_t CTPulseHighLength
Definition: stm32f3xx_hal_tsc.h:69
TSC_InitTypeDef::ShieldIOs
uint32_t ShieldIOs
Definition: stm32f3xx_hal_tsc.h:92
TSC_InitTypeDef::SpreadSpectrumPrescaler
uint32_t SpreadSpectrumPrescaler
Definition: stm32f3xx_hal_tsc.h:77
TSC_InitTypeDef::AcquisitionMode
uint32_t AcquisitionMode
Definition: stm32f3xx_hal_tsc.h:87
TSC_InitTypeDef::CTPulseLowLength
uint32_t CTPulseLowLength
Definition: stm32f3xx_hal_tsc.h:71
TSC_InitTypeDef::ChannelIOs
uint32_t ChannelIOs
Definition: stm32f3xx_hal_tsc.h:91
TSC_InitTypeDef::IODefaultMode
uint32_t IODefaultMode
Definition: stm32f3xx_hal_tsc.h:83
TSC_InitTypeDef::SpreadSpectrumDeviation
uint32_t SpreadSpectrumDeviation
Definition: stm32f3xx_hal_tsc.h:75
TSC_InitTypeDef::MaxCountValue
uint32_t MaxCountValue
Definition: stm32f3xx_hal_tsc.h:81
TSC_InitTypeDef::PulseGeneratorPrescaler
uint32_t PulseGeneratorPrescaler
Definition: stm32f3xx_hal_tsc.h:79
TSC_TypeDef
Touch Sensing Controller (TSC)
Definition: stm32f303xe.h:682