My Project
Loading...
Searching...
No Matches
stm32f3xx_ll_pwr.h
Go to the documentation of this file.
1
19/* Define to prevent recursive inclusion -------------------------------------*/
20#ifndef __STM32F3xx_LL_PWR_H
21#define __STM32F3xx_LL_PWR_H
22
23#ifdef __cplusplus
24extern "C" {
25#endif
26
27/* Includes ------------------------------------------------------------------*/
28#include "stm32f3xx.h"
29
34#if defined(PWR)
35
40/* Private types -------------------------------------------------------------*/
41/* Private variables ---------------------------------------------------------*/
42/* Private constants ---------------------------------------------------------*/
43/* Private macros ------------------------------------------------------------*/
44/* Exported types ------------------------------------------------------------*/
45/* Exported constants --------------------------------------------------------*/
54#define LL_PWR_CR_CSBF PWR_CR_CSBF
55#define LL_PWR_CR_CWUF PWR_CR_CWUF
64#define LL_PWR_CSR_WUF PWR_CSR_WUF
65#define LL_PWR_CSR_SBF PWR_CSR_SBF
66#if defined(PWR_PVD_SUPPORT)
67#define LL_PWR_CSR_PVDO PWR_CSR_PVDO
68#endif /* PWR_PVD_SUPPORT */
69#if defined(PWR_CSR_VREFINTRDYF)
70#define LL_PWR_CSR_VREFINTRDYF PWR_CSR_VREFINTRDYF
71#endif /* PWR_CSR_VREFINTRDYF */
72#define LL_PWR_CSR_EWUP1 PWR_CSR_EWUP1
73#define LL_PWR_CSR_EWUP2 PWR_CSR_EWUP2
74#if defined(PWR_CSR_EWUP3)
75#define LL_PWR_CSR_EWUP3 PWR_CSR_EWUP3
76#endif /* PWR_CSR_EWUP3 */
85#define LL_PWR_MODE_STOP_MAINREGU 0x00000000U
86#define LL_PWR_MODE_STOP_LPREGU (PWR_CR_LPDS)
87#define LL_PWR_MODE_STANDBY (PWR_CR_PDDS)
92#if defined(PWR_CR_LPDS)
96#define LL_PWR_REGU_DSMODE_MAIN 0x00000000U
97#define LL_PWR_REGU_DSMODE_LOW_POWER (PWR_CR_LPDS)
101#endif /* PWR_CR_LPDS */
102
103#if defined(PWR_PVD_SUPPORT)
107#define LL_PWR_PVDLEVEL_0 (PWR_CR_PLS_LEV0)
108#define LL_PWR_PVDLEVEL_1 (PWR_CR_PLS_LEV1)
109#define LL_PWR_PVDLEVEL_2 (PWR_CR_PLS_LEV2)
110#define LL_PWR_PVDLEVEL_3 (PWR_CR_PLS_LEV3)
111#define LL_PWR_PVDLEVEL_4 (PWR_CR_PLS_LEV4)
112#define LL_PWR_PVDLEVEL_5 (PWR_CR_PLS_LEV5)
113#define LL_PWR_PVDLEVEL_6 (PWR_CR_PLS_LEV6)
114#define LL_PWR_PVDLEVEL_7 (PWR_CR_PLS_LEV7)
118#endif /* PWR_PVD_SUPPORT */
122#define LL_PWR_WAKEUP_PIN1 (PWR_CSR_EWUP1)
123#define LL_PWR_WAKEUP_PIN2 (PWR_CSR_EWUP2)
124#if defined(PWR_CSR_EWUP3)
125#define LL_PWR_WAKEUP_PIN3 (PWR_CSR_EWUP3)
126#endif /* PWR_CSR_EWUP3 */
134#if defined(SDADC1)
135#define LL_PWR_SDADC_ANALOG1 (PWR_CR_ENSD1)
136#endif /* SDADC1 */
137#if defined(SDADC2)
138#define LL_PWR_SDADC_ANALOG2 (PWR_CR_ENSD2)
139#endif /* SDADC2 */
140#if defined(SDADC3)
141#define LL_PWR_SDADC_ANALOG3 (PWR_CR_ENSD3)
142#endif /* SDADC3 */
151/* Exported macro ------------------------------------------------------------*/
166#define LL_PWR_WriteReg(__REG__, __VALUE__) WRITE_REG(PWR->__REG__, (__VALUE__))
167
173#define LL_PWR_ReadReg(__REG__) READ_REG(PWR->__REG__)
182/* Exported functions --------------------------------------------------------*/
201__STATIC_INLINE void LL_PWR_EnableSDADC(uint32_t Analogx)
202{
203 SET_BIT(PWR->CR, Analogx);
204}
205
217__STATIC_INLINE void LL_PWR_DisableSDADC(uint32_t Analogx)
218{
219 CLEAR_BIT(PWR->CR, Analogx);
220}
221
233__STATIC_INLINE uint32_t LL_PWR_IsEnabledSDADC(uint32_t Analogx)
234{
235 return (READ_BIT(PWR->CR, Analogx) == (Analogx));
236}
237
243__STATIC_INLINE void LL_PWR_EnableBkUpAccess(void)
244{
245 SET_BIT(PWR->CR, PWR_CR_DBP);
246}
247
253__STATIC_INLINE void LL_PWR_DisableBkUpAccess(void)
254{
256}
257
263__STATIC_INLINE uint32_t LL_PWR_IsEnabledBkUpAccess(void)
264{
265 return (READ_BIT(PWR->CR, PWR_CR_DBP) == (PWR_CR_DBP));
266}
267
268#if defined(PWR_CR_LPDS)
277__STATIC_INLINE void LL_PWR_SetRegulModeDS(uint32_t RegulMode)
278{
279 MODIFY_REG(PWR->CR, PWR_CR_LPDS, RegulMode);
280}
281
289__STATIC_INLINE uint32_t LL_PWR_GetRegulModeDS(void)
290{
291 return (uint32_t)(READ_BIT(PWR->CR, PWR_CR_LPDS));
292}
293#endif /* PWR_CR_LPDS */
294
305__STATIC_INLINE void LL_PWR_SetPowerMode(uint32_t PDMode)
306{
307 MODIFY_REG(PWR->CR, (PWR_CR_PDDS| PWR_CR_LPDS), PDMode);
308}
309
319__STATIC_INLINE uint32_t LL_PWR_GetPowerMode(void)
320{
321 return (uint32_t)(READ_BIT(PWR->CR, (PWR_CR_PDDS| PWR_CR_LPDS)));
322}
323
324#if defined(PWR_PVD_SUPPORT)
339__STATIC_INLINE void LL_PWR_SetPVDLevel(uint32_t PVDLevel)
340{
341 MODIFY_REG(PWR->CR, PWR_CR_PLS, PVDLevel);
342}
343
357__STATIC_INLINE uint32_t LL_PWR_GetPVDLevel(void)
358{
359 return (uint32_t)(READ_BIT(PWR->CR, PWR_CR_PLS));
360}
361
367__STATIC_INLINE void LL_PWR_EnablePVD(void)
368{
369 SET_BIT(PWR->CR, PWR_CR_PVDE);
370}
371
377__STATIC_INLINE void LL_PWR_DisablePVD(void)
378{
380}
381
387__STATIC_INLINE uint32_t LL_PWR_IsEnabledPVD(void)
388{
389 return (READ_BIT(PWR->CR, PWR_CR_PVDE) == (PWR_CR_PVDE));
390}
391#endif /* PWR_PVD_SUPPORT */
392
406__STATIC_INLINE void LL_PWR_EnableWakeUpPin(uint32_t WakeUpPin)
407{
408 SET_BIT(PWR->CSR, WakeUpPin);
409}
410
424__STATIC_INLINE void LL_PWR_DisableWakeUpPin(uint32_t WakeUpPin)
425{
426 CLEAR_BIT(PWR->CSR, WakeUpPin);
427}
428
442__STATIC_INLINE uint32_t LL_PWR_IsEnabledWakeUpPin(uint32_t WakeUpPin)
443{
444 return (READ_BIT(PWR->CSR, WakeUpPin) == (WakeUpPin));
445}
446
447
461__STATIC_INLINE uint32_t LL_PWR_IsActiveFlag_WU(void)
462{
463 return (READ_BIT(PWR->CSR, PWR_CSR_WUF) == (PWR_CSR_WUF));
464}
465
471__STATIC_INLINE uint32_t LL_PWR_IsActiveFlag_SB(void)
472{
473 return (READ_BIT(PWR->CSR, PWR_CSR_SBF) == (PWR_CSR_SBF));
474}
475
476#if defined(PWR_PVD_SUPPORT)
482__STATIC_INLINE uint32_t LL_PWR_IsActiveFlag_PVDO(void)
483{
484 return (READ_BIT(PWR->CSR, PWR_CSR_PVDO) == (PWR_CSR_PVDO));
485}
486#endif /* PWR_PVD_SUPPORT */
487
488#if defined(PWR_CSR_VREFINTRDYF)
494__STATIC_INLINE uint32_t LL_PWR_IsActiveFlag_VREFINTRDY(void)
495{
497}
498#endif /* PWR_CSR_VREFINTRDYF */
504__STATIC_INLINE void LL_PWR_ClearFlag_SB(void)
505{
506 SET_BIT(PWR->CR, PWR_CR_CSBF);
507}
508
514__STATIC_INLINE void LL_PWR_ClearFlag_WU(void)
515{
516 SET_BIT(PWR->CR, PWR_CR_CWUF);
517}
518
523#if defined(USE_FULL_LL_DRIVER)
527ErrorStatus LL_PWR_DeInit(void);
531#endif /* USE_FULL_LL_DRIVER */
532
541#endif /* defined(PWR) */
542
547#ifdef __cplusplus
548}
549#endif
550
551#endif /* __STM32F3xx_LL_PWR_H */
#define __STATIC_INLINE
Definition: cmsis_armcc.h:59
#define CLEAR_BIT(REG, BIT)
Definition: stm32f3xx.h:192
#define SET_BIT(REG, BIT)
Definition: stm32f3xx.h:190
#define MODIFY_REG(REG, CLEARMASK, SETMASK)
Definition: stm32f3xx.h:202
#define READ_BIT(REG, BIT)
Definition: stm32f3xx.h:194
ErrorStatus
Definition: stm32f3xx.h:177
#define PWR_CR_PVDE
Definition: stm32f303xe.h:10649
#define PWR_CSR_PVDO
Definition: stm32f303xe.h:10681
#define PWR_CR_CWUF
Definition: stm32f303xe.h:10643
#define PWR_CR_LPDS
Definition: stm32f303xe.h:10637
#define PWR_CR_PDDS
Definition: stm32f303xe.h:10640
#define PWR_CSR_VREFINTRDYF
Definition: stm32f303xe.h:10684
#define PWR_CSR_WUF
Definition: stm32f303xe.h:10675
#define PWR_CR_CSBF
Definition: stm32f303xe.h:10646
#define PWR_CSR_SBF
Definition: stm32f303xe.h:10678
#define PWR_CR_PLS
Definition: stm32f303xe.h:10653
#define PWR_CR_DBP
Definition: stm32f303xe.h:10670
#define PWR
Definition: stm32f303xe.h:931
CMSIS STM32F3xx Device Peripheral Access Layer Header File.