20#ifndef __STM32F3xx_LL_PWR_H
21#define __STM32F3xx_LL_PWR_H
54#define LL_PWR_CR_CSBF PWR_CR_CSBF
55#define LL_PWR_CR_CWUF PWR_CR_CWUF
64#define LL_PWR_CSR_WUF PWR_CSR_WUF
65#define LL_PWR_CSR_SBF PWR_CSR_SBF
66#if defined(PWR_PVD_SUPPORT)
67#define LL_PWR_CSR_PVDO PWR_CSR_PVDO
69#if defined(PWR_CSR_VREFINTRDYF)
70#define LL_PWR_CSR_VREFINTRDYF PWR_CSR_VREFINTRDYF
72#define LL_PWR_CSR_EWUP1 PWR_CSR_EWUP1
73#define LL_PWR_CSR_EWUP2 PWR_CSR_EWUP2
74#if defined(PWR_CSR_EWUP3)
75#define LL_PWR_CSR_EWUP3 PWR_CSR_EWUP3
85#define LL_PWR_MODE_STOP_MAINREGU 0x00000000U
86#define LL_PWR_MODE_STOP_LPREGU (PWR_CR_LPDS)
87#define LL_PWR_MODE_STANDBY (PWR_CR_PDDS)
92#if defined(PWR_CR_LPDS)
96#define LL_PWR_REGU_DSMODE_MAIN 0x00000000U
97#define LL_PWR_REGU_DSMODE_LOW_POWER (PWR_CR_LPDS)
103#if defined(PWR_PVD_SUPPORT)
107#define LL_PWR_PVDLEVEL_0 (PWR_CR_PLS_LEV0)
108#define LL_PWR_PVDLEVEL_1 (PWR_CR_PLS_LEV1)
109#define LL_PWR_PVDLEVEL_2 (PWR_CR_PLS_LEV2)
110#define LL_PWR_PVDLEVEL_3 (PWR_CR_PLS_LEV3)
111#define LL_PWR_PVDLEVEL_4 (PWR_CR_PLS_LEV4)
112#define LL_PWR_PVDLEVEL_5 (PWR_CR_PLS_LEV5)
113#define LL_PWR_PVDLEVEL_6 (PWR_CR_PLS_LEV6)
114#define LL_PWR_PVDLEVEL_7 (PWR_CR_PLS_LEV7)
122#define LL_PWR_WAKEUP_PIN1 (PWR_CSR_EWUP1)
123#define LL_PWR_WAKEUP_PIN2 (PWR_CSR_EWUP2)
124#if defined(PWR_CSR_EWUP3)
125#define LL_PWR_WAKEUP_PIN3 (PWR_CSR_EWUP3)
135#define LL_PWR_SDADC_ANALOG1 (PWR_CR_ENSD1)
138#define LL_PWR_SDADC_ANALOG2 (PWR_CR_ENSD2)
141#define LL_PWR_SDADC_ANALOG3 (PWR_CR_ENSD3)
166#define LL_PWR_WriteReg(__REG__, __VALUE__) WRITE_REG(PWR->__REG__, (__VALUE__))
173#define LL_PWR_ReadReg(__REG__) READ_REG(PWR->__REG__)
268#if defined(PWR_CR_LPDS)
324#if defined(PWR_PVD_SUPPORT)
444 return (
READ_BIT(
PWR->CSR, WakeUpPin) == (WakeUpPin));
476#if defined(PWR_PVD_SUPPORT)
488#if defined(PWR_CSR_VREFINTRDYF)
523#if defined(USE_FULL_LL_DRIVER)
#define __STATIC_INLINE
Definition: cmsis_armcc.h:59
#define CLEAR_BIT(REG, BIT)
Definition: stm32f3xx.h:192
#define SET_BIT(REG, BIT)
Definition: stm32f3xx.h:190
#define MODIFY_REG(REG, CLEARMASK, SETMASK)
Definition: stm32f3xx.h:202
#define READ_BIT(REG, BIT)
Definition: stm32f3xx.h:194
ErrorStatus
Definition: stm32f3xx.h:177
#define PWR_CR_PVDE
Definition: stm32f303xe.h:10649
#define PWR_CSR_PVDO
Definition: stm32f303xe.h:10681
#define PWR_CR_CWUF
Definition: stm32f303xe.h:10643
#define PWR_CR_LPDS
Definition: stm32f303xe.h:10637
#define PWR_CR_PDDS
Definition: stm32f303xe.h:10640
#define PWR_CSR_VREFINTRDYF
Definition: stm32f303xe.h:10684
#define PWR_CSR_WUF
Definition: stm32f303xe.h:10675
#define PWR_CR_CSBF
Definition: stm32f303xe.h:10646
#define PWR_CSR_SBF
Definition: stm32f303xe.h:10678
#define PWR_CR_PLS
Definition: stm32f303xe.h:10653
#define PWR_CR_DBP
Definition: stm32f303xe.h:10670
#define PWR
Definition: stm32f303xe.h:931
CMSIS STM32F3xx Device Peripheral Access Layer Header File.