19#ifndef __STM32F3xx_LL_RCC_H
20#define __STM32F3xx_LL_RCC_H
46#define RCC_POSITION_HPRE (uint32_t)POSITION_VAL(RCC_CFGR_HPRE)
47#define RCC_POSITION_PPRE1 (uint32_t)POSITION_VAL(RCC_CFGR_PPRE1)
48#define RCC_POSITION_PPRE2 (uint32_t)POSITION_VAL(RCC_CFGR_PPRE2)
49#define RCC_POSITION_HSICAL (uint32_t)POSITION_VAL(RCC_CR_HSICAL)
50#define RCC_POSITION_HSITRIM (uint32_t)POSITION_VAL(RCC_CR_HSITRIM)
51#define RCC_POSITION_PLLMUL (uint32_t)POSITION_VAL(RCC_CFGR_PLLMUL)
52#define RCC_POSITION_USART1SW (uint32_t)0U
53#define RCC_POSITION_USART2SW (uint32_t)16U
54#define RCC_POSITION_USART3SW (uint32_t)18U
55#define RCC_POSITION_TIM1SW (uint32_t)8U
56#define RCC_POSITION_TIM8SW (uint32_t)9U
57#define RCC_POSITION_TIM15SW (uint32_t)10U
58#define RCC_POSITION_TIM16SW (uint32_t)11U
59#define RCC_POSITION_TIM17SW (uint32_t)13U
60#define RCC_POSITION_TIM20SW (uint32_t)15U
61#define RCC_POSITION_TIM2SW (uint32_t)24U
62#define RCC_POSITION_TIM34SW (uint32_t)25U
69#if defined(USE_FULL_LL_DRIVER)
78#if defined(USE_FULL_LL_DRIVER)
92 uint32_t SYSCLK_Frequency;
93 uint32_t HCLK_Frequency;
94 uint32_t PCLK1_Frequency;
95 uint32_t PCLK2_Frequency;
96} LL_RCC_ClocksTypeDef;
118#if !defined (HSE_VALUE)
119#define HSE_VALUE 8000000U
122#if !defined (HSI_VALUE)
123#define HSI_VALUE 8000000U
126#if !defined (LSE_VALUE)
127#define LSE_VALUE 32768U
130#if !defined (LSI_VALUE)
131#define LSI_VALUE 40000U
134#if !defined (EXTERNAL_CLOCK_VALUE)
135#define EXTERNAL_CLOCK_VALUE 12288000U
145#define LL_RCC_CIR_LSIRDYC RCC_CIR_LSIRDYC
146#define LL_RCC_CIR_LSERDYC RCC_CIR_LSERDYC
147#define LL_RCC_CIR_HSIRDYC RCC_CIR_HSIRDYC
148#define LL_RCC_CIR_HSERDYC RCC_CIR_HSERDYC
149#define LL_RCC_CIR_PLLRDYC RCC_CIR_PLLRDYC
150#define LL_RCC_CIR_CSSC RCC_CIR_CSSC
159#define LL_RCC_CIR_LSIRDYF RCC_CIR_LSIRDYF
160#define LL_RCC_CIR_LSERDYF RCC_CIR_LSERDYF
161#define LL_RCC_CIR_HSIRDYF RCC_CIR_HSIRDYF
162#define LL_RCC_CIR_HSERDYF RCC_CIR_HSERDYF
163#define LL_RCC_CFGR_MCOF RCC_CFGR_MCOF
164#define LL_RCC_CIR_PLLRDYF RCC_CIR_PLLRDYF
165#define LL_RCC_CIR_CSSF RCC_CIR_CSSF
166#define LL_RCC_CSR_OBLRSTF RCC_CSR_OBLRSTF
167#define LL_RCC_CSR_PINRSTF RCC_CSR_PINRSTF
168#define LL_RCC_CSR_PORRSTF RCC_CSR_PORRSTF
169#define LL_RCC_CSR_SFTRSTF RCC_CSR_SFTRSTF
170#define LL_RCC_CSR_IWDGRSTF RCC_CSR_IWDGRSTF
171#define LL_RCC_CSR_WWDGRSTF RCC_CSR_WWDGRSTF
172#define LL_RCC_CSR_LPWRRSTF RCC_CSR_LPWRRSTF
173#if defined(RCC_CSR_V18PWRRSTF)
174#define LL_RCC_CSR_V18PWRRSTF RCC_CSR_V18PWRRSTF
184#define LL_RCC_CIR_LSIRDYIE RCC_CIR_LSIRDYIE
185#define LL_RCC_CIR_LSERDYIE RCC_CIR_LSERDYIE
186#define LL_RCC_CIR_HSIRDYIE RCC_CIR_HSIRDYIE
187#define LL_RCC_CIR_HSERDYIE RCC_CIR_HSERDYIE
188#define LL_RCC_CIR_PLLRDYIE RCC_CIR_PLLRDYIE
196#define LL_RCC_LSEDRIVE_LOW ((uint32_t)0x00000000U)
197#define LL_RCC_LSEDRIVE_MEDIUMLOW RCC_BDCR_LSEDRV_1
198#define LL_RCC_LSEDRIVE_MEDIUMHIGH RCC_BDCR_LSEDRV_0
199#define LL_RCC_LSEDRIVE_HIGH RCC_BDCR_LSEDRV
207#define LL_RCC_SYS_CLKSOURCE_HSI RCC_CFGR_SW_HSI
208#define LL_RCC_SYS_CLKSOURCE_HSE RCC_CFGR_SW_HSE
209#define LL_RCC_SYS_CLKSOURCE_PLL RCC_CFGR_SW_PLL
217#define LL_RCC_SYS_CLKSOURCE_STATUS_HSI RCC_CFGR_SWS_HSI
218#define LL_RCC_SYS_CLKSOURCE_STATUS_HSE RCC_CFGR_SWS_HSE
219#define LL_RCC_SYS_CLKSOURCE_STATUS_PLL RCC_CFGR_SWS_PLL
227#define LL_RCC_SYSCLK_DIV_1 RCC_CFGR_HPRE_DIV1
228#define LL_RCC_SYSCLK_DIV_2 RCC_CFGR_HPRE_DIV2
229#define LL_RCC_SYSCLK_DIV_4 RCC_CFGR_HPRE_DIV4
230#define LL_RCC_SYSCLK_DIV_8 RCC_CFGR_HPRE_DIV8
231#define LL_RCC_SYSCLK_DIV_16 RCC_CFGR_HPRE_DIV16
232#define LL_RCC_SYSCLK_DIV_64 RCC_CFGR_HPRE_DIV64
233#define LL_RCC_SYSCLK_DIV_128 RCC_CFGR_HPRE_DIV128
234#define LL_RCC_SYSCLK_DIV_256 RCC_CFGR_HPRE_DIV256
235#define LL_RCC_SYSCLK_DIV_512 RCC_CFGR_HPRE_DIV512
243#define LL_RCC_APB1_DIV_1 RCC_CFGR_PPRE1_DIV1
244#define LL_RCC_APB1_DIV_2 RCC_CFGR_PPRE1_DIV2
245#define LL_RCC_APB1_DIV_4 RCC_CFGR_PPRE1_DIV4
246#define LL_RCC_APB1_DIV_8 RCC_CFGR_PPRE1_DIV8
247#define LL_RCC_APB1_DIV_16 RCC_CFGR_PPRE1_DIV16
255#define LL_RCC_APB2_DIV_1 RCC_CFGR_PPRE2_DIV1
256#define LL_RCC_APB2_DIV_2 RCC_CFGR_PPRE2_DIV2
257#define LL_RCC_APB2_DIV_4 RCC_CFGR_PPRE2_DIV4
258#define LL_RCC_APB2_DIV_8 RCC_CFGR_PPRE2_DIV8
259#define LL_RCC_APB2_DIV_16 RCC_CFGR_PPRE2_DIV16
267#define LL_RCC_MCO1SOURCE_NOCLOCK RCC_CFGR_MCOSEL_NOCLOCK
268#define LL_RCC_MCO1SOURCE_SYSCLK RCC_CFGR_MCOSEL_SYSCLK
269#define LL_RCC_MCO1SOURCE_HSI RCC_CFGR_MCOSEL_HSI
270#define LL_RCC_MCO1SOURCE_HSE RCC_CFGR_MCOSEL_HSE
271#define LL_RCC_MCO1SOURCE_LSI RCC_CFGR_MCOSEL_LSI
272#define LL_RCC_MCO1SOURCE_LSE RCC_CFGR_MCOSEL_LSE
273#define LL_RCC_MCO1SOURCE_PLLCLK_DIV_2 RCC_CFGR_MCOSEL_PLL_DIV2
274#if defined(RCC_CFGR_PLLNODIV)
275#define LL_RCC_MCO1SOURCE_PLLCLK (RCC_CFGR_MCOSEL_PLL_DIV2 | RCC_CFGR_PLLNODIV)
284#define LL_RCC_MCO1_DIV_1 ((uint32_t)0x00000000U)
285#if defined(RCC_CFGR_MCOPRE)
286#define LL_RCC_MCO1_DIV_2 RCC_CFGR_MCOPRE_DIV2
287#define LL_RCC_MCO1_DIV_4 RCC_CFGR_MCOPRE_DIV4
288#define LL_RCC_MCO1_DIV_8 RCC_CFGR_MCOPRE_DIV8
289#define LL_RCC_MCO1_DIV_16 RCC_CFGR_MCOPRE_DIV16
290#define LL_RCC_MCO1_DIV_32 RCC_CFGR_MCOPRE_DIV32
291#define LL_RCC_MCO1_DIV_64 RCC_CFGR_MCOPRE_DIV64
292#define LL_RCC_MCO1_DIV_128 RCC_CFGR_MCOPRE_DIV128
298#if defined(USE_FULL_LL_DRIVER)
302#define LL_RCC_PERIPH_FREQUENCY_NO 0x00000000U
303#define LL_RCC_PERIPH_FREQUENCY_NA 0xFFFFFFFFU
312#if defined(RCC_CFGR3_USART1SW_PCLK1)
313#define LL_RCC_USART1_CLKSOURCE_PCLK1 (uint32_t)((RCC_POSITION_USART1SW << 24U) | RCC_CFGR3_USART1SW_PCLK1)
315#define LL_RCC_USART1_CLKSOURCE_PCLK2 (uint32_t)((RCC_POSITION_USART1SW << 24U) | RCC_CFGR3_USART1SW_PCLK2)
317#define LL_RCC_USART1_CLKSOURCE_SYSCLK (uint32_t)((RCC_POSITION_USART1SW << 24U) | RCC_CFGR3_USART1SW_SYSCLK)
318#define LL_RCC_USART1_CLKSOURCE_LSE (uint32_t)((RCC_POSITION_USART1SW << 24U) | RCC_CFGR3_USART1SW_LSE)
319#define LL_RCC_USART1_CLKSOURCE_HSI (uint32_t)((RCC_POSITION_USART1SW << 24U) | RCC_CFGR3_USART1SW_HSI)
320#if defined(RCC_CFGR3_USART2SW)
321#define LL_RCC_USART2_CLKSOURCE_PCLK1 (uint32_t)((RCC_POSITION_USART2SW << 24U) | RCC_CFGR3_USART2SW_PCLK)
322#define LL_RCC_USART2_CLKSOURCE_SYSCLK (uint32_t)((RCC_POSITION_USART2SW << 24U) | RCC_CFGR3_USART2SW_SYSCLK)
323#define LL_RCC_USART2_CLKSOURCE_LSE (uint32_t)((RCC_POSITION_USART2SW << 24U) | RCC_CFGR3_USART2SW_LSE)
324#define LL_RCC_USART2_CLKSOURCE_HSI (uint32_t)((RCC_POSITION_USART2SW << 24U) | RCC_CFGR3_USART2SW_HSI)
326#if defined(RCC_CFGR3_USART3SW)
327#define LL_RCC_USART3_CLKSOURCE_PCLK1 (uint32_t)((RCC_POSITION_USART3SW << 24U) | RCC_CFGR3_USART3SW_PCLK)
328#define LL_RCC_USART3_CLKSOURCE_SYSCLK (uint32_t)((RCC_POSITION_USART3SW << 24U) | RCC_CFGR3_USART3SW_SYSCLK)
329#define LL_RCC_USART3_CLKSOURCE_LSE (uint32_t)((RCC_POSITION_USART3SW << 24U) | RCC_CFGR3_USART3SW_LSE)
330#define LL_RCC_USART3_CLKSOURCE_HSI (uint32_t)((RCC_POSITION_USART3SW << 24U) | RCC_CFGR3_USART3SW_HSI)
336#if defined(RCC_CFGR3_UART4SW) || defined(RCC_CFGR3_UART5SW)
340#define LL_RCC_UART4_CLKSOURCE_PCLK1 (uint32_t)((RCC_CFGR3_UART4SW >> 8U) | RCC_CFGR3_UART4SW_PCLK)
341#define LL_RCC_UART4_CLKSOURCE_SYSCLK (uint32_t)((RCC_CFGR3_UART4SW >> 8U) | RCC_CFGR3_UART4SW_SYSCLK)
342#define LL_RCC_UART4_CLKSOURCE_LSE (uint32_t)((RCC_CFGR3_UART4SW >> 8U) | RCC_CFGR3_UART4SW_LSE)
343#define LL_RCC_UART4_CLKSOURCE_HSI (uint32_t)((RCC_CFGR3_UART4SW >> 8U) | RCC_CFGR3_UART4SW_HSI)
344#define LL_RCC_UART5_CLKSOURCE_PCLK1 (uint32_t)((RCC_CFGR3_UART5SW >> 8U) | RCC_CFGR3_UART5SW_PCLK)
345#define LL_RCC_UART5_CLKSOURCE_SYSCLK (uint32_t)((RCC_CFGR3_UART5SW >> 8U) | RCC_CFGR3_UART5SW_SYSCLK)
346#define LL_RCC_UART5_CLKSOURCE_LSE (uint32_t)((RCC_CFGR3_UART5SW >> 8U) | RCC_CFGR3_UART5SW_LSE)
347#define LL_RCC_UART5_CLKSOURCE_HSI (uint32_t)((RCC_CFGR3_UART5SW >> 8U) | RCC_CFGR3_UART5SW_HSI)
357#define LL_RCC_I2C1_CLKSOURCE_HSI (uint32_t)((RCC_CFGR3_I2C1SW << 24U) | RCC_CFGR3_I2C1SW_HSI)
358#define LL_RCC_I2C1_CLKSOURCE_SYSCLK (uint32_t)((RCC_CFGR3_I2C1SW << 24U) | RCC_CFGR3_I2C1SW_SYSCLK)
359#if defined(RCC_CFGR3_I2C2SW)
360#define LL_RCC_I2C2_CLKSOURCE_HSI (uint32_t)((RCC_CFGR3_I2C2SW << 24U) | RCC_CFGR3_I2C2SW_HSI)
361#define LL_RCC_I2C2_CLKSOURCE_SYSCLK (uint32_t)((RCC_CFGR3_I2C2SW << 24U) | RCC_CFGR3_I2C2SW_SYSCLK)
363#if defined(RCC_CFGR3_I2C3SW)
364#define LL_RCC_I2C3_CLKSOURCE_HSI (uint32_t)((RCC_CFGR3_I2C3SW << 24U) | RCC_CFGR3_I2C3SW_HSI)
365#define LL_RCC_I2C3_CLKSOURCE_SYSCLK (uint32_t)((RCC_CFGR3_I2C3SW << 24U) | RCC_CFGR3_I2C3SW_SYSCLK)
371#if defined(RCC_CFGR_I2SSRC)
375#define LL_RCC_I2S_CLKSOURCE_SYSCLK RCC_CFGR_I2SSRC_SYSCLK
376#define LL_RCC_I2S_CLKSOURCE_PIN RCC_CFGR_I2SSRC_EXT
383#if defined(RCC_CFGR3_TIMSW)
387#define LL_RCC_TIM1_CLKSOURCE_PCLK2 (uint32_t)(((RCC_POSITION_TIM1SW - RCC_POSITION_TIM1SW) << 27U) | RCC_CFGR3_TIM1SW_PCLK2)
388#define LL_RCC_TIM1_CLKSOURCE_PLL (uint32_t)(((RCC_POSITION_TIM1SW - RCC_POSITION_TIM1SW) << 27U) | RCC_CFGR3_TIM1SW_PLL)
389#if defined(RCC_CFGR3_TIM8SW)
390#define LL_RCC_TIM8_CLKSOURCE_PCLK2 (uint32_t)(((RCC_POSITION_TIM8SW - RCC_POSITION_TIM1SW) << 27U) | RCC_CFGR3_TIM8SW_PCLK2)
391#define LL_RCC_TIM8_CLKSOURCE_PLL (uint32_t)(((RCC_POSITION_TIM8SW - RCC_POSITION_TIM1SW) << 27U) | RCC_CFGR3_TIM8SW_PLL)
393#if defined(RCC_CFGR3_TIM15SW)
394#define LL_RCC_TIM15_CLKSOURCE_PCLK2 (uint32_t)(((RCC_POSITION_TIM15SW - RCC_POSITION_TIM1SW) << 27U) | RCC_CFGR3_TIM15SW_PCLK2)
395#define LL_RCC_TIM15_CLKSOURCE_PLL (uint32_t)(((RCC_POSITION_TIM15SW - RCC_POSITION_TIM1SW) << 27U) | RCC_CFGR3_TIM15SW_PLL)
397#if defined(RCC_CFGR3_TIM16SW)
398#define LL_RCC_TIM16_CLKSOURCE_PCLK2 (uint32_t)(((RCC_POSITION_TIM16SW - RCC_POSITION_TIM1SW) << 27U) | RCC_CFGR3_TIM16SW_PCLK2)
399#define LL_RCC_TIM16_CLKSOURCE_PLL (uint32_t)(((RCC_POSITION_TIM16SW - RCC_POSITION_TIM1SW) << 27U) | RCC_CFGR3_TIM16SW_PLL)
401#if defined(RCC_CFGR3_TIM17SW)
402#define LL_RCC_TIM17_CLKSOURCE_PCLK2 (uint32_t)(((RCC_POSITION_TIM17SW - RCC_POSITION_TIM1SW) << 27U) | RCC_CFGR3_TIM17SW_PCLK2)
403#define LL_RCC_TIM17_CLKSOURCE_PLL (uint32_t)(((RCC_POSITION_TIM17SW - RCC_POSITION_TIM1SW) << 27U) | RCC_CFGR3_TIM17SW_PLL)
405#if defined(RCC_CFGR3_TIM20SW)
406#define LL_RCC_TIM20_CLKSOURCE_PCLK2 (uint32_t)(((RCC_POSITION_TIM20SW - RCC_POSITION_TIM1SW) << 27U) | RCC_CFGR3_TIM20SW_PCLK2)
407#define LL_RCC_TIM20_CLKSOURCE_PLL (uint32_t)(((RCC_POSITION_TIM20SW - RCC_POSITION_TIM1SW) << 27U) | RCC_CFGR3_TIM20SW_PLL)
409#if defined(RCC_CFGR3_TIM2SW)
410#define LL_RCC_TIM2_CLKSOURCE_PCLK1 (uint32_t)(((RCC_POSITION_TIM2SW - RCC_POSITION_TIM1SW) << 27U) | RCC_CFGR3_TIM2SW_PCLK1)
411#define LL_RCC_TIM2_CLKSOURCE_PLL (uint32_t)(((RCC_POSITION_TIM2SW - RCC_POSITION_TIM1SW) << 27U) | RCC_CFGR3_TIM2SW_PLL)
413#if defined(RCC_CFGR3_TIM34SW)
414#define LL_RCC_TIM34_CLKSOURCE_PCLK1 (uint32_t)(((RCC_POSITION_TIM34SW - RCC_POSITION_TIM1SW) << 27U) | RCC_CFGR3_TIM34SW_PCLK1)
415#define LL_RCC_TIM34_CLKSOURCE_PLL (uint32_t)(((RCC_POSITION_TIM34SW - RCC_POSITION_TIM1SW) << 27U) | RCC_CFGR3_TIM34SW_PLL)
427#define LL_RCC_HRTIM1_CLKSOURCE_PCLK2 RCC_CFGR3_HRTIM1SW_PCLK2
428#define LL_RCC_HRTIM1_CLKSOURCE_PLL RCC_CFGR3_HRTIM1SW_PLL
439#define LL_RCC_CEC_CLKSOURCE_HSI_DIV244 RCC_CFGR3_CECSW_HSI_DIV244
440#define LL_RCC_CEC_CLKSOURCE_LSE RCC_CFGR3_CECSW_LSE
451#define LL_RCC_USB_CLKSOURCE_PLL RCC_CFGR_USBPRE_DIV1
452#define LL_RCC_USB_CLKSOURCE_PLL_DIV_1_5 RCC_CFGR_USBPRE_DIV1_5
459#if defined(RCC_CFGR_ADCPRE)
463#define LL_RCC_ADC_CLKSRC_PCLK2_DIV_2 RCC_CFGR_ADCPRE_DIV2
464#define LL_RCC_ADC_CLKSRC_PCLK2_DIV_4 RCC_CFGR_ADCPRE_DIV4
465#define LL_RCC_ADC_CLKSRC_PCLK2_DIV_6 RCC_CFGR_ADCPRE_DIV6
466#define LL_RCC_ADC_CLKSRC_PCLK2_DIV_8 RCC_CFGR_ADCPRE_DIV8
471#elif defined(RCC_CFGR2_ADC1PRES)
475#define LL_RCC_ADC1_CLKSRC_HCLK RCC_CFGR2_ADC1PRES_NO
476#define LL_RCC_ADC1_CLKSRC_PLL_DIV_1 RCC_CFGR2_ADC1PRES_DIV1
477#define LL_RCC_ADC1_CLKSRC_PLL_DIV_2 RCC_CFGR2_ADC1PRES_DIV2
478#define LL_RCC_ADC1_CLKSRC_PLL_DIV_4 RCC_CFGR2_ADC1PRES_DIV4
479#define LL_RCC_ADC1_CLKSRC_PLL_DIV_6 RCC_CFGR2_ADC1PRES_DIV6
480#define LL_RCC_ADC1_CLKSRC_PLL_DIV_8 RCC_CFGR2_ADC1PRES_DIV8
481#define LL_RCC_ADC1_CLKSRC_PLL_DIV_10 RCC_CFGR2_ADC1PRES_DIV10
482#define LL_RCC_ADC1_CLKSRC_PLL_DIV_12 RCC_CFGR2_ADC1PRES_DIV12
483#define LL_RCC_ADC1_CLKSRC_PLL_DIV_16 RCC_CFGR2_ADC1PRES_DIV16
484#define LL_RCC_ADC1_CLKSRC_PLL_DIV_32 RCC_CFGR2_ADC1PRES_DIV32
485#define LL_RCC_ADC1_CLKSRC_PLL_DIV_64 RCC_CFGR2_ADC1PRES_DIV64
486#define LL_RCC_ADC1_CLKSRC_PLL_DIV_128 RCC_CFGR2_ADC1PRES_DIV128
487#define LL_RCC_ADC1_CLKSRC_PLL_DIV_256 RCC_CFGR2_ADC1PRES_DIV256
492#elif defined(RCC_CFGR2_ADCPRE12) || defined(RCC_CFGR2_ADCPRE34)
493#if defined(RCC_CFGR2_ADCPRE12) && defined(RCC_CFGR2_ADCPRE34)
497#define LL_RCC_ADC12_CLKSRC_HCLK (uint32_t)((RCC_CFGR2_ADCPRE12 << 16U) | RCC_CFGR2_ADCPRE12_NO)
498#define LL_RCC_ADC12_CLKSRC_PLL_DIV_1 (uint32_t)((RCC_CFGR2_ADCPRE12 << 16U) | RCC_CFGR2_ADCPRE12_DIV1)
499#define LL_RCC_ADC12_CLKSRC_PLL_DIV_2 (uint32_t)((RCC_CFGR2_ADCPRE12 << 16U) | RCC_CFGR2_ADCPRE12_DIV2)
500#define LL_RCC_ADC12_CLKSRC_PLL_DIV_4 (uint32_t)((RCC_CFGR2_ADCPRE12 << 16U) | RCC_CFGR2_ADCPRE12_DIV4)
501#define LL_RCC_ADC12_CLKSRC_PLL_DIV_6 (uint32_t)((RCC_CFGR2_ADCPRE12 << 16U) | RCC_CFGR2_ADCPRE12_DIV6)
502#define LL_RCC_ADC12_CLKSRC_PLL_DIV_8 (uint32_t)((RCC_CFGR2_ADCPRE12 << 16U) | RCC_CFGR2_ADCPRE12_DIV8)
503#define LL_RCC_ADC12_CLKSRC_PLL_DIV_10 (uint32_t)((RCC_CFGR2_ADCPRE12 << 16U) | RCC_CFGR2_ADCPRE12_DIV10)
504#define LL_RCC_ADC12_CLKSRC_PLL_DIV_12 (uint32_t)((RCC_CFGR2_ADCPRE12 << 16U) | RCC_CFGR2_ADCPRE12_DIV12)
505#define LL_RCC_ADC12_CLKSRC_PLL_DIV_16 (uint32_t)((RCC_CFGR2_ADCPRE12 << 16U) | RCC_CFGR2_ADCPRE12_DIV16)
506#define LL_RCC_ADC12_CLKSRC_PLL_DIV_32 (uint32_t)((RCC_CFGR2_ADCPRE12 << 16U) | RCC_CFGR2_ADCPRE12_DIV32)
507#define LL_RCC_ADC12_CLKSRC_PLL_DIV_64 (uint32_t)((RCC_CFGR2_ADCPRE12 << 16U) | RCC_CFGR2_ADCPRE12_DIV64)
508#define LL_RCC_ADC12_CLKSRC_PLL_DIV_128 (uint32_t)((RCC_CFGR2_ADCPRE12 << 16U) | RCC_CFGR2_ADCPRE12_DIV128)
509#define LL_RCC_ADC12_CLKSRC_PLL_DIV_256 (uint32_t)((RCC_CFGR2_ADCPRE12 << 16U) | RCC_CFGR2_ADCPRE12_DIV256)
517#define LL_RCC_ADC34_CLKSRC_HCLK (uint32_t)((RCC_CFGR2_ADCPRE34 << 16U) | RCC_CFGR2_ADCPRE34_NO)
518#define LL_RCC_ADC34_CLKSRC_PLL_DIV_1 (uint32_t)((RCC_CFGR2_ADCPRE34 << 16U) | RCC_CFGR2_ADCPRE34_DIV1)
519#define LL_RCC_ADC34_CLKSRC_PLL_DIV_2 (uint32_t)((RCC_CFGR2_ADCPRE34 << 16U) | RCC_CFGR2_ADCPRE34_DIV2)
520#define LL_RCC_ADC34_CLKSRC_PLL_DIV_4 (uint32_t)((RCC_CFGR2_ADCPRE34 << 16U) | RCC_CFGR2_ADCPRE34_DIV4)
521#define LL_RCC_ADC34_CLKSRC_PLL_DIV_6 (uint32_t)((RCC_CFGR2_ADCPRE34 << 16U) | RCC_CFGR2_ADCPRE34_DIV6)
522#define LL_RCC_ADC34_CLKSRC_PLL_DIV_8 (uint32_t)((RCC_CFGR2_ADCPRE34 << 16U) | RCC_CFGR2_ADCPRE34_DIV8)
523#define LL_RCC_ADC34_CLKSRC_PLL_DIV_10 (uint32_t)((RCC_CFGR2_ADCPRE34 << 16U) | RCC_CFGR2_ADCPRE34_DIV10)
524#define LL_RCC_ADC34_CLKSRC_PLL_DIV_12 (uint32_t)((RCC_CFGR2_ADCPRE34 << 16U) | RCC_CFGR2_ADCPRE34_DIV12)
525#define LL_RCC_ADC34_CLKSRC_PLL_DIV_16 (uint32_t)((RCC_CFGR2_ADCPRE34 << 16U) | RCC_CFGR2_ADCPRE34_DIV16)
526#define LL_RCC_ADC34_CLKSRC_PLL_DIV_32 (uint32_t)((RCC_CFGR2_ADCPRE34 << 16U) | RCC_CFGR2_ADCPRE34_DIV32)
527#define LL_RCC_ADC34_CLKSRC_PLL_DIV_64 (uint32_t)((RCC_CFGR2_ADCPRE34 << 16U) | RCC_CFGR2_ADCPRE34_DIV64)
528#define LL_RCC_ADC34_CLKSRC_PLL_DIV_128 (uint32_t)((RCC_CFGR2_ADCPRE34 << 16U) | RCC_CFGR2_ADCPRE34_DIV128)
529#define LL_RCC_ADC34_CLKSRC_PLL_DIV_256 (uint32_t)((RCC_CFGR2_ADCPRE34 << 16U) | RCC_CFGR2_ADCPRE34_DIV256)
538#define LL_RCC_ADC12_CLKSRC_HCLK RCC_CFGR2_ADCPRE12_NO
539#define LL_RCC_ADC12_CLKSRC_PLL_DIV_1 RCC_CFGR2_ADCPRE12_DIV1
540#define LL_RCC_ADC12_CLKSRC_PLL_DIV_2 RCC_CFGR2_ADCPRE12_DIV2
541#define LL_RCC_ADC12_CLKSRC_PLL_DIV_4 RCC_CFGR2_ADCPRE12_DIV4
542#define LL_RCC_ADC12_CLKSRC_PLL_DIV_6 RCC_CFGR2_ADCPRE12_DIV6
543#define LL_RCC_ADC12_CLKSRC_PLL_DIV_8 RCC_CFGR2_ADCPRE12_DIV8
544#define LL_RCC_ADC12_CLKSRC_PLL_DIV_10 RCC_CFGR2_ADCPRE12_DIV10
545#define LL_RCC_ADC12_CLKSRC_PLL_DIV_12 RCC_CFGR2_ADCPRE12_DIV12
546#define LL_RCC_ADC12_CLKSRC_PLL_DIV_16 RCC_CFGR2_ADCPRE12_DIV16
547#define LL_RCC_ADC12_CLKSRC_PLL_DIV_32 RCC_CFGR2_ADCPRE12_DIV32
548#define LL_RCC_ADC12_CLKSRC_PLL_DIV_64 RCC_CFGR2_ADCPRE12_DIV64
549#define LL_RCC_ADC12_CLKSRC_PLL_DIV_128 RCC_CFGR2_ADCPRE12_DIV128
550#define LL_RCC_ADC12_CLKSRC_PLL_DIV_256 RCC_CFGR2_ADCPRE12_DIV256
559#if defined(RCC_CFGR_SDPRE)
563#define LL_RCC_SDADC_CLKSRC_SYS_DIV_1 RCC_CFGR_SDPRE_DIV1
564#define LL_RCC_SDADC_CLKSRC_SYS_DIV_2 RCC_CFGR_SDPRE_DIV2
565#define LL_RCC_SDADC_CLKSRC_SYS_DIV_4 RCC_CFGR_SDPRE_DIV4
566#define LL_RCC_SDADC_CLKSRC_SYS_DIV_6 RCC_CFGR_SDPRE_DIV6
567#define LL_RCC_SDADC_CLKSRC_SYS_DIV_8 RCC_CFGR_SDPRE_DIV8
568#define LL_RCC_SDADC_CLKSRC_SYS_DIV_10 RCC_CFGR_SDPRE_DIV10
569#define LL_RCC_SDADC_CLKSRC_SYS_DIV_12 RCC_CFGR_SDPRE_DIV12
570#define LL_RCC_SDADC_CLKSRC_SYS_DIV_14 RCC_CFGR_SDPRE_DIV14
571#define LL_RCC_SDADC_CLKSRC_SYS_DIV_16 RCC_CFGR_SDPRE_DIV16
572#define LL_RCC_SDADC_CLKSRC_SYS_DIV_20 RCC_CFGR_SDPRE_DIV20
573#define LL_RCC_SDADC_CLKSRC_SYS_DIV_24 RCC_CFGR_SDPRE_DIV24
574#define LL_RCC_SDADC_CLKSRC_SYS_DIV_28 RCC_CFGR_SDPRE_DIV28
575#define LL_RCC_SDADC_CLKSRC_SYS_DIV_32 RCC_CFGR_SDPRE_DIV32
576#define LL_RCC_SDADC_CLKSRC_SYS_DIV_36 RCC_CFGR_SDPRE_DIV36
577#define LL_RCC_SDADC_CLKSRC_SYS_DIV_40 RCC_CFGR_SDPRE_DIV40
578#define LL_RCC_SDADC_CLKSRC_SYS_DIV_44 RCC_CFGR_SDPRE_DIV44
579#define LL_RCC_SDADC_CLKSRC_SYS_DIV_48 RCC_CFGR_SDPRE_DIV48
589#define LL_RCC_USART1_CLKSOURCE RCC_POSITION_USART1SW
590#if defined(RCC_CFGR3_USART2SW)
591#define LL_RCC_USART2_CLKSOURCE RCC_POSITION_USART2SW
593#if defined(RCC_CFGR3_USART3SW)
594#define LL_RCC_USART3_CLKSOURCE RCC_POSITION_USART3SW
600#if defined(RCC_CFGR3_UART4SW) || defined(RCC_CFGR3_UART5SW)
604#define LL_RCC_UART4_CLKSOURCE RCC_CFGR3_UART4SW
605#define LL_RCC_UART5_CLKSOURCE RCC_CFGR3_UART5SW
615#define LL_RCC_I2C1_CLKSOURCE RCC_CFGR3_I2C1SW
616#if defined(RCC_CFGR3_I2C2SW)
617#define LL_RCC_I2C2_CLKSOURCE RCC_CFGR3_I2C2SW
619#if defined(RCC_CFGR3_I2C3SW)
620#define LL_RCC_I2C3_CLKSOURCE RCC_CFGR3_I2C3SW
626#if defined(RCC_CFGR_I2SSRC)
630#define LL_RCC_I2S_CLKSOURCE RCC_CFGR_I2SSRC
637#if defined(RCC_CFGR3_TIMSW)
641#define LL_RCC_TIM1_CLKSOURCE (RCC_POSITION_TIM1SW - RCC_POSITION_TIM1SW)
642#if defined(RCC_CFGR3_TIM2SW)
643#define LL_RCC_TIM2_CLKSOURCE (RCC_POSITION_TIM2SW - RCC_POSITION_TIM1SW)
645#if defined(RCC_CFGR3_TIM8SW)
646#define LL_RCC_TIM8_CLKSOURCE (RCC_POSITION_TIM8SW - RCC_POSITION_TIM1SW)
648#if defined(RCC_CFGR3_TIM15SW)
649#define LL_RCC_TIM15_CLKSOURCE (RCC_POSITION_TIM15SW - RCC_POSITION_TIM1SW)
651#if defined(RCC_CFGR3_TIM16SW)
652#define LL_RCC_TIM16_CLKSOURCE (RCC_POSITION_TIM16SW - RCC_POSITION_TIM1SW)
654#if defined(RCC_CFGR3_TIM17SW)
655#define LL_RCC_TIM17_CLKSOURCE (RCC_POSITION_TIM17SW - RCC_POSITION_TIM1SW)
657#if defined(RCC_CFGR3_TIM20SW)
658#define LL_RCC_TIM20_CLKSOURCE (RCC_POSITION_TIM20SW - RCC_POSITION_TIM1SW)
660#if defined(RCC_CFGR3_TIM34SW)
661#define LL_RCC_TIM34_CLKSOURCE (RCC_POSITION_TIM34SW - RCC_POSITION_TIM1SW)
673#define LL_RCC_HRTIM1_CLKSOURCE RCC_CFGR3_HRTIM1SW
684#define LL_RCC_CEC_CLKSOURCE RCC_CFGR3_CECSW
695#define LL_RCC_USB_CLKSOURCE RCC_CFGR_USBPRE
702#if defined(RCC_CFGR_ADCPRE)
706#define LL_RCC_ADC_CLKSOURCE RCC_CFGR_ADCPRE
713#if defined(RCC_CFGR2_ADC1PRES) || defined(RCC_CFGR2_ADCPRE12) || defined(RCC_CFGR2_ADCPRE34)
717#if defined(RCC_CFGR2_ADC1PRES)
718#define LL_RCC_ADC1_CLKSOURCE RCC_CFGR2_ADC1PRES
720#define LL_RCC_ADC12_CLKSOURCE RCC_CFGR2_ADCPRE12
721#if defined(RCC_CFGR2_ADCPRE34)
722#define LL_RCC_ADC34_CLKSOURCE RCC_CFGR2_ADCPRE34
731#if defined(RCC_CFGR_SDPRE)
735#define LL_RCC_SDADC_CLKSOURCE RCC_CFGR_SDPRE
746#define LL_RCC_RTC_CLKSOURCE_NONE 0x00000000U
747#define LL_RCC_RTC_CLKSOURCE_LSE RCC_BDCR_RTCSEL_0
748#define LL_RCC_RTC_CLKSOURCE_LSI RCC_BDCR_RTCSEL_1
749#define LL_RCC_RTC_CLKSOURCE_HSE_DIV32 RCC_BDCR_RTCSEL
757#define LL_RCC_PLL_MUL_2 RCC_CFGR_PLLMUL2
758#define LL_RCC_PLL_MUL_3 RCC_CFGR_PLLMUL3
759#define LL_RCC_PLL_MUL_4 RCC_CFGR_PLLMUL4
760#define LL_RCC_PLL_MUL_5 RCC_CFGR_PLLMUL5
761#define LL_RCC_PLL_MUL_6 RCC_CFGR_PLLMUL6
762#define LL_RCC_PLL_MUL_7 RCC_CFGR_PLLMUL7
763#define LL_RCC_PLL_MUL_8 RCC_CFGR_PLLMUL8
764#define LL_RCC_PLL_MUL_9 RCC_CFGR_PLLMUL9
765#define LL_RCC_PLL_MUL_10 RCC_CFGR_PLLMUL10
766#define LL_RCC_PLL_MUL_11 RCC_CFGR_PLLMUL11
767#define LL_RCC_PLL_MUL_12 RCC_CFGR_PLLMUL12
768#define LL_RCC_PLL_MUL_13 RCC_CFGR_PLLMUL13
769#define LL_RCC_PLL_MUL_14 RCC_CFGR_PLLMUL14
770#define LL_RCC_PLL_MUL_15 RCC_CFGR_PLLMUL15
771#define LL_RCC_PLL_MUL_16 RCC_CFGR_PLLMUL16
779#define LL_RCC_PLLSOURCE_NONE 0x00000000U
780#define LL_RCC_PLLSOURCE_HSE RCC_CFGR_PLLSRC_HSE_PREDIV
781#if defined(RCC_PLLSRC_PREDIV1_SUPPORT)
782#define LL_RCC_PLLSOURCE_HSI RCC_CFGR_PLLSRC_HSI_PREDIV
784#define LL_RCC_PLLSOURCE_HSI_DIV_2 RCC_CFGR_PLLSRC_HSI_DIV2
785#define LL_RCC_PLLSOURCE_HSE_DIV_1 (RCC_CFGR_PLLSRC_HSE_PREDIV | RCC_CFGR2_PREDIV_DIV1)
786#define LL_RCC_PLLSOURCE_HSE_DIV_2 (RCC_CFGR_PLLSRC_HSE_PREDIV | RCC_CFGR2_PREDIV_DIV2)
787#define LL_RCC_PLLSOURCE_HSE_DIV_3 (RCC_CFGR_PLLSRC_HSE_PREDIV | RCC_CFGR2_PREDIV_DIV3)
788#define LL_RCC_PLLSOURCE_HSE_DIV_4 (RCC_CFGR_PLLSRC_HSE_PREDIV | RCC_CFGR2_PREDIV_DIV4)
789#define LL_RCC_PLLSOURCE_HSE_DIV_5 (RCC_CFGR_PLLSRC_HSE_PREDIV | RCC_CFGR2_PREDIV_DIV5)
790#define LL_RCC_PLLSOURCE_HSE_DIV_6 (RCC_CFGR_PLLSRC_HSE_PREDIV | RCC_CFGR2_PREDIV_DIV6)
791#define LL_RCC_PLLSOURCE_HSE_DIV_7 (RCC_CFGR_PLLSRC_HSE_PREDIV | RCC_CFGR2_PREDIV_DIV7)
792#define LL_RCC_PLLSOURCE_HSE_DIV_8 (RCC_CFGR_PLLSRC_HSE_PREDIV | RCC_CFGR2_PREDIV_DIV8)
793#define LL_RCC_PLLSOURCE_HSE_DIV_9 (RCC_CFGR_PLLSRC_HSE_PREDIV | RCC_CFGR2_PREDIV_DIV9)
794#define LL_RCC_PLLSOURCE_HSE_DIV_10 (RCC_CFGR_PLLSRC_HSE_PREDIV | RCC_CFGR2_PREDIV_DIV10)
795#define LL_RCC_PLLSOURCE_HSE_DIV_11 (RCC_CFGR_PLLSRC_HSE_PREDIV | RCC_CFGR2_PREDIV_DIV11)
796#define LL_RCC_PLLSOURCE_HSE_DIV_12 (RCC_CFGR_PLLSRC_HSE_PREDIV | RCC_CFGR2_PREDIV_DIV12)
797#define LL_RCC_PLLSOURCE_HSE_DIV_13 (RCC_CFGR_PLLSRC_HSE_PREDIV | RCC_CFGR2_PREDIV_DIV13)
798#define LL_RCC_PLLSOURCE_HSE_DIV_14 (RCC_CFGR_PLLSRC_HSE_PREDIV | RCC_CFGR2_PREDIV_DIV14)
799#define LL_RCC_PLLSOURCE_HSE_DIV_15 (RCC_CFGR_PLLSRC_HSE_PREDIV | RCC_CFGR2_PREDIV_DIV15)
800#define LL_RCC_PLLSOURCE_HSE_DIV_16 (RCC_CFGR_PLLSRC_HSE_PREDIV | RCC_CFGR2_PREDIV_DIV16)
809#define LL_RCC_PREDIV_DIV_1 RCC_CFGR2_PREDIV_DIV1
810#define LL_RCC_PREDIV_DIV_2 RCC_CFGR2_PREDIV_DIV2
811#define LL_RCC_PREDIV_DIV_3 RCC_CFGR2_PREDIV_DIV3
812#define LL_RCC_PREDIV_DIV_4 RCC_CFGR2_PREDIV_DIV4
813#define LL_RCC_PREDIV_DIV_5 RCC_CFGR2_PREDIV_DIV5
814#define LL_RCC_PREDIV_DIV_6 RCC_CFGR2_PREDIV_DIV6
815#define LL_RCC_PREDIV_DIV_7 RCC_CFGR2_PREDIV_DIV7
816#define LL_RCC_PREDIV_DIV_8 RCC_CFGR2_PREDIV_DIV8
817#define LL_RCC_PREDIV_DIV_9 RCC_CFGR2_PREDIV_DIV9
818#define LL_RCC_PREDIV_DIV_10 RCC_CFGR2_PREDIV_DIV10
819#define LL_RCC_PREDIV_DIV_11 RCC_CFGR2_PREDIV_DIV11
820#define LL_RCC_PREDIV_DIV_12 RCC_CFGR2_PREDIV_DIV12
821#define LL_RCC_PREDIV_DIV_13 RCC_CFGR2_PREDIV_DIV13
822#define LL_RCC_PREDIV_DIV_14 RCC_CFGR2_PREDIV_DIV14
823#define LL_RCC_PREDIV_DIV_15 RCC_CFGR2_PREDIV_DIV15
824#define LL_RCC_PREDIV_DIV_16 RCC_CFGR2_PREDIV_DIV16
848#define LL_RCC_WriteReg(__REG__, __VALUE__) WRITE_REG(RCC->__REG__, (__VALUE__))
855#define LL_RCC_ReadReg(__REG__) READ_REG(RCC->__REG__)
864#if defined(RCC_PLLSRC_PREDIV1_SUPPORT)
905#define __LL_RCC_CALC_PLLCLK_FREQ(__INPUTFREQ__, __PLLMUL__, __PLLPREDIV__) \
906 (((__INPUTFREQ__) / ((((__PLLPREDIV__) & RCC_CFGR2_PREDIV) + 1U))) * ((((__PLLMUL__) & RCC_CFGR_PLLMUL) >> RCC_POSITION_PLLMUL) + 2U))
931#define __LL_RCC_CALC_PLLCLK_FREQ(__INPUTFREQ__, __PLLMUL__) \
932 ((__INPUTFREQ__) * ((((__PLLMUL__) & RCC_CFGR_PLLMUL) >> RCC_POSITION_PLLMUL) + 2U))
951#define __LL_RCC_CALC_HCLK_FREQ(__SYSCLKFREQ__, __AHBPRESCALER__) ((__SYSCLKFREQ__) >> AHBPrescTable[((__AHBPRESCALER__) & RCC_CFGR_HPRE) >> RCC_CFGR_HPRE_Pos])
966#define __LL_RCC_CALC_PCLK1_FREQ(__HCLKFREQ__, __APB1PRESCALER__) ((__HCLKFREQ__) >> APBPrescTable[(__APB1PRESCALER__) >> RCC_CFGR_PPRE1_Pos])
981#define __LL_RCC_CALC_PCLK2_FREQ(__HCLKFREQ__, __APB2PRESCALER__) ((__HCLKFREQ__) >> APBPrescTable[(__APB2PRESCALER__) >> RCC_CFGR_PPRE2_Pos])
1444__STATIC_INLINE void LL_RCC_ConfigMCO(uint32_t MCOxSource, uint32_t MCOxPrescaler)
1446#if defined(RCC_CFGR_MCOPRE)
1447#if defined(RCC_CFGR_PLLNODIV)
1493#if defined(RCC_CFGR3_UART4SW) || defined(RCC_CFGR3_UART5SW)
1533 MODIFY_REG(
RCC->CFGR3, ((I2CxSource & 0xFF000000U) >> 24U), (I2CxSource & 0x00FFFFFFU));
1536#if defined(RCC_CFGR_I2SSRC)
1551#if defined(RCC_CFGR3_TIMSW)
1634#if defined(RCC_CFGR_ADCPRE)
1650#elif defined(RCC_CFGR2_ADC1PRES)
1675#elif defined(RCC_CFGR2_ADCPRE12) || defined(RCC_CFGR2_ADCPRE34)
1713#if defined(RCC_CFGR2_ADCPRE34)
1714 MODIFY_REG(
RCC->CFGR2, (ADCxSource >> 16U), (ADCxSource & 0x0000FFFFU));
1721#if defined(RCC_CFGR_SDPRE)
1784#if defined(RCC_CFGR3_UART4SW) || defined(RCC_CFGR3_UART5SW)
1804 return (uint32_t)(
READ_BIT(
RCC->CFGR3, UARTx) | (UARTx >> 8U));
1831 return (uint32_t)(
READ_BIT(
RCC->CFGR3, I2Cx) | (I2Cx << 24U));
1834#if defined(RCC_CFGR_I2SSRC)
1850#if defined(RCC_CFGR3_TIMSW)
1946#if defined(RCC_CFGR_ADCPRE)
1963#elif defined(RCC_CFGR2_ADC1PRES)
1989#elif defined(RCC_CFGR2_ADCPRE12) || defined(RCC_CFGR2_ADCPRE34)
2031#if defined(RCC_CFGR2_ADCPRE34)
2032 return (uint32_t)(
READ_BIT(
RCC->CFGR2, ADCx) | (ADCx << 16U));
2039#if defined(RCC_CFGR_SDPRE)
2198#if defined(RCC_PLLSRC_PREDIV1_SUPPORT)
2242__STATIC_INLINE void LL_RCC_PLL_ConfigDomain_SYS(uint32_t Source, uint32_t PLLMul, uint32_t PLLDiv)
2291__STATIC_INLINE void LL_RCC_PLL_ConfigDomain_SYS(uint32_t Source, uint32_t PLLMul)
2492#if defined(RCC_CFGR_MCOF)
2500 return (
READ_BIT(
RCC->CFGR, RCC_CFGR_MCOF) == (RCC_CFGR_MCOF));
2594#if defined(RCC_CSR_V18PWRRSTF)
2778#if defined(USE_FULL_LL_DRIVER)
2790void LL_RCC_GetSystemClocksFreq(LL_RCC_ClocksTypeDef *RCC_Clocks);
2791uint32_t LL_RCC_GetUSARTClockFreq(uint32_t USARTxSource);
2792#if defined(UART4) || defined(UART5)
2793uint32_t LL_RCC_GetUARTClockFreq(uint32_t UARTxSource);
2795uint32_t LL_RCC_GetI2CClockFreq(uint32_t I2CxSource);
2796#if defined(RCC_CFGR_I2SSRC)
2797uint32_t LL_RCC_GetI2SClockFreq(uint32_t I2SxSource);
2799#if defined(USB_OTG_FS) || defined(USB)
2800uint32_t LL_RCC_GetUSBClockFreq(uint32_t USBxSource);
2802#if (defined(RCC_CFGR_ADCPRE) || defined(RCC_CFGR2_ADC1PRES) || defined(RCC_CFGR2_ADCPRE12) || defined(RCC_CFGR2_ADCPRE34))
2803uint32_t LL_RCC_GetADCClockFreq(uint32_t ADCxSource);
2805#if defined(RCC_CFGR_SDPRE)
2806uint32_t LL_RCC_GetSDADCClockFreq(uint32_t SDADCxSource);
2809uint32_t LL_RCC_GetCECClockFreq(uint32_t CECxSource);
2811#if defined(RCC_CFGR3_TIMSW)
2812uint32_t LL_RCC_GetTIMClockFreq(uint32_t TIMxSource);
2814uint32_t LL_RCC_GetHRTIMClockFreq(uint32_t HRTIMxSource);
#define __STATIC_INLINE
Definition: cmsis_armcc.h:59
#define CLEAR_BIT(REG, BIT)
Definition: stm32f3xx.h:192
#define SET_BIT(REG, BIT)
Definition: stm32f3xx.h:190
#define MODIFY_REG(REG, CLEARMASK, SETMASK)
Definition: stm32f3xx.h:202
#define READ_BIT(REG, BIT)
Definition: stm32f3xx.h:194
ErrorStatus
Definition: stm32f3xx.h:177
#define RCC_BDCR_LSEON
Definition: stm32f303xe.h:11220
#define RCC_CFGR2_PREDIV
Definition: stm32f303xe.h:11333
#define RCC_CFGR2_ADCPRE12
Definition: stm32f303xe.h:11359
#define RCC_CFGR_SW
Definition: stm32f303xe.h:10758
#define RCC_CIR_PLLRDYF
Definition: stm32f303xe.h:10941
#define RCC_CIR_HSERDYF
Definition: stm32f303xe.h:10938
#define RCC_CSR_OBLRSTF
Definition: stm32f303xe.h:11268
#define RCC_CIR_LSERDYC
Definition: stm32f303xe.h:10965
#define RCC_CFGR_SWS
Definition: stm32f303xe.h:10769
#define RCC_CSR_SFTRSTF
Definition: stm32f303xe.h:11277
#define RCC_CIR_PLLRDYIE
Definition: stm32f303xe.h:10959
#define RCC_CR_HSITRIM_Pos
Definition: stm32f303xe.h:10714
#define RCC_CSR_IWDGRSTF
Definition: stm32f303xe.h:11280
#define RCC_CIR_PLLRDYC
Definition: stm32f303xe.h:10974
#define RCC_CSR_V18PWRRSTF
Definition: stm32f303xe.h:11262
#define RCC_BDCR_BDRST
Definition: stm32f303xe.h:11251
#define RCC_CFGR_MCOPRE
Definition: stm32f303xe.h:10895
#define RCC_CIR_CSSC
Definition: stm32f303xe.h:10977
#define RCC_CSR_PINRSTF
Definition: stm32f303xe.h:11271
#define RCC_CFGR_PPRE1
Definition: stm32f303xe.h:10799
#define RCC_CFGR_PLLMUL
Definition: stm32f303xe.h:10839
#define RCC_BDCR_LSEBYP
Definition: stm32f303xe.h:11226
#define RCC_CIR_HSERDYIE
Definition: stm32f303xe.h:10956
#define RCC_CFGR3_TIM1SW
Definition: stm32f303xe.h:11449
#define RCC_CFGR3_UART5SW
Definition: stm32f303xe.h:11531
#define RCC_CR_HSITRIM
Definition: stm32f303xe.h:10716
#define RCC_CFGR_I2SSRC
Definition: stm32f303xe.h:10872
#define RCC_CSR_LPWRRSTF
Definition: stm32f303xe.h:11286
#define RCC_CR_HSICAL
Definition: stm32f303xe.h:10725
#define RCC_CIR_LSERDYIE
Definition: stm32f303xe.h:10950
#define RCC_CFGR_MCOSEL
Definition: stm32f303xe.h:10914
#define RCC_BDCR_RTCEN
Definition: stm32f303xe.h:11248
#define RCC_CSR_LSION
Definition: stm32f303xe.h:11256
#define RCC_CSR_PORRSTF
Definition: stm32f303xe.h:11274
#define RCC_CR_HSERDY
Definition: stm32f303xe.h:10740
#define RCC_CIR_LSIRDYIE
Definition: stm32f303xe.h:10947
#define RCC_CIR_HSERDYC
Definition: stm32f303xe.h:10971
#define RCC_CIR_LSIRDYC
Definition: stm32f303xe.h:10962
#define RCC_CR_HSIRDY
Definition: stm32f303xe.h:10712
#define RCC_CR_HSEBYP
Definition: stm32f303xe.h:10743
#define RCC_BDCR_LSEDRV
Definition: stm32f303xe.h:11230
#define RCC_CR_HSICAL_Pos
Definition: stm32f303xe.h:10723
#define RCC_BDCR_LSERDY
Definition: stm32f303xe.h:11223
#define RCC_CSR_LSIRDY
Definition: stm32f303xe.h:11259
#define RCC_CFGR3_USART1SW
Definition: stm32f303xe.h:11407
#define RCC_CFGR_PLLSRC
Definition: stm32f303xe.h:10826
#define RCC_BDCR_RTCSEL
Definition: stm32f303xe.h:11236
#define RCC_CIR_LSERDYF
Definition: stm32f303xe.h:10932
#define RCC_CIR_HSIRDYIE
Definition: stm32f303xe.h:10953
#define RCC_CFGR_PLLNODIV
Definition: stm32f303xe.h:10911
#define RCC_CSR_WWDGRSTF
Definition: stm32f303xe.h:11283
#define RCC_CIR_LSIRDYF
Definition: stm32f303xe.h:10929
#define RCC_CR_CSSON
Definition: stm32f303xe.h:10746
#define RCC_CR_PLLON
Definition: stm32f303xe.h:10749
#define RCC_CIR_HSIRDYC
Definition: stm32f303xe.h:10968
#define RCC_CIR_HSIRDYF
Definition: stm32f303xe.h:10935
#define RCC_CFGR_PPRE2
Definition: stm32f303xe.h:10813
#define RCC_CIR_CSSF
Definition: stm32f303xe.h:10944
#define RCC_CR_HSEON
Definition: stm32f303xe.h:10737
#define RCC_CFGR_USBPRE
Definition: stm32f303xe.h:10864
#define RCC_CR_HSION
Definition: stm32f303xe.h:10709
#define RCC_CR_PLLRDY
Definition: stm32f303xe.h:10752
#define RCC_CSR_RMVF
Definition: stm32f303xe.h:11265
#define RCC_CFGR_HPRE
Definition: stm32f303xe.h:10780
#define RCC_CFGR3_UART4SW
Definition: stm32f303xe.h:11520
#define RCC
Definition: stm32f303xe.h:977
CMSIS STM32F3xx Device Peripheral Access Layer Header File.