stm32f3xx_ll_rcc.h

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/* Define to prevent recursive inclusion -------------------------------------*/
#ifndef __STM32F3xx_LL_RCC_H
#define __STM32F3xx_LL_RCC_H
 
#ifdef __cplusplus
extern "C" {
#endif
 
/* Includes ------------------------------------------------------------------*/
#include "stm32f3xx.h"
 
#if defined(RCC)
 
/* Private types -------------------------------------------------------------*/
/* Private variables ---------------------------------------------------------*/
/* Private constants ---------------------------------------------------------*/
/* Defines used for the bit position in the register and perform offsets*/
#define RCC_POSITION_HPRE       (uint32_t)POSITION_VAL(RCC_CFGR_HPRE)     
#define RCC_POSITION_PPRE1      (uint32_t)POSITION_VAL(RCC_CFGR_PPRE1)    
#define RCC_POSITION_PPRE2      (uint32_t)POSITION_VAL(RCC_CFGR_PPRE2)    
#define RCC_POSITION_HSICAL     (uint32_t)POSITION_VAL(RCC_CR_HSICAL)     
#define RCC_POSITION_HSITRIM    (uint32_t)POSITION_VAL(RCC_CR_HSITRIM)    
#define RCC_POSITION_PLLMUL     (uint32_t)POSITION_VAL(RCC_CFGR_PLLMUL)   
#define RCC_POSITION_USART1SW   (uint32_t)0U                              
#define RCC_POSITION_USART2SW   (uint32_t)16U                             
#define RCC_POSITION_USART3SW   (uint32_t)18U                             
#define RCC_POSITION_TIM1SW     (uint32_t)8U                              
#define RCC_POSITION_TIM8SW     (uint32_t)9U                              
#define RCC_POSITION_TIM15SW    (uint32_t)10U                             
#define RCC_POSITION_TIM16SW    (uint32_t)11U                             
#define RCC_POSITION_TIM17SW    (uint32_t)13U                             
#define RCC_POSITION_TIM20SW    (uint32_t)15U                             
#define RCC_POSITION_TIM2SW     (uint32_t)24U                             
#define RCC_POSITION_TIM34SW    (uint32_t)25U                             
/* Private macros ------------------------------------------------------------*/
#if defined(USE_FULL_LL_DRIVER)
#endif /*USE_FULL_LL_DRIVER*/
/* Exported types ------------------------------------------------------------*/
#if defined(USE_FULL_LL_DRIVER)
typedef struct
{
  uint32_t SYSCLK_Frequency;        
  uint32_t HCLK_Frequency;          
  uint32_t PCLK1_Frequency;         
  uint32_t PCLK2_Frequency;         
} LL_RCC_ClocksTypeDef;
 
#endif /* USE_FULL_LL_DRIVER */
 
/* Exported constants --------------------------------------------------------*/
#if !defined  (HSE_VALUE)
#define HSE_VALUE    8000000U  
#endif /* HSE_VALUE */
 
#if !defined  (HSI_VALUE)
#define HSI_VALUE    8000000U  
#endif /* HSI_VALUE */
 
#if !defined  (LSE_VALUE)
#define LSE_VALUE    32768U    
#endif /* LSE_VALUE */
 
#if !defined  (LSI_VALUE)
#define LSI_VALUE    40000U    
#endif /* LSI_VALUE */
 
#if !defined  (EXTERNAL_CLOCK_VALUE)
#define EXTERNAL_CLOCK_VALUE    12288000U 
#endif /* EXTERNAL_CLOCK_VALUE */
#define LL_RCC_CIR_LSIRDYC                RCC_CIR_LSIRDYC     
#define LL_RCC_CIR_LSERDYC                RCC_CIR_LSERDYC     
#define LL_RCC_CIR_HSIRDYC                RCC_CIR_HSIRDYC     
#define LL_RCC_CIR_HSERDYC                RCC_CIR_HSERDYC     
#define LL_RCC_CIR_PLLRDYC                RCC_CIR_PLLRDYC     
#define LL_RCC_CIR_CSSC                   RCC_CIR_CSSC        
#define LL_RCC_CIR_LSIRDYF                RCC_CIR_LSIRDYF     
#define LL_RCC_CIR_LSERDYF                RCC_CIR_LSERDYF     
#define LL_RCC_CIR_HSIRDYF                RCC_CIR_HSIRDYF     
#define LL_RCC_CIR_HSERDYF                RCC_CIR_HSERDYF     
#define LL_RCC_CFGR_MCOF                  RCC_CFGR_MCOF     
#define LL_RCC_CIR_PLLRDYF                RCC_CIR_PLLRDYF     
#define LL_RCC_CIR_CSSF                   RCC_CIR_CSSF       
#define LL_RCC_CSR_OBLRSTF                RCC_CSR_OBLRSTF         
#define LL_RCC_CSR_PINRSTF                RCC_CSR_PINRSTF         
#define LL_RCC_CSR_PORRSTF                RCC_CSR_PORRSTF         
#define LL_RCC_CSR_SFTRSTF                RCC_CSR_SFTRSTF         
#define LL_RCC_CSR_IWDGRSTF               RCC_CSR_IWDGRSTF        
#define LL_RCC_CSR_WWDGRSTF               RCC_CSR_WWDGRSTF        
#define LL_RCC_CSR_LPWRRSTF               RCC_CSR_LPWRRSTF        
#if defined(RCC_CSR_V18PWRRSTF)
#define LL_RCC_CSR_V18PWRRSTF             RCC_CSR_V18PWRRSTF      
#endif /* RCC_CSR_V18PWRRSTF */
#define LL_RCC_CIR_LSIRDYIE               RCC_CIR_LSIRDYIE      
#define LL_RCC_CIR_LSERDYIE               RCC_CIR_LSERDYIE      
#define LL_RCC_CIR_HSIRDYIE               RCC_CIR_HSIRDYIE      
#define LL_RCC_CIR_HSERDYIE               RCC_CIR_HSERDYIE      
#define LL_RCC_CIR_PLLRDYIE               RCC_CIR_PLLRDYIE      
#define LL_RCC_LSEDRIVE_LOW                ((uint32_t)0x00000000U) 
#define LL_RCC_LSEDRIVE_MEDIUMLOW          RCC_BDCR_LSEDRV_1 
#define LL_RCC_LSEDRIVE_MEDIUMHIGH         RCC_BDCR_LSEDRV_0 
#define LL_RCC_LSEDRIVE_HIGH               RCC_BDCR_LSEDRV   
#define LL_RCC_SYS_CLKSOURCE_HSI           RCC_CFGR_SW_HSI    
#define LL_RCC_SYS_CLKSOURCE_HSE           RCC_CFGR_SW_HSE    
#define LL_RCC_SYS_CLKSOURCE_PLL           RCC_CFGR_SW_PLL    
#define LL_RCC_SYS_CLKSOURCE_STATUS_HSI    RCC_CFGR_SWS_HSI   
#define LL_RCC_SYS_CLKSOURCE_STATUS_HSE    RCC_CFGR_SWS_HSE   
#define LL_RCC_SYS_CLKSOURCE_STATUS_PLL    RCC_CFGR_SWS_PLL   
#define LL_RCC_SYSCLK_DIV_1                RCC_CFGR_HPRE_DIV1   
#define LL_RCC_SYSCLK_DIV_2                RCC_CFGR_HPRE_DIV2   
#define LL_RCC_SYSCLK_DIV_4                RCC_CFGR_HPRE_DIV4   
#define LL_RCC_SYSCLK_DIV_8                RCC_CFGR_HPRE_DIV8   
#define LL_RCC_SYSCLK_DIV_16               RCC_CFGR_HPRE_DIV16  
#define LL_RCC_SYSCLK_DIV_64               RCC_CFGR_HPRE_DIV64  
#define LL_RCC_SYSCLK_DIV_128              RCC_CFGR_HPRE_DIV128 
#define LL_RCC_SYSCLK_DIV_256              RCC_CFGR_HPRE_DIV256 
#define LL_RCC_SYSCLK_DIV_512              RCC_CFGR_HPRE_DIV512 
#define LL_RCC_APB1_DIV_1                  RCC_CFGR_PPRE1_DIV1  
#define LL_RCC_APB1_DIV_2                  RCC_CFGR_PPRE1_DIV2  
#define LL_RCC_APB1_DIV_4                  RCC_CFGR_PPRE1_DIV4  
#define LL_RCC_APB1_DIV_8                  RCC_CFGR_PPRE1_DIV8  
#define LL_RCC_APB1_DIV_16                 RCC_CFGR_PPRE1_DIV16 
#define LL_RCC_APB2_DIV_1                  RCC_CFGR_PPRE2_DIV1  
#define LL_RCC_APB2_DIV_2                  RCC_CFGR_PPRE2_DIV2  
#define LL_RCC_APB2_DIV_4                  RCC_CFGR_PPRE2_DIV4  
#define LL_RCC_APB2_DIV_8                  RCC_CFGR_PPRE2_DIV8  
#define LL_RCC_APB2_DIV_16                 RCC_CFGR_PPRE2_DIV16 
#define LL_RCC_MCO1SOURCE_NOCLOCK          RCC_CFGR_MCOSEL_NOCLOCK      
#define LL_RCC_MCO1SOURCE_SYSCLK           RCC_CFGR_MCOSEL_SYSCLK       
#define LL_RCC_MCO1SOURCE_HSI              RCC_CFGR_MCOSEL_HSI          
#define LL_RCC_MCO1SOURCE_HSE              RCC_CFGR_MCOSEL_HSE          
#define LL_RCC_MCO1SOURCE_LSI              RCC_CFGR_MCOSEL_LSI          
#define LL_RCC_MCO1SOURCE_LSE              RCC_CFGR_MCOSEL_LSE          
#define LL_RCC_MCO1SOURCE_PLLCLK_DIV_2     RCC_CFGR_MCOSEL_PLL_DIV2     
#if defined(RCC_CFGR_PLLNODIV)
#define LL_RCC_MCO1SOURCE_PLLCLK           (RCC_CFGR_MCOSEL_PLL_DIV2 | RCC_CFGR_PLLNODIV) 
#endif /* RCC_CFGR_PLLNODIV */
#define LL_RCC_MCO1_DIV_1                  ((uint32_t)0x00000000U)
#if defined(RCC_CFGR_MCOPRE)
#define LL_RCC_MCO1_DIV_2                  RCC_CFGR_MCOPRE_DIV2   
#define LL_RCC_MCO1_DIV_4                  RCC_CFGR_MCOPRE_DIV4   
#define LL_RCC_MCO1_DIV_8                  RCC_CFGR_MCOPRE_DIV8   
#define LL_RCC_MCO1_DIV_16                 RCC_CFGR_MCOPRE_DIV16  
#define LL_RCC_MCO1_DIV_32                 RCC_CFGR_MCOPRE_DIV32  
#define LL_RCC_MCO1_DIV_64                 RCC_CFGR_MCOPRE_DIV64  
#define LL_RCC_MCO1_DIV_128                RCC_CFGR_MCOPRE_DIV128 
#endif /* RCC_CFGR_MCOPRE */
#if defined(USE_FULL_LL_DRIVER)
#define LL_RCC_PERIPH_FREQUENCY_NO         0x00000000U      
#define LL_RCC_PERIPH_FREQUENCY_NA         0xFFFFFFFFU      
#endif /* USE_FULL_LL_DRIVER */
 
#if defined(RCC_CFGR3_USART1SW_PCLK1)
#define LL_RCC_USART1_CLKSOURCE_PCLK1    (uint32_t)((RCC_POSITION_USART1SW << 24U) | RCC_CFGR3_USART1SW_PCLK1)  
#else
#define LL_RCC_USART1_CLKSOURCE_PCLK2    (uint32_t)((RCC_POSITION_USART1SW << 24U) | RCC_CFGR3_USART1SW_PCLK2)  
#endif /*RCC_CFGR3_USART1SW_PCLK1*/
#define LL_RCC_USART1_CLKSOURCE_SYSCLK   (uint32_t)((RCC_POSITION_USART1SW << 24U) | RCC_CFGR3_USART1SW_SYSCLK) 
#define LL_RCC_USART1_CLKSOURCE_LSE      (uint32_t)((RCC_POSITION_USART1SW << 24U) | RCC_CFGR3_USART1SW_LSE)    
#define LL_RCC_USART1_CLKSOURCE_HSI      (uint32_t)((RCC_POSITION_USART1SW << 24U) | RCC_CFGR3_USART1SW_HSI)    
#if defined(RCC_CFGR3_USART2SW)
#define LL_RCC_USART2_CLKSOURCE_PCLK1    (uint32_t)((RCC_POSITION_USART2SW << 24U) | RCC_CFGR3_USART2SW_PCLK)   
#define LL_RCC_USART2_CLKSOURCE_SYSCLK   (uint32_t)((RCC_POSITION_USART2SW << 24U) | RCC_CFGR3_USART2SW_SYSCLK) 
#define LL_RCC_USART2_CLKSOURCE_LSE      (uint32_t)((RCC_POSITION_USART2SW << 24U) | RCC_CFGR3_USART2SW_LSE)    
#define LL_RCC_USART2_CLKSOURCE_HSI      (uint32_t)((RCC_POSITION_USART2SW << 24U) | RCC_CFGR3_USART2SW_HSI)    
#endif /* RCC_CFGR3_USART2SW */
#if defined(RCC_CFGR3_USART3SW)
#define LL_RCC_USART3_CLKSOURCE_PCLK1    (uint32_t)((RCC_POSITION_USART3SW << 24U) | RCC_CFGR3_USART3SW_PCLK)   
#define LL_RCC_USART3_CLKSOURCE_SYSCLK   (uint32_t)((RCC_POSITION_USART3SW << 24U) | RCC_CFGR3_USART3SW_SYSCLK) 
#define LL_RCC_USART3_CLKSOURCE_LSE      (uint32_t)((RCC_POSITION_USART3SW << 24U) | RCC_CFGR3_USART3SW_LSE)    
#define LL_RCC_USART3_CLKSOURCE_HSI      (uint32_t)((RCC_POSITION_USART3SW << 24U) | RCC_CFGR3_USART3SW_HSI)    
#endif /* RCC_CFGR3_USART3SW */
#if defined(RCC_CFGR3_UART4SW) || defined(RCC_CFGR3_UART5SW)
#define LL_RCC_UART4_CLKSOURCE_PCLK1     (uint32_t)((RCC_CFGR3_UART4SW >> 8U) | RCC_CFGR3_UART4SW_PCLK)   
#define LL_RCC_UART4_CLKSOURCE_SYSCLK    (uint32_t)((RCC_CFGR3_UART4SW >> 8U) | RCC_CFGR3_UART4SW_SYSCLK) 
#define LL_RCC_UART4_CLKSOURCE_LSE       (uint32_t)((RCC_CFGR3_UART4SW >> 8U) | RCC_CFGR3_UART4SW_LSE)    
#define LL_RCC_UART4_CLKSOURCE_HSI       (uint32_t)((RCC_CFGR3_UART4SW >> 8U) | RCC_CFGR3_UART4SW_HSI)    
#define LL_RCC_UART5_CLKSOURCE_PCLK1     (uint32_t)((RCC_CFGR3_UART5SW >> 8U) | RCC_CFGR3_UART5SW_PCLK)   
#define LL_RCC_UART5_CLKSOURCE_SYSCLK    (uint32_t)((RCC_CFGR3_UART5SW >> 8U) | RCC_CFGR3_UART5SW_SYSCLK) 
#define LL_RCC_UART5_CLKSOURCE_LSE       (uint32_t)((RCC_CFGR3_UART5SW >> 8U) | RCC_CFGR3_UART5SW_LSE)    
#define LL_RCC_UART5_CLKSOURCE_HSI       (uint32_t)((RCC_CFGR3_UART5SW >> 8U) | RCC_CFGR3_UART5SW_HSI)    
#endif /* RCC_CFGR3_UART4SW || RCC_CFGR3_UART5SW */
 
#define LL_RCC_I2C1_CLKSOURCE_HSI        (uint32_t)((RCC_CFGR3_I2C1SW << 24U) | RCC_CFGR3_I2C1SW_HSI)    
#define LL_RCC_I2C1_CLKSOURCE_SYSCLK     (uint32_t)((RCC_CFGR3_I2C1SW << 24U) | RCC_CFGR3_I2C1SW_SYSCLK) 
#if defined(RCC_CFGR3_I2C2SW)
#define LL_RCC_I2C2_CLKSOURCE_HSI        (uint32_t)((RCC_CFGR3_I2C2SW << 24U) | RCC_CFGR3_I2C2SW_HSI)    
#define LL_RCC_I2C2_CLKSOURCE_SYSCLK     (uint32_t)((RCC_CFGR3_I2C2SW << 24U) | RCC_CFGR3_I2C2SW_SYSCLK) 
#endif /*RCC_CFGR3_I2C2SW*/
#if defined(RCC_CFGR3_I2C3SW)
#define LL_RCC_I2C3_CLKSOURCE_HSI        (uint32_t)((RCC_CFGR3_I2C3SW << 24U) | RCC_CFGR3_I2C3SW_HSI)    
#define LL_RCC_I2C3_CLKSOURCE_SYSCLK     (uint32_t)((RCC_CFGR3_I2C3SW << 24U) | RCC_CFGR3_I2C3SW_SYSCLK) 
#endif /*RCC_CFGR3_I2C3SW*/
#if defined(RCC_CFGR_I2SSRC)
#define LL_RCC_I2S_CLKSOURCE_SYSCLK      RCC_CFGR_I2SSRC_SYSCLK 
#define LL_RCC_I2S_CLKSOURCE_PIN         RCC_CFGR_I2SSRC_EXT    
#endif /* RCC_CFGR_I2SSRC */
 
#if defined(RCC_CFGR3_TIMSW)
#define LL_RCC_TIM1_CLKSOURCE_PCLK2      (uint32_t)(((RCC_POSITION_TIM1SW - RCC_POSITION_TIM1SW) << 27U) | RCC_CFGR3_TIM1SW_PCLK2)   
#define LL_RCC_TIM1_CLKSOURCE_PLL        (uint32_t)(((RCC_POSITION_TIM1SW - RCC_POSITION_TIM1SW) << 27U) | RCC_CFGR3_TIM1SW_PLL)     
#if defined(RCC_CFGR3_TIM8SW)
#define LL_RCC_TIM8_CLKSOURCE_PCLK2      (uint32_t)(((RCC_POSITION_TIM8SW - RCC_POSITION_TIM1SW) << 27U) | RCC_CFGR3_TIM8SW_PCLK2)   
#define LL_RCC_TIM8_CLKSOURCE_PLL        (uint32_t)(((RCC_POSITION_TIM8SW - RCC_POSITION_TIM1SW) << 27U) | RCC_CFGR3_TIM8SW_PLL)     
#endif /*RCC_CFGR3_TIM8SW*/
#if defined(RCC_CFGR3_TIM15SW)
#define LL_RCC_TIM15_CLKSOURCE_PCLK2     (uint32_t)(((RCC_POSITION_TIM15SW - RCC_POSITION_TIM1SW) << 27U) | RCC_CFGR3_TIM15SW_PCLK2) 
#define LL_RCC_TIM15_CLKSOURCE_PLL       (uint32_t)(((RCC_POSITION_TIM15SW - RCC_POSITION_TIM1SW) << 27U) | RCC_CFGR3_TIM15SW_PLL)   
#endif /*RCC_CFGR3_TIM15SW*/
#if defined(RCC_CFGR3_TIM16SW)
#define LL_RCC_TIM16_CLKSOURCE_PCLK2     (uint32_t)(((RCC_POSITION_TIM16SW - RCC_POSITION_TIM1SW) << 27U) | RCC_CFGR3_TIM16SW_PCLK2) 
#define LL_RCC_TIM16_CLKSOURCE_PLL       (uint32_t)(((RCC_POSITION_TIM16SW - RCC_POSITION_TIM1SW) << 27U) | RCC_CFGR3_TIM16SW_PLL)   
#endif /*RCC_CFGR3_TIM16SW*/
#if defined(RCC_CFGR3_TIM17SW)
#define LL_RCC_TIM17_CLKSOURCE_PCLK2     (uint32_t)(((RCC_POSITION_TIM17SW - RCC_POSITION_TIM1SW) << 27U) | RCC_CFGR3_TIM17SW_PCLK2) 
#define LL_RCC_TIM17_CLKSOURCE_PLL       (uint32_t)(((RCC_POSITION_TIM17SW - RCC_POSITION_TIM1SW) << 27U) | RCC_CFGR3_TIM17SW_PLL)   
#endif /*RCC_CFGR3_TIM17SW*/
#if defined(RCC_CFGR3_TIM20SW)
#define LL_RCC_TIM20_CLKSOURCE_PCLK2     (uint32_t)(((RCC_POSITION_TIM20SW - RCC_POSITION_TIM1SW) << 27U) | RCC_CFGR3_TIM20SW_PCLK2) 
#define LL_RCC_TIM20_CLKSOURCE_PLL       (uint32_t)(((RCC_POSITION_TIM20SW - RCC_POSITION_TIM1SW) << 27U) | RCC_CFGR3_TIM20SW_PLL)   
#endif /*RCC_CFGR3_TIM20SW*/
#if defined(RCC_CFGR3_TIM2SW)
#define LL_RCC_TIM2_CLKSOURCE_PCLK1      (uint32_t)(((RCC_POSITION_TIM2SW - RCC_POSITION_TIM1SW) << 27U) | RCC_CFGR3_TIM2SW_PCLK1)   
#define LL_RCC_TIM2_CLKSOURCE_PLL        (uint32_t)(((RCC_POSITION_TIM2SW - RCC_POSITION_TIM1SW) << 27U) | RCC_CFGR3_TIM2SW_PLL)     
#endif /*RCC_CFGR3_TIM2SW*/
#if defined(RCC_CFGR3_TIM34SW)
#define LL_RCC_TIM34_CLKSOURCE_PCLK1     (uint32_t)(((RCC_POSITION_TIM34SW - RCC_POSITION_TIM1SW) << 27U) | RCC_CFGR3_TIM34SW_PCLK1) 
#define LL_RCC_TIM34_CLKSOURCE_PLL       (uint32_t)(((RCC_POSITION_TIM34SW - RCC_POSITION_TIM1SW) << 27U) | RCC_CFGR3_TIM34SW_PLL)   
#endif /*RCC_CFGR3_TIM34SW*/
#endif /* RCC_CFGR3_TIMSW */
 
#if defined(HRTIM1)
#define LL_RCC_HRTIM1_CLKSOURCE_PCLK2    RCC_CFGR3_HRTIM1SW_PCLK2 
#define LL_RCC_HRTIM1_CLKSOURCE_PLL      RCC_CFGR3_HRTIM1SW_PLL   
#endif /* HRTIM1 */
 
#if defined(CEC)
#define LL_RCC_CEC_CLKSOURCE_HSI_DIV244  RCC_CFGR3_CECSW_HSI_DIV244 
#define LL_RCC_CEC_CLKSOURCE_LSE         RCC_CFGR3_CECSW_LSE        
#endif /* CEC */
 
#if defined(USB)
#define LL_RCC_USB_CLKSOURCE_PLL         RCC_CFGR_USBPRE_DIV1    
#define LL_RCC_USB_CLKSOURCE_PLL_DIV_1_5 RCC_CFGR_USBPRE_DIV1_5  
#endif /* USB */
 
#if defined(RCC_CFGR_ADCPRE)
#define LL_RCC_ADC_CLKSRC_PCLK2_DIV_2    RCC_CFGR_ADCPRE_DIV2      
#define LL_RCC_ADC_CLKSRC_PCLK2_DIV_4    RCC_CFGR_ADCPRE_DIV4      
#define LL_RCC_ADC_CLKSRC_PCLK2_DIV_6    RCC_CFGR_ADCPRE_DIV6      
#define LL_RCC_ADC_CLKSRC_PCLK2_DIV_8    RCC_CFGR_ADCPRE_DIV8      
#elif defined(RCC_CFGR2_ADC1PRES)
#define LL_RCC_ADC1_CLKSRC_HCLK          RCC_CFGR2_ADC1PRES_NO     
#define LL_RCC_ADC1_CLKSRC_PLL_DIV_1     RCC_CFGR2_ADC1PRES_DIV1   
#define LL_RCC_ADC1_CLKSRC_PLL_DIV_2     RCC_CFGR2_ADC1PRES_DIV2   
#define LL_RCC_ADC1_CLKSRC_PLL_DIV_4     RCC_CFGR2_ADC1PRES_DIV4   
#define LL_RCC_ADC1_CLKSRC_PLL_DIV_6     RCC_CFGR2_ADC1PRES_DIV6   
#define LL_RCC_ADC1_CLKSRC_PLL_DIV_8     RCC_CFGR2_ADC1PRES_DIV8   
#define LL_RCC_ADC1_CLKSRC_PLL_DIV_10    RCC_CFGR2_ADC1PRES_DIV10  
#define LL_RCC_ADC1_CLKSRC_PLL_DIV_12    RCC_CFGR2_ADC1PRES_DIV12  
#define LL_RCC_ADC1_CLKSRC_PLL_DIV_16    RCC_CFGR2_ADC1PRES_DIV16  
#define LL_RCC_ADC1_CLKSRC_PLL_DIV_32    RCC_CFGR2_ADC1PRES_DIV32  
#define LL_RCC_ADC1_CLKSRC_PLL_DIV_64    RCC_CFGR2_ADC1PRES_DIV64  
#define LL_RCC_ADC1_CLKSRC_PLL_DIV_128   RCC_CFGR2_ADC1PRES_DIV128 
#define LL_RCC_ADC1_CLKSRC_PLL_DIV_256   RCC_CFGR2_ADC1PRES_DIV256 
#elif defined(RCC_CFGR2_ADCPRE12) || defined(RCC_CFGR2_ADCPRE34)
#if defined(RCC_CFGR2_ADCPRE12) && defined(RCC_CFGR2_ADCPRE34)
#define LL_RCC_ADC12_CLKSRC_HCLK         (uint32_t)((RCC_CFGR2_ADCPRE12 << 16U) | RCC_CFGR2_ADCPRE12_NO)     
#define LL_RCC_ADC12_CLKSRC_PLL_DIV_1    (uint32_t)((RCC_CFGR2_ADCPRE12 << 16U) | RCC_CFGR2_ADCPRE12_DIV1)   
#define LL_RCC_ADC12_CLKSRC_PLL_DIV_2    (uint32_t)((RCC_CFGR2_ADCPRE12 << 16U) | RCC_CFGR2_ADCPRE12_DIV2)   
#define LL_RCC_ADC12_CLKSRC_PLL_DIV_4    (uint32_t)((RCC_CFGR2_ADCPRE12 << 16U) | RCC_CFGR2_ADCPRE12_DIV4)   
#define LL_RCC_ADC12_CLKSRC_PLL_DIV_6    (uint32_t)((RCC_CFGR2_ADCPRE12 << 16U) | RCC_CFGR2_ADCPRE12_DIV6)   
#define LL_RCC_ADC12_CLKSRC_PLL_DIV_8    (uint32_t)((RCC_CFGR2_ADCPRE12 << 16U) | RCC_CFGR2_ADCPRE12_DIV8)   
#define LL_RCC_ADC12_CLKSRC_PLL_DIV_10   (uint32_t)((RCC_CFGR2_ADCPRE12 << 16U) | RCC_CFGR2_ADCPRE12_DIV10)  
#define LL_RCC_ADC12_CLKSRC_PLL_DIV_12   (uint32_t)((RCC_CFGR2_ADCPRE12 << 16U) | RCC_CFGR2_ADCPRE12_DIV12)  
#define LL_RCC_ADC12_CLKSRC_PLL_DIV_16   (uint32_t)((RCC_CFGR2_ADCPRE12 << 16U) | RCC_CFGR2_ADCPRE12_DIV16)  
#define LL_RCC_ADC12_CLKSRC_PLL_DIV_32   (uint32_t)((RCC_CFGR2_ADCPRE12 << 16U) | RCC_CFGR2_ADCPRE12_DIV32)  
#define LL_RCC_ADC12_CLKSRC_PLL_DIV_64   (uint32_t)((RCC_CFGR2_ADCPRE12 << 16U) | RCC_CFGR2_ADCPRE12_DIV64)  
#define LL_RCC_ADC12_CLKSRC_PLL_DIV_128  (uint32_t)((RCC_CFGR2_ADCPRE12 << 16U) | RCC_CFGR2_ADCPRE12_DIV128) 
#define LL_RCC_ADC12_CLKSRC_PLL_DIV_256  (uint32_t)((RCC_CFGR2_ADCPRE12 << 16U) | RCC_CFGR2_ADCPRE12_DIV256) 
#define LL_RCC_ADC34_CLKSRC_HCLK         (uint32_t)((RCC_CFGR2_ADCPRE34 << 16U) | RCC_CFGR2_ADCPRE34_NO)     
#define LL_RCC_ADC34_CLKSRC_PLL_DIV_1    (uint32_t)((RCC_CFGR2_ADCPRE34 << 16U) | RCC_CFGR2_ADCPRE34_DIV1)   
#define LL_RCC_ADC34_CLKSRC_PLL_DIV_2    (uint32_t)((RCC_CFGR2_ADCPRE34 << 16U) | RCC_CFGR2_ADCPRE34_DIV2)   
#define LL_RCC_ADC34_CLKSRC_PLL_DIV_4    (uint32_t)((RCC_CFGR2_ADCPRE34 << 16U) | RCC_CFGR2_ADCPRE34_DIV4)   
#define LL_RCC_ADC34_CLKSRC_PLL_DIV_6    (uint32_t)((RCC_CFGR2_ADCPRE34 << 16U) | RCC_CFGR2_ADCPRE34_DIV6)   
#define LL_RCC_ADC34_CLKSRC_PLL_DIV_8    (uint32_t)((RCC_CFGR2_ADCPRE34 << 16U) | RCC_CFGR2_ADCPRE34_DIV8)   
#define LL_RCC_ADC34_CLKSRC_PLL_DIV_10   (uint32_t)((RCC_CFGR2_ADCPRE34 << 16U) | RCC_CFGR2_ADCPRE34_DIV10)  
#define LL_RCC_ADC34_CLKSRC_PLL_DIV_12   (uint32_t)((RCC_CFGR2_ADCPRE34 << 16U) | RCC_CFGR2_ADCPRE34_DIV12)  
#define LL_RCC_ADC34_CLKSRC_PLL_DIV_16   (uint32_t)((RCC_CFGR2_ADCPRE34 << 16U) | RCC_CFGR2_ADCPRE34_DIV16)  
#define LL_RCC_ADC34_CLKSRC_PLL_DIV_32   (uint32_t)((RCC_CFGR2_ADCPRE34 << 16U) | RCC_CFGR2_ADCPRE34_DIV32)  
#define LL_RCC_ADC34_CLKSRC_PLL_DIV_64   (uint32_t)((RCC_CFGR2_ADCPRE34 << 16U) | RCC_CFGR2_ADCPRE34_DIV64)  
#define LL_RCC_ADC34_CLKSRC_PLL_DIV_128  (uint32_t)((RCC_CFGR2_ADCPRE34 << 16U) | RCC_CFGR2_ADCPRE34_DIV128) 
#define LL_RCC_ADC34_CLKSRC_PLL_DIV_256  (uint32_t)((RCC_CFGR2_ADCPRE34 << 16U) | RCC_CFGR2_ADCPRE34_DIV256) 
#else
#define LL_RCC_ADC12_CLKSRC_HCLK         RCC_CFGR2_ADCPRE12_NO     
#define LL_RCC_ADC12_CLKSRC_PLL_DIV_1    RCC_CFGR2_ADCPRE12_DIV1   
#define LL_RCC_ADC12_CLKSRC_PLL_DIV_2    RCC_CFGR2_ADCPRE12_DIV2   
#define LL_RCC_ADC12_CLKSRC_PLL_DIV_4    RCC_CFGR2_ADCPRE12_DIV4   
#define LL_RCC_ADC12_CLKSRC_PLL_DIV_6    RCC_CFGR2_ADCPRE12_DIV6   
#define LL_RCC_ADC12_CLKSRC_PLL_DIV_8    RCC_CFGR2_ADCPRE12_DIV8   
#define LL_RCC_ADC12_CLKSRC_PLL_DIV_10   RCC_CFGR2_ADCPRE12_DIV10  
#define LL_RCC_ADC12_CLKSRC_PLL_DIV_12   RCC_CFGR2_ADCPRE12_DIV12  
#define LL_RCC_ADC12_CLKSRC_PLL_DIV_16   RCC_CFGR2_ADCPRE12_DIV16  
#define LL_RCC_ADC12_CLKSRC_PLL_DIV_32   RCC_CFGR2_ADCPRE12_DIV32  
#define LL_RCC_ADC12_CLKSRC_PLL_DIV_64   RCC_CFGR2_ADCPRE12_DIV64  
#define LL_RCC_ADC12_CLKSRC_PLL_DIV_128  RCC_CFGR2_ADCPRE12_DIV128 
#define LL_RCC_ADC12_CLKSRC_PLL_DIV_256  RCC_CFGR2_ADCPRE12_DIV256 
#endif /* RCC_CFGR2_ADCPRE12 && RCC_CFGR2_ADCPRE34 */
 
#endif /* RCC_CFGR_ADCPRE */
 
#if defined(RCC_CFGR_SDPRE)
#define LL_RCC_SDADC_CLKSRC_SYS_DIV_1    RCC_CFGR_SDPRE_DIV1   
#define LL_RCC_SDADC_CLKSRC_SYS_DIV_2    RCC_CFGR_SDPRE_DIV2   
#define LL_RCC_SDADC_CLKSRC_SYS_DIV_4    RCC_CFGR_SDPRE_DIV4   
#define LL_RCC_SDADC_CLKSRC_SYS_DIV_6    RCC_CFGR_SDPRE_DIV6   
#define LL_RCC_SDADC_CLKSRC_SYS_DIV_8    RCC_CFGR_SDPRE_DIV8   
#define LL_RCC_SDADC_CLKSRC_SYS_DIV_10   RCC_CFGR_SDPRE_DIV10  
#define LL_RCC_SDADC_CLKSRC_SYS_DIV_12   RCC_CFGR_SDPRE_DIV12  
#define LL_RCC_SDADC_CLKSRC_SYS_DIV_14   RCC_CFGR_SDPRE_DIV14  
#define LL_RCC_SDADC_CLKSRC_SYS_DIV_16   RCC_CFGR_SDPRE_DIV16  
#define LL_RCC_SDADC_CLKSRC_SYS_DIV_20   RCC_CFGR_SDPRE_DIV20  
#define LL_RCC_SDADC_CLKSRC_SYS_DIV_24   RCC_CFGR_SDPRE_DIV24  
#define LL_RCC_SDADC_CLKSRC_SYS_DIV_28   RCC_CFGR_SDPRE_DIV28  
#define LL_RCC_SDADC_CLKSRC_SYS_DIV_32   RCC_CFGR_SDPRE_DIV32  
#define LL_RCC_SDADC_CLKSRC_SYS_DIV_36   RCC_CFGR_SDPRE_DIV36  
#define LL_RCC_SDADC_CLKSRC_SYS_DIV_40   RCC_CFGR_SDPRE_DIV40  
#define LL_RCC_SDADC_CLKSRC_SYS_DIV_44   RCC_CFGR_SDPRE_DIV44  
#define LL_RCC_SDADC_CLKSRC_SYS_DIV_48   RCC_CFGR_SDPRE_DIV48  
#endif /* RCC_CFGR_SDPRE */
 
#define LL_RCC_USART1_CLKSOURCE          RCC_POSITION_USART1SW 
#if defined(RCC_CFGR3_USART2SW)
#define LL_RCC_USART2_CLKSOURCE          RCC_POSITION_USART2SW 
#endif /* RCC_CFGR3_USART2SW */
#if defined(RCC_CFGR3_USART3SW)
#define LL_RCC_USART3_CLKSOURCE          RCC_POSITION_USART3SW 
#endif /* RCC_CFGR3_USART3SW */
#if defined(RCC_CFGR3_UART4SW) || defined(RCC_CFGR3_UART5SW)
#define LL_RCC_UART4_CLKSOURCE           RCC_CFGR3_UART4SW 
#define LL_RCC_UART5_CLKSOURCE           RCC_CFGR3_UART5SW 
#endif /* RCC_CFGR3_UART4SW || RCC_CFGR3_UART5SW */
 
#define LL_RCC_I2C1_CLKSOURCE            RCC_CFGR3_I2C1SW 
#if defined(RCC_CFGR3_I2C2SW)
#define LL_RCC_I2C2_CLKSOURCE            RCC_CFGR3_I2C2SW 
#endif /*RCC_CFGR3_I2C2SW*/
#if defined(RCC_CFGR3_I2C3SW)
#define LL_RCC_I2C3_CLKSOURCE            RCC_CFGR3_I2C3SW 
#endif /*RCC_CFGR3_I2C3SW*/
#if defined(RCC_CFGR_I2SSRC)
#define LL_RCC_I2S_CLKSOURCE             RCC_CFGR_I2SSRC       
#endif /* RCC_CFGR_I2SSRC */
 
#if defined(RCC_CFGR3_TIMSW)
#define LL_RCC_TIM1_CLKSOURCE            (RCC_POSITION_TIM1SW - RCC_POSITION_TIM1SW)  
#if defined(RCC_CFGR3_TIM2SW)
#define LL_RCC_TIM2_CLKSOURCE            (RCC_POSITION_TIM2SW - RCC_POSITION_TIM1SW)  
#endif /*RCC_CFGR3_TIM2SW*/
#if defined(RCC_CFGR3_TIM8SW)
#define LL_RCC_TIM8_CLKSOURCE            (RCC_POSITION_TIM8SW - RCC_POSITION_TIM1SW)  
#endif /*RCC_CFGR3_TIM8SW*/
#if defined(RCC_CFGR3_TIM15SW)
#define LL_RCC_TIM15_CLKSOURCE           (RCC_POSITION_TIM15SW - RCC_POSITION_TIM1SW) 
#endif /*RCC_CFGR3_TIM15SW*/
#if defined(RCC_CFGR3_TIM16SW)
#define LL_RCC_TIM16_CLKSOURCE           (RCC_POSITION_TIM16SW - RCC_POSITION_TIM1SW) 
#endif /*RCC_CFGR3_TIM16SW*/
#if defined(RCC_CFGR3_TIM17SW)
#define LL_RCC_TIM17_CLKSOURCE           (RCC_POSITION_TIM17SW - RCC_POSITION_TIM1SW) 
#endif /*RCC_CFGR3_TIM17SW*/
#if defined(RCC_CFGR3_TIM20SW)
#define LL_RCC_TIM20_CLKSOURCE           (RCC_POSITION_TIM20SW - RCC_POSITION_TIM1SW) 
#endif /*RCC_CFGR3_TIM20SW*/
#if defined(RCC_CFGR3_TIM34SW)
#define LL_RCC_TIM34_CLKSOURCE           (RCC_POSITION_TIM34SW - RCC_POSITION_TIM1SW) 
#endif /*RCC_CFGR3_TIM34SW*/
#endif /* RCC_CFGR3_TIMSW */
 
#if defined(HRTIM1)
#define LL_RCC_HRTIM1_CLKSOURCE          RCC_CFGR3_HRTIM1SW 
#endif /* HRTIM1 */
 
#if defined(CEC)
#define LL_RCC_CEC_CLKSOURCE             RCC_CFGR3_CECSW 
#endif /* CEC */
 
#if defined(USB)
#define LL_RCC_USB_CLKSOURCE             RCC_CFGR_USBPRE 
#endif /* USB */
 
#if defined(RCC_CFGR_ADCPRE)
#define LL_RCC_ADC_CLKSOURCE             RCC_CFGR_ADCPRE 
#endif /* RCC_CFGR_ADCPRE */
 
#if defined(RCC_CFGR2_ADC1PRES) || defined(RCC_CFGR2_ADCPRE12) || defined(RCC_CFGR2_ADCPRE34)
#if defined(RCC_CFGR2_ADC1PRES)
#define LL_RCC_ADC1_CLKSOURCE            RCC_CFGR2_ADC1PRES 
#else
#define LL_RCC_ADC12_CLKSOURCE           RCC_CFGR2_ADCPRE12 
#if defined(RCC_CFGR2_ADCPRE34)
#define LL_RCC_ADC34_CLKSOURCE           RCC_CFGR2_ADCPRE34 
#endif /*RCC_CFGR2_ADCPRE34*/
#endif /*RCC_CFGR2_ADC1PRES*/
#endif /* RCC_CFGR2_ADC1PRES || RCC_CFGR2_ADCPRE12 || RCC_CFGR2_ADCPRE34 */
 
#if defined(RCC_CFGR_SDPRE)
#define LL_RCC_SDADC_CLKSOURCE           RCC_CFGR_SDPRE  
#endif /* RCC_CFGR_SDPRE */
 
 
#define LL_RCC_RTC_CLKSOURCE_NONE          0x00000000U                   
#define LL_RCC_RTC_CLKSOURCE_LSE           RCC_BDCR_RTCSEL_0       
#define LL_RCC_RTC_CLKSOURCE_LSI           RCC_BDCR_RTCSEL_1       
#define LL_RCC_RTC_CLKSOURCE_HSE_DIV32     RCC_BDCR_RTCSEL         
#define LL_RCC_PLL_MUL_2                   RCC_CFGR_PLLMUL2  
#define LL_RCC_PLL_MUL_3                   RCC_CFGR_PLLMUL3  
#define LL_RCC_PLL_MUL_4                   RCC_CFGR_PLLMUL4  
#define LL_RCC_PLL_MUL_5                   RCC_CFGR_PLLMUL5  
#define LL_RCC_PLL_MUL_6                   RCC_CFGR_PLLMUL6  
#define LL_RCC_PLL_MUL_7                   RCC_CFGR_PLLMUL7  
#define LL_RCC_PLL_MUL_8                   RCC_CFGR_PLLMUL8  
#define LL_RCC_PLL_MUL_9                   RCC_CFGR_PLLMUL9  
#define LL_RCC_PLL_MUL_10                  RCC_CFGR_PLLMUL10  
#define LL_RCC_PLL_MUL_11                  RCC_CFGR_PLLMUL11  
#define LL_RCC_PLL_MUL_12                  RCC_CFGR_PLLMUL12  
#define LL_RCC_PLL_MUL_13                  RCC_CFGR_PLLMUL13  
#define LL_RCC_PLL_MUL_14                  RCC_CFGR_PLLMUL14  
#define LL_RCC_PLL_MUL_15                  RCC_CFGR_PLLMUL15  
#define LL_RCC_PLL_MUL_16                  RCC_CFGR_PLLMUL16  
#define LL_RCC_PLLSOURCE_NONE              0x00000000U                                   
#define LL_RCC_PLLSOURCE_HSE               RCC_CFGR_PLLSRC_HSE_PREDIV                    
#if defined(RCC_PLLSRC_PREDIV1_SUPPORT)
#define LL_RCC_PLLSOURCE_HSI               RCC_CFGR_PLLSRC_HSI_PREDIV                    
#else
#define LL_RCC_PLLSOURCE_HSI_DIV_2         RCC_CFGR_PLLSRC_HSI_DIV2                      
#define LL_RCC_PLLSOURCE_HSE_DIV_1         (RCC_CFGR_PLLSRC_HSE_PREDIV | RCC_CFGR2_PREDIV_DIV1)    
#define LL_RCC_PLLSOURCE_HSE_DIV_2         (RCC_CFGR_PLLSRC_HSE_PREDIV | RCC_CFGR2_PREDIV_DIV2)    
#define LL_RCC_PLLSOURCE_HSE_DIV_3         (RCC_CFGR_PLLSRC_HSE_PREDIV | RCC_CFGR2_PREDIV_DIV3)    
#define LL_RCC_PLLSOURCE_HSE_DIV_4         (RCC_CFGR_PLLSRC_HSE_PREDIV | RCC_CFGR2_PREDIV_DIV4)    
#define LL_RCC_PLLSOURCE_HSE_DIV_5         (RCC_CFGR_PLLSRC_HSE_PREDIV | RCC_CFGR2_PREDIV_DIV5)    
#define LL_RCC_PLLSOURCE_HSE_DIV_6         (RCC_CFGR_PLLSRC_HSE_PREDIV | RCC_CFGR2_PREDIV_DIV6)    
#define LL_RCC_PLLSOURCE_HSE_DIV_7         (RCC_CFGR_PLLSRC_HSE_PREDIV | RCC_CFGR2_PREDIV_DIV7)    
#define LL_RCC_PLLSOURCE_HSE_DIV_8         (RCC_CFGR_PLLSRC_HSE_PREDIV | RCC_CFGR2_PREDIV_DIV8)    
#define LL_RCC_PLLSOURCE_HSE_DIV_9         (RCC_CFGR_PLLSRC_HSE_PREDIV | RCC_CFGR2_PREDIV_DIV9)    
#define LL_RCC_PLLSOURCE_HSE_DIV_10        (RCC_CFGR_PLLSRC_HSE_PREDIV | RCC_CFGR2_PREDIV_DIV10)   
#define LL_RCC_PLLSOURCE_HSE_DIV_11        (RCC_CFGR_PLLSRC_HSE_PREDIV | RCC_CFGR2_PREDIV_DIV11)   
#define LL_RCC_PLLSOURCE_HSE_DIV_12        (RCC_CFGR_PLLSRC_HSE_PREDIV | RCC_CFGR2_PREDIV_DIV12)   
#define LL_RCC_PLLSOURCE_HSE_DIV_13        (RCC_CFGR_PLLSRC_HSE_PREDIV | RCC_CFGR2_PREDIV_DIV13)   
#define LL_RCC_PLLSOURCE_HSE_DIV_14        (RCC_CFGR_PLLSRC_HSE_PREDIV | RCC_CFGR2_PREDIV_DIV14)   
#define LL_RCC_PLLSOURCE_HSE_DIV_15        (RCC_CFGR_PLLSRC_HSE_PREDIV | RCC_CFGR2_PREDIV_DIV15)   
#define LL_RCC_PLLSOURCE_HSE_DIV_16        (RCC_CFGR_PLLSRC_HSE_PREDIV | RCC_CFGR2_PREDIV_DIV16)   
#endif /* RCC_PLLSRC_PREDIV1_SUPPORT */
#define LL_RCC_PREDIV_DIV_1                RCC_CFGR2_PREDIV_DIV1   
#define LL_RCC_PREDIV_DIV_2                RCC_CFGR2_PREDIV_DIV2   
#define LL_RCC_PREDIV_DIV_3                RCC_CFGR2_PREDIV_DIV3   
#define LL_RCC_PREDIV_DIV_4                RCC_CFGR2_PREDIV_DIV4   
#define LL_RCC_PREDIV_DIV_5                RCC_CFGR2_PREDIV_DIV5   
#define LL_RCC_PREDIV_DIV_6                RCC_CFGR2_PREDIV_DIV6   
#define LL_RCC_PREDIV_DIV_7                RCC_CFGR2_PREDIV_DIV7   
#define LL_RCC_PREDIV_DIV_8                RCC_CFGR2_PREDIV_DIV8   
#define LL_RCC_PREDIV_DIV_9                RCC_CFGR2_PREDIV_DIV9   
#define LL_RCC_PREDIV_DIV_10               RCC_CFGR2_PREDIV_DIV10  
#define LL_RCC_PREDIV_DIV_11               RCC_CFGR2_PREDIV_DIV11  
#define LL_RCC_PREDIV_DIV_12               RCC_CFGR2_PREDIV_DIV12  
#define LL_RCC_PREDIV_DIV_13               RCC_CFGR2_PREDIV_DIV13  
#define LL_RCC_PREDIV_DIV_14               RCC_CFGR2_PREDIV_DIV14  
#define LL_RCC_PREDIV_DIV_15               RCC_CFGR2_PREDIV_DIV15  
#define LL_RCC_PREDIV_DIV_16               RCC_CFGR2_PREDIV_DIV16  
/* Exported macro ------------------------------------------------------------*/
#define LL_RCC_WriteReg(__REG__, __VALUE__) WRITE_REG(RCC->__REG__, (__VALUE__))
 
#define LL_RCC_ReadReg(__REG__) READ_REG(RCC->__REG__)
#if defined(RCC_PLLSRC_PREDIV1_SUPPORT)
#define __LL_RCC_CALC_PLLCLK_FREQ(__INPUTFREQ__, __PLLMUL__, __PLLPREDIV__) \
          (((__INPUTFREQ__) / ((((__PLLPREDIV__) & RCC_CFGR2_PREDIV) + 1U))) * ((((__PLLMUL__) & RCC_CFGR_PLLMUL) >> RCC_POSITION_PLLMUL) + 2U))
 
#else
#define __LL_RCC_CALC_PLLCLK_FREQ(__INPUTFREQ__, __PLLMUL__) \
          ((__INPUTFREQ__) * ((((__PLLMUL__) & RCC_CFGR_PLLMUL) >> RCC_POSITION_PLLMUL) + 2U))
#endif /* RCC_PLLSRC_PREDIV1_SUPPORT */
#define __LL_RCC_CALC_HCLK_FREQ(__SYSCLKFREQ__, __AHBPRESCALER__) ((__SYSCLKFREQ__) >> AHBPrescTable[((__AHBPRESCALER__) & RCC_CFGR_HPRE) >>  RCC_CFGR_HPRE_Pos])
 
#define __LL_RCC_CALC_PCLK1_FREQ(__HCLKFREQ__, __APB1PRESCALER__) ((__HCLKFREQ__) >> APBPrescTable[(__APB1PRESCALER__) >>  RCC_CFGR_PPRE1_Pos])
 
#define __LL_RCC_CALC_PCLK2_FREQ(__HCLKFREQ__, __APB2PRESCALER__) ((__HCLKFREQ__) >> APBPrescTable[(__APB2PRESCALER__) >>  RCC_CFGR_PPRE2_Pos])
 
/* Exported functions --------------------------------------------------------*/
__STATIC_INLINE void LL_RCC_HSE_EnableCSS(void)
{
  SET_BIT(RCC->CR, RCC_CR_CSSON);
}
 
__STATIC_INLINE void LL_RCC_HSE_DisableCSS(void)
{
  CLEAR_BIT(RCC->CR, RCC_CR_CSSON);
}
 
__STATIC_INLINE void LL_RCC_HSE_EnableBypass(void)
{
  SET_BIT(RCC->CR, RCC_CR_HSEBYP);
}
 
__STATIC_INLINE void LL_RCC_HSE_DisableBypass(void)
{
  CLEAR_BIT(RCC->CR, RCC_CR_HSEBYP);
}
 
__STATIC_INLINE void LL_RCC_HSE_Enable(void)
{
  SET_BIT(RCC->CR, RCC_CR_HSEON);
}
 
__STATIC_INLINE void LL_RCC_HSE_Disable(void)
{
  CLEAR_BIT(RCC->CR, RCC_CR_HSEON);
}
 
__STATIC_INLINE uint32_t LL_RCC_HSE_IsReady(void)
{
  return (READ_BIT(RCC->CR, RCC_CR_HSERDY) == (RCC_CR_HSERDY));
}
 
__STATIC_INLINE void LL_RCC_HSI_Enable(void)
{
  SET_BIT(RCC->CR, RCC_CR_HSION);
}
 
__STATIC_INLINE void LL_RCC_HSI_Disable(void)
{
  CLEAR_BIT(RCC->CR, RCC_CR_HSION);
}
 
__STATIC_INLINE uint32_t LL_RCC_HSI_IsReady(void)
{
  return (READ_BIT(RCC->CR, RCC_CR_HSIRDY) == (RCC_CR_HSIRDY));
}
 
__STATIC_INLINE uint32_t LL_RCC_HSI_GetCalibration(void)
{
  return (uint32_t)(READ_BIT(RCC->CR, RCC_CR_HSICAL) >> RCC_CR_HSICAL_Pos);
}
 
__STATIC_INLINE void LL_RCC_HSI_SetCalibTrimming(uint32_t Value)
{
  MODIFY_REG(RCC->CR, RCC_CR_HSITRIM, Value << RCC_CR_HSITRIM_Pos);
}
 
__STATIC_INLINE uint32_t LL_RCC_HSI_GetCalibTrimming(void)
{
  return (uint32_t)(READ_BIT(RCC->CR, RCC_CR_HSITRIM) >> RCC_CR_HSITRIM_Pos);
}
 
__STATIC_INLINE void LL_RCC_LSE_Enable(void)
{
  SET_BIT(RCC->BDCR, RCC_BDCR_LSEON);
}
 
__STATIC_INLINE void LL_RCC_LSE_Disable(void)
{
  CLEAR_BIT(RCC->BDCR, RCC_BDCR_LSEON);
}
 
__STATIC_INLINE void LL_RCC_LSE_EnableBypass(void)
{
  SET_BIT(RCC->BDCR, RCC_BDCR_LSEBYP);
}
 
__STATIC_INLINE void LL_RCC_LSE_DisableBypass(void)
{
  CLEAR_BIT(RCC->BDCR, RCC_BDCR_LSEBYP);
}
 
__STATIC_INLINE void LL_RCC_LSE_SetDriveCapability(uint32_t LSEDrive)
{
  MODIFY_REG(RCC->BDCR, RCC_BDCR_LSEDRV, LSEDrive);
}
 
__STATIC_INLINE uint32_t LL_RCC_LSE_GetDriveCapability(void)
{
  return (uint32_t)(READ_BIT(RCC->BDCR, RCC_BDCR_LSEDRV));
}
 
__STATIC_INLINE uint32_t LL_RCC_LSE_IsReady(void)
{
  return (READ_BIT(RCC->BDCR, RCC_BDCR_LSERDY) == (RCC_BDCR_LSERDY));
}
 
__STATIC_INLINE void LL_RCC_LSI_Enable(void)
{
  SET_BIT(RCC->CSR, RCC_CSR_LSION);
}
 
__STATIC_INLINE void LL_RCC_LSI_Disable(void)
{
  CLEAR_BIT(RCC->CSR, RCC_CSR_LSION);
}
 
__STATIC_INLINE uint32_t LL_RCC_LSI_IsReady(void)
{
  return (READ_BIT(RCC->CSR, RCC_CSR_LSIRDY) == (RCC_CSR_LSIRDY));
}
 
__STATIC_INLINE void LL_RCC_SetSysClkSource(uint32_t Source)
{
  MODIFY_REG(RCC->CFGR, RCC_CFGR_SW, Source);
}
 
__STATIC_INLINE uint32_t LL_RCC_GetSysClkSource(void)
{
  return (uint32_t)(READ_BIT(RCC->CFGR, RCC_CFGR_SWS));
}
 
__STATIC_INLINE void LL_RCC_SetAHBPrescaler(uint32_t Prescaler)
{
  MODIFY_REG(RCC->CFGR, RCC_CFGR_HPRE, Prescaler);
}
 
__STATIC_INLINE void LL_RCC_SetAPB1Prescaler(uint32_t Prescaler)
{
  MODIFY_REG(RCC->CFGR, RCC_CFGR_PPRE1, Prescaler);
}
 
__STATIC_INLINE void LL_RCC_SetAPB2Prescaler(uint32_t Prescaler)
{
  MODIFY_REG(RCC->CFGR, RCC_CFGR_PPRE2, Prescaler);
}
 
__STATIC_INLINE uint32_t LL_RCC_GetAHBPrescaler(void)
{
  return (uint32_t)(READ_BIT(RCC->CFGR, RCC_CFGR_HPRE));
}
 
__STATIC_INLINE uint32_t LL_RCC_GetAPB1Prescaler(void)
{
  return (uint32_t)(READ_BIT(RCC->CFGR, RCC_CFGR_PPRE1));
}
 
__STATIC_INLINE uint32_t LL_RCC_GetAPB2Prescaler(void)
{
  return (uint32_t)(READ_BIT(RCC->CFGR, RCC_CFGR_PPRE2));
}
 
__STATIC_INLINE void LL_RCC_ConfigMCO(uint32_t MCOxSource, uint32_t MCOxPrescaler)
{
#if defined(RCC_CFGR_MCOPRE)
#if defined(RCC_CFGR_PLLNODIV)
  MODIFY_REG(RCC->CFGR, RCC_CFGR_MCOSEL | RCC_CFGR_MCOPRE | RCC_CFGR_PLLNODIV, MCOxSource | MCOxPrescaler);
#else
  MODIFY_REG(RCC->CFGR, RCC_CFGR_MCOSEL | RCC_CFGR_MCOPRE, MCOxSource | MCOxPrescaler);
#endif /* RCC_CFGR_PLLNODIV */
#else
  MODIFY_REG(RCC->CFGR, RCC_CFGR_MCOSEL, MCOxSource);
#endif /* RCC_CFGR_MCOPRE */
}
 
__STATIC_INLINE void LL_RCC_SetUSARTClockSource(uint32_t USARTxSource)
{
  MODIFY_REG(RCC->CFGR3, (RCC_CFGR3_USART1SW << ((USARTxSource  & 0xFF000000U) >> 24U)), (USARTxSource & 0x00FFFFFFU));
}
 
#if defined(RCC_CFGR3_UART4SW) || defined(RCC_CFGR3_UART5SW)
__STATIC_INLINE void LL_RCC_SetUARTClockSource(uint32_t UARTxSource)
{
  MODIFY_REG(RCC->CFGR3, ((UARTxSource  & 0x0000FFFFU) << 8U), (UARTxSource & (RCC_CFGR3_UART4SW | RCC_CFGR3_UART5SW)));
}
#endif /* RCC_CFGR3_UART4SW || RCC_CFGR3_UART5SW */
 
__STATIC_INLINE void LL_RCC_SetI2CClockSource(uint32_t I2CxSource)
{
  MODIFY_REG(RCC->CFGR3, ((I2CxSource  & 0xFF000000U) >> 24U), (I2CxSource & 0x00FFFFFFU));
}
 
#if defined(RCC_CFGR_I2SSRC)
__STATIC_INLINE void LL_RCC_SetI2SClockSource(uint32_t I2SxSource)
{
  MODIFY_REG(RCC->CFGR, RCC_CFGR_I2SSRC, I2SxSource);
}
#endif /* RCC_CFGR_I2SSRC */
 
#if defined(RCC_CFGR3_TIMSW)
__STATIC_INLINE void LL_RCC_SetTIMClockSource(uint32_t TIMxSource)
{
  MODIFY_REG(RCC->CFGR3, (RCC_CFGR3_TIM1SW << (TIMxSource >> 27U)), (TIMxSource & 0x03FFFFFFU));
}
#endif /* RCC_CFGR3_TIMSW */
 
#if defined(HRTIM1)
__STATIC_INLINE void LL_RCC_SetHRTIMClockSource(uint32_t HRTIMxSource)
{
  MODIFY_REG(RCC->CFGR3, RCC_CFGR3_HRTIMSW, HRTIMxSource);
}
#endif /* HRTIM1 */
 
#if defined(CEC)
__STATIC_INLINE void LL_RCC_SetCECClockSource(uint32_t CECxSource)
{
  MODIFY_REG(RCC->CFGR3, RCC_CFGR3_CECSW, CECxSource);
}
#endif /* CEC */
 
#if defined(USB)
__STATIC_INLINE void LL_RCC_SetUSBClockSource(uint32_t USBxSource)
{
  MODIFY_REG(RCC->CFGR, RCC_CFGR_USBPRE, USBxSource);
}
#endif /* USB */
 
#if defined(RCC_CFGR_ADCPRE)
__STATIC_INLINE void LL_RCC_SetADCClockSource(uint32_t ADCxSource)
{
  MODIFY_REG(RCC->CFGR, RCC_CFGR_ADCPRE, ADCxSource);
}
 
#elif defined(RCC_CFGR2_ADC1PRES)
__STATIC_INLINE void LL_RCC_SetADCClockSource(uint32_t ADCxSource)
{
  MODIFY_REG(RCC->CFGR2, RCC_CFGR2_ADC1PRES, ADCxSource);
}
 
#elif defined(RCC_CFGR2_ADCPRE12) || defined(RCC_CFGR2_ADCPRE34)
__STATIC_INLINE void LL_RCC_SetADCClockSource(uint32_t ADCxSource)
{
#if defined(RCC_CFGR2_ADCPRE34)
  MODIFY_REG(RCC->CFGR2, (ADCxSource >> 16U), (ADCxSource & 0x0000FFFFU));
#else
  MODIFY_REG(RCC->CFGR2, RCC_CFGR2_ADCPRE12, ADCxSource);
#endif /* RCC_CFGR2_ADCPRE34 */
}
#endif /* RCC_CFGR_ADCPRE */
 
#if defined(RCC_CFGR_SDPRE)
__STATIC_INLINE void LL_RCC_SetSDADCClockSource(uint32_t SDADCxSource)
{
  MODIFY_REG(RCC->CFGR, RCC_CFGR_SDPRE, SDADCxSource);
}
#endif /* RCC_CFGR_SDPRE */
 
__STATIC_INLINE uint32_t LL_RCC_GetUSARTClockSource(uint32_t USARTx)
{
  return (uint32_t)(READ_BIT(RCC->CFGR3, (RCC_CFGR3_USART1SW << USARTx)) | (USARTx << 24U));
}
 
#if defined(RCC_CFGR3_UART4SW) || defined(RCC_CFGR3_UART5SW)
__STATIC_INLINE uint32_t LL_RCC_GetUARTClockSource(uint32_t UARTx)
{
  return (uint32_t)(READ_BIT(RCC->CFGR3, UARTx) | (UARTx >> 8U));
}
#endif /* RCC_CFGR3_UART4SW || RCC_CFGR3_UART5SW */
 
__STATIC_INLINE uint32_t LL_RCC_GetI2CClockSource(uint32_t I2Cx)
{
  return (uint32_t)(READ_BIT(RCC->CFGR3, I2Cx) | (I2Cx << 24U));
}
 
#if defined(RCC_CFGR_I2SSRC)
__STATIC_INLINE uint32_t LL_RCC_GetI2SClockSource(uint32_t I2Sx)
{
  return (uint32_t)(READ_BIT(RCC->CFGR, I2Sx));
}
#endif /* RCC_CFGR_I2SSRC */
 
#if defined(RCC_CFGR3_TIMSW)
__STATIC_INLINE uint32_t LL_RCC_GetTIMClockSource(uint32_t TIMx)
{
  return (uint32_t)(READ_BIT(RCC->CFGR3, (RCC_CFGR3_TIM1SW << TIMx)) | (TIMx << 27U));
}
#endif /* RCC_CFGR3_TIMSW */
 
#if defined(HRTIM1)
__STATIC_INLINE uint32_t LL_RCC_GetHRTIMClockSource(uint32_t HRTIMx)
{
  return (uint32_t)(READ_BIT(RCC->CFGR3, HRTIMx));
}
#endif /* HRTIM1 */
 
#if defined(CEC)
__STATIC_INLINE uint32_t LL_RCC_GetCECClockSource(uint32_t CECx)
{
  return (uint32_t)(READ_BIT(RCC->CFGR3, CECx));
}
#endif /* CEC */
 
#if defined(USB)
__STATIC_INLINE uint32_t LL_RCC_GetUSBClockSource(uint32_t USBx)
{
  return (uint32_t)(READ_BIT(RCC->CFGR, USBx));
}
#endif /* USB */
 
#if defined(RCC_CFGR_ADCPRE)
__STATIC_INLINE uint32_t LL_RCC_GetADCClockSource(uint32_t ADCx)
{
  return (uint32_t)(READ_BIT(RCC->CFGR, ADCx));
}
 
#elif defined(RCC_CFGR2_ADC1PRES)
__STATIC_INLINE uint32_t LL_RCC_GetADCClockSource(uint32_t ADCx)
{
  return (uint32_t)(READ_BIT(RCC->CFGR2, ADCx));
}
 
#elif defined(RCC_CFGR2_ADCPRE12) || defined(RCC_CFGR2_ADCPRE34)
__STATIC_INLINE uint32_t LL_RCC_GetADCClockSource(uint32_t ADCx)
{
#if defined(RCC_CFGR2_ADCPRE34)
  return (uint32_t)(READ_BIT(RCC->CFGR2, ADCx) | (ADCx << 16U));
#else
  return (uint32_t)(READ_BIT(RCC->CFGR2, ADCx));
#endif /*RCC_CFGR2_ADCPRE34*/
}
#endif /* RCC_CFGR_ADCPRE */
 
#if defined(RCC_CFGR_SDPRE)
__STATIC_INLINE uint32_t LL_RCC_GetSDADCClockSource(uint32_t SDADCx)
{
  return (uint32_t)(READ_BIT(RCC->CFGR, SDADCx));
}
#endif /* RCC_CFGR_SDPRE */
 
__STATIC_INLINE void LL_RCC_SetRTCClockSource(uint32_t Source)
{
  MODIFY_REG(RCC->BDCR, RCC_BDCR_RTCSEL, Source);
}
 
__STATIC_INLINE uint32_t LL_RCC_GetRTCClockSource(void)
{
  return (uint32_t)(READ_BIT(RCC->BDCR, RCC_BDCR_RTCSEL));
}
 
__STATIC_INLINE void LL_RCC_EnableRTC(void)
{
  SET_BIT(RCC->BDCR, RCC_BDCR_RTCEN);
}
 
__STATIC_INLINE void LL_RCC_DisableRTC(void)
{
  CLEAR_BIT(RCC->BDCR, RCC_BDCR_RTCEN);
}
 
__STATIC_INLINE uint32_t LL_RCC_IsEnabledRTC(void)
{
  return (READ_BIT(RCC->BDCR, RCC_BDCR_RTCEN) == (RCC_BDCR_RTCEN));
}
 
__STATIC_INLINE void LL_RCC_ForceBackupDomainReset(void)
{
  SET_BIT(RCC->BDCR, RCC_BDCR_BDRST);
}
 
__STATIC_INLINE void LL_RCC_ReleaseBackupDomainReset(void)
{
  CLEAR_BIT(RCC->BDCR, RCC_BDCR_BDRST);
}
 
__STATIC_INLINE void LL_RCC_PLL_Enable(void)
{
  SET_BIT(RCC->CR, RCC_CR_PLLON);
}
 
__STATIC_INLINE void LL_RCC_PLL_Disable(void)
{
  CLEAR_BIT(RCC->CR, RCC_CR_PLLON);
}
 
__STATIC_INLINE uint32_t LL_RCC_PLL_IsReady(void)
{
  return (READ_BIT(RCC->CR, RCC_CR_PLLRDY) == (RCC_CR_PLLRDY));
}
 
#if defined(RCC_PLLSRC_PREDIV1_SUPPORT)
__STATIC_INLINE void LL_RCC_PLL_ConfigDomain_SYS(uint32_t Source, uint32_t PLLMul, uint32_t PLLDiv)
{
  MODIFY_REG(RCC->CFGR, RCC_CFGR_PLLSRC | RCC_CFGR_PLLMUL, Source | PLLMul);
  MODIFY_REG(RCC->CFGR2, RCC_CFGR2_PREDIV, PLLDiv);
}
 
#else
 
__STATIC_INLINE void LL_RCC_PLL_ConfigDomain_SYS(uint32_t Source, uint32_t PLLMul)
{
  MODIFY_REG(RCC->CFGR, RCC_CFGR_PLLSRC | RCC_CFGR_PLLMUL, (Source & RCC_CFGR_PLLSRC) | PLLMul);
  MODIFY_REG(RCC->CFGR2, RCC_CFGR2_PREDIV, (Source & RCC_CFGR2_PREDIV));
}
#endif /* RCC_PLLSRC_PREDIV1_SUPPORT */
 
__STATIC_INLINE void LL_RCC_PLL_SetMainSource(uint32_t PLLSource)
{
  MODIFY_REG(RCC->CFGR, RCC_CFGR_PLLSRC, PLLSource);
}
 
__STATIC_INLINE uint32_t LL_RCC_PLL_GetMainSource(void)
{
  return (uint32_t)(READ_BIT(RCC->CFGR, RCC_CFGR_PLLSRC));
}
 
__STATIC_INLINE uint32_t LL_RCC_PLL_GetMultiplicator(void)
{
  return (uint32_t)(READ_BIT(RCC->CFGR, RCC_CFGR_PLLMUL));
}
 
__STATIC_INLINE uint32_t LL_RCC_PLL_GetPrediv(void)
{
  return (uint32_t)(READ_BIT(RCC->CFGR2, RCC_CFGR2_PREDIV));
}
 
__STATIC_INLINE void LL_RCC_ClearFlag_LSIRDY(void)
{
  SET_BIT(RCC->CIR, RCC_CIR_LSIRDYC);
}
 
__STATIC_INLINE void LL_RCC_ClearFlag_LSERDY(void)
{
  SET_BIT(RCC->CIR, RCC_CIR_LSERDYC);
}
 
__STATIC_INLINE void LL_RCC_ClearFlag_HSIRDY(void)
{
  SET_BIT(RCC->CIR, RCC_CIR_HSIRDYC);
}
 
__STATIC_INLINE void LL_RCC_ClearFlag_HSERDY(void)
{
  SET_BIT(RCC->CIR, RCC_CIR_HSERDYC);
}
 
__STATIC_INLINE void LL_RCC_ClearFlag_PLLRDY(void)
{
  SET_BIT(RCC->CIR, RCC_CIR_PLLRDYC);
}
 
__STATIC_INLINE void LL_RCC_ClearFlag_HSECSS(void)
{
  SET_BIT(RCC->CIR, RCC_CIR_CSSC);
}
 
__STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_LSIRDY(void)
{
  return (READ_BIT(RCC->CIR, RCC_CIR_LSIRDYF) == (RCC_CIR_LSIRDYF));
}
 
__STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_LSERDY(void)
{
  return (READ_BIT(RCC->CIR, RCC_CIR_LSERDYF) == (RCC_CIR_LSERDYF));
}
 
__STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_HSIRDY(void)
{
  return (READ_BIT(RCC->CIR, RCC_CIR_HSIRDYF) == (RCC_CIR_HSIRDYF));
}
 
__STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_HSERDY(void)
{
  return (READ_BIT(RCC->CIR, RCC_CIR_HSERDYF) == (RCC_CIR_HSERDYF));
}
 
#if defined(RCC_CFGR_MCOF)
__STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_MCO1(void)
{
  return (READ_BIT(RCC->CFGR, RCC_CFGR_MCOF) == (RCC_CFGR_MCOF));
}
#endif /* RCC_CFGR_MCOF */
 
__STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_PLLRDY(void)
{
  return (READ_BIT(RCC->CIR, RCC_CIR_PLLRDYF) == (RCC_CIR_PLLRDYF));
}
 
__STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_HSECSS(void)
{
  return (READ_BIT(RCC->CIR, RCC_CIR_CSSF) == (RCC_CIR_CSSF));
}
 
__STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_IWDGRST(void)
{
  return (READ_BIT(RCC->CSR, RCC_CSR_IWDGRSTF) == (RCC_CSR_IWDGRSTF));
}
 
__STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_LPWRRST(void)
{
  return (READ_BIT(RCC->CSR, RCC_CSR_LPWRRSTF) == (RCC_CSR_LPWRRSTF));
}
 
__STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_OBLRST(void)
{
  return (READ_BIT(RCC->CSR, RCC_CSR_OBLRSTF) == (RCC_CSR_OBLRSTF));
}
 
__STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_PINRST(void)
{
  return (READ_BIT(RCC->CSR, RCC_CSR_PINRSTF) == (RCC_CSR_PINRSTF));
}
 
__STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_PORRST(void)
{
  return (READ_BIT(RCC->CSR, RCC_CSR_PORRSTF) == (RCC_CSR_PORRSTF));
}
 
__STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_SFTRST(void)
{
  return (READ_BIT(RCC->CSR, RCC_CSR_SFTRSTF) == (RCC_CSR_SFTRSTF));
}
 
__STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_WWDGRST(void)
{
  return (READ_BIT(RCC->CSR, RCC_CSR_WWDGRSTF) == (RCC_CSR_WWDGRSTF));
}
 
#if defined(RCC_CSR_V18PWRRSTF)
__STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_V18PWRRST(void)
{
  return (READ_BIT(RCC->CSR, RCC_CSR_V18PWRRSTF) == (RCC_CSR_V18PWRRSTF));
}
#endif /* RCC_CSR_V18PWRRSTF */
 
__STATIC_INLINE void LL_RCC_ClearResetFlags(void)
{
  SET_BIT(RCC->CSR, RCC_CSR_RMVF);
}
 
__STATIC_INLINE void LL_RCC_EnableIT_LSIRDY(void)
{
  SET_BIT(RCC->CIR, RCC_CIR_LSIRDYIE);
}
 
__STATIC_INLINE void LL_RCC_EnableIT_LSERDY(void)
{
  SET_BIT(RCC->CIR, RCC_CIR_LSERDYIE);
}
 
__STATIC_INLINE void LL_RCC_EnableIT_HSIRDY(void)
{
  SET_BIT(RCC->CIR, RCC_CIR_HSIRDYIE);
}
 
__STATIC_INLINE void LL_RCC_EnableIT_HSERDY(void)
{
  SET_BIT(RCC->CIR, RCC_CIR_HSERDYIE);
}
 
__STATIC_INLINE void LL_RCC_EnableIT_PLLRDY(void)
{
  SET_BIT(RCC->CIR, RCC_CIR_PLLRDYIE);
}
 
__STATIC_INLINE void LL_RCC_DisableIT_LSIRDY(void)
{
  CLEAR_BIT(RCC->CIR, RCC_CIR_LSIRDYIE);
}
 
__STATIC_INLINE void LL_RCC_DisableIT_LSERDY(void)
{
  CLEAR_BIT(RCC->CIR, RCC_CIR_LSERDYIE);
}
 
__STATIC_INLINE void LL_RCC_DisableIT_HSIRDY(void)
{
  CLEAR_BIT(RCC->CIR, RCC_CIR_HSIRDYIE);
}
 
__STATIC_INLINE void LL_RCC_DisableIT_HSERDY(void)
{
  CLEAR_BIT(RCC->CIR, RCC_CIR_HSERDYIE);
}
 
__STATIC_INLINE void LL_RCC_DisableIT_PLLRDY(void)
{
  CLEAR_BIT(RCC->CIR, RCC_CIR_PLLRDYIE);
}
 
__STATIC_INLINE uint32_t LL_RCC_IsEnabledIT_LSIRDY(void)
{
  return (READ_BIT(RCC->CIR, RCC_CIR_LSIRDYIE) == (RCC_CIR_LSIRDYIE));
}
 
__STATIC_INLINE uint32_t LL_RCC_IsEnabledIT_LSERDY(void)
{
  return (READ_BIT(RCC->CIR, RCC_CIR_LSERDYIE) == (RCC_CIR_LSERDYIE));
}
 
__STATIC_INLINE uint32_t LL_RCC_IsEnabledIT_HSIRDY(void)
{
  return (READ_BIT(RCC->CIR, RCC_CIR_HSIRDYIE) == (RCC_CIR_HSIRDYIE));
}
 
__STATIC_INLINE uint32_t LL_RCC_IsEnabledIT_HSERDY(void)
{
  return (READ_BIT(RCC->CIR, RCC_CIR_HSERDYIE) == (RCC_CIR_HSERDYIE));
}
 
__STATIC_INLINE uint32_t LL_RCC_IsEnabledIT_PLLRDY(void)
{
  return (READ_BIT(RCC->CIR, RCC_CIR_PLLRDYIE) == (RCC_CIR_PLLRDYIE));
}
 
#if defined(USE_FULL_LL_DRIVER)
ErrorStatus LL_RCC_DeInit(void);
void        LL_RCC_GetSystemClocksFreq(LL_RCC_ClocksTypeDef *RCC_Clocks);
uint32_t    LL_RCC_GetUSARTClockFreq(uint32_t USARTxSource);
#if defined(UART4) || defined(UART5)
uint32_t    LL_RCC_GetUARTClockFreq(uint32_t UARTxSource);
#endif /* UART4 || UART5 */
uint32_t    LL_RCC_GetI2CClockFreq(uint32_t I2CxSource);
#if defined(RCC_CFGR_I2SSRC)
uint32_t    LL_RCC_GetI2SClockFreq(uint32_t I2SxSource);
#endif /* RCC_CFGR_I2SSRC */
#if defined(USB_OTG_FS) || defined(USB)
uint32_t    LL_RCC_GetUSBClockFreq(uint32_t USBxSource);
#endif /* USB_OTG_FS || USB */
#if (defined(RCC_CFGR_ADCPRE) || defined(RCC_CFGR2_ADC1PRES) || defined(RCC_CFGR2_ADCPRE12) || defined(RCC_CFGR2_ADCPRE34))
uint32_t    LL_RCC_GetADCClockFreq(uint32_t ADCxSource);
#endif /*RCC_CFGR_ADCPRE || RCC_CFGR2_ADC1PRES || RCC_CFGR2_ADCPRE12 || RCC_CFGR2_ADCPRE34 */
#if defined(RCC_CFGR_SDPRE)
uint32_t    LL_RCC_GetSDADCClockFreq(uint32_t SDADCxSource);
#endif /*RCC_CFGR_SDPRE */
#if defined(CEC)
uint32_t    LL_RCC_GetCECClockFreq(uint32_t CECxSource);
#endif /* CEC */
#if defined(RCC_CFGR3_TIMSW)
uint32_t    LL_RCC_GetTIMClockFreq(uint32_t TIMxSource);
#endif /*RCC_CFGR3_TIMSW*/
uint32_t    LL_RCC_GetHRTIMClockFreq(uint32_t HRTIMxSource);
#endif /* USE_FULL_LL_DRIVER */
 
#endif /* RCC */
 
#ifdef __cplusplus
}
#endif
 
#endif /* __STM32F3xx_LL_RCC_H */