Controller Area Network. More...

#include <stm32f303xe.h>

Public Attributes
__IO uint32_t	MCR

__IO uint32_t	MSR

__IO uint32_t	TSR

__IO uint32_t	RF0R

__IO uint32_t	RF1R

__IO uint32_t	IER

__IO uint32_t	ESR

__IO uint32_t	BTR

uint32_t	RESERVED0 [88]

CAN_TxMailBox_TypeDef	sTxMailBox [3]

CAN_FIFOMailBox_TypeDef	sFIFOMailBox [2]

uint32_t	RESERVED1 [12]

__IO uint32_t	FMR

__IO uint32_t	FM1R

uint32_t	RESERVED2

__IO uint32_t	FS1R

uint32_t	RESERVED3

__IO uint32_t	FFA1R

uint32_t	RESERVED4

__IO uint32_t	FA1R

uint32_t	RESERVED5 [8]

CAN_FilterRegister_TypeDef	sFilterRegister [28]

Detailed Description

Controller Area Network.

Member Data Documentation

◆ BTR

__IO uint32_t CAN_TypeDef::BTR

CAN bit timing register, Address offset: 0x1C

◆ ESR

__IO uint32_t CAN_TypeDef::ESR

CAN error status register, Address offset: 0x18

◆ FA1R

__IO uint32_t CAN_TypeDef::FA1R

CAN filter activation register, Address offset: 0x21C

◆ FFA1R

__IO uint32_t CAN_TypeDef::FFA1R

CAN filter FIFO assignment register, Address offset: 0x214

◆ FM1R

__IO uint32_t CAN_TypeDef::FM1R

CAN filter mode register, Address offset: 0x204

◆ FMR

__IO uint32_t CAN_TypeDef::FMR

CAN filter master register, Address offset: 0x200

◆ FS1R

__IO uint32_t CAN_TypeDef::FS1R

CAN filter scale register, Address offset: 0x20C

◆ IER

__IO uint32_t CAN_TypeDef::IER

CAN interrupt enable register, Address offset: 0x14

◆ MCR

__IO uint32_t CAN_TypeDef::MCR

CAN master control register, Address offset: 0x00

◆ MSR

__IO uint32_t CAN_TypeDef::MSR

CAN master status register, Address offset: 0x04

◆ RESERVED0

uint32_t CAN_TypeDef::RESERVED0[88]

Reserved, 0x020 - 0x17F

◆ RESERVED1

uint32_t CAN_TypeDef::RESERVED1[12]

Reserved, 0x1D0 - 0x1FF

◆ RESERVED2

uint32_t CAN_TypeDef::RESERVED2

Reserved, 0x208

◆ RESERVED3

uint32_t CAN_TypeDef::RESERVED3

Reserved, 0x210

◆ RESERVED4

uint32_t CAN_TypeDef::RESERVED4

Reserved, 0x218

◆ RESERVED5

uint32_t CAN_TypeDef::RESERVED5[8]

Reserved, 0x220-0x23F

◆ RF0R

__IO uint32_t CAN_TypeDef::RF0R

CAN receive FIFO 0 register, Address offset: 0x0C

◆ RF1R

__IO uint32_t CAN_TypeDef::RF1R

CAN receive FIFO 1 register, Address offset: 0x10

◆ sFIFOMailBox

CAN_FIFOMailBox_TypeDef CAN_TypeDef::sFIFOMailBox[2]

CAN FIFO MailBox, Address offset: 0x1B0 - 0x1CC

◆ sFilterRegister

CAN_FilterRegister_TypeDef CAN_TypeDef::sFilterRegister[28]

CAN Filter Register, Address offset: 0x240-0x31C

◆ sTxMailBox

CAN_TxMailBox_TypeDef CAN_TypeDef::sTxMailBox[3]

CAN Tx MailBox, Address offset: 0x180 - 0x1AC

◆ TSR

__IO uint32_t CAN_TypeDef::TSR

CAN transmit status register, Address offset: 0x08

The documentation for this struct was generated from the following file:

Drivers/CMSIS/Device/ST/STM32F3xx/Include/stm32f303xe.h

Public Attributes