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stm32f303xe.h
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1
33#ifndef __STM32F303xE_H
34#define __STM32F303xE_H
35
36#ifdef __cplusplus
37 extern "C" {
38#endif /* __cplusplus */
39
47#define __CM4_REV 0x0001U
48#define __MPU_PRESENT 1U
49#define __NVIC_PRIO_BITS 4U
50#define __Vendor_SysTickConfig 0U
51#define __FPU_PRESENT 1U
65typedef enum
66{
67/****** Cortex-M4 Processor Exceptions Numbers ****************************************************************/
68 NonMaskableInt_IRQn = -14,
69 HardFault_IRQn = -13,
70 MemoryManagement_IRQn = -12,
71 BusFault_IRQn = -11,
72 UsageFault_IRQn = -10,
73 SVCall_IRQn = -5,
74 DebugMonitor_IRQn = -4,
75 PendSV_IRQn = -2,
76 SysTick_IRQn = -1,
77/****** STM32 specific Interrupt Numbers **********************************************************************/
78 WWDG_IRQn = 0,
79 PVD_IRQn = 1,
80 TAMP_STAMP_IRQn = 2,
81 RTC_WKUP_IRQn = 3,
82 FLASH_IRQn = 4,
83 RCC_IRQn = 5,
84 EXTI0_IRQn = 6,
85 EXTI1_IRQn = 7,
86 EXTI2_TSC_IRQn = 8,
87 EXTI3_IRQn = 9,
88 EXTI4_IRQn = 10,
89 DMA1_Channel1_IRQn = 11,
90 DMA1_Channel2_IRQn = 12,
91 DMA1_Channel3_IRQn = 13,
92 DMA1_Channel4_IRQn = 14,
93 DMA1_Channel5_IRQn = 15,
94 DMA1_Channel6_IRQn = 16,
95 DMA1_Channel7_IRQn = 17,
96 ADC1_2_IRQn = 18,
97 USB_HP_CAN_TX_IRQn = 19,
98 USB_LP_CAN_RX0_IRQn = 20,
99 CAN_RX1_IRQn = 21,
100 CAN_SCE_IRQn = 22,
101 EXTI9_5_IRQn = 23,
102 TIM1_BRK_TIM15_IRQn = 24,
103 TIM1_UP_TIM16_IRQn = 25,
104 TIM1_TRG_COM_TIM17_IRQn = 26,
105 TIM1_CC_IRQn = 27,
106 TIM2_IRQn = 28,
107 TIM3_IRQn = 29,
108 TIM4_IRQn = 30,
109 I2C1_EV_IRQn = 31,
110 I2C1_ER_IRQn = 32,
111 I2C2_EV_IRQn = 33,
112 I2C2_ER_IRQn = 34,
113 SPI1_IRQn = 35,
114 SPI2_IRQn = 36,
115 USART1_IRQn = 37,
116 USART2_IRQn = 38,
117 USART3_IRQn = 39,
118 EXTI15_10_IRQn = 40,
119 RTC_Alarm_IRQn = 41,
120 USBWakeUp_IRQn = 42,
121 TIM8_BRK_IRQn = 43,
122 TIM8_UP_IRQn = 44,
123 TIM8_TRG_COM_IRQn = 45,
124 TIM8_CC_IRQn = 46,
125 ADC3_IRQn = 47,
126 FMC_IRQn = 48,
127 SPI3_IRQn = 51,
128 UART4_IRQn = 52,
129 UART5_IRQn = 53,
130 TIM6_DAC_IRQn = 54,
131 TIM7_IRQn = 55,
132 DMA2_Channel1_IRQn = 56,
133 DMA2_Channel2_IRQn = 57,
134 DMA2_Channel3_IRQn = 58,
135 DMA2_Channel4_IRQn = 59,
136 DMA2_Channel5_IRQn = 60,
137 ADC4_IRQn = 61,
138 COMP1_2_3_IRQn = 64,
139 COMP4_5_6_IRQn = 65,
140 COMP7_IRQn = 66,
141 I2C3_EV_IRQn = 72,
142 I2C3_ER_IRQn = 73,
143 USB_HP_IRQn = 74,
144 USB_LP_IRQn = 75,
145 USBWakeUp_RMP_IRQn = 76,
146 TIM20_BRK_IRQn = 77,
147 TIM20_UP_IRQn = 78,
148 TIM20_TRG_COM_IRQn = 79,
149 TIM20_CC_IRQn = 80,
150 FPU_IRQn = 81,
151 SPI4_IRQn = 84,
152} IRQn_Type;
153
158#include "core_cm4.h" /* Cortex-M4 processor and core peripherals */
159#include "system_stm32f3xx.h" /* STM32F3xx System Header */
160#include <stdint.h>
161
170typedef struct
171{
172 __IO uint32_t ISR;
173 __IO uint32_t IER;
174 __IO uint32_t CR;
175 __IO uint32_t CFGR;
176 uint32_t RESERVED0;
177 __IO uint32_t SMPR1;
178 __IO uint32_t SMPR2;
179 uint32_t RESERVED1;
180 __IO uint32_t TR1;
181 __IO uint32_t TR2;
182 __IO uint32_t TR3;
183 uint32_t RESERVED2;
184 __IO uint32_t SQR1;
185 __IO uint32_t SQR2;
186 __IO uint32_t SQR3;
187 __IO uint32_t SQR4;
188 __IO uint32_t DR;
189 uint32_t RESERVED3;
190 uint32_t RESERVED4;
191 __IO uint32_t JSQR;
192 uint32_t RESERVED5[4];
193 __IO uint32_t OFR1;
194 __IO uint32_t OFR2;
195 __IO uint32_t OFR3;
196 __IO uint32_t OFR4;
197 uint32_t RESERVED6[4];
198 __IO uint32_t JDR1;
199 __IO uint32_t JDR2;
200 __IO uint32_t JDR3;
201 __IO uint32_t JDR4;
202 uint32_t RESERVED7[4];
203 __IO uint32_t AWD2CR;
204 __IO uint32_t AWD3CR;
205 uint32_t RESERVED8;
206 uint32_t RESERVED9;
207 __IO uint32_t DIFSEL;
208 __IO uint32_t CALFACT;
210} ADC_TypeDef;
211
212typedef struct
213{
214 __IO uint32_t CSR;
215 uint32_t RESERVED;
216 __IO uint32_t CCR;
217 __IO uint32_t CDR;
219} ADC_Common_TypeDef;
220
224typedef struct
225{
226 __IO uint32_t TIR;
227 __IO uint32_t TDTR;
228 __IO uint32_t TDLR;
229 __IO uint32_t TDHR;
230} CAN_TxMailBox_TypeDef;
231
235typedef struct
236{
237 __IO uint32_t RIR;
238 __IO uint32_t RDTR;
239 __IO uint32_t RDLR;
240 __IO uint32_t RDHR;
241} CAN_FIFOMailBox_TypeDef;
242
246typedef struct
247{
248 __IO uint32_t FR1;
249 __IO uint32_t FR2;
250} CAN_FilterRegister_TypeDef;
251
255typedef struct
256{
257 __IO uint32_t MCR;
258 __IO uint32_t MSR;
259 __IO uint32_t TSR;
260 __IO uint32_t RF0R;
261 __IO uint32_t RF1R;
262 __IO uint32_t IER;
263 __IO uint32_t ESR;
264 __IO uint32_t BTR;
265 uint32_t RESERVED0[88];
266 CAN_TxMailBox_TypeDef sTxMailBox[3];
267 CAN_FIFOMailBox_TypeDef sFIFOMailBox[2];
268 uint32_t RESERVED1[12];
269 __IO uint32_t FMR;
270 __IO uint32_t FM1R;
271 uint32_t RESERVED2;
272 __IO uint32_t FS1R;
273 uint32_t RESERVED3;
274 __IO uint32_t FFA1R;
275 uint32_t RESERVED4;
276 __IO uint32_t FA1R;
277 uint32_t RESERVED5[8];
278 CAN_FilterRegister_TypeDef sFilterRegister[28];
279} CAN_TypeDef;
280
284typedef struct
285{
286 __IO uint32_t CSR;
287} COMP_TypeDef;
288
289typedef struct
290{
291 __IO uint32_t CSR;
292} COMP_Common_TypeDef;
293
298typedef struct
299{
300 __IO uint32_t DR;
301 __IO uint8_t IDR;
302 uint8_t RESERVED0;
303 uint16_t RESERVED1;
304 __IO uint32_t CR;
305 uint32_t RESERVED2;
306 __IO uint32_t INIT;
307 __IO uint32_t POL;
308} CRC_TypeDef;
309
314typedef struct
315{
316 __IO uint32_t CR;
317 __IO uint32_t SWTRIGR;
318 __IO uint32_t DHR12R1;
319 __IO uint32_t DHR12L1;
320 __IO uint32_t DHR8R1;
321 __IO uint32_t DHR12R2;
322 __IO uint32_t DHR12L2;
323 __IO uint32_t DHR8R2;
324 __IO uint32_t DHR12RD;
325 __IO uint32_t DHR12LD;
326 __IO uint32_t DHR8RD;
327 __IO uint32_t DOR1;
328 __IO uint32_t DOR2;
329 __IO uint32_t SR;
330} DAC_TypeDef;
331
336typedef struct
337{
338 __IO uint32_t IDCODE;
339 __IO uint32_t CR;
340 __IO uint32_t APB1FZ;
341 __IO uint32_t APB2FZ;
342}DBGMCU_TypeDef;
343
348typedef struct
349{
350 __IO uint32_t CCR;
351 __IO uint32_t CNDTR;
352 __IO uint32_t CPAR;
353 __IO uint32_t CMAR;
354} DMA_Channel_TypeDef;
355
356typedef struct
357{
358 __IO uint32_t ISR;
359 __IO uint32_t IFCR;
360} DMA_TypeDef;
361
366typedef struct
367{
368 __IO uint32_t IMR;
369 __IO uint32_t EMR;
370 __IO uint32_t RTSR;
371 __IO uint32_t FTSR;
372 __IO uint32_t SWIER;
373 __IO uint32_t PR;
374 uint32_t RESERVED1;
375 uint32_t RESERVED2;
376 __IO uint32_t IMR2;
377 __IO uint32_t EMR2;
378 __IO uint32_t RTSR2;
379 __IO uint32_t FTSR2;
380 __IO uint32_t SWIER2;
381 __IO uint32_t PR2;
382}EXTI_TypeDef;
383
388typedef struct
389{
390 __IO uint32_t ACR;
391 __IO uint32_t KEYR;
392 __IO uint32_t OPTKEYR;
393 __IO uint32_t SR;
394 __IO uint32_t CR;
395 __IO uint32_t AR;
396 uint32_t RESERVED;
397 __IO uint32_t OBR;
398 __IO uint32_t WRPR;
400} FLASH_TypeDef;
401
406typedef struct
407{
408 __IO uint32_t BTCR[8];
409} FMC_Bank1_TypeDef;
410
415typedef struct
416{
417 __IO uint32_t BWTR[7];
418} FMC_Bank1E_TypeDef;
419
424typedef struct
425{
426 __IO uint32_t PCR2;
427 __IO uint32_t SR2;
428 __IO uint32_t PMEM2;
429 __IO uint32_t PATT2;
430 uint32_t RESERVED0;
431 __IO uint32_t ECCR2;
432 uint32_t RESERVED1;
433 uint32_t RESERVED2;
434 __IO uint32_t PCR3;
435 __IO uint32_t SR3;
436 __IO uint32_t PMEM3;
437 __IO uint32_t PATT3;
438 uint32_t RESERVED3;
439 __IO uint32_t ECCR3;
440} FMC_Bank2_3_TypeDef;
441
446typedef struct
447{
448 __IO uint32_t PCR4;
449 __IO uint32_t SR4;
450 __IO uint32_t PMEM4;
451 __IO uint32_t PATT4;
452 __IO uint32_t PIO4;
453} FMC_Bank4_TypeDef;
454
458typedef struct
459{
460 __IO uint16_t RDP;
461 __IO uint16_t USER;
462 __IO uint16_t Data0;
463 __IO uint16_t Data1;
464 __IO uint16_t WRP0;
465 __IO uint16_t WRP1;
466 __IO uint16_t WRP2;
467 __IO uint16_t WRP3;
468} OB_TypeDef;
469
474typedef struct
475{
476 __IO uint32_t MODER;
477 __IO uint32_t OTYPER;
478 __IO uint32_t OSPEEDR;
479 __IO uint32_t PUPDR;
480 __IO uint32_t IDR;
481 __IO uint32_t ODR;
482 __IO uint32_t BSRR;
483 __IO uint32_t LCKR;
484 __IO uint32_t AFR[2];
485 __IO uint32_t BRR;
486}GPIO_TypeDef;
487
492typedef struct
493{
494 __IO uint32_t CSR;
495} OPAMP_TypeDef;
496
501typedef struct
502{
503 __IO uint32_t CFGR1;
504 __IO uint32_t RCR;
505 __IO uint32_t EXTICR[4];
506 __IO uint32_t CFGR2;
507 __IO uint32_t RESERVED0;
508 __IO uint32_t RESERVED1;
509 __IO uint32_t RESERVED2;
510 __IO uint32_t RESERVED4;
511 __IO uint32_t RESERVED5;
512 __IO uint32_t RESERVED6;
513 __IO uint32_t RESERVED7;
514 __IO uint32_t RESERVED8;
515 __IO uint32_t RESERVED9;
516 __IO uint32_t RESERVED10;
517 __IO uint32_t RESERVED11;
518 __IO uint32_t CFGR4;
519 __IO uint32_t RESERVED12;
520 __IO uint32_t RESERVED13;
521} SYSCFG_TypeDef;
522
527typedef struct
528{
529 __IO uint32_t CR1;
530 __IO uint32_t CR2;
531 __IO uint32_t OAR1;
532 __IO uint32_t OAR2;
533 __IO uint32_t TIMINGR;
534 __IO uint32_t TIMEOUTR;
535 __IO uint32_t ISR;
536 __IO uint32_t ICR;
537 __IO uint32_t PECR;
538 __IO uint32_t RXDR;
539 __IO uint32_t TXDR;
540}I2C_TypeDef;
541
546typedef struct
547{
548 __IO uint32_t KR;
549 __IO uint32_t PR;
550 __IO uint32_t RLR;
551 __IO uint32_t SR;
552 __IO uint32_t WINR;
553} IWDG_TypeDef;
554
559typedef struct
560{
561 __IO uint32_t CR;
562 __IO uint32_t CSR;
563} PWR_TypeDef;
564
568typedef struct
569{
570 __IO uint32_t CR;
571 __IO uint32_t CFGR;
572 __IO uint32_t CIR;
573 __IO uint32_t APB2RSTR;
574 __IO uint32_t APB1RSTR;
575 __IO uint32_t AHBENR;
576 __IO uint32_t APB2ENR;
577 __IO uint32_t APB1ENR;
578 __IO uint32_t BDCR;
579 __IO uint32_t CSR;
580 __IO uint32_t AHBRSTR;
581 __IO uint32_t CFGR2;
582 __IO uint32_t CFGR3;
583} RCC_TypeDef;
584
589typedef struct
590{
591 __IO uint32_t TR;
592 __IO uint32_t DR;
593 __IO uint32_t CR;
594 __IO uint32_t ISR;
595 __IO uint32_t PRER;
596 __IO uint32_t WUTR;
597 uint32_t RESERVED0;
598 __IO uint32_t ALRMAR;
599 __IO uint32_t ALRMBR;
600 __IO uint32_t WPR;
601 __IO uint32_t SSR;
602 __IO uint32_t SHIFTR;
603 __IO uint32_t TSTR;
604 __IO uint32_t TSDR;
605 __IO uint32_t TSSSR;
606 __IO uint32_t CALR;
607 __IO uint32_t TAFCR;
608 __IO uint32_t ALRMASSR;
609 __IO uint32_t ALRMBSSR;
610 uint32_t RESERVED7;
611 __IO uint32_t BKP0R;
612 __IO uint32_t BKP1R;
613 __IO uint32_t BKP2R;
614 __IO uint32_t BKP3R;
615 __IO uint32_t BKP4R;
616 __IO uint32_t BKP5R;
617 __IO uint32_t BKP6R;
618 __IO uint32_t BKP7R;
619 __IO uint32_t BKP8R;
620 __IO uint32_t BKP9R;
621 __IO uint32_t BKP10R;
622 __IO uint32_t BKP11R;
623 __IO uint32_t BKP12R;
624 __IO uint32_t BKP13R;
625 __IO uint32_t BKP14R;
626 __IO uint32_t BKP15R;
627} RTC_TypeDef;
628
629
634typedef struct
635{
636 __IO uint32_t CR1;
637 __IO uint32_t CR2;
638 __IO uint32_t SR;
639 __IO uint32_t DR;
640 __IO uint32_t CRCPR;
641 __IO uint32_t RXCRCR;
642 __IO uint32_t TXCRCR;
643 __IO uint32_t I2SCFGR;
644 __IO uint32_t I2SPR;
645} SPI_TypeDef;
646
650typedef struct
651{
652 __IO uint32_t CR1;
653 __IO uint32_t CR2;
654 __IO uint32_t SMCR;
655 __IO uint32_t DIER;
656 __IO uint32_t SR;
657 __IO uint32_t EGR;
658 __IO uint32_t CCMR1;
659 __IO uint32_t CCMR2;
660 __IO uint32_t CCER;
661 __IO uint32_t CNT;
662 __IO uint32_t PSC;
663 __IO uint32_t ARR;
664 __IO uint32_t RCR;
665 __IO uint32_t CCR1;
666 __IO uint32_t CCR2;
667 __IO uint32_t CCR3;
668 __IO uint32_t CCR4;
669 __IO uint32_t BDTR;
670 __IO uint32_t DCR;
671 __IO uint32_t DMAR;
672 __IO uint32_t OR;
673 __IO uint32_t CCMR3;
674 __IO uint32_t CCR5;
675 __IO uint32_t CCR6;
676} TIM_TypeDef;
677
681typedef struct
682{
683 __IO uint32_t CR;
684 __IO uint32_t IER;
685 __IO uint32_t ICR;
686 __IO uint32_t ISR;
687 __IO uint32_t IOHCR;
688 uint32_t RESERVED1;
689 __IO uint32_t IOASCR;
690 uint32_t RESERVED2;
691 __IO uint32_t IOSCR;
692 uint32_t RESERVED3;
693 __IO uint32_t IOCCR;
694 uint32_t RESERVED4;
695 __IO uint32_t IOGCSR;
696 __IO uint32_t IOGXCR[8];
697} TSC_TypeDef;
698
703typedef struct
704{
705 __IO uint32_t CR1;
706 __IO uint32_t CR2;
707 __IO uint32_t CR3;
708 __IO uint32_t BRR;
709 __IO uint32_t GTPR;
710 __IO uint32_t RTOR;
711 __IO uint32_t RQR;
712 __IO uint32_t ISR;
713 __IO uint32_t ICR;
714 __IO uint16_t RDR;
715 uint16_t RESERVED1;
716 __IO uint16_t TDR;
717 uint16_t RESERVED2;
718} USART_TypeDef;
719
724typedef struct
725{
726 __IO uint16_t EP0R;
727 __IO uint16_t RESERVED0;
728 __IO uint16_t EP1R;
729 __IO uint16_t RESERVED1;
730 __IO uint16_t EP2R;
731 __IO uint16_t RESERVED2;
732 __IO uint16_t EP3R;
733 __IO uint16_t RESERVED3;
734 __IO uint16_t EP4R;
735 __IO uint16_t RESERVED4;
736 __IO uint16_t EP5R;
737 __IO uint16_t RESERVED5;
738 __IO uint16_t EP6R;
739 __IO uint16_t RESERVED6;
740 __IO uint16_t EP7R;
741 __IO uint16_t RESERVED7[17];
742 __IO uint16_t CNTR;
743 __IO uint16_t RESERVED8;
744 __IO uint16_t ISTR;
745 __IO uint16_t RESERVED9;
746 __IO uint16_t FNR;
747 __IO uint16_t RESERVEDA;
748 __IO uint16_t DADDR;
749 __IO uint16_t RESERVEDB;
750 __IO uint16_t BTABLE;
751 __IO uint16_t RESERVEDC;
752 __IO uint16_t LPMCSR;
753 __IO uint16_t RESERVEDD;
754} USB_TypeDef;
755
759typedef struct
760{
761 __IO uint32_t CR;
762 __IO uint32_t CFR;
763 __IO uint32_t SR;
764} WWDG_TypeDef;
765
774#define FLASH_BASE 0x08000000UL
775#define CCMDATARAM_BASE 0x10000000UL
776#define SRAM_BASE 0x20000000UL
777#define PERIPH_BASE 0x40000000UL
778#define FMC_BASE 0x60000000UL
779#define FMC_R_BASE 0xA0000000UL
781#define SRAM_BB_BASE 0x22000000UL
782#define PERIPH_BB_BASE 0x42000000UL
786#define APB1PERIPH_BASE PERIPH_BASE
787#define APB2PERIPH_BASE (PERIPH_BASE + 0x00010000UL)
788#define AHB1PERIPH_BASE (PERIPH_BASE + 0x00020000UL)
789#define AHB2PERIPH_BASE (PERIPH_BASE + 0x08000000UL)
790#define AHB3PERIPH_BASE (PERIPH_BASE + 0x10000000UL)
791
793#define TIM2_BASE (APB1PERIPH_BASE + 0x00000000UL)
794#define TIM3_BASE (APB1PERIPH_BASE + 0x00000400UL)
795#define TIM4_BASE (APB1PERIPH_BASE + 0x00000800UL)
796#define TIM6_BASE (APB1PERIPH_BASE + 0x00001000UL)
797#define TIM7_BASE (APB1PERIPH_BASE + 0x00001400UL)
798#define RTC_BASE (APB1PERIPH_BASE + 0x00002800UL)
799#define WWDG_BASE (APB1PERIPH_BASE + 0x00002C00UL)
800#define IWDG_BASE (APB1PERIPH_BASE + 0x00003000UL)
801#define I2S2ext_BASE (APB1PERIPH_BASE + 0x00003400UL)
802#define SPI2_BASE (APB1PERIPH_BASE + 0x00003800UL)
803#define SPI3_BASE (APB1PERIPH_BASE + 0x00003C00UL)
804#define I2S3ext_BASE (APB1PERIPH_BASE + 0x00004000UL)
805#define USART2_BASE (APB1PERIPH_BASE + 0x00004400UL)
806#define USART3_BASE (APB1PERIPH_BASE + 0x00004800UL)
807#define UART4_BASE (APB1PERIPH_BASE + 0x00004C00UL)
808#define UART5_BASE (APB1PERIPH_BASE + 0x00005000UL)
809#define I2C1_BASE (APB1PERIPH_BASE + 0x00005400UL)
810#define I2C2_BASE (APB1PERIPH_BASE + 0x00005800UL)
811#define USB_BASE (APB1PERIPH_BASE + 0x00005C00UL)
812#define USB_PMAADDR (APB1PERIPH_BASE + 0x00006000UL)
813#define CAN_BASE (APB1PERIPH_BASE + 0x00006400UL)
814#define PWR_BASE (APB1PERIPH_BASE + 0x00007000UL)
815#define DAC1_BASE (APB1PERIPH_BASE + 0x00007400UL)
816#define DAC_BASE DAC1_BASE
817#define I2C3_BASE (APB1PERIPH_BASE + 0x00007800UL)
818
820#define SYSCFG_BASE (APB2PERIPH_BASE + 0x00000000UL)
821#define COMP1_BASE (APB2PERIPH_BASE + 0x0000001CUL)
822#define COMP2_BASE (APB2PERIPH_BASE + 0x00000020UL)
823#define COMP3_BASE (APB2PERIPH_BASE + 0x00000024UL)
824#define COMP4_BASE (APB2PERIPH_BASE + 0x00000028UL)
825#define COMP5_BASE (APB2PERIPH_BASE + 0x0000002CUL)
826#define COMP6_BASE (APB2PERIPH_BASE + 0x00000030UL)
827#define COMP7_BASE (APB2PERIPH_BASE + 0x00000034UL)
828#define COMP_BASE COMP1_BASE
829#define OPAMP1_BASE (APB2PERIPH_BASE + 0x00000038UL)
830#define OPAMP2_BASE (APB2PERIPH_BASE + 0x0000003CUL)
831#define OPAMP3_BASE (APB2PERIPH_BASE + 0x00000040UL)
832#define OPAMP4_BASE (APB2PERIPH_BASE + 0x00000044UL)
833#define OPAMP_BASE OPAMP1_BASE
834#define EXTI_BASE (APB2PERIPH_BASE + 0x00000400UL)
835#define TIM1_BASE (APB2PERIPH_BASE + 0x00002C00UL)
836#define SPI1_BASE (APB2PERIPH_BASE + 0x00003000UL)
837#define TIM8_BASE (APB2PERIPH_BASE + 0x00003400UL)
838#define USART1_BASE (APB2PERIPH_BASE + 0x00003800UL)
839#define SPI4_BASE (APB2PERIPH_BASE + 0x00003C00UL)
840#define TIM15_BASE (APB2PERIPH_BASE + 0x00004000UL)
841#define TIM16_BASE (APB2PERIPH_BASE + 0x00004400UL)
842#define TIM17_BASE (APB2PERIPH_BASE + 0x00004800UL)
843#define TIM20_BASE (APB2PERIPH_BASE + 0x00005000UL)
844
846#define DMA1_BASE (AHB1PERIPH_BASE + 0x00000000UL)
847#define DMA1_Channel1_BASE (AHB1PERIPH_BASE + 0x00000008UL)
848#define DMA1_Channel2_BASE (AHB1PERIPH_BASE + 0x0000001CUL)
849#define DMA1_Channel3_BASE (AHB1PERIPH_BASE + 0x00000030UL)
850#define DMA1_Channel4_BASE (AHB1PERIPH_BASE + 0x00000044UL)
851#define DMA1_Channel5_BASE (AHB1PERIPH_BASE + 0x00000058UL)
852#define DMA1_Channel6_BASE (AHB1PERIPH_BASE + 0x0000006CUL)
853#define DMA1_Channel7_BASE (AHB1PERIPH_BASE + 0x00000080UL)
854#define DMA2_BASE (AHB1PERIPH_BASE + 0x00000400UL)
855#define DMA2_Channel1_BASE (AHB1PERIPH_BASE + 0x00000408UL)
856#define DMA2_Channel2_BASE (AHB1PERIPH_BASE + 0x0000041CUL)
857#define DMA2_Channel3_BASE (AHB1PERIPH_BASE + 0x00000430UL)
858#define DMA2_Channel4_BASE (AHB1PERIPH_BASE + 0x00000444UL)
859#define DMA2_Channel5_BASE (AHB1PERIPH_BASE + 0x00000458UL)
860#define RCC_BASE (AHB1PERIPH_BASE + 0x00001000UL)
861#define FLASH_R_BASE (AHB1PERIPH_BASE + 0x00002000UL)
862#define OB_BASE 0x1FFFF800UL
863#define FLASHSIZE_BASE 0x1FFFF7CCUL
864#define UID_BASE 0x1FFFF7ACUL
865#define CRC_BASE (AHB1PERIPH_BASE + 0x00003000UL)
866#define TSC_BASE (AHB1PERIPH_BASE + 0x00004000UL)
867
869#define GPIOA_BASE (AHB2PERIPH_BASE + 0x00000000UL)
870#define GPIOB_BASE (AHB2PERIPH_BASE + 0x00000400UL)
871#define GPIOC_BASE (AHB2PERIPH_BASE + 0x00000800UL)
872#define GPIOD_BASE (AHB2PERIPH_BASE + 0x00000C00UL)
873#define GPIOE_BASE (AHB2PERIPH_BASE + 0x00001000UL)
874#define GPIOF_BASE (AHB2PERIPH_BASE + 0x00001400UL)
875#define GPIOG_BASE (AHB2PERIPH_BASE + 0x00001800UL)
876#define GPIOH_BASE (AHB2PERIPH_BASE + 0x00001C00UL)
877
879#define ADC1_BASE (AHB3PERIPH_BASE + 0x00000000UL)
880#define ADC2_BASE (AHB3PERIPH_BASE + 0x00000100UL)
881#define ADC1_2_COMMON_BASE (AHB3PERIPH_BASE + 0x00000300UL)
882#define ADC3_BASE (AHB3PERIPH_BASE + 0x00000400UL)
883#define ADC4_BASE (AHB3PERIPH_BASE + 0x00000500UL)
884#define ADC3_4_COMMON_BASE (AHB3PERIPH_BASE + 0x00000700UL)
885
887#define FMC_BANK1 (FMC_BASE)
888#define FMC_BANK1_1 (FMC_BANK1)
889#define FMC_BANK1_2 (FMC_BANK1 + 0x04000000UL)
890#define FMC_BANK1_3 (FMC_BANK1 + 0x08000000UL)
891#define FMC_BANK1_4 (FMC_BANK1 + 0x0C000000UL)
893#define FMC_BANK2 (FMC_BASE + 0x10000000UL)
894#define FMC_BANK3 (FMC_BASE + 0x20000000UL)
895#define FMC_BANK4 (FMC_BASE + 0x30000000UL)
898#define FMC_Bank1_R_BASE (FMC_R_BASE + 0x0000UL)
899#define FMC_Bank1E_R_BASE (FMC_R_BASE + 0x0104UL)
900#define FMC_Bank2_3_R_BASE (FMC_R_BASE + 0x0060UL)
901#define FMC_Bank4_R_BASE (FMC_R_BASE + 0x00A0UL)
902
903#define DBGMCU_BASE 0xE0042000UL
911#define TIM2 ((TIM_TypeDef *) TIM2_BASE)
912#define TIM3 ((TIM_TypeDef *) TIM3_BASE)
913#define TIM4 ((TIM_TypeDef *) TIM4_BASE)
914#define TIM6 ((TIM_TypeDef *) TIM6_BASE)
915#define TIM7 ((TIM_TypeDef *) TIM7_BASE)
916#define RTC ((RTC_TypeDef *) RTC_BASE)
917#define WWDG ((WWDG_TypeDef *) WWDG_BASE)
918#define IWDG ((IWDG_TypeDef *) IWDG_BASE)
919#define I2S2ext ((SPI_TypeDef *) I2S2ext_BASE)
920#define SPI2 ((SPI_TypeDef *) SPI2_BASE)
921#define SPI3 ((SPI_TypeDef *) SPI3_BASE)
922#define I2S3ext ((SPI_TypeDef *) I2S3ext_BASE)
923#define USART2 ((USART_TypeDef *) USART2_BASE)
924#define USART3 ((USART_TypeDef *) USART3_BASE)
925#define UART4 ((USART_TypeDef *) UART4_BASE)
926#define UART5 ((USART_TypeDef *) UART5_BASE)
927#define I2C1 ((I2C_TypeDef *) I2C1_BASE)
928#define I2C2 ((I2C_TypeDef *) I2C2_BASE)
929#define I2C3 ((I2C_TypeDef *) I2C3_BASE)
930#define CAN ((CAN_TypeDef *) CAN_BASE)
931#define PWR ((PWR_TypeDef *) PWR_BASE)
932#define DAC ((DAC_TypeDef *) DAC_BASE)
933#define DAC1 ((DAC_TypeDef *) DAC1_BASE)
934#define COMP1 ((COMP_TypeDef *) COMP1_BASE)
935#define COMP2 ((COMP_TypeDef *) COMP2_BASE)
936#define COMP12_COMMON ((COMP_Common_TypeDef *) COMP2_BASE)
937#define COMP3 ((COMP_TypeDef *) COMP3_BASE)
938#define COMP4 ((COMP_TypeDef *) COMP4_BASE)
939#define COMP34_COMMON ((COMP_Common_TypeDef *) COMP4_BASE)
940#define COMP5 ((COMP_TypeDef *) COMP5_BASE)
941#define COMP6 ((COMP_TypeDef *) COMP6_BASE)
942#define COMP56_COMMON ((COMP_Common_TypeDef *) COMP6_BASE)
943#define COMP7 ((COMP_TypeDef *) COMP7_BASE)
944/* Legacy define */
945#define COMP ((COMP_TypeDef *) COMP_BASE)
946#define OPAMP1 ((OPAMP_TypeDef *) OPAMP1_BASE)
947#define OPAMP ((OPAMP_TypeDef *) OPAMP_BASE)
948#define OPAMP2 ((OPAMP_TypeDef *) OPAMP2_BASE)
949#define OPAMP3 ((OPAMP_TypeDef *) OPAMP3_BASE)
950#define OPAMP4 ((OPAMP_TypeDef *) OPAMP4_BASE)
951#define SYSCFG ((SYSCFG_TypeDef *) SYSCFG_BASE)
952#define EXTI ((EXTI_TypeDef *) EXTI_BASE)
953#define TIM1 ((TIM_TypeDef *) TIM1_BASE)
954#define SPI1 ((SPI_TypeDef *) SPI1_BASE)
955#define TIM8 ((TIM_TypeDef *) TIM8_BASE)
956#define USART1 ((USART_TypeDef *) USART1_BASE)
957#define SPI4 ((SPI_TypeDef *) SPI4_BASE)
958#define TIM15 ((TIM_TypeDef *) TIM15_BASE)
959#define TIM16 ((TIM_TypeDef *) TIM16_BASE)
960#define TIM17 ((TIM_TypeDef *) TIM17_BASE)
961#define TIM20 ((TIM_TypeDef *) TIM20_BASE)
962#define DBGMCU ((DBGMCU_TypeDef *) DBGMCU_BASE)
963#define DMA1 ((DMA_TypeDef *) DMA1_BASE)
964#define DMA1_Channel1 ((DMA_Channel_TypeDef *) DMA1_Channel1_BASE)
965#define DMA1_Channel2 ((DMA_Channel_TypeDef *) DMA1_Channel2_BASE)
966#define DMA1_Channel3 ((DMA_Channel_TypeDef *) DMA1_Channel3_BASE)
967#define DMA1_Channel4 ((DMA_Channel_TypeDef *) DMA1_Channel4_BASE)
968#define DMA1_Channel5 ((DMA_Channel_TypeDef *) DMA1_Channel5_BASE)
969#define DMA1_Channel6 ((DMA_Channel_TypeDef *) DMA1_Channel6_BASE)
970#define DMA1_Channel7 ((DMA_Channel_TypeDef *) DMA1_Channel7_BASE)
971#define DMA2 ((DMA_TypeDef *) DMA2_BASE)
972#define DMA2_Channel1 ((DMA_Channel_TypeDef *) DMA2_Channel1_BASE)
973#define DMA2_Channel2 ((DMA_Channel_TypeDef *) DMA2_Channel2_BASE)
974#define DMA2_Channel3 ((DMA_Channel_TypeDef *) DMA2_Channel3_BASE)
975#define DMA2_Channel4 ((DMA_Channel_TypeDef *) DMA2_Channel4_BASE)
976#define DMA2_Channel5 ((DMA_Channel_TypeDef *) DMA2_Channel5_BASE)
977#define RCC ((RCC_TypeDef *) RCC_BASE)
978#define FLASH ((FLASH_TypeDef *) FLASH_R_BASE)
979#define OB ((OB_TypeDef *) OB_BASE)
980#define CRC ((CRC_TypeDef *) CRC_BASE)
981#define TSC ((TSC_TypeDef *) TSC_BASE)
982#define GPIOA ((GPIO_TypeDef *) GPIOA_BASE)
983#define GPIOB ((GPIO_TypeDef *) GPIOB_BASE)
984#define GPIOC ((GPIO_TypeDef *) GPIOC_BASE)
985#define GPIOD ((GPIO_TypeDef *) GPIOD_BASE)
986#define GPIOE ((GPIO_TypeDef *) GPIOE_BASE)
987#define GPIOF ((GPIO_TypeDef *) GPIOF_BASE)
988#define GPIOG ((GPIO_TypeDef *) GPIOG_BASE)
989#define GPIOH ((GPIO_TypeDef *) GPIOH_BASE)
990#define ADC1 ((ADC_TypeDef *) ADC1_BASE)
991#define ADC2 ((ADC_TypeDef *) ADC2_BASE)
992#define ADC3 ((ADC_TypeDef *) ADC3_BASE)
993#define ADC4 ((ADC_TypeDef *) ADC4_BASE)
994#define ADC12_COMMON ((ADC_Common_TypeDef *) ADC1_2_COMMON_BASE)
995#define ADC34_COMMON ((ADC_Common_TypeDef *) ADC3_4_COMMON_BASE)
996/* Legacy defines */
997#define ADC1_2_COMMON ADC12_COMMON
998#define ADC3_4_COMMON ADC34_COMMON
999#define USB ((USB_TypeDef *) USB_BASE)
1000#define FMC_Bank1 ((FMC_Bank1_TypeDef *) FMC_Bank1_R_BASE)
1001#define FMC_Bank1E ((FMC_Bank1E_TypeDef *) FMC_Bank1E_R_BASE)
1002#define FMC_Bank2_3 ((FMC_Bank2_3_TypeDef *) FMC_Bank2_3_R_BASE)
1003#define FMC_Bank4 ((FMC_Bank4_TypeDef *) FMC_Bank4_R_BASE)
1004
1016#define LSI_STARTUP_TIME 85U
1026/******************************************************************************/
1027/* Peripheral Registers_Bits_Definition */
1028/******************************************************************************/
1029
1030/******************************************************************************/
1031/* */
1032/* Analog to Digital Converter SAR (ADC) */
1033/* */
1034/******************************************************************************/
1035
1036#define ADC5_V1_1
1038/*
1039 * @brief Specific device feature definitions (not present on all devices in the STM32F3 series)
1040 */
1041#define ADC_MULTIMODE_SUPPORT
1043/******************** Bit definition for ADC_ISR register ********************/
1044#define ADC_ISR_ADRDY_Pos (0U)
1045#define ADC_ISR_ADRDY_Msk (0x1UL << ADC_ISR_ADRDY_Pos)
1046#define ADC_ISR_ADRDY ADC_ISR_ADRDY_Msk
1047#define ADC_ISR_EOSMP_Pos (1U)
1048#define ADC_ISR_EOSMP_Msk (0x1UL << ADC_ISR_EOSMP_Pos)
1049#define ADC_ISR_EOSMP ADC_ISR_EOSMP_Msk
1050#define ADC_ISR_EOC_Pos (2U)
1051#define ADC_ISR_EOC_Msk (0x1UL << ADC_ISR_EOC_Pos)
1052#define ADC_ISR_EOC ADC_ISR_EOC_Msk
1053#define ADC_ISR_EOS_Pos (3U)
1054#define ADC_ISR_EOS_Msk (0x1UL << ADC_ISR_EOS_Pos)
1055#define ADC_ISR_EOS ADC_ISR_EOS_Msk
1056#define ADC_ISR_OVR_Pos (4U)
1057#define ADC_ISR_OVR_Msk (0x1UL << ADC_ISR_OVR_Pos)
1058#define ADC_ISR_OVR ADC_ISR_OVR_Msk
1059#define ADC_ISR_JEOC_Pos (5U)
1060#define ADC_ISR_JEOC_Msk (0x1UL << ADC_ISR_JEOC_Pos)
1061#define ADC_ISR_JEOC ADC_ISR_JEOC_Msk
1062#define ADC_ISR_JEOS_Pos (6U)
1063#define ADC_ISR_JEOS_Msk (0x1UL << ADC_ISR_JEOS_Pos)
1064#define ADC_ISR_JEOS ADC_ISR_JEOS_Msk
1065#define ADC_ISR_AWD1_Pos (7U)
1066#define ADC_ISR_AWD1_Msk (0x1UL << ADC_ISR_AWD1_Pos)
1067#define ADC_ISR_AWD1 ADC_ISR_AWD1_Msk
1068#define ADC_ISR_AWD2_Pos (8U)
1069#define ADC_ISR_AWD2_Msk (0x1UL << ADC_ISR_AWD2_Pos)
1070#define ADC_ISR_AWD2 ADC_ISR_AWD2_Msk
1071#define ADC_ISR_AWD3_Pos (9U)
1072#define ADC_ISR_AWD3_Msk (0x1UL << ADC_ISR_AWD3_Pos)
1073#define ADC_ISR_AWD3 ADC_ISR_AWD3_Msk
1074#define ADC_ISR_JQOVF_Pos (10U)
1075#define ADC_ISR_JQOVF_Msk (0x1UL << ADC_ISR_JQOVF_Pos)
1076#define ADC_ISR_JQOVF ADC_ISR_JQOVF_Msk
1078/* Legacy defines */
1079#define ADC_ISR_ADRD (ADC_ISR_ADRDY)
1080
1081/******************** Bit definition for ADC_IER register ********************/
1082#define ADC_IER_ADRDYIE_Pos (0U)
1083#define ADC_IER_ADRDYIE_Msk (0x1UL << ADC_IER_ADRDYIE_Pos)
1084#define ADC_IER_ADRDYIE ADC_IER_ADRDYIE_Msk
1085#define ADC_IER_EOSMPIE_Pos (1U)
1086#define ADC_IER_EOSMPIE_Msk (0x1UL << ADC_IER_EOSMPIE_Pos)
1087#define ADC_IER_EOSMPIE ADC_IER_EOSMPIE_Msk
1088#define ADC_IER_EOCIE_Pos (2U)
1089#define ADC_IER_EOCIE_Msk (0x1UL << ADC_IER_EOCIE_Pos)
1090#define ADC_IER_EOCIE ADC_IER_EOCIE_Msk
1091#define ADC_IER_EOSIE_Pos (3U)
1092#define ADC_IER_EOSIE_Msk (0x1UL << ADC_IER_EOSIE_Pos)
1093#define ADC_IER_EOSIE ADC_IER_EOSIE_Msk
1094#define ADC_IER_OVRIE_Pos (4U)
1095#define ADC_IER_OVRIE_Msk (0x1UL << ADC_IER_OVRIE_Pos)
1096#define ADC_IER_OVRIE ADC_IER_OVRIE_Msk
1097#define ADC_IER_JEOCIE_Pos (5U)
1098#define ADC_IER_JEOCIE_Msk (0x1UL << ADC_IER_JEOCIE_Pos)
1099#define ADC_IER_JEOCIE ADC_IER_JEOCIE_Msk
1100#define ADC_IER_JEOSIE_Pos (6U)
1101#define ADC_IER_JEOSIE_Msk (0x1UL << ADC_IER_JEOSIE_Pos)
1102#define ADC_IER_JEOSIE ADC_IER_JEOSIE_Msk
1103#define ADC_IER_AWD1IE_Pos (7U)
1104#define ADC_IER_AWD1IE_Msk (0x1UL << ADC_IER_AWD1IE_Pos)
1105#define ADC_IER_AWD1IE ADC_IER_AWD1IE_Msk
1106#define ADC_IER_AWD2IE_Pos (8U)
1107#define ADC_IER_AWD2IE_Msk (0x1UL << ADC_IER_AWD2IE_Pos)
1108#define ADC_IER_AWD2IE ADC_IER_AWD2IE_Msk
1109#define ADC_IER_AWD3IE_Pos (9U)
1110#define ADC_IER_AWD3IE_Msk (0x1UL << ADC_IER_AWD3IE_Pos)
1111#define ADC_IER_AWD3IE ADC_IER_AWD3IE_Msk
1112#define ADC_IER_JQOVFIE_Pos (10U)
1113#define ADC_IER_JQOVFIE_Msk (0x1UL << ADC_IER_JQOVFIE_Pos)
1114#define ADC_IER_JQOVFIE ADC_IER_JQOVFIE_Msk
1116/* Legacy defines */
1117#define ADC_IER_RDY (ADC_IER_ADRDYIE)
1118#define ADC_IER_EOSMP (ADC_IER_EOSMPIE)
1119#define ADC_IER_EOC (ADC_IER_EOCIE)
1120#define ADC_IER_EOS (ADC_IER_EOSIE)
1121#define ADC_IER_OVR (ADC_IER_OVRIE)
1122#define ADC_IER_JEOC (ADC_IER_JEOCIE)
1123#define ADC_IER_JEOS (ADC_IER_JEOSIE)
1124#define ADC_IER_AWD1 (ADC_IER_AWD1IE)
1125#define ADC_IER_AWD2 (ADC_IER_AWD2IE)
1126#define ADC_IER_AWD3 (ADC_IER_AWD3IE)
1127#define ADC_IER_JQOVF (ADC_IER_JQOVFIE)
1128
1129/******************** Bit definition for ADC_CR register ********************/
1130#define ADC_CR_ADEN_Pos (0U)
1131#define ADC_CR_ADEN_Msk (0x1UL << ADC_CR_ADEN_Pos)
1132#define ADC_CR_ADEN ADC_CR_ADEN_Msk
1133#define ADC_CR_ADDIS_Pos (1U)
1134#define ADC_CR_ADDIS_Msk (0x1UL << ADC_CR_ADDIS_Pos)
1135#define ADC_CR_ADDIS ADC_CR_ADDIS_Msk
1136#define ADC_CR_ADSTART_Pos (2U)
1137#define ADC_CR_ADSTART_Msk (0x1UL << ADC_CR_ADSTART_Pos)
1138#define ADC_CR_ADSTART ADC_CR_ADSTART_Msk
1139#define ADC_CR_JADSTART_Pos (3U)
1140#define ADC_CR_JADSTART_Msk (0x1UL << ADC_CR_JADSTART_Pos)
1141#define ADC_CR_JADSTART ADC_CR_JADSTART_Msk
1142#define ADC_CR_ADSTP_Pos (4U)
1143#define ADC_CR_ADSTP_Msk (0x1UL << ADC_CR_ADSTP_Pos)
1144#define ADC_CR_ADSTP ADC_CR_ADSTP_Msk
1145#define ADC_CR_JADSTP_Pos (5U)
1146#define ADC_CR_JADSTP_Msk (0x1UL << ADC_CR_JADSTP_Pos)
1147#define ADC_CR_JADSTP ADC_CR_JADSTP_Msk
1148#define ADC_CR_ADVREGEN_Pos (28U)
1149#define ADC_CR_ADVREGEN_Msk (0x3UL << ADC_CR_ADVREGEN_Pos)
1150#define ADC_CR_ADVREGEN ADC_CR_ADVREGEN_Msk
1151#define ADC_CR_ADVREGEN_0 (0x1UL << ADC_CR_ADVREGEN_Pos)
1152#define ADC_CR_ADVREGEN_1 (0x2UL << ADC_CR_ADVREGEN_Pos)
1153#define ADC_CR_ADCALDIF_Pos (30U)
1154#define ADC_CR_ADCALDIF_Msk (0x1UL << ADC_CR_ADCALDIF_Pos)
1155#define ADC_CR_ADCALDIF ADC_CR_ADCALDIF_Msk
1156#define ADC_CR_ADCAL_Pos (31U)
1157#define ADC_CR_ADCAL_Msk (0x1UL << ADC_CR_ADCAL_Pos)
1158#define ADC_CR_ADCAL ADC_CR_ADCAL_Msk
1160/******************** Bit definition for ADC_CFGR register ******************/
1161#define ADC_CFGR_DMAEN_Pos (0U)
1162#define ADC_CFGR_DMAEN_Msk (0x1UL << ADC_CFGR_DMAEN_Pos)
1163#define ADC_CFGR_DMAEN ADC_CFGR_DMAEN_Msk
1164#define ADC_CFGR_DMACFG_Pos (1U)
1165#define ADC_CFGR_DMACFG_Msk (0x1UL << ADC_CFGR_DMACFG_Pos)
1166#define ADC_CFGR_DMACFG ADC_CFGR_DMACFG_Msk
1168#define ADC_CFGR_RES_Pos (3U)
1169#define ADC_CFGR_RES_Msk (0x3UL << ADC_CFGR_RES_Pos)
1170#define ADC_CFGR_RES ADC_CFGR_RES_Msk
1171#define ADC_CFGR_RES_0 (0x1UL << ADC_CFGR_RES_Pos)
1172#define ADC_CFGR_RES_1 (0x2UL << ADC_CFGR_RES_Pos)
1174#define ADC_CFGR_ALIGN_Pos (5U)
1175#define ADC_CFGR_ALIGN_Msk (0x1UL << ADC_CFGR_ALIGN_Pos)
1176#define ADC_CFGR_ALIGN ADC_CFGR_ALIGN_Msk
1178#define ADC_CFGR_EXTSEL_Pos (6U)
1179#define ADC_CFGR_EXTSEL_Msk (0xFUL << ADC_CFGR_EXTSEL_Pos)
1180#define ADC_CFGR_EXTSEL ADC_CFGR_EXTSEL_Msk
1181#define ADC_CFGR_EXTSEL_0 (0x1UL << ADC_CFGR_EXTSEL_Pos)
1182#define ADC_CFGR_EXTSEL_1 (0x2UL << ADC_CFGR_EXTSEL_Pos)
1183#define ADC_CFGR_EXTSEL_2 (0x4UL << ADC_CFGR_EXTSEL_Pos)
1184#define ADC_CFGR_EXTSEL_3 (0x8UL << ADC_CFGR_EXTSEL_Pos)
1186#define ADC_CFGR_EXTEN_Pos (10U)
1187#define ADC_CFGR_EXTEN_Msk (0x3UL << ADC_CFGR_EXTEN_Pos)
1188#define ADC_CFGR_EXTEN ADC_CFGR_EXTEN_Msk
1189#define ADC_CFGR_EXTEN_0 (0x1UL << ADC_CFGR_EXTEN_Pos)
1190#define ADC_CFGR_EXTEN_1 (0x2UL << ADC_CFGR_EXTEN_Pos)
1192#define ADC_CFGR_OVRMOD_Pos (12U)
1193#define ADC_CFGR_OVRMOD_Msk (0x1UL << ADC_CFGR_OVRMOD_Pos)
1194#define ADC_CFGR_OVRMOD ADC_CFGR_OVRMOD_Msk
1195#define ADC_CFGR_CONT_Pos (13U)
1196#define ADC_CFGR_CONT_Msk (0x1UL << ADC_CFGR_CONT_Pos)
1197#define ADC_CFGR_CONT ADC_CFGR_CONT_Msk
1198#define ADC_CFGR_AUTDLY_Pos (14U)
1199#define ADC_CFGR_AUTDLY_Msk (0x1UL << ADC_CFGR_AUTDLY_Pos)
1200#define ADC_CFGR_AUTDLY ADC_CFGR_AUTDLY_Msk
1202#define ADC_CFGR_DISCEN_Pos (16U)
1203#define ADC_CFGR_DISCEN_Msk (0x1UL << ADC_CFGR_DISCEN_Pos)
1204#define ADC_CFGR_DISCEN ADC_CFGR_DISCEN_Msk
1206#define ADC_CFGR_DISCNUM_Pos (17U)
1207#define ADC_CFGR_DISCNUM_Msk (0x7UL << ADC_CFGR_DISCNUM_Pos)
1208#define ADC_CFGR_DISCNUM ADC_CFGR_DISCNUM_Msk
1209#define ADC_CFGR_DISCNUM_0 (0x1UL << ADC_CFGR_DISCNUM_Pos)
1210#define ADC_CFGR_DISCNUM_1 (0x2UL << ADC_CFGR_DISCNUM_Pos)
1211#define ADC_CFGR_DISCNUM_2 (0x4UL << ADC_CFGR_DISCNUM_Pos)
1213#define ADC_CFGR_JDISCEN_Pos (20U)
1214#define ADC_CFGR_JDISCEN_Msk (0x1UL << ADC_CFGR_JDISCEN_Pos)
1215#define ADC_CFGR_JDISCEN ADC_CFGR_JDISCEN_Msk
1216#define ADC_CFGR_JQM_Pos (21U)
1217#define ADC_CFGR_JQM_Msk (0x1UL << ADC_CFGR_JQM_Pos)
1218#define ADC_CFGR_JQM ADC_CFGR_JQM_Msk
1219#define ADC_CFGR_AWD1SGL_Pos (22U)
1220#define ADC_CFGR_AWD1SGL_Msk (0x1UL << ADC_CFGR_AWD1SGL_Pos)
1221#define ADC_CFGR_AWD1SGL ADC_CFGR_AWD1SGL_Msk
1222#define ADC_CFGR_AWD1EN_Pos (23U)
1223#define ADC_CFGR_AWD1EN_Msk (0x1UL << ADC_CFGR_AWD1EN_Pos)
1224#define ADC_CFGR_AWD1EN ADC_CFGR_AWD1EN_Msk
1225#define ADC_CFGR_JAWD1EN_Pos (24U)
1226#define ADC_CFGR_JAWD1EN_Msk (0x1UL << ADC_CFGR_JAWD1EN_Pos)
1227#define ADC_CFGR_JAWD1EN ADC_CFGR_JAWD1EN_Msk
1228#define ADC_CFGR_JAUTO_Pos (25U)
1229#define ADC_CFGR_JAUTO_Msk (0x1UL << ADC_CFGR_JAUTO_Pos)
1230#define ADC_CFGR_JAUTO ADC_CFGR_JAUTO_Msk
1232#define ADC_CFGR_AWD1CH_Pos (26U)
1233#define ADC_CFGR_AWD1CH_Msk (0x1FUL << ADC_CFGR_AWD1CH_Pos)
1234#define ADC_CFGR_AWD1CH ADC_CFGR_AWD1CH_Msk
1235#define ADC_CFGR_AWD1CH_0 (0x01UL << ADC_CFGR_AWD1CH_Pos)
1236#define ADC_CFGR_AWD1CH_1 (0x02UL << ADC_CFGR_AWD1CH_Pos)
1237#define ADC_CFGR_AWD1CH_2 (0x04UL << ADC_CFGR_AWD1CH_Pos)
1238#define ADC_CFGR_AWD1CH_3 (0x08UL << ADC_CFGR_AWD1CH_Pos)
1239#define ADC_CFGR_AWD1CH_4 (0x10UL << ADC_CFGR_AWD1CH_Pos)
1241/* Legacy defines */
1242#define ADC_CFGR_AUTOFF_Pos (15U)
1243#define ADC_CFGR_AUTOFF_Msk (0x1UL << ADC_CFGR_AUTOFF_Pos)
1244#define ADC_CFGR_AUTOFF ADC_CFGR_AUTOFF_Msk
1246/******************** Bit definition for ADC_SMPR1 register *****************/
1247#define ADC_SMPR1_SMP0_Pos (0U)
1248#define ADC_SMPR1_SMP0_Msk (0x7UL << ADC_SMPR1_SMP0_Pos)
1249#define ADC_SMPR1_SMP0 ADC_SMPR1_SMP0_Msk
1250#define ADC_SMPR1_SMP0_0 (0x1UL << ADC_SMPR1_SMP0_Pos)
1251#define ADC_SMPR1_SMP0_1 (0x2UL << ADC_SMPR1_SMP0_Pos)
1252#define ADC_SMPR1_SMP0_2 (0x4UL << ADC_SMPR1_SMP0_Pos)
1254#define ADC_SMPR1_SMP1_Pos (3U)
1255#define ADC_SMPR1_SMP1_Msk (0x7UL << ADC_SMPR1_SMP1_Pos)
1256#define ADC_SMPR1_SMP1 ADC_SMPR1_SMP1_Msk
1257#define ADC_SMPR1_SMP1_0 (0x1UL << ADC_SMPR1_SMP1_Pos)
1258#define ADC_SMPR1_SMP1_1 (0x2UL << ADC_SMPR1_SMP1_Pos)
1259#define ADC_SMPR1_SMP1_2 (0x4UL << ADC_SMPR1_SMP1_Pos)
1261#define ADC_SMPR1_SMP2_Pos (6U)
1262#define ADC_SMPR1_SMP2_Msk (0x7UL << ADC_SMPR1_SMP2_Pos)
1263#define ADC_SMPR1_SMP2 ADC_SMPR1_SMP2_Msk
1264#define ADC_SMPR1_SMP2_0 (0x1UL << ADC_SMPR1_SMP2_Pos)
1265#define ADC_SMPR1_SMP2_1 (0x2UL << ADC_SMPR1_SMP2_Pos)
1266#define ADC_SMPR1_SMP2_2 (0x4UL << ADC_SMPR1_SMP2_Pos)
1268#define ADC_SMPR1_SMP3_Pos (9U)
1269#define ADC_SMPR1_SMP3_Msk (0x7UL << ADC_SMPR1_SMP3_Pos)
1270#define ADC_SMPR1_SMP3 ADC_SMPR1_SMP3_Msk
1271#define ADC_SMPR1_SMP3_0 (0x1UL << ADC_SMPR1_SMP3_Pos)
1272#define ADC_SMPR1_SMP3_1 (0x2UL << ADC_SMPR1_SMP3_Pos)
1273#define ADC_SMPR1_SMP3_2 (0x4UL << ADC_SMPR1_SMP3_Pos)
1275#define ADC_SMPR1_SMP4_Pos (12U)
1276#define ADC_SMPR1_SMP4_Msk (0x7UL << ADC_SMPR1_SMP4_Pos)
1277#define ADC_SMPR1_SMP4 ADC_SMPR1_SMP4_Msk
1278#define ADC_SMPR1_SMP4_0 (0x1UL << ADC_SMPR1_SMP4_Pos)
1279#define ADC_SMPR1_SMP4_1 (0x2UL << ADC_SMPR1_SMP4_Pos)
1280#define ADC_SMPR1_SMP4_2 (0x4UL << ADC_SMPR1_SMP4_Pos)
1282#define ADC_SMPR1_SMP5_Pos (15U)
1283#define ADC_SMPR1_SMP5_Msk (0x7UL << ADC_SMPR1_SMP5_Pos)
1284#define ADC_SMPR1_SMP5 ADC_SMPR1_SMP5_Msk
1285#define ADC_SMPR1_SMP5_0 (0x1UL << ADC_SMPR1_SMP5_Pos)
1286#define ADC_SMPR1_SMP5_1 (0x2UL << ADC_SMPR1_SMP5_Pos)
1287#define ADC_SMPR1_SMP5_2 (0x4UL << ADC_SMPR1_SMP5_Pos)
1289#define ADC_SMPR1_SMP6_Pos (18U)
1290#define ADC_SMPR1_SMP6_Msk (0x7UL << ADC_SMPR1_SMP6_Pos)
1291#define ADC_SMPR1_SMP6 ADC_SMPR1_SMP6_Msk
1292#define ADC_SMPR1_SMP6_0 (0x1UL << ADC_SMPR1_SMP6_Pos)
1293#define ADC_SMPR1_SMP6_1 (0x2UL << ADC_SMPR1_SMP6_Pos)
1294#define ADC_SMPR1_SMP6_2 (0x4UL << ADC_SMPR1_SMP6_Pos)
1296#define ADC_SMPR1_SMP7_Pos (21U)
1297#define ADC_SMPR1_SMP7_Msk (0x7UL << ADC_SMPR1_SMP7_Pos)
1298#define ADC_SMPR1_SMP7 ADC_SMPR1_SMP7_Msk
1299#define ADC_SMPR1_SMP7_0 (0x1UL << ADC_SMPR1_SMP7_Pos)
1300#define ADC_SMPR1_SMP7_1 (0x2UL << ADC_SMPR1_SMP7_Pos)
1301#define ADC_SMPR1_SMP7_2 (0x4UL << ADC_SMPR1_SMP7_Pos)
1303#define ADC_SMPR1_SMP8_Pos (24U)
1304#define ADC_SMPR1_SMP8_Msk (0x7UL << ADC_SMPR1_SMP8_Pos)
1305#define ADC_SMPR1_SMP8 ADC_SMPR1_SMP8_Msk
1306#define ADC_SMPR1_SMP8_0 (0x1UL << ADC_SMPR1_SMP8_Pos)
1307#define ADC_SMPR1_SMP8_1 (0x2UL << ADC_SMPR1_SMP8_Pos)
1308#define ADC_SMPR1_SMP8_2 (0x4UL << ADC_SMPR1_SMP8_Pos)
1310#define ADC_SMPR1_SMP9_Pos (27U)
1311#define ADC_SMPR1_SMP9_Msk (0x7UL << ADC_SMPR1_SMP9_Pos)
1312#define ADC_SMPR1_SMP9 ADC_SMPR1_SMP9_Msk
1313#define ADC_SMPR1_SMP9_0 (0x1UL << ADC_SMPR1_SMP9_Pos)
1314#define ADC_SMPR1_SMP9_1 (0x2UL << ADC_SMPR1_SMP9_Pos)
1315#define ADC_SMPR1_SMP9_2 (0x4UL << ADC_SMPR1_SMP9_Pos)
1317/******************** Bit definition for ADC_SMPR2 register *****************/
1318#define ADC_SMPR2_SMP10_Pos (0U)
1319#define ADC_SMPR2_SMP10_Msk (0x7UL << ADC_SMPR2_SMP10_Pos)
1320#define ADC_SMPR2_SMP10 ADC_SMPR2_SMP10_Msk
1321#define ADC_SMPR2_SMP10_0 (0x1UL << ADC_SMPR2_SMP10_Pos)
1322#define ADC_SMPR2_SMP10_1 (0x2UL << ADC_SMPR2_SMP10_Pos)
1323#define ADC_SMPR2_SMP10_2 (0x4UL << ADC_SMPR2_SMP10_Pos)
1325#define ADC_SMPR2_SMP11_Pos (3U)
1326#define ADC_SMPR2_SMP11_Msk (0x7UL << ADC_SMPR2_SMP11_Pos)
1327#define ADC_SMPR2_SMP11 ADC_SMPR2_SMP11_Msk
1328#define ADC_SMPR2_SMP11_0 (0x1UL << ADC_SMPR2_SMP11_Pos)
1329#define ADC_SMPR2_SMP11_1 (0x2UL << ADC_SMPR2_SMP11_Pos)
1330#define ADC_SMPR2_SMP11_2 (0x4UL << ADC_SMPR2_SMP11_Pos)
1332#define ADC_SMPR2_SMP12_Pos (6U)
1333#define ADC_SMPR2_SMP12_Msk (0x7UL << ADC_SMPR2_SMP12_Pos)
1334#define ADC_SMPR2_SMP12 ADC_SMPR2_SMP12_Msk
1335#define ADC_SMPR2_SMP12_0 (0x1UL << ADC_SMPR2_SMP12_Pos)
1336#define ADC_SMPR2_SMP12_1 (0x2UL << ADC_SMPR2_SMP12_Pos)
1337#define ADC_SMPR2_SMP12_2 (0x4UL << ADC_SMPR2_SMP12_Pos)
1339#define ADC_SMPR2_SMP13_Pos (9U)
1340#define ADC_SMPR2_SMP13_Msk (0x7UL << ADC_SMPR2_SMP13_Pos)
1341#define ADC_SMPR2_SMP13 ADC_SMPR2_SMP13_Msk
1342#define ADC_SMPR2_SMP13_0 (0x1UL << ADC_SMPR2_SMP13_Pos)
1343#define ADC_SMPR2_SMP13_1 (0x2UL << ADC_SMPR2_SMP13_Pos)
1344#define ADC_SMPR2_SMP13_2 (0x4UL << ADC_SMPR2_SMP13_Pos)
1346#define ADC_SMPR2_SMP14_Pos (12U)
1347#define ADC_SMPR2_SMP14_Msk (0x7UL << ADC_SMPR2_SMP14_Pos)
1348#define ADC_SMPR2_SMP14 ADC_SMPR2_SMP14_Msk
1349#define ADC_SMPR2_SMP14_0 (0x1UL << ADC_SMPR2_SMP14_Pos)
1350#define ADC_SMPR2_SMP14_1 (0x2UL << ADC_SMPR2_SMP14_Pos)
1351#define ADC_SMPR2_SMP14_2 (0x4UL << ADC_SMPR2_SMP14_Pos)
1353#define ADC_SMPR2_SMP15_Pos (15U)
1354#define ADC_SMPR2_SMP15_Msk (0x7UL << ADC_SMPR2_SMP15_Pos)
1355#define ADC_SMPR2_SMP15 ADC_SMPR2_SMP15_Msk
1356#define ADC_SMPR2_SMP15_0 (0x1UL << ADC_SMPR2_SMP15_Pos)
1357#define ADC_SMPR2_SMP15_1 (0x2UL << ADC_SMPR2_SMP15_Pos)
1358#define ADC_SMPR2_SMP15_2 (0x4UL << ADC_SMPR2_SMP15_Pos)
1360#define ADC_SMPR2_SMP16_Pos (18U)
1361#define ADC_SMPR2_SMP16_Msk (0x7UL << ADC_SMPR2_SMP16_Pos)
1362#define ADC_SMPR2_SMP16 ADC_SMPR2_SMP16_Msk
1363#define ADC_SMPR2_SMP16_0 (0x1UL << ADC_SMPR2_SMP16_Pos)
1364#define ADC_SMPR2_SMP16_1 (0x2UL << ADC_SMPR2_SMP16_Pos)
1365#define ADC_SMPR2_SMP16_2 (0x4UL << ADC_SMPR2_SMP16_Pos)
1367#define ADC_SMPR2_SMP17_Pos (21U)
1368#define ADC_SMPR2_SMP17_Msk (0x7UL << ADC_SMPR2_SMP17_Pos)
1369#define ADC_SMPR2_SMP17 ADC_SMPR2_SMP17_Msk
1370#define ADC_SMPR2_SMP17_0 (0x1UL << ADC_SMPR2_SMP17_Pos)
1371#define ADC_SMPR2_SMP17_1 (0x2UL << ADC_SMPR2_SMP17_Pos)
1372#define ADC_SMPR2_SMP17_2 (0x4UL << ADC_SMPR2_SMP17_Pos)
1374#define ADC_SMPR2_SMP18_Pos (24U)
1375#define ADC_SMPR2_SMP18_Msk (0x7UL << ADC_SMPR2_SMP18_Pos)
1376#define ADC_SMPR2_SMP18 ADC_SMPR2_SMP18_Msk
1377#define ADC_SMPR2_SMP18_0 (0x1UL << ADC_SMPR2_SMP18_Pos)
1378#define ADC_SMPR2_SMP18_1 (0x2UL << ADC_SMPR2_SMP18_Pos)
1379#define ADC_SMPR2_SMP18_2 (0x4UL << ADC_SMPR2_SMP18_Pos)
1381/******************** Bit definition for ADC_TR1 register *******************/
1382#define ADC_TR1_LT1_Pos (0U)
1383#define ADC_TR1_LT1_Msk (0xFFFUL << ADC_TR1_LT1_Pos)
1384#define ADC_TR1_LT1 ADC_TR1_LT1_Msk
1385#define ADC_TR1_LT1_0 (0x001UL << ADC_TR1_LT1_Pos)
1386#define ADC_TR1_LT1_1 (0x002UL << ADC_TR1_LT1_Pos)
1387#define ADC_TR1_LT1_2 (0x004UL << ADC_TR1_LT1_Pos)
1388#define ADC_TR1_LT1_3 (0x008UL << ADC_TR1_LT1_Pos)
1389#define ADC_TR1_LT1_4 (0x010UL << ADC_TR1_LT1_Pos)
1390#define ADC_TR1_LT1_5 (0x020UL << ADC_TR1_LT1_Pos)
1391#define ADC_TR1_LT1_6 (0x040UL << ADC_TR1_LT1_Pos)
1392#define ADC_TR1_LT1_7 (0x080UL << ADC_TR1_LT1_Pos)
1393#define ADC_TR1_LT1_8 (0x100UL << ADC_TR1_LT1_Pos)
1394#define ADC_TR1_LT1_9 (0x200UL << ADC_TR1_LT1_Pos)
1395#define ADC_TR1_LT1_10 (0x400UL << ADC_TR1_LT1_Pos)
1396#define ADC_TR1_LT1_11 (0x800UL << ADC_TR1_LT1_Pos)
1398#define ADC_TR1_HT1_Pos (16U)
1399#define ADC_TR1_HT1_Msk (0xFFFUL << ADC_TR1_HT1_Pos)
1400#define ADC_TR1_HT1 ADC_TR1_HT1_Msk
1401#define ADC_TR1_HT1_0 (0x001UL << ADC_TR1_HT1_Pos)
1402#define ADC_TR1_HT1_1 (0x002UL << ADC_TR1_HT1_Pos)
1403#define ADC_TR1_HT1_2 (0x004UL << ADC_TR1_HT1_Pos)
1404#define ADC_TR1_HT1_3 (0x008UL << ADC_TR1_HT1_Pos)
1405#define ADC_TR1_HT1_4 (0x010UL << ADC_TR1_HT1_Pos)
1406#define ADC_TR1_HT1_5 (0x020UL << ADC_TR1_HT1_Pos)
1407#define ADC_TR1_HT1_6 (0x040UL << ADC_TR1_HT1_Pos)
1408#define ADC_TR1_HT1_7 (0x080UL << ADC_TR1_HT1_Pos)
1409#define ADC_TR1_HT1_8 (0x100UL << ADC_TR1_HT1_Pos)
1410#define ADC_TR1_HT1_9 (0x200UL << ADC_TR1_HT1_Pos)
1411#define ADC_TR1_HT1_10 (0x400UL << ADC_TR1_HT1_Pos)
1412#define ADC_TR1_HT1_11 (0x800UL << ADC_TR1_HT1_Pos)
1414/******************** Bit definition for ADC_TR2 register *******************/
1415#define ADC_TR2_LT2_Pos (0U)
1416#define ADC_TR2_LT2_Msk (0xFFUL << ADC_TR2_LT2_Pos)
1417#define ADC_TR2_LT2 ADC_TR2_LT2_Msk
1418#define ADC_TR2_LT2_0 (0x01UL << ADC_TR2_LT2_Pos)
1419#define ADC_TR2_LT2_1 (0x02UL << ADC_TR2_LT2_Pos)
1420#define ADC_TR2_LT2_2 (0x04UL << ADC_TR2_LT2_Pos)
1421#define ADC_TR2_LT2_3 (0x08UL << ADC_TR2_LT2_Pos)
1422#define ADC_TR2_LT2_4 (0x10UL << ADC_TR2_LT2_Pos)
1423#define ADC_TR2_LT2_5 (0x20UL << ADC_TR2_LT2_Pos)
1424#define ADC_TR2_LT2_6 (0x40UL << ADC_TR2_LT2_Pos)
1425#define ADC_TR2_LT2_7 (0x80UL << ADC_TR2_LT2_Pos)
1427#define ADC_TR2_HT2_Pos (16U)
1428#define ADC_TR2_HT2_Msk (0xFFUL << ADC_TR2_HT2_Pos)
1429#define ADC_TR2_HT2 ADC_TR2_HT2_Msk
1430#define ADC_TR2_HT2_0 (0x01UL << ADC_TR2_HT2_Pos)
1431#define ADC_TR2_HT2_1 (0x02UL << ADC_TR2_HT2_Pos)
1432#define ADC_TR2_HT2_2 (0x04UL << ADC_TR2_HT2_Pos)
1433#define ADC_TR2_HT2_3 (0x08UL << ADC_TR2_HT2_Pos)
1434#define ADC_TR2_HT2_4 (0x10UL << ADC_TR2_HT2_Pos)
1435#define ADC_TR2_HT2_5 (0x20UL << ADC_TR2_HT2_Pos)
1436#define ADC_TR2_HT2_6 (0x40UL << ADC_TR2_HT2_Pos)
1437#define ADC_TR2_HT2_7 (0x80UL << ADC_TR2_HT2_Pos)
1439/******************** Bit definition for ADC_TR3 register *******************/
1440#define ADC_TR3_LT3_Pos (0U)
1441#define ADC_TR3_LT3_Msk (0xFFUL << ADC_TR3_LT3_Pos)
1442#define ADC_TR3_LT3 ADC_TR3_LT3_Msk
1443#define ADC_TR3_LT3_0 (0x01UL << ADC_TR3_LT3_Pos)
1444#define ADC_TR3_LT3_1 (0x02UL << ADC_TR3_LT3_Pos)
1445#define ADC_TR3_LT3_2 (0x04UL << ADC_TR3_LT3_Pos)
1446#define ADC_TR3_LT3_3 (0x08UL << ADC_TR3_LT3_Pos)
1447#define ADC_TR3_LT3_4 (0x10UL << ADC_TR3_LT3_Pos)
1448#define ADC_TR3_LT3_5 (0x20UL << ADC_TR3_LT3_Pos)
1449#define ADC_TR3_LT3_6 (0x40UL << ADC_TR3_LT3_Pos)
1450#define ADC_TR3_LT3_7 (0x80UL << ADC_TR3_LT3_Pos)
1452#define ADC_TR3_HT3_Pos (16U)
1453#define ADC_TR3_HT3_Msk (0xFFUL << ADC_TR3_HT3_Pos)
1454#define ADC_TR3_HT3 ADC_TR3_HT3_Msk
1455#define ADC_TR3_HT3_0 (0x01UL << ADC_TR3_HT3_Pos)
1456#define ADC_TR3_HT3_1 (0x02UL << ADC_TR3_HT3_Pos)
1457#define ADC_TR3_HT3_2 (0x04UL << ADC_TR3_HT3_Pos)
1458#define ADC_TR3_HT3_3 (0x08UL << ADC_TR3_HT3_Pos)
1459#define ADC_TR3_HT3_4 (0x10UL << ADC_TR3_HT3_Pos)
1460#define ADC_TR3_HT3_5 (0x20UL << ADC_TR3_HT3_Pos)
1461#define ADC_TR3_HT3_6 (0x40UL << ADC_TR3_HT3_Pos)
1462#define ADC_TR3_HT3_7 (0x80UL << ADC_TR3_HT3_Pos)
1464/******************** Bit definition for ADC_SQR1 register ******************/
1465#define ADC_SQR1_L_Pos (0U)
1466#define ADC_SQR1_L_Msk (0xFUL << ADC_SQR1_L_Pos)
1467#define ADC_SQR1_L ADC_SQR1_L_Msk
1468#define ADC_SQR1_L_0 (0x1UL << ADC_SQR1_L_Pos)
1469#define ADC_SQR1_L_1 (0x2UL << ADC_SQR1_L_Pos)
1470#define ADC_SQR1_L_2 (0x4UL << ADC_SQR1_L_Pos)
1471#define ADC_SQR1_L_3 (0x8UL << ADC_SQR1_L_Pos)
1473#define ADC_SQR1_SQ1_Pos (6U)
1474#define ADC_SQR1_SQ1_Msk (0x1FUL << ADC_SQR1_SQ1_Pos)
1475#define ADC_SQR1_SQ1 ADC_SQR1_SQ1_Msk
1476#define ADC_SQR1_SQ1_0 (0x01UL << ADC_SQR1_SQ1_Pos)
1477#define ADC_SQR1_SQ1_1 (0x02UL << ADC_SQR1_SQ1_Pos)
1478#define ADC_SQR1_SQ1_2 (0x04UL << ADC_SQR1_SQ1_Pos)
1479#define ADC_SQR1_SQ1_3 (0x08UL << ADC_SQR1_SQ1_Pos)
1480#define ADC_SQR1_SQ1_4 (0x10UL << ADC_SQR1_SQ1_Pos)
1482#define ADC_SQR1_SQ2_Pos (12U)
1483#define ADC_SQR1_SQ2_Msk (0x1FUL << ADC_SQR1_SQ2_Pos)
1484#define ADC_SQR1_SQ2 ADC_SQR1_SQ2_Msk
1485#define ADC_SQR1_SQ2_0 (0x01UL << ADC_SQR1_SQ2_Pos)
1486#define ADC_SQR1_SQ2_1 (0x02UL << ADC_SQR1_SQ2_Pos)
1487#define ADC_SQR1_SQ2_2 (0x04UL << ADC_SQR1_SQ2_Pos)
1488#define ADC_SQR1_SQ2_3 (0x08UL << ADC_SQR1_SQ2_Pos)
1489#define ADC_SQR1_SQ2_4 (0x10UL << ADC_SQR1_SQ2_Pos)
1491#define ADC_SQR1_SQ3_Pos (18U)
1492#define ADC_SQR1_SQ3_Msk (0x1FUL << ADC_SQR1_SQ3_Pos)
1493#define ADC_SQR1_SQ3 ADC_SQR1_SQ3_Msk
1494#define ADC_SQR1_SQ3_0 (0x01UL << ADC_SQR1_SQ3_Pos)
1495#define ADC_SQR1_SQ3_1 (0x02UL << ADC_SQR1_SQ3_Pos)
1496#define ADC_SQR1_SQ3_2 (0x04UL << ADC_SQR1_SQ3_Pos)
1497#define ADC_SQR1_SQ3_3 (0x08UL << ADC_SQR1_SQ3_Pos)
1498#define ADC_SQR1_SQ3_4 (0x10UL << ADC_SQR1_SQ3_Pos)
1500#define ADC_SQR1_SQ4_Pos (24U)
1501#define ADC_SQR1_SQ4_Msk (0x1FUL << ADC_SQR1_SQ4_Pos)
1502#define ADC_SQR1_SQ4 ADC_SQR1_SQ4_Msk
1503#define ADC_SQR1_SQ4_0 (0x01UL << ADC_SQR1_SQ4_Pos)
1504#define ADC_SQR1_SQ4_1 (0x02UL << ADC_SQR1_SQ4_Pos)
1505#define ADC_SQR1_SQ4_2 (0x04UL << ADC_SQR1_SQ4_Pos)
1506#define ADC_SQR1_SQ4_3 (0x08UL << ADC_SQR1_SQ4_Pos)
1507#define ADC_SQR1_SQ4_4 (0x10UL << ADC_SQR1_SQ4_Pos)
1509/******************** Bit definition for ADC_SQR2 register ******************/
1510#define ADC_SQR2_SQ5_Pos (0U)
1511#define ADC_SQR2_SQ5_Msk (0x1FUL << ADC_SQR2_SQ5_Pos)
1512#define ADC_SQR2_SQ5 ADC_SQR2_SQ5_Msk
1513#define ADC_SQR2_SQ5_0 (0x01UL << ADC_SQR2_SQ5_Pos)
1514#define ADC_SQR2_SQ5_1 (0x02UL << ADC_SQR2_SQ5_Pos)
1515#define ADC_SQR2_SQ5_2 (0x04UL << ADC_SQR2_SQ5_Pos)
1516#define ADC_SQR2_SQ5_3 (0x08UL << ADC_SQR2_SQ5_Pos)
1517#define ADC_SQR2_SQ5_4 (0x10UL << ADC_SQR2_SQ5_Pos)
1519#define ADC_SQR2_SQ6_Pos (6U)
1520#define ADC_SQR2_SQ6_Msk (0x1FUL << ADC_SQR2_SQ6_Pos)
1521#define ADC_SQR2_SQ6 ADC_SQR2_SQ6_Msk
1522#define ADC_SQR2_SQ6_0 (0x01UL << ADC_SQR2_SQ6_Pos)
1523#define ADC_SQR2_SQ6_1 (0x02UL << ADC_SQR2_SQ6_Pos)
1524#define ADC_SQR2_SQ6_2 (0x04UL << ADC_SQR2_SQ6_Pos)
1525#define ADC_SQR2_SQ6_3 (0x08UL << ADC_SQR2_SQ6_Pos)
1526#define ADC_SQR2_SQ6_4 (0x10UL << ADC_SQR2_SQ6_Pos)
1528#define ADC_SQR2_SQ7_Pos (12U)
1529#define ADC_SQR2_SQ7_Msk (0x1FUL << ADC_SQR2_SQ7_Pos)
1530#define ADC_SQR2_SQ7 ADC_SQR2_SQ7_Msk
1531#define ADC_SQR2_SQ7_0 (0x01UL << ADC_SQR2_SQ7_Pos)
1532#define ADC_SQR2_SQ7_1 (0x02UL << ADC_SQR2_SQ7_Pos)
1533#define ADC_SQR2_SQ7_2 (0x04UL << ADC_SQR2_SQ7_Pos)
1534#define ADC_SQR2_SQ7_3 (0x08UL << ADC_SQR2_SQ7_Pos)
1535#define ADC_SQR2_SQ7_4 (0x10UL << ADC_SQR2_SQ7_Pos)
1537#define ADC_SQR2_SQ8_Pos (18U)
1538#define ADC_SQR2_SQ8_Msk (0x1FUL << ADC_SQR2_SQ8_Pos)
1539#define ADC_SQR2_SQ8 ADC_SQR2_SQ8_Msk
1540#define ADC_SQR2_SQ8_0 (0x01UL << ADC_SQR2_SQ8_Pos)
1541#define ADC_SQR2_SQ8_1 (0x02UL << ADC_SQR2_SQ8_Pos)
1542#define ADC_SQR2_SQ8_2 (0x04UL << ADC_SQR2_SQ8_Pos)
1543#define ADC_SQR2_SQ8_3 (0x08UL << ADC_SQR2_SQ8_Pos)
1544#define ADC_SQR2_SQ8_4 (0x10UL << ADC_SQR2_SQ8_Pos)
1546#define ADC_SQR2_SQ9_Pos (24U)
1547#define ADC_SQR2_SQ9_Msk (0x1FUL << ADC_SQR2_SQ9_Pos)
1548#define ADC_SQR2_SQ9 ADC_SQR2_SQ9_Msk
1549#define ADC_SQR2_SQ9_0 (0x01UL << ADC_SQR2_SQ9_Pos)
1550#define ADC_SQR2_SQ9_1 (0x02UL << ADC_SQR2_SQ9_Pos)
1551#define ADC_SQR2_SQ9_2 (0x04UL << ADC_SQR2_SQ9_Pos)
1552#define ADC_SQR2_SQ9_3 (0x08UL << ADC_SQR2_SQ9_Pos)
1553#define ADC_SQR2_SQ9_4 (0x10UL << ADC_SQR2_SQ9_Pos)
1555/******************** Bit definition for ADC_SQR3 register ******************/
1556#define ADC_SQR3_SQ10_Pos (0U)
1557#define ADC_SQR3_SQ10_Msk (0x1FUL << ADC_SQR3_SQ10_Pos)
1558#define ADC_SQR3_SQ10 ADC_SQR3_SQ10_Msk
1559#define ADC_SQR3_SQ10_0 (0x01UL << ADC_SQR3_SQ10_Pos)
1560#define ADC_SQR3_SQ10_1 (0x02UL << ADC_SQR3_SQ10_Pos)
1561#define ADC_SQR3_SQ10_2 (0x04UL << ADC_SQR3_SQ10_Pos)
1562#define ADC_SQR3_SQ10_3 (0x08UL << ADC_SQR3_SQ10_Pos)
1563#define ADC_SQR3_SQ10_4 (0x10UL << ADC_SQR3_SQ10_Pos)
1565#define ADC_SQR3_SQ11_Pos (6U)
1566#define ADC_SQR3_SQ11_Msk (0x1FUL << ADC_SQR3_SQ11_Pos)
1567#define ADC_SQR3_SQ11 ADC_SQR3_SQ11_Msk
1568#define ADC_SQR3_SQ11_0 (0x01UL << ADC_SQR3_SQ11_Pos)
1569#define ADC_SQR3_SQ11_1 (0x02UL << ADC_SQR3_SQ11_Pos)
1570#define ADC_SQR3_SQ11_2 (0x04UL << ADC_SQR3_SQ11_Pos)
1571#define ADC_SQR3_SQ11_3 (0x08UL << ADC_SQR3_SQ11_Pos)
1572#define ADC_SQR3_SQ11_4 (0x10UL << ADC_SQR3_SQ11_Pos)
1574#define ADC_SQR3_SQ12_Pos (12U)
1575#define ADC_SQR3_SQ12_Msk (0x1FUL << ADC_SQR3_SQ12_Pos)
1576#define ADC_SQR3_SQ12 ADC_SQR3_SQ12_Msk
1577#define ADC_SQR3_SQ12_0 (0x01UL << ADC_SQR3_SQ12_Pos)
1578#define ADC_SQR3_SQ12_1 (0x02UL << ADC_SQR3_SQ12_Pos)
1579#define ADC_SQR3_SQ12_2 (0x04UL << ADC_SQR3_SQ12_Pos)
1580#define ADC_SQR3_SQ12_3 (0x08UL << ADC_SQR3_SQ12_Pos)
1581#define ADC_SQR3_SQ12_4 (0x10UL << ADC_SQR3_SQ12_Pos)
1583#define ADC_SQR3_SQ13_Pos (18U)
1584#define ADC_SQR3_SQ13_Msk (0x1FUL << ADC_SQR3_SQ13_Pos)
1585#define ADC_SQR3_SQ13 ADC_SQR3_SQ13_Msk
1586#define ADC_SQR3_SQ13_0 (0x01UL << ADC_SQR3_SQ13_Pos)
1587#define ADC_SQR3_SQ13_1 (0x02UL << ADC_SQR3_SQ13_Pos)
1588#define ADC_SQR3_SQ13_2 (0x04UL << ADC_SQR3_SQ13_Pos)
1589#define ADC_SQR3_SQ13_3 (0x08UL << ADC_SQR3_SQ13_Pos)
1590#define ADC_SQR3_SQ13_4 (0x10UL << ADC_SQR3_SQ13_Pos)
1592#define ADC_SQR3_SQ14_Pos (24U)
1593#define ADC_SQR3_SQ14_Msk (0x1FUL << ADC_SQR3_SQ14_Pos)
1594#define ADC_SQR3_SQ14 ADC_SQR3_SQ14_Msk
1595#define ADC_SQR3_SQ14_0 (0x01UL << ADC_SQR3_SQ14_Pos)
1596#define ADC_SQR3_SQ14_1 (0x02UL << ADC_SQR3_SQ14_Pos)
1597#define ADC_SQR3_SQ14_2 (0x04UL << ADC_SQR3_SQ14_Pos)
1598#define ADC_SQR3_SQ14_3 (0x08UL << ADC_SQR3_SQ14_Pos)
1599#define ADC_SQR3_SQ14_4 (0x10UL << ADC_SQR3_SQ14_Pos)
1601/******************** Bit definition for ADC_SQR4 register ******************/
1602#define ADC_SQR4_SQ15_Pos (0U)
1603#define ADC_SQR4_SQ15_Msk (0x1FUL << ADC_SQR4_SQ15_Pos)
1604#define ADC_SQR4_SQ15 ADC_SQR4_SQ15_Msk
1605#define ADC_SQR4_SQ15_0 (0x01UL << ADC_SQR4_SQ15_Pos)
1606#define ADC_SQR4_SQ15_1 (0x02UL << ADC_SQR4_SQ15_Pos)
1607#define ADC_SQR4_SQ15_2 (0x04UL << ADC_SQR4_SQ15_Pos)
1608#define ADC_SQR4_SQ15_3 (0x08UL << ADC_SQR4_SQ15_Pos)
1609#define ADC_SQR4_SQ15_4 (0x10UL << ADC_SQR4_SQ15_Pos)
1611#define ADC_SQR4_SQ16_Pos (6U)
1612#define ADC_SQR4_SQ16_Msk (0x1FUL << ADC_SQR4_SQ16_Pos)
1613#define ADC_SQR4_SQ16 ADC_SQR4_SQ16_Msk
1614#define ADC_SQR4_SQ16_0 (0x01UL << ADC_SQR4_SQ16_Pos)
1615#define ADC_SQR4_SQ16_1 (0x02UL << ADC_SQR4_SQ16_Pos)
1616#define ADC_SQR4_SQ16_2 (0x04UL << ADC_SQR4_SQ16_Pos)
1617#define ADC_SQR4_SQ16_3 (0x08UL << ADC_SQR4_SQ16_Pos)
1618#define ADC_SQR4_SQ16_4 (0x10UL << ADC_SQR4_SQ16_Pos)
1620/******************** Bit definition for ADC_DR register ********************/
1621#define ADC_DR_RDATA_Pos (0U)
1622#define ADC_DR_RDATA_Msk (0xFFFFUL << ADC_DR_RDATA_Pos)
1623#define ADC_DR_RDATA ADC_DR_RDATA_Msk
1624#define ADC_DR_RDATA_0 (0x0001UL << ADC_DR_RDATA_Pos)
1625#define ADC_DR_RDATA_1 (0x0002UL << ADC_DR_RDATA_Pos)
1626#define ADC_DR_RDATA_2 (0x0004UL << ADC_DR_RDATA_Pos)
1627#define ADC_DR_RDATA_3 (0x0008UL << ADC_DR_RDATA_Pos)
1628#define ADC_DR_RDATA_4 (0x0010UL << ADC_DR_RDATA_Pos)
1629#define ADC_DR_RDATA_5 (0x0020UL << ADC_DR_RDATA_Pos)
1630#define ADC_DR_RDATA_6 (0x0040UL << ADC_DR_RDATA_Pos)
1631#define ADC_DR_RDATA_7 (0x0080UL << ADC_DR_RDATA_Pos)
1632#define ADC_DR_RDATA_8 (0x0100UL << ADC_DR_RDATA_Pos)
1633#define ADC_DR_RDATA_9 (0x0200UL << ADC_DR_RDATA_Pos)
1634#define ADC_DR_RDATA_10 (0x0400UL << ADC_DR_RDATA_Pos)
1635#define ADC_DR_RDATA_11 (0x0800UL << ADC_DR_RDATA_Pos)
1636#define ADC_DR_RDATA_12 (0x1000UL << ADC_DR_RDATA_Pos)
1637#define ADC_DR_RDATA_13 (0x2000UL << ADC_DR_RDATA_Pos)
1638#define ADC_DR_RDATA_14 (0x4000UL << ADC_DR_RDATA_Pos)
1639#define ADC_DR_RDATA_15 (0x8000UL << ADC_DR_RDATA_Pos)
1641/******************** Bit definition for ADC_JSQR register ******************/
1642#define ADC_JSQR_JL_Pos (0U)
1643#define ADC_JSQR_JL_Msk (0x3UL << ADC_JSQR_JL_Pos)
1644#define ADC_JSQR_JL ADC_JSQR_JL_Msk
1645#define ADC_JSQR_JL_0 (0x1UL << ADC_JSQR_JL_Pos)
1646#define ADC_JSQR_JL_1 (0x2UL << ADC_JSQR_JL_Pos)
1648#define ADC_JSQR_JEXTSEL_Pos (2U)
1649#define ADC_JSQR_JEXTSEL_Msk (0xFUL << ADC_JSQR_JEXTSEL_Pos)
1650#define ADC_JSQR_JEXTSEL ADC_JSQR_JEXTSEL_Msk
1651#define ADC_JSQR_JEXTSEL_0 (0x1UL << ADC_JSQR_JEXTSEL_Pos)
1652#define ADC_JSQR_JEXTSEL_1 (0x2UL << ADC_JSQR_JEXTSEL_Pos)
1653#define ADC_JSQR_JEXTSEL_2 (0x4UL << ADC_JSQR_JEXTSEL_Pos)
1654#define ADC_JSQR_JEXTSEL_3 (0x8UL << ADC_JSQR_JEXTSEL_Pos)
1656#define ADC_JSQR_JEXTEN_Pos (6U)
1657#define ADC_JSQR_JEXTEN_Msk (0x3UL << ADC_JSQR_JEXTEN_Pos)
1658#define ADC_JSQR_JEXTEN ADC_JSQR_JEXTEN_Msk
1659#define ADC_JSQR_JEXTEN_0 (0x1UL << ADC_JSQR_JEXTEN_Pos)
1660#define ADC_JSQR_JEXTEN_1 (0x2UL << ADC_JSQR_JEXTEN_Pos)
1662#define ADC_JSQR_JSQ1_Pos (8U)
1663#define ADC_JSQR_JSQ1_Msk (0x1FUL << ADC_JSQR_JSQ1_Pos)
1664#define ADC_JSQR_JSQ1 ADC_JSQR_JSQ1_Msk
1665#define ADC_JSQR_JSQ1_0 (0x01UL << ADC_JSQR_JSQ1_Pos)
1666#define ADC_JSQR_JSQ1_1 (0x02UL << ADC_JSQR_JSQ1_Pos)
1667#define ADC_JSQR_JSQ1_2 (0x04UL << ADC_JSQR_JSQ1_Pos)
1668#define ADC_JSQR_JSQ1_3 (0x08UL << ADC_JSQR_JSQ1_Pos)
1669#define ADC_JSQR_JSQ1_4 (0x10UL << ADC_JSQR_JSQ1_Pos)
1671#define ADC_JSQR_JSQ2_Pos (14U)
1672#define ADC_JSQR_JSQ2_Msk (0x1FUL << ADC_JSQR_JSQ2_Pos)
1673#define ADC_JSQR_JSQ2 ADC_JSQR_JSQ2_Msk
1674#define ADC_JSQR_JSQ2_0 (0x01UL << ADC_JSQR_JSQ2_Pos)
1675#define ADC_JSQR_JSQ2_1 (0x02UL << ADC_JSQR_JSQ2_Pos)
1676#define ADC_JSQR_JSQ2_2 (0x04UL << ADC_JSQR_JSQ2_Pos)
1677#define ADC_JSQR_JSQ2_3 (0x08UL << ADC_JSQR_JSQ2_Pos)
1678#define ADC_JSQR_JSQ2_4 (0x10UL << ADC_JSQR_JSQ2_Pos)
1680#define ADC_JSQR_JSQ3_Pos (20U)
1681#define ADC_JSQR_JSQ3_Msk (0x1FUL << ADC_JSQR_JSQ3_Pos)
1682#define ADC_JSQR_JSQ3 ADC_JSQR_JSQ3_Msk
1683#define ADC_JSQR_JSQ3_0 (0x01UL << ADC_JSQR_JSQ3_Pos)
1684#define ADC_JSQR_JSQ3_1 (0x02UL << ADC_JSQR_JSQ3_Pos)
1685#define ADC_JSQR_JSQ3_2 (0x04UL << ADC_JSQR_JSQ3_Pos)
1686#define ADC_JSQR_JSQ3_3 (0x08UL << ADC_JSQR_JSQ3_Pos)
1687#define ADC_JSQR_JSQ3_4 (0x10UL << ADC_JSQR_JSQ3_Pos)
1689#define ADC_JSQR_JSQ4_Pos (26U)
1690#define ADC_JSQR_JSQ4_Msk (0x1FUL << ADC_JSQR_JSQ4_Pos)
1691#define ADC_JSQR_JSQ4 ADC_JSQR_JSQ4_Msk
1692#define ADC_JSQR_JSQ4_0 (0x01UL << ADC_JSQR_JSQ4_Pos)
1693#define ADC_JSQR_JSQ4_1 (0x02UL << ADC_JSQR_JSQ4_Pos)
1694#define ADC_JSQR_JSQ4_2 (0x04UL << ADC_JSQR_JSQ4_Pos)
1695#define ADC_JSQR_JSQ4_3 (0x08UL << ADC_JSQR_JSQ4_Pos)
1696#define ADC_JSQR_JSQ4_4 (0x10UL << ADC_JSQR_JSQ4_Pos)
1699/******************** Bit definition for ADC_OFR1 register ******************/
1700#define ADC_OFR1_OFFSET1_Pos (0U)
1701#define ADC_OFR1_OFFSET1_Msk (0xFFFUL << ADC_OFR1_OFFSET1_Pos)
1702#define ADC_OFR1_OFFSET1 ADC_OFR1_OFFSET1_Msk
1703#define ADC_OFR1_OFFSET1_0 (0x001UL << ADC_OFR1_OFFSET1_Pos)
1704#define ADC_OFR1_OFFSET1_1 (0x002UL << ADC_OFR1_OFFSET1_Pos)
1705#define ADC_OFR1_OFFSET1_2 (0x004UL << ADC_OFR1_OFFSET1_Pos)
1706#define ADC_OFR1_OFFSET1_3 (0x008UL << ADC_OFR1_OFFSET1_Pos)
1707#define ADC_OFR1_OFFSET1_4 (0x010UL << ADC_OFR1_OFFSET1_Pos)
1708#define ADC_OFR1_OFFSET1_5 (0x020UL << ADC_OFR1_OFFSET1_Pos)
1709#define ADC_OFR1_OFFSET1_6 (0x040UL << ADC_OFR1_OFFSET1_Pos)
1710#define ADC_OFR1_OFFSET1_7 (0x080UL << ADC_OFR1_OFFSET1_Pos)
1711#define ADC_OFR1_OFFSET1_8 (0x100UL << ADC_OFR1_OFFSET1_Pos)
1712#define ADC_OFR1_OFFSET1_9 (0x200UL << ADC_OFR1_OFFSET1_Pos)
1713#define ADC_OFR1_OFFSET1_10 (0x400UL << ADC_OFR1_OFFSET1_Pos)
1714#define ADC_OFR1_OFFSET1_11 (0x800UL << ADC_OFR1_OFFSET1_Pos)
1716#define ADC_OFR1_OFFSET1_CH_Pos (26U)
1717#define ADC_OFR1_OFFSET1_CH_Msk (0x1FUL << ADC_OFR1_OFFSET1_CH_Pos)
1718#define ADC_OFR1_OFFSET1_CH ADC_OFR1_OFFSET1_CH_Msk
1719#define ADC_OFR1_OFFSET1_CH_0 (0x01UL << ADC_OFR1_OFFSET1_CH_Pos)
1720#define ADC_OFR1_OFFSET1_CH_1 (0x02UL << ADC_OFR1_OFFSET1_CH_Pos)
1721#define ADC_OFR1_OFFSET1_CH_2 (0x04UL << ADC_OFR1_OFFSET1_CH_Pos)
1722#define ADC_OFR1_OFFSET1_CH_3 (0x08UL << ADC_OFR1_OFFSET1_CH_Pos)
1723#define ADC_OFR1_OFFSET1_CH_4 (0x10UL << ADC_OFR1_OFFSET1_CH_Pos)
1725#define ADC_OFR1_OFFSET1_EN_Pos (31U)
1726#define ADC_OFR1_OFFSET1_EN_Msk (0x1UL << ADC_OFR1_OFFSET1_EN_Pos)
1727#define ADC_OFR1_OFFSET1_EN ADC_OFR1_OFFSET1_EN_Msk
1729/******************** Bit definition for ADC_OFR2 register ******************/
1730#define ADC_OFR2_OFFSET2_Pos (0U)
1731#define ADC_OFR2_OFFSET2_Msk (0xFFFUL << ADC_OFR2_OFFSET2_Pos)
1732#define ADC_OFR2_OFFSET2 ADC_OFR2_OFFSET2_Msk
1733#define ADC_OFR2_OFFSET2_0 (0x001UL << ADC_OFR2_OFFSET2_Pos)
1734#define ADC_OFR2_OFFSET2_1 (0x002UL << ADC_OFR2_OFFSET2_Pos)
1735#define ADC_OFR2_OFFSET2_2 (0x004UL << ADC_OFR2_OFFSET2_Pos)
1736#define ADC_OFR2_OFFSET2_3 (0x008UL << ADC_OFR2_OFFSET2_Pos)
1737#define ADC_OFR2_OFFSET2_4 (0x010UL << ADC_OFR2_OFFSET2_Pos)
1738#define ADC_OFR2_OFFSET2_5 (0x020UL << ADC_OFR2_OFFSET2_Pos)
1739#define ADC_OFR2_OFFSET2_6 (0x040UL << ADC_OFR2_OFFSET2_Pos)
1740#define ADC_OFR2_OFFSET2_7 (0x080UL << ADC_OFR2_OFFSET2_Pos)
1741#define ADC_OFR2_OFFSET2_8 (0x100UL << ADC_OFR2_OFFSET2_Pos)
1742#define ADC_OFR2_OFFSET2_9 (0x200UL << ADC_OFR2_OFFSET2_Pos)
1743#define ADC_OFR2_OFFSET2_10 (0x400UL << ADC_OFR2_OFFSET2_Pos)
1744#define ADC_OFR2_OFFSET2_11 (0x800UL << ADC_OFR2_OFFSET2_Pos)
1746#define ADC_OFR2_OFFSET2_CH_Pos (26U)
1747#define ADC_OFR2_OFFSET2_CH_Msk (0x1FUL << ADC_OFR2_OFFSET2_CH_Pos)
1748#define ADC_OFR2_OFFSET2_CH ADC_OFR2_OFFSET2_CH_Msk
1749#define ADC_OFR2_OFFSET2_CH_0 (0x01UL << ADC_OFR2_OFFSET2_CH_Pos)
1750#define ADC_OFR2_OFFSET2_CH_1 (0x02UL << ADC_OFR2_OFFSET2_CH_Pos)
1751#define ADC_OFR2_OFFSET2_CH_2 (0x04UL << ADC_OFR2_OFFSET2_CH_Pos)
1752#define ADC_OFR2_OFFSET2_CH_3 (0x08UL << ADC_OFR2_OFFSET2_CH_Pos)
1753#define ADC_OFR2_OFFSET2_CH_4 (0x10UL << ADC_OFR2_OFFSET2_CH_Pos)
1755#define ADC_OFR2_OFFSET2_EN_Pos (31U)
1756#define ADC_OFR2_OFFSET2_EN_Msk (0x1UL << ADC_OFR2_OFFSET2_EN_Pos)
1757#define ADC_OFR2_OFFSET2_EN ADC_OFR2_OFFSET2_EN_Msk
1759/******************** Bit definition for ADC_OFR3 register ******************/
1760#define ADC_OFR3_OFFSET3_Pos (0U)
1761#define ADC_OFR3_OFFSET3_Msk (0xFFFUL << ADC_OFR3_OFFSET3_Pos)
1762#define ADC_OFR3_OFFSET3 ADC_OFR3_OFFSET3_Msk
1763#define ADC_OFR3_OFFSET3_0 (0x001UL << ADC_OFR3_OFFSET3_Pos)
1764#define ADC_OFR3_OFFSET3_1 (0x002UL << ADC_OFR3_OFFSET3_Pos)
1765#define ADC_OFR3_OFFSET3_2 (0x004UL << ADC_OFR3_OFFSET3_Pos)
1766#define ADC_OFR3_OFFSET3_3 (0x008UL << ADC_OFR3_OFFSET3_Pos)
1767#define ADC_OFR3_OFFSET3_4 (0x010UL << ADC_OFR3_OFFSET3_Pos)
1768#define ADC_OFR3_OFFSET3_5 (0x020UL << ADC_OFR3_OFFSET3_Pos)
1769#define ADC_OFR3_OFFSET3_6 (0x040UL << ADC_OFR3_OFFSET3_Pos)
1770#define ADC_OFR3_OFFSET3_7 (0x080UL << ADC_OFR3_OFFSET3_Pos)
1771#define ADC_OFR3_OFFSET3_8 (0x100UL << ADC_OFR3_OFFSET3_Pos)
1772#define ADC_OFR3_OFFSET3_9 (0x200UL << ADC_OFR3_OFFSET3_Pos)
1773#define ADC_OFR3_OFFSET3_10 (0x400UL << ADC_OFR3_OFFSET3_Pos)
1774#define ADC_OFR3_OFFSET3_11 (0x800UL << ADC_OFR3_OFFSET3_Pos)
1776#define ADC_OFR3_OFFSET3_CH_Pos (26U)
1777#define ADC_OFR3_OFFSET3_CH_Msk (0x1FUL << ADC_OFR3_OFFSET3_CH_Pos)
1778#define ADC_OFR3_OFFSET3_CH ADC_OFR3_OFFSET3_CH_Msk
1779#define ADC_OFR3_OFFSET3_CH_0 (0x01UL << ADC_OFR3_OFFSET3_CH_Pos)
1780#define ADC_OFR3_OFFSET3_CH_1 (0x02UL << ADC_OFR3_OFFSET3_CH_Pos)
1781#define ADC_OFR3_OFFSET3_CH_2 (0x04UL << ADC_OFR3_OFFSET3_CH_Pos)
1782#define ADC_OFR3_OFFSET3_CH_3 (0x08UL << ADC_OFR3_OFFSET3_CH_Pos)
1783#define ADC_OFR3_OFFSET3_CH_4 (0x10UL << ADC_OFR3_OFFSET3_CH_Pos)
1785#define ADC_OFR3_OFFSET3_EN_Pos (31U)
1786#define ADC_OFR3_OFFSET3_EN_Msk (0x1UL << ADC_OFR3_OFFSET3_EN_Pos)
1787#define ADC_OFR3_OFFSET3_EN ADC_OFR3_OFFSET3_EN_Msk
1789/******************** Bit definition for ADC_OFR4 register ******************/
1790#define ADC_OFR4_OFFSET4_Pos (0U)
1791#define ADC_OFR4_OFFSET4_Msk (0xFFFUL << ADC_OFR4_OFFSET4_Pos)
1792#define ADC_OFR4_OFFSET4 ADC_OFR4_OFFSET4_Msk
1793#define ADC_OFR4_OFFSET4_0 (0x001UL << ADC_OFR4_OFFSET4_Pos)
1794#define ADC_OFR4_OFFSET4_1 (0x002UL << ADC_OFR4_OFFSET4_Pos)
1795#define ADC_OFR4_OFFSET4_2 (0x004UL << ADC_OFR4_OFFSET4_Pos)
1796#define ADC_OFR4_OFFSET4_3 (0x008UL << ADC_OFR4_OFFSET4_Pos)
1797#define ADC_OFR4_OFFSET4_4 (0x010UL << ADC_OFR4_OFFSET4_Pos)
1798#define ADC_OFR4_OFFSET4_5 (0x020UL << ADC_OFR4_OFFSET4_Pos)
1799#define ADC_OFR4_OFFSET4_6 (0x040UL << ADC_OFR4_OFFSET4_Pos)
1800#define ADC_OFR4_OFFSET4_7 (0x080UL << ADC_OFR4_OFFSET4_Pos)
1801#define ADC_OFR4_OFFSET4_8 (0x100UL << ADC_OFR4_OFFSET4_Pos)
1802#define ADC_OFR4_OFFSET4_9 (0x200UL << ADC_OFR4_OFFSET4_Pos)
1803#define ADC_OFR4_OFFSET4_10 (0x400UL << ADC_OFR4_OFFSET4_Pos)
1804#define ADC_OFR4_OFFSET4_11 (0x800UL << ADC_OFR4_OFFSET4_Pos)
1806#define ADC_OFR4_OFFSET4_CH_Pos (26U)
1807#define ADC_OFR4_OFFSET4_CH_Msk (0x1FUL << ADC_OFR4_OFFSET4_CH_Pos)
1808#define ADC_OFR4_OFFSET4_CH ADC_OFR4_OFFSET4_CH_Msk
1809#define ADC_OFR4_OFFSET4_CH_0 (0x01UL << ADC_OFR4_OFFSET4_CH_Pos)
1810#define ADC_OFR4_OFFSET4_CH_1 (0x02UL << ADC_OFR4_OFFSET4_CH_Pos)
1811#define ADC_OFR4_OFFSET4_CH_2 (0x04UL << ADC_OFR4_OFFSET4_CH_Pos)
1812#define ADC_OFR4_OFFSET4_CH_3 (0x08UL << ADC_OFR4_OFFSET4_CH_Pos)
1813#define ADC_OFR4_OFFSET4_CH_4 (0x10UL << ADC_OFR4_OFFSET4_CH_Pos)
1815#define ADC_OFR4_OFFSET4_EN_Pos (31U)
1816#define ADC_OFR4_OFFSET4_EN_Msk (0x1UL << ADC_OFR4_OFFSET4_EN_Pos)
1817#define ADC_OFR4_OFFSET4_EN ADC_OFR4_OFFSET4_EN_Msk
1819/******************** Bit definition for ADC_JDR1 register ******************/
1820#define ADC_JDR1_JDATA_Pos (0U)
1821#define ADC_JDR1_JDATA_Msk (0xFFFFUL << ADC_JDR1_JDATA_Pos)
1822#define ADC_JDR1_JDATA ADC_JDR1_JDATA_Msk
1823#define ADC_JDR1_JDATA_0 (0x0001UL << ADC_JDR1_JDATA_Pos)
1824#define ADC_JDR1_JDATA_1 (0x0002UL << ADC_JDR1_JDATA_Pos)
1825#define ADC_JDR1_JDATA_2 (0x0004UL << ADC_JDR1_JDATA_Pos)
1826#define ADC_JDR1_JDATA_3 (0x0008UL << ADC_JDR1_JDATA_Pos)
1827#define ADC_JDR1_JDATA_4 (0x0010UL << ADC_JDR1_JDATA_Pos)
1828#define ADC_JDR1_JDATA_5 (0x0020UL << ADC_JDR1_JDATA_Pos)
1829#define ADC_JDR1_JDATA_6 (0x0040UL << ADC_JDR1_JDATA_Pos)
1830#define ADC_JDR1_JDATA_7 (0x0080UL << ADC_JDR1_JDATA_Pos)
1831#define ADC_JDR1_JDATA_8 (0x0100UL << ADC_JDR1_JDATA_Pos)
1832#define ADC_JDR1_JDATA_9 (0x0200UL << ADC_JDR1_JDATA_Pos)
1833#define ADC_JDR1_JDATA_10 (0x0400UL << ADC_JDR1_JDATA_Pos)
1834#define ADC_JDR1_JDATA_11 (0x0800UL << ADC_JDR1_JDATA_Pos)
1835#define ADC_JDR1_JDATA_12 (0x1000UL << ADC_JDR1_JDATA_Pos)
1836#define ADC_JDR1_JDATA_13 (0x2000UL << ADC_JDR1_JDATA_Pos)
1837#define ADC_JDR1_JDATA_14 (0x4000UL << ADC_JDR1_JDATA_Pos)
1838#define ADC_JDR1_JDATA_15 (0x8000UL << ADC_JDR1_JDATA_Pos)
1840/******************** Bit definition for ADC_JDR2 register ******************/
1841#define ADC_JDR2_JDATA_Pos (0U)
1842#define ADC_JDR2_JDATA_Msk (0xFFFFUL << ADC_JDR2_JDATA_Pos)
1843#define ADC_JDR2_JDATA ADC_JDR2_JDATA_Msk
1844#define ADC_JDR2_JDATA_0 (0x0001UL << ADC_JDR2_JDATA_Pos)
1845#define ADC_JDR2_JDATA_1 (0x0002UL << ADC_JDR2_JDATA_Pos)
1846#define ADC_JDR2_JDATA_2 (0x0004UL << ADC_JDR2_JDATA_Pos)
1847#define ADC_JDR2_JDATA_3 (0x0008UL << ADC_JDR2_JDATA_Pos)
1848#define ADC_JDR2_JDATA_4 (0x0010UL << ADC_JDR2_JDATA_Pos)
1849#define ADC_JDR2_JDATA_5 (0x0020UL << ADC_JDR2_JDATA_Pos)
1850#define ADC_JDR2_JDATA_6 (0x0040UL << ADC_JDR2_JDATA_Pos)
1851#define ADC_JDR2_JDATA_7 (0x0080UL << ADC_JDR2_JDATA_Pos)
1852#define ADC_JDR2_JDATA_8 (0x0100UL << ADC_JDR2_JDATA_Pos)
1853#define ADC_JDR2_JDATA_9 (0x0200UL << ADC_JDR2_JDATA_Pos)
1854#define ADC_JDR2_JDATA_10 (0x0400UL << ADC_JDR2_JDATA_Pos)
1855#define ADC_JDR2_JDATA_11 (0x0800UL << ADC_JDR2_JDATA_Pos)
1856#define ADC_JDR2_JDATA_12 (0x1000UL << ADC_JDR2_JDATA_Pos)
1857#define ADC_JDR2_JDATA_13 (0x2000UL << ADC_JDR2_JDATA_Pos)
1858#define ADC_JDR2_JDATA_14 (0x4000UL << ADC_JDR2_JDATA_Pos)
1859#define ADC_JDR2_JDATA_15 (0x8000UL << ADC_JDR2_JDATA_Pos)
1861/******************** Bit definition for ADC_JDR3 register ******************/
1862#define ADC_JDR3_JDATA_Pos (0U)
1863#define ADC_JDR3_JDATA_Msk (0xFFFFUL << ADC_JDR3_JDATA_Pos)
1864#define ADC_JDR3_JDATA ADC_JDR3_JDATA_Msk
1865#define ADC_JDR3_JDATA_0 (0x0001UL << ADC_JDR3_JDATA_Pos)
1866#define ADC_JDR3_JDATA_1 (0x0002UL << ADC_JDR3_JDATA_Pos)
1867#define ADC_JDR3_JDATA_2 (0x0004UL << ADC_JDR3_JDATA_Pos)
1868#define ADC_JDR3_JDATA_3 (0x0008UL << ADC_JDR3_JDATA_Pos)
1869#define ADC_JDR3_JDATA_4 (0x0010UL << ADC_JDR3_JDATA_Pos)
1870#define ADC_JDR3_JDATA_5 (0x0020UL << ADC_JDR3_JDATA_Pos)
1871#define ADC_JDR3_JDATA_6 (0x0040UL << ADC_JDR3_JDATA_Pos)
1872#define ADC_JDR3_JDATA_7 (0x0080UL << ADC_JDR3_JDATA_Pos)
1873#define ADC_JDR3_JDATA_8 (0x0100UL << ADC_JDR3_JDATA_Pos)
1874#define ADC_JDR3_JDATA_9 (0x0200UL << ADC_JDR3_JDATA_Pos)
1875#define ADC_JDR3_JDATA_10 (0x0400UL << ADC_JDR3_JDATA_Pos)
1876#define ADC_JDR3_JDATA_11 (0x0800UL << ADC_JDR3_JDATA_Pos)
1877#define ADC_JDR3_JDATA_12 (0x1000UL << ADC_JDR3_JDATA_Pos)
1878#define ADC_JDR3_JDATA_13 (0x2000UL << ADC_JDR3_JDATA_Pos)
1879#define ADC_JDR3_JDATA_14 (0x4000UL << ADC_JDR3_JDATA_Pos)
1880#define ADC_JDR3_JDATA_15 (0x8000UL << ADC_JDR3_JDATA_Pos)
1882/******************** Bit definition for ADC_JDR4 register ******************/
1883#define ADC_JDR4_JDATA_Pos (0U)
1884#define ADC_JDR4_JDATA_Msk (0xFFFFUL << ADC_JDR4_JDATA_Pos)
1885#define ADC_JDR4_JDATA ADC_JDR4_JDATA_Msk
1886#define ADC_JDR4_JDATA_0 (0x0001UL << ADC_JDR4_JDATA_Pos)
1887#define ADC_JDR4_JDATA_1 (0x0002UL << ADC_JDR4_JDATA_Pos)
1888#define ADC_JDR4_JDATA_2 (0x0004UL << ADC_JDR4_JDATA_Pos)
1889#define ADC_JDR4_JDATA_3 (0x0008UL << ADC_JDR4_JDATA_Pos)
1890#define ADC_JDR4_JDATA_4 (0x0010UL << ADC_JDR4_JDATA_Pos)
1891#define ADC_JDR4_JDATA_5 (0x0020UL << ADC_JDR4_JDATA_Pos)
1892#define ADC_JDR4_JDATA_6 (0x0040UL << ADC_JDR4_JDATA_Pos)
1893#define ADC_JDR4_JDATA_7 (0x0080UL << ADC_JDR4_JDATA_Pos)
1894#define ADC_JDR4_JDATA_8 (0x0100UL << ADC_JDR4_JDATA_Pos)
1895#define ADC_JDR4_JDATA_9 (0x0200UL << ADC_JDR4_JDATA_Pos)
1896#define ADC_JDR4_JDATA_10 (0x0400UL << ADC_JDR4_JDATA_Pos)
1897#define ADC_JDR4_JDATA_11 (0x0800UL << ADC_JDR4_JDATA_Pos)
1898#define ADC_JDR4_JDATA_12 (0x1000UL << ADC_JDR4_JDATA_Pos)
1899#define ADC_JDR4_JDATA_13 (0x2000UL << ADC_JDR4_JDATA_Pos)
1900#define ADC_JDR4_JDATA_14 (0x4000UL << ADC_JDR4_JDATA_Pos)
1901#define ADC_JDR4_JDATA_15 (0x8000UL << ADC_JDR4_JDATA_Pos)
1903/******************** Bit definition for ADC_AWD2CR register ****************/
1904#define ADC_AWD2CR_AWD2CH_Pos (1U)
1905#define ADC_AWD2CR_AWD2CH_Msk (0x3FFFFUL << ADC_AWD2CR_AWD2CH_Pos)
1906#define ADC_AWD2CR_AWD2CH ADC_AWD2CR_AWD2CH_Msk
1907#define ADC_AWD2CR_AWD2CH_0 (0x00001UL << ADC_AWD2CR_AWD2CH_Pos)
1908#define ADC_AWD2CR_AWD2CH_1 (0x00002UL << ADC_AWD2CR_AWD2CH_Pos)
1909#define ADC_AWD2CR_AWD2CH_2 (0x00004UL << ADC_AWD2CR_AWD2CH_Pos)
1910#define ADC_AWD2CR_AWD2CH_3 (0x00008UL << ADC_AWD2CR_AWD2CH_Pos)
1911#define ADC_AWD2CR_AWD2CH_4 (0x00010UL << ADC_AWD2CR_AWD2CH_Pos)
1912#define ADC_AWD2CR_AWD2CH_5 (0x00020UL << ADC_AWD2CR_AWD2CH_Pos)
1913#define ADC_AWD2CR_AWD2CH_6 (0x00040UL << ADC_AWD2CR_AWD2CH_Pos)
1914#define ADC_AWD2CR_AWD2CH_7 (0x00080UL << ADC_AWD2CR_AWD2CH_Pos)
1915#define ADC_AWD2CR_AWD2CH_8 (0x00100UL << ADC_AWD2CR_AWD2CH_Pos)
1916#define ADC_AWD2CR_AWD2CH_9 (0x00200UL << ADC_AWD2CR_AWD2CH_Pos)
1917#define ADC_AWD2CR_AWD2CH_10 (0x00400UL << ADC_AWD2CR_AWD2CH_Pos)
1918#define ADC_AWD2CR_AWD2CH_11 (0x00800UL << ADC_AWD2CR_AWD2CH_Pos)
1919#define ADC_AWD2CR_AWD2CH_12 (0x01000UL << ADC_AWD2CR_AWD2CH_Pos)
1920#define ADC_AWD2CR_AWD2CH_13 (0x02000UL << ADC_AWD2CR_AWD2CH_Pos)
1921#define ADC_AWD2CR_AWD2CH_14 (0x04000UL << ADC_AWD2CR_AWD2CH_Pos)
1922#define ADC_AWD2CR_AWD2CH_15 (0x08000UL << ADC_AWD2CR_AWD2CH_Pos)
1923#define ADC_AWD2CR_AWD2CH_16 (0x10000UL << ADC_AWD2CR_AWD2CH_Pos)
1924#define ADC_AWD2CR_AWD2CH_17 (0x20000UL << ADC_AWD2CR_AWD2CH_Pos)
1926/******************** Bit definition for ADC_AWD3CR register ****************/
1927#define ADC_AWD3CR_AWD3CH_Pos (1U)
1928#define ADC_AWD3CR_AWD3CH_Msk (0x3FFFFUL << ADC_AWD3CR_AWD3CH_Pos)
1929#define ADC_AWD3CR_AWD3CH ADC_AWD3CR_AWD3CH_Msk
1930#define ADC_AWD3CR_AWD3CH_0 (0x00001UL << ADC_AWD3CR_AWD3CH_Pos)
1931#define ADC_AWD3CR_AWD3CH_1 (0x00002UL << ADC_AWD3CR_AWD3CH_Pos)
1932#define ADC_AWD3CR_AWD3CH_2 (0x00004UL << ADC_AWD3CR_AWD3CH_Pos)
1933#define ADC_AWD3CR_AWD3CH_3 (0x00008UL << ADC_AWD3CR_AWD3CH_Pos)
1934#define ADC_AWD3CR_AWD3CH_4 (0x00010UL << ADC_AWD3CR_AWD3CH_Pos)
1935#define ADC_AWD3CR_AWD3CH_5 (0x00020UL << ADC_AWD3CR_AWD3CH_Pos)
1936#define ADC_AWD3CR_AWD3CH_6 (0x00040UL << ADC_AWD3CR_AWD3CH_Pos)
1937#define ADC_AWD3CR_AWD3CH_7 (0x00080UL << ADC_AWD3CR_AWD3CH_Pos)
1938#define ADC_AWD3CR_AWD3CH_8 (0x00100UL << ADC_AWD3CR_AWD3CH_Pos)
1939#define ADC_AWD3CR_AWD3CH_9 (0x00200UL << ADC_AWD3CR_AWD3CH_Pos)
1940#define ADC_AWD3CR_AWD3CH_10 (0x00400UL << ADC_AWD3CR_AWD3CH_Pos)
1941#define ADC_AWD3CR_AWD3CH_11 (0x00800UL << ADC_AWD3CR_AWD3CH_Pos)
1942#define ADC_AWD3CR_AWD3CH_12 (0x01000UL << ADC_AWD3CR_AWD3CH_Pos)
1943#define ADC_AWD3CR_AWD3CH_13 (0x02000UL << ADC_AWD3CR_AWD3CH_Pos)
1944#define ADC_AWD3CR_AWD3CH_14 (0x04000UL << ADC_AWD3CR_AWD3CH_Pos)
1945#define ADC_AWD3CR_AWD3CH_15 (0x08000UL << ADC_AWD3CR_AWD3CH_Pos)
1946#define ADC_AWD3CR_AWD3CH_16 (0x10000UL << ADC_AWD3CR_AWD3CH_Pos)
1947#define ADC_AWD3CR_AWD3CH_17 (0x20000UL << ADC_AWD3CR_AWD3CH_Pos)
1949/******************** Bit definition for ADC_DIFSEL register ****************/
1950#define ADC_DIFSEL_DIFSEL_Pos (1U)
1951#define ADC_DIFSEL_DIFSEL_Msk (0x3FFFFUL << ADC_DIFSEL_DIFSEL_Pos)
1952#define ADC_DIFSEL_DIFSEL ADC_DIFSEL_DIFSEL_Msk
1953#define ADC_DIFSEL_DIFSEL_0 (0x00001UL << ADC_DIFSEL_DIFSEL_Pos)
1954#define ADC_DIFSEL_DIFSEL_1 (0x00002UL << ADC_DIFSEL_DIFSEL_Pos)
1955#define ADC_DIFSEL_DIFSEL_2 (0x00004UL << ADC_DIFSEL_DIFSEL_Pos)
1956#define ADC_DIFSEL_DIFSEL_3 (0x00008UL << ADC_DIFSEL_DIFSEL_Pos)
1957#define ADC_DIFSEL_DIFSEL_4 (0x00010UL << ADC_DIFSEL_DIFSEL_Pos)
1958#define ADC_DIFSEL_DIFSEL_5 (0x00020UL << ADC_DIFSEL_DIFSEL_Pos)
1959#define ADC_DIFSEL_DIFSEL_6 (0x00040UL << ADC_DIFSEL_DIFSEL_Pos)
1960#define ADC_DIFSEL_DIFSEL_7 (0x00080UL << ADC_DIFSEL_DIFSEL_Pos)
1961#define ADC_DIFSEL_DIFSEL_8 (0x00100UL << ADC_DIFSEL_DIFSEL_Pos)
1962#define ADC_DIFSEL_DIFSEL_9 (0x00200UL << ADC_DIFSEL_DIFSEL_Pos)
1963#define ADC_DIFSEL_DIFSEL_10 (0x00400UL << ADC_DIFSEL_DIFSEL_Pos)
1964#define ADC_DIFSEL_DIFSEL_11 (0x00800UL << ADC_DIFSEL_DIFSEL_Pos)
1965#define ADC_DIFSEL_DIFSEL_12 (0x01000UL << ADC_DIFSEL_DIFSEL_Pos)
1966#define ADC_DIFSEL_DIFSEL_13 (0x02000UL << ADC_DIFSEL_DIFSEL_Pos)
1967#define ADC_DIFSEL_DIFSEL_14 (0x04000UL << ADC_DIFSEL_DIFSEL_Pos)
1968#define ADC_DIFSEL_DIFSEL_15 (0x08000UL << ADC_DIFSEL_DIFSEL_Pos)
1969#define ADC_DIFSEL_DIFSEL_16 (0x10000UL << ADC_DIFSEL_DIFSEL_Pos)
1970#define ADC_DIFSEL_DIFSEL_17 (0x20000UL << ADC_DIFSEL_DIFSEL_Pos)
1972/******************** Bit definition for ADC_CALFACT register ***************/
1973#define ADC_CALFACT_CALFACT_S_Pos (0U)
1974#define ADC_CALFACT_CALFACT_S_Msk (0x7FUL << ADC_CALFACT_CALFACT_S_Pos)
1975#define ADC_CALFACT_CALFACT_S ADC_CALFACT_CALFACT_S_Msk
1976#define ADC_CALFACT_CALFACT_S_0 (0x01UL << ADC_CALFACT_CALFACT_S_Pos)
1977#define ADC_CALFACT_CALFACT_S_1 (0x02UL << ADC_CALFACT_CALFACT_S_Pos)
1978#define ADC_CALFACT_CALFACT_S_2 (0x04UL << ADC_CALFACT_CALFACT_S_Pos)
1979#define ADC_CALFACT_CALFACT_S_3 (0x08UL << ADC_CALFACT_CALFACT_S_Pos)
1980#define ADC_CALFACT_CALFACT_S_4 (0x10UL << ADC_CALFACT_CALFACT_S_Pos)
1981#define ADC_CALFACT_CALFACT_S_5 (0x20UL << ADC_CALFACT_CALFACT_S_Pos)
1982#define ADC_CALFACT_CALFACT_S_6 (0x40UL << ADC_CALFACT_CALFACT_S_Pos)
1984#define ADC_CALFACT_CALFACT_D_Pos (16U)
1985#define ADC_CALFACT_CALFACT_D_Msk (0x7FUL << ADC_CALFACT_CALFACT_D_Pos)
1986#define ADC_CALFACT_CALFACT_D ADC_CALFACT_CALFACT_D_Msk
1987#define ADC_CALFACT_CALFACT_D_0 (0x01UL << ADC_CALFACT_CALFACT_D_Pos)
1988#define ADC_CALFACT_CALFACT_D_1 (0x02UL << ADC_CALFACT_CALFACT_D_Pos)
1989#define ADC_CALFACT_CALFACT_D_2 (0x04UL << ADC_CALFACT_CALFACT_D_Pos)
1990#define ADC_CALFACT_CALFACT_D_3 (0x08UL << ADC_CALFACT_CALFACT_D_Pos)
1991#define ADC_CALFACT_CALFACT_D_4 (0x10UL << ADC_CALFACT_CALFACT_D_Pos)
1992#define ADC_CALFACT_CALFACT_D_5 (0x20UL << ADC_CALFACT_CALFACT_D_Pos)
1993#define ADC_CALFACT_CALFACT_D_6 (0x40UL << ADC_CALFACT_CALFACT_D_Pos)
1995/************************* ADC Common registers *****************************/
1996/*************** Bit definition for ADC12_COMMON_CSR register ***************/
1997#define ADC12_CSR_ADRDY_MST_Pos (0U)
1998#define ADC12_CSR_ADRDY_MST_Msk (0x1UL << ADC12_CSR_ADRDY_MST_Pos)
1999#define ADC12_CSR_ADRDY_MST ADC12_CSR_ADRDY_MST_Msk
2000#define ADC12_CSR_ADRDY_EOSMP_MST_Pos (1U)
2001#define ADC12_CSR_ADRDY_EOSMP_MST_Msk (0x1UL << ADC12_CSR_ADRDY_EOSMP_MST_Pos)
2002#define ADC12_CSR_ADRDY_EOSMP_MST ADC12_CSR_ADRDY_EOSMP_MST_Msk
2003#define ADC12_CSR_ADRDY_EOC_MST_Pos (2U)
2004#define ADC12_CSR_ADRDY_EOC_MST_Msk (0x1UL << ADC12_CSR_ADRDY_EOC_MST_Pos)
2005#define ADC12_CSR_ADRDY_EOC_MST ADC12_CSR_ADRDY_EOC_MST_Msk
2006#define ADC12_CSR_ADRDY_EOS_MST_Pos (3U)
2007#define ADC12_CSR_ADRDY_EOS_MST_Msk (0x1UL << ADC12_CSR_ADRDY_EOS_MST_Pos)
2008#define ADC12_CSR_ADRDY_EOS_MST ADC12_CSR_ADRDY_EOS_MST_Msk
2009#define ADC12_CSR_ADRDY_OVR_MST_Pos (4U)
2010#define ADC12_CSR_ADRDY_OVR_MST_Msk (0x1UL << ADC12_CSR_ADRDY_OVR_MST_Pos)
2011#define ADC12_CSR_ADRDY_OVR_MST ADC12_CSR_ADRDY_OVR_MST_Msk
2012#define ADC12_CSR_ADRDY_JEOC_MST_Pos (5U)
2013#define ADC12_CSR_ADRDY_JEOC_MST_Msk (0x1UL << ADC12_CSR_ADRDY_JEOC_MST_Pos)
2014#define ADC12_CSR_ADRDY_JEOC_MST ADC12_CSR_ADRDY_JEOC_MST_Msk
2015#define ADC12_CSR_ADRDY_JEOS_MST_Pos (6U)
2016#define ADC12_CSR_ADRDY_JEOS_MST_Msk (0x1UL << ADC12_CSR_ADRDY_JEOS_MST_Pos)
2017#define ADC12_CSR_ADRDY_JEOS_MST ADC12_CSR_ADRDY_JEOS_MST_Msk
2018#define ADC12_CSR_AWD1_MST_Pos (7U)
2019#define ADC12_CSR_AWD1_MST_Msk (0x1UL << ADC12_CSR_AWD1_MST_Pos)
2020#define ADC12_CSR_AWD1_MST ADC12_CSR_AWD1_MST_Msk
2021#define ADC12_CSR_AWD2_MST_Pos (8U)
2022#define ADC12_CSR_AWD2_MST_Msk (0x1UL << ADC12_CSR_AWD2_MST_Pos)
2023#define ADC12_CSR_AWD2_MST ADC12_CSR_AWD2_MST_Msk
2024#define ADC12_CSR_AWD3_MST_Pos (9U)
2025#define ADC12_CSR_AWD3_MST_Msk (0x1UL << ADC12_CSR_AWD3_MST_Pos)
2026#define ADC12_CSR_AWD3_MST ADC12_CSR_AWD3_MST_Msk
2027#define ADC12_CSR_JQOVF_MST_Pos (10U)
2028#define ADC12_CSR_JQOVF_MST_Msk (0x1UL << ADC12_CSR_JQOVF_MST_Pos)
2029#define ADC12_CSR_JQOVF_MST ADC12_CSR_JQOVF_MST_Msk
2030#define ADC12_CSR_ADRDY_SLV_Pos (16U)
2031#define ADC12_CSR_ADRDY_SLV_Msk (0x1UL << ADC12_CSR_ADRDY_SLV_Pos)
2032#define ADC12_CSR_ADRDY_SLV ADC12_CSR_ADRDY_SLV_Msk
2033#define ADC12_CSR_ADRDY_EOSMP_SLV_Pos (17U)
2034#define ADC12_CSR_ADRDY_EOSMP_SLV_Msk (0x1UL << ADC12_CSR_ADRDY_EOSMP_SLV_Pos)
2035#define ADC12_CSR_ADRDY_EOSMP_SLV ADC12_CSR_ADRDY_EOSMP_SLV_Msk
2036#define ADC12_CSR_ADRDY_EOC_SLV_Pos (18U)
2037#define ADC12_CSR_ADRDY_EOC_SLV_Msk (0x1UL << ADC12_CSR_ADRDY_EOC_SLV_Pos)
2038#define ADC12_CSR_ADRDY_EOC_SLV ADC12_CSR_ADRDY_EOC_SLV_Msk
2039#define ADC12_CSR_ADRDY_EOS_SLV_Pos (19U)
2040#define ADC12_CSR_ADRDY_EOS_SLV_Msk (0x1UL << ADC12_CSR_ADRDY_EOS_SLV_Pos)
2041#define ADC12_CSR_ADRDY_EOS_SLV ADC12_CSR_ADRDY_EOS_SLV_Msk
2042#define ADC12_CSR_ADRDY_OVR_SLV_Pos (20U)
2043#define ADC12_CSR_ADRDY_OVR_SLV_Msk (0x1UL << ADC12_CSR_ADRDY_OVR_SLV_Pos)
2044#define ADC12_CSR_ADRDY_OVR_SLV ADC12_CSR_ADRDY_OVR_SLV_Msk
2045#define ADC12_CSR_ADRDY_JEOC_SLV_Pos (21U)
2046#define ADC12_CSR_ADRDY_JEOC_SLV_Msk (0x1UL << ADC12_CSR_ADRDY_JEOC_SLV_Pos)
2047#define ADC12_CSR_ADRDY_JEOC_SLV ADC12_CSR_ADRDY_JEOC_SLV_Msk
2048#define ADC12_CSR_ADRDY_JEOS_SLV_Pos (22U)
2049#define ADC12_CSR_ADRDY_JEOS_SLV_Msk (0x1UL << ADC12_CSR_ADRDY_JEOS_SLV_Pos)
2050#define ADC12_CSR_ADRDY_JEOS_SLV ADC12_CSR_ADRDY_JEOS_SLV_Msk
2051#define ADC12_CSR_AWD1_SLV_Pos (23U)
2052#define ADC12_CSR_AWD1_SLV_Msk (0x1UL << ADC12_CSR_AWD1_SLV_Pos)
2053#define ADC12_CSR_AWD1_SLV ADC12_CSR_AWD1_SLV_Msk
2054#define ADC12_CSR_AWD2_SLV_Pos (24U)
2055#define ADC12_CSR_AWD2_SLV_Msk (0x1UL << ADC12_CSR_AWD2_SLV_Pos)
2056#define ADC12_CSR_AWD2_SLV ADC12_CSR_AWD2_SLV_Msk
2057#define ADC12_CSR_AWD3_SLV_Pos (25U)
2058#define ADC12_CSR_AWD3_SLV_Msk (0x1UL << ADC12_CSR_AWD3_SLV_Pos)
2059#define ADC12_CSR_AWD3_SLV ADC12_CSR_AWD3_SLV_Msk
2060#define ADC12_CSR_JQOVF_SLV_Pos (26U)
2061#define ADC12_CSR_JQOVF_SLV_Msk (0x1UL << ADC12_CSR_JQOVF_SLV_Pos)
2062#define ADC12_CSR_JQOVF_SLV ADC12_CSR_JQOVF_SLV_Msk
2064/*************** Bit definition for ADC34_COMMON_CSR register ***************/
2065#define ADC34_CSR_ADRDY_MST_Pos (0U)
2066#define ADC34_CSR_ADRDY_MST_Msk (0x1UL << ADC34_CSR_ADRDY_MST_Pos)
2067#define ADC34_CSR_ADRDY_MST ADC34_CSR_ADRDY_MST_Msk
2068#define ADC34_CSR_ADRDY_EOSMP_MST_Pos (1U)
2069#define ADC34_CSR_ADRDY_EOSMP_MST_Msk (0x1UL << ADC34_CSR_ADRDY_EOSMP_MST_Pos)
2070#define ADC34_CSR_ADRDY_EOSMP_MST ADC34_CSR_ADRDY_EOSMP_MST_Msk
2071#define ADC34_CSR_ADRDY_EOC_MST_Pos (2U)
2072#define ADC34_CSR_ADRDY_EOC_MST_Msk (0x1UL << ADC34_CSR_ADRDY_EOC_MST_Pos)
2073#define ADC34_CSR_ADRDY_EOC_MST ADC34_CSR_ADRDY_EOC_MST_Msk
2074#define ADC34_CSR_ADRDY_EOS_MST_Pos (3U)
2075#define ADC34_CSR_ADRDY_EOS_MST_Msk (0x1UL << ADC34_CSR_ADRDY_EOS_MST_Pos)
2076#define ADC34_CSR_ADRDY_EOS_MST ADC34_CSR_ADRDY_EOS_MST_Msk
2077#define ADC34_CSR_ADRDY_OVR_MST_Pos (4U)
2078#define ADC34_CSR_ADRDY_OVR_MST_Msk (0x1UL << ADC34_CSR_ADRDY_OVR_MST_Pos)
2079#define ADC34_CSR_ADRDY_OVR_MST ADC34_CSR_ADRDY_OVR_MST_Msk
2080#define ADC34_CSR_ADRDY_JEOC_MST_Pos (5U)
2081#define ADC34_CSR_ADRDY_JEOC_MST_Msk (0x1UL << ADC34_CSR_ADRDY_JEOC_MST_Pos)
2082#define ADC34_CSR_ADRDY_JEOC_MST ADC34_CSR_ADRDY_JEOC_MST_Msk
2083#define ADC34_CSR_ADRDY_JEOS_MST_Pos (6U)
2084#define ADC34_CSR_ADRDY_JEOS_MST_Msk (0x1UL << ADC34_CSR_ADRDY_JEOS_MST_Pos)
2085#define ADC34_CSR_ADRDY_JEOS_MST ADC34_CSR_ADRDY_JEOS_MST_Msk
2086#define ADC34_CSR_AWD1_MST_Pos (7U)
2087#define ADC34_CSR_AWD1_MST_Msk (0x1UL << ADC34_CSR_AWD1_MST_Pos)
2088#define ADC34_CSR_AWD1_MST ADC34_CSR_AWD1_MST_Msk
2089#define ADC34_CSR_AWD2_MST_Pos (8U)
2090#define ADC34_CSR_AWD2_MST_Msk (0x1UL << ADC34_CSR_AWD2_MST_Pos)
2091#define ADC34_CSR_AWD2_MST ADC34_CSR_AWD2_MST_Msk
2092#define ADC34_CSR_AWD3_MST_Pos (9U)
2093#define ADC34_CSR_AWD3_MST_Msk (0x1UL << ADC34_CSR_AWD3_MST_Pos)
2094#define ADC34_CSR_AWD3_MST ADC34_CSR_AWD3_MST_Msk
2095#define ADC34_CSR_JQOVF_MST_Pos (10U)
2096#define ADC34_CSR_JQOVF_MST_Msk (0x1UL << ADC34_CSR_JQOVF_MST_Pos)
2097#define ADC34_CSR_JQOVF_MST ADC34_CSR_JQOVF_MST_Msk
2098#define ADC34_CSR_ADRDY_SLV_Pos (16U)
2099#define ADC34_CSR_ADRDY_SLV_Msk (0x1UL << ADC34_CSR_ADRDY_SLV_Pos)
2100#define ADC34_CSR_ADRDY_SLV ADC34_CSR_ADRDY_SLV_Msk
2101#define ADC34_CSR_ADRDY_EOSMP_SLV_Pos (17U)
2102#define ADC34_CSR_ADRDY_EOSMP_SLV_Msk (0x1UL << ADC34_CSR_ADRDY_EOSMP_SLV_Pos)
2103#define ADC34_CSR_ADRDY_EOSMP_SLV ADC34_CSR_ADRDY_EOSMP_SLV_Msk
2104#define ADC34_CSR_ADRDY_EOC_SLV_Pos (18U)
2105#define ADC34_CSR_ADRDY_EOC_SLV_Msk (0x1UL << ADC34_CSR_ADRDY_EOC_SLV_Pos)
2106#define ADC34_CSR_ADRDY_EOC_SLV ADC34_CSR_ADRDY_EOC_SLV_Msk
2107#define ADC34_CSR_ADRDY_EOS_SLV_Pos (19U)
2108#define ADC34_CSR_ADRDY_EOS_SLV_Msk (0x1UL << ADC34_CSR_ADRDY_EOS_SLV_Pos)
2109#define ADC34_CSR_ADRDY_EOS_SLV ADC34_CSR_ADRDY_EOS_SLV_Msk
2110#define ADC12_CSR_ADRDY_OVR_SLV_Pos (20U)
2111#define ADC12_CSR_ADRDY_OVR_SLV_Msk (0x1UL << ADC12_CSR_ADRDY_OVR_SLV_Pos)
2112#define ADC12_CSR_ADRDY_OVR_SLV ADC12_CSR_ADRDY_OVR_SLV_Msk
2113#define ADC34_CSR_ADRDY_JEOC_SLV_Pos (21U)
2114#define ADC34_CSR_ADRDY_JEOC_SLV_Msk (0x1UL << ADC34_CSR_ADRDY_JEOC_SLV_Pos)
2115#define ADC34_CSR_ADRDY_JEOC_SLV ADC34_CSR_ADRDY_JEOC_SLV_Msk
2116#define ADC34_CSR_ADRDY_JEOS_SLV_Pos (22U)
2117#define ADC34_CSR_ADRDY_JEOS_SLV_Msk (0x1UL << ADC34_CSR_ADRDY_JEOS_SLV_Pos)
2118#define ADC34_CSR_ADRDY_JEOS_SLV ADC34_CSR_ADRDY_JEOS_SLV_Msk
2119#define ADC34_CSR_AWD1_SLV_Pos (23U)
2120#define ADC34_CSR_AWD1_SLV_Msk (0x1UL << ADC34_CSR_AWD1_SLV_Pos)
2121#define ADC34_CSR_AWD1_SLV ADC34_CSR_AWD1_SLV_Msk
2122#define ADC34_CSR_AWD2_SLV_Pos (24U)
2123#define ADC34_CSR_AWD2_SLV_Msk (0x1UL << ADC34_CSR_AWD2_SLV_Pos)
2124#define ADC34_CSR_AWD2_SLV ADC34_CSR_AWD2_SLV_Msk
2125#define ADC34_CSR_AWD3_SLV_Pos (25U)
2126#define ADC34_CSR_AWD3_SLV_Msk (0x1UL << ADC34_CSR_AWD3_SLV_Pos)
2127#define ADC34_CSR_AWD3_SLV ADC34_CSR_AWD3_SLV_Msk
2128#define ADC34_CSR_JQOVF_SLV_Pos (26U)
2129#define ADC34_CSR_JQOVF_SLV_Msk (0x1UL << ADC34_CSR_JQOVF_SLV_Pos)
2130#define ADC34_CSR_JQOVF_SLV ADC34_CSR_JQOVF_SLV_Msk
2132/*************** Bit definition for ADC12_COMMON_CCR register ***************/
2133#define ADC12_CCR_MULTI_Pos (0U)
2134#define ADC12_CCR_MULTI_Msk (0x1FUL << ADC12_CCR_MULTI_Pos)
2135#define ADC12_CCR_MULTI ADC12_CCR_MULTI_Msk
2136#define ADC12_CCR_MULTI_0 (0x01UL << ADC12_CCR_MULTI_Pos)
2137#define ADC12_CCR_MULTI_1 (0x02UL << ADC12_CCR_MULTI_Pos)
2138#define ADC12_CCR_MULTI_2 (0x04UL << ADC12_CCR_MULTI_Pos)
2139#define ADC12_CCR_MULTI_3 (0x08UL << ADC12_CCR_MULTI_Pos)
2140#define ADC12_CCR_MULTI_4 (0x10UL << ADC12_CCR_MULTI_Pos)
2141#define ADC12_CCR_DELAY_Pos (8U)
2142#define ADC12_CCR_DELAY_Msk (0xFUL << ADC12_CCR_DELAY_Pos)
2143#define ADC12_CCR_DELAY ADC12_CCR_DELAY_Msk
2144#define ADC12_CCR_DELAY_0 (0x1UL << ADC12_CCR_DELAY_Pos)
2145#define ADC12_CCR_DELAY_1 (0x2UL << ADC12_CCR_DELAY_Pos)
2146#define ADC12_CCR_DELAY_2 (0x4UL << ADC12_CCR_DELAY_Pos)
2147#define ADC12_CCR_DELAY_3 (0x8UL << ADC12_CCR_DELAY_Pos)
2148#define ADC12_CCR_DMACFG_Pos (13U)
2149#define ADC12_CCR_DMACFG_Msk (0x1UL << ADC12_CCR_DMACFG_Pos)
2150#define ADC12_CCR_DMACFG ADC12_CCR_DMACFG_Msk
2151#define ADC12_CCR_MDMA_Pos (14U)
2152#define ADC12_CCR_MDMA_Msk (0x3UL << ADC12_CCR_MDMA_Pos)
2153#define ADC12_CCR_MDMA ADC12_CCR_MDMA_Msk
2154#define ADC12_CCR_MDMA_0 (0x1UL << ADC12_CCR_MDMA_Pos)
2155#define ADC12_CCR_MDMA_1 (0x2UL << ADC12_CCR_MDMA_Pos)
2156#define ADC12_CCR_CKMODE_Pos (16U)
2157#define ADC12_CCR_CKMODE_Msk (0x3UL << ADC12_CCR_CKMODE_Pos)
2158#define ADC12_CCR_CKMODE ADC12_CCR_CKMODE_Msk
2159#define ADC12_CCR_CKMODE_0 (0x1UL << ADC12_CCR_CKMODE_Pos)
2160#define ADC12_CCR_CKMODE_1 (0x2UL << ADC12_CCR_CKMODE_Pos)
2161#define ADC12_CCR_VREFEN_Pos (22U)
2162#define ADC12_CCR_VREFEN_Msk (0x1UL << ADC12_CCR_VREFEN_Pos)
2163#define ADC12_CCR_VREFEN ADC12_CCR_VREFEN_Msk
2164#define ADC12_CCR_TSEN_Pos (23U)
2165#define ADC12_CCR_TSEN_Msk (0x1UL << ADC12_CCR_TSEN_Pos)
2166#define ADC12_CCR_TSEN ADC12_CCR_TSEN_Msk
2167#define ADC12_CCR_VBATEN_Pos (24U)
2168#define ADC12_CCR_VBATEN_Msk (0x1UL << ADC12_CCR_VBATEN_Pos)
2169#define ADC12_CCR_VBATEN ADC12_CCR_VBATEN_Msk
2171/*************** Bit definition for ADC34_COMMON_CCR register ***************/
2172#define ADC34_CCR_MULTI_Pos (0U)
2173#define ADC34_CCR_MULTI_Msk (0x1FUL << ADC34_CCR_MULTI_Pos)
2174#define ADC34_CCR_MULTI ADC34_CCR_MULTI_Msk
2175#define ADC34_CCR_MULTI_0 (0x01UL << ADC34_CCR_MULTI_Pos)
2176#define ADC34_CCR_MULTI_1 (0x02UL << ADC34_CCR_MULTI_Pos)
2177#define ADC34_CCR_MULTI_2 (0x04UL << ADC34_CCR_MULTI_Pos)
2178#define ADC34_CCR_MULTI_3 (0x08UL << ADC34_CCR_MULTI_Pos)
2179#define ADC34_CCR_MULTI_4 (0x10UL << ADC34_CCR_MULTI_Pos)
2181#define ADC34_CCR_DELAY_Pos (8U)
2182#define ADC34_CCR_DELAY_Msk (0xFUL << ADC34_CCR_DELAY_Pos)
2183#define ADC34_CCR_DELAY ADC34_CCR_DELAY_Msk
2184#define ADC34_CCR_DELAY_0 (0x1UL << ADC34_CCR_DELAY_Pos)
2185#define ADC34_CCR_DELAY_1 (0x2UL << ADC34_CCR_DELAY_Pos)
2186#define ADC34_CCR_DELAY_2 (0x4UL << ADC34_CCR_DELAY_Pos)
2187#define ADC34_CCR_DELAY_3 (0x8UL << ADC34_CCR_DELAY_Pos)
2189#define ADC34_CCR_DMACFG_Pos (13U)
2190#define ADC34_CCR_DMACFG_Msk (0x1UL << ADC34_CCR_DMACFG_Pos)
2191#define ADC34_CCR_DMACFG ADC34_CCR_DMACFG_Msk
2192#define ADC34_CCR_MDMA_Pos (14U)
2193#define ADC34_CCR_MDMA_Msk (0x3UL << ADC34_CCR_MDMA_Pos)
2194#define ADC34_CCR_MDMA ADC34_CCR_MDMA_Msk
2195#define ADC34_CCR_MDMA_0 (0x1UL << ADC34_CCR_MDMA_Pos)
2196#define ADC34_CCR_MDMA_1 (0x2UL << ADC34_CCR_MDMA_Pos)
2198#define ADC34_CCR_CKMODE_Pos (16U)
2199#define ADC34_CCR_CKMODE_Msk (0x3UL << ADC34_CCR_CKMODE_Pos)
2200#define ADC34_CCR_CKMODE ADC34_CCR_CKMODE_Msk
2201#define ADC34_CCR_CKMODE_0 (0x1UL << ADC34_CCR_CKMODE_Pos)
2202#define ADC34_CCR_CKMODE_1 (0x2UL << ADC34_CCR_CKMODE_Pos)
2204#define ADC34_CCR_VREFEN_Pos (22U)
2205#define ADC34_CCR_VREFEN_Msk (0x1UL << ADC34_CCR_VREFEN_Pos)
2206#define ADC34_CCR_VREFEN ADC34_CCR_VREFEN_Msk
2207#define ADC34_CCR_TSEN_Pos (23U)
2208#define ADC34_CCR_TSEN_Msk (0x1UL << ADC34_CCR_TSEN_Pos)
2209#define ADC34_CCR_TSEN ADC34_CCR_TSEN_Msk
2210#define ADC34_CCR_VBATEN_Pos (24U)
2211#define ADC34_CCR_VBATEN_Msk (0x1UL << ADC34_CCR_VBATEN_Pos)
2212#define ADC34_CCR_VBATEN ADC34_CCR_VBATEN_Msk
2214/*************** Bit definition for ADC12_COMMON_CDR register ***************/
2215#define ADC12_CDR_RDATA_MST_Pos (0U)
2216#define ADC12_CDR_RDATA_MST_Msk (0xFFFFUL << ADC12_CDR_RDATA_MST_Pos)
2217#define ADC12_CDR_RDATA_MST ADC12_CDR_RDATA_MST_Msk
2218#define ADC12_CDR_RDATA_MST_0 (0x0001UL << ADC12_CDR_RDATA_MST_Pos)
2219#define ADC12_CDR_RDATA_MST_1 (0x0002UL << ADC12_CDR_RDATA_MST_Pos)
2220#define ADC12_CDR_RDATA_MST_2 (0x0004UL << ADC12_CDR_RDATA_MST_Pos)
2221#define ADC12_CDR_RDATA_MST_3 (0x0008UL << ADC12_CDR_RDATA_MST_Pos)
2222#define ADC12_CDR_RDATA_MST_4 (0x0010UL << ADC12_CDR_RDATA_MST_Pos)
2223#define ADC12_CDR_RDATA_MST_5 (0x0020UL << ADC12_CDR_RDATA_MST_Pos)
2224#define ADC12_CDR_RDATA_MST_6 (0x0040UL << ADC12_CDR_RDATA_MST_Pos)
2225#define ADC12_CDR_RDATA_MST_7 (0x0080UL << ADC12_CDR_RDATA_MST_Pos)
2226#define ADC12_CDR_RDATA_MST_8 (0x0100UL << ADC12_CDR_RDATA_MST_Pos)
2227#define ADC12_CDR_RDATA_MST_9 (0x0200UL << ADC12_CDR_RDATA_MST_Pos)
2228#define ADC12_CDR_RDATA_MST_10 (0x0400UL << ADC12_CDR_RDATA_MST_Pos)
2229#define ADC12_CDR_RDATA_MST_11 (0x0800UL << ADC12_CDR_RDATA_MST_Pos)
2230#define ADC12_CDR_RDATA_MST_12 (0x1000UL << ADC12_CDR_RDATA_MST_Pos)
2231#define ADC12_CDR_RDATA_MST_13 (0x2000UL << ADC12_CDR_RDATA_MST_Pos)
2232#define ADC12_CDR_RDATA_MST_14 (0x4000UL << ADC12_CDR_RDATA_MST_Pos)
2233#define ADC12_CDR_RDATA_MST_15 (0x8000UL << ADC12_CDR_RDATA_MST_Pos)
2235#define ADC12_CDR_RDATA_SLV_Pos (16U)
2236#define ADC12_CDR_RDATA_SLV_Msk (0xFFFFUL << ADC12_CDR_RDATA_SLV_Pos)
2237#define ADC12_CDR_RDATA_SLV ADC12_CDR_RDATA_SLV_Msk
2238#define ADC12_CDR_RDATA_SLV_0 (0x0001UL << ADC12_CDR_RDATA_SLV_Pos)
2239#define ADC12_CDR_RDATA_SLV_1 (0x0002UL << ADC12_CDR_RDATA_SLV_Pos)
2240#define ADC12_CDR_RDATA_SLV_2 (0x0004UL << ADC12_CDR_RDATA_SLV_Pos)
2241#define ADC12_CDR_RDATA_SLV_3 (0x0008UL << ADC12_CDR_RDATA_SLV_Pos)
2242#define ADC12_CDR_RDATA_SLV_4 (0x0010UL << ADC12_CDR_RDATA_SLV_Pos)
2243#define ADC12_CDR_RDATA_SLV_5 (0x0020UL << ADC12_CDR_RDATA_SLV_Pos)
2244#define ADC12_CDR_RDATA_SLV_6 (0x0040UL << ADC12_CDR_RDATA_SLV_Pos)
2245#define ADC12_CDR_RDATA_SLV_7 (0x0080UL << ADC12_CDR_RDATA_SLV_Pos)
2246#define ADC12_CDR_RDATA_SLV_8 (0x0100UL << ADC12_CDR_RDATA_SLV_Pos)
2247#define ADC12_CDR_RDATA_SLV_9 (0x0200UL << ADC12_CDR_RDATA_SLV_Pos)
2248#define ADC12_CDR_RDATA_SLV_10 (0x0400UL << ADC12_CDR_RDATA_SLV_Pos)
2249#define ADC12_CDR_RDATA_SLV_11 (0x0800UL << ADC12_CDR_RDATA_SLV_Pos)
2250#define ADC12_CDR_RDATA_SLV_12 (0x1000UL << ADC12_CDR_RDATA_SLV_Pos)
2251#define ADC12_CDR_RDATA_SLV_13 (0x2000UL << ADC12_CDR_RDATA_SLV_Pos)
2252#define ADC12_CDR_RDATA_SLV_14 (0x4000UL << ADC12_CDR_RDATA_SLV_Pos)
2253#define ADC12_CDR_RDATA_SLV_15 (0x8000UL << ADC12_CDR_RDATA_SLV_Pos)
2255/*************** Bit definition for ADC34_COMMON_CDR register ***************/
2256#define ADC34_CDR_RDATA_MST_Pos (0U)
2257#define ADC34_CDR_RDATA_MST_Msk (0xFFFFUL << ADC34_CDR_RDATA_MST_Pos)
2258#define ADC34_CDR_RDATA_MST ADC34_CDR_RDATA_MST_Msk
2259#define ADC34_CDR_RDATA_MST_0 (0x0001UL << ADC34_CDR_RDATA_MST_Pos)
2260#define ADC34_CDR_RDATA_MST_1 (0x0002UL << ADC34_CDR_RDATA_MST_Pos)
2261#define ADC34_CDR_RDATA_MST_2 (0x0004UL << ADC34_CDR_RDATA_MST_Pos)
2262#define ADC34_CDR_RDATA_MST_3 (0x0008UL << ADC34_CDR_RDATA_MST_Pos)
2263#define ADC34_CDR_RDATA_MST_4 (0x0010UL << ADC34_CDR_RDATA_MST_Pos)
2264#define ADC34_CDR_RDATA_MST_5 (0x0020UL << ADC34_CDR_RDATA_MST_Pos)
2265#define ADC34_CDR_RDATA_MST_6 (0x0040UL << ADC34_CDR_RDATA_MST_Pos)
2266#define ADC34_CDR_RDATA_MST_7 (0x0080UL << ADC34_CDR_RDATA_MST_Pos)
2267#define ADC34_CDR_RDATA_MST_8 (0x0100UL << ADC34_CDR_RDATA_MST_Pos)
2268#define ADC34_CDR_RDATA_MST_9 (0x0200UL << ADC34_CDR_RDATA_MST_Pos)
2269#define ADC34_CDR_RDATA_MST_10 (0x0400UL << ADC34_CDR_RDATA_MST_Pos)
2270#define ADC34_CDR_RDATA_MST_11 (0x0800UL << ADC34_CDR_RDATA_MST_Pos)
2271#define ADC34_CDR_RDATA_MST_12 (0x1000UL << ADC34_CDR_RDATA_MST_Pos)
2272#define ADC34_CDR_RDATA_MST_13 (0x2000UL << ADC34_CDR_RDATA_MST_Pos)
2273#define ADC34_CDR_RDATA_MST_14 (0x4000UL << ADC34_CDR_RDATA_MST_Pos)
2274#define ADC34_CDR_RDATA_MST_15 (0x8000UL << ADC34_CDR_RDATA_MST_Pos)
2276#define ADC34_CDR_RDATA_SLV_Pos (16U)
2277#define ADC34_CDR_RDATA_SLV_Msk (0xFFFFUL << ADC34_CDR_RDATA_SLV_Pos)
2278#define ADC34_CDR_RDATA_SLV ADC34_CDR_RDATA_SLV_Msk
2279#define ADC34_CDR_RDATA_SLV_0 (0x0001UL << ADC34_CDR_RDATA_SLV_Pos)
2280#define ADC34_CDR_RDATA_SLV_1 (0x0002UL << ADC34_CDR_RDATA_SLV_Pos)
2281#define ADC34_CDR_RDATA_SLV_2 (0x0004UL << ADC34_CDR_RDATA_SLV_Pos)
2282#define ADC34_CDR_RDATA_SLV_3 (0x0008UL << ADC34_CDR_RDATA_SLV_Pos)
2283#define ADC34_CDR_RDATA_SLV_4 (0x0010UL << ADC34_CDR_RDATA_SLV_Pos)
2284#define ADC34_CDR_RDATA_SLV_5 (0x0020UL << ADC34_CDR_RDATA_SLV_Pos)
2285#define ADC34_CDR_RDATA_SLV_6 (0x0040UL << ADC34_CDR_RDATA_SLV_Pos)
2286#define ADC34_CDR_RDATA_SLV_7 (0x0080UL << ADC34_CDR_RDATA_SLV_Pos)
2287#define ADC34_CDR_RDATA_SLV_8 (0x0100UL << ADC34_CDR_RDATA_SLV_Pos)
2288#define ADC34_CDR_RDATA_SLV_9 (0x0200UL << ADC34_CDR_RDATA_SLV_Pos)
2289#define ADC34_CDR_RDATA_SLV_10 (0x0400UL << ADC34_CDR_RDATA_SLV_Pos)
2290#define ADC34_CDR_RDATA_SLV_11 (0x0800UL << ADC34_CDR_RDATA_SLV_Pos)
2291#define ADC34_CDR_RDATA_SLV_12 (0x1000UL << ADC34_CDR_RDATA_SLV_Pos)
2292#define ADC34_CDR_RDATA_SLV_13 (0x2000UL << ADC34_CDR_RDATA_SLV_Pos)
2293#define ADC34_CDR_RDATA_SLV_14 (0x4000UL << ADC34_CDR_RDATA_SLV_Pos)
2294#define ADC34_CDR_RDATA_SLV_15 (0x8000UL << ADC34_CDR_RDATA_SLV_Pos)
2296/******************** Bit definition for ADC_CSR register *******************/
2297#define ADC_CSR_ADRDY_MST_Pos (0U)
2298#define ADC_CSR_ADRDY_MST_Msk (0x1UL << ADC_CSR_ADRDY_MST_Pos)
2299#define ADC_CSR_ADRDY_MST ADC_CSR_ADRDY_MST_Msk
2300#define ADC_CSR_EOSMP_MST_Pos (1U)
2301#define ADC_CSR_EOSMP_MST_Msk (0x1UL << ADC_CSR_EOSMP_MST_Pos)
2302#define ADC_CSR_EOSMP_MST ADC_CSR_EOSMP_MST_Msk
2303#define ADC_CSR_EOC_MST_Pos (2U)
2304#define ADC_CSR_EOC_MST_Msk (0x1UL << ADC_CSR_EOC_MST_Pos)
2305#define ADC_CSR_EOC_MST ADC_CSR_EOC_MST_Msk
2306#define ADC_CSR_EOS_MST_Pos (3U)
2307#define ADC_CSR_EOS_MST_Msk (0x1UL << ADC_CSR_EOS_MST_Pos)
2308#define ADC_CSR_EOS_MST ADC_CSR_EOS_MST_Msk
2309#define ADC_CSR_OVR_MST_Pos (4U)
2310#define ADC_CSR_OVR_MST_Msk (0x1UL << ADC_CSR_OVR_MST_Pos)
2311#define ADC_CSR_OVR_MST ADC_CSR_OVR_MST_Msk
2312#define ADC_CSR_JEOC_MST_Pos (5U)
2313#define ADC_CSR_JEOC_MST_Msk (0x1UL << ADC_CSR_JEOC_MST_Pos)
2314#define ADC_CSR_JEOC_MST ADC_CSR_JEOC_MST_Msk
2315#define ADC_CSR_JEOS_MST_Pos (6U)
2316#define ADC_CSR_JEOS_MST_Msk (0x1UL << ADC_CSR_JEOS_MST_Pos)
2317#define ADC_CSR_JEOS_MST ADC_CSR_JEOS_MST_Msk
2318#define ADC_CSR_AWD1_MST_Pos (7U)
2319#define ADC_CSR_AWD1_MST_Msk (0x1UL << ADC_CSR_AWD1_MST_Pos)
2320#define ADC_CSR_AWD1_MST ADC_CSR_AWD1_MST_Msk
2321#define ADC_CSR_AWD2_MST_Pos (8U)
2322#define ADC_CSR_AWD2_MST_Msk (0x1UL << ADC_CSR_AWD2_MST_Pos)
2323#define ADC_CSR_AWD2_MST ADC_CSR_AWD2_MST_Msk
2324#define ADC_CSR_AWD3_MST_Pos (9U)
2325#define ADC_CSR_AWD3_MST_Msk (0x1UL << ADC_CSR_AWD3_MST_Pos)
2326#define ADC_CSR_AWD3_MST ADC_CSR_AWD3_MST_Msk
2327#define ADC_CSR_JQOVF_MST_Pos (10U)
2328#define ADC_CSR_JQOVF_MST_Msk (0x1UL << ADC_CSR_JQOVF_MST_Pos)
2329#define ADC_CSR_JQOVF_MST ADC_CSR_JQOVF_MST_Msk
2331#define ADC_CSR_ADRDY_SLV_Pos (16U)
2332#define ADC_CSR_ADRDY_SLV_Msk (0x1UL << ADC_CSR_ADRDY_SLV_Pos)
2333#define ADC_CSR_ADRDY_SLV ADC_CSR_ADRDY_SLV_Msk
2334#define ADC_CSR_EOSMP_SLV_Pos (17U)
2335#define ADC_CSR_EOSMP_SLV_Msk (0x1UL << ADC_CSR_EOSMP_SLV_Pos)
2336#define ADC_CSR_EOSMP_SLV ADC_CSR_EOSMP_SLV_Msk
2337#define ADC_CSR_EOC_SLV_Pos (18U)
2338#define ADC_CSR_EOC_SLV_Msk (0x1UL << ADC_CSR_EOC_SLV_Pos)
2339#define ADC_CSR_EOC_SLV ADC_CSR_EOC_SLV_Msk
2340#define ADC_CSR_EOS_SLV_Pos (19U)
2341#define ADC_CSR_EOS_SLV_Msk (0x1UL << ADC_CSR_EOS_SLV_Pos)
2342#define ADC_CSR_EOS_SLV ADC_CSR_EOS_SLV_Msk
2343#define ADC_CSR_OVR_SLV_Pos (20U)
2344#define ADC_CSR_OVR_SLV_Msk (0x1UL << ADC_CSR_OVR_SLV_Pos)
2345#define ADC_CSR_OVR_SLV ADC_CSR_OVR_SLV_Msk
2346#define ADC_CSR_JEOC_SLV_Pos (21U)
2347#define ADC_CSR_JEOC_SLV_Msk (0x1UL << ADC_CSR_JEOC_SLV_Pos)
2348#define ADC_CSR_JEOC_SLV ADC_CSR_JEOC_SLV_Msk
2349#define ADC_CSR_JEOS_SLV_Pos (22U)
2350#define ADC_CSR_JEOS_SLV_Msk (0x1UL << ADC_CSR_JEOS_SLV_Pos)
2351#define ADC_CSR_JEOS_SLV ADC_CSR_JEOS_SLV_Msk
2352#define ADC_CSR_AWD1_SLV_Pos (23U)
2353#define ADC_CSR_AWD1_SLV_Msk (0x1UL << ADC_CSR_AWD1_SLV_Pos)
2354#define ADC_CSR_AWD1_SLV ADC_CSR_AWD1_SLV_Msk
2355#define ADC_CSR_AWD2_SLV_Pos (24U)
2356#define ADC_CSR_AWD2_SLV_Msk (0x1UL << ADC_CSR_AWD2_SLV_Pos)
2357#define ADC_CSR_AWD2_SLV ADC_CSR_AWD2_SLV_Msk
2358#define ADC_CSR_AWD3_SLV_Pos (25U)
2359#define ADC_CSR_AWD3_SLV_Msk (0x1UL << ADC_CSR_AWD3_SLV_Pos)
2360#define ADC_CSR_AWD3_SLV ADC_CSR_AWD3_SLV_Msk
2361#define ADC_CSR_JQOVF_SLV_Pos (26U)
2362#define ADC_CSR_JQOVF_SLV_Msk (0x1UL << ADC_CSR_JQOVF_SLV_Pos)
2363#define ADC_CSR_JQOVF_SLV ADC_CSR_JQOVF_SLV_Msk
2365/* Legacy defines */
2366#define ADC_CSR_ADRDY_EOSMP_MST ADC_CSR_EOSMP_MST
2367#define ADC_CSR_ADRDY_EOC_MST ADC_CSR_EOC_MST
2368#define ADC_CSR_ADRDY_EOS_MST ADC_CSR_EOS_MST
2369#define ADC_CSR_ADRDY_OVR_MST ADC_CSR_OVR_MST
2370#define ADC_CSR_ADRDY_JEOC_MST ADC_CSR_JEOC_MST
2371#define ADC_CSR_ADRDY_JEOS_MST ADC_CSR_JEOS_MST
2372
2373#define ADC_CSR_ADRDY_EOSMP_SLV ADC_CSR_EOSMP_SLV
2374#define ADC_CSR_ADRDY_EOC_SLV ADC_CSR_EOC_SLV
2375#define ADC_CSR_ADRDY_EOS_SLV ADC_CSR_EOS_SLV
2376#define ADC_CSR_ADRDY_OVR_SLV ADC_CSR_OVR_SLV
2377#define ADC_CSR_ADRDY_JEOC_SLV ADC_CSR_JEOC_SLV
2378#define ADC_CSR_ADRDY_JEOS_SLV ADC_CSR_JEOS_SLV
2379
2380/******************** Bit definition for ADC_CCR register *******************/
2381#define ADC_CCR_DUAL_Pos (0U)
2382#define ADC_CCR_DUAL_Msk (0x1FUL << ADC_CCR_DUAL_Pos)
2383#define ADC_CCR_DUAL ADC_CCR_DUAL_Msk
2384#define ADC_CCR_DUAL_0 (0x01UL << ADC_CCR_DUAL_Pos)
2385#define ADC_CCR_DUAL_1 (0x02UL << ADC_CCR_DUAL_Pos)
2386#define ADC_CCR_DUAL_2 (0x04UL << ADC_CCR_DUAL_Pos)
2387#define ADC_CCR_DUAL_3 (0x08UL << ADC_CCR_DUAL_Pos)
2388#define ADC_CCR_DUAL_4 (0x10UL << ADC_CCR_DUAL_Pos)
2390#define ADC_CCR_DELAY_Pos (8U)
2391#define ADC_CCR_DELAY_Msk (0xFUL << ADC_CCR_DELAY_Pos)
2392#define ADC_CCR_DELAY ADC_CCR_DELAY_Msk
2393#define ADC_CCR_DELAY_0 (0x1UL << ADC_CCR_DELAY_Pos)
2394#define ADC_CCR_DELAY_1 (0x2UL << ADC_CCR_DELAY_Pos)
2395#define ADC_CCR_DELAY_2 (0x4UL << ADC_CCR_DELAY_Pos)
2396#define ADC_CCR_DELAY_3 (0x8UL << ADC_CCR_DELAY_Pos)
2398#define ADC_CCR_DMACFG_Pos (13U)
2399#define ADC_CCR_DMACFG_Msk (0x1UL << ADC_CCR_DMACFG_Pos)
2400#define ADC_CCR_DMACFG ADC_CCR_DMACFG_Msk
2402#define ADC_CCR_MDMA_Pos (14U)
2403#define ADC_CCR_MDMA_Msk (0x3UL << ADC_CCR_MDMA_Pos)
2404#define ADC_CCR_MDMA ADC_CCR_MDMA_Msk
2405#define ADC_CCR_MDMA_0 (0x1UL << ADC_CCR_MDMA_Pos)
2406#define ADC_CCR_MDMA_1 (0x2UL << ADC_CCR_MDMA_Pos)
2408#define ADC_CCR_CKMODE_Pos (16U)
2409#define ADC_CCR_CKMODE_Msk (0x3UL << ADC_CCR_CKMODE_Pos)
2410#define ADC_CCR_CKMODE ADC_CCR_CKMODE_Msk
2411#define ADC_CCR_CKMODE_0 (0x1UL << ADC_CCR_CKMODE_Pos)
2412#define ADC_CCR_CKMODE_1 (0x2UL << ADC_CCR_CKMODE_Pos)
2414#define ADC_CCR_VREFEN_Pos (22U)
2415#define ADC_CCR_VREFEN_Msk (0x1UL << ADC_CCR_VREFEN_Pos)
2416#define ADC_CCR_VREFEN ADC_CCR_VREFEN_Msk
2417#define ADC_CCR_TSEN_Pos (23U)
2418#define ADC_CCR_TSEN_Msk (0x1UL << ADC_CCR_TSEN_Pos)
2419#define ADC_CCR_TSEN ADC_CCR_TSEN_Msk
2420#define ADC_CCR_VBATEN_Pos (24U)
2421#define ADC_CCR_VBATEN_Msk (0x1UL << ADC_CCR_VBATEN_Pos)
2422#define ADC_CCR_VBATEN ADC_CCR_VBATEN_Msk
2424/* Legacy defines */
2425#define ADC_CCR_MULTI (ADC_CCR_DUAL)
2426#define ADC_CCR_MULTI_0 (ADC_CCR_DUAL_0)
2427#define ADC_CCR_MULTI_1 (ADC_CCR_DUAL_1)
2428#define ADC_CCR_MULTI_2 (ADC_CCR_DUAL_2)
2429#define ADC_CCR_MULTI_3 (ADC_CCR_DUAL_3)
2430#define ADC_CCR_MULTI_4 (ADC_CCR_DUAL_4)
2431
2432/******************** Bit definition for ADC_CDR register *******************/
2433#define ADC_CDR_RDATA_MST_Pos (0U)
2434#define ADC_CDR_RDATA_MST_Msk (0xFFFFUL << ADC_CDR_RDATA_MST_Pos)
2435#define ADC_CDR_RDATA_MST ADC_CDR_RDATA_MST_Msk
2436#define ADC_CDR_RDATA_MST_0 (0x0001UL << ADC_CDR_RDATA_MST_Pos)
2437#define ADC_CDR_RDATA_MST_1 (0x0002UL << ADC_CDR_RDATA_MST_Pos)
2438#define ADC_CDR_RDATA_MST_2 (0x0004UL << ADC_CDR_RDATA_MST_Pos)
2439#define ADC_CDR_RDATA_MST_3 (0x0008UL << ADC_CDR_RDATA_MST_Pos)
2440#define ADC_CDR_RDATA_MST_4 (0x0010UL << ADC_CDR_RDATA_MST_Pos)
2441#define ADC_CDR_RDATA_MST_5 (0x0020UL << ADC_CDR_RDATA_MST_Pos)
2442#define ADC_CDR_RDATA_MST_6 (0x0040UL << ADC_CDR_RDATA_MST_Pos)
2443#define ADC_CDR_RDATA_MST_7 (0x0080UL << ADC_CDR_RDATA_MST_Pos)
2444#define ADC_CDR_RDATA_MST_8 (0x0100UL << ADC_CDR_RDATA_MST_Pos)
2445#define ADC_CDR_RDATA_MST_9 (0x0200UL << ADC_CDR_RDATA_MST_Pos)
2446#define ADC_CDR_RDATA_MST_10 (0x0400UL << ADC_CDR_RDATA_MST_Pos)
2447#define ADC_CDR_RDATA_MST_11 (0x0800UL << ADC_CDR_RDATA_MST_Pos)
2448#define ADC_CDR_RDATA_MST_12 (0x1000UL << ADC_CDR_RDATA_MST_Pos)
2449#define ADC_CDR_RDATA_MST_13 (0x2000UL << ADC_CDR_RDATA_MST_Pos)
2450#define ADC_CDR_RDATA_MST_14 (0x4000UL << ADC_CDR_RDATA_MST_Pos)
2451#define ADC_CDR_RDATA_MST_15 (0x8000UL << ADC_CDR_RDATA_MST_Pos)
2453#define ADC_CDR_RDATA_SLV_Pos (16U)
2454#define ADC_CDR_RDATA_SLV_Msk (0xFFFFUL << ADC_CDR_RDATA_SLV_Pos)
2455#define ADC_CDR_RDATA_SLV ADC_CDR_RDATA_SLV_Msk
2456#define ADC_CDR_RDATA_SLV_0 (0x0001UL << ADC_CDR_RDATA_SLV_Pos)
2457#define ADC_CDR_RDATA_SLV_1 (0x0002UL << ADC_CDR_RDATA_SLV_Pos)
2458#define ADC_CDR_RDATA_SLV_2 (0x0004UL << ADC_CDR_RDATA_SLV_Pos)
2459#define ADC_CDR_RDATA_SLV_3 (0x0008UL << ADC_CDR_RDATA_SLV_Pos)
2460#define ADC_CDR_RDATA_SLV_4 (0x0010UL << ADC_CDR_RDATA_SLV_Pos)
2461#define ADC_CDR_RDATA_SLV_5 (0x0020UL << ADC_CDR_RDATA_SLV_Pos)
2462#define ADC_CDR_RDATA_SLV_6 (0x0040UL << ADC_CDR_RDATA_SLV_Pos)
2463#define ADC_CDR_RDATA_SLV_7 (0x0080UL << ADC_CDR_RDATA_SLV_Pos)
2464#define ADC_CDR_RDATA_SLV_8 (0x0100UL << ADC_CDR_RDATA_SLV_Pos)
2465#define ADC_CDR_RDATA_SLV_9 (0x0200UL << ADC_CDR_RDATA_SLV_Pos)
2466#define ADC_CDR_RDATA_SLV_10 (0x0400UL << ADC_CDR_RDATA_SLV_Pos)
2467#define ADC_CDR_RDATA_SLV_11 (0x0800UL << ADC_CDR_RDATA_SLV_Pos)
2468#define ADC_CDR_RDATA_SLV_12 (0x1000UL << ADC_CDR_RDATA_SLV_Pos)
2469#define ADC_CDR_RDATA_SLV_13 (0x2000UL << ADC_CDR_RDATA_SLV_Pos)
2470#define ADC_CDR_RDATA_SLV_14 (0x4000UL << ADC_CDR_RDATA_SLV_Pos)
2471#define ADC_CDR_RDATA_SLV_15 (0x8000UL << ADC_CDR_RDATA_SLV_Pos)
2473/******************************************************************************/
2474/* */
2475/* Analog Comparators (COMP) */
2476/* */
2477/******************************************************************************/
2478
2479#define COMP_V1_3_0_0
2481/********************** Bit definition for COMP1_CSR register ***************/
2482#define COMP1_CSR_COMP1EN_Pos (0U)
2483#define COMP1_CSR_COMP1EN_Msk (0x1UL << COMP1_CSR_COMP1EN_Pos)
2484#define COMP1_CSR_COMP1EN COMP1_CSR_COMP1EN_Msk
2485#define COMP1_CSR_COMP1SW1_Pos (1U)
2486#define COMP1_CSR_COMP1SW1_Msk (0x1UL << COMP1_CSR_COMP1SW1_Pos)
2487#define COMP1_CSR_COMP1SW1 COMP1_CSR_COMP1SW1_Msk
2488/* Legacy defines */
2489#define COMP_CSR_COMP1SW1 COMP1_CSR_COMP1SW1
2490#define COMP1_CSR_COMP1INSEL_Pos (4U)
2491#define COMP1_CSR_COMP1INSEL_Msk (0x7UL << COMP1_CSR_COMP1INSEL_Pos)
2492#define COMP1_CSR_COMP1INSEL COMP1_CSR_COMP1INSEL_Msk
2493#define COMP1_CSR_COMP1INSEL_0 (0x1UL << COMP1_CSR_COMP1INSEL_Pos)
2494#define COMP1_CSR_COMP1INSEL_1 (0x2UL << COMP1_CSR_COMP1INSEL_Pos)
2495#define COMP1_CSR_COMP1INSEL_2 (0x4UL << COMP1_CSR_COMP1INSEL_Pos)
2496#define COMP1_CSR_COMP1OUTSEL_Pos (10U)
2497#define COMP1_CSR_COMP1OUTSEL_Msk (0xFUL << COMP1_CSR_COMP1OUTSEL_Pos)
2498#define COMP1_CSR_COMP1OUTSEL COMP1_CSR_COMP1OUTSEL_Msk
2499#define COMP1_CSR_COMP1OUTSEL_0 (0x1UL << COMP1_CSR_COMP1OUTSEL_Pos)
2500#define COMP1_CSR_COMP1OUTSEL_1 (0x2UL << COMP1_CSR_COMP1OUTSEL_Pos)
2501#define COMP1_CSR_COMP1OUTSEL_2 (0x4UL << COMP1_CSR_COMP1OUTSEL_Pos)
2502#define COMP1_CSR_COMP1OUTSEL_3 (0x8UL << COMP1_CSR_COMP1OUTSEL_Pos)
2503#define COMP1_CSR_COMP1POL_Pos (15U)
2504#define COMP1_CSR_COMP1POL_Msk (0x1UL << COMP1_CSR_COMP1POL_Pos)
2505#define COMP1_CSR_COMP1POL COMP1_CSR_COMP1POL_Msk
2506#define COMP1_CSR_COMP1BLANKING_Pos (18U)
2507#define COMP1_CSR_COMP1BLANKING_Msk (0x3UL << COMP1_CSR_COMP1BLANKING_Pos)
2508#define COMP1_CSR_COMP1BLANKING COMP1_CSR_COMP1BLANKING_Msk
2509#define COMP1_CSR_COMP1BLANKING_0 (0x1UL << COMP1_CSR_COMP1BLANKING_Pos)
2510#define COMP1_CSR_COMP1BLANKING_1 (0x2UL << COMP1_CSR_COMP1BLANKING_Pos)
2511#define COMP1_CSR_COMP1BLANKING_2 (0x4UL << COMP1_CSR_COMP1BLANKING_Pos)
2512#define COMP1_CSR_COMP1OUT_Pos (30U)
2513#define COMP1_CSR_COMP1OUT_Msk (0x1UL << COMP1_CSR_COMP1OUT_Pos)
2514#define COMP1_CSR_COMP1OUT COMP1_CSR_COMP1OUT_Msk
2515#define COMP1_CSR_COMP1LOCK_Pos (31U)
2516#define COMP1_CSR_COMP1LOCK_Msk (0x1UL << COMP1_CSR_COMP1LOCK_Pos)
2517#define COMP1_CSR_COMP1LOCK COMP1_CSR_COMP1LOCK_Msk
2519/********************** Bit definition for COMP2_CSR register ***************/
2520#define COMP2_CSR_COMP2EN_Pos (0U)
2521#define COMP2_CSR_COMP2EN_Msk (0x1UL << COMP2_CSR_COMP2EN_Pos)
2522#define COMP2_CSR_COMP2EN COMP2_CSR_COMP2EN_Msk
2523#define COMP2_CSR_COMP2INSEL_Pos (4U)
2524#define COMP2_CSR_COMP2INSEL_Msk (0x7UL << COMP2_CSR_COMP2INSEL_Pos)
2525#define COMP2_CSR_COMP2INSEL COMP2_CSR_COMP2INSEL_Msk
2526#define COMP2_CSR_COMP2INSEL_0 (0x00000010U)
2527#define COMP2_CSR_COMP2INSEL_1 (0x00000020U)
2528#define COMP2_CSR_COMP2INSEL_2 (0x00000040U)
2529#define COMP2_CSR_COMP2OUTSEL_Pos (10U)
2530#define COMP2_CSR_COMP2OUTSEL_Msk (0xFUL << COMP2_CSR_COMP2OUTSEL_Pos)
2531#define COMP2_CSR_COMP2OUTSEL COMP2_CSR_COMP2OUTSEL_Msk
2532#define COMP2_CSR_COMP2OUTSEL_0 (0x1UL << COMP2_CSR_COMP2OUTSEL_Pos)
2533#define COMP2_CSR_COMP2OUTSEL_1 (0x2UL << COMP2_CSR_COMP2OUTSEL_Pos)
2534#define COMP2_CSR_COMP2OUTSEL_2 (0x4UL << COMP2_CSR_COMP2OUTSEL_Pos)
2535#define COMP2_CSR_COMP2OUTSEL_3 (0x8UL << COMP2_CSR_COMP2OUTSEL_Pos)
2536#define COMP2_CSR_COMP2POL_Pos (15U)
2537#define COMP2_CSR_COMP2POL_Msk (0x1UL << COMP2_CSR_COMP2POL_Pos)
2538#define COMP2_CSR_COMP2POL COMP2_CSR_COMP2POL_Msk
2539#define COMP2_CSR_COMP2BLANKING_Pos (18U)
2540#define COMP2_CSR_COMP2BLANKING_Msk (0x3UL << COMP2_CSR_COMP2BLANKING_Pos)
2541#define COMP2_CSR_COMP2BLANKING COMP2_CSR_COMP2BLANKING_Msk
2542#define COMP2_CSR_COMP2BLANKING_0 (0x1UL << COMP2_CSR_COMP2BLANKING_Pos)
2543#define COMP2_CSR_COMP2BLANKING_1 (0x2UL << COMP2_CSR_COMP2BLANKING_Pos)
2544#define COMP2_CSR_COMP2BLANKING_2 (0x4UL << COMP2_CSR_COMP2BLANKING_Pos)
2545#define COMP2_CSR_COMP2OUT_Pos (30U)
2546#define COMP2_CSR_COMP2OUT_Msk (0x1UL << COMP2_CSR_COMP2OUT_Pos)
2547#define COMP2_CSR_COMP2OUT COMP2_CSR_COMP2OUT_Msk
2548#define COMP2_CSR_COMP2LOCK_Pos (31U)
2549#define COMP2_CSR_COMP2LOCK_Msk (0x1UL << COMP2_CSR_COMP2LOCK_Pos)
2550#define COMP2_CSR_COMP2LOCK COMP2_CSR_COMP2LOCK_Msk
2552/********************** Bit definition for COMP3_CSR register ***************/
2553#define COMP3_CSR_COMP3EN_Pos (0U)
2554#define COMP3_CSR_COMP3EN_Msk (0x1UL << COMP3_CSR_COMP3EN_Pos)
2555#define COMP3_CSR_COMP3EN COMP3_CSR_COMP3EN_Msk
2556#define COMP3_CSR_COMP3INSEL_Pos (4U)
2557#define COMP3_CSR_COMP3INSEL_Msk (0x7UL << COMP3_CSR_COMP3INSEL_Pos)
2558#define COMP3_CSR_COMP3INSEL COMP3_CSR_COMP3INSEL_Msk
2559#define COMP3_CSR_COMP3INSEL_0 (0x1UL << COMP3_CSR_COMP3INSEL_Pos)
2560#define COMP3_CSR_COMP3INSEL_1 (0x2UL << COMP3_CSR_COMP3INSEL_Pos)
2561#define COMP3_CSR_COMP3INSEL_2 (0x4UL << COMP3_CSR_COMP3INSEL_Pos)
2562#define COMP3_CSR_COMP3OUTSEL_Pos (10U)
2563#define COMP3_CSR_COMP3OUTSEL_Msk (0xFUL << COMP3_CSR_COMP3OUTSEL_Pos)
2564#define COMP3_CSR_COMP3OUTSEL COMP3_CSR_COMP3OUTSEL_Msk
2565#define COMP3_CSR_COMP3OUTSEL_0 (0x1UL << COMP3_CSR_COMP3OUTSEL_Pos)
2566#define COMP3_CSR_COMP3OUTSEL_1 (0x2UL << COMP3_CSR_COMP3OUTSEL_Pos)
2567#define COMP3_CSR_COMP3OUTSEL_2 (0x4UL << COMP3_CSR_COMP3OUTSEL_Pos)
2568#define COMP3_CSR_COMP3OUTSEL_3 (0x8UL << COMP3_CSR_COMP3OUTSEL_Pos)
2569#define COMP3_CSR_COMP3POL_Pos (15U)
2570#define COMP3_CSR_COMP3POL_Msk (0x1UL << COMP3_CSR_COMP3POL_Pos)
2571#define COMP3_CSR_COMP3POL COMP3_CSR_COMP3POL_Msk
2572#define COMP3_CSR_COMP3BLANKING_Pos (18U)
2573#define COMP3_CSR_COMP3BLANKING_Msk (0x3UL << COMP3_CSR_COMP3BLANKING_Pos)
2574#define COMP3_CSR_COMP3BLANKING COMP3_CSR_COMP3BLANKING_Msk
2575#define COMP3_CSR_COMP3BLANKING_0 (0x1UL << COMP3_CSR_COMP3BLANKING_Pos)
2576#define COMP3_CSR_COMP3BLANKING_1 (0x2UL << COMP3_CSR_COMP3BLANKING_Pos)
2577#define COMP3_CSR_COMP3BLANKING_2 (0x4UL << COMP3_CSR_COMP3BLANKING_Pos)
2578#define COMP3_CSR_COMP3OUT_Pos (30U)
2579#define COMP3_CSR_COMP3OUT_Msk (0x1UL << COMP3_CSR_COMP3OUT_Pos)
2580#define COMP3_CSR_COMP3OUT COMP3_CSR_COMP3OUT_Msk
2581#define COMP3_CSR_COMP3LOCK_Pos (31U)
2582#define COMP3_CSR_COMP3LOCK_Msk (0x1UL << COMP3_CSR_COMP3LOCK_Pos)
2583#define COMP3_CSR_COMP3LOCK COMP3_CSR_COMP3LOCK_Msk
2585/********************** Bit definition for COMP4_CSR register ***************/
2586#define COMP4_CSR_COMP4EN_Pos (0U)
2587#define COMP4_CSR_COMP4EN_Msk (0x1UL << COMP4_CSR_COMP4EN_Pos)
2588#define COMP4_CSR_COMP4EN COMP4_CSR_COMP4EN_Msk
2589#define COMP4_CSR_COMP4INSEL_Pos (4U)
2590#define COMP4_CSR_COMP4INSEL_Msk (0x7UL << COMP4_CSR_COMP4INSEL_Pos)
2591#define COMP4_CSR_COMP4INSEL COMP4_CSR_COMP4INSEL_Msk
2592#define COMP4_CSR_COMP4INSEL_0 (0x00000010U)
2593#define COMP4_CSR_COMP4INSEL_1 (0x00000020U)
2594#define COMP4_CSR_COMP4INSEL_2 (0x00000040U)
2595#define COMP4_CSR_COMP4OUTSEL_Pos (10U)
2596#define COMP4_CSR_COMP4OUTSEL_Msk (0xFUL << COMP4_CSR_COMP4OUTSEL_Pos)
2597#define COMP4_CSR_COMP4OUTSEL COMP4_CSR_COMP4OUTSEL_Msk
2598#define COMP4_CSR_COMP4OUTSEL_0 (0x1UL << COMP4_CSR_COMP4OUTSEL_Pos)
2599#define COMP4_CSR_COMP4OUTSEL_1 (0x2UL << COMP4_CSR_COMP4OUTSEL_Pos)
2600#define COMP4_CSR_COMP4OUTSEL_2 (0x4UL << COMP4_CSR_COMP4OUTSEL_Pos)
2601#define COMP4_CSR_COMP4OUTSEL_3 (0x8UL << COMP4_CSR_COMP4OUTSEL_Pos)
2602#define COMP4_CSR_COMP4POL_Pos (15U)
2603#define COMP4_CSR_COMP4POL_Msk (0x1UL << COMP4_CSR_COMP4POL_Pos)
2604#define COMP4_CSR_COMP4POL COMP4_CSR_COMP4POL_Msk
2605#define COMP4_CSR_COMP4BLANKING_Pos (18U)
2606#define COMP4_CSR_COMP4BLANKING_Msk (0x3UL << COMP4_CSR_COMP4BLANKING_Pos)
2607#define COMP4_CSR_COMP4BLANKING COMP4_CSR_COMP4BLANKING_Msk
2608#define COMP4_CSR_COMP4BLANKING_0 (0x1UL << COMP4_CSR_COMP4BLANKING_Pos)
2609#define COMP4_CSR_COMP4BLANKING_1 (0x2UL << COMP4_CSR_COMP4BLANKING_Pos)
2610#define COMP4_CSR_COMP4BLANKING_2 (0x4UL << COMP4_CSR_COMP4BLANKING_Pos)
2611#define COMP4_CSR_COMP4OUT_Pos (30U)
2612#define COMP4_CSR_COMP4OUT_Msk (0x1UL << COMP4_CSR_COMP4OUT_Pos)
2613#define COMP4_CSR_COMP4OUT COMP4_CSR_COMP4OUT_Msk
2614#define COMP4_CSR_COMP4LOCK_Pos (31U)
2615#define COMP4_CSR_COMP4LOCK_Msk (0x1UL << COMP4_CSR_COMP4LOCK_Pos)
2616#define COMP4_CSR_COMP4LOCK COMP4_CSR_COMP4LOCK_Msk
2618/********************** Bit definition for COMP5_CSR register ***************/
2619#define COMP5_CSR_COMP5EN_Pos (0U)
2620#define COMP5_CSR_COMP5EN_Msk (0x1UL << COMP5_CSR_COMP5EN_Pos)
2621#define COMP5_CSR_COMP5EN COMP5_CSR_COMP5EN_Msk
2622#define COMP5_CSR_COMP5INSEL_Pos (4U)
2623#define COMP5_CSR_COMP5INSEL_Msk (0x7UL << COMP5_CSR_COMP5INSEL_Pos)
2624#define COMP5_CSR_COMP5INSEL COMP5_CSR_COMP5INSEL_Msk
2625#define COMP5_CSR_COMP5INSEL_0 (0x1UL << COMP5_CSR_COMP5INSEL_Pos)
2626#define COMP5_CSR_COMP5INSEL_1 (0x2UL << COMP5_CSR_COMP5INSEL_Pos)
2627#define COMP5_CSR_COMP5INSEL_2 (0x4UL << COMP5_CSR_COMP5INSEL_Pos)
2628#define COMP5_CSR_COMP5OUTSEL_Pos (10U)
2629#define COMP5_CSR_COMP5OUTSEL_Msk (0xFUL << COMP5_CSR_COMP5OUTSEL_Pos)
2630#define COMP5_CSR_COMP5OUTSEL COMP5_CSR_COMP5OUTSEL_Msk
2631#define COMP5_CSR_COMP5OUTSEL_0 (0x1UL << COMP5_CSR_COMP5OUTSEL_Pos)
2632#define COMP5_CSR_COMP5OUTSEL_1 (0x2UL << COMP5_CSR_COMP5OUTSEL_Pos)
2633#define COMP5_CSR_COMP5OUTSEL_2 (0x4UL << COMP5_CSR_COMP5OUTSEL_Pos)
2634#define COMP5_CSR_COMP5OUTSEL_3 (0x8UL << COMP5_CSR_COMP5OUTSEL_Pos)
2635#define COMP5_CSR_COMP5POL_Pos (15U)
2636#define COMP5_CSR_COMP5POL_Msk (0x1UL << COMP5_CSR_COMP5POL_Pos)
2637#define COMP5_CSR_COMP5POL COMP5_CSR_COMP5POL_Msk
2638#define COMP5_CSR_COMP5BLANKING_Pos (18U)
2639#define COMP5_CSR_COMP5BLANKING_Msk (0x3UL << COMP5_CSR_COMP5BLANKING_Pos)
2640#define COMP5_CSR_COMP5BLANKING COMP5_CSR_COMP5BLANKING_Msk
2641#define COMP5_CSR_COMP5BLANKING_0 (0x1UL << COMP5_CSR_COMP5BLANKING_Pos)
2642#define COMP5_CSR_COMP5BLANKING_1 (0x2UL << COMP5_CSR_COMP5BLANKING_Pos)
2643#define COMP5_CSR_COMP5BLANKING_2 (0x4UL << COMP5_CSR_COMP5BLANKING_Pos)
2644#define COMP5_CSR_COMP5OUT_Pos (30U)
2645#define COMP5_CSR_COMP5OUT_Msk (0x1UL << COMP5_CSR_COMP5OUT_Pos)
2646#define COMP5_CSR_COMP5OUT COMP5_CSR_COMP5OUT_Msk
2647#define COMP5_CSR_COMP5LOCK_Pos (31U)
2648#define COMP5_CSR_COMP5LOCK_Msk (0x1UL << COMP5_CSR_COMP5LOCK_Pos)
2649#define COMP5_CSR_COMP5LOCK COMP5_CSR_COMP5LOCK_Msk
2651/********************** Bit definition for COMP6_CSR register ***************/
2652#define COMP6_CSR_COMP6EN_Pos (0U)
2653#define COMP6_CSR_COMP6EN_Msk (0x1UL << COMP6_CSR_COMP6EN_Pos)
2654#define COMP6_CSR_COMP6EN COMP6_CSR_COMP6EN_Msk
2655#define COMP6_CSR_COMP6INSEL_Pos (4U)
2656#define COMP6_CSR_COMP6INSEL_Msk (0x7UL << COMP6_CSR_COMP6INSEL_Pos)
2657#define COMP6_CSR_COMP6INSEL COMP6_CSR_COMP6INSEL_Msk
2658#define COMP6_CSR_COMP6INSEL_0 (0x00000010U)
2659#define COMP6_CSR_COMP6INSEL_1 (0x00000020U)
2660#define COMP6_CSR_COMP6INSEL_2 (0x00000040U)
2661#define COMP6_CSR_COMP6OUTSEL_Pos (10U)
2662#define COMP6_CSR_COMP6OUTSEL_Msk (0xFUL << COMP6_CSR_COMP6OUTSEL_Pos)
2663#define COMP6_CSR_COMP6OUTSEL COMP6_CSR_COMP6OUTSEL_Msk
2664#define COMP6_CSR_COMP6OUTSEL_0 (0x1UL << COMP6_CSR_COMP6OUTSEL_Pos)
2665#define COMP6_CSR_COMP6OUTSEL_1 (0x2UL << COMP6_CSR_COMP6OUTSEL_Pos)
2666#define COMP6_CSR_COMP6OUTSEL_2 (0x4UL << COMP6_CSR_COMP6OUTSEL_Pos)
2667#define COMP6_CSR_COMP6OUTSEL_3 (0x8UL << COMP6_CSR_COMP6OUTSEL_Pos)
2668#define COMP6_CSR_COMP6POL_Pos (15U)
2669#define COMP6_CSR_COMP6POL_Msk (0x1UL << COMP6_CSR_COMP6POL_Pos)
2670#define COMP6_CSR_COMP6POL COMP6_CSR_COMP6POL_Msk
2671#define COMP6_CSR_COMP6BLANKING_Pos (18U)
2672#define COMP6_CSR_COMP6BLANKING_Msk (0x3UL << COMP6_CSR_COMP6BLANKING_Pos)
2673#define COMP6_CSR_COMP6BLANKING COMP6_CSR_COMP6BLANKING_Msk
2674#define COMP6_CSR_COMP6BLANKING_0 (0x1UL << COMP6_CSR_COMP6BLANKING_Pos)
2675#define COMP6_CSR_COMP6BLANKING_1 (0x2UL << COMP6_CSR_COMP6BLANKING_Pos)
2676#define COMP6_CSR_COMP6BLANKING_2 (0x4UL << COMP6_CSR_COMP6BLANKING_Pos)
2677#define COMP6_CSR_COMP6OUT_Pos (30U)
2678#define COMP6_CSR_COMP6OUT_Msk (0x1UL << COMP6_CSR_COMP6OUT_Pos)
2679#define COMP6_CSR_COMP6OUT COMP6_CSR_COMP6OUT_Msk
2680#define COMP6_CSR_COMP6LOCK_Pos (31U)
2681#define COMP6_CSR_COMP6LOCK_Msk (0x1UL << COMP6_CSR_COMP6LOCK_Pos)
2682#define COMP6_CSR_COMP6LOCK COMP6_CSR_COMP6LOCK_Msk
2684/********************** Bit definition for COMP7_CSR register ***************/
2685#define COMP7_CSR_COMP7EN_Pos (0U)
2686#define COMP7_CSR_COMP7EN_Msk (0x1UL << COMP7_CSR_COMP7EN_Pos)
2687#define COMP7_CSR_COMP7EN COMP7_CSR_COMP7EN_Msk
2688#define COMP7_CSR_COMP7INSEL_Pos (4U)
2689#define COMP7_CSR_COMP7INSEL_Msk (0x7UL << COMP7_CSR_COMP7INSEL_Pos)
2690#define COMP7_CSR_COMP7INSEL COMP7_CSR_COMP7INSEL_Msk
2691#define COMP7_CSR_COMP7INSEL_0 (0x1UL << COMP7_CSR_COMP7INSEL_Pos)
2692#define COMP7_CSR_COMP7INSEL_1 (0x2UL << COMP7_CSR_COMP7INSEL_Pos)
2693#define COMP7_CSR_COMP7INSEL_2 (0x4UL << COMP7_CSR_COMP7INSEL_Pos)
2694#define COMP7_CSR_COMP7OUTSEL_Pos (10U)
2695#define COMP7_CSR_COMP7OUTSEL_Msk (0xFUL << COMP7_CSR_COMP7OUTSEL_Pos)
2696#define COMP7_CSR_COMP7OUTSEL COMP7_CSR_COMP7OUTSEL_Msk
2697#define COMP7_CSR_COMP7OUTSEL_0 (0x1UL << COMP7_CSR_COMP7OUTSEL_Pos)
2698#define COMP7_CSR_COMP7OUTSEL_1 (0x2UL << COMP7_CSR_COMP7OUTSEL_Pos)
2699#define COMP7_CSR_COMP7OUTSEL_2 (0x4UL << COMP7_CSR_COMP7OUTSEL_Pos)
2700#define COMP7_CSR_COMP7OUTSEL_3 (0x8UL << COMP7_CSR_COMP7OUTSEL_Pos)
2701#define COMP7_CSR_COMP7POL_Pos (15U)
2702#define COMP7_CSR_COMP7POL_Msk (0x1UL << COMP7_CSR_COMP7POL_Pos)
2703#define COMP7_CSR_COMP7POL COMP7_CSR_COMP7POL_Msk
2704#define COMP7_CSR_COMP7BLANKING_Pos (18U)
2705#define COMP7_CSR_COMP7BLANKING_Msk (0x3UL << COMP7_CSR_COMP7BLANKING_Pos)
2706#define COMP7_CSR_COMP7BLANKING COMP7_CSR_COMP7BLANKING_Msk
2707#define COMP7_CSR_COMP7BLANKING_0 (0x1UL << COMP7_CSR_COMP7BLANKING_Pos)
2708#define COMP7_CSR_COMP7BLANKING_1 (0x2UL << COMP7_CSR_COMP7BLANKING_Pos)
2709#define COMP7_CSR_COMP7BLANKING_2 (0x4UL << COMP7_CSR_COMP7BLANKING_Pos)
2710#define COMP7_CSR_COMP7OUT_Pos (30U)
2711#define COMP7_CSR_COMP7OUT_Msk (0x1UL << COMP7_CSR_COMP7OUT_Pos)
2712#define COMP7_CSR_COMP7OUT COMP7_CSR_COMP7OUT_Msk
2713#define COMP7_CSR_COMP7LOCK_Pos (31U)
2714#define COMP7_CSR_COMP7LOCK_Msk (0x1UL << COMP7_CSR_COMP7LOCK_Pos)
2715#define COMP7_CSR_COMP7LOCK COMP7_CSR_COMP7LOCK_Msk
2717/********************** Bit definition for COMP_CSR register ****************/
2718#define COMP_CSR_COMPxEN_Pos (0U)
2719#define COMP_CSR_COMPxEN_Msk (0x1UL << COMP_CSR_COMPxEN_Pos)
2720#define COMP_CSR_COMPxEN COMP_CSR_COMPxEN_Msk
2721#define COMP_CSR_COMPxSW1_Pos (1U)
2722#define COMP_CSR_COMPxSW1_Msk (0x1UL << COMP_CSR_COMPxSW1_Pos)
2723#define COMP_CSR_COMPxSW1 COMP_CSR_COMPxSW1_Msk
2724#define COMP_CSR_COMPxINSEL_Pos (4U)
2725#define COMP_CSR_COMPxINSEL_Msk (0x7UL << COMP_CSR_COMPxINSEL_Pos)
2726#define COMP_CSR_COMPxINSEL COMP_CSR_COMPxINSEL_Msk
2727#define COMP_CSR_COMPxINSEL_0 (0x00000010U)
2728#define COMP_CSR_COMPxINSEL_1 (0x00000020U)
2729#define COMP_CSR_COMPxINSEL_2 (0x00000040U)
2730#define COMP_CSR_COMPxOUTSEL_Pos (10U)
2731#define COMP_CSR_COMPxOUTSEL_Msk (0xFUL << COMP_CSR_COMPxOUTSEL_Pos)
2732#define COMP_CSR_COMPxOUTSEL COMP_CSR_COMPxOUTSEL_Msk
2733#define COMP_CSR_COMPxOUTSEL_0 (0x1UL << COMP_CSR_COMPxOUTSEL_Pos)
2734#define COMP_CSR_COMPxOUTSEL_1 (0x2UL << COMP_CSR_COMPxOUTSEL_Pos)
2735#define COMP_CSR_COMPxOUTSEL_2 (0x4UL << COMP_CSR_COMPxOUTSEL_Pos)
2736#define COMP_CSR_COMPxOUTSEL_3 (0x8UL << COMP_CSR_COMPxOUTSEL_Pos)
2737#define COMP_CSR_COMPxPOL_Pos (15U)
2738#define COMP_CSR_COMPxPOL_Msk (0x1UL << COMP_CSR_COMPxPOL_Pos)
2739#define COMP_CSR_COMPxPOL COMP_CSR_COMPxPOL_Msk
2740#define COMP_CSR_COMPxBLANKING_Pos (18U)
2741#define COMP_CSR_COMPxBLANKING_Msk (0x3UL << COMP_CSR_COMPxBLANKING_Pos)
2742#define COMP_CSR_COMPxBLANKING COMP_CSR_COMPxBLANKING_Msk
2743#define COMP_CSR_COMPxBLANKING_0 (0x1UL << COMP_CSR_COMPxBLANKING_Pos)
2744#define COMP_CSR_COMPxBLANKING_1 (0x2UL << COMP_CSR_COMPxBLANKING_Pos)
2745#define COMP_CSR_COMPxBLANKING_2 (0x4UL << COMP_CSR_COMPxBLANKING_Pos)
2746#define COMP_CSR_COMPxOUT_Pos (30U)
2747#define COMP_CSR_COMPxOUT_Msk (0x1UL << COMP_CSR_COMPxOUT_Pos)
2748#define COMP_CSR_COMPxOUT COMP_CSR_COMPxOUT_Msk
2749#define COMP_CSR_COMPxLOCK_Pos (31U)
2750#define COMP_CSR_COMPxLOCK_Msk (0x1UL << COMP_CSR_COMPxLOCK_Pos)
2751#define COMP_CSR_COMPxLOCK COMP_CSR_COMPxLOCK_Msk
2753/******************************************************************************/
2754/* */
2755/* Operational Amplifier (OPAMP) */
2756/* */
2757/******************************************************************************/
2758/********************* Bit definition for OPAMP1_CSR register ***************/
2759#define OPAMP1_CSR_OPAMP1EN_Pos (0U)
2760#define OPAMP1_CSR_OPAMP1EN_Msk (0x1UL << OPAMP1_CSR_OPAMP1EN_Pos)
2761#define OPAMP1_CSR_OPAMP1EN OPAMP1_CSR_OPAMP1EN_Msk
2762#define OPAMP1_CSR_FORCEVP_Pos (1U)
2763#define OPAMP1_CSR_FORCEVP_Msk (0x1UL << OPAMP1_CSR_FORCEVP_Pos)
2764#define OPAMP1_CSR_FORCEVP OPAMP1_CSR_FORCEVP_Msk
2765#define OPAMP1_CSR_VPSEL_Pos (2U)
2766#define OPAMP1_CSR_VPSEL_Msk (0x3UL << OPAMP1_CSR_VPSEL_Pos)
2767#define OPAMP1_CSR_VPSEL OPAMP1_CSR_VPSEL_Msk
2768#define OPAMP1_CSR_VPSEL_0 (0x1UL << OPAMP1_CSR_VPSEL_Pos)
2769#define OPAMP1_CSR_VPSEL_1 (0x2UL << OPAMP1_CSR_VPSEL_Pos)
2770#define OPAMP1_CSR_VMSEL_Pos (5U)
2771#define OPAMP1_CSR_VMSEL_Msk (0x3UL << OPAMP1_CSR_VMSEL_Pos)
2772#define OPAMP1_CSR_VMSEL OPAMP1_CSR_VMSEL_Msk
2773#define OPAMP1_CSR_VMSEL_0 (0x1UL << OPAMP1_CSR_VMSEL_Pos)
2774#define OPAMP1_CSR_VMSEL_1 (0x2UL << OPAMP1_CSR_VMSEL_Pos)
2775#define OPAMP1_CSR_TCMEN_Pos (7U)
2776#define OPAMP1_CSR_TCMEN_Msk (0x1UL << OPAMP1_CSR_TCMEN_Pos)
2777#define OPAMP1_CSR_TCMEN OPAMP1_CSR_TCMEN_Msk
2778#define OPAMP1_CSR_VMSSEL_Pos (8U)
2779#define OPAMP1_CSR_VMSSEL_Msk (0x1UL << OPAMP1_CSR_VMSSEL_Pos)
2780#define OPAMP1_CSR_VMSSEL OPAMP1_CSR_VMSSEL_Msk
2781#define OPAMP1_CSR_VPSSEL_Pos (9U)
2782#define OPAMP1_CSR_VPSSEL_Msk (0x3UL << OPAMP1_CSR_VPSSEL_Pos)
2783#define OPAMP1_CSR_VPSSEL OPAMP1_CSR_VPSSEL_Msk
2784#define OPAMP1_CSR_VPSSEL_0 (0x1UL << OPAMP1_CSR_VPSSEL_Pos)
2785#define OPAMP1_CSR_VPSSEL_1 (0x2UL << OPAMP1_CSR_VPSSEL_Pos)
2786#define OPAMP1_CSR_CALON_Pos (11U)
2787#define OPAMP1_CSR_CALON_Msk (0x1UL << OPAMP1_CSR_CALON_Pos)
2788#define OPAMP1_CSR_CALON OPAMP1_CSR_CALON_Msk
2789#define OPAMP1_CSR_CALSEL_Pos (12U)
2790#define OPAMP1_CSR_CALSEL_Msk (0x3UL << OPAMP1_CSR_CALSEL_Pos)
2791#define OPAMP1_CSR_CALSEL OPAMP1_CSR_CALSEL_Msk
2792#define OPAMP1_CSR_CALSEL_0 (0x1UL << OPAMP1_CSR_CALSEL_Pos)
2793#define OPAMP1_CSR_CALSEL_1 (0x2UL << OPAMP1_CSR_CALSEL_Pos)
2794#define OPAMP1_CSR_PGGAIN_Pos (14U)
2795#define OPAMP1_CSR_PGGAIN_Msk (0xFUL << OPAMP1_CSR_PGGAIN_Pos)
2796#define OPAMP1_CSR_PGGAIN OPAMP1_CSR_PGGAIN_Msk
2797#define OPAMP1_CSR_PGGAIN_0 (0x1UL << OPAMP1_CSR_PGGAIN_Pos)
2798#define OPAMP1_CSR_PGGAIN_1 (0x2UL << OPAMP1_CSR_PGGAIN_Pos)
2799#define OPAMP1_CSR_PGGAIN_2 (0x4UL << OPAMP1_CSR_PGGAIN_Pos)
2800#define OPAMP1_CSR_PGGAIN_3 (0x8UL << OPAMP1_CSR_PGGAIN_Pos)
2801#define OPAMP1_CSR_USERTRIM_Pos (18U)
2802#define OPAMP1_CSR_USERTRIM_Msk (0x1UL << OPAMP1_CSR_USERTRIM_Pos)
2803#define OPAMP1_CSR_USERTRIM OPAMP1_CSR_USERTRIM_Msk
2804#define OPAMP1_CSR_TRIMOFFSETP_Pos (19U)
2805#define OPAMP1_CSR_TRIMOFFSETP_Msk (0x1FUL << OPAMP1_CSR_TRIMOFFSETP_Pos)
2806#define OPAMP1_CSR_TRIMOFFSETP OPAMP1_CSR_TRIMOFFSETP_Msk
2807#define OPAMP1_CSR_TRIMOFFSETN_Pos (24U)
2808#define OPAMP1_CSR_TRIMOFFSETN_Msk (0x1FUL << OPAMP1_CSR_TRIMOFFSETN_Pos)
2809#define OPAMP1_CSR_TRIMOFFSETN OPAMP1_CSR_TRIMOFFSETN_Msk
2810#define OPAMP1_CSR_TSTREF_Pos (29U)
2811#define OPAMP1_CSR_TSTREF_Msk (0x1UL << OPAMP1_CSR_TSTREF_Pos)
2812#define OPAMP1_CSR_TSTREF OPAMP1_CSR_TSTREF_Msk
2813#define OPAMP1_CSR_OUTCAL_Pos (30U)
2814#define OPAMP1_CSR_OUTCAL_Msk (0x1UL << OPAMP1_CSR_OUTCAL_Pos)
2815#define OPAMP1_CSR_OUTCAL OPAMP1_CSR_OUTCAL_Msk
2816#define OPAMP1_CSR_LOCK_Pos (31U)
2817#define OPAMP1_CSR_LOCK_Msk (0x1UL << OPAMP1_CSR_LOCK_Pos)
2818#define OPAMP1_CSR_LOCK OPAMP1_CSR_LOCK_Msk
2820/********************* Bit definition for OPAMP2_CSR register ***************/
2821#define OPAMP2_CSR_OPAMP2EN_Pos (0U)
2822#define OPAMP2_CSR_OPAMP2EN_Msk (0x1UL << OPAMP2_CSR_OPAMP2EN_Pos)
2823#define OPAMP2_CSR_OPAMP2EN OPAMP2_CSR_OPAMP2EN_Msk
2824#define OPAMP2_CSR_FORCEVP_Pos (1U)
2825#define OPAMP2_CSR_FORCEVP_Msk (0x1UL << OPAMP2_CSR_FORCEVP_Pos)
2826#define OPAMP2_CSR_FORCEVP OPAMP2_CSR_FORCEVP_Msk
2827#define OPAMP2_CSR_VPSEL_Pos (2U)
2828#define OPAMP2_CSR_VPSEL_Msk (0x3UL << OPAMP2_CSR_VPSEL_Pos)
2829#define OPAMP2_CSR_VPSEL OPAMP2_CSR_VPSEL_Msk
2830#define OPAMP2_CSR_VPSEL_0 (0x1UL << OPAMP2_CSR_VPSEL_Pos)
2831#define OPAMP2_CSR_VPSEL_1 (0x2UL << OPAMP2_CSR_VPSEL_Pos)
2832#define OPAMP2_CSR_VMSEL_Pos (5U)
2833#define OPAMP2_CSR_VMSEL_Msk (0x3UL << OPAMP2_CSR_VMSEL_Pos)
2834#define OPAMP2_CSR_VMSEL OPAMP2_CSR_VMSEL_Msk
2835#define OPAMP2_CSR_VMSEL_0 (0x1UL << OPAMP2_CSR_VMSEL_Pos)
2836#define OPAMP2_CSR_VMSEL_1 (0x2UL << OPAMP2_CSR_VMSEL_Pos)
2837#define OPAMP2_CSR_TCMEN_Pos (7U)
2838#define OPAMP2_CSR_TCMEN_Msk (0x1UL << OPAMP2_CSR_TCMEN_Pos)
2839#define OPAMP2_CSR_TCMEN OPAMP2_CSR_TCMEN_Msk
2840#define OPAMP2_CSR_VMSSEL_Pos (8U)
2841#define OPAMP2_CSR_VMSSEL_Msk (0x1UL << OPAMP2_CSR_VMSSEL_Pos)
2842#define OPAMP2_CSR_VMSSEL OPAMP2_CSR_VMSSEL_Msk
2843#define OPAMP2_CSR_VPSSEL_Pos (9U)
2844#define OPAMP2_CSR_VPSSEL_Msk (0x3UL << OPAMP2_CSR_VPSSEL_Pos)
2845#define OPAMP2_CSR_VPSSEL OPAMP2_CSR_VPSSEL_Msk
2846#define OPAMP2_CSR_VPSSEL_0 (0x1UL << OPAMP2_CSR_VPSSEL_Pos)
2847#define OPAMP2_CSR_VPSSEL_1 (0x2UL << OPAMP2_CSR_VPSSEL_Pos)
2848#define OPAMP2_CSR_CALON_Pos (11U)
2849#define OPAMP2_CSR_CALON_Msk (0x1UL << OPAMP2_CSR_CALON_Pos)
2850#define OPAMP2_CSR_CALON OPAMP2_CSR_CALON_Msk
2851#define OPAMP2_CSR_CALSEL_Pos (12U)
2852#define OPAMP2_CSR_CALSEL_Msk (0x3UL << OPAMP2_CSR_CALSEL_Pos)
2853#define OPAMP2_CSR_CALSEL OPAMP2_CSR_CALSEL_Msk
2854#define OPAMP2_CSR_CALSEL_0 (0x1UL << OPAMP2_CSR_CALSEL_Pos)
2855#define OPAMP2_CSR_CALSEL_1 (0x2UL << OPAMP2_CSR_CALSEL_Pos)
2856#define OPAMP2_CSR_PGGAIN_Pos (14U)
2857#define OPAMP2_CSR_PGGAIN_Msk (0xFUL << OPAMP2_CSR_PGGAIN_Pos)
2858#define OPAMP2_CSR_PGGAIN OPAMP2_CSR_PGGAIN_Msk
2859#define OPAMP2_CSR_PGGAIN_0 (0x1UL << OPAMP2_CSR_PGGAIN_Pos)
2860#define OPAMP2_CSR_PGGAIN_1 (0x2UL << OPAMP2_CSR_PGGAIN_Pos)
2861#define OPAMP2_CSR_PGGAIN_2 (0x4UL << OPAMP2_CSR_PGGAIN_Pos)
2862#define OPAMP2_CSR_PGGAIN_3 (0x8UL << OPAMP2_CSR_PGGAIN_Pos)
2863#define OPAMP2_CSR_USERTRIM_Pos (18U)
2864#define OPAMP2_CSR_USERTRIM_Msk (0x1UL << OPAMP2_CSR_USERTRIM_Pos)
2865#define OPAMP2_CSR_USERTRIM OPAMP2_CSR_USERTRIM_Msk
2866#define OPAMP2_CSR_TRIMOFFSETP_Pos (19U)
2867#define OPAMP2_CSR_TRIMOFFSETP_Msk (0x1FUL << OPAMP2_CSR_TRIMOFFSETP_Pos)
2868#define OPAMP2_CSR_TRIMOFFSETP OPAMP2_CSR_TRIMOFFSETP_Msk
2869#define OPAMP2_CSR_TRIMOFFSETN_Pos (24U)
2870#define OPAMP2_CSR_TRIMOFFSETN_Msk (0x1FUL << OPAMP2_CSR_TRIMOFFSETN_Pos)
2871#define OPAMP2_CSR_TRIMOFFSETN OPAMP2_CSR_TRIMOFFSETN_Msk
2872#define OPAMP2_CSR_TSTREF_Pos (29U)
2873#define OPAMP2_CSR_TSTREF_Msk (0x1UL << OPAMP2_CSR_TSTREF_Pos)
2874#define OPAMP2_CSR_TSTREF OPAMP2_CSR_TSTREF_Msk
2875#define OPAMP2_CSR_OUTCAL_Pos (30U)
2876#define OPAMP2_CSR_OUTCAL_Msk (0x1UL << OPAMP2_CSR_OUTCAL_Pos)
2877#define OPAMP2_CSR_OUTCAL OPAMP2_CSR_OUTCAL_Msk
2878#define OPAMP2_CSR_LOCK_Pos (31U)
2879#define OPAMP2_CSR_LOCK_Msk (0x1UL << OPAMP2_CSR_LOCK_Pos)
2880#define OPAMP2_CSR_LOCK OPAMP2_CSR_LOCK_Msk
2882/********************* Bit definition for OPAMP3_CSR register ***************/
2883#define OPAMP3_CSR_OPAMP3EN_Pos (0U)
2884#define OPAMP3_CSR_OPAMP3EN_Msk (0x1UL << OPAMP3_CSR_OPAMP3EN_Pos)
2885#define OPAMP3_CSR_OPAMP3EN OPAMP3_CSR_OPAMP3EN_Msk
2886#define OPAMP3_CSR_FORCEVP_Pos (1U)
2887#define OPAMP3_CSR_FORCEVP_Msk (0x1UL << OPAMP3_CSR_FORCEVP_Pos)
2888#define OPAMP3_CSR_FORCEVP OPAMP3_CSR_FORCEVP_Msk
2889#define OPAMP3_CSR_VPSEL_Pos (2U)
2890#define OPAMP3_CSR_VPSEL_Msk (0x3UL << OPAMP3_CSR_VPSEL_Pos)
2891#define OPAMP3_CSR_VPSEL OPAMP3_CSR_VPSEL_Msk
2892#define OPAMP3_CSR_VPSEL_0 (0x1UL << OPAMP3_CSR_VPSEL_Pos)
2893#define OPAMP3_CSR_VPSEL_1 (0x2UL << OPAMP3_CSR_VPSEL_Pos)
2894#define OPAMP3_CSR_VMSEL_Pos (5U)
2895#define OPAMP3_CSR_VMSEL_Msk (0x3UL << OPAMP3_CSR_VMSEL_Pos)
2896#define OPAMP3_CSR_VMSEL OPAMP3_CSR_VMSEL_Msk
2897#define OPAMP3_CSR_VMSEL_0 (0x1UL << OPAMP3_CSR_VMSEL_Pos)
2898#define OPAMP3_CSR_VMSEL_1 (0x2UL << OPAMP3_CSR_VMSEL_Pos)
2899#define OPAMP3_CSR_TCMEN_Pos (7U)
2900#define OPAMP3_CSR_TCMEN_Msk (0x1UL << OPAMP3_CSR_TCMEN_Pos)
2901#define OPAMP3_CSR_TCMEN OPAMP3_CSR_TCMEN_Msk
2902#define OPAMP3_CSR_VMSSEL_Pos (8U)
2903#define OPAMP3_CSR_VMSSEL_Msk (0x1UL << OPAMP3_CSR_VMSSEL_Pos)
2904#define OPAMP3_CSR_VMSSEL OPAMP3_CSR_VMSSEL_Msk
2905#define OPAMP3_CSR_VPSSEL_Pos (9U)
2906#define OPAMP3_CSR_VPSSEL_Msk (0x3UL << OPAMP3_CSR_VPSSEL_Pos)
2907#define OPAMP3_CSR_VPSSEL OPAMP3_CSR_VPSSEL_Msk
2908#define OPAMP3_CSR_VPSSEL_0 (0x1UL << OPAMP3_CSR_VPSSEL_Pos)
2909#define OPAMP3_CSR_VPSSEL_1 (0x2UL << OPAMP3_CSR_VPSSEL_Pos)
2910#define OPAMP3_CSR_CALON_Pos (11U)
2911#define OPAMP3_CSR_CALON_Msk (0x1UL << OPAMP3_CSR_CALON_Pos)
2912#define OPAMP3_CSR_CALON OPAMP3_CSR_CALON_Msk
2913#define OPAMP3_CSR_CALSEL_Pos (12U)
2914#define OPAMP3_CSR_CALSEL_Msk (0x3UL << OPAMP3_CSR_CALSEL_Pos)
2915#define OPAMP3_CSR_CALSEL OPAMP3_CSR_CALSEL_Msk
2916#define OPAMP3_CSR_CALSEL_0 (0x1UL << OPAMP3_CSR_CALSEL_Pos)
2917#define OPAMP3_CSR_CALSEL_1 (0x2UL << OPAMP3_CSR_CALSEL_Pos)
2918#define OPAMP3_CSR_PGGAIN_Pos (14U)
2919#define OPAMP3_CSR_PGGAIN_Msk (0xFUL << OPAMP3_CSR_PGGAIN_Pos)
2920#define OPAMP3_CSR_PGGAIN OPAMP3_CSR_PGGAIN_Msk
2921#define OPAMP3_CSR_PGGAIN_0 (0x1UL << OPAMP3_CSR_PGGAIN_Pos)
2922#define OPAMP3_CSR_PGGAIN_1 (0x2UL << OPAMP3_CSR_PGGAIN_Pos)
2923#define OPAMP3_CSR_PGGAIN_2 (0x4UL << OPAMP3_CSR_PGGAIN_Pos)
2924#define OPAMP3_CSR_PGGAIN_3 (0x8UL << OPAMP3_CSR_PGGAIN_Pos)
2925#define OPAMP3_CSR_USERTRIM_Pos (18U)
2926#define OPAMP3_CSR_USERTRIM_Msk (0x1UL << OPAMP3_CSR_USERTRIM_Pos)
2927#define OPAMP3_CSR_USERTRIM OPAMP3_CSR_USERTRIM_Msk
2928#define OPAMP3_CSR_TRIMOFFSETP_Pos (19U)
2929#define OPAMP3_CSR_TRIMOFFSETP_Msk (0x1FUL << OPAMP3_CSR_TRIMOFFSETP_Pos)
2930#define OPAMP3_CSR_TRIMOFFSETP OPAMP3_CSR_TRIMOFFSETP_Msk
2931#define OPAMP3_CSR_TRIMOFFSETN_Pos (24U)
2932#define OPAMP3_CSR_TRIMOFFSETN_Msk (0x1FUL << OPAMP3_CSR_TRIMOFFSETN_Pos)
2933#define OPAMP3_CSR_TRIMOFFSETN OPAMP3_CSR_TRIMOFFSETN_Msk
2934#define OPAMP3_CSR_TSTREF_Pos (29U)
2935#define OPAMP3_CSR_TSTREF_Msk (0x1UL << OPAMP3_CSR_TSTREF_Pos)
2936#define OPAMP3_CSR_TSTREF OPAMP3_CSR_TSTREF_Msk
2937#define OPAMP3_CSR_OUTCAL_Pos (30U)
2938#define OPAMP3_CSR_OUTCAL_Msk (0x1UL << OPAMP3_CSR_OUTCAL_Pos)
2939#define OPAMP3_CSR_OUTCAL OPAMP3_CSR_OUTCAL_Msk
2940#define OPAMP3_CSR_LOCK_Pos (31U)
2941#define OPAMP3_CSR_LOCK_Msk (0x1UL << OPAMP3_CSR_LOCK_Pos)
2942#define OPAMP3_CSR_LOCK OPAMP3_CSR_LOCK_Msk
2944/********************* Bit definition for OPAMP4_CSR register ***************/
2945#define OPAMP4_CSR_OPAMP4EN_Pos (0U)
2946#define OPAMP4_CSR_OPAMP4EN_Msk (0x1UL << OPAMP4_CSR_OPAMP4EN_Pos)
2947#define OPAMP4_CSR_OPAMP4EN OPAMP4_CSR_OPAMP4EN_Msk
2948#define OPAMP4_CSR_FORCEVP_Pos (1U)
2949#define OPAMP4_CSR_FORCEVP_Msk (0x1UL << OPAMP4_CSR_FORCEVP_Pos)
2950#define OPAMP4_CSR_FORCEVP OPAMP4_CSR_FORCEVP_Msk
2951#define OPAMP4_CSR_VPSEL_Pos (2U)
2952#define OPAMP4_CSR_VPSEL_Msk (0x3UL << OPAMP4_CSR_VPSEL_Pos)
2953#define OPAMP4_CSR_VPSEL OPAMP4_CSR_VPSEL_Msk
2954#define OPAMP4_CSR_VPSEL_0 (0x1UL << OPAMP4_CSR_VPSEL_Pos)
2955#define OPAMP4_CSR_VPSEL_1 (0x2UL << OPAMP4_CSR_VPSEL_Pos)
2956#define OPAMP4_CSR_VMSEL_Pos (5U)
2957#define OPAMP4_CSR_VMSEL_Msk (0x3UL << OPAMP4_CSR_VMSEL_Pos)
2958#define OPAMP4_CSR_VMSEL OPAMP4_CSR_VMSEL_Msk
2959#define OPAMP4_CSR_VMSEL_0 (0x1UL << OPAMP4_CSR_VMSEL_Pos)
2960#define OPAMP4_CSR_VMSEL_1 (0x2UL << OPAMP4_CSR_VMSEL_Pos)
2961#define OPAMP4_CSR_TCMEN_Pos (7U)
2962#define OPAMP4_CSR_TCMEN_Msk (0x1UL << OPAMP4_CSR_TCMEN_Pos)
2963#define OPAMP4_CSR_TCMEN OPAMP4_CSR_TCMEN_Msk
2964#define OPAMP4_CSR_VMSSEL_Pos (8U)
2965#define OPAMP4_CSR_VMSSEL_Msk (0x1UL << OPAMP4_CSR_VMSSEL_Pos)
2966#define OPAMP4_CSR_VMSSEL OPAMP4_CSR_VMSSEL_Msk
2967#define OPAMP4_CSR_VPSSEL_Pos (9U)
2968#define OPAMP4_CSR_VPSSEL_Msk (0x3UL << OPAMP4_CSR_VPSSEL_Pos)
2969#define OPAMP4_CSR_VPSSEL OPAMP4_CSR_VPSSEL_Msk
2970#define OPAMP4_CSR_VPSSEL_0 (0x1UL << OPAMP4_CSR_VPSSEL_Pos)
2971#define OPAMP4_CSR_VPSSEL_1 (0x2UL << OPAMP4_CSR_VPSSEL_Pos)
2972#define OPAMP4_CSR_CALON_Pos (11U)
2973#define OPAMP4_CSR_CALON_Msk (0x1UL << OPAMP4_CSR_CALON_Pos)
2974#define OPAMP4_CSR_CALON OPAMP4_CSR_CALON_Msk
2975#define OPAMP4_CSR_CALSEL_Pos (12U)
2976#define OPAMP4_CSR_CALSEL_Msk (0x3UL << OPAMP4_CSR_CALSEL_Pos)
2977#define OPAMP4_CSR_CALSEL OPAMP4_CSR_CALSEL_Msk
2978#define OPAMP4_CSR_CALSEL_0 (0x1UL << OPAMP4_CSR_CALSEL_Pos)
2979#define OPAMP4_CSR_CALSEL_1 (0x2UL << OPAMP4_CSR_CALSEL_Pos)
2980#define OPAMP4_CSR_PGGAIN_Pos (14U)
2981#define OPAMP4_CSR_PGGAIN_Msk (0xFUL << OPAMP4_CSR_PGGAIN_Pos)
2982#define OPAMP4_CSR_PGGAIN OPAMP4_CSR_PGGAIN_Msk
2983#define OPAMP4_CSR_PGGAIN_0 (0x1UL << OPAMP4_CSR_PGGAIN_Pos)
2984#define OPAMP4_CSR_PGGAIN_1 (0x2UL << OPAMP4_CSR_PGGAIN_Pos)
2985#define OPAMP4_CSR_PGGAIN_2 (0x4UL << OPAMP4_CSR_PGGAIN_Pos)
2986#define OPAMP4_CSR_PGGAIN_3 (0x8UL << OPAMP4_CSR_PGGAIN_Pos)
2987#define OPAMP4_CSR_USERTRIM_Pos (18U)
2988#define OPAMP4_CSR_USERTRIM_Msk (0x1UL << OPAMP4_CSR_USERTRIM_Pos)
2989#define OPAMP4_CSR_USERTRIM OPAMP4_CSR_USERTRIM_Msk
2990#define OPAMP4_CSR_TRIMOFFSETP_Pos (19U)
2991#define OPAMP4_CSR_TRIMOFFSETP_Msk (0x1FUL << OPAMP4_CSR_TRIMOFFSETP_Pos)
2992#define OPAMP4_CSR_TRIMOFFSETP OPAMP4_CSR_TRIMOFFSETP_Msk
2993#define OPAMP4_CSR_TRIMOFFSETN_Pos (24U)
2994#define OPAMP4_CSR_TRIMOFFSETN_Msk (0x1FUL << OPAMP4_CSR_TRIMOFFSETN_Pos)
2995#define OPAMP4_CSR_TRIMOFFSETN OPAMP4_CSR_TRIMOFFSETN_Msk
2996#define OPAMP4_CSR_TSTREF_Pos (29U)
2997#define OPAMP4_CSR_TSTREF_Msk (0x1UL << OPAMP4_CSR_TSTREF_Pos)
2998#define OPAMP4_CSR_TSTREF OPAMP4_CSR_TSTREF_Msk
2999#define OPAMP4_CSR_OUTCAL_Pos (30U)
3000#define OPAMP4_CSR_OUTCAL_Msk (0x1UL << OPAMP4_CSR_OUTCAL_Pos)
3001#define OPAMP4_CSR_OUTCAL OPAMP4_CSR_OUTCAL_Msk
3002#define OPAMP4_CSR_LOCK_Pos (31U)
3003#define OPAMP4_CSR_LOCK_Msk (0x1UL << OPAMP4_CSR_LOCK_Pos)
3004#define OPAMP4_CSR_LOCK OPAMP4_CSR_LOCK_Msk
3006/********************* Bit definition for OPAMPx_CSR register ***************/
3007#define OPAMP_CSR_OPAMPxEN_Pos (0U)
3008#define OPAMP_CSR_OPAMPxEN_Msk (0x1UL << OPAMP_CSR_OPAMPxEN_Pos)
3009#define OPAMP_CSR_OPAMPxEN OPAMP_CSR_OPAMPxEN_Msk
3010#define OPAMP_CSR_FORCEVP_Pos (1U)
3011#define OPAMP_CSR_FORCEVP_Msk (0x1UL << OPAMP_CSR_FORCEVP_Pos)
3012#define OPAMP_CSR_FORCEVP OPAMP_CSR_FORCEVP_Msk
3013#define OPAMP_CSR_VPSEL_Pos (2U)
3014#define OPAMP_CSR_VPSEL_Msk (0x3UL << OPAMP_CSR_VPSEL_Pos)
3015#define OPAMP_CSR_VPSEL OPAMP_CSR_VPSEL_Msk
3016#define OPAMP_CSR_VPSEL_0 (0x1UL << OPAMP_CSR_VPSEL_Pos)
3017#define OPAMP_CSR_VPSEL_1 (0x2UL << OPAMP_CSR_VPSEL_Pos)
3018#define OPAMP_CSR_VMSEL_Pos (5U)
3019#define OPAMP_CSR_VMSEL_Msk (0x3UL << OPAMP_CSR_VMSEL_Pos)
3020#define OPAMP_CSR_VMSEL OPAMP_CSR_VMSEL_Msk
3021#define OPAMP_CSR_VMSEL_0 (0x1UL << OPAMP_CSR_VMSEL_Pos)
3022#define OPAMP_CSR_VMSEL_1 (0x2UL << OPAMP_CSR_VMSEL_Pos)
3023#define OPAMP_CSR_TCMEN_Pos (7U)
3024#define OPAMP_CSR_TCMEN_Msk (0x1UL << OPAMP_CSR_TCMEN_Pos)
3025#define OPAMP_CSR_TCMEN OPAMP_CSR_TCMEN_Msk
3026#define OPAMP_CSR_VMSSEL_Pos (8U)
3027#define OPAMP_CSR_VMSSEL_Msk (0x1UL << OPAMP_CSR_VMSSEL_Pos)
3028#define OPAMP_CSR_VMSSEL OPAMP_CSR_VMSSEL_Msk
3029#define OPAMP_CSR_VPSSEL_Pos (9U)
3030#define OPAMP_CSR_VPSSEL_Msk (0x3UL << OPAMP_CSR_VPSSEL_Pos)
3031#define OPAMP_CSR_VPSSEL OPAMP_CSR_VPSSEL_Msk
3032#define OPAMP_CSR_VPSSEL_0 (0x1UL << OPAMP_CSR_VPSSEL_Pos)
3033#define OPAMP_CSR_VPSSEL_1 (0x2UL << OPAMP_CSR_VPSSEL_Pos)
3034#define OPAMP_CSR_CALON_Pos (11U)
3035#define OPAMP_CSR_CALON_Msk (0x1UL << OPAMP_CSR_CALON_Pos)
3036#define OPAMP_CSR_CALON OPAMP_CSR_CALON_Msk
3037#define OPAMP_CSR_CALSEL_Pos (12U)
3038#define OPAMP_CSR_CALSEL_Msk (0x3UL << OPAMP_CSR_CALSEL_Pos)
3039#define OPAMP_CSR_CALSEL OPAMP_CSR_CALSEL_Msk
3040#define OPAMP_CSR_CALSEL_0 (0x1UL << OPAMP_CSR_CALSEL_Pos)
3041#define OPAMP_CSR_CALSEL_1 (0x2UL << OPAMP_CSR_CALSEL_Pos)
3042#define OPAMP_CSR_PGGAIN_Pos (14U)
3043#define OPAMP_CSR_PGGAIN_Msk (0xFUL << OPAMP_CSR_PGGAIN_Pos)
3044#define OPAMP_CSR_PGGAIN OPAMP_CSR_PGGAIN_Msk
3045#define OPAMP_CSR_PGGAIN_0 (0x1UL << OPAMP_CSR_PGGAIN_Pos)
3046#define OPAMP_CSR_PGGAIN_1 (0x2UL << OPAMP_CSR_PGGAIN_Pos)
3047#define OPAMP_CSR_PGGAIN_2 (0x4UL << OPAMP_CSR_PGGAIN_Pos)
3048#define OPAMP_CSR_PGGAIN_3 (0x8UL << OPAMP_CSR_PGGAIN_Pos)
3049#define OPAMP_CSR_USERTRIM_Pos (18U)
3050#define OPAMP_CSR_USERTRIM_Msk (0x1UL << OPAMP_CSR_USERTRIM_Pos)
3051#define OPAMP_CSR_USERTRIM OPAMP_CSR_USERTRIM_Msk
3052#define OPAMP_CSR_TRIMOFFSETP_Pos (19U)
3053#define OPAMP_CSR_TRIMOFFSETP_Msk (0x1FUL << OPAMP_CSR_TRIMOFFSETP_Pos)
3054#define OPAMP_CSR_TRIMOFFSETP OPAMP_CSR_TRIMOFFSETP_Msk
3055#define OPAMP_CSR_TRIMOFFSETN_Pos (24U)
3056#define OPAMP_CSR_TRIMOFFSETN_Msk (0x1FUL << OPAMP_CSR_TRIMOFFSETN_Pos)
3057#define OPAMP_CSR_TRIMOFFSETN OPAMP_CSR_TRIMOFFSETN_Msk
3058#define OPAMP_CSR_TSTREF_Pos (29U)
3059#define OPAMP_CSR_TSTREF_Msk (0x1UL << OPAMP_CSR_TSTREF_Pos)
3060#define OPAMP_CSR_TSTREF OPAMP_CSR_TSTREF_Msk
3061#define OPAMP_CSR_OUTCAL_Pos (30U)
3062#define OPAMP_CSR_OUTCAL_Msk (0x1UL << OPAMP_CSR_OUTCAL_Pos)
3063#define OPAMP_CSR_OUTCAL OPAMP_CSR_OUTCAL_Msk
3064#define OPAMP_CSR_LOCK_Pos (31U)
3065#define OPAMP_CSR_LOCK_Msk (0x1UL << OPAMP_CSR_LOCK_Pos)
3066#define OPAMP_CSR_LOCK OPAMP_CSR_LOCK_Msk
3068/******************************************************************************/
3069/* */
3070/* Controller Area Network (CAN ) */
3071/* */
3072/******************************************************************************/
3073/******************* Bit definition for CAN_MCR register ********************/
3074#define CAN_MCR_INRQ_Pos (0U)
3075#define CAN_MCR_INRQ_Msk (0x1UL << CAN_MCR_INRQ_Pos)
3076#define CAN_MCR_INRQ CAN_MCR_INRQ_Msk
3077#define CAN_MCR_SLEEP_Pos (1U)
3078#define CAN_MCR_SLEEP_Msk (0x1UL << CAN_MCR_SLEEP_Pos)
3079#define CAN_MCR_SLEEP CAN_MCR_SLEEP_Msk
3080#define CAN_MCR_TXFP_Pos (2U)
3081#define CAN_MCR_TXFP_Msk (0x1UL << CAN_MCR_TXFP_Pos)
3082#define CAN_MCR_TXFP CAN_MCR_TXFP_Msk
3083#define CAN_MCR_RFLM_Pos (3U)
3084#define CAN_MCR_RFLM_Msk (0x1UL << CAN_MCR_RFLM_Pos)
3085#define CAN_MCR_RFLM CAN_MCR_RFLM_Msk
3086#define CAN_MCR_NART_Pos (4U)
3087#define CAN_MCR_NART_Msk (0x1UL << CAN_MCR_NART_Pos)
3088#define CAN_MCR_NART CAN_MCR_NART_Msk
3089#define CAN_MCR_AWUM_Pos (5U)
3090#define CAN_MCR_AWUM_Msk (0x1UL << CAN_MCR_AWUM_Pos)
3091#define CAN_MCR_AWUM CAN_MCR_AWUM_Msk
3092#define CAN_MCR_ABOM_Pos (6U)
3093#define CAN_MCR_ABOM_Msk (0x1UL << CAN_MCR_ABOM_Pos)
3094#define CAN_MCR_ABOM CAN_MCR_ABOM_Msk
3095#define CAN_MCR_TTCM_Pos (7U)
3096#define CAN_MCR_TTCM_Msk (0x1UL << CAN_MCR_TTCM_Pos)
3097#define CAN_MCR_TTCM CAN_MCR_TTCM_Msk
3098#define CAN_MCR_RESET_Pos (15U)
3099#define CAN_MCR_RESET_Msk (0x1UL << CAN_MCR_RESET_Pos)
3100#define CAN_MCR_RESET CAN_MCR_RESET_Msk
3102/******************* Bit definition for CAN_MSR register ********************/
3103#define CAN_MSR_INAK_Pos (0U)
3104#define CAN_MSR_INAK_Msk (0x1UL << CAN_MSR_INAK_Pos)
3105#define CAN_MSR_INAK CAN_MSR_INAK_Msk
3106#define CAN_MSR_SLAK_Pos (1U)
3107#define CAN_MSR_SLAK_Msk (0x1UL << CAN_MSR_SLAK_Pos)
3108#define CAN_MSR_SLAK CAN_MSR_SLAK_Msk
3109#define CAN_MSR_ERRI_Pos (2U)
3110#define CAN_MSR_ERRI_Msk (0x1UL << CAN_MSR_ERRI_Pos)
3111#define CAN_MSR_ERRI CAN_MSR_ERRI_Msk
3112#define CAN_MSR_WKUI_Pos (3U)
3113#define CAN_MSR_WKUI_Msk (0x1UL << CAN_MSR_WKUI_Pos)
3114#define CAN_MSR_WKUI CAN_MSR_WKUI_Msk
3115#define CAN_MSR_SLAKI_Pos (4U)
3116#define CAN_MSR_SLAKI_Msk (0x1UL << CAN_MSR_SLAKI_Pos)
3117#define CAN_MSR_SLAKI CAN_MSR_SLAKI_Msk
3118#define CAN_MSR_TXM_Pos (8U)
3119#define CAN_MSR_TXM_Msk (0x1UL << CAN_MSR_TXM_Pos)
3120#define CAN_MSR_TXM CAN_MSR_TXM_Msk
3121#define CAN_MSR_RXM_Pos (9U)
3122#define CAN_MSR_RXM_Msk (0x1UL << CAN_MSR_RXM_Pos)
3123#define CAN_MSR_RXM CAN_MSR_RXM_Msk
3124#define CAN_MSR_SAMP_Pos (10U)
3125#define CAN_MSR_SAMP_Msk (0x1UL << CAN_MSR_SAMP_Pos)
3126#define CAN_MSR_SAMP CAN_MSR_SAMP_Msk
3127#define CAN_MSR_RX_Pos (11U)
3128#define CAN_MSR_RX_Msk (0x1UL << CAN_MSR_RX_Pos)
3129#define CAN_MSR_RX CAN_MSR_RX_Msk
3131/******************* Bit definition for CAN_TSR register ********************/
3132#define CAN_TSR_RQCP0_Pos (0U)
3133#define CAN_TSR_RQCP0_Msk (0x1UL << CAN_TSR_RQCP0_Pos)
3134#define CAN_TSR_RQCP0 CAN_TSR_RQCP0_Msk
3135#define CAN_TSR_TXOK0_Pos (1U)
3136#define CAN_TSR_TXOK0_Msk (0x1UL << CAN_TSR_TXOK0_Pos)
3137#define CAN_TSR_TXOK0 CAN_TSR_TXOK0_Msk
3138#define CAN_TSR_ALST0_Pos (2U)
3139#define CAN_TSR_ALST0_Msk (0x1UL << CAN_TSR_ALST0_Pos)
3140#define CAN_TSR_ALST0 CAN_TSR_ALST0_Msk
3141#define CAN_TSR_TERR0_Pos (3U)
3142#define CAN_TSR_TERR0_Msk (0x1UL << CAN_TSR_TERR0_Pos)
3143#define CAN_TSR_TERR0 CAN_TSR_TERR0_Msk
3144#define CAN_TSR_ABRQ0_Pos (7U)
3145#define CAN_TSR_ABRQ0_Msk (0x1UL << CAN_TSR_ABRQ0_Pos)
3146#define CAN_TSR_ABRQ0 CAN_TSR_ABRQ0_Msk
3147#define CAN_TSR_RQCP1_Pos (8U)
3148#define CAN_TSR_RQCP1_Msk (0x1UL << CAN_TSR_RQCP1_Pos)
3149#define CAN_TSR_RQCP1 CAN_TSR_RQCP1_Msk
3150#define CAN_TSR_TXOK1_Pos (9U)
3151#define CAN_TSR_TXOK1_Msk (0x1UL << CAN_TSR_TXOK1_Pos)
3152#define CAN_TSR_TXOK1 CAN_TSR_TXOK1_Msk
3153#define CAN_TSR_ALST1_Pos (10U)
3154#define CAN_TSR_ALST1_Msk (0x1UL << CAN_TSR_ALST1_Pos)
3155#define CAN_TSR_ALST1 CAN_TSR_ALST1_Msk
3156#define CAN_TSR_TERR1_Pos (11U)
3157#define CAN_TSR_TERR1_Msk (0x1UL << CAN_TSR_TERR1_Pos)
3158#define CAN_TSR_TERR1 CAN_TSR_TERR1_Msk
3159#define CAN_TSR_ABRQ1_Pos (15U)
3160#define CAN_TSR_ABRQ1_Msk (0x1UL << CAN_TSR_ABRQ1_Pos)
3161#define CAN_TSR_ABRQ1 CAN_TSR_ABRQ1_Msk
3162#define CAN_TSR_RQCP2_Pos (16U)
3163#define CAN_TSR_RQCP2_Msk (0x1UL << CAN_TSR_RQCP2_Pos)
3164#define CAN_TSR_RQCP2 CAN_TSR_RQCP2_Msk
3165#define CAN_TSR_TXOK2_Pos (17U)
3166#define CAN_TSR_TXOK2_Msk (0x1UL << CAN_TSR_TXOK2_Pos)
3167#define CAN_TSR_TXOK2 CAN_TSR_TXOK2_Msk
3168#define CAN_TSR_ALST2_Pos (18U)
3169#define CAN_TSR_ALST2_Msk (0x1UL << CAN_TSR_ALST2_Pos)
3170#define CAN_TSR_ALST2 CAN_TSR_ALST2_Msk
3171#define CAN_TSR_TERR2_Pos (19U)
3172#define CAN_TSR_TERR2_Msk (0x1UL << CAN_TSR_TERR2_Pos)
3173#define CAN_TSR_TERR2 CAN_TSR_TERR2_Msk
3174#define CAN_TSR_ABRQ2_Pos (23U)
3175#define CAN_TSR_ABRQ2_Msk (0x1UL << CAN_TSR_ABRQ2_Pos)
3176#define CAN_TSR_ABRQ2 CAN_TSR_ABRQ2_Msk
3177#define CAN_TSR_CODE_Pos (24U)
3178#define CAN_TSR_CODE_Msk (0x3UL << CAN_TSR_CODE_Pos)
3179#define CAN_TSR_CODE CAN_TSR_CODE_Msk
3181#define CAN_TSR_TME_Pos (26U)
3182#define CAN_TSR_TME_Msk (0x7UL << CAN_TSR_TME_Pos)
3183#define CAN_TSR_TME CAN_TSR_TME_Msk
3184#define CAN_TSR_TME0_Pos (26U)
3185#define CAN_TSR_TME0_Msk (0x1UL << CAN_TSR_TME0_Pos)
3186#define CAN_TSR_TME0 CAN_TSR_TME0_Msk
3187#define CAN_TSR_TME1_Pos (27U)
3188#define CAN_TSR_TME1_Msk (0x1UL << CAN_TSR_TME1_Pos)
3189#define CAN_TSR_TME1 CAN_TSR_TME1_Msk
3190#define CAN_TSR_TME2_Pos (28U)
3191#define CAN_TSR_TME2_Msk (0x1UL << CAN_TSR_TME2_Pos)
3192#define CAN_TSR_TME2 CAN_TSR_TME2_Msk
3194#define CAN_TSR_LOW_Pos (29U)
3195#define CAN_TSR_LOW_Msk (0x7UL << CAN_TSR_LOW_Pos)
3196#define CAN_TSR_LOW CAN_TSR_LOW_Msk
3197#define CAN_TSR_LOW0_Pos (29U)
3198#define CAN_TSR_LOW0_Msk (0x1UL << CAN_TSR_LOW0_Pos)
3199#define CAN_TSR_LOW0 CAN_TSR_LOW0_Msk
3200#define CAN_TSR_LOW1_Pos (30U)
3201#define CAN_TSR_LOW1_Msk (0x1UL << CAN_TSR_LOW1_Pos)
3202#define CAN_TSR_LOW1 CAN_TSR_LOW1_Msk
3203#define CAN_TSR_LOW2_Pos (31U)
3204#define CAN_TSR_LOW2_Msk (0x1UL << CAN_TSR_LOW2_Pos)
3205#define CAN_TSR_LOW2 CAN_TSR_LOW2_Msk
3207/******************* Bit definition for CAN_RF0R register *******************/
3208#define CAN_RF0R_FMP0_Pos (0U)
3209#define CAN_RF0R_FMP0_Msk (0x3UL << CAN_RF0R_FMP0_Pos)
3210#define CAN_RF0R_FMP0 CAN_RF0R_FMP0_Msk
3211#define CAN_RF0R_FULL0_Pos (3U)
3212#define CAN_RF0R_FULL0_Msk (0x1UL << CAN_RF0R_FULL0_Pos)
3213#define CAN_RF0R_FULL0 CAN_RF0R_FULL0_Msk
3214#define CAN_RF0R_FOVR0_Pos (4U)
3215#define CAN_RF0R_FOVR0_Msk (0x1UL << CAN_RF0R_FOVR0_Pos)
3216#define CAN_RF0R_FOVR0 CAN_RF0R_FOVR0_Msk
3217#define CAN_RF0R_RFOM0_Pos (5U)
3218#define CAN_RF0R_RFOM0_Msk (0x1UL << CAN_RF0R_RFOM0_Pos)
3219#define CAN_RF0R_RFOM0 CAN_RF0R_RFOM0_Msk
3221/******************* Bit definition for CAN_RF1R register *******************/
3222#define CAN_RF1R_FMP1_Pos (0U)
3223#define CAN_RF1R_FMP1_Msk (0x3UL << CAN_RF1R_FMP1_Pos)
3224#define CAN_RF1R_FMP1 CAN_RF1R_FMP1_Msk
3225#define CAN_RF1R_FULL1_Pos (3U)
3226#define CAN_RF1R_FULL1_Msk (0x1UL << CAN_RF1R_FULL1_Pos)
3227#define CAN_RF1R_FULL1 CAN_RF1R_FULL1_Msk
3228#define CAN_RF1R_FOVR1_Pos (4U)
3229#define CAN_RF1R_FOVR1_Msk (0x1UL << CAN_RF1R_FOVR1_Pos)
3230#define CAN_RF1R_FOVR1 CAN_RF1R_FOVR1_Msk
3231#define CAN_RF1R_RFOM1_Pos (5U)
3232#define CAN_RF1R_RFOM1_Msk (0x1UL << CAN_RF1R_RFOM1_Pos)
3233#define CAN_RF1R_RFOM1 CAN_RF1R_RFOM1_Msk
3235/******************** Bit definition for CAN_IER register *******************/
3236#define CAN_IER_TMEIE_Pos (0U)
3237#define CAN_IER_TMEIE_Msk (0x1UL << CAN_IER_TMEIE_Pos)
3238#define CAN_IER_TMEIE CAN_IER_TMEIE_Msk
3239#define CAN_IER_FMPIE0_Pos (1U)
3240#define CAN_IER_FMPIE0_Msk (0x1UL << CAN_IER_FMPIE0_Pos)
3241#define CAN_IER_FMPIE0 CAN_IER_FMPIE0_Msk
3242#define CAN_IER_FFIE0_Pos (2U)
3243#define CAN_IER_FFIE0_Msk (0x1UL << CAN_IER_FFIE0_Pos)
3244#define CAN_IER_FFIE0 CAN_IER_FFIE0_Msk
3245#define CAN_IER_FOVIE0_Pos (3U)
3246#define CAN_IER_FOVIE0_Msk (0x1UL << CAN_IER_FOVIE0_Pos)
3247#define CAN_IER_FOVIE0 CAN_IER_FOVIE0_Msk
3248#define CAN_IER_FMPIE1_Pos (4U)
3249#define CAN_IER_FMPIE1_Msk (0x1UL << CAN_IER_FMPIE1_Pos)
3250#define CAN_IER_FMPIE1 CAN_IER_FMPIE1_Msk
3251#define CAN_IER_FFIE1_Pos (5U)
3252#define CAN_IER_FFIE1_Msk (0x1UL << CAN_IER_FFIE1_Pos)
3253#define CAN_IER_FFIE1 CAN_IER_FFIE1_Msk
3254#define CAN_IER_FOVIE1_Pos (6U)
3255#define CAN_IER_FOVIE1_Msk (0x1UL << CAN_IER_FOVIE1_Pos)
3256#define CAN_IER_FOVIE1 CAN_IER_FOVIE1_Msk
3257#define CAN_IER_EWGIE_Pos (8U)
3258#define CAN_IER_EWGIE_Msk (0x1UL << CAN_IER_EWGIE_Pos)
3259#define CAN_IER_EWGIE CAN_IER_EWGIE_Msk
3260#define CAN_IER_EPVIE_Pos (9U)
3261#define CAN_IER_EPVIE_Msk (0x1UL << CAN_IER_EPVIE_Pos)
3262#define CAN_IER_EPVIE CAN_IER_EPVIE_Msk
3263#define CAN_IER_BOFIE_Pos (10U)
3264#define CAN_IER_BOFIE_Msk (0x1UL << CAN_IER_BOFIE_Pos)
3265#define CAN_IER_BOFIE CAN_IER_BOFIE_Msk
3266#define CAN_IER_LECIE_Pos (11U)
3267#define CAN_IER_LECIE_Msk (0x1UL << CAN_IER_LECIE_Pos)
3268#define CAN_IER_LECIE CAN_IER_LECIE_Msk
3269#define CAN_IER_ERRIE_Pos (15U)
3270#define CAN_IER_ERRIE_Msk (0x1UL << CAN_IER_ERRIE_Pos)
3271#define CAN_IER_ERRIE CAN_IER_ERRIE_Msk
3272#define CAN_IER_WKUIE_Pos (16U)
3273#define CAN_IER_WKUIE_Msk (0x1UL << CAN_IER_WKUIE_Pos)
3274#define CAN_IER_WKUIE CAN_IER_WKUIE_Msk
3275#define CAN_IER_SLKIE_Pos (17U)
3276#define CAN_IER_SLKIE_Msk (0x1UL << CAN_IER_SLKIE_Pos)
3277#define CAN_IER_SLKIE CAN_IER_SLKIE_Msk
3279/******************** Bit definition for CAN_ESR register *******************/
3280#define CAN_ESR_EWGF_Pos (0U)
3281#define CAN_ESR_EWGF_Msk (0x1UL << CAN_ESR_EWGF_Pos)
3282#define CAN_ESR_EWGF CAN_ESR_EWGF_Msk
3283#define CAN_ESR_EPVF_Pos (1U)
3284#define CAN_ESR_EPVF_Msk (0x1UL << CAN_ESR_EPVF_Pos)
3285#define CAN_ESR_EPVF CAN_ESR_EPVF_Msk
3286#define CAN_ESR_BOFF_Pos (2U)
3287#define CAN_ESR_BOFF_Msk (0x1UL << CAN_ESR_BOFF_Pos)
3288#define CAN_ESR_BOFF CAN_ESR_BOFF_Msk
3290#define CAN_ESR_LEC_Pos (4U)
3291#define CAN_ESR_LEC_Msk (0x7UL << CAN_ESR_LEC_Pos)
3292#define CAN_ESR_LEC CAN_ESR_LEC_Msk
3293#define CAN_ESR_LEC_0 (0x1UL << CAN_ESR_LEC_Pos)
3294#define CAN_ESR_LEC_1 (0x2UL << CAN_ESR_LEC_Pos)
3295#define CAN_ESR_LEC_2 (0x4UL << CAN_ESR_LEC_Pos)
3297#define CAN_ESR_TEC_Pos (16U)
3298#define CAN_ESR_TEC_Msk (0xFFUL << CAN_ESR_TEC_Pos)
3299#define CAN_ESR_TEC CAN_ESR_TEC_Msk
3300#define CAN_ESR_REC_Pos (24U)
3301#define CAN_ESR_REC_Msk (0xFFUL << CAN_ESR_REC_Pos)
3302#define CAN_ESR_REC CAN_ESR_REC_Msk
3304/******************* Bit definition for CAN_BTR register ********************/
3305#define CAN_BTR_BRP_Pos (0U)
3306#define CAN_BTR_BRP_Msk (0x3FFUL << CAN_BTR_BRP_Pos)
3307#define CAN_BTR_BRP CAN_BTR_BRP_Msk
3308#define CAN_BTR_TS1_Pos (16U)
3309#define CAN_BTR_TS1_Msk (0xFUL << CAN_BTR_TS1_Pos)
3310#define CAN_BTR_TS1 CAN_BTR_TS1_Msk
3311#define CAN_BTR_TS1_0 (0x1UL << CAN_BTR_TS1_Pos)
3312#define CAN_BTR_TS1_1 (0x2UL << CAN_BTR_TS1_Pos)
3313#define CAN_BTR_TS1_2 (0x4UL << CAN_BTR_TS1_Pos)
3314#define CAN_BTR_TS1_3 (0x8UL << CAN_BTR_TS1_Pos)
3315#define CAN_BTR_TS2_Pos (20U)
3316#define CAN_BTR_TS2_Msk (0x7UL << CAN_BTR_TS2_Pos)
3317#define CAN_BTR_TS2 CAN_BTR_TS2_Msk
3318#define CAN_BTR_TS2_0 (0x1UL << CAN_BTR_TS2_Pos)
3319#define CAN_BTR_TS2_1 (0x2UL << CAN_BTR_TS2_Pos)
3320#define CAN_BTR_TS2_2 (0x4UL << CAN_BTR_TS2_Pos)
3321#define CAN_BTR_SJW_Pos (24U)
3322#define CAN_BTR_SJW_Msk (0x3UL << CAN_BTR_SJW_Pos)
3323#define CAN_BTR_SJW CAN_BTR_SJW_Msk
3324#define CAN_BTR_SJW_0 (0x1UL << CAN_BTR_SJW_Pos)
3325#define CAN_BTR_SJW_1 (0x2UL << CAN_BTR_SJW_Pos)
3326#define CAN_BTR_LBKM_Pos (30U)
3327#define CAN_BTR_LBKM_Msk (0x1UL << CAN_BTR_LBKM_Pos)
3328#define CAN_BTR_LBKM CAN_BTR_LBKM_Msk
3329#define CAN_BTR_SILM_Pos (31U)
3330#define CAN_BTR_SILM_Msk (0x1UL << CAN_BTR_SILM_Pos)
3331#define CAN_BTR_SILM CAN_BTR_SILM_Msk
3334/****************** Bit definition for CAN_TI0R register ********************/
3335#define CAN_TI0R_TXRQ_Pos (0U)
3336#define CAN_TI0R_TXRQ_Msk (0x1UL << CAN_TI0R_TXRQ_Pos)
3337#define CAN_TI0R_TXRQ CAN_TI0R_TXRQ_Msk
3338#define CAN_TI0R_RTR_Pos (1U)
3339#define CAN_TI0R_RTR_Msk (0x1UL << CAN_TI0R_RTR_Pos)
3340#define CAN_TI0R_RTR CAN_TI0R_RTR_Msk
3341#define CAN_TI0R_IDE_Pos (2U)
3342#define CAN_TI0R_IDE_Msk (0x1UL << CAN_TI0R_IDE_Pos)
3343#define CAN_TI0R_IDE CAN_TI0R_IDE_Msk
3344#define CAN_TI0R_EXID_Pos (3U)
3345#define CAN_TI0R_EXID_Msk (0x3FFFFUL << CAN_TI0R_EXID_Pos)
3346#define CAN_TI0R_EXID CAN_TI0R_EXID_Msk
3347#define CAN_TI0R_STID_Pos (21U)
3348#define CAN_TI0R_STID_Msk (0x7FFUL << CAN_TI0R_STID_Pos)
3349#define CAN_TI0R_STID CAN_TI0R_STID_Msk
3351/****************** Bit definition for CAN_TDT0R register *******************/
3352#define CAN_TDT0R_DLC_Pos (0U)
3353#define CAN_TDT0R_DLC_Msk (0xFUL << CAN_TDT0R_DLC_Pos)
3354#define CAN_TDT0R_DLC CAN_TDT0R_DLC_Msk
3355#define CAN_TDT0R_TGT_Pos (8U)
3356#define CAN_TDT0R_TGT_Msk (0x1UL << CAN_TDT0R_TGT_Pos)
3357#define CAN_TDT0R_TGT CAN_TDT0R_TGT_Msk
3358#define CAN_TDT0R_TIME_Pos (16U)
3359#define CAN_TDT0R_TIME_Msk (0xFFFFUL << CAN_TDT0R_TIME_Pos)
3360#define CAN_TDT0R_TIME CAN_TDT0R_TIME_Msk
3362/****************** Bit definition for CAN_TDL0R register *******************/
3363#define CAN_TDL0R_DATA0_Pos (0U)
3364#define CAN_TDL0R_DATA0_Msk (0xFFUL << CAN_TDL0R_DATA0_Pos)
3365#define CAN_TDL0R_DATA0 CAN_TDL0R_DATA0_Msk
3366#define CAN_TDL0R_DATA1_Pos (8U)
3367#define CAN_TDL0R_DATA1_Msk (0xFFUL << CAN_TDL0R_DATA1_Pos)
3368#define CAN_TDL0R_DATA1 CAN_TDL0R_DATA1_Msk
3369#define CAN_TDL0R_DATA2_Pos (16U)
3370#define CAN_TDL0R_DATA2_Msk (0xFFUL << CAN_TDL0R_DATA2_Pos)
3371#define CAN_TDL0R_DATA2 CAN_TDL0R_DATA2_Msk
3372#define CAN_TDL0R_DATA3_Pos (24U)
3373#define CAN_TDL0R_DATA3_Msk (0xFFUL << CAN_TDL0R_DATA3_Pos)
3374#define CAN_TDL0R_DATA3 CAN_TDL0R_DATA3_Msk
3376/****************** Bit definition for CAN_TDH0R register *******************/
3377#define CAN_TDH0R_DATA4_Pos (0U)
3378#define CAN_TDH0R_DATA4_Msk (0xFFUL << CAN_TDH0R_DATA4_Pos)
3379#define CAN_TDH0R_DATA4 CAN_TDH0R_DATA4_Msk
3380#define CAN_TDH0R_DATA5_Pos (8U)
3381#define CAN_TDH0R_DATA5_Msk (0xFFUL << CAN_TDH0R_DATA5_Pos)
3382#define CAN_TDH0R_DATA5 CAN_TDH0R_DATA5_Msk
3383#define CAN_TDH0R_DATA6_Pos (16U)
3384#define CAN_TDH0R_DATA6_Msk (0xFFUL << CAN_TDH0R_DATA6_Pos)
3385#define CAN_TDH0R_DATA6 CAN_TDH0R_DATA6_Msk
3386#define CAN_TDH0R_DATA7_Pos (24U)
3387#define CAN_TDH0R_DATA7_Msk (0xFFUL << CAN_TDH0R_DATA7_Pos)
3388#define CAN_TDH0R_DATA7 CAN_TDH0R_DATA7_Msk
3390/******************* Bit definition for CAN_TI1R register *******************/
3391#define CAN_TI1R_TXRQ_Pos (0U)
3392#define CAN_TI1R_TXRQ_Msk (0x1UL << CAN_TI1R_TXRQ_Pos)
3393#define CAN_TI1R_TXRQ CAN_TI1R_TXRQ_Msk
3394#define CAN_TI1R_RTR_Pos (1U)
3395#define CAN_TI1R_RTR_Msk (0x1UL << CAN_TI1R_RTR_Pos)
3396#define CAN_TI1R_RTR CAN_TI1R_RTR_Msk
3397#define CAN_TI1R_IDE_Pos (2U)
3398#define CAN_TI1R_IDE_Msk (0x1UL << CAN_TI1R_IDE_Pos)
3399#define CAN_TI1R_IDE CAN_TI1R_IDE_Msk
3400#define CAN_TI1R_EXID_Pos (3U)
3401#define CAN_TI1R_EXID_Msk (0x3FFFFUL << CAN_TI1R_EXID_Pos)
3402#define CAN_TI1R_EXID CAN_TI1R_EXID_Msk
3403#define CAN_TI1R_STID_Pos (21U)
3404#define CAN_TI1R_STID_Msk (0x7FFUL << CAN_TI1R_STID_Pos)
3405#define CAN_TI1R_STID CAN_TI1R_STID_Msk
3407/******************* Bit definition for CAN_TDT1R register ******************/
3408#define CAN_TDT1R_DLC_Pos (0U)
3409#define CAN_TDT1R_DLC_Msk (0xFUL << CAN_TDT1R_DLC_Pos)
3410#define CAN_TDT1R_DLC CAN_TDT1R_DLC_Msk
3411#define CAN_TDT1R_TGT_Pos (8U)
3412#define CAN_TDT1R_TGT_Msk (0x1UL << CAN_TDT1R_TGT_Pos)
3413#define CAN_TDT1R_TGT CAN_TDT1R_TGT_Msk
3414#define CAN_TDT1R_TIME_Pos (16U)
3415#define CAN_TDT1R_TIME_Msk (0xFFFFUL << CAN_TDT1R_TIME_Pos)
3416#define CAN_TDT1R_TIME CAN_TDT1R_TIME_Msk
3418/******************* Bit definition for CAN_TDL1R register ******************/
3419#define CAN_TDL1R_DATA0_Pos (0U)
3420#define CAN_TDL1R_DATA0_Msk (0xFFUL << CAN_TDL1R_DATA0_Pos)
3421#define CAN_TDL1R_DATA0 CAN_TDL1R_DATA0_Msk
3422#define CAN_TDL1R_DATA1_Pos (8U)
3423#define CAN_TDL1R_DATA1_Msk (0xFFUL << CAN_TDL1R_DATA1_Pos)
3424#define CAN_TDL1R_DATA1 CAN_TDL1R_DATA1_Msk
3425#define CAN_TDL1R_DATA2_Pos (16U)
3426#define CAN_TDL1R_DATA2_Msk (0xFFUL << CAN_TDL1R_DATA2_Pos)
3427#define CAN_TDL1R_DATA2 CAN_TDL1R_DATA2_Msk
3428#define CAN_TDL1R_DATA3_Pos (24U)
3429#define CAN_TDL1R_DATA3_Msk (0xFFUL << CAN_TDL1R_DATA3_Pos)
3430#define CAN_TDL1R_DATA3 CAN_TDL1R_DATA3_Msk
3432/******************* Bit definition for CAN_TDH1R register ******************/
3433#define CAN_TDH1R_DATA4_Pos (0U)
3434#define CAN_TDH1R_DATA4_Msk (0xFFUL << CAN_TDH1R_DATA4_Pos)
3435#define CAN_TDH1R_DATA4 CAN_TDH1R_DATA4_Msk
3436#define CAN_TDH1R_DATA5_Pos (8U)
3437#define CAN_TDH1R_DATA5_Msk (0xFFUL << CAN_TDH1R_DATA5_Pos)
3438#define CAN_TDH1R_DATA5 CAN_TDH1R_DATA5_Msk
3439#define CAN_TDH1R_DATA6_Pos (16U)
3440#define CAN_TDH1R_DATA6_Msk (0xFFUL << CAN_TDH1R_DATA6_Pos)
3441#define CAN_TDH1R_DATA6 CAN_TDH1R_DATA6_Msk
3442#define CAN_TDH1R_DATA7_Pos (24U)
3443#define CAN_TDH1R_DATA7_Msk (0xFFUL << CAN_TDH1R_DATA7_Pos)
3444#define CAN_TDH1R_DATA7 CAN_TDH1R_DATA7_Msk
3446/******************* Bit definition for CAN_TI2R register *******************/
3447#define CAN_TI2R_TXRQ_Pos (0U)
3448#define CAN_TI2R_TXRQ_Msk (0x1UL << CAN_TI2R_TXRQ_Pos)
3449#define CAN_TI2R_TXRQ CAN_TI2R_TXRQ_Msk
3450#define CAN_TI2R_RTR_Pos (1U)
3451#define CAN_TI2R_RTR_Msk (0x1UL << CAN_TI2R_RTR_Pos)
3452#define CAN_TI2R_RTR CAN_TI2R_RTR_Msk
3453#define CAN_TI2R_IDE_Pos (2U)
3454#define CAN_TI2R_IDE_Msk (0x1UL << CAN_TI2R_IDE_Pos)
3455#define CAN_TI2R_IDE CAN_TI2R_IDE_Msk
3456#define CAN_TI2R_EXID_Pos (3U)
3457#define CAN_TI2R_EXID_Msk (0x3FFFFUL << CAN_TI2R_EXID_Pos)
3458#define CAN_TI2R_EXID CAN_TI2R_EXID_Msk
3459#define CAN_TI2R_STID_Pos (21U)
3460#define CAN_TI2R_STID_Msk (0x7FFUL << CAN_TI2R_STID_Pos)
3461#define CAN_TI2R_STID CAN_TI2R_STID_Msk
3463/******************* Bit definition for CAN_TDT2R register ******************/
3464#define CAN_TDT2R_DLC_Pos (0U)
3465#define CAN_TDT2R_DLC_Msk (0xFUL << CAN_TDT2R_DLC_Pos)
3466#define CAN_TDT2R_DLC CAN_TDT2R_DLC_Msk
3467#define CAN_TDT2R_TGT_Pos (8U)
3468#define CAN_TDT2R_TGT_Msk (0x1UL << CAN_TDT2R_TGT_Pos)
3469#define CAN_TDT2R_TGT CAN_TDT2R_TGT_Msk
3470#define CAN_TDT2R_TIME_Pos (16U)
3471#define CAN_TDT2R_TIME_Msk (0xFFFFUL << CAN_TDT2R_TIME_Pos)
3472#define CAN_TDT2R_TIME CAN_TDT2R_TIME_Msk
3474/******************* Bit definition for CAN_TDL2R register ******************/
3475#define CAN_TDL2R_DATA0_Pos (0U)
3476#define CAN_TDL2R_DATA0_Msk (0xFFUL << CAN_TDL2R_DATA0_Pos)
3477#define CAN_TDL2R_DATA0 CAN_TDL2R_DATA0_Msk
3478#define CAN_TDL2R_DATA1_Pos (8U)
3479#define CAN_TDL2R_DATA1_Msk (0xFFUL << CAN_TDL2R_DATA1_Pos)
3480#define CAN_TDL2R_DATA1 CAN_TDL2R_DATA1_Msk
3481#define CAN_TDL2R_DATA2_Pos (16U)
3482#define CAN_TDL2R_DATA2_Msk (0xFFUL << CAN_TDL2R_DATA2_Pos)
3483#define CAN_TDL2R_DATA2 CAN_TDL2R_DATA2_Msk
3484#define CAN_TDL2R_DATA3_Pos (24U)
3485#define CAN_TDL2R_DATA3_Msk (0xFFUL << CAN_TDL2R_DATA3_Pos)
3486#define CAN_TDL2R_DATA3 CAN_TDL2R_DATA3_Msk
3488/******************* Bit definition for CAN_TDH2R register ******************/
3489#define CAN_TDH2R_DATA4_Pos (0U)
3490#define CAN_TDH2R_DATA4_Msk (0xFFUL << CAN_TDH2R_DATA4_Pos)
3491#define CAN_TDH2R_DATA4 CAN_TDH2R_DATA4_Msk
3492#define CAN_TDH2R_DATA5_Pos (8U)
3493#define CAN_TDH2R_DATA5_Msk (0xFFUL << CAN_TDH2R_DATA5_Pos)
3494#define CAN_TDH2R_DATA5 CAN_TDH2R_DATA5_Msk
3495#define CAN_TDH2R_DATA6_Pos (16U)
3496#define CAN_TDH2R_DATA6_Msk (0xFFUL << CAN_TDH2R_DATA6_Pos)
3497#define CAN_TDH2R_DATA6 CAN_TDH2R_DATA6_Msk
3498#define CAN_TDH2R_DATA7_Pos (24U)
3499#define CAN_TDH2R_DATA7_Msk (0xFFUL << CAN_TDH2R_DATA7_Pos)
3500#define CAN_TDH2R_DATA7 CAN_TDH2R_DATA7_Msk
3502/******************* Bit definition for CAN_RI0R register *******************/
3503#define CAN_RI0R_RTR_Pos (1U)
3504#define CAN_RI0R_RTR_Msk (0x1UL << CAN_RI0R_RTR_Pos)
3505#define CAN_RI0R_RTR CAN_RI0R_RTR_Msk
3506#define CAN_RI0R_IDE_Pos (2U)
3507#define CAN_RI0R_IDE_Msk (0x1UL << CAN_RI0R_IDE_Pos)
3508#define CAN_RI0R_IDE CAN_RI0R_IDE_Msk
3509#define CAN_RI0R_EXID_Pos (3U)
3510#define CAN_RI0R_EXID_Msk (0x3FFFFUL << CAN_RI0R_EXID_Pos)
3511#define CAN_RI0R_EXID CAN_RI0R_EXID_Msk
3512#define CAN_RI0R_STID_Pos (21U)
3513#define CAN_RI0R_STID_Msk (0x7FFUL << CAN_RI0R_STID_Pos)
3514#define CAN_RI0R_STID CAN_RI0R_STID_Msk
3516/******************* Bit definition for CAN_RDT0R register ******************/
3517#define CAN_RDT0R_DLC_Pos (0U)
3518#define CAN_RDT0R_DLC_Msk (0xFUL << CAN_RDT0R_DLC_Pos)
3519#define CAN_RDT0R_DLC CAN_RDT0R_DLC_Msk
3520#define CAN_RDT0R_FMI_Pos (8U)
3521#define CAN_RDT0R_FMI_Msk (0xFFUL << CAN_RDT0R_FMI_Pos)
3522#define CAN_RDT0R_FMI CAN_RDT0R_FMI_Msk
3523#define CAN_RDT0R_TIME_Pos (16U)
3524#define CAN_RDT0R_TIME_Msk (0xFFFFUL << CAN_RDT0R_TIME_Pos)
3525#define CAN_RDT0R_TIME CAN_RDT0R_TIME_Msk
3527/******************* Bit definition for CAN_RDL0R register ******************/
3528#define CAN_RDL0R_DATA0_Pos (0U)
3529#define CAN_RDL0R_DATA0_Msk (0xFFUL << CAN_RDL0R_DATA0_Pos)
3530#define CAN_RDL0R_DATA0 CAN_RDL0R_DATA0_Msk
3531#define CAN_RDL0R_DATA1_Pos (8U)
3532#define CAN_RDL0R_DATA1_Msk (0xFFUL << CAN_RDL0R_DATA1_Pos)
3533#define CAN_RDL0R_DATA1 CAN_RDL0R_DATA1_Msk
3534#define CAN_RDL0R_DATA2_Pos (16U)
3535#define CAN_RDL0R_DATA2_Msk (0xFFUL << CAN_RDL0R_DATA2_Pos)
3536#define CAN_RDL0R_DATA2 CAN_RDL0R_DATA2_Msk
3537#define CAN_RDL0R_DATA3_Pos (24U)
3538#define CAN_RDL0R_DATA3_Msk (0xFFUL << CAN_RDL0R_DATA3_Pos)
3539#define CAN_RDL0R_DATA3 CAN_RDL0R_DATA3_Msk
3541/******************* Bit definition for CAN_RDH0R register ******************/
3542#define CAN_RDH0R_DATA4_Pos (0U)
3543#define CAN_RDH0R_DATA4_Msk (0xFFUL << CAN_RDH0R_DATA4_Pos)
3544#define CAN_RDH0R_DATA4 CAN_RDH0R_DATA4_Msk
3545#define CAN_RDH0R_DATA5_Pos (8U)
3546#define CAN_RDH0R_DATA5_Msk (0xFFUL << CAN_RDH0R_DATA5_Pos)
3547#define CAN_RDH0R_DATA5 CAN_RDH0R_DATA5_Msk
3548#define CAN_RDH0R_DATA6_Pos (16U)
3549#define CAN_RDH0R_DATA6_Msk (0xFFUL << CAN_RDH0R_DATA6_Pos)
3550#define CAN_RDH0R_DATA6 CAN_RDH0R_DATA6_Msk
3551#define CAN_RDH0R_DATA7_Pos (24U)
3552#define CAN_RDH0R_DATA7_Msk (0xFFUL << CAN_RDH0R_DATA7_Pos)
3553#define CAN_RDH0R_DATA7 CAN_RDH0R_DATA7_Msk
3555/******************* Bit definition for CAN_RI1R register *******************/
3556#define CAN_RI1R_RTR_Pos (1U)
3557#define CAN_RI1R_RTR_Msk (0x1UL << CAN_RI1R_RTR_Pos)
3558#define CAN_RI1R_RTR CAN_RI1R_RTR_Msk
3559#define CAN_RI1R_IDE_Pos (2U)
3560#define CAN_RI1R_IDE_Msk (0x1UL << CAN_RI1R_IDE_Pos)
3561#define CAN_RI1R_IDE CAN_RI1R_IDE_Msk
3562#define CAN_RI1R_EXID_Pos (3U)
3563#define CAN_RI1R_EXID_Msk (0x3FFFFUL << CAN_RI1R_EXID_Pos)
3564#define CAN_RI1R_EXID CAN_RI1R_EXID_Msk
3565#define CAN_RI1R_STID_Pos (21U)
3566#define CAN_RI1R_STID_Msk (0x7FFUL << CAN_RI1R_STID_Pos)
3567#define CAN_RI1R_STID CAN_RI1R_STID_Msk
3569/******************* Bit definition for CAN_RDT1R register ******************/
3570#define CAN_RDT1R_DLC_Pos (0U)
3571#define CAN_RDT1R_DLC_Msk (0xFUL << CAN_RDT1R_DLC_Pos)
3572#define CAN_RDT1R_DLC CAN_RDT1R_DLC_Msk
3573#define CAN_RDT1R_FMI_Pos (8U)
3574#define CAN_RDT1R_FMI_Msk (0xFFUL << CAN_RDT1R_FMI_Pos)
3575#define CAN_RDT1R_FMI CAN_RDT1R_FMI_Msk
3576#define CAN_RDT1R_TIME_Pos (16U)
3577#define CAN_RDT1R_TIME_Msk (0xFFFFUL << CAN_RDT1R_TIME_Pos)
3578#define CAN_RDT1R_TIME CAN_RDT1R_TIME_Msk
3580/******************* Bit definition for CAN_RDL1R register ******************/
3581#define CAN_RDL1R_DATA0_Pos (0U)
3582#define CAN_RDL1R_DATA0_Msk (0xFFUL << CAN_RDL1R_DATA0_Pos)
3583#define CAN_RDL1R_DATA0 CAN_RDL1R_DATA0_Msk
3584#define CAN_RDL1R_DATA1_Pos (8U)
3585#define CAN_RDL1R_DATA1_Msk (0xFFUL << CAN_RDL1R_DATA1_Pos)
3586#define CAN_RDL1R_DATA1 CAN_RDL1R_DATA1_Msk
3587#define CAN_RDL1R_DATA2_Pos (16U)
3588#define CAN_RDL1R_DATA2_Msk (0xFFUL << CAN_RDL1R_DATA2_Pos)
3589#define CAN_RDL1R_DATA2 CAN_RDL1R_DATA2_Msk
3590#define CAN_RDL1R_DATA3_Pos (24U)
3591#define CAN_RDL1R_DATA3_Msk (0xFFUL << CAN_RDL1R_DATA3_Pos)
3592#define CAN_RDL1R_DATA3 CAN_RDL1R_DATA3_Msk
3594/******************* Bit definition for CAN_RDH1R register ******************/
3595#define CAN_RDH1R_DATA4_Pos (0U)
3596#define CAN_RDH1R_DATA4_Msk (0xFFUL << CAN_RDH1R_DATA4_Pos)
3597#define CAN_RDH1R_DATA4 CAN_RDH1R_DATA4_Msk
3598#define CAN_RDH1R_DATA5_Pos (8U)
3599#define CAN_RDH1R_DATA5_Msk (0xFFUL << CAN_RDH1R_DATA5_Pos)
3600#define CAN_RDH1R_DATA5 CAN_RDH1R_DATA5_Msk
3601#define CAN_RDH1R_DATA6_Pos (16U)
3602#define CAN_RDH1R_DATA6_Msk (0xFFUL << CAN_RDH1R_DATA6_Pos)
3603#define CAN_RDH1R_DATA6 CAN_RDH1R_DATA6_Msk
3604#define CAN_RDH1R_DATA7_Pos (24U)
3605#define CAN_RDH1R_DATA7_Msk (0xFFUL << CAN_RDH1R_DATA7_Pos)
3606#define CAN_RDH1R_DATA7 CAN_RDH1R_DATA7_Msk
3609/******************* Bit definition for CAN_FMR register ********************/
3610#define CAN_FMR_FINIT_Pos (0U)
3611#define CAN_FMR_FINIT_Msk (0x1UL << CAN_FMR_FINIT_Pos)
3612#define CAN_FMR_FINIT CAN_FMR_FINIT_Msk
3614/******************* Bit definition for CAN_FM1R register *******************/
3615#define CAN_FM1R_FBM_Pos (0U)
3616#define CAN_FM1R_FBM_Msk (0x3FFFUL << CAN_FM1R_FBM_Pos)
3617#define CAN_FM1R_FBM CAN_FM1R_FBM_Msk
3618#define CAN_FM1R_FBM0_Pos (0U)
3619#define CAN_FM1R_FBM0_Msk (0x1UL << CAN_FM1R_FBM0_Pos)
3620#define CAN_FM1R_FBM0 CAN_FM1R_FBM0_Msk
3621#define CAN_FM1R_FBM1_Pos (1U)
3622#define CAN_FM1R_FBM1_Msk (0x1UL << CAN_FM1R_FBM1_Pos)
3623#define CAN_FM1R_FBM1 CAN_FM1R_FBM1_Msk
3624#define CAN_FM1R_FBM2_Pos (2U)
3625#define CAN_FM1R_FBM2_Msk (0x1UL << CAN_FM1R_FBM2_Pos)
3626#define CAN_FM1R_FBM2 CAN_FM1R_FBM2_Msk
3627#define CAN_FM1R_FBM3_Pos (3U)
3628#define CAN_FM1R_FBM3_Msk (0x1UL << CAN_FM1R_FBM3_Pos)
3629#define CAN_FM1R_FBM3 CAN_FM1R_FBM3_Msk
3630#define CAN_FM1R_FBM4_Pos (4U)
3631#define CAN_FM1R_FBM4_Msk (0x1UL << CAN_FM1R_FBM4_Pos)
3632#define CAN_FM1R_FBM4 CAN_FM1R_FBM4_Msk
3633#define CAN_FM1R_FBM5_Pos (5U)
3634#define CAN_FM1R_FBM5_Msk (0x1UL << CAN_FM1R_FBM5_Pos)
3635#define CAN_FM1R_FBM5 CAN_FM1R_FBM5_Msk
3636#define CAN_FM1R_FBM6_Pos (6U)
3637#define CAN_FM1R_FBM6_Msk (0x1UL << CAN_FM1R_FBM6_Pos)
3638#define CAN_FM1R_FBM6 CAN_FM1R_FBM6_Msk
3639#define CAN_FM1R_FBM7_Pos (7U)
3640#define CAN_FM1R_FBM7_Msk (0x1UL << CAN_FM1R_FBM7_Pos)
3641#define CAN_FM1R_FBM7 CAN_FM1R_FBM7_Msk
3642#define CAN_FM1R_FBM8_Pos (8U)
3643#define CAN_FM1R_FBM8_Msk (0x1UL << CAN_FM1R_FBM8_Pos)
3644#define CAN_FM1R_FBM8 CAN_FM1R_FBM8_Msk
3645#define CAN_FM1R_FBM9_Pos (9U)
3646#define CAN_FM1R_FBM9_Msk (0x1UL << CAN_FM1R_FBM9_Pos)
3647#define CAN_FM1R_FBM9 CAN_FM1R_FBM9_Msk
3648#define CAN_FM1R_FBM10_Pos (10U)
3649#define CAN_FM1R_FBM10_Msk (0x1UL << CAN_FM1R_FBM10_Pos)
3650#define CAN_FM1R_FBM10 CAN_FM1R_FBM10_Msk
3651#define CAN_FM1R_FBM11_Pos (11U)
3652#define CAN_FM1R_FBM11_Msk (0x1UL << CAN_FM1R_FBM11_Pos)
3653#define CAN_FM1R_FBM11 CAN_FM1R_FBM11_Msk
3654#define CAN_FM1R_FBM12_Pos (12U)
3655#define CAN_FM1R_FBM12_Msk (0x1UL << CAN_FM1R_FBM12_Pos)
3656#define CAN_FM1R_FBM12 CAN_FM1R_FBM12_Msk
3657#define CAN_FM1R_FBM13_Pos (13U)
3658#define CAN_FM1R_FBM13_Msk (0x1UL << CAN_FM1R_FBM13_Pos)
3659#define CAN_FM1R_FBM13 CAN_FM1R_FBM13_Msk
3661/******************* Bit definition for CAN_FS1R register *******************/
3662#define CAN_FS1R_FSC_Pos (0U)
3663#define CAN_FS1R_FSC_Msk (0x3FFFUL << CAN_FS1R_FSC_Pos)
3664#define CAN_FS1R_FSC CAN_FS1R_FSC_Msk
3665#define CAN_FS1R_FSC0_Pos (0U)
3666#define CAN_FS1R_FSC0_Msk (0x1UL << CAN_FS1R_FSC0_Pos)
3667#define CAN_FS1R_FSC0 CAN_FS1R_FSC0_Msk
3668#define CAN_FS1R_FSC1_Pos (1U)
3669#define CAN_FS1R_FSC1_Msk (0x1UL << CAN_FS1R_FSC1_Pos)
3670#define CAN_FS1R_FSC1 CAN_FS1R_FSC1_Msk
3671#define CAN_FS1R_FSC2_Pos (2U)
3672#define CAN_FS1R_FSC2_Msk (0x1UL << CAN_FS1R_FSC2_Pos)
3673#define CAN_FS1R_FSC2 CAN_FS1R_FSC2_Msk
3674#define CAN_FS1R_FSC3_Pos (3U)
3675#define CAN_FS1R_FSC3_Msk (0x1UL << CAN_FS1R_FSC3_Pos)
3676#define CAN_FS1R_FSC3 CAN_FS1R_FSC3_Msk
3677#define CAN_FS1R_FSC4_Pos (4U)
3678#define CAN_FS1R_FSC4_Msk (0x1UL << CAN_FS1R_FSC4_Pos)
3679#define CAN_FS1R_FSC4 CAN_FS1R_FSC4_Msk
3680#define CAN_FS1R_FSC5_Pos (5U)
3681#define CAN_FS1R_FSC5_Msk (0x1UL << CAN_FS1R_FSC5_Pos)
3682#define CAN_FS1R_FSC5 CAN_FS1R_FSC5_Msk
3683#define CAN_FS1R_FSC6_Pos (6U)
3684#define CAN_FS1R_FSC6_Msk (0x1UL << CAN_FS1R_FSC6_Pos)
3685#define CAN_FS1R_FSC6 CAN_FS1R_FSC6_Msk
3686#define CAN_FS1R_FSC7_Pos (7U)
3687#define CAN_FS1R_FSC7_Msk (0x1UL << CAN_FS1R_FSC7_Pos)
3688#define CAN_FS1R_FSC7 CAN_FS1R_FSC7_Msk
3689#define CAN_FS1R_FSC8_Pos (8U)
3690#define CAN_FS1R_FSC8_Msk (0x1UL << CAN_FS1R_FSC8_Pos)
3691#define CAN_FS1R_FSC8 CAN_FS1R_FSC8_Msk
3692#define CAN_FS1R_FSC9_Pos (9U)
3693#define CAN_FS1R_FSC9_Msk (0x1UL << CAN_FS1R_FSC9_Pos)
3694#define CAN_FS1R_FSC9 CAN_FS1R_FSC9_Msk
3695#define CAN_FS1R_FSC10_Pos (10U)
3696#define CAN_FS1R_FSC10_Msk (0x1UL << CAN_FS1R_FSC10_Pos)
3697#define CAN_FS1R_FSC10 CAN_FS1R_FSC10_Msk
3698#define CAN_FS1R_FSC11_Pos (11U)
3699#define CAN_FS1R_FSC11_Msk (0x1UL << CAN_FS1R_FSC11_Pos)
3700#define CAN_FS1R_FSC11 CAN_FS1R_FSC11_Msk
3701#define CAN_FS1R_FSC12_Pos (12U)
3702#define CAN_FS1R_FSC12_Msk (0x1UL << CAN_FS1R_FSC12_Pos)
3703#define CAN_FS1R_FSC12 CAN_FS1R_FSC12_Msk
3704#define CAN_FS1R_FSC13_Pos (13U)
3705#define CAN_FS1R_FSC13_Msk (0x1UL << CAN_FS1R_FSC13_Pos)
3706#define CAN_FS1R_FSC13 CAN_FS1R_FSC13_Msk
3708/****************** Bit definition for CAN_FFA1R register *******************/
3709#define CAN_FFA1R_FFA_Pos (0U)
3710#define CAN_FFA1R_FFA_Msk (0x3FFFUL << CAN_FFA1R_FFA_Pos)
3711#define CAN_FFA1R_FFA CAN_FFA1R_FFA_Msk
3712#define CAN_FFA1R_FFA0_Pos (0U)
3713#define CAN_FFA1R_FFA0_Msk (0x1UL << CAN_FFA1R_FFA0_Pos)
3714#define CAN_FFA1R_FFA0 CAN_FFA1R_FFA0_Msk
3715#define CAN_FFA1R_FFA1_Pos (1U)
3716#define CAN_FFA1R_FFA1_Msk (0x1UL << CAN_FFA1R_FFA1_Pos)
3717#define CAN_FFA1R_FFA1 CAN_FFA1R_FFA1_Msk
3718#define CAN_FFA1R_FFA2_Pos (2U)
3719#define CAN_FFA1R_FFA2_Msk (0x1UL << CAN_FFA1R_FFA2_Pos)
3720#define CAN_FFA1R_FFA2 CAN_FFA1R_FFA2_Msk
3721#define CAN_FFA1R_FFA3_Pos (3U)
3722#define CAN_FFA1R_FFA3_Msk (0x1UL << CAN_FFA1R_FFA3_Pos)
3723#define CAN_FFA1R_FFA3 CAN_FFA1R_FFA3_Msk
3724#define CAN_FFA1R_FFA4_Pos (4U)
3725#define CAN_FFA1R_FFA4_Msk (0x1UL << CAN_FFA1R_FFA4_Pos)
3726#define CAN_FFA1R_FFA4 CAN_FFA1R_FFA4_Msk
3727#define CAN_FFA1R_FFA5_Pos (5U)
3728#define CAN_FFA1R_FFA5_Msk (0x1UL << CAN_FFA1R_FFA5_Pos)
3729#define CAN_FFA1R_FFA5 CAN_FFA1R_FFA5_Msk
3730#define CAN_FFA1R_FFA6_Pos (6U)
3731#define CAN_FFA1R_FFA6_Msk (0x1UL << CAN_FFA1R_FFA6_Pos)
3732#define CAN_FFA1R_FFA6 CAN_FFA1R_FFA6_Msk
3733#define CAN_FFA1R_FFA7_Pos (7U)
3734#define CAN_FFA1R_FFA7_Msk (0x1UL << CAN_FFA1R_FFA7_Pos)
3735#define CAN_FFA1R_FFA7 CAN_FFA1R_FFA7_Msk
3736#define CAN_FFA1R_FFA8_Pos (8U)
3737#define CAN_FFA1R_FFA8_Msk (0x1UL << CAN_FFA1R_FFA8_Pos)
3738#define CAN_FFA1R_FFA8 CAN_FFA1R_FFA8_Msk
3739#define CAN_FFA1R_FFA9_Pos (9U)
3740#define CAN_FFA1R_FFA9_Msk (0x1UL << CAN_FFA1R_FFA9_Pos)
3741#define CAN_FFA1R_FFA9 CAN_FFA1R_FFA9_Msk
3742#define CAN_FFA1R_FFA10_Pos (10U)
3743#define CAN_FFA1R_FFA10_Msk (0x1UL << CAN_FFA1R_FFA10_Pos)
3744#define CAN_FFA1R_FFA10 CAN_FFA1R_FFA10_Msk
3745#define CAN_FFA1R_FFA11_Pos (11U)
3746#define CAN_FFA1R_FFA11_Msk (0x1UL << CAN_FFA1R_FFA11_Pos)
3747#define CAN_FFA1R_FFA11 CAN_FFA1R_FFA11_Msk
3748#define CAN_FFA1R_FFA12_Pos (12U)
3749#define CAN_FFA1R_FFA12_Msk (0x1UL << CAN_FFA1R_FFA12_Pos)
3750#define CAN_FFA1R_FFA12 CAN_FFA1R_FFA12_Msk
3751#define CAN_FFA1R_FFA13_Pos (13U)
3752#define CAN_FFA1R_FFA13_Msk (0x1UL << CAN_FFA1R_FFA13_Pos)
3753#define CAN_FFA1R_FFA13 CAN_FFA1R_FFA13_Msk
3755/******************* Bit definition for CAN_FA1R register *******************/
3756#define CAN_FA1R_FACT_Pos (0U)
3757#define CAN_FA1R_FACT_Msk (0x3FFFUL << CAN_FA1R_FACT_Pos)
3758#define CAN_FA1R_FACT CAN_FA1R_FACT_Msk
3759#define CAN_FA1R_FACT0_Pos (0U)
3760#define CAN_FA1R_FACT0_Msk (0x1UL << CAN_FA1R_FACT0_Pos)
3761#define CAN_FA1R_FACT0 CAN_FA1R_FACT0_Msk
3762#define CAN_FA1R_FACT1_Pos (1U)
3763#define CAN_FA1R_FACT1_Msk (0x1UL << CAN_FA1R_FACT1_Pos)
3764#define CAN_FA1R_FACT1 CAN_FA1R_FACT1_Msk
3765#define CAN_FA1R_FACT2_Pos (2U)
3766#define CAN_FA1R_FACT2_Msk (0x1UL << CAN_FA1R_FACT2_Pos)
3767#define CAN_FA1R_FACT2 CAN_FA1R_FACT2_Msk
3768#define CAN_FA1R_FACT3_Pos (3U)
3769#define CAN_FA1R_FACT3_Msk (0x1UL << CAN_FA1R_FACT3_Pos)
3770#define CAN_FA1R_FACT3 CAN_FA1R_FACT3_Msk
3771#define CAN_FA1R_FACT4_Pos (4U)
3772#define CAN_FA1R_FACT4_Msk (0x1UL << CAN_FA1R_FACT4_Pos)
3773#define CAN_FA1R_FACT4 CAN_FA1R_FACT4_Msk
3774#define CAN_FA1R_FACT5_Pos (5U)
3775#define CAN_FA1R_FACT5_Msk (0x1UL << CAN_FA1R_FACT5_Pos)
3776#define CAN_FA1R_FACT5 CAN_FA1R_FACT5_Msk
3777#define CAN_FA1R_FACT6_Pos (6U)
3778#define CAN_FA1R_FACT6_Msk (0x1UL << CAN_FA1R_FACT6_Pos)
3779#define CAN_FA1R_FACT6 CAN_FA1R_FACT6_Msk
3780#define CAN_FA1R_FACT7_Pos (7U)
3781#define CAN_FA1R_FACT7_Msk (0x1UL << CAN_FA1R_FACT7_Pos)
3782#define CAN_FA1R_FACT7 CAN_FA1R_FACT7_Msk
3783#define CAN_FA1R_FACT8_Pos (8U)
3784#define CAN_FA1R_FACT8_Msk (0x1UL << CAN_FA1R_FACT8_Pos)
3785#define CAN_FA1R_FACT8 CAN_FA1R_FACT8_Msk
3786#define CAN_FA1R_FACT9_Pos (9U)
3787#define CAN_FA1R_FACT9_Msk (0x1UL << CAN_FA1R_FACT9_Pos)
3788#define CAN_FA1R_FACT9 CAN_FA1R_FACT9_Msk
3789#define CAN_FA1R_FACT10_Pos (10U)
3790#define CAN_FA1R_FACT10_Msk (0x1UL << CAN_FA1R_FACT10_Pos)
3791#define CAN_FA1R_FACT10 CAN_FA1R_FACT10_Msk
3792#define CAN_FA1R_FACT11_Pos (11U)
3793#define CAN_FA1R_FACT11_Msk (0x1UL << CAN_FA1R_FACT11_Pos)
3794#define CAN_FA1R_FACT11 CAN_FA1R_FACT11_Msk
3795#define CAN_FA1R_FACT12_Pos (12U)
3796#define CAN_FA1R_FACT12_Msk (0x1UL << CAN_FA1R_FACT12_Pos)
3797#define CAN_FA1R_FACT12 CAN_FA1R_FACT12_Msk
3798#define CAN_FA1R_FACT13_Pos (13U)
3799#define CAN_FA1R_FACT13_Msk (0x1UL << CAN_FA1R_FACT13_Pos)
3800#define CAN_FA1R_FACT13 CAN_FA1R_FACT13_Msk
3802/******************* Bit definition for CAN_F0R1 register *******************/
3803#define CAN_F0R1_FB0_Pos (0U)
3804#define CAN_F0R1_FB0_Msk (0x1UL << CAN_F0R1_FB0_Pos)
3805#define CAN_F0R1_FB0 CAN_F0R1_FB0_Msk
3806#define CAN_F0R1_FB1_Pos (1U)
3807#define CAN_F0R1_FB1_Msk (0x1UL << CAN_F0R1_FB1_Pos)
3808#define CAN_F0R1_FB1 CAN_F0R1_FB1_Msk
3809#define CAN_F0R1_FB2_Pos (2U)
3810#define CAN_F0R1_FB2_Msk (0x1UL << CAN_F0R1_FB2_Pos)
3811#define CAN_F0R1_FB2 CAN_F0R1_FB2_Msk
3812#define CAN_F0R1_FB3_Pos (3U)
3813#define CAN_F0R1_FB3_Msk (0x1UL << CAN_F0R1_FB3_Pos)
3814#define CAN_F0R1_FB3 CAN_F0R1_FB3_Msk
3815#define CAN_F0R1_FB4_Pos (4U)
3816#define CAN_F0R1_FB4_Msk (0x1UL << CAN_F0R1_FB4_Pos)
3817#define CAN_F0R1_FB4 CAN_F0R1_FB4_Msk
3818#define CAN_F0R1_FB5_Pos (5U)
3819#define CAN_F0R1_FB5_Msk (0x1UL << CAN_F0R1_FB5_Pos)
3820#define CAN_F0R1_FB5 CAN_F0R1_FB5_Msk
3821#define CAN_F0R1_FB6_Pos (6U)
3822#define CAN_F0R1_FB6_Msk (0x1UL << CAN_F0R1_FB6_Pos)
3823#define CAN_F0R1_FB6 CAN_F0R1_FB6_Msk
3824#define CAN_F0R1_FB7_Pos (7U)
3825#define CAN_F0R1_FB7_Msk (0x1UL << CAN_F0R1_FB7_Pos)
3826#define CAN_F0R1_FB7 CAN_F0R1_FB7_Msk
3827#define CAN_F0R1_FB8_Pos (8U)
3828#define CAN_F0R1_FB8_Msk (0x1UL << CAN_F0R1_FB8_Pos)
3829#define CAN_F0R1_FB8 CAN_F0R1_FB8_Msk
3830#define CAN_F0R1_FB9_Pos (9U)
3831#define CAN_F0R1_FB9_Msk (0x1UL << CAN_F0R1_FB9_Pos)
3832#define CAN_F0R1_FB9 CAN_F0R1_FB9_Msk
3833#define CAN_F0R1_FB10_Pos (10U)
3834#define CAN_F0R1_FB10_Msk (0x1UL << CAN_F0R1_FB10_Pos)
3835#define CAN_F0R1_FB10 CAN_F0R1_FB10_Msk
3836#define CAN_F0R1_FB11_Pos (11U)
3837#define CAN_F0R1_FB11_Msk (0x1UL << CAN_F0R1_FB11_Pos)
3838#define CAN_F0R1_FB11 CAN_F0R1_FB11_Msk
3839#define CAN_F0R1_FB12_Pos (12U)
3840#define CAN_F0R1_FB12_Msk (0x1UL << CAN_F0R1_FB12_Pos)
3841#define CAN_F0R1_FB12 CAN_F0R1_FB12_Msk
3842#define CAN_F0R1_FB13_Pos (13U)
3843#define CAN_F0R1_FB13_Msk (0x1UL << CAN_F0R1_FB13_Pos)
3844#define CAN_F0R1_FB13 CAN_F0R1_FB13_Msk
3845#define CAN_F0R1_FB14_Pos (14U)
3846#define CAN_F0R1_FB14_Msk (0x1UL << CAN_F0R1_FB14_Pos)
3847#define CAN_F0R1_FB14 CAN_F0R1_FB14_Msk
3848#define CAN_F0R1_FB15_Pos (15U)
3849#define CAN_F0R1_FB15_Msk (0x1UL << CAN_F0R1_FB15_Pos)
3850#define CAN_F0R1_FB15 CAN_F0R1_FB15_Msk
3851#define CAN_F0R1_FB16_Pos (16U)
3852#define CAN_F0R1_FB16_Msk (0x1UL << CAN_F0R1_FB16_Pos)
3853#define CAN_F0R1_FB16 CAN_F0R1_FB16_Msk
3854#define CAN_F0R1_FB17_Pos (17U)
3855#define CAN_F0R1_FB17_Msk (0x1UL << CAN_F0R1_FB17_Pos)
3856#define CAN_F0R1_FB17 CAN_F0R1_FB17_Msk
3857#define CAN_F0R1_FB18_Pos (18U)
3858#define CAN_F0R1_FB18_Msk (0x1UL << CAN_F0R1_FB18_Pos)
3859#define CAN_F0R1_FB18 CAN_F0R1_FB18_Msk
3860#define CAN_F0R1_FB19_Pos (19U)
3861#define CAN_F0R1_FB19_Msk (0x1UL << CAN_F0R1_FB19_Pos)
3862#define CAN_F0R1_FB19 CAN_F0R1_FB19_Msk
3863#define CAN_F0R1_FB20_Pos (20U)
3864#define CAN_F0R1_FB20_Msk (0x1UL << CAN_F0R1_FB20_Pos)
3865#define CAN_F0R1_FB20 CAN_F0R1_FB20_Msk
3866#define CAN_F0R1_FB21_Pos (21U)
3867#define CAN_F0R1_FB21_Msk (0x1UL << CAN_F0R1_FB21_Pos)
3868#define CAN_F0R1_FB21 CAN_F0R1_FB21_Msk
3869#define CAN_F0R1_FB22_Pos (22U)
3870#define CAN_F0R1_FB22_Msk (0x1UL << CAN_F0R1_FB22_Pos)
3871#define CAN_F0R1_FB22 CAN_F0R1_FB22_Msk
3872#define CAN_F0R1_FB23_Pos (23U)
3873#define CAN_F0R1_FB23_Msk (0x1UL << CAN_F0R1_FB23_Pos)
3874#define CAN_F0R1_FB23 CAN_F0R1_FB23_Msk
3875#define CAN_F0R1_FB24_Pos (24U)
3876#define CAN_F0R1_FB24_Msk (0x1UL << CAN_F0R1_FB24_Pos)
3877#define CAN_F0R1_FB24 CAN_F0R1_FB24_Msk
3878#define CAN_F0R1_FB25_Pos (25U)
3879#define CAN_F0R1_FB25_Msk (0x1UL << CAN_F0R1_FB25_Pos)
3880#define CAN_F0R1_FB25 CAN_F0R1_FB25_Msk
3881#define CAN_F0R1_FB26_Pos (26U)
3882#define CAN_F0R1_FB26_Msk (0x1UL << CAN_F0R1_FB26_Pos)
3883#define CAN_F0R1_FB26 CAN_F0R1_FB26_Msk
3884#define CAN_F0R1_FB27_Pos (27U)
3885#define CAN_F0R1_FB27_Msk (0x1UL << CAN_F0R1_FB27_Pos)
3886#define CAN_F0R1_FB27 CAN_F0R1_FB27_Msk
3887#define CAN_F0R1_FB28_Pos (28U)
3888#define CAN_F0R1_FB28_Msk (0x1UL << CAN_F0R1_FB28_Pos)
3889#define CAN_F0R1_FB28 CAN_F0R1_FB28_Msk
3890#define CAN_F0R1_FB29_Pos (29U)
3891#define CAN_F0R1_FB29_Msk (0x1UL << CAN_F0R1_FB29_Pos)
3892#define CAN_F0R1_FB29 CAN_F0R1_FB29_Msk
3893#define CAN_F0R1_FB30_Pos (30U)
3894#define CAN_F0R1_FB30_Msk (0x1UL << CAN_F0R1_FB30_Pos)
3895#define CAN_F0R1_FB30 CAN_F0R1_FB30_Msk
3896#define CAN_F0R1_FB31_Pos (31U)
3897#define CAN_F0R1_FB31_Msk (0x1UL << CAN_F0R1_FB31_Pos)
3898#define CAN_F0R1_FB31 CAN_F0R1_FB31_Msk
3900/******************* Bit definition for CAN_F1R1 register *******************/
3901#define CAN_F1R1_FB0_Pos (0U)
3902#define CAN_F1R1_FB0_Msk (0x1UL << CAN_F1R1_FB0_Pos)
3903#define CAN_F1R1_FB0 CAN_F1R1_FB0_Msk
3904#define CAN_F1R1_FB1_Pos (1U)
3905#define CAN_F1R1_FB1_Msk (0x1UL << CAN_F1R1_FB1_Pos)
3906#define CAN_F1R1_FB1 CAN_F1R1_FB1_Msk
3907#define CAN_F1R1_FB2_Pos (2U)
3908#define CAN_F1R1_FB2_Msk (0x1UL << CAN_F1R1_FB2_Pos)
3909#define CAN_F1R1_FB2 CAN_F1R1_FB2_Msk
3910#define CAN_F1R1_FB3_Pos (3U)
3911#define CAN_F1R1_FB3_Msk (0x1UL << CAN_F1R1_FB3_Pos)
3912#define CAN_F1R1_FB3 CAN_F1R1_FB3_Msk
3913#define CAN_F1R1_FB4_Pos (4U)
3914#define CAN_F1R1_FB4_Msk (0x1UL << CAN_F1R1_FB4_Pos)
3915#define CAN_F1R1_FB4 CAN_F1R1_FB4_Msk
3916#define CAN_F1R1_FB5_Pos (5U)
3917#define CAN_F1R1_FB5_Msk (0x1UL << CAN_F1R1_FB5_Pos)
3918#define CAN_F1R1_FB5 CAN_F1R1_FB5_Msk
3919#define CAN_F1R1_FB6_Pos (6U)
3920#define CAN_F1R1_FB6_Msk (0x1UL << CAN_F1R1_FB6_Pos)
3921#define CAN_F1R1_FB6 CAN_F1R1_FB6_Msk
3922#define CAN_F1R1_FB7_Pos (7U)
3923#define CAN_F1R1_FB7_Msk (0x1UL << CAN_F1R1_FB7_Pos)
3924#define CAN_F1R1_FB7 CAN_F1R1_FB7_Msk
3925#define CAN_F1R1_FB8_Pos (8U)
3926#define CAN_F1R1_FB8_Msk (0x1UL << CAN_F1R1_FB8_Pos)
3927#define CAN_F1R1_FB8 CAN_F1R1_FB8_Msk
3928#define CAN_F1R1_FB9_Pos (9U)
3929#define CAN_F1R1_FB9_Msk (0x1UL << CAN_F1R1_FB9_Pos)
3930#define CAN_F1R1_FB9 CAN_F1R1_FB9_Msk
3931#define CAN_F1R1_FB10_Pos (10U)
3932#define CAN_F1R1_FB10_Msk (0x1UL << CAN_F1R1_FB10_Pos)
3933#define CAN_F1R1_FB10 CAN_F1R1_FB10_Msk
3934#define CAN_F1R1_FB11_Pos (11U)
3935#define CAN_F1R1_FB11_Msk (0x1UL << CAN_F1R1_FB11_Pos)
3936#define CAN_F1R1_FB11 CAN_F1R1_FB11_Msk
3937#define CAN_F1R1_FB12_Pos (12U)
3938#define CAN_F1R1_FB12_Msk (0x1UL << CAN_F1R1_FB12_Pos)
3939#define CAN_F1R1_FB12 CAN_F1R1_FB12_Msk
3940#define CAN_F1R1_FB13_Pos (13U)
3941#define CAN_F1R1_FB13_Msk (0x1UL << CAN_F1R1_FB13_Pos)
3942#define CAN_F1R1_FB13 CAN_F1R1_FB13_Msk
3943#define CAN_F1R1_FB14_Pos (14U)
3944#define CAN_F1R1_FB14_Msk (0x1UL << CAN_F1R1_FB14_Pos)
3945#define CAN_F1R1_FB14 CAN_F1R1_FB14_Msk
3946#define CAN_F1R1_FB15_Pos (15U)
3947#define CAN_F1R1_FB15_Msk (0x1UL << CAN_F1R1_FB15_Pos)
3948#define CAN_F1R1_FB15 CAN_F1R1_FB15_Msk
3949#define CAN_F1R1_FB16_Pos (16U)
3950#define CAN_F1R1_FB16_Msk (0x1UL << CAN_F1R1_FB16_Pos)
3951#define CAN_F1R1_FB16 CAN_F1R1_FB16_Msk
3952#define CAN_F1R1_FB17_Pos (17U)
3953#define CAN_F1R1_FB17_Msk (0x1UL << CAN_F1R1_FB17_Pos)
3954#define CAN_F1R1_FB17 CAN_F1R1_FB17_Msk
3955#define CAN_F1R1_FB18_Pos (18U)
3956#define CAN_F1R1_FB18_Msk (0x1UL << CAN_F1R1_FB18_Pos)
3957#define CAN_F1R1_FB18 CAN_F1R1_FB18_Msk
3958#define CAN_F1R1_FB19_Pos (19U)
3959#define CAN_F1R1_FB19_Msk (0x1UL << CAN_F1R1_FB19_Pos)
3960#define CAN_F1R1_FB19 CAN_F1R1_FB19_Msk
3961#define CAN_F1R1_FB20_Pos (20U)
3962#define CAN_F1R1_FB20_Msk (0x1UL << CAN_F1R1_FB20_Pos)
3963#define CAN_F1R1_FB20 CAN_F1R1_FB20_Msk
3964#define CAN_F1R1_FB21_Pos (21U)
3965#define CAN_F1R1_FB21_Msk (0x1UL << CAN_F1R1_FB21_Pos)
3966#define CAN_F1R1_FB21 CAN_F1R1_FB21_Msk
3967#define CAN_F1R1_FB22_Pos (22U)
3968#define CAN_F1R1_FB22_Msk (0x1UL << CAN_F1R1_FB22_Pos)
3969#define CAN_F1R1_FB22 CAN_F1R1_FB22_Msk
3970#define CAN_F1R1_FB23_Pos (23U)
3971#define CAN_F1R1_FB23_Msk (0x1UL << CAN_F1R1_FB23_Pos)
3972#define CAN_F1R1_FB23 CAN_F1R1_FB23_Msk
3973#define CAN_F1R1_FB24_Pos (24U)
3974#define CAN_F1R1_FB24_Msk (0x1UL << CAN_F1R1_FB24_Pos)
3975#define CAN_F1R1_FB24 CAN_F1R1_FB24_Msk
3976#define CAN_F1R1_FB25_Pos (25U)
3977#define CAN_F1R1_FB25_Msk (0x1UL << CAN_F1R1_FB25_Pos)
3978#define CAN_F1R1_FB25 CAN_F1R1_FB25_Msk
3979#define CAN_F1R1_FB26_Pos (26U)
3980#define CAN_F1R1_FB26_Msk (0x1UL << CAN_F1R1_FB26_Pos)
3981#define CAN_F1R1_FB26 CAN_F1R1_FB26_Msk
3982#define CAN_F1R1_FB27_Pos (27U)
3983#define CAN_F1R1_FB27_Msk (0x1UL << CAN_F1R1_FB27_Pos)
3984#define CAN_F1R1_FB27 CAN_F1R1_FB27_Msk
3985#define CAN_F1R1_FB28_Pos (28U)
3986#define CAN_F1R1_FB28_Msk (0x1UL << CAN_F1R1_FB28_Pos)
3987#define CAN_F1R1_FB28 CAN_F1R1_FB28_Msk
3988#define CAN_F1R1_FB29_Pos (29U)
3989#define CAN_F1R1_FB29_Msk (0x1UL << CAN_F1R1_FB29_Pos)
3990#define CAN_F1R1_FB29 CAN_F1R1_FB29_Msk
3991#define CAN_F1R1_FB30_Pos (30U)
3992#define CAN_F1R1_FB30_Msk (0x1UL << CAN_F1R1_FB30_Pos)
3993#define CAN_F1R1_FB30 CAN_F1R1_FB30_Msk
3994#define CAN_F1R1_FB31_Pos (31U)
3995#define CAN_F1R1_FB31_Msk (0x1UL << CAN_F1R1_FB31_Pos)
3996#define CAN_F1R1_FB31 CAN_F1R1_FB31_Msk
3998/******************* Bit definition for CAN_F2R1 register *******************/
3999#define CAN_F2R1_FB0_Pos (0U)
4000#define CAN_F2R1_FB0_Msk (0x1UL << CAN_F2R1_FB0_Pos)
4001#define CAN_F2R1_FB0 CAN_F2R1_FB0_Msk
4002#define CAN_F2R1_FB1_Pos (1U)
4003#define CAN_F2R1_FB1_Msk (0x1UL << CAN_F2R1_FB1_Pos)
4004#define CAN_F2R1_FB1 CAN_F2R1_FB1_Msk
4005#define CAN_F2R1_FB2_Pos (2U)
4006#define CAN_F2R1_FB2_Msk (0x1UL << CAN_F2R1_FB2_Pos)
4007#define CAN_F2R1_FB2 CAN_F2R1_FB2_Msk
4008#define CAN_F2R1_FB3_Pos (3U)
4009#define CAN_F2R1_FB3_Msk (0x1UL << CAN_F2R1_FB3_Pos)
4010#define CAN_F2R1_FB3 CAN_F2R1_FB3_Msk
4011#define CAN_F2R1_FB4_Pos (4U)
4012#define CAN_F2R1_FB4_Msk (0x1UL << CAN_F2R1_FB4_Pos)
4013#define CAN_F2R1_FB4 CAN_F2R1_FB4_Msk
4014#define CAN_F2R1_FB5_Pos (5U)
4015#define CAN_F2R1_FB5_Msk (0x1UL << CAN_F2R1_FB5_Pos)
4016#define CAN_F2R1_FB5 CAN_F2R1_FB5_Msk
4017#define CAN_F2R1_FB6_Pos (6U)
4018#define CAN_F2R1_FB6_Msk (0x1UL << CAN_F2R1_FB6_Pos)
4019#define CAN_F2R1_FB6 CAN_F2R1_FB6_Msk
4020#define CAN_F2R1_FB7_Pos (7U)
4021#define CAN_F2R1_FB7_Msk (0x1UL << CAN_F2R1_FB7_Pos)
4022#define CAN_F2R1_FB7 CAN_F2R1_FB7_Msk
4023#define CAN_F2R1_FB8_Pos (8U)
4024#define CAN_F2R1_FB8_Msk (0x1UL << CAN_F2R1_FB8_Pos)
4025#define CAN_F2R1_FB8 CAN_F2R1_FB8_Msk
4026#define CAN_F2R1_FB9_Pos (9U)
4027#define CAN_F2R1_FB9_Msk (0x1UL << CAN_F2R1_FB9_Pos)
4028#define CAN_F2R1_FB9 CAN_F2R1_FB9_Msk
4029#define CAN_F2R1_FB10_Pos (10U)
4030#define CAN_F2R1_FB10_Msk (0x1UL << CAN_F2R1_FB10_Pos)
4031#define CAN_F2R1_FB10 CAN_F2R1_FB10_Msk
4032#define CAN_F2R1_FB11_Pos (11U)
4033#define CAN_F2R1_FB11_Msk (0x1UL << CAN_F2R1_FB11_Pos)
4034#define CAN_F2R1_FB11 CAN_F2R1_FB11_Msk
4035#define CAN_F2R1_FB12_Pos (12U)
4036#define CAN_F2R1_FB12_Msk (0x1UL << CAN_F2R1_FB12_Pos)
4037#define CAN_F2R1_FB12 CAN_F2R1_FB12_Msk
4038#define CAN_F2R1_FB13_Pos (13U)
4039#define CAN_F2R1_FB13_Msk (0x1UL << CAN_F2R1_FB13_Pos)
4040#define CAN_F2R1_FB13 CAN_F2R1_FB13_Msk
4041#define CAN_F2R1_FB14_Pos (14U)
4042#define CAN_F2R1_FB14_Msk (0x1UL << CAN_F2R1_FB14_Pos)
4043#define CAN_F2R1_FB14 CAN_F2R1_FB14_Msk
4044#define CAN_F2R1_FB15_Pos (15U)
4045#define CAN_F2R1_FB15_Msk (0x1UL << CAN_F2R1_FB15_Pos)
4046#define CAN_F2R1_FB15 CAN_F2R1_FB15_Msk
4047#define CAN_F2R1_FB16_Pos (16U)
4048#define CAN_F2R1_FB16_Msk (0x1UL << CAN_F2R1_FB16_Pos)
4049#define CAN_F2R1_FB16 CAN_F2R1_FB16_Msk
4050#define CAN_F2R1_FB17_Pos (17U)
4051#define CAN_F2R1_FB17_Msk (0x1UL << CAN_F2R1_FB17_Pos)
4052#define CAN_F2R1_FB17 CAN_F2R1_FB17_Msk
4053#define CAN_F2R1_FB18_Pos (18U)
4054#define CAN_F2R1_FB18_Msk (0x1UL << CAN_F2R1_FB18_Pos)
4055#define CAN_F2R1_FB18 CAN_F2R1_FB18_Msk
4056#define CAN_F2R1_FB19_Pos (19U)
4057#define CAN_F2R1_FB19_Msk (0x1UL << CAN_F2R1_FB19_Pos)
4058#define CAN_F2R1_FB19 CAN_F2R1_FB19_Msk
4059#define CAN_F2R1_FB20_Pos (20U)
4060#define CAN_F2R1_FB20_Msk (0x1UL << CAN_F2R1_FB20_Pos)
4061#define CAN_F2R1_FB20 CAN_F2R1_FB20_Msk
4062#define CAN_F2R1_FB21_Pos (21U)
4063#define CAN_F2R1_FB21_Msk (0x1UL << CAN_F2R1_FB21_Pos)
4064#define CAN_F2R1_FB21 CAN_F2R1_FB21_Msk
4065#define CAN_F2R1_FB22_Pos (22U)
4066#define CAN_F2R1_FB22_Msk (0x1UL << CAN_F2R1_FB22_Pos)
4067#define CAN_F2R1_FB22 CAN_F2R1_FB22_Msk
4068#define CAN_F2R1_FB23_Pos (23U)
4069#define CAN_F2R1_FB23_Msk (0x1UL << CAN_F2R1_FB23_Pos)
4070#define CAN_F2R1_FB23 CAN_F2R1_FB23_Msk
4071#define CAN_F2R1_FB24_Pos (24U)
4072#define CAN_F2R1_FB24_Msk (0x1UL << CAN_F2R1_FB24_Pos)
4073#define CAN_F2R1_FB24 CAN_F2R1_FB24_Msk
4074#define CAN_F2R1_FB25_Pos (25U)
4075#define CAN_F2R1_FB25_Msk (0x1UL << CAN_F2R1_FB25_Pos)
4076#define CAN_F2R1_FB25 CAN_F2R1_FB25_Msk
4077#define CAN_F2R1_FB26_Pos (26U)
4078#define CAN_F2R1_FB26_Msk (0x1UL << CAN_F2R1_FB26_Pos)
4079#define CAN_F2R1_FB26 CAN_F2R1_FB26_Msk
4080#define CAN_F2R1_FB27_Pos (27U)
4081#define CAN_F2R1_FB27_Msk (0x1UL << CAN_F2R1_FB27_Pos)
4082#define CAN_F2R1_FB27 CAN_F2R1_FB27_Msk
4083#define CAN_F2R1_FB28_Pos (28U)
4084#define CAN_F2R1_FB28_Msk (0x1UL << CAN_F2R1_FB28_Pos)
4085#define CAN_F2R1_FB28 CAN_F2R1_FB28_Msk
4086#define CAN_F2R1_FB29_Pos (29U)
4087#define CAN_F2R1_FB29_Msk (0x1UL << CAN_F2R1_FB29_Pos)
4088#define CAN_F2R1_FB29 CAN_F2R1_FB29_Msk
4089#define CAN_F2R1_FB30_Pos (30U)
4090#define CAN_F2R1_FB30_Msk (0x1UL << CAN_F2R1_FB30_Pos)
4091#define CAN_F2R1_FB30 CAN_F2R1_FB30_Msk
4092#define CAN_F2R1_FB31_Pos (31U)
4093#define CAN_F2R1_FB31_Msk (0x1UL << CAN_F2R1_FB31_Pos)
4094#define CAN_F2R1_FB31 CAN_F2R1_FB31_Msk
4096/******************* Bit definition for CAN_F3R1 register *******************/
4097#define CAN_F3R1_FB0_Pos (0U)
4098#define CAN_F3R1_FB0_Msk (0x1UL << CAN_F3R1_FB0_Pos)
4099#define CAN_F3R1_FB0 CAN_F3R1_FB0_Msk
4100#define CAN_F3R1_FB1_Pos (1U)
4101#define CAN_F3R1_FB1_Msk (0x1UL << CAN_F3R1_FB1_Pos)
4102#define CAN_F3R1_FB1 CAN_F3R1_FB1_Msk
4103#define CAN_F3R1_FB2_Pos (2U)
4104#define CAN_F3R1_FB2_Msk (0x1UL << CAN_F3R1_FB2_Pos)
4105#define CAN_F3R1_FB2 CAN_F3R1_FB2_Msk
4106#define CAN_F3R1_FB3_Pos (3U)
4107#define CAN_F3R1_FB3_Msk (0x1UL << CAN_F3R1_FB3_Pos)
4108#define CAN_F3R1_FB3 CAN_F3R1_FB3_Msk
4109#define CAN_F3R1_FB4_Pos (4U)
4110#define CAN_F3R1_FB4_Msk (0x1UL << CAN_F3R1_FB4_Pos)
4111#define CAN_F3R1_FB4 CAN_F3R1_FB4_Msk
4112#define CAN_F3R1_FB5_Pos (5U)
4113#define CAN_F3R1_FB5_Msk (0x1UL << CAN_F3R1_FB5_Pos)
4114#define CAN_F3R1_FB5 CAN_F3R1_FB5_Msk
4115#define CAN_F3R1_FB6_Pos (6U)
4116#define CAN_F3R1_FB6_Msk (0x1UL << CAN_F3R1_FB6_Pos)
4117#define CAN_F3R1_FB6 CAN_F3R1_FB6_Msk
4118#define CAN_F3R1_FB7_Pos (7U)
4119#define CAN_F3R1_FB7_Msk (0x1UL << CAN_F3R1_FB7_Pos)
4120#define CAN_F3R1_FB7 CAN_F3R1_FB7_Msk
4121#define CAN_F3R1_FB8_Pos (8U)
4122#define CAN_F3R1_FB8_Msk (0x1UL << CAN_F3R1_FB8_Pos)
4123#define CAN_F3R1_FB8 CAN_F3R1_FB8_Msk
4124#define CAN_F3R1_FB9_Pos (9U)
4125#define CAN_F3R1_FB9_Msk (0x1UL << CAN_F3R1_FB9_Pos)
4126#define CAN_F3R1_FB9 CAN_F3R1_FB9_Msk
4127#define CAN_F3R1_FB10_Pos (10U)
4128#define CAN_F3R1_FB10_Msk (0x1UL << CAN_F3R1_FB10_Pos)
4129#define CAN_F3R1_FB10 CAN_F3R1_FB10_Msk
4130#define CAN_F3R1_FB11_Pos (11U)
4131#define CAN_F3R1_FB11_Msk (0x1UL << CAN_F3R1_FB11_Pos)
4132#define CAN_F3R1_FB11 CAN_F3R1_FB11_Msk
4133#define CAN_F3R1_FB12_Pos (12U)
4134#define CAN_F3R1_FB12_Msk (0x1UL << CAN_F3R1_FB12_Pos)
4135#define CAN_F3R1_FB12 CAN_F3R1_FB12_Msk
4136#define CAN_F3R1_FB13_Pos (13U)
4137#define CAN_F3R1_FB13_Msk (0x1UL << CAN_F3R1_FB13_Pos)
4138#define CAN_F3R1_FB13 CAN_F3R1_FB13_Msk
4139#define CAN_F3R1_FB14_Pos (14U)
4140#define CAN_F3R1_FB14_Msk (0x1UL << CAN_F3R1_FB14_Pos)
4141#define CAN_F3R1_FB14 CAN_F3R1_FB14_Msk
4142#define CAN_F3R1_FB15_Pos (15U)
4143#define CAN_F3R1_FB15_Msk (0x1UL << CAN_F3R1_FB15_Pos)
4144#define CAN_F3R1_FB15 CAN_F3R1_FB15_Msk
4145#define CAN_F3R1_FB16_Pos (16U)
4146#define CAN_F3R1_FB16_Msk (0x1UL << CAN_F3R1_FB16_Pos)
4147#define CAN_F3R1_FB16 CAN_F3R1_FB16_Msk
4148#define CAN_F3R1_FB17_Pos (17U)
4149#define CAN_F3R1_FB17_Msk (0x1UL << CAN_F3R1_FB17_Pos)
4150#define CAN_F3R1_FB17 CAN_F3R1_FB17_Msk
4151#define CAN_F3R1_FB18_Pos (18U)
4152#define CAN_F3R1_FB18_Msk (0x1UL << CAN_F3R1_FB18_Pos)
4153#define CAN_F3R1_FB18 CAN_F3R1_FB18_Msk
4154#define CAN_F3R1_FB19_Pos (19U)
4155#define CAN_F3R1_FB19_Msk (0x1UL << CAN_F3R1_FB19_Pos)
4156#define CAN_F3R1_FB19 CAN_F3R1_FB19_Msk
4157#define CAN_F3R1_FB20_Pos (20U)
4158#define CAN_F3R1_FB20_Msk (0x1UL << CAN_F3R1_FB20_Pos)
4159#define CAN_F3R1_FB20 CAN_F3R1_FB20_Msk
4160#define CAN_F3R1_FB21_Pos (21U)
4161#define CAN_F3R1_FB21_Msk (0x1UL << CAN_F3R1_FB21_Pos)
4162#define CAN_F3R1_FB21 CAN_F3R1_FB21_Msk
4163#define CAN_F3R1_FB22_Pos (22U)
4164#define CAN_F3R1_FB22_Msk (0x1UL << CAN_F3R1_FB22_Pos)
4165#define CAN_F3R1_FB22 CAN_F3R1_FB22_Msk
4166#define CAN_F3R1_FB23_Pos (23U)
4167#define CAN_F3R1_FB23_Msk (0x1UL << CAN_F3R1_FB23_Pos)
4168#define CAN_F3R1_FB23 CAN_F3R1_FB23_Msk
4169#define CAN_F3R1_FB24_Pos (24U)
4170#define CAN_F3R1_FB24_Msk (0x1UL << CAN_F3R1_FB24_Pos)
4171#define CAN_F3R1_FB24 CAN_F3R1_FB24_Msk
4172#define CAN_F3R1_FB25_Pos (25U)
4173#define CAN_F3R1_FB25_Msk (0x1UL << CAN_F3R1_FB25_Pos)
4174#define CAN_F3R1_FB25 CAN_F3R1_FB25_Msk
4175#define CAN_F3R1_FB26_Pos (26U)
4176#define CAN_F3R1_FB26_Msk (0x1UL << CAN_F3R1_FB26_Pos)
4177#define CAN_F3R1_FB26 CAN_F3R1_FB26_Msk
4178#define CAN_F3R1_FB27_Pos (27U)
4179#define CAN_F3R1_FB27_Msk (0x1UL << CAN_F3R1_FB27_Pos)
4180#define CAN_F3R1_FB27 CAN_F3R1_FB27_Msk
4181#define CAN_F3R1_FB28_Pos (28U)
4182#define CAN_F3R1_FB28_Msk (0x1UL << CAN_F3R1_FB28_Pos)
4183#define CAN_F3R1_FB28 CAN_F3R1_FB28_Msk
4184#define CAN_F3R1_FB29_Pos (29U)
4185#define CAN_F3R1_FB29_Msk (0x1UL << CAN_F3R1_FB29_Pos)
4186#define CAN_F3R1_FB29 CAN_F3R1_FB29_Msk
4187#define CAN_F3R1_FB30_Pos (30U)
4188#define CAN_F3R1_FB30_Msk (0x1UL << CAN_F3R1_FB30_Pos)
4189#define CAN_F3R1_FB30 CAN_F3R1_FB30_Msk
4190#define CAN_F3R1_FB31_Pos (31U)
4191#define CAN_F3R1_FB31_Msk (0x1UL << CAN_F3R1_FB31_Pos)
4192#define CAN_F3R1_FB31 CAN_F3R1_FB31_Msk
4194/******************* Bit definition for CAN_F4R1 register *******************/
4195#define CAN_F4R1_FB0_Pos (0U)
4196#define CAN_F4R1_FB0_Msk (0x1UL << CAN_F4R1_FB0_Pos)
4197#define CAN_F4R1_FB0 CAN_F4R1_FB0_Msk
4198#define CAN_F4R1_FB1_Pos (1U)
4199#define CAN_F4R1_FB1_Msk (0x1UL << CAN_F4R1_FB1_Pos)
4200#define CAN_F4R1_FB1 CAN_F4R1_FB1_Msk
4201#define CAN_F4R1_FB2_Pos (2U)
4202#define CAN_F4R1_FB2_Msk (0x1UL << CAN_F4R1_FB2_Pos)
4203#define CAN_F4R1_FB2 CAN_F4R1_FB2_Msk
4204#define CAN_F4R1_FB3_Pos (3U)
4205#define CAN_F4R1_FB3_Msk (0x1UL << CAN_F4R1_FB3_Pos)
4206#define CAN_F4R1_FB3 CAN_F4R1_FB3_Msk
4207#define CAN_F4R1_FB4_Pos (4U)
4208#define CAN_F4R1_FB4_Msk (0x1UL << CAN_F4R1_FB4_Pos)
4209#define CAN_F4R1_FB4 CAN_F4R1_FB4_Msk
4210#define CAN_F4R1_FB5_Pos (5U)
4211#define CAN_F4R1_FB5_Msk (0x1UL << CAN_F4R1_FB5_Pos)
4212#define CAN_F4R1_FB5 CAN_F4R1_FB5_Msk
4213#define CAN_F4R1_FB6_Pos (6U)
4214#define CAN_F4R1_FB6_Msk (0x1UL << CAN_F4R1_FB6_Pos)
4215#define CAN_F4R1_FB6 CAN_F4R1_FB6_Msk
4216#define CAN_F4R1_FB7_Pos (7U)
4217#define CAN_F4R1_FB7_Msk (0x1UL << CAN_F4R1_FB7_Pos)
4218#define CAN_F4R1_FB7 CAN_F4R1_FB7_Msk
4219#define CAN_F4R1_FB8_Pos (8U)
4220#define CAN_F4R1_FB8_Msk (0x1UL << CAN_F4R1_FB8_Pos)
4221#define CAN_F4R1_FB8 CAN_F4R1_FB8_Msk
4222#define CAN_F4R1_FB9_Pos (9U)
4223#define CAN_F4R1_FB9_Msk (0x1UL << CAN_F4R1_FB9_Pos)
4224#define CAN_F4R1_FB9 CAN_F4R1_FB9_Msk
4225#define CAN_F4R1_FB10_Pos (10U)
4226#define CAN_F4R1_FB10_Msk (0x1UL << CAN_F4R1_FB10_Pos)
4227#define CAN_F4R1_FB10 CAN_F4R1_FB10_Msk
4228#define CAN_F4R1_FB11_Pos (11U)
4229#define CAN_F4R1_FB11_Msk (0x1UL << CAN_F4R1_FB11_Pos)
4230#define CAN_F4R1_FB11 CAN_F4R1_FB11_Msk
4231#define CAN_F4R1_FB12_Pos (12U)
4232#define CAN_F4R1_FB12_Msk (0x1UL << CAN_F4R1_FB12_Pos)
4233#define CAN_F4R1_FB12 CAN_F4R1_FB12_Msk
4234#define CAN_F4R1_FB13_Pos (13U)
4235#define CAN_F4R1_FB13_Msk (0x1UL << CAN_F4R1_FB13_Pos)
4236#define CAN_F4R1_FB13 CAN_F4R1_FB13_Msk
4237#define CAN_F4R1_FB14_Pos (14U)
4238#define CAN_F4R1_FB14_Msk (0x1UL << CAN_F4R1_FB14_Pos)
4239#define CAN_F4R1_FB14 CAN_F4R1_FB14_Msk
4240#define CAN_F4R1_FB15_Pos (15U)
4241#define CAN_F4R1_FB15_Msk (0x1UL << CAN_F4R1_FB15_Pos)
4242#define CAN_F4R1_FB15 CAN_F4R1_FB15_Msk
4243#define CAN_F4R1_FB16_Pos (16U)
4244#define CAN_F4R1_FB16_Msk (0x1UL << CAN_F4R1_FB16_Pos)
4245#define CAN_F4R1_FB16 CAN_F4R1_FB16_Msk
4246#define CAN_F4R1_FB17_Pos (17U)
4247#define CAN_F4R1_FB17_Msk (0x1UL << CAN_F4R1_FB17_Pos)
4248#define CAN_F4R1_FB17 CAN_F4R1_FB17_Msk
4249#define CAN_F4R1_FB18_Pos (18U)
4250#define CAN_F4R1_FB18_Msk (0x1UL << CAN_F4R1_FB18_Pos)
4251#define CAN_F4R1_FB18 CAN_F4R1_FB18_Msk
4252#define CAN_F4R1_FB19_Pos (19U)
4253#define CAN_F4R1_FB19_Msk (0x1UL << CAN_F4R1_FB19_Pos)
4254#define CAN_F4R1_FB19 CAN_F4R1_FB19_Msk
4255#define CAN_F4R1_FB20_Pos (20U)
4256#define CAN_F4R1_FB20_Msk (0x1UL << CAN_F4R1_FB20_Pos)
4257#define CAN_F4R1_FB20 CAN_F4R1_FB20_Msk
4258#define CAN_F4R1_FB21_Pos (21U)
4259#define CAN_F4R1_FB21_Msk (0x1UL << CAN_F4R1_FB21_Pos)
4260#define CAN_F4R1_FB21 CAN_F4R1_FB21_Msk
4261#define CAN_F4R1_FB22_Pos (22U)
4262#define CAN_F4R1_FB22_Msk (0x1UL << CAN_F4R1_FB22_Pos)
4263#define CAN_F4R1_FB22 CAN_F4R1_FB22_Msk
4264#define CAN_F4R1_FB23_Pos (23U)
4265#define CAN_F4R1_FB23_Msk (0x1UL << CAN_F4R1_FB23_Pos)
4266#define CAN_F4R1_FB23 CAN_F4R1_FB23_Msk
4267#define CAN_F4R1_FB24_Pos (24U)
4268#define CAN_F4R1_FB24_Msk (0x1UL << CAN_F4R1_FB24_Pos)
4269#define CAN_F4R1_FB24 CAN_F4R1_FB24_Msk
4270#define CAN_F4R1_FB25_Pos (25U)
4271#define CAN_F4R1_FB25_Msk (0x1UL << CAN_F4R1_FB25_Pos)
4272#define CAN_F4R1_FB25 CAN_F4R1_FB25_Msk
4273#define CAN_F4R1_FB26_Pos (26U)
4274#define CAN_F4R1_FB26_Msk (0x1UL << CAN_F4R1_FB26_Pos)
4275#define CAN_F4R1_FB26 CAN_F4R1_FB26_Msk
4276#define CAN_F4R1_FB27_Pos (27U)
4277#define CAN_F4R1_FB27_Msk (0x1UL << CAN_F4R1_FB27_Pos)
4278#define CAN_F4R1_FB27 CAN_F4R1_FB27_Msk
4279#define CAN_F4R1_FB28_Pos (28U)
4280#define CAN_F4R1_FB28_Msk (0x1UL << CAN_F4R1_FB28_Pos)
4281#define CAN_F4R1_FB28 CAN_F4R1_FB28_Msk
4282#define CAN_F4R1_FB29_Pos (29U)
4283#define CAN_F4R1_FB29_Msk (0x1UL << CAN_F4R1_FB29_Pos)
4284#define CAN_F4R1_FB29 CAN_F4R1_FB29_Msk
4285#define CAN_F4R1_FB30_Pos (30U)
4286#define CAN_F4R1_FB30_Msk (0x1UL << CAN_F4R1_FB30_Pos)
4287#define CAN_F4R1_FB30 CAN_F4R1_FB30_Msk
4288#define CAN_F4R1_FB31_Pos (31U)
4289#define CAN_F4R1_FB31_Msk (0x1UL << CAN_F4R1_FB31_Pos)
4290#define CAN_F4R1_FB31 CAN_F4R1_FB31_Msk
4292/******************* Bit definition for CAN_F5R1 register *******************/
4293#define CAN_F5R1_FB0_Pos (0U)
4294#define CAN_F5R1_FB0_Msk (0x1UL << CAN_F5R1_FB0_Pos)
4295#define CAN_F5R1_FB0 CAN_F5R1_FB0_Msk
4296#define CAN_F5R1_FB1_Pos (1U)
4297#define CAN_F5R1_FB1_Msk (0x1UL << CAN_F5R1_FB1_Pos)
4298#define CAN_F5R1_FB1 CAN_F5R1_FB1_Msk
4299#define CAN_F5R1_FB2_Pos (2U)
4300#define CAN_F5R1_FB2_Msk (0x1UL << CAN_F5R1_FB2_Pos)
4301#define CAN_F5R1_FB2 CAN_F5R1_FB2_Msk
4302#define CAN_F5R1_FB3_Pos (3U)
4303#define CAN_F5R1_FB3_Msk (0x1UL << CAN_F5R1_FB3_Pos)
4304#define CAN_F5R1_FB3 CAN_F5R1_FB3_Msk
4305#define CAN_F5R1_FB4_Pos (4U)
4306#define CAN_F5R1_FB4_Msk (0x1UL << CAN_F5R1_FB4_Pos)
4307#define CAN_F5R1_FB4 CAN_F5R1_FB4_Msk
4308#define CAN_F5R1_FB5_Pos (5U)
4309#define CAN_F5R1_FB5_Msk (0x1UL << CAN_F5R1_FB5_Pos)
4310#define CAN_F5R1_FB5 CAN_F5R1_FB5_Msk
4311#define CAN_F5R1_FB6_Pos (6U)
4312#define CAN_F5R1_FB6_Msk (0x1UL << CAN_F5R1_FB6_Pos)
4313#define CAN_F5R1_FB6 CAN_F5R1_FB6_Msk
4314#define CAN_F5R1_FB7_Pos (7U)
4315#define CAN_F5R1_FB7_Msk (0x1UL << CAN_F5R1_FB7_Pos)
4316#define CAN_F5R1_FB7 CAN_F5R1_FB7_Msk
4317#define CAN_F5R1_FB8_Pos (8U)
4318#define CAN_F5R1_FB8_Msk (0x1UL << CAN_F5R1_FB8_Pos)
4319#define CAN_F5R1_FB8 CAN_F5R1_FB8_Msk
4320#define CAN_F5R1_FB9_Pos (9U)
4321#define CAN_F5R1_FB9_Msk (0x1UL << CAN_F5R1_FB9_Pos)
4322#define CAN_F5R1_FB9 CAN_F5R1_FB9_Msk
4323#define CAN_F5R1_FB10_Pos (10U)
4324#define CAN_F5R1_FB10_Msk (0x1UL << CAN_F5R1_FB10_Pos)
4325#define CAN_F5R1_FB10 CAN_F5R1_FB10_Msk
4326#define CAN_F5R1_FB11_Pos (11U)
4327#define CAN_F5R1_FB11_Msk (0x1UL << CAN_F5R1_FB11_Pos)
4328#define CAN_F5R1_FB11 CAN_F5R1_FB11_Msk
4329#define CAN_F5R1_FB12_Pos (12U)
4330#define CAN_F5R1_FB12_Msk (0x1UL << CAN_F5R1_FB12_Pos)
4331#define CAN_F5R1_FB12 CAN_F5R1_FB12_Msk
4332#define CAN_F5R1_FB13_Pos (13U)
4333#define CAN_F5R1_FB13_Msk (0x1UL << CAN_F5R1_FB13_Pos)
4334#define CAN_F5R1_FB13 CAN_F5R1_FB13_Msk
4335#define CAN_F5R1_FB14_Pos (14U)
4336#define CAN_F5R1_FB14_Msk (0x1UL << CAN_F5R1_FB14_Pos)
4337#define CAN_F5R1_FB14 CAN_F5R1_FB14_Msk
4338#define CAN_F5R1_FB15_Pos (15U)
4339#define CAN_F5R1_FB15_Msk (0x1UL << CAN_F5R1_FB15_Pos)
4340#define CAN_F5R1_FB15 CAN_F5R1_FB15_Msk
4341#define CAN_F5R1_FB16_Pos (16U)
4342#define CAN_F5R1_FB16_Msk (0x1UL << CAN_F5R1_FB16_Pos)
4343#define CAN_F5R1_FB16 CAN_F5R1_FB16_Msk
4344#define CAN_F5R1_FB17_Pos (17U)
4345#define CAN_F5R1_FB17_Msk (0x1UL << CAN_F5R1_FB17_Pos)
4346#define CAN_F5R1_FB17 CAN_F5R1_FB17_Msk
4347#define CAN_F5R1_FB18_Pos (18U)
4348#define CAN_F5R1_FB18_Msk (0x1UL << CAN_F5R1_FB18_Pos)
4349#define CAN_F5R1_FB18 CAN_F5R1_FB18_Msk
4350#define CAN_F5R1_FB19_Pos (19U)
4351#define CAN_F5R1_FB19_Msk (0x1UL << CAN_F5R1_FB19_Pos)
4352#define CAN_F5R1_FB19 CAN_F5R1_FB19_Msk
4353#define CAN_F5R1_FB20_Pos (20U)
4354#define CAN_F5R1_FB20_Msk (0x1UL << CAN_F5R1_FB20_Pos)
4355#define CAN_F5R1_FB20 CAN_F5R1_FB20_Msk
4356#define CAN_F5R1_FB21_Pos (21U)
4357#define CAN_F5R1_FB21_Msk (0x1UL << CAN_F5R1_FB21_Pos)
4358#define CAN_F5R1_FB21 CAN_F5R1_FB21_Msk
4359#define CAN_F5R1_FB22_Pos (22U)
4360#define CAN_F5R1_FB22_Msk (0x1UL << CAN_F5R1_FB22_Pos)
4361#define CAN_F5R1_FB22 CAN_F5R1_FB22_Msk
4362#define CAN_F5R1_FB23_Pos (23U)
4363#define CAN_F5R1_FB23_Msk (0x1UL << CAN_F5R1_FB23_Pos)
4364#define CAN_F5R1_FB23 CAN_F5R1_FB23_Msk
4365#define CAN_F5R1_FB24_Pos (24U)
4366#define CAN_F5R1_FB24_Msk (0x1UL << CAN_F5R1_FB24_Pos)
4367#define CAN_F5R1_FB24 CAN_F5R1_FB24_Msk
4368#define CAN_F5R1_FB25_Pos (25U)
4369#define CAN_F5R1_FB25_Msk (0x1UL << CAN_F5R1_FB25_Pos)
4370#define CAN_F5R1_FB25 CAN_F5R1_FB25_Msk
4371#define CAN_F5R1_FB26_Pos (26U)
4372#define CAN_F5R1_FB26_Msk (0x1UL << CAN_F5R1_FB26_Pos)
4373#define CAN_F5R1_FB26 CAN_F5R1_FB26_Msk
4374#define CAN_F5R1_FB27_Pos (27U)
4375#define CAN_F5R1_FB27_Msk (0x1UL << CAN_F5R1_FB27_Pos)
4376#define CAN_F5R1_FB27 CAN_F5R1_FB27_Msk
4377#define CAN_F5R1_FB28_Pos (28U)
4378#define CAN_F5R1_FB28_Msk (0x1UL << CAN_F5R1_FB28_Pos)
4379#define CAN_F5R1_FB28 CAN_F5R1_FB28_Msk
4380#define CAN_F5R1_FB29_Pos (29U)
4381#define CAN_F5R1_FB29_Msk (0x1UL << CAN_F5R1_FB29_Pos)
4382#define CAN_F5R1_FB29 CAN_F5R1_FB29_Msk
4383#define CAN_F5R1_FB30_Pos (30U)
4384#define CAN_F5R1_FB30_Msk (0x1UL << CAN_F5R1_FB30_Pos)
4385#define CAN_F5R1_FB30 CAN_F5R1_FB30_Msk
4386#define CAN_F5R1_FB31_Pos (31U)
4387#define CAN_F5R1_FB31_Msk (0x1UL << CAN_F5R1_FB31_Pos)
4388#define CAN_F5R1_FB31 CAN_F5R1_FB31_Msk
4390/******************* Bit definition for CAN_F6R1 register *******************/
4391#define CAN_F6R1_FB0_Pos (0U)
4392#define CAN_F6R1_FB0_Msk (0x1UL << CAN_F6R1_FB0_Pos)
4393#define CAN_F6R1_FB0 CAN_F6R1_FB0_Msk
4394#define CAN_F6R1_FB1_Pos (1U)
4395#define CAN_F6R1_FB1_Msk (0x1UL << CAN_F6R1_FB1_Pos)
4396#define CAN_F6R1_FB1 CAN_F6R1_FB1_Msk
4397#define CAN_F6R1_FB2_Pos (2U)
4398#define CAN_F6R1_FB2_Msk (0x1UL << CAN_F6R1_FB2_Pos)
4399#define CAN_F6R1_FB2 CAN_F6R1_FB2_Msk
4400#define CAN_F6R1_FB3_Pos (3U)
4401#define CAN_F6R1_FB3_Msk (0x1UL << CAN_F6R1_FB3_Pos)
4402#define CAN_F6R1_FB3 CAN_F6R1_FB3_Msk
4403#define CAN_F6R1_FB4_Pos (4U)
4404#define CAN_F6R1_FB4_Msk (0x1UL << CAN_F6R1_FB4_Pos)
4405#define CAN_F6R1_FB4 CAN_F6R1_FB4_Msk
4406#define CAN_F6R1_FB5_Pos (5U)
4407#define CAN_F6R1_FB5_Msk (0x1UL << CAN_F6R1_FB5_Pos)
4408#define CAN_F6R1_FB5 CAN_F6R1_FB5_Msk
4409#define CAN_F6R1_FB6_Pos (6U)
4410#define CAN_F6R1_FB6_Msk (0x1UL << CAN_F6R1_FB6_Pos)
4411#define CAN_F6R1_FB6 CAN_F6R1_FB6_Msk
4412#define CAN_F6R1_FB7_Pos (7U)
4413#define CAN_F6R1_FB7_Msk (0x1UL << CAN_F6R1_FB7_Pos)
4414#define CAN_F6R1_FB7 CAN_F6R1_FB7_Msk
4415#define CAN_F6R1_FB8_Pos (8U)
4416#define CAN_F6R1_FB8_Msk (0x1UL << CAN_F6R1_FB8_Pos)
4417#define CAN_F6R1_FB8 CAN_F6R1_FB8_Msk
4418#define CAN_F6R1_FB9_Pos (9U)
4419#define CAN_F6R1_FB9_Msk (0x1UL << CAN_F6R1_FB9_Pos)
4420#define CAN_F6R1_FB9 CAN_F6R1_FB9_Msk
4421#define CAN_F6R1_FB10_Pos (10U)
4422#define CAN_F6R1_FB10_Msk (0x1UL << CAN_F6R1_FB10_Pos)
4423#define CAN_F6R1_FB10 CAN_F6R1_FB10_Msk
4424#define CAN_F6R1_FB11_Pos (11U)
4425#define CAN_F6R1_FB11_Msk (0x1UL << CAN_F6R1_FB11_Pos)
4426#define CAN_F6R1_FB11 CAN_F6R1_FB11_Msk
4427#define CAN_F6R1_FB12_Pos (12U)
4428#define CAN_F6R1_FB12_Msk (0x1UL << CAN_F6R1_FB12_Pos)
4429#define CAN_F6R1_FB12 CAN_F6R1_FB12_Msk
4430#define CAN_F6R1_FB13_Pos (13U)
4431#define CAN_F6R1_FB13_Msk (0x1UL << CAN_F6R1_FB13_Pos)
4432#define CAN_F6R1_FB13 CAN_F6R1_FB13_Msk
4433#define CAN_F6R1_FB14_Pos (14U)
4434#define CAN_F6R1_FB14_Msk (0x1UL << CAN_F6R1_FB14_Pos)
4435#define CAN_F6R1_FB14 CAN_F6R1_FB14_Msk
4436#define CAN_F6R1_FB15_Pos (15U)
4437#define CAN_F6R1_FB15_Msk (0x1UL << CAN_F6R1_FB15_Pos)
4438#define CAN_F6R1_FB15 CAN_F6R1_FB15_Msk
4439#define CAN_F6R1_FB16_Pos (16U)
4440#define CAN_F6R1_FB16_Msk (0x1UL << CAN_F6R1_FB16_Pos)
4441#define CAN_F6R1_FB16 CAN_F6R1_FB16_Msk
4442#define CAN_F6R1_FB17_Pos (17U)
4443#define CAN_F6R1_FB17_Msk (0x1UL << CAN_F6R1_FB17_Pos)
4444#define CAN_F6R1_FB17 CAN_F6R1_FB17_Msk
4445#define CAN_F6R1_FB18_Pos (18U)
4446#define CAN_F6R1_FB18_Msk (0x1UL << CAN_F6R1_FB18_Pos)
4447#define CAN_F6R1_FB18 CAN_F6R1_FB18_Msk
4448#define CAN_F6R1_FB19_Pos (19U)
4449#define CAN_F6R1_FB19_Msk (0x1UL << CAN_F6R1_FB19_Pos)
4450#define CAN_F6R1_FB19 CAN_F6R1_FB19_Msk
4451#define CAN_F6R1_FB20_Pos (20U)
4452#define CAN_F6R1_FB20_Msk (0x1UL << CAN_F6R1_FB20_Pos)
4453#define CAN_F6R1_FB20 CAN_F6R1_FB20_Msk
4454#define CAN_F6R1_FB21_Pos (21U)
4455#define CAN_F6R1_FB21_Msk (0x1UL << CAN_F6R1_FB21_Pos)
4456#define CAN_F6R1_FB21 CAN_F6R1_FB21_Msk
4457#define CAN_F6R1_FB22_Pos (22U)
4458#define CAN_F6R1_FB22_Msk (0x1UL << CAN_F6R1_FB22_Pos)
4459#define CAN_F6R1_FB22 CAN_F6R1_FB22_Msk
4460#define CAN_F6R1_FB23_Pos (23U)
4461#define CAN_F6R1_FB23_Msk (0x1UL << CAN_F6R1_FB23_Pos)
4462#define CAN_F6R1_FB23 CAN_F6R1_FB23_Msk
4463#define CAN_F6R1_FB24_Pos (24U)
4464#define CAN_F6R1_FB24_Msk (0x1UL << CAN_F6R1_FB24_Pos)
4465#define CAN_F6R1_FB24 CAN_F6R1_FB24_Msk
4466#define CAN_F6R1_FB25_Pos (25U)
4467#define CAN_F6R1_FB25_Msk (0x1UL << CAN_F6R1_FB25_Pos)
4468#define CAN_F6R1_FB25 CAN_F6R1_FB25_Msk
4469#define CAN_F6R1_FB26_Pos (26U)
4470#define CAN_F6R1_FB26_Msk (0x1UL << CAN_F6R1_FB26_Pos)
4471#define CAN_F6R1_FB26 CAN_F6R1_FB26_Msk
4472#define CAN_F6R1_FB27_Pos (27U)
4473#define CAN_F6R1_FB27_Msk (0x1UL << CAN_F6R1_FB27_Pos)
4474#define CAN_F6R1_FB27 CAN_F6R1_FB27_Msk
4475#define CAN_F6R1_FB28_Pos (28U)
4476#define CAN_F6R1_FB28_Msk (0x1UL << CAN_F6R1_FB28_Pos)
4477#define CAN_F6R1_FB28 CAN_F6R1_FB28_Msk
4478#define CAN_F6R1_FB29_Pos (29U)
4479#define CAN_F6R1_FB29_Msk (0x1UL << CAN_F6R1_FB29_Pos)
4480#define CAN_F6R1_FB29 CAN_F6R1_FB29_Msk
4481#define CAN_F6R1_FB30_Pos (30U)
4482#define CAN_F6R1_FB30_Msk (0x1UL << CAN_F6R1_FB30_Pos)
4483#define CAN_F6R1_FB30 CAN_F6R1_FB30_Msk
4484#define CAN_F6R1_FB31_Pos (31U)
4485#define CAN_F6R1_FB31_Msk (0x1UL << CAN_F6R1_FB31_Pos)
4486#define CAN_F6R1_FB31 CAN_F6R1_FB31_Msk
4488/******************* Bit definition for CAN_F7R1 register *******************/
4489#define CAN_F7R1_FB0_Pos (0U)
4490#define CAN_F7R1_FB0_Msk (0x1UL << CAN_F7R1_FB0_Pos)
4491#define CAN_F7R1_FB0 CAN_F7R1_FB0_Msk
4492#define CAN_F7R1_FB1_Pos (1U)
4493#define CAN_F7R1_FB1_Msk (0x1UL << CAN_F7R1_FB1_Pos)
4494#define CAN_F7R1_FB1 CAN_F7R1_FB1_Msk
4495#define CAN_F7R1_FB2_Pos (2U)
4496#define CAN_F7R1_FB2_Msk (0x1UL << CAN_F7R1_FB2_Pos)
4497#define CAN_F7R1_FB2 CAN_F7R1_FB2_Msk
4498#define CAN_F7R1_FB3_Pos (3U)
4499#define CAN_F7R1_FB3_Msk (0x1UL << CAN_F7R1_FB3_Pos)
4500#define CAN_F7R1_FB3 CAN_F7R1_FB3_Msk
4501#define CAN_F7R1_FB4_Pos (4U)
4502#define CAN_F7R1_FB4_Msk (0x1UL << CAN_F7R1_FB4_Pos)
4503#define CAN_F7R1_FB4 CAN_F7R1_FB4_Msk
4504#define CAN_F7R1_FB5_Pos (5U)
4505#define CAN_F7R1_FB5_Msk (0x1UL << CAN_F7R1_FB5_Pos)
4506#define CAN_F7R1_FB5 CAN_F7R1_FB5_Msk
4507#define CAN_F7R1_FB6_Pos (6U)
4508#define CAN_F7R1_FB6_Msk (0x1UL << CAN_F7R1_FB6_Pos)
4509#define CAN_F7R1_FB6 CAN_F7R1_FB6_Msk
4510#define CAN_F7R1_FB7_Pos (7U)
4511#define CAN_F7R1_FB7_Msk (0x1UL << CAN_F7R1_FB7_Pos)
4512#define CAN_F7R1_FB7 CAN_F7R1_FB7_Msk
4513#define CAN_F7R1_FB8_Pos (8U)
4514#define CAN_F7R1_FB8_Msk (0x1UL << CAN_F7R1_FB8_Pos)
4515#define CAN_F7R1_FB8 CAN_F7R1_FB8_Msk
4516#define CAN_F7R1_FB9_Pos (9U)
4517#define CAN_F7R1_FB9_Msk (0x1UL << CAN_F7R1_FB9_Pos)
4518#define CAN_F7R1_FB9 CAN_F7R1_FB9_Msk
4519#define CAN_F7R1_FB10_Pos (10U)
4520#define CAN_F7R1_FB10_Msk (0x1UL << CAN_F7R1_FB10_Pos)
4521#define CAN_F7R1_FB10 CAN_F7R1_FB10_Msk
4522#define CAN_F7R1_FB11_Pos (11U)
4523#define CAN_F7R1_FB11_Msk (0x1UL << CAN_F7R1_FB11_Pos)
4524#define CAN_F7R1_FB11 CAN_F7R1_FB11_Msk
4525#define CAN_F7R1_FB12_Pos (12U)
4526#define CAN_F7R1_FB12_Msk (0x1UL << CAN_F7R1_FB12_Pos)
4527#define CAN_F7R1_FB12 CAN_F7R1_FB12_Msk
4528#define CAN_F7R1_FB13_Pos (13U)
4529#define CAN_F7R1_FB13_Msk (0x1UL << CAN_F7R1_FB13_Pos)
4530#define CAN_F7R1_FB13 CAN_F7R1_FB13_Msk
4531#define CAN_F7R1_FB14_Pos (14U)
4532#define CAN_F7R1_FB14_Msk (0x1UL << CAN_F7R1_FB14_Pos)
4533#define CAN_F7R1_FB14 CAN_F7R1_FB14_Msk
4534#define CAN_F7R1_FB15_Pos (15U)
4535#define CAN_F7R1_FB15_Msk (0x1UL << CAN_F7R1_FB15_Pos)
4536#define CAN_F7R1_FB15 CAN_F7R1_FB15_Msk
4537#define CAN_F7R1_FB16_Pos (16U)
4538#define CAN_F7R1_FB16_Msk (0x1UL << CAN_F7R1_FB16_Pos)
4539#define CAN_F7R1_FB16 CAN_F7R1_FB16_Msk
4540#define CAN_F7R1_FB17_Pos (17U)
4541#define CAN_F7R1_FB17_Msk (0x1UL << CAN_F7R1_FB17_Pos)
4542#define CAN_F7R1_FB17 CAN_F7R1_FB17_Msk
4543#define CAN_F7R1_FB18_Pos (18U)
4544#define CAN_F7R1_FB18_Msk (0x1UL << CAN_F7R1_FB18_Pos)
4545#define CAN_F7R1_FB18 CAN_F7R1_FB18_Msk
4546#define CAN_F7R1_FB19_Pos (19U)
4547#define CAN_F7R1_FB19_Msk (0x1UL << CAN_F7R1_FB19_Pos)
4548#define CAN_F7R1_FB19 CAN_F7R1_FB19_Msk
4549#define CAN_F7R1_FB20_Pos (20U)
4550#define CAN_F7R1_FB20_Msk (0x1UL << CAN_F7R1_FB20_Pos)
4551#define CAN_F7R1_FB20 CAN_F7R1_FB20_Msk
4552#define CAN_F7R1_FB21_Pos (21U)
4553#define CAN_F7R1_FB21_Msk (0x1UL << CAN_F7R1_FB21_Pos)
4554#define CAN_F7R1_FB21 CAN_F7R1_FB21_Msk
4555#define CAN_F7R1_FB22_Pos (22U)
4556#define CAN_F7R1_FB22_Msk (0x1UL << CAN_F7R1_FB22_Pos)
4557#define CAN_F7R1_FB22 CAN_F7R1_FB22_Msk
4558#define CAN_F7R1_FB23_Pos (23U)
4559#define CAN_F7R1_FB23_Msk (0x1UL << CAN_F7R1_FB23_Pos)
4560#define CAN_F7R1_FB23 CAN_F7R1_FB23_Msk
4561#define CAN_F7R1_FB24_Pos (24U)
4562#define CAN_F7R1_FB24_Msk (0x1UL << CAN_F7R1_FB24_Pos)
4563#define CAN_F7R1_FB24 CAN_F7R1_FB24_Msk
4564#define CAN_F7R1_FB25_Pos (25U)
4565#define CAN_F7R1_FB25_Msk (0x1UL << CAN_F7R1_FB25_Pos)
4566#define CAN_F7R1_FB25 CAN_F7R1_FB25_Msk
4567#define CAN_F7R1_FB26_Pos (26U)
4568#define CAN_F7R1_FB26_Msk (0x1UL << CAN_F7R1_FB26_Pos)
4569#define CAN_F7R1_FB26 CAN_F7R1_FB26_Msk
4570#define CAN_F7R1_FB27_Pos (27U)
4571#define CAN_F7R1_FB27_Msk (0x1UL << CAN_F7R1_FB27_Pos)
4572#define CAN_F7R1_FB27 CAN_F7R1_FB27_Msk
4573#define CAN_F7R1_FB28_Pos (28U)
4574#define CAN_F7R1_FB28_Msk (0x1UL << CAN_F7R1_FB28_Pos)
4575#define CAN_F7R1_FB28 CAN_F7R1_FB28_Msk
4576#define CAN_F7R1_FB29_Pos (29U)
4577#define CAN_F7R1_FB29_Msk (0x1UL << CAN_F7R1_FB29_Pos)
4578#define CAN_F7R1_FB29 CAN_F7R1_FB29_Msk
4579#define CAN_F7R1_FB30_Pos (30U)
4580#define CAN_F7R1_FB30_Msk (0x1UL << CAN_F7R1_FB30_Pos)
4581#define CAN_F7R1_FB30 CAN_F7R1_FB30_Msk
4582#define CAN_F7R1_FB31_Pos (31U)
4583#define CAN_F7R1_FB31_Msk (0x1UL << CAN_F7R1_FB31_Pos)
4584#define CAN_F7R1_FB31 CAN_F7R1_FB31_Msk
4586/******************* Bit definition for CAN_F8R1 register *******************/
4587#define CAN_F8R1_FB0_Pos (0U)
4588#define CAN_F8R1_FB0_Msk (0x1UL << CAN_F8R1_FB0_Pos)
4589#define CAN_F8R1_FB0 CAN_F8R1_FB0_Msk
4590#define CAN_F8R1_FB1_Pos (1U)
4591#define CAN_F8R1_FB1_Msk (0x1UL << CAN_F8R1_FB1_Pos)
4592#define CAN_F8R1_FB1 CAN_F8R1_FB1_Msk
4593#define CAN_F8R1_FB2_Pos (2U)
4594#define CAN_F8R1_FB2_Msk (0x1UL << CAN_F8R1_FB2_Pos)
4595#define CAN_F8R1_FB2 CAN_F8R1_FB2_Msk
4596#define CAN_F8R1_FB3_Pos (3U)
4597#define CAN_F8R1_FB3_Msk (0x1UL << CAN_F8R1_FB3_Pos)
4598#define CAN_F8R1_FB3 CAN_F8R1_FB3_Msk
4599#define CAN_F8R1_FB4_Pos (4U)
4600#define CAN_F8R1_FB4_Msk (0x1UL << CAN_F8R1_FB4_Pos)
4601#define CAN_F8R1_FB4 CAN_F8R1_FB4_Msk
4602#define CAN_F8R1_FB5_Pos (5U)
4603#define CAN_F8R1_FB5_Msk (0x1UL << CAN_F8R1_FB5_Pos)
4604#define CAN_F8R1_FB5 CAN_F8R1_FB5_Msk
4605#define CAN_F8R1_FB6_Pos (6U)
4606#define CAN_F8R1_FB6_Msk (0x1UL << CAN_F8R1_FB6_Pos)
4607#define CAN_F8R1_FB6 CAN_F8R1_FB6_Msk
4608#define CAN_F8R1_FB7_Pos (7U)
4609#define CAN_F8R1_FB7_Msk (0x1UL << CAN_F8R1_FB7_Pos)
4610#define CAN_F8R1_FB7 CAN_F8R1_FB7_Msk
4611#define CAN_F8R1_FB8_Pos (8U)
4612#define CAN_F8R1_FB8_Msk (0x1UL << CAN_F8R1_FB8_Pos)
4613#define CAN_F8R1_FB8 CAN_F8R1_FB8_Msk
4614#define CAN_F8R1_FB9_Pos (9U)
4615#define CAN_F8R1_FB9_Msk (0x1UL << CAN_F8R1_FB9_Pos)
4616#define CAN_F8R1_FB9 CAN_F8R1_FB9_Msk
4617#define CAN_F8R1_FB10_Pos (10U)
4618#define CAN_F8R1_FB10_Msk (0x1UL << CAN_F8R1_FB10_Pos)
4619#define CAN_F8R1_FB10 CAN_F8R1_FB10_Msk
4620#define CAN_F8R1_FB11_Pos (11U)
4621#define CAN_F8R1_FB11_Msk (0x1UL << CAN_F8R1_FB11_Pos)
4622#define CAN_F8R1_FB11 CAN_F8R1_FB11_Msk
4623#define CAN_F8R1_FB12_Pos (12U)
4624#define CAN_F8R1_FB12_Msk (0x1UL << CAN_F8R1_FB12_Pos)
4625#define CAN_F8R1_FB12 CAN_F8R1_FB12_Msk
4626#define CAN_F8R1_FB13_Pos (13U)
4627#define CAN_F8R1_FB13_Msk (0x1UL << CAN_F8R1_FB13_Pos)
4628#define CAN_F8R1_FB13 CAN_F8R1_FB13_Msk
4629#define CAN_F8R1_FB14_Pos (14U)
4630#define CAN_F8R1_FB14_Msk (0x1UL << CAN_F8R1_FB14_Pos)
4631#define CAN_F8R1_FB14 CAN_F8R1_FB14_Msk
4632#define CAN_F8R1_FB15_Pos (15U)
4633#define CAN_F8R1_FB15_Msk (0x1UL << CAN_F8R1_FB15_Pos)
4634#define CAN_F8R1_FB15 CAN_F8R1_FB15_Msk
4635#define CAN_F8R1_FB16_Pos (16U)
4636#define CAN_F8R1_FB16_Msk (0x1UL << CAN_F8R1_FB16_Pos)
4637#define CAN_F8R1_FB16 CAN_F8R1_FB16_Msk
4638#define CAN_F8R1_FB17_Pos (17U)
4639#define CAN_F8R1_FB17_Msk (0x1UL << CAN_F8R1_FB17_Pos)
4640#define CAN_F8R1_FB17 CAN_F8R1_FB17_Msk
4641#define CAN_F8R1_FB18_Pos (18U)
4642#define CAN_F8R1_FB18_Msk (0x1UL << CAN_F8R1_FB18_Pos)
4643#define CAN_F8R1_FB18 CAN_F8R1_FB18_Msk
4644#define CAN_F8R1_FB19_Pos (19U)
4645#define CAN_F8R1_FB19_Msk (0x1UL << CAN_F8R1_FB19_Pos)
4646#define CAN_F8R1_FB19 CAN_F8R1_FB19_Msk
4647#define CAN_F8R1_FB20_Pos (20U)
4648#define CAN_F8R1_FB20_Msk (0x1UL << CAN_F8R1_FB20_Pos)
4649#define CAN_F8R1_FB20 CAN_F8R1_FB20_Msk
4650#define CAN_F8R1_FB21_Pos (21U)
4651#define CAN_F8R1_FB21_Msk (0x1UL << CAN_F8R1_FB21_Pos)
4652#define CAN_F8R1_FB21 CAN_F8R1_FB21_Msk
4653#define CAN_F8R1_FB22_Pos (22U)
4654#define CAN_F8R1_FB22_Msk (0x1UL << CAN_F8R1_FB22_Pos)
4655#define CAN_F8R1_FB22 CAN_F8R1_FB22_Msk
4656#define CAN_F8R1_FB23_Pos (23U)
4657#define CAN_F8R1_FB23_Msk (0x1UL << CAN_F8R1_FB23_Pos)
4658#define CAN_F8R1_FB23 CAN_F8R1_FB23_Msk
4659#define CAN_F8R1_FB24_Pos (24U)
4660#define CAN_F8R1_FB24_Msk (0x1UL << CAN_F8R1_FB24_Pos)
4661#define CAN_F8R1_FB24 CAN_F8R1_FB24_Msk
4662#define CAN_F8R1_FB25_Pos (25U)
4663#define CAN_F8R1_FB25_Msk (0x1UL << CAN_F8R1_FB25_Pos)
4664#define CAN_F8R1_FB25 CAN_F8R1_FB25_Msk
4665#define CAN_F8R1_FB26_Pos (26U)
4666#define CAN_F8R1_FB26_Msk (0x1UL << CAN_F8R1_FB26_Pos)
4667#define CAN_F8R1_FB26 CAN_F8R1_FB26_Msk
4668#define CAN_F8R1_FB27_Pos (27U)
4669#define CAN_F8R1_FB27_Msk (0x1UL << CAN_F8R1_FB27_Pos)
4670#define CAN_F8R1_FB27 CAN_F8R1_FB27_Msk
4671#define CAN_F8R1_FB28_Pos (28U)
4672#define CAN_F8R1_FB28_Msk (0x1UL << CAN_F8R1_FB28_Pos)
4673#define CAN_F8R1_FB28 CAN_F8R1_FB28_Msk
4674#define CAN_F8R1_FB29_Pos (29U)
4675#define CAN_F8R1_FB29_Msk (0x1UL << CAN_F8R1_FB29_Pos)
4676#define CAN_F8R1_FB29 CAN_F8R1_FB29_Msk
4677#define CAN_F8R1_FB30_Pos (30U)
4678#define CAN_F8R1_FB30_Msk (0x1UL << CAN_F8R1_FB30_Pos)
4679#define CAN_F8R1_FB30 CAN_F8R1_FB30_Msk
4680#define CAN_F8R1_FB31_Pos (31U)
4681#define CAN_F8R1_FB31_Msk (0x1UL << CAN_F8R1_FB31_Pos)
4682#define CAN_F8R1_FB31 CAN_F8R1_FB31_Msk
4684/******************* Bit definition for CAN_F9R1 register *******************/
4685#define CAN_F9R1_FB0_Pos (0U)
4686#define CAN_F9R1_FB0_Msk (0x1UL << CAN_F9R1_FB0_Pos)
4687#define CAN_F9R1_FB0 CAN_F9R1_FB0_Msk
4688#define CAN_F9R1_FB1_Pos (1U)
4689#define CAN_F9R1_FB1_Msk (0x1UL << CAN_F9R1_FB1_Pos)
4690#define CAN_F9R1_FB1 CAN_F9R1_FB1_Msk
4691#define CAN_F9R1_FB2_Pos (2U)
4692#define CAN_F9R1_FB2_Msk (0x1UL << CAN_F9R1_FB2_Pos)
4693#define CAN_F9R1_FB2 CAN_F9R1_FB2_Msk
4694#define CAN_F9R1_FB3_Pos (3U)
4695#define CAN_F9R1_FB3_Msk (0x1UL << CAN_F9R1_FB3_Pos)
4696#define CAN_F9R1_FB3 CAN_F9R1_FB3_Msk
4697#define CAN_F9R1_FB4_Pos (4U)
4698#define CAN_F9R1_FB4_Msk (0x1UL << CAN_F9R1_FB4_Pos)
4699#define CAN_F9R1_FB4 CAN_F9R1_FB4_Msk
4700#define CAN_F9R1_FB5_Pos (5U)
4701#define CAN_F9R1_FB5_Msk (0x1UL << CAN_F9R1_FB5_Pos)
4702#define CAN_F9R1_FB5 CAN_F9R1_FB5_Msk
4703#define CAN_F9R1_FB6_Pos (6U)
4704#define CAN_F9R1_FB6_Msk (0x1UL << CAN_F9R1_FB6_Pos)
4705#define CAN_F9R1_FB6 CAN_F9R1_FB6_Msk
4706#define CAN_F9R1_FB7_Pos (7U)
4707#define CAN_F9R1_FB7_Msk (0x1UL << CAN_F9R1_FB7_Pos)
4708#define CAN_F9R1_FB7 CAN_F9R1_FB7_Msk
4709#define CAN_F9R1_FB8_Pos (8U)
4710#define CAN_F9R1_FB8_Msk (0x1UL << CAN_F9R1_FB8_Pos)
4711#define CAN_F9R1_FB8 CAN_F9R1_FB8_Msk
4712#define CAN_F9R1_FB9_Pos (9U)
4713#define CAN_F9R1_FB9_Msk (0x1UL << CAN_F9R1_FB9_Pos)
4714#define CAN_F9R1_FB9 CAN_F9R1_FB9_Msk
4715#define CAN_F9R1_FB10_Pos (10U)
4716#define CAN_F9R1_FB10_Msk (0x1UL << CAN_F9R1_FB10_Pos)
4717#define CAN_F9R1_FB10 CAN_F9R1_FB10_Msk
4718#define CAN_F9R1_FB11_Pos (11U)
4719#define CAN_F9R1_FB11_Msk (0x1UL << CAN_F9R1_FB11_Pos)
4720#define CAN_F9R1_FB11 CAN_F9R1_FB11_Msk
4721#define CAN_F9R1_FB12_Pos (12U)
4722#define CAN_F9R1_FB12_Msk (0x1UL << CAN_F9R1_FB12_Pos)
4723#define CAN_F9R1_FB12 CAN_F9R1_FB12_Msk
4724#define CAN_F9R1_FB13_Pos (13U)
4725#define CAN_F9R1_FB13_Msk (0x1UL << CAN_F9R1_FB13_Pos)
4726#define CAN_F9R1_FB13 CAN_F9R1_FB13_Msk
4727#define CAN_F9R1_FB14_Pos (14U)
4728#define CAN_F9R1_FB14_Msk (0x1UL << CAN_F9R1_FB14_Pos)
4729#define CAN_F9R1_FB14 CAN_F9R1_FB14_Msk
4730#define CAN_F9R1_FB15_Pos (15U)
4731#define CAN_F9R1_FB15_Msk (0x1UL << CAN_F9R1_FB15_Pos)
4732#define CAN_F9R1_FB15 CAN_F9R1_FB15_Msk
4733#define CAN_F9R1_FB16_Pos (16U)
4734#define CAN_F9R1_FB16_Msk (0x1UL << CAN_F9R1_FB16_Pos)
4735#define CAN_F9R1_FB16 CAN_F9R1_FB16_Msk
4736#define CAN_F9R1_FB17_Pos (17U)
4737#define CAN_F9R1_FB17_Msk (0x1UL << CAN_F9R1_FB17_Pos)
4738#define CAN_F9R1_FB17 CAN_F9R1_FB17_Msk
4739#define CAN_F9R1_FB18_Pos (18U)
4740#define CAN_F9R1_FB18_Msk (0x1UL << CAN_F9R1_FB18_Pos)
4741#define CAN_F9R1_FB18 CAN_F9R1_FB18_Msk
4742#define CAN_F9R1_FB19_Pos (19U)
4743#define CAN_F9R1_FB19_Msk (0x1UL << CAN_F9R1_FB19_Pos)
4744#define CAN_F9R1_FB19 CAN_F9R1_FB19_Msk
4745#define CAN_F9R1_FB20_Pos (20U)
4746#define CAN_F9R1_FB20_Msk (0x1UL << CAN_F9R1_FB20_Pos)
4747#define CAN_F9R1_FB20 CAN_F9R1_FB20_Msk
4748#define CAN_F9R1_FB21_Pos (21U)
4749#define CAN_F9R1_FB21_Msk (0x1UL << CAN_F9R1_FB21_Pos)
4750#define CAN_F9R1_FB21 CAN_F9R1_FB21_Msk
4751#define CAN_F9R1_FB22_Pos (22U)
4752#define CAN_F9R1_FB22_Msk (0x1UL << CAN_F9R1_FB22_Pos)
4753#define CAN_F9R1_FB22 CAN_F9R1_FB22_Msk
4754#define CAN_F9R1_FB23_Pos (23U)
4755#define CAN_F9R1_FB23_Msk (0x1UL << CAN_F9R1_FB23_Pos)
4756#define CAN_F9R1_FB23 CAN_F9R1_FB23_Msk
4757#define CAN_F9R1_FB24_Pos (24U)
4758#define CAN_F9R1_FB24_Msk (0x1UL << CAN_F9R1_FB24_Pos)
4759#define CAN_F9R1_FB24 CAN_F9R1_FB24_Msk
4760#define CAN_F9R1_FB25_Pos (25U)
4761#define CAN_F9R1_FB25_Msk (0x1UL << CAN_F9R1_FB25_Pos)
4762#define CAN_F9R1_FB25 CAN_F9R1_FB25_Msk
4763#define CAN_F9R1_FB26_Pos (26U)
4764#define CAN_F9R1_FB26_Msk (0x1UL << CAN_F9R1_FB26_Pos)
4765#define CAN_F9R1_FB26 CAN_F9R1_FB26_Msk
4766#define CAN_F9R1_FB27_Pos (27U)
4767#define CAN_F9R1_FB27_Msk (0x1UL << CAN_F9R1_FB27_Pos)
4768#define CAN_F9R1_FB27 CAN_F9R1_FB27_Msk
4769#define CAN_F9R1_FB28_Pos (28U)
4770#define CAN_F9R1_FB28_Msk (0x1UL << CAN_F9R1_FB28_Pos)
4771#define CAN_F9R1_FB28 CAN_F9R1_FB28_Msk
4772#define CAN_F9R1_FB29_Pos (29U)
4773#define CAN_F9R1_FB29_Msk (0x1UL << CAN_F9R1_FB29_Pos)
4774#define CAN_F9R1_FB29 CAN_F9R1_FB29_Msk
4775#define CAN_F9R1_FB30_Pos (30U)
4776#define CAN_F9R1_FB30_Msk (0x1UL << CAN_F9R1_FB30_Pos)
4777#define CAN_F9R1_FB30 CAN_F9R1_FB30_Msk
4778#define CAN_F9R1_FB31_Pos (31U)
4779#define CAN_F9R1_FB31_Msk (0x1UL << CAN_F9R1_FB31_Pos)
4780#define CAN_F9R1_FB31 CAN_F9R1_FB31_Msk
4782/******************* Bit definition for CAN_F10R1 register ******************/
4783#define CAN_F10R1_FB0_Pos (0U)
4784#define CAN_F10R1_FB0_Msk (0x1UL << CAN_F10R1_FB0_Pos)
4785#define CAN_F10R1_FB0 CAN_F10R1_FB0_Msk
4786#define CAN_F10R1_FB1_Pos (1U)
4787#define CAN_F10R1_FB1_Msk (0x1UL << CAN_F10R1_FB1_Pos)
4788#define CAN_F10R1_FB1 CAN_F10R1_FB1_Msk
4789#define CAN_F10R1_FB2_Pos (2U)
4790#define CAN_F10R1_FB2_Msk (0x1UL << CAN_F10R1_FB2_Pos)
4791#define CAN_F10R1_FB2 CAN_F10R1_FB2_Msk
4792#define CAN_F10R1_FB3_Pos (3U)
4793#define CAN_F10R1_FB3_Msk (0x1UL << CAN_F10R1_FB3_Pos)
4794#define CAN_F10R1_FB3 CAN_F10R1_FB3_Msk
4795#define CAN_F10R1_FB4_Pos (4U)
4796#define CAN_F10R1_FB4_Msk (0x1UL << CAN_F10R1_FB4_Pos)
4797#define CAN_F10R1_FB4 CAN_F10R1_FB4_Msk
4798#define CAN_F10R1_FB5_Pos (5U)
4799#define CAN_F10R1_FB5_Msk (0x1UL << CAN_F10R1_FB5_Pos)
4800#define CAN_F10R1_FB5 CAN_F10R1_FB5_Msk
4801#define CAN_F10R1_FB6_Pos (6U)
4802#define CAN_F10R1_FB6_Msk (0x1UL << CAN_F10R1_FB6_Pos)
4803#define CAN_F10R1_FB6 CAN_F10R1_FB6_Msk
4804#define CAN_F10R1_FB7_Pos (7U)
4805#define CAN_F10R1_FB7_Msk (0x1UL << CAN_F10R1_FB7_Pos)
4806#define CAN_F10R1_FB7 CAN_F10R1_FB7_Msk
4807#define CAN_F10R1_FB8_Pos (8U)
4808#define CAN_F10R1_FB8_Msk (0x1UL << CAN_F10R1_FB8_Pos)
4809#define CAN_F10R1_FB8 CAN_F10R1_FB8_Msk
4810#define CAN_F10R1_FB9_Pos (9U)
4811#define CAN_F10R1_FB9_Msk (0x1UL << CAN_F10R1_FB9_Pos)
4812#define CAN_F10R1_FB9 CAN_F10R1_FB9_Msk
4813#define CAN_F10R1_FB10_Pos (10U)
4814#define CAN_F10R1_FB10_Msk (0x1UL << CAN_F10R1_FB10_Pos)
4815#define CAN_F10R1_FB10 CAN_F10R1_FB10_Msk
4816#define CAN_F10R1_FB11_Pos (11U)
4817#define CAN_F10R1_FB11_Msk (0x1UL << CAN_F10R1_FB11_Pos)
4818#define CAN_F10R1_FB11 CAN_F10R1_FB11_Msk
4819#define CAN_F10R1_FB12_Pos (12U)
4820#define CAN_F10R1_FB12_Msk (0x1UL << CAN_F10R1_FB12_Pos)
4821#define CAN_F10R1_FB12 CAN_F10R1_FB12_Msk
4822#define CAN_F10R1_FB13_Pos (13U)
4823#define CAN_F10R1_FB13_Msk (0x1UL << CAN_F10R1_FB13_Pos)
4824#define CAN_F10R1_FB13 CAN_F10R1_FB13_Msk
4825#define CAN_F10R1_FB14_Pos (14U)
4826#define CAN_F10R1_FB14_Msk (0x1UL << CAN_F10R1_FB14_Pos)
4827#define CAN_F10R1_FB14 CAN_F10R1_FB14_Msk
4828#define CAN_F10R1_FB15_Pos (15U)
4829#define CAN_F10R1_FB15_Msk (0x1UL << CAN_F10R1_FB15_Pos)
4830#define CAN_F10R1_FB15 CAN_F10R1_FB15_Msk
4831#define CAN_F10R1_FB16_Pos (16U)
4832#define CAN_F10R1_FB16_Msk (0x1UL << CAN_F10R1_FB16_Pos)
4833#define CAN_F10R1_FB16 CAN_F10R1_FB16_Msk
4834#define CAN_F10R1_FB17_Pos (17U)
4835#define CAN_F10R1_FB17_Msk (0x1UL << CAN_F10R1_FB17_Pos)
4836#define CAN_F10R1_FB17 CAN_F10R1_FB17_Msk
4837#define CAN_F10R1_FB18_Pos (18U)
4838#define CAN_F10R1_FB18_Msk (0x1UL << CAN_F10R1_FB18_Pos)
4839#define CAN_F10R1_FB18 CAN_F10R1_FB18_Msk
4840#define CAN_F10R1_FB19_Pos (19U)
4841#define CAN_F10R1_FB19_Msk (0x1UL << CAN_F10R1_FB19_Pos)
4842#define CAN_F10R1_FB19 CAN_F10R1_FB19_Msk
4843#define CAN_F10R1_FB20_Pos (20U)
4844#define CAN_F10R1_FB20_Msk (0x1UL << CAN_F10R1_FB20_Pos)
4845#define CAN_F10R1_FB20 CAN_F10R1_FB20_Msk
4846#define CAN_F10R1_FB21_Pos (21U)
4847#define CAN_F10R1_FB21_Msk (0x1UL << CAN_F10R1_FB21_Pos)
4848#define CAN_F10R1_FB21 CAN_F10R1_FB21_Msk
4849#define CAN_F10R1_FB22_Pos (22U)
4850#define CAN_F10R1_FB22_Msk (0x1UL << CAN_F10R1_FB22_Pos)
4851#define CAN_F10R1_FB22 CAN_F10R1_FB22_Msk
4852#define CAN_F10R1_FB23_Pos (23U)
4853#define CAN_F10R1_FB23_Msk (0x1UL << CAN_F10R1_FB23_Pos)
4854#define CAN_F10R1_FB23 CAN_F10R1_FB23_Msk
4855#define CAN_F10R1_FB24_Pos (24U)
4856#define CAN_F10R1_FB24_Msk (0x1UL << CAN_F10R1_FB24_Pos)
4857#define CAN_F10R1_FB24 CAN_F10R1_FB24_Msk
4858#define CAN_F10R1_FB25_Pos (25U)
4859#define CAN_F10R1_FB25_Msk (0x1UL << CAN_F10R1_FB25_Pos)
4860#define CAN_F10R1_FB25 CAN_F10R1_FB25_Msk
4861#define CAN_F10R1_FB26_Pos (26U)
4862#define CAN_F10R1_FB26_Msk (0x1UL << CAN_F10R1_FB26_Pos)
4863#define CAN_F10R1_FB26 CAN_F10R1_FB26_Msk
4864#define CAN_F10R1_FB27_Pos (27U)
4865#define CAN_F10R1_FB27_Msk (0x1UL << CAN_F10R1_FB27_Pos)
4866#define CAN_F10R1_FB27 CAN_F10R1_FB27_Msk
4867#define CAN_F10R1_FB28_Pos (28U)
4868#define CAN_F10R1_FB28_Msk (0x1UL << CAN_F10R1_FB28_Pos)
4869#define CAN_F10R1_FB28 CAN_F10R1_FB28_Msk
4870#define CAN_F10R1_FB29_Pos (29U)
4871#define CAN_F10R1_FB29_Msk (0x1UL << CAN_F10R1_FB29_Pos)
4872#define CAN_F10R1_FB29 CAN_F10R1_FB29_Msk
4873#define CAN_F10R1_FB30_Pos (30U)
4874#define CAN_F10R1_FB30_Msk (0x1UL << CAN_F10R1_FB30_Pos)
4875#define CAN_F10R1_FB30 CAN_F10R1_FB30_Msk
4876#define CAN_F10R1_FB31_Pos (31U)
4877#define CAN_F10R1_FB31_Msk (0x1UL << CAN_F10R1_FB31_Pos)
4878#define CAN_F10R1_FB31 CAN_F10R1_FB31_Msk
4880/******************* Bit definition for CAN_F11R1 register ******************/
4881#define CAN_F11R1_FB0_Pos (0U)
4882#define CAN_F11R1_FB0_Msk (0x1UL << CAN_F11R1_FB0_Pos)
4883#define CAN_F11R1_FB0 CAN_F11R1_FB0_Msk
4884#define CAN_F11R1_FB1_Pos (1U)
4885#define CAN_F11R1_FB1_Msk (0x1UL << CAN_F11R1_FB1_Pos)
4886#define CAN_F11R1_FB1 CAN_F11R1_FB1_Msk
4887#define CAN_F11R1_FB2_Pos (2U)
4888#define CAN_F11R1_FB2_Msk (0x1UL << CAN_F11R1_FB2_Pos)
4889#define CAN_F11R1_FB2 CAN_F11R1_FB2_Msk
4890#define CAN_F11R1_FB3_Pos (3U)
4891#define CAN_F11R1_FB3_Msk (0x1UL << CAN_F11R1_FB3_Pos)
4892#define CAN_F11R1_FB3 CAN_F11R1_FB3_Msk
4893#define CAN_F11R1_FB4_Pos (4U)
4894#define CAN_F11R1_FB4_Msk (0x1UL << CAN_F11R1_FB4_Pos)
4895#define CAN_F11R1_FB4 CAN_F11R1_FB4_Msk
4896#define CAN_F11R1_FB5_Pos (5U)
4897#define CAN_F11R1_FB5_Msk (0x1UL << CAN_F11R1_FB5_Pos)
4898#define CAN_F11R1_FB5 CAN_F11R1_FB5_Msk
4899#define CAN_F11R1_FB6_Pos (6U)
4900#define CAN_F11R1_FB6_Msk (0x1UL << CAN_F11R1_FB6_Pos)
4901#define CAN_F11R1_FB6 CAN_F11R1_FB6_Msk
4902#define CAN_F11R1_FB7_Pos (7U)
4903#define CAN_F11R1_FB7_Msk (0x1UL << CAN_F11R1_FB7_Pos)
4904#define CAN_F11R1_FB7 CAN_F11R1_FB7_Msk
4905#define CAN_F11R1_FB8_Pos (8U)
4906#define CAN_F11R1_FB8_Msk (0x1UL << CAN_F11R1_FB8_Pos)
4907#define CAN_F11R1_FB8 CAN_F11R1_FB8_Msk
4908#define CAN_F11R1_FB9_Pos (9U)
4909#define CAN_F11R1_FB9_Msk (0x1UL << CAN_F11R1_FB9_Pos)
4910#define CAN_F11R1_FB9 CAN_F11R1_FB9_Msk
4911#define CAN_F11R1_FB10_Pos (10U)
4912#define CAN_F11R1_FB10_Msk (0x1UL << CAN_F11R1_FB10_Pos)
4913#define CAN_F11R1_FB10 CAN_F11R1_FB10_Msk
4914#define CAN_F11R1_FB11_Pos (11U)
4915#define CAN_F11R1_FB11_Msk (0x1UL << CAN_F11R1_FB11_Pos)
4916#define CAN_F11R1_FB11 CAN_F11R1_FB11_Msk
4917#define CAN_F11R1_FB12_Pos (12U)
4918#define CAN_F11R1_FB12_Msk (0x1UL << CAN_F11R1_FB12_Pos)
4919#define CAN_F11R1_FB12 CAN_F11R1_FB12_Msk
4920#define CAN_F11R1_FB13_Pos (13U)
4921#define CAN_F11R1_FB13_Msk (0x1UL << CAN_F11R1_FB13_Pos)
4922#define CAN_F11R1_FB13 CAN_F11R1_FB13_Msk
4923#define CAN_F11R1_FB14_Pos (14U)
4924#define CAN_F11R1_FB14_Msk (0x1UL << CAN_F11R1_FB14_Pos)
4925#define CAN_F11R1_FB14 CAN_F11R1_FB14_Msk
4926#define CAN_F11R1_FB15_Pos (15U)
4927#define CAN_F11R1_FB15_Msk (0x1UL << CAN_F11R1_FB15_Pos)
4928#define CAN_F11R1_FB15 CAN_F11R1_FB15_Msk
4929#define CAN_F11R1_FB16_Pos (16U)
4930#define CAN_F11R1_FB16_Msk (0x1UL << CAN_F11R1_FB16_Pos)
4931#define CAN_F11R1_FB16 CAN_F11R1_FB16_Msk
4932#define CAN_F11R1_FB17_Pos (17U)
4933#define CAN_F11R1_FB17_Msk (0x1UL << CAN_F11R1_FB17_Pos)
4934#define CAN_F11R1_FB17 CAN_F11R1_FB17_Msk
4935#define CAN_F11R1_FB18_Pos (18U)
4936#define CAN_F11R1_FB18_Msk (0x1UL << CAN_F11R1_FB18_Pos)
4937#define CAN_F11R1_FB18 CAN_F11R1_FB18_Msk
4938#define CAN_F11R1_FB19_Pos (19U)
4939#define CAN_F11R1_FB19_Msk (0x1UL << CAN_F11R1_FB19_Pos)
4940#define CAN_F11R1_FB19 CAN_F11R1_FB19_Msk
4941#define CAN_F11R1_FB20_Pos (20U)
4942#define CAN_F11R1_FB20_Msk (0x1UL << CAN_F11R1_FB20_Pos)
4943#define CAN_F11R1_FB20 CAN_F11R1_FB20_Msk
4944#define CAN_F11R1_FB21_Pos (21U)
4945#define CAN_F11R1_FB21_Msk (0x1UL << CAN_F11R1_FB21_Pos)
4946#define CAN_F11R1_FB21 CAN_F11R1_FB21_Msk
4947#define CAN_F11R1_FB22_Pos (22U)
4948#define CAN_F11R1_FB22_Msk (0x1UL << CAN_F11R1_FB22_Pos)
4949#define CAN_F11R1_FB22 CAN_F11R1_FB22_Msk
4950#define CAN_F11R1_FB23_Pos (23U)
4951#define CAN_F11R1_FB23_Msk (0x1UL << CAN_F11R1_FB23_Pos)
4952#define CAN_F11R1_FB23 CAN_F11R1_FB23_Msk
4953#define CAN_F11R1_FB24_Pos (24U)
4954#define CAN_F11R1_FB24_Msk (0x1UL << CAN_F11R1_FB24_Pos)
4955#define CAN_F11R1_FB24 CAN_F11R1_FB24_Msk
4956#define CAN_F11R1_FB25_Pos (25U)
4957#define CAN_F11R1_FB25_Msk (0x1UL << CAN_F11R1_FB25_Pos)
4958#define CAN_F11R1_FB25 CAN_F11R1_FB25_Msk
4959#define CAN_F11R1_FB26_Pos (26U)
4960#define CAN_F11R1_FB26_Msk (0x1UL << CAN_F11R1_FB26_Pos)
4961#define CAN_F11R1_FB26 CAN_F11R1_FB26_Msk
4962#define CAN_F11R1_FB27_Pos (27U)
4963#define CAN_F11R1_FB27_Msk (0x1UL << CAN_F11R1_FB27_Pos)
4964#define CAN_F11R1_FB27 CAN_F11R1_FB27_Msk
4965#define CAN_F11R1_FB28_Pos (28U)
4966#define CAN_F11R1_FB28_Msk (0x1UL << CAN_F11R1_FB28_Pos)
4967#define CAN_F11R1_FB28 CAN_F11R1_FB28_Msk
4968#define CAN_F11R1_FB29_Pos (29U)
4969#define CAN_F11R1_FB29_Msk (0x1UL << CAN_F11R1_FB29_Pos)
4970#define CAN_F11R1_FB29 CAN_F11R1_FB29_Msk
4971#define CAN_F11R1_FB30_Pos (30U)
4972#define CAN_F11R1_FB30_Msk (0x1UL << CAN_F11R1_FB30_Pos)
4973#define CAN_F11R1_FB30 CAN_F11R1_FB30_Msk
4974#define CAN_F11R1_FB31_Pos (31U)
4975#define CAN_F11R1_FB31_Msk (0x1UL << CAN_F11R1_FB31_Pos)
4976#define CAN_F11R1_FB31 CAN_F11R1_FB31_Msk
4978/******************* Bit definition for CAN_F12R1 register ******************/
4979#define CAN_F12R1_FB0_Pos (0U)
4980#define CAN_F12R1_FB0_Msk (0x1UL << CAN_F12R1_FB0_Pos)
4981#define CAN_F12R1_FB0 CAN_F12R1_FB0_Msk
4982#define CAN_F12R1_FB1_Pos (1U)
4983#define CAN_F12R1_FB1_Msk (0x1UL << CAN_F12R1_FB1_Pos)
4984#define CAN_F12R1_FB1 CAN_F12R1_FB1_Msk
4985#define CAN_F12R1_FB2_Pos (2U)
4986#define CAN_F12R1_FB2_Msk (0x1UL << CAN_F12R1_FB2_Pos)
4987#define CAN_F12R1_FB2 CAN_F12R1_FB2_Msk
4988#define CAN_F12R1_FB3_Pos (3U)
4989#define CAN_F12R1_FB3_Msk (0x1UL << CAN_F12R1_FB3_Pos)
4990#define CAN_F12R1_FB3 CAN_F12R1_FB3_Msk
4991#define CAN_F12R1_FB4_Pos (4U)
4992#define CAN_F12R1_FB4_Msk (0x1UL << CAN_F12R1_FB4_Pos)
4993#define CAN_F12R1_FB4 CAN_F12R1_FB4_Msk
4994#define CAN_F12R1_FB5_Pos (5U)
4995#define CAN_F12R1_FB5_Msk (0x1UL << CAN_F12R1_FB5_Pos)
4996#define CAN_F12R1_FB5 CAN_F12R1_FB5_Msk
4997#define CAN_F12R1_FB6_Pos (6U)
4998#define CAN_F12R1_FB6_Msk (0x1UL << CAN_F12R1_FB6_Pos)
4999#define CAN_F12R1_FB6 CAN_F12R1_FB6_Msk
5000#define CAN_F12R1_FB7_Pos (7U)
5001#define CAN_F12R1_FB7_Msk (0x1UL << CAN_F12R1_FB7_Pos)
5002#define CAN_F12R1_FB7 CAN_F12R1_FB7_Msk
5003#define CAN_F12R1_FB8_Pos (8U)
5004#define CAN_F12R1_FB8_Msk (0x1UL << CAN_F12R1_FB8_Pos)
5005#define CAN_F12R1_FB8 CAN_F12R1_FB8_Msk
5006#define CAN_F12R1_FB9_Pos (9U)
5007#define CAN_F12R1_FB9_Msk (0x1UL << CAN_F12R1_FB9_Pos)
5008#define CAN_F12R1_FB9 CAN_F12R1_FB9_Msk
5009#define CAN_F12R1_FB10_Pos (10U)
5010#define CAN_F12R1_FB10_Msk (0x1UL << CAN_F12R1_FB10_Pos)
5011#define CAN_F12R1_FB10 CAN_F12R1_FB10_Msk
5012#define CAN_F12R1_FB11_Pos (11U)
5013#define CAN_F12R1_FB11_Msk (0x1UL << CAN_F12R1_FB11_Pos)
5014#define CAN_F12R1_FB11 CAN_F12R1_FB11_Msk
5015#define CAN_F12R1_FB12_Pos (12U)
5016#define CAN_F12R1_FB12_Msk (0x1UL << CAN_F12R1_FB12_Pos)
5017#define CAN_F12R1_FB12 CAN_F12R1_FB12_Msk
5018#define CAN_F12R1_FB13_Pos (13U)
5019#define CAN_F12R1_FB13_Msk (0x1UL << CAN_F12R1_FB13_Pos)
5020#define CAN_F12R1_FB13 CAN_F12R1_FB13_Msk
5021#define CAN_F12R1_FB14_Pos (14U)
5022#define CAN_F12R1_FB14_Msk (0x1UL << CAN_F12R1_FB14_Pos)
5023#define CAN_F12R1_FB14 CAN_F12R1_FB14_Msk
5024#define CAN_F12R1_FB15_Pos (15U)
5025#define CAN_F12R1_FB15_Msk (0x1UL << CAN_F12R1_FB15_Pos)
5026#define CAN_F12R1_FB15 CAN_F12R1_FB15_Msk
5027#define CAN_F12R1_FB16_Pos (16U)
5028#define CAN_F12R1_FB16_Msk (0x1UL << CAN_F12R1_FB16_Pos)
5029#define CAN_F12R1_FB16 CAN_F12R1_FB16_Msk
5030#define CAN_F12R1_FB17_Pos (17U)
5031#define CAN_F12R1_FB17_Msk (0x1UL << CAN_F12R1_FB17_Pos)
5032#define CAN_F12R1_FB17 CAN_F12R1_FB17_Msk
5033#define CAN_F12R1_FB18_Pos (18U)
5034#define CAN_F12R1_FB18_Msk (0x1UL << CAN_F12R1_FB18_Pos)
5035#define CAN_F12R1_FB18 CAN_F12R1_FB18_Msk
5036#define CAN_F12R1_FB19_Pos (19U)
5037#define CAN_F12R1_FB19_Msk (0x1UL << CAN_F12R1_FB19_Pos)
5038#define CAN_F12R1_FB19 CAN_F12R1_FB19_Msk
5039#define CAN_F12R1_FB20_Pos (20U)
5040#define CAN_F12R1_FB20_Msk (0x1UL << CAN_F12R1_FB20_Pos)
5041#define CAN_F12R1_FB20 CAN_F12R1_FB20_Msk
5042#define CAN_F12R1_FB21_Pos (21U)
5043#define CAN_F12R1_FB21_Msk (0x1UL << CAN_F12R1_FB21_Pos)
5044#define CAN_F12R1_FB21 CAN_F12R1_FB21_Msk
5045#define CAN_F12R1_FB22_Pos (22U)
5046#define CAN_F12R1_FB22_Msk (0x1UL << CAN_F12R1_FB22_Pos)
5047#define CAN_F12R1_FB22 CAN_F12R1_FB22_Msk
5048#define CAN_F12R1_FB23_Pos (23U)
5049#define CAN_F12R1_FB23_Msk (0x1UL << CAN_F12R1_FB23_Pos)
5050#define CAN_F12R1_FB23 CAN_F12R1_FB23_Msk
5051#define CAN_F12R1_FB24_Pos (24U)
5052#define CAN_F12R1_FB24_Msk (0x1UL << CAN_F12R1_FB24_Pos)
5053#define CAN_F12R1_FB24 CAN_F12R1_FB24_Msk
5054#define CAN_F12R1_FB25_Pos (25U)
5055#define CAN_F12R1_FB25_Msk (0x1UL << CAN_F12R1_FB25_Pos)
5056#define CAN_F12R1_FB25 CAN_F12R1_FB25_Msk
5057#define CAN_F12R1_FB26_Pos (26U)
5058#define CAN_F12R1_FB26_Msk (0x1UL << CAN_F12R1_FB26_Pos)
5059#define CAN_F12R1_FB26 CAN_F12R1_FB26_Msk
5060#define CAN_F12R1_FB27_Pos (27U)
5061#define CAN_F12R1_FB27_Msk (0x1UL << CAN_F12R1_FB27_Pos)
5062#define CAN_F12R1_FB27 CAN_F12R1_FB27_Msk
5063#define CAN_F12R1_FB28_Pos (28U)
5064#define CAN_F12R1_FB28_Msk (0x1UL << CAN_F12R1_FB28_Pos)
5065#define CAN_F12R1_FB28 CAN_F12R1_FB28_Msk
5066#define CAN_F12R1_FB29_Pos (29U)
5067#define CAN_F12R1_FB29_Msk (0x1UL << CAN_F12R1_FB29_Pos)
5068#define CAN_F12R1_FB29 CAN_F12R1_FB29_Msk
5069#define CAN_F12R1_FB30_Pos (30U)
5070#define CAN_F12R1_FB30_Msk (0x1UL << CAN_F12R1_FB30_Pos)
5071#define CAN_F12R1_FB30 CAN_F12R1_FB30_Msk
5072#define CAN_F12R1_FB31_Pos (31U)
5073#define CAN_F12R1_FB31_Msk (0x1UL << CAN_F12R1_FB31_Pos)
5074#define CAN_F12R1_FB31 CAN_F12R1_FB31_Msk
5076/******************* Bit definition for CAN_F13R1 register ******************/
5077#define CAN_F13R1_FB0_Pos (0U)
5078#define CAN_F13R1_FB0_Msk (0x1UL << CAN_F13R1_FB0_Pos)
5079#define CAN_F13R1_FB0 CAN_F13R1_FB0_Msk
5080#define CAN_F13R1_FB1_Pos (1U)
5081#define CAN_F13R1_FB1_Msk (0x1UL << CAN_F13R1_FB1_Pos)
5082#define CAN_F13R1_FB1 CAN_F13R1_FB1_Msk
5083#define CAN_F13R1_FB2_Pos (2U)
5084#define CAN_F13R1_FB2_Msk (0x1UL << CAN_F13R1_FB2_Pos)
5085#define CAN_F13R1_FB2 CAN_F13R1_FB2_Msk
5086#define CAN_F13R1_FB3_Pos (3U)
5087#define CAN_F13R1_FB3_Msk (0x1UL << CAN_F13R1_FB3_Pos)
5088#define CAN_F13R1_FB3 CAN_F13R1_FB3_Msk
5089#define CAN_F13R1_FB4_Pos (4U)
5090#define CAN_F13R1_FB4_Msk (0x1UL << CAN_F13R1_FB4_Pos)
5091#define CAN_F13R1_FB4 CAN_F13R1_FB4_Msk
5092#define CAN_F13R1_FB5_Pos (5U)
5093#define CAN_F13R1_FB5_Msk (0x1UL << CAN_F13R1_FB5_Pos)
5094#define CAN_F13R1_FB5 CAN_F13R1_FB5_Msk
5095#define CAN_F13R1_FB6_Pos (6U)
5096#define CAN_F13R1_FB6_Msk (0x1UL << CAN_F13R1_FB6_Pos)
5097#define CAN_F13R1_FB6 CAN_F13R1_FB6_Msk
5098#define CAN_F13R1_FB7_Pos (7U)
5099#define CAN_F13R1_FB7_Msk (0x1UL << CAN_F13R1_FB7_Pos)
5100#define CAN_F13R1_FB7 CAN_F13R1_FB7_Msk
5101#define CAN_F13R1_FB8_Pos (8U)
5102#define CAN_F13R1_FB8_Msk (0x1UL << CAN_F13R1_FB8_Pos)
5103#define CAN_F13R1_FB8 CAN_F13R1_FB8_Msk
5104#define CAN_F13R1_FB9_Pos (9U)
5105#define CAN_F13R1_FB9_Msk (0x1UL << CAN_F13R1_FB9_Pos)
5106#define CAN_F13R1_FB9 CAN_F13R1_FB9_Msk
5107#define CAN_F13R1_FB10_Pos (10U)
5108#define CAN_F13R1_FB10_Msk (0x1UL << CAN_F13R1_FB10_Pos)
5109#define CAN_F13R1_FB10 CAN_F13R1_FB10_Msk
5110#define CAN_F13R1_FB11_Pos (11U)
5111#define CAN_F13R1_FB11_Msk (0x1UL << CAN_F13R1_FB11_Pos)
5112#define CAN_F13R1_FB11 CAN_F13R1_FB11_Msk
5113#define CAN_F13R1_FB12_Pos (12U)
5114#define CAN_F13R1_FB12_Msk (0x1UL << CAN_F13R1_FB12_Pos)
5115#define CAN_F13R1_FB12 CAN_F13R1_FB12_Msk
5116#define CAN_F13R1_FB13_Pos (13U)
5117#define CAN_F13R1_FB13_Msk (0x1UL << CAN_F13R1_FB13_Pos)
5118#define CAN_F13R1_FB13 CAN_F13R1_FB13_Msk
5119#define CAN_F13R1_FB14_Pos (14U)
5120#define CAN_F13R1_FB14_Msk (0x1UL << CAN_F13R1_FB14_Pos)
5121#define CAN_F13R1_FB14 CAN_F13R1_FB14_Msk
5122#define CAN_F13R1_FB15_Pos (15U)
5123#define CAN_F13R1_FB15_Msk (0x1UL << CAN_F13R1_FB15_Pos)
5124#define CAN_F13R1_FB15 CAN_F13R1_FB15_Msk
5125#define CAN_F13R1_FB16_Pos (16U)
5126#define CAN_F13R1_FB16_Msk (0x1UL << CAN_F13R1_FB16_Pos)
5127#define CAN_F13R1_FB16 CAN_F13R1_FB16_Msk
5128#define CAN_F13R1_FB17_Pos (17U)
5129#define CAN_F13R1_FB17_Msk (0x1UL << CAN_F13R1_FB17_Pos)
5130#define CAN_F13R1_FB17 CAN_F13R1_FB17_Msk
5131#define CAN_F13R1_FB18_Pos (18U)
5132#define CAN_F13R1_FB18_Msk (0x1UL << CAN_F13R1_FB18_Pos)
5133#define CAN_F13R1_FB18 CAN_F13R1_FB18_Msk
5134#define CAN_F13R1_FB19_Pos (19U)
5135#define CAN_F13R1_FB19_Msk (0x1UL << CAN_F13R1_FB19_Pos)
5136#define CAN_F13R1_FB19 CAN_F13R1_FB19_Msk
5137#define CAN_F13R1_FB20_Pos (20U)
5138#define CAN_F13R1_FB20_Msk (0x1UL << CAN_F13R1_FB20_Pos)
5139#define CAN_F13R1_FB20 CAN_F13R1_FB20_Msk
5140#define CAN_F13R1_FB21_Pos (21U)
5141#define CAN_F13R1_FB21_Msk (0x1UL << CAN_F13R1_FB21_Pos)
5142#define CAN_F13R1_FB21 CAN_F13R1_FB21_Msk
5143#define CAN_F13R1_FB22_Pos (22U)
5144#define CAN_F13R1_FB22_Msk (0x1UL << CAN_F13R1_FB22_Pos)
5145#define CAN_F13R1_FB22 CAN_F13R1_FB22_Msk
5146#define CAN_F13R1_FB23_Pos (23U)
5147#define CAN_F13R1_FB23_Msk (0x1UL << CAN_F13R1_FB23_Pos)
5148#define CAN_F13R1_FB23 CAN_F13R1_FB23_Msk
5149#define CAN_F13R1_FB24_Pos (24U)
5150#define CAN_F13R1_FB24_Msk (0x1UL << CAN_F13R1_FB24_Pos)
5151#define CAN_F13R1_FB24 CAN_F13R1_FB24_Msk
5152#define CAN_F13R1_FB25_Pos (25U)
5153#define CAN_F13R1_FB25_Msk (0x1UL << CAN_F13R1_FB25_Pos)
5154#define CAN_F13R1_FB25 CAN_F13R1_FB25_Msk
5155#define CAN_F13R1_FB26_Pos (26U)
5156#define CAN_F13R1_FB26_Msk (0x1UL << CAN_F13R1_FB26_Pos)
5157#define CAN_F13R1_FB26 CAN_F13R1_FB26_Msk
5158#define CAN_F13R1_FB27_Pos (27U)
5159#define CAN_F13R1_FB27_Msk (0x1UL << CAN_F13R1_FB27_Pos)
5160#define CAN_F13R1_FB27 CAN_F13R1_FB27_Msk
5161#define CAN_F13R1_FB28_Pos (28U)
5162#define CAN_F13R1_FB28_Msk (0x1UL << CAN_F13R1_FB28_Pos)
5163#define CAN_F13R1_FB28 CAN_F13R1_FB28_Msk
5164#define CAN_F13R1_FB29_Pos (29U)
5165#define CAN_F13R1_FB29_Msk (0x1UL << CAN_F13R1_FB29_Pos)
5166#define CAN_F13R1_FB29 CAN_F13R1_FB29_Msk
5167#define CAN_F13R1_FB30_Pos (30U)
5168#define CAN_F13R1_FB30_Msk (0x1UL << CAN_F13R1_FB30_Pos)
5169#define CAN_F13R1_FB30 CAN_F13R1_FB30_Msk
5170#define CAN_F13R1_FB31_Pos (31U)
5171#define CAN_F13R1_FB31_Msk (0x1UL << CAN_F13R1_FB31_Pos)
5172#define CAN_F13R1_FB31 CAN_F13R1_FB31_Msk
5174/******************* Bit definition for CAN_F0R2 register *******************/
5175#define CAN_F0R2_FB0_Pos (0U)
5176#define CAN_F0R2_FB0_Msk (0x1UL << CAN_F0R2_FB0_Pos)
5177#define CAN_F0R2_FB0 CAN_F0R2_FB0_Msk
5178#define CAN_F0R2_FB1_Pos (1U)
5179#define CAN_F0R2_FB1_Msk (0x1UL << CAN_F0R2_FB1_Pos)
5180#define CAN_F0R2_FB1 CAN_F0R2_FB1_Msk
5181#define CAN_F0R2_FB2_Pos (2U)
5182#define CAN_F0R2_FB2_Msk (0x1UL << CAN_F0R2_FB2_Pos)
5183#define CAN_F0R2_FB2 CAN_F0R2_FB2_Msk
5184#define CAN_F0R2_FB3_Pos (3U)
5185#define CAN_F0R2_FB3_Msk (0x1UL << CAN_F0R2_FB3_Pos)
5186#define CAN_F0R2_FB3 CAN_F0R2_FB3_Msk
5187#define CAN_F0R2_FB4_Pos (4U)
5188#define CAN_F0R2_FB4_Msk (0x1UL << CAN_F0R2_FB4_Pos)
5189#define CAN_F0R2_FB4 CAN_F0R2_FB4_Msk
5190#define CAN_F0R2_FB5_Pos (5U)
5191#define CAN_F0R2_FB5_Msk (0x1UL << CAN_F0R2_FB5_Pos)
5192#define CAN_F0R2_FB5 CAN_F0R2_FB5_Msk
5193#define CAN_F0R2_FB6_Pos (6U)
5194#define CAN_F0R2_FB6_Msk (0x1UL << CAN_F0R2_FB6_Pos)
5195#define CAN_F0R2_FB6 CAN_F0R2_FB6_Msk
5196#define CAN_F0R2_FB7_Pos (7U)
5197#define CAN_F0R2_FB7_Msk (0x1UL << CAN_F0R2_FB7_Pos)
5198#define CAN_F0R2_FB7 CAN_F0R2_FB7_Msk
5199#define CAN_F0R2_FB8_Pos (8U)
5200#define CAN_F0R2_FB8_Msk (0x1UL << CAN_F0R2_FB8_Pos)
5201#define CAN_F0R2_FB8 CAN_F0R2_FB8_Msk
5202#define CAN_F0R2_FB9_Pos (9U)
5203#define CAN_F0R2_FB9_Msk (0x1UL << CAN_F0R2_FB9_Pos)
5204#define CAN_F0R2_FB9 CAN_F0R2_FB9_Msk
5205#define CAN_F0R2_FB10_Pos (10U)
5206#define CAN_F0R2_FB10_Msk (0x1UL << CAN_F0R2_FB10_Pos)
5207#define CAN_F0R2_FB10 CAN_F0R2_FB10_Msk
5208#define CAN_F0R2_FB11_Pos (11U)
5209#define CAN_F0R2_FB11_Msk (0x1UL << CAN_F0R2_FB11_Pos)
5210#define CAN_F0R2_FB11 CAN_F0R2_FB11_Msk
5211#define CAN_F0R2_FB12_Pos (12U)
5212#define CAN_F0R2_FB12_Msk (0x1UL << CAN_F0R2_FB12_Pos)
5213#define CAN_F0R2_FB12 CAN_F0R2_FB12_Msk
5214#define CAN_F0R2_FB13_Pos (13U)
5215#define CAN_F0R2_FB13_Msk (0x1UL << CAN_F0R2_FB13_Pos)
5216#define CAN_F0R2_FB13 CAN_F0R2_FB13_Msk
5217#define CAN_F0R2_FB14_Pos (14U)
5218#define CAN_F0R2_FB14_Msk (0x1UL << CAN_F0R2_FB14_Pos)
5219#define CAN_F0R2_FB14 CAN_F0R2_FB14_Msk
5220#define CAN_F0R2_FB15_Pos (15U)
5221#define CAN_F0R2_FB15_Msk (0x1UL << CAN_F0R2_FB15_Pos)
5222#define CAN_F0R2_FB15 CAN_F0R2_FB15_Msk
5223#define CAN_F0R2_FB16_Pos (16U)
5224#define CAN_F0R2_FB16_Msk (0x1UL << CAN_F0R2_FB16_Pos)
5225#define CAN_F0R2_FB16 CAN_F0R2_FB16_Msk
5226#define CAN_F0R2_FB17_Pos (17U)
5227#define CAN_F0R2_FB17_Msk (0x1UL << CAN_F0R2_FB17_Pos)
5228#define CAN_F0R2_FB17 CAN_F0R2_FB17_Msk
5229#define CAN_F0R2_FB18_Pos (18U)
5230#define CAN_F0R2_FB18_Msk (0x1UL << CAN_F0R2_FB18_Pos)
5231#define CAN_F0R2_FB18 CAN_F0R2_FB18_Msk
5232#define CAN_F0R2_FB19_Pos (19U)
5233#define CAN_F0R2_FB19_Msk (0x1UL << CAN_F0R2_FB19_Pos)
5234#define CAN_F0R2_FB19 CAN_F0R2_FB19_Msk
5235#define CAN_F0R2_FB20_Pos (20U)
5236#define CAN_F0R2_FB20_Msk (0x1UL << CAN_F0R2_FB20_Pos)
5237#define CAN_F0R2_FB20 CAN_F0R2_FB20_Msk
5238#define CAN_F0R2_FB21_Pos (21U)
5239#define CAN_F0R2_FB21_Msk (0x1UL << CAN_F0R2_FB21_Pos)
5240#define CAN_F0R2_FB21 CAN_F0R2_FB21_Msk
5241#define CAN_F0R2_FB22_Pos (22U)
5242#define CAN_F0R2_FB22_Msk (0x1UL << CAN_F0R2_FB22_Pos)
5243#define CAN_F0R2_FB22 CAN_F0R2_FB22_Msk
5244#define CAN_F0R2_FB23_Pos (23U)
5245#define CAN_F0R2_FB23_Msk (0x1UL << CAN_F0R2_FB23_Pos)
5246#define CAN_F0R2_FB23 CAN_F0R2_FB23_Msk
5247#define CAN_F0R2_FB24_Pos (24U)
5248#define CAN_F0R2_FB24_Msk (0x1UL << CAN_F0R2_FB24_Pos)
5249#define CAN_F0R2_FB24 CAN_F0R2_FB24_Msk
5250#define CAN_F0R2_FB25_Pos (25U)
5251#define CAN_F0R2_FB25_Msk (0x1UL << CAN_F0R2_FB25_Pos)
5252#define CAN_F0R2_FB25 CAN_F0R2_FB25_Msk
5253#define CAN_F0R2_FB26_Pos (26U)
5254#define CAN_F0R2_FB26_Msk (0x1UL << CAN_F0R2_FB26_Pos)
5255#define CAN_F0R2_FB26 CAN_F0R2_FB26_Msk
5256#define CAN_F0R2_FB27_Pos (27U)
5257#define CAN_F0R2_FB27_Msk (0x1UL << CAN_F0R2_FB27_Pos)
5258#define CAN_F0R2_FB27 CAN_F0R2_FB27_Msk
5259#define CAN_F0R2_FB28_Pos (28U)
5260#define CAN_F0R2_FB28_Msk (0x1UL << CAN_F0R2_FB28_Pos)
5261#define CAN_F0R2_FB28 CAN_F0R2_FB28_Msk
5262#define CAN_F0R2_FB29_Pos (29U)
5263#define CAN_F0R2_FB29_Msk (0x1UL << CAN_F0R2_FB29_Pos)
5264#define CAN_F0R2_FB29 CAN_F0R2_FB29_Msk
5265#define CAN_F0R2_FB30_Pos (30U)
5266#define CAN_F0R2_FB30_Msk (0x1UL << CAN_F0R2_FB30_Pos)
5267#define CAN_F0R2_FB30 CAN_F0R2_FB30_Msk
5268#define CAN_F0R2_FB31_Pos (31U)
5269#define CAN_F0R2_FB31_Msk (0x1UL << CAN_F0R2_FB31_Pos)
5270#define CAN_F0R2_FB31 CAN_F0R2_FB31_Msk
5272/******************* Bit definition for CAN_F1R2 register *******************/
5273#define CAN_F1R2_FB0_Pos (0U)
5274#define CAN_F1R2_FB0_Msk (0x1UL << CAN_F1R2_FB0_Pos)
5275#define CAN_F1R2_FB0 CAN_F1R2_FB0_Msk
5276#define CAN_F1R2_FB1_Pos (1U)
5277#define CAN_F1R2_FB1_Msk (0x1UL << CAN_F1R2_FB1_Pos)
5278#define CAN_F1R2_FB1 CAN_F1R2_FB1_Msk
5279#define CAN_F1R2_FB2_Pos (2U)
5280#define CAN_F1R2_FB2_Msk (0x1UL << CAN_F1R2_FB2_Pos)
5281#define CAN_F1R2_FB2 CAN_F1R2_FB2_Msk
5282#define CAN_F1R2_FB3_Pos (3U)
5283#define CAN_F1R2_FB3_Msk (0x1UL << CAN_F1R2_FB3_Pos)
5284#define CAN_F1R2_FB3 CAN_F1R2_FB3_Msk
5285#define CAN_F1R2_FB4_Pos (4U)
5286#define CAN_F1R2_FB4_Msk (0x1UL << CAN_F1R2_FB4_Pos)
5287#define CAN_F1R2_FB4 CAN_F1R2_FB4_Msk
5288#define CAN_F1R2_FB5_Pos (5U)
5289#define CAN_F1R2_FB5_Msk (0x1UL << CAN_F1R2_FB5_Pos)
5290#define CAN_F1R2_FB5 CAN_F1R2_FB5_Msk
5291#define CAN_F1R2_FB6_Pos (6U)
5292#define CAN_F1R2_FB6_Msk (0x1UL << CAN_F1R2_FB6_Pos)
5293#define CAN_F1R2_FB6 CAN_F1R2_FB6_Msk
5294#define CAN_F1R2_FB7_Pos (7U)
5295#define CAN_F1R2_FB7_Msk (0x1UL << CAN_F1R2_FB7_Pos)
5296#define CAN_F1R2_FB7 CAN_F1R2_FB7_Msk
5297#define CAN_F1R2_FB8_Pos (8U)
5298#define CAN_F1R2_FB8_Msk (0x1UL << CAN_F1R2_FB8_Pos)
5299#define CAN_F1R2_FB8 CAN_F1R2_FB8_Msk
5300#define CAN_F1R2_FB9_Pos (9U)
5301#define CAN_F1R2_FB9_Msk (0x1UL << CAN_F1R2_FB9_Pos)
5302#define CAN_F1R2_FB9 CAN_F1R2_FB9_Msk
5303#define CAN_F1R2_FB10_Pos (10U)
5304#define CAN_F1R2_FB10_Msk (0x1UL << CAN_F1R2_FB10_Pos)
5305#define CAN_F1R2_FB10 CAN_F1R2_FB10_Msk
5306#define CAN_F1R2_FB11_Pos (11U)
5307#define CAN_F1R2_FB11_Msk (0x1UL << CAN_F1R2_FB11_Pos)
5308#define CAN_F1R2_FB11 CAN_F1R2_FB11_Msk
5309#define CAN_F1R2_FB12_Pos (12U)
5310#define CAN_F1R2_FB12_Msk (0x1UL << CAN_F1R2_FB12_Pos)
5311#define CAN_F1R2_FB12 CAN_F1R2_FB12_Msk
5312#define CAN_F1R2_FB13_Pos (13U)
5313#define CAN_F1R2_FB13_Msk (0x1UL << CAN_F1R2_FB13_Pos)
5314#define CAN_F1R2_FB13 CAN_F1R2_FB13_Msk
5315#define CAN_F1R2_FB14_Pos (14U)
5316#define CAN_F1R2_FB14_Msk (0x1UL << CAN_F1R2_FB14_Pos)
5317#define CAN_F1R2_FB14 CAN_F1R2_FB14_Msk
5318#define CAN_F1R2_FB15_Pos (15U)
5319#define CAN_F1R2_FB15_Msk (0x1UL << CAN_F1R2_FB15_Pos)
5320#define CAN_F1R2_FB15 CAN_F1R2_FB15_Msk
5321#define CAN_F1R2_FB16_Pos (16U)
5322#define CAN_F1R2_FB16_Msk (0x1UL << CAN_F1R2_FB16_Pos)
5323#define CAN_F1R2_FB16 CAN_F1R2_FB16_Msk
5324#define CAN_F1R2_FB17_Pos (17U)
5325#define CAN_F1R2_FB17_Msk (0x1UL << CAN_F1R2_FB17_Pos)
5326#define CAN_F1R2_FB17 CAN_F1R2_FB17_Msk
5327#define CAN_F1R2_FB18_Pos (18U)
5328#define CAN_F1R2_FB18_Msk (0x1UL << CAN_F1R2_FB18_Pos)
5329#define CAN_F1R2_FB18 CAN_F1R2_FB18_Msk
5330#define CAN_F1R2_FB19_Pos (19U)
5331#define CAN_F1R2_FB19_Msk (0x1UL << CAN_F1R2_FB19_Pos)
5332#define CAN_F1R2_FB19 CAN_F1R2_FB19_Msk
5333#define CAN_F1R2_FB20_Pos (20U)
5334#define CAN_F1R2_FB20_Msk (0x1UL << CAN_F1R2_FB20_Pos)
5335#define CAN_F1R2_FB20 CAN_F1R2_FB20_Msk
5336#define CAN_F1R2_FB21_Pos (21U)
5337#define CAN_F1R2_FB21_Msk (0x1UL << CAN_F1R2_FB21_Pos)
5338#define CAN_F1R2_FB21 CAN_F1R2_FB21_Msk
5339#define CAN_F1R2_FB22_Pos (22U)
5340#define CAN_F1R2_FB22_Msk (0x1UL << CAN_F1R2_FB22_Pos)
5341#define CAN_F1R2_FB22 CAN_F1R2_FB22_Msk
5342#define CAN_F1R2_FB23_Pos (23U)
5343#define CAN_F1R2_FB23_Msk (0x1UL << CAN_F1R2_FB23_Pos)
5344#define CAN_F1R2_FB23 CAN_F1R2_FB23_Msk
5345#define CAN_F1R2_FB24_Pos (24U)
5346#define CAN_F1R2_FB24_Msk (0x1UL << CAN_F1R2_FB24_Pos)
5347#define CAN_F1R2_FB24 CAN_F1R2_FB24_Msk
5348#define CAN_F1R2_FB25_Pos (25U)
5349#define CAN_F1R2_FB25_Msk (0x1UL << CAN_F1R2_FB25_Pos)
5350#define CAN_F1R2_FB25 CAN_F1R2_FB25_Msk
5351#define CAN_F1R2_FB26_Pos (26U)
5352#define CAN_F1R2_FB26_Msk (0x1UL << CAN_F1R2_FB26_Pos)
5353#define CAN_F1R2_FB26 CAN_F1R2_FB26_Msk
5354#define CAN_F1R2_FB27_Pos (27U)
5355#define CAN_F1R2_FB27_Msk (0x1UL << CAN_F1R2_FB27_Pos)
5356#define CAN_F1R2_FB27 CAN_F1R2_FB27_Msk
5357#define CAN_F1R2_FB28_Pos (28U)
5358#define CAN_F1R2_FB28_Msk (0x1UL << CAN_F1R2_FB28_Pos)
5359#define CAN_F1R2_FB28 CAN_F1R2_FB28_Msk
5360#define CAN_F1R2_FB29_Pos (29U)
5361#define CAN_F1R2_FB29_Msk (0x1UL << CAN_F1R2_FB29_Pos)
5362#define CAN_F1R2_FB29 CAN_F1R2_FB29_Msk
5363#define CAN_F1R2_FB30_Pos (30U)
5364#define CAN_F1R2_FB30_Msk (0x1UL << CAN_F1R2_FB30_Pos)
5365#define CAN_F1R2_FB30 CAN_F1R2_FB30_Msk
5366#define CAN_F1R2_FB31_Pos (31U)
5367#define CAN_F1R2_FB31_Msk (0x1UL << CAN_F1R2_FB31_Pos)
5368#define CAN_F1R2_FB31 CAN_F1R2_FB31_Msk
5370/******************* Bit definition for CAN_F2R2 register *******************/
5371#define CAN_F2R2_FB0_Pos (0U)
5372#define CAN_F2R2_FB0_Msk (0x1UL << CAN_F2R2_FB0_Pos)
5373#define CAN_F2R2_FB0 CAN_F2R2_FB0_Msk
5374#define CAN_F2R2_FB1_Pos (1U)
5375#define CAN_F2R2_FB1_Msk (0x1UL << CAN_F2R2_FB1_Pos)
5376#define CAN_F2R2_FB1 CAN_F2R2_FB1_Msk
5377#define CAN_F2R2_FB2_Pos (2U)
5378#define CAN_F2R2_FB2_Msk (0x1UL << CAN_F2R2_FB2_Pos)
5379#define CAN_F2R2_FB2 CAN_F2R2_FB2_Msk
5380#define CAN_F2R2_FB3_Pos (3U)
5381#define CAN_F2R2_FB3_Msk (0x1UL << CAN_F2R2_FB3_Pos)
5382#define CAN_F2R2_FB3 CAN_F2R2_FB3_Msk
5383#define CAN_F2R2_FB4_Pos (4U)
5384#define CAN_F2R2_FB4_Msk (0x1UL << CAN_F2R2_FB4_Pos)
5385#define CAN_F2R2_FB4 CAN_F2R2_FB4_Msk
5386#define CAN_F2R2_FB5_Pos (5U)
5387#define CAN_F2R2_FB5_Msk (0x1UL << CAN_F2R2_FB5_Pos)
5388#define CAN_F2R2_FB5 CAN_F2R2_FB5_Msk
5389#define CAN_F2R2_FB6_Pos (6U)
5390#define CAN_F2R2_FB6_Msk (0x1UL << CAN_F2R2_FB6_Pos)
5391#define CAN_F2R2_FB6 CAN_F2R2_FB6_Msk
5392#define CAN_F2R2_FB7_Pos (7U)
5393#define CAN_F2R2_FB7_Msk (0x1UL << CAN_F2R2_FB7_Pos)
5394#define CAN_F2R2_FB7 CAN_F2R2_FB7_Msk
5395#define CAN_F2R2_FB8_Pos (8U)
5396#define CAN_F2R2_FB8_Msk (0x1UL << CAN_F2R2_FB8_Pos)
5397#define CAN_F2R2_FB8 CAN_F2R2_FB8_Msk
5398#define CAN_F2R2_FB9_Pos (9U)
5399#define CAN_F2R2_FB9_Msk (0x1UL << CAN_F2R2_FB9_Pos)
5400#define CAN_F2R2_FB9 CAN_F2R2_FB9_Msk
5401#define CAN_F2R2_FB10_Pos (10U)
5402#define CAN_F2R2_FB10_Msk (0x1UL << CAN_F2R2_FB10_Pos)
5403#define CAN_F2R2_FB10 CAN_F2R2_FB10_Msk
5404#define CAN_F2R2_FB11_Pos (11U)
5405#define CAN_F2R2_FB11_Msk (0x1UL << CAN_F2R2_FB11_Pos)
5406#define CAN_F2R2_FB11 CAN_F2R2_FB11_Msk
5407#define CAN_F2R2_FB12_Pos (12U)
5408#define CAN_F2R2_FB12_Msk (0x1UL << CAN_F2R2_FB12_Pos)
5409#define CAN_F2R2_FB12 CAN_F2R2_FB12_Msk
5410#define CAN_F2R2_FB13_Pos (13U)
5411#define CAN_F2R2_FB13_Msk (0x1UL << CAN_F2R2_FB13_Pos)
5412#define CAN_F2R2_FB13 CAN_F2R2_FB13_Msk
5413#define CAN_F2R2_FB14_Pos (14U)
5414#define CAN_F2R2_FB14_Msk (0x1UL << CAN_F2R2_FB14_Pos)
5415#define CAN_F2R2_FB14 CAN_F2R2_FB14_Msk
5416#define CAN_F2R2_FB15_Pos (15U)
5417#define CAN_F2R2_FB15_Msk (0x1UL << CAN_F2R2_FB15_Pos)
5418#define CAN_F2R2_FB15 CAN_F2R2_FB15_Msk
5419#define CAN_F2R2_FB16_Pos (16U)
5420#define CAN_F2R2_FB16_Msk (0x1UL << CAN_F2R2_FB16_Pos)
5421#define CAN_F2R2_FB16 CAN_F2R2_FB16_Msk
5422#define CAN_F2R2_FB17_Pos (17U)
5423#define CAN_F2R2_FB17_Msk (0x1UL << CAN_F2R2_FB17_Pos)
5424#define CAN_F2R2_FB17 CAN_F2R2_FB17_Msk
5425#define CAN_F2R2_FB18_Pos (18U)
5426#define CAN_F2R2_FB18_Msk (0x1UL << CAN_F2R2_FB18_Pos)
5427#define CAN_F2R2_FB18 CAN_F2R2_FB18_Msk
5428#define CAN_F2R2_FB19_Pos (19U)
5429#define CAN_F2R2_FB19_Msk (0x1UL << CAN_F2R2_FB19_Pos)
5430#define CAN_F2R2_FB19 CAN_F2R2_FB19_Msk
5431#define CAN_F2R2_FB20_Pos (20U)
5432#define CAN_F2R2_FB20_Msk (0x1UL << CAN_F2R2_FB20_Pos)
5433#define CAN_F2R2_FB20 CAN_F2R2_FB20_Msk
5434#define CAN_F2R2_FB21_Pos (21U)
5435#define CAN_F2R2_FB21_Msk (0x1UL << CAN_F2R2_FB21_Pos)
5436#define CAN_F2R2_FB21 CAN_F2R2_FB21_Msk
5437#define CAN_F2R2_FB22_Pos (22U)
5438#define CAN_F2R2_FB22_Msk (0x1UL << CAN_F2R2_FB22_Pos)
5439#define CAN_F2R2_FB22 CAN_F2R2_FB22_Msk
5440#define CAN_F2R2_FB23_Pos (23U)
5441#define CAN_F2R2_FB23_Msk (0x1UL << CAN_F2R2_FB23_Pos)
5442#define CAN_F2R2_FB23 CAN_F2R2_FB23_Msk
5443#define CAN_F2R2_FB24_Pos (24U)
5444#define CAN_F2R2_FB24_Msk (0x1UL << CAN_F2R2_FB24_Pos)
5445#define CAN_F2R2_FB24 CAN_F2R2_FB24_Msk
5446#define CAN_F2R2_FB25_Pos (25U)
5447#define CAN_F2R2_FB25_Msk (0x1UL << CAN_F2R2_FB25_Pos)
5448#define CAN_F2R2_FB25 CAN_F2R2_FB25_Msk
5449#define CAN_F2R2_FB26_Pos (26U)
5450#define CAN_F2R2_FB26_Msk (0x1UL << CAN_F2R2_FB26_Pos)
5451#define CAN_F2R2_FB26 CAN_F2R2_FB26_Msk
5452#define CAN_F2R2_FB27_Pos (27U)
5453#define CAN_F2R2_FB27_Msk (0x1UL << CAN_F2R2_FB27_Pos)
5454#define CAN_F2R2_FB27 CAN_F2R2_FB27_Msk
5455#define CAN_F2R2_FB28_Pos (28U)
5456#define CAN_F2R2_FB28_Msk (0x1UL << CAN_F2R2_FB28_Pos)
5457#define CAN_F2R2_FB28 CAN_F2R2_FB28_Msk
5458#define CAN_F2R2_FB29_Pos (29U)
5459#define CAN_F2R2_FB29_Msk (0x1UL << CAN_F2R2_FB29_Pos)
5460#define CAN_F2R2_FB29 CAN_F2R2_FB29_Msk
5461#define CAN_F2R2_FB30_Pos (30U)
5462#define CAN_F2R2_FB30_Msk (0x1UL << CAN_F2R2_FB30_Pos)
5463#define CAN_F2R2_FB30 CAN_F2R2_FB30_Msk
5464#define CAN_F2R2_FB31_Pos (31U)
5465#define CAN_F2R2_FB31_Msk (0x1UL << CAN_F2R2_FB31_Pos)
5466#define CAN_F2R2_FB31 CAN_F2R2_FB31_Msk
5468/******************* Bit definition for CAN_F3R2 register *******************/
5469#define CAN_F3R2_FB0_Pos (0U)
5470#define CAN_F3R2_FB0_Msk (0x1UL << CAN_F3R2_FB0_Pos)
5471#define CAN_F3R2_FB0 CAN_F3R2_FB0_Msk
5472#define CAN_F3R2_FB1_Pos (1U)
5473#define CAN_F3R2_FB1_Msk (0x1UL << CAN_F3R2_FB1_Pos)
5474#define CAN_F3R2_FB1 CAN_F3R2_FB1_Msk
5475#define CAN_F3R2_FB2_Pos (2U)
5476#define CAN_F3R2_FB2_Msk (0x1UL << CAN_F3R2_FB2_Pos)
5477#define CAN_F3R2_FB2 CAN_F3R2_FB2_Msk
5478#define CAN_F3R2_FB3_Pos (3U)
5479#define CAN_F3R2_FB3_Msk (0x1UL << CAN_F3R2_FB3_Pos)
5480#define CAN_F3R2_FB3 CAN_F3R2_FB3_Msk
5481#define CAN_F3R2_FB4_Pos (4U)
5482#define CAN_F3R2_FB4_Msk (0x1UL << CAN_F3R2_FB4_Pos)
5483#define CAN_F3R2_FB4 CAN_F3R2_FB4_Msk
5484#define CAN_F3R2_FB5_Pos (5U)
5485#define CAN_F3R2_FB5_Msk (0x1UL << CAN_F3R2_FB5_Pos)
5486#define CAN_F3R2_FB5 CAN_F3R2_FB5_Msk
5487#define CAN_F3R2_FB6_Pos (6U)
5488#define CAN_F3R2_FB6_Msk (0x1UL << CAN_F3R2_FB6_Pos)
5489#define CAN_F3R2_FB6 CAN_F3R2_FB6_Msk
5490#define CAN_F3R2_FB7_Pos (7U)
5491#define CAN_F3R2_FB7_Msk (0x1UL << CAN_F3R2_FB7_Pos)
5492#define CAN_F3R2_FB7 CAN_F3R2_FB7_Msk
5493#define CAN_F3R2_FB8_Pos (8U)
5494#define CAN_F3R2_FB8_Msk (0x1UL << CAN_F3R2_FB8_Pos)
5495#define CAN_F3R2_FB8 CAN_F3R2_FB8_Msk
5496#define CAN_F3R2_FB9_Pos (9U)
5497#define CAN_F3R2_FB9_Msk (0x1UL << CAN_F3R2_FB9_Pos)
5498#define CAN_F3R2_FB9 CAN_F3R2_FB9_Msk
5499#define CAN_F3R2_FB10_Pos (10U)
5500#define CAN_F3R2_FB10_Msk (0x1UL << CAN_F3R2_FB10_Pos)
5501#define CAN_F3R2_FB10 CAN_F3R2_FB10_Msk
5502#define CAN_F3R2_FB11_Pos (11U)
5503#define CAN_F3R2_FB11_Msk (0x1UL << CAN_F3R2_FB11_Pos)
5504#define CAN_F3R2_FB11 CAN_F3R2_FB11_Msk
5505#define CAN_F3R2_FB12_Pos (12U)
5506#define CAN_F3R2_FB12_Msk (0x1UL << CAN_F3R2_FB12_Pos)
5507#define CAN_F3R2_FB12 CAN_F3R2_FB12_Msk
5508#define CAN_F3R2_FB13_Pos (13U)
5509#define CAN_F3R2_FB13_Msk (0x1UL << CAN_F3R2_FB13_Pos)
5510#define CAN_F3R2_FB13 CAN_F3R2_FB13_Msk
5511#define CAN_F3R2_FB14_Pos (14U)
5512#define CAN_F3R2_FB14_Msk (0x1UL << CAN_F3R2_FB14_Pos)
5513#define CAN_F3R2_FB14 CAN_F3R2_FB14_Msk
5514#define CAN_F3R2_FB15_Pos (15U)
5515#define CAN_F3R2_FB15_Msk (0x1UL << CAN_F3R2_FB15_Pos)
5516#define CAN_F3R2_FB15 CAN_F3R2_FB15_Msk
5517#define CAN_F3R2_FB16_Pos (16U)
5518#define CAN_F3R2_FB16_Msk (0x1UL << CAN_F3R2_FB16_Pos)
5519#define CAN_F3R2_FB16 CAN_F3R2_FB16_Msk
5520#define CAN_F3R2_FB17_Pos (17U)
5521#define CAN_F3R2_FB17_Msk (0x1UL << CAN_F3R2_FB17_Pos)
5522#define CAN_F3R2_FB17 CAN_F3R2_FB17_Msk
5523#define CAN_F3R2_FB18_Pos (18U)
5524#define CAN_F3R2_FB18_Msk (0x1UL << CAN_F3R2_FB18_Pos)
5525#define CAN_F3R2_FB18 CAN_F3R2_FB18_Msk
5526#define CAN_F3R2_FB19_Pos (19U)
5527#define CAN_F3R2_FB19_Msk (0x1UL << CAN_F3R2_FB19_Pos)
5528#define CAN_F3R2_FB19 CAN_F3R2_FB19_Msk
5529#define CAN_F3R2_FB20_Pos (20U)
5530#define CAN_F3R2_FB20_Msk (0x1UL << CAN_F3R2_FB20_Pos)
5531#define CAN_F3R2_FB20 CAN_F3R2_FB20_Msk
5532#define CAN_F3R2_FB21_Pos (21U)
5533#define CAN_F3R2_FB21_Msk (0x1UL << CAN_F3R2_FB21_Pos)
5534#define CAN_F3R2_FB21 CAN_F3R2_FB21_Msk
5535#define CAN_F3R2_FB22_Pos (22U)
5536#define CAN_F3R2_FB22_Msk (0x1UL << CAN_F3R2_FB22_Pos)
5537#define CAN_F3R2_FB22 CAN_F3R2_FB22_Msk
5538#define CAN_F3R2_FB23_Pos (23U)
5539#define CAN_F3R2_FB23_Msk (0x1UL << CAN_F3R2_FB23_Pos)
5540#define CAN_F3R2_FB23 CAN_F3R2_FB23_Msk
5541#define CAN_F3R2_FB24_Pos (24U)
5542#define CAN_F3R2_FB24_Msk (0x1UL << CAN_F3R2_FB24_Pos)
5543#define CAN_F3R2_FB24 CAN_F3R2_FB24_Msk
5544#define CAN_F3R2_FB25_Pos (25U)
5545#define CAN_F3R2_FB25_Msk (0x1UL << CAN_F3R2_FB25_Pos)
5546#define CAN_F3R2_FB25 CAN_F3R2_FB25_Msk
5547#define CAN_F3R2_FB26_Pos (26U)
5548#define CAN_F3R2_FB26_Msk (0x1UL << CAN_F3R2_FB26_Pos)
5549#define CAN_F3R2_FB26 CAN_F3R2_FB26_Msk
5550#define CAN_F3R2_FB27_Pos (27U)
5551#define CAN_F3R2_FB27_Msk (0x1UL << CAN_F3R2_FB27_Pos)
5552#define CAN_F3R2_FB27 CAN_F3R2_FB27_Msk
5553#define CAN_F3R2_FB28_Pos (28U)
5554#define CAN_F3R2_FB28_Msk (0x1UL << CAN_F3R2_FB28_Pos)
5555#define CAN_F3R2_FB28 CAN_F3R2_FB28_Msk
5556#define CAN_F3R2_FB29_Pos (29U)
5557#define CAN_F3R2_FB29_Msk (0x1UL << CAN_F3R2_FB29_Pos)
5558#define CAN_F3R2_FB29 CAN_F3R2_FB29_Msk
5559#define CAN_F3R2_FB30_Pos (30U)
5560#define CAN_F3R2_FB30_Msk (0x1UL << CAN_F3R2_FB30_Pos)
5561#define CAN_F3R2_FB30 CAN_F3R2_FB30_Msk
5562#define CAN_F3R2_FB31_Pos (31U)
5563#define CAN_F3R2_FB31_Msk (0x1UL << CAN_F3R2_FB31_Pos)
5564#define CAN_F3R2_FB31 CAN_F3R2_FB31_Msk
5566/******************* Bit definition for CAN_F4R2 register *******************/
5567#define CAN_F4R2_FB0_Pos (0U)
5568#define CAN_F4R2_FB0_Msk (0x1UL << CAN_F4R2_FB0_Pos)
5569#define CAN_F4R2_FB0 CAN_F4R2_FB0_Msk
5570#define CAN_F4R2_FB1_Pos (1U)
5571#define CAN_F4R2_FB1_Msk (0x1UL << CAN_F4R2_FB1_Pos)
5572#define CAN_F4R2_FB1 CAN_F4R2_FB1_Msk
5573#define CAN_F4R2_FB2_Pos (2U)
5574#define CAN_F4R2_FB2_Msk (0x1UL << CAN_F4R2_FB2_Pos)
5575#define CAN_F4R2_FB2 CAN_F4R2_FB2_Msk
5576#define CAN_F4R2_FB3_Pos (3U)
5577#define CAN_F4R2_FB3_Msk (0x1UL << CAN_F4R2_FB3_Pos)
5578#define CAN_F4R2_FB3 CAN_F4R2_FB3_Msk
5579#define CAN_F4R2_FB4_Pos (4U)
5580#define CAN_F4R2_FB4_Msk (0x1UL << CAN_F4R2_FB4_Pos)
5581#define CAN_F4R2_FB4 CAN_F4R2_FB4_Msk
5582#define CAN_F4R2_FB5_Pos (5U)
5583#define CAN_F4R2_FB5_Msk (0x1UL << CAN_F4R2_FB5_Pos)
5584#define CAN_F4R2_FB5 CAN_F4R2_FB5_Msk
5585#define CAN_F4R2_FB6_Pos (6U)
5586#define CAN_F4R2_FB6_Msk (0x1UL << CAN_F4R2_FB6_Pos)
5587#define CAN_F4R2_FB6 CAN_F4R2_FB6_Msk
5588#define CAN_F4R2_FB7_Pos (7U)
5589#define CAN_F4R2_FB7_Msk (0x1UL << CAN_F4R2_FB7_Pos)
5590#define CAN_F4R2_FB7 CAN_F4R2_FB7_Msk
5591#define CAN_F4R2_FB8_Pos (8U)
5592#define CAN_F4R2_FB8_Msk (0x1UL << CAN_F4R2_FB8_Pos)
5593#define CAN_F4R2_FB8 CAN_F4R2_FB8_Msk
5594#define CAN_F4R2_FB9_Pos (9U)
5595#define CAN_F4R2_FB9_Msk (0x1UL << CAN_F4R2_FB9_Pos)
5596#define CAN_F4R2_FB9 CAN_F4R2_FB9_Msk
5597#define CAN_F4R2_FB10_Pos (10U)
5598#define CAN_F4R2_FB10_Msk (0x1UL << CAN_F4R2_FB10_Pos)
5599#define CAN_F4R2_FB10 CAN_F4R2_FB10_Msk
5600#define CAN_F4R2_FB11_Pos (11U)
5601#define CAN_F4R2_FB11_Msk (0x1UL << CAN_F4R2_FB11_Pos)
5602#define CAN_F4R2_FB11 CAN_F4R2_FB11_Msk
5603#define CAN_F4R2_FB12_Pos (12U)
5604#define CAN_F4R2_FB12_Msk (0x1UL << CAN_F4R2_FB12_Pos)
5605#define CAN_F4R2_FB12 CAN_F4R2_FB12_Msk
5606#define CAN_F4R2_FB13_Pos (13U)
5607#define CAN_F4R2_FB13_Msk (0x1UL << CAN_F4R2_FB13_Pos)
5608#define CAN_F4R2_FB13 CAN_F4R2_FB13_Msk
5609#define CAN_F4R2_FB14_Pos (14U)
5610#define CAN_F4R2_FB14_Msk (0x1UL << CAN_F4R2_FB14_Pos)
5611#define CAN_F4R2_FB14 CAN_F4R2_FB14_Msk
5612#define CAN_F4R2_FB15_Pos (15U)
5613#define CAN_F4R2_FB15_Msk (0x1UL << CAN_F4R2_FB15_Pos)
5614#define CAN_F4R2_FB15 CAN_F4R2_FB15_Msk
5615#define CAN_F4R2_FB16_Pos (16U)
5616#define CAN_F4R2_FB16_Msk (0x1UL << CAN_F4R2_FB16_Pos)
5617#define CAN_F4R2_FB16 CAN_F4R2_FB16_Msk
5618#define CAN_F4R2_FB17_Pos (17U)
5619#define CAN_F4R2_FB17_Msk (0x1UL << CAN_F4R2_FB17_Pos)
5620#define CAN_F4R2_FB17 CAN_F4R2_FB17_Msk
5621#define CAN_F4R2_FB18_Pos (18U)
5622#define CAN_F4R2_FB18_Msk (0x1UL << CAN_F4R2_FB18_Pos)
5623#define CAN_F4R2_FB18 CAN_F4R2_FB18_Msk
5624#define CAN_F4R2_FB19_Pos (19U)
5625#define CAN_F4R2_FB19_Msk (0x1UL << CAN_F4R2_FB19_Pos)
5626#define CAN_F4R2_FB19 CAN_F4R2_FB19_Msk
5627#define CAN_F4R2_FB20_Pos (20U)
5628#define CAN_F4R2_FB20_Msk (0x1UL << CAN_F4R2_FB20_Pos)
5629#define CAN_F4R2_FB20 CAN_F4R2_FB20_Msk
5630#define CAN_F4R2_FB21_Pos (21U)
5631#define CAN_F4R2_FB21_Msk (0x1UL << CAN_F4R2_FB21_Pos)
5632#define CAN_F4R2_FB21 CAN_F4R2_FB21_Msk
5633#define CAN_F4R2_FB22_Pos (22U)
5634#define CAN_F4R2_FB22_Msk (0x1UL << CAN_F4R2_FB22_Pos)
5635#define CAN_F4R2_FB22 CAN_F4R2_FB22_Msk
5636#define CAN_F4R2_FB23_Pos (23U)
5637#define CAN_F4R2_FB23_Msk (0x1UL << CAN_F4R2_FB23_Pos)
5638#define CAN_F4R2_FB23 CAN_F4R2_FB23_Msk
5639#define CAN_F4R2_FB24_Pos (24U)
5640#define CAN_F4R2_FB24_Msk (0x1UL << CAN_F4R2_FB24_Pos)
5641#define CAN_F4R2_FB24 CAN_F4R2_FB24_Msk
5642#define CAN_F4R2_FB25_Pos (25U)
5643#define CAN_F4R2_FB25_Msk (0x1UL << CAN_F4R2_FB25_Pos)
5644#define CAN_F4R2_FB25 CAN_F4R2_FB25_Msk
5645#define CAN_F4R2_FB26_Pos (26U)
5646#define CAN_F4R2_FB26_Msk (0x1UL << CAN_F4R2_FB26_Pos)
5647#define CAN_F4R2_FB26 CAN_F4R2_FB26_Msk
5648#define CAN_F4R2_FB27_Pos (27U)
5649#define CAN_F4R2_FB27_Msk (0x1UL << CAN_F4R2_FB27_Pos)
5650#define CAN_F4R2_FB27 CAN_F4R2_FB27_Msk
5651#define CAN_F4R2_FB28_Pos (28U)
5652#define CAN_F4R2_FB28_Msk (0x1UL << CAN_F4R2_FB28_Pos)
5653#define CAN_F4R2_FB28 CAN_F4R2_FB28_Msk
5654#define CAN_F4R2_FB29_Pos (29U)
5655#define CAN_F4R2_FB29_Msk (0x1UL << CAN_F4R2_FB29_Pos)
5656#define CAN_F4R2_FB29 CAN_F4R2_FB29_Msk
5657#define CAN_F4R2_FB30_Pos (30U)
5658#define CAN_F4R2_FB30_Msk (0x1UL << CAN_F4R2_FB30_Pos)
5659#define CAN_F4R2_FB30 CAN_F4R2_FB30_Msk
5660#define CAN_F4R2_FB31_Pos (31U)
5661#define CAN_F4R2_FB31_Msk (0x1UL << CAN_F4R2_FB31_Pos)
5662#define CAN_F4R2_FB31 CAN_F4R2_FB31_Msk
5664/******************* Bit definition for CAN_F5R2 register *******************/
5665#define CAN_F5R2_FB0_Pos (0U)
5666#define CAN_F5R2_FB0_Msk (0x1UL << CAN_F5R2_FB0_Pos)
5667#define CAN_F5R2_FB0 CAN_F5R2_FB0_Msk
5668#define CAN_F5R2_FB1_Pos (1U)
5669#define CAN_F5R2_FB1_Msk (0x1UL << CAN_F5R2_FB1_Pos)
5670#define CAN_F5R2_FB1 CAN_F5R2_FB1_Msk
5671#define CAN_F5R2_FB2_Pos (2U)
5672#define CAN_F5R2_FB2_Msk (0x1UL << CAN_F5R2_FB2_Pos)
5673#define CAN_F5R2_FB2 CAN_F5R2_FB2_Msk
5674#define CAN_F5R2_FB3_Pos (3U)
5675#define CAN_F5R2_FB3_Msk (0x1UL << CAN_F5R2_FB3_Pos)
5676#define CAN_F5R2_FB3 CAN_F5R2_FB3_Msk
5677#define CAN_F5R2_FB4_Pos (4U)
5678#define CAN_F5R2_FB4_Msk (0x1UL << CAN_F5R2_FB4_Pos)
5679#define CAN_F5R2_FB4 CAN_F5R2_FB4_Msk
5680#define CAN_F5R2_FB5_Pos (5U)
5681#define CAN_F5R2_FB5_Msk (0x1UL << CAN_F5R2_FB5_Pos)
5682#define CAN_F5R2_FB5 CAN_F5R2_FB5_Msk
5683#define CAN_F5R2_FB6_Pos (6U)
5684#define CAN_F5R2_FB6_Msk (0x1UL << CAN_F5R2_FB6_Pos)
5685#define CAN_F5R2_FB6 CAN_F5R2_FB6_Msk
5686#define CAN_F5R2_FB7_Pos (7U)
5687#define CAN_F5R2_FB7_Msk (0x1UL << CAN_F5R2_FB7_Pos)
5688#define CAN_F5R2_FB7 CAN_F5R2_FB7_Msk
5689#define CAN_F5R2_FB8_Pos (8U)
5690#define CAN_F5R2_FB8_Msk (0x1UL << CAN_F5R2_FB8_Pos)
5691#define CAN_F5R2_FB8 CAN_F5R2_FB8_Msk
5692#define CAN_F5R2_FB9_Pos (9U)
5693#define CAN_F5R2_FB9_Msk (0x1UL << CAN_F5R2_FB9_Pos)
5694#define CAN_F5R2_FB9 CAN_F5R2_FB9_Msk
5695#define CAN_F5R2_FB10_Pos (10U)
5696#define CAN_F5R2_FB10_Msk (0x1UL << CAN_F5R2_FB10_Pos)
5697#define CAN_F5R2_FB10 CAN_F5R2_FB10_Msk
5698#define CAN_F5R2_FB11_Pos (11U)
5699#define CAN_F5R2_FB11_Msk (0x1UL << CAN_F5R2_FB11_Pos)
5700#define CAN_F5R2_FB11 CAN_F5R2_FB11_Msk
5701#define CAN_F5R2_FB12_Pos (12U)
5702#define CAN_F5R2_FB12_Msk (0x1UL << CAN_F5R2_FB12_Pos)
5703#define CAN_F5R2_FB12 CAN_F5R2_FB12_Msk
5704#define CAN_F5R2_FB13_Pos (13U)
5705#define CAN_F5R2_FB13_Msk (0x1UL << CAN_F5R2_FB13_Pos)
5706#define CAN_F5R2_FB13 CAN_F5R2_FB13_Msk
5707#define CAN_F5R2_FB14_Pos (14U)
5708#define CAN_F5R2_FB14_Msk (0x1UL << CAN_F5R2_FB14_Pos)
5709#define CAN_F5R2_FB14 CAN_F5R2_FB14_Msk
5710#define CAN_F5R2_FB15_Pos (15U)
5711#define CAN_F5R2_FB15_Msk (0x1UL << CAN_F5R2_FB15_Pos)
5712#define CAN_F5R2_FB15 CAN_F5R2_FB15_Msk
5713#define CAN_F5R2_FB16_Pos (16U)
5714#define CAN_F5R2_FB16_Msk (0x1UL << CAN_F5R2_FB16_Pos)
5715#define CAN_F5R2_FB16 CAN_F5R2_FB16_Msk
5716#define CAN_F5R2_FB17_Pos (17U)
5717#define CAN_F5R2_FB17_Msk (0x1UL << CAN_F5R2_FB17_Pos)
5718#define CAN_F5R2_FB17 CAN_F5R2_FB17_Msk
5719#define CAN_F5R2_FB18_Pos (18U)
5720#define CAN_F5R2_FB18_Msk (0x1UL << CAN_F5R2_FB18_Pos)
5721#define CAN_F5R2_FB18 CAN_F5R2_FB18_Msk
5722#define CAN_F5R2_FB19_Pos (19U)
5723#define CAN_F5R2_FB19_Msk (0x1UL << CAN_F5R2_FB19_Pos)
5724#define CAN_F5R2_FB19 CAN_F5R2_FB19_Msk
5725#define CAN_F5R2_FB20_Pos (20U)
5726#define CAN_F5R2_FB20_Msk (0x1UL << CAN_F5R2_FB20_Pos)
5727#define CAN_F5R2_FB20 CAN_F5R2_FB20_Msk
5728#define CAN_F5R2_FB21_Pos (21U)
5729#define CAN_F5R2_FB21_Msk (0x1UL << CAN_F5R2_FB21_Pos)
5730#define CAN_F5R2_FB21 CAN_F5R2_FB21_Msk
5731#define CAN_F5R2_FB22_Pos (22U)
5732#define CAN_F5R2_FB22_Msk (0x1UL << CAN_F5R2_FB22_Pos)
5733#define CAN_F5R2_FB22 CAN_F5R2_FB22_Msk
5734#define CAN_F5R2_FB23_Pos (23U)
5735#define CAN_F5R2_FB23_Msk (0x1UL << CAN_F5R2_FB23_Pos)
5736#define CAN_F5R2_FB23 CAN_F5R2_FB23_Msk
5737#define CAN_F5R2_FB24_Pos (24U)
5738#define CAN_F5R2_FB24_Msk (0x1UL << CAN_F5R2_FB24_Pos)
5739#define CAN_F5R2_FB24 CAN_F5R2_FB24_Msk
5740#define CAN_F5R2_FB25_Pos (25U)
5741#define CAN_F5R2_FB25_Msk (0x1UL << CAN_F5R2_FB25_Pos)
5742#define CAN_F5R2_FB25 CAN_F5R2_FB25_Msk
5743#define CAN_F5R2_FB26_Pos (26U)
5744#define CAN_F5R2_FB26_Msk (0x1UL << CAN_F5R2_FB26_Pos)
5745#define CAN_F5R2_FB26 CAN_F5R2_FB26_Msk
5746#define CAN_F5R2_FB27_Pos (27U)
5747#define CAN_F5R2_FB27_Msk (0x1UL << CAN_F5R2_FB27_Pos)
5748#define CAN_F5R2_FB27 CAN_F5R2_FB27_Msk
5749#define CAN_F5R2_FB28_Pos (28U)
5750#define CAN_F5R2_FB28_Msk (0x1UL << CAN_F5R2_FB28_Pos)
5751#define CAN_F5R2_FB28 CAN_F5R2_FB28_Msk
5752#define CAN_F5R2_FB29_Pos (29U)
5753#define CAN_F5R2_FB29_Msk (0x1UL << CAN_F5R2_FB29_Pos)
5754#define CAN_F5R2_FB29 CAN_F5R2_FB29_Msk
5755#define CAN_F5R2_FB30_Pos (30U)
5756#define CAN_F5R2_FB30_Msk (0x1UL << CAN_F5R2_FB30_Pos)
5757#define CAN_F5R2_FB30 CAN_F5R2_FB30_Msk
5758#define CAN_F5R2_FB31_Pos (31U)
5759#define CAN_F5R2_FB31_Msk (0x1UL << CAN_F5R2_FB31_Pos)
5760#define CAN_F5R2_FB31 CAN_F5R2_FB31_Msk
5762/******************* Bit definition for CAN_F6R2 register *******************/
5763#define CAN_F6R2_FB0_Pos (0U)
5764#define CAN_F6R2_FB0_Msk (0x1UL << CAN_F6R2_FB0_Pos)
5765#define CAN_F6R2_FB0 CAN_F6R2_FB0_Msk
5766#define CAN_F6R2_FB1_Pos (1U)
5767#define CAN_F6R2_FB1_Msk (0x1UL << CAN_F6R2_FB1_Pos)
5768#define CAN_F6R2_FB1 CAN_F6R2_FB1_Msk
5769#define CAN_F6R2_FB2_Pos (2U)
5770#define CAN_F6R2_FB2_Msk (0x1UL << CAN_F6R2_FB2_Pos)
5771#define CAN_F6R2_FB2 CAN_F6R2_FB2_Msk
5772#define CAN_F6R2_FB3_Pos (3U)
5773#define CAN_F6R2_FB3_Msk (0x1UL << CAN_F6R2_FB3_Pos)
5774#define CAN_F6R2_FB3 CAN_F6R2_FB3_Msk
5775#define CAN_F6R2_FB4_Pos (4U)
5776#define CAN_F6R2_FB4_Msk (0x1UL << CAN_F6R2_FB4_Pos)
5777#define CAN_F6R2_FB4 CAN_F6R2_FB4_Msk
5778#define CAN_F6R2_FB5_Pos (5U)
5779#define CAN_F6R2_FB5_Msk (0x1UL << CAN_F6R2_FB5_Pos)
5780#define CAN_F6R2_FB5 CAN_F6R2_FB5_Msk
5781#define CAN_F6R2_FB6_Pos (6U)
5782#define CAN_F6R2_FB6_Msk (0x1UL << CAN_F6R2_FB6_Pos)
5783#define CAN_F6R2_FB6 CAN_F6R2_FB6_Msk
5784#define CAN_F6R2_FB7_Pos (7U)
5785#define CAN_F6R2_FB7_Msk (0x1UL << CAN_F6R2_FB7_Pos)
5786#define CAN_F6R2_FB7 CAN_F6R2_FB7_Msk
5787#define CAN_F6R2_FB8_Pos (8U)
5788#define CAN_F6R2_FB8_Msk (0x1UL << CAN_F6R2_FB8_Pos)
5789#define CAN_F6R2_FB8 CAN_F6R2_FB8_Msk
5790#define CAN_F6R2_FB9_Pos (9U)
5791#define CAN_F6R2_FB9_Msk (0x1UL << CAN_F6R2_FB9_Pos)
5792#define CAN_F6R2_FB9 CAN_F6R2_FB9_Msk
5793#define CAN_F6R2_FB10_Pos (10U)
5794#define CAN_F6R2_FB10_Msk (0x1UL << CAN_F6R2_FB10_Pos)
5795#define CAN_F6R2_FB10 CAN_F6R2_FB10_Msk
5796#define CAN_F6R2_FB11_Pos (11U)
5797#define CAN_F6R2_FB11_Msk (0x1UL << CAN_F6R2_FB11_Pos)
5798#define CAN_F6R2_FB11 CAN_F6R2_FB11_Msk
5799#define CAN_F6R2_FB12_Pos (12U)
5800#define CAN_F6R2_FB12_Msk (0x1UL << CAN_F6R2_FB12_Pos)
5801#define CAN_F6R2_FB12 CAN_F6R2_FB12_Msk
5802#define CAN_F6R2_FB13_Pos (13U)
5803#define CAN_F6R2_FB13_Msk (0x1UL << CAN_F6R2_FB13_Pos)
5804#define CAN_F6R2_FB13 CAN_F6R2_FB13_Msk
5805#define CAN_F6R2_FB14_Pos (14U)
5806#define CAN_F6R2_FB14_Msk (0x1UL << CAN_F6R2_FB14_Pos)
5807#define CAN_F6R2_FB14 CAN_F6R2_FB14_Msk
5808#define CAN_F6R2_FB15_Pos (15U)
5809#define CAN_F6R2_FB15_Msk (0x1UL << CAN_F6R2_FB15_Pos)
5810#define CAN_F6R2_FB15 CAN_F6R2_FB15_Msk
5811#define CAN_F6R2_FB16_Pos (16U)
5812#define CAN_F6R2_FB16_Msk (0x1UL << CAN_F6R2_FB16_Pos)
5813#define CAN_F6R2_FB16 CAN_F6R2_FB16_Msk
5814#define CAN_F6R2_FB17_Pos (17U)
5815#define CAN_F6R2_FB17_Msk (0x1UL << CAN_F6R2_FB17_Pos)
5816#define CAN_F6R2_FB17 CAN_F6R2_FB17_Msk
5817#define CAN_F6R2_FB18_Pos (18U)
5818#define CAN_F6R2_FB18_Msk (0x1UL << CAN_F6R2_FB18_Pos)
5819#define CAN_F6R2_FB18 CAN_F6R2_FB18_Msk
5820#define CAN_F6R2_FB19_Pos (19U)
5821#define CAN_F6R2_FB19_Msk (0x1UL << CAN_F6R2_FB19_Pos)
5822#define CAN_F6R2_FB19 CAN_F6R2_FB19_Msk
5823#define CAN_F6R2_FB20_Pos (20U)
5824#define CAN_F6R2_FB20_Msk (0x1UL << CAN_F6R2_FB20_Pos)
5825#define CAN_F6R2_FB20 CAN_F6R2_FB20_Msk
5826#define CAN_F6R2_FB21_Pos (21U)
5827#define CAN_F6R2_FB21_Msk (0x1UL << CAN_F6R2_FB21_Pos)
5828#define CAN_F6R2_FB21 CAN_F6R2_FB21_Msk
5829#define CAN_F6R2_FB22_Pos (22U)
5830#define CAN_F6R2_FB22_Msk (0x1UL << CAN_F6R2_FB22_Pos)
5831#define CAN_F6R2_FB22 CAN_F6R2_FB22_Msk
5832#define CAN_F6R2_FB23_Pos (23U)
5833#define CAN_F6R2_FB23_Msk (0x1UL << CAN_F6R2_FB23_Pos)
5834#define CAN_F6R2_FB23 CAN_F6R2_FB23_Msk
5835#define CAN_F6R2_FB24_Pos (24U)
5836#define CAN_F6R2_FB24_Msk (0x1UL << CAN_F6R2_FB24_Pos)
5837#define CAN_F6R2_FB24 CAN_F6R2_FB24_Msk
5838#define CAN_F6R2_FB25_Pos (25U)
5839#define CAN_F6R2_FB25_Msk (0x1UL << CAN_F6R2_FB25_Pos)
5840#define CAN_F6R2_FB25 CAN_F6R2_FB25_Msk
5841#define CAN_F6R2_FB26_Pos (26U)
5842#define CAN_F6R2_FB26_Msk (0x1UL << CAN_F6R2_FB26_Pos)
5843#define CAN_F6R2_FB26 CAN_F6R2_FB26_Msk
5844#define CAN_F6R2_FB27_Pos (27U)
5845#define CAN_F6R2_FB27_Msk (0x1UL << CAN_F6R2_FB27_Pos)
5846#define CAN_F6R2_FB27 CAN_F6R2_FB27_Msk
5847#define CAN_F6R2_FB28_Pos (28U)
5848#define CAN_F6R2_FB28_Msk (0x1UL << CAN_F6R2_FB28_Pos)
5849#define CAN_F6R2_FB28 CAN_F6R2_FB28_Msk
5850#define CAN_F6R2_FB29_Pos (29U)
5851#define CAN_F6R2_FB29_Msk (0x1UL << CAN_F6R2_FB29_Pos)
5852#define CAN_F6R2_FB29 CAN_F6R2_FB29_Msk
5853#define CAN_F6R2_FB30_Pos (30U)
5854#define CAN_F6R2_FB30_Msk (0x1UL << CAN_F6R2_FB30_Pos)
5855#define CAN_F6R2_FB30 CAN_F6R2_FB30_Msk
5856#define CAN_F6R2_FB31_Pos (31U)
5857#define CAN_F6R2_FB31_Msk (0x1UL << CAN_F6R2_FB31_Pos)
5858#define CAN_F6R2_FB31 CAN_F6R2_FB31_Msk
5860/******************* Bit definition for CAN_F7R2 register *******************/
5861#define CAN_F7R2_FB0_Pos (0U)
5862#define CAN_F7R2_FB0_Msk (0x1UL << CAN_F7R2_FB0_Pos)
5863#define CAN_F7R2_FB0 CAN_F7R2_FB0_Msk
5864#define CAN_F7R2_FB1_Pos (1U)
5865#define CAN_F7R2_FB1_Msk (0x1UL << CAN_F7R2_FB1_Pos)
5866#define CAN_F7R2_FB1 CAN_F7R2_FB1_Msk
5867#define CAN_F7R2_FB2_Pos (2U)
5868#define CAN_F7R2_FB2_Msk (0x1UL << CAN_F7R2_FB2_Pos)
5869#define CAN_F7R2_FB2 CAN_F7R2_FB2_Msk
5870#define CAN_F7R2_FB3_Pos (3U)
5871#define CAN_F7R2_FB3_Msk (0x1UL << CAN_F7R2_FB3_Pos)
5872#define CAN_F7R2_FB3 CAN_F7R2_FB3_Msk
5873#define CAN_F7R2_FB4_Pos (4U)
5874#define CAN_F7R2_FB4_Msk (0x1UL << CAN_F7R2_FB4_Pos)
5875#define CAN_F7R2_FB4 CAN_F7R2_FB4_Msk
5876#define CAN_F7R2_FB5_Pos (5U)
5877#define CAN_F7R2_FB5_Msk (0x1UL << CAN_F7R2_FB5_Pos)
5878#define CAN_F7R2_FB5 CAN_F7R2_FB5_Msk
5879#define CAN_F7R2_FB6_Pos (6U)
5880#define CAN_F7R2_FB6_Msk (0x1UL << CAN_F7R2_FB6_Pos)
5881#define CAN_F7R2_FB6 CAN_F7R2_FB6_Msk
5882#define CAN_F7R2_FB7_Pos (7U)
5883#define CAN_F7R2_FB7_Msk (0x1UL << CAN_F7R2_FB7_Pos)
5884#define CAN_F7R2_FB7 CAN_F7R2_FB7_Msk
5885#define CAN_F7R2_FB8_Pos (8U)
5886#define CAN_F7R2_FB8_Msk (0x1UL << CAN_F7R2_FB8_Pos)
5887#define CAN_F7R2_FB8 CAN_F7R2_FB8_Msk
5888#define CAN_F7R2_FB9_Pos (9U)
5889#define CAN_F7R2_FB9_Msk (0x1UL << CAN_F7R2_FB9_Pos)
5890#define CAN_F7R2_FB9 CAN_F7R2_FB9_Msk
5891#define CAN_F7R2_FB10_Pos (10U)
5892#define CAN_F7R2_FB10_Msk (0x1UL << CAN_F7R2_FB10_Pos)
5893#define CAN_F7R2_FB10 CAN_F7R2_FB10_Msk
5894#define CAN_F7R2_FB11_Pos (11U)
5895#define CAN_F7R2_FB11_Msk (0x1UL << CAN_F7R2_FB11_Pos)
5896#define CAN_F7R2_FB11 CAN_F7R2_FB11_Msk
5897#define CAN_F7R2_FB12_Pos (12U)
5898#define CAN_F7R2_FB12_Msk (0x1UL << CAN_F7R2_FB12_Pos)
5899#define CAN_F7R2_FB12 CAN_F7R2_FB12_Msk
5900#define CAN_F7R2_FB13_Pos (13U)
5901#define CAN_F7R2_FB13_Msk (0x1UL << CAN_F7R2_FB13_Pos)
5902#define CAN_F7R2_FB13 CAN_F7R2_FB13_Msk
5903#define CAN_F7R2_FB14_Pos (14U)
5904#define CAN_F7R2_FB14_Msk (0x1UL << CAN_F7R2_FB14_Pos)
5905#define CAN_F7R2_FB14 CAN_F7R2_FB14_Msk
5906#define CAN_F7R2_FB15_Pos (15U)
5907#define CAN_F7R2_FB15_Msk (0x1UL << CAN_F7R2_FB15_Pos)
5908#define CAN_F7R2_FB15 CAN_F7R2_FB15_Msk
5909#define CAN_F7R2_FB16_Pos (16U)
5910#define CAN_F7R2_FB16_Msk (0x1UL << CAN_F7R2_FB16_Pos)
5911#define CAN_F7R2_FB16 CAN_F7R2_FB16_Msk
5912#define CAN_F7R2_FB17_Pos (17U)
5913#define CAN_F7R2_FB17_Msk (0x1UL << CAN_F7R2_FB17_Pos)
5914#define CAN_F7R2_FB17 CAN_F7R2_FB17_Msk
5915#define CAN_F7R2_FB18_Pos (18U)
5916#define CAN_F7R2_FB18_Msk (0x1UL << CAN_F7R2_FB18_Pos)
5917#define CAN_F7R2_FB18 CAN_F7R2_FB18_Msk
5918#define CAN_F7R2_FB19_Pos (19U)
5919#define CAN_F7R2_FB19_Msk (0x1UL << CAN_F7R2_FB19_Pos)
5920#define CAN_F7R2_FB19 CAN_F7R2_FB19_Msk
5921#define CAN_F7R2_FB20_Pos (20U)
5922#define CAN_F7R2_FB20_Msk (0x1UL << CAN_F7R2_FB20_Pos)
5923#define CAN_F7R2_FB20 CAN_F7R2_FB20_Msk
5924#define CAN_F7R2_FB21_Pos (21U)
5925#define CAN_F7R2_FB21_Msk (0x1UL << CAN_F7R2_FB21_Pos)
5926#define CAN_F7R2_FB21 CAN_F7R2_FB21_Msk
5927#define CAN_F7R2_FB22_Pos (22U)
5928#define CAN_F7R2_FB22_Msk (0x1UL << CAN_F7R2_FB22_Pos)
5929#define CAN_F7R2_FB22 CAN_F7R2_FB22_Msk
5930#define CAN_F7R2_FB23_Pos (23U)
5931#define CAN_F7R2_FB23_Msk (0x1UL << CAN_F7R2_FB23_Pos)
5932#define CAN_F7R2_FB23 CAN_F7R2_FB23_Msk
5933#define CAN_F7R2_FB24_Pos (24U)
5934#define CAN_F7R2_FB24_Msk (0x1UL << CAN_F7R2_FB24_Pos)
5935#define CAN_F7R2_FB24 CAN_F7R2_FB24_Msk
5936#define CAN_F7R2_FB25_Pos (25U)
5937#define CAN_F7R2_FB25_Msk (0x1UL << CAN_F7R2_FB25_Pos)
5938#define CAN_F7R2_FB25 CAN_F7R2_FB25_Msk
5939#define CAN_F7R2_FB26_Pos (26U)
5940#define CAN_F7R2_FB26_Msk (0x1UL << CAN_F7R2_FB26_Pos)
5941#define CAN_F7R2_FB26 CAN_F7R2_FB26_Msk
5942#define CAN_F7R2_FB27_Pos (27U)
5943#define CAN_F7R2_FB27_Msk (0x1UL << CAN_F7R2_FB27_Pos)
5944#define CAN_F7R2_FB27 CAN_F7R2_FB27_Msk
5945#define CAN_F7R2_FB28_Pos (28U)
5946#define CAN_F7R2_FB28_Msk (0x1UL << CAN_F7R2_FB28_Pos)
5947#define CAN_F7R2_FB28 CAN_F7R2_FB28_Msk
5948#define CAN_F7R2_FB29_Pos (29U)
5949#define CAN_F7R2_FB29_Msk (0x1UL << CAN_F7R2_FB29_Pos)
5950#define CAN_F7R2_FB29 CAN_F7R2_FB29_Msk
5951#define CAN_F7R2_FB30_Pos (30U)
5952#define CAN_F7R2_FB30_Msk (0x1UL << CAN_F7R2_FB30_Pos)
5953#define CAN_F7R2_FB30 CAN_F7R2_FB30_Msk
5954#define CAN_F7R2_FB31_Pos (31U)
5955#define CAN_F7R2_FB31_Msk (0x1UL << CAN_F7R2_FB31_Pos)
5956#define CAN_F7R2_FB31 CAN_F7R2_FB31_Msk
5958/******************* Bit definition for CAN_F8R2 register *******************/
5959#define CAN_F8R2_FB0_Pos (0U)
5960#define CAN_F8R2_FB0_Msk (0x1UL << CAN_F8R2_FB0_Pos)
5961#define CAN_F8R2_FB0 CAN_F8R2_FB0_Msk
5962#define CAN_F8R2_FB1_Pos (1U)
5963#define CAN_F8R2_FB1_Msk (0x1UL << CAN_F8R2_FB1_Pos)
5964#define CAN_F8R2_FB1 CAN_F8R2_FB1_Msk
5965#define CAN_F8R2_FB2_Pos (2U)
5966#define CAN_F8R2_FB2_Msk (0x1UL << CAN_F8R2_FB2_Pos)
5967#define CAN_F8R2_FB2 CAN_F8R2_FB2_Msk
5968#define CAN_F8R2_FB3_Pos (3U)
5969#define CAN_F8R2_FB3_Msk (0x1UL << CAN_F8R2_FB3_Pos)
5970#define CAN_F8R2_FB3 CAN_F8R2_FB3_Msk
5971#define CAN_F8R2_FB4_Pos (4U)
5972#define CAN_F8R2_FB4_Msk (0x1UL << CAN_F8R2_FB4_Pos)
5973#define CAN_F8R2_FB4 CAN_F8R2_FB4_Msk
5974#define CAN_F8R2_FB5_Pos (5U)
5975#define CAN_F8R2_FB5_Msk (0x1UL << CAN_F8R2_FB5_Pos)
5976#define CAN_F8R2_FB5 CAN_F8R2_FB5_Msk
5977#define CAN_F8R2_FB6_Pos (6U)
5978#define CAN_F8R2_FB6_Msk (0x1UL << CAN_F8R2_FB6_Pos)
5979#define CAN_F8R2_FB6 CAN_F8R2_FB6_Msk
5980#define CAN_F8R2_FB7_Pos (7U)
5981#define CAN_F8R2_FB7_Msk (0x1UL << CAN_F8R2_FB7_Pos)
5982#define CAN_F8R2_FB7 CAN_F8R2_FB7_Msk
5983#define CAN_F8R2_FB8_Pos (8U)
5984#define CAN_F8R2_FB8_Msk (0x1UL << CAN_F8R2_FB8_Pos)
5985#define CAN_F8R2_FB8 CAN_F8R2_FB8_Msk
5986#define CAN_F8R2_FB9_Pos (9U)
5987#define CAN_F8R2_FB9_Msk (0x1UL << CAN_F8R2_FB9_Pos)
5988#define CAN_F8R2_FB9 CAN_F8R2_FB9_Msk
5989#define CAN_F8R2_FB10_Pos (10U)
5990#define CAN_F8R2_FB10_Msk (0x1UL << CAN_F8R2_FB10_Pos)
5991#define CAN_F8R2_FB10 CAN_F8R2_FB10_Msk
5992#define CAN_F8R2_FB11_Pos (11U)
5993#define CAN_F8R2_FB11_Msk (0x1UL << CAN_F8R2_FB11_Pos)
5994#define CAN_F8R2_FB11 CAN_F8R2_FB11_Msk
5995#define CAN_F8R2_FB12_Pos (12U)
5996#define CAN_F8R2_FB12_Msk (0x1UL << CAN_F8R2_FB12_Pos)
5997#define CAN_F8R2_FB12 CAN_F8R2_FB12_Msk
5998#define CAN_F8R2_FB13_Pos (13U)
5999#define CAN_F8R2_FB13_Msk (0x1UL << CAN_F8R2_FB13_Pos)
6000#define CAN_F8R2_FB13 CAN_F8R2_FB13_Msk
6001#define CAN_F8R2_FB14_Pos (14U)
6002#define CAN_F8R2_FB14_Msk (0x1UL << CAN_F8R2_FB14_Pos)
6003#define CAN_F8R2_FB14 CAN_F8R2_FB14_Msk
6004#define CAN_F8R2_FB15_Pos (15U)
6005#define CAN_F8R2_FB15_Msk (0x1UL << CAN_F8R2_FB15_Pos)
6006#define CAN_F8R2_FB15 CAN_F8R2_FB15_Msk
6007#define CAN_F8R2_FB16_Pos (16U)
6008#define CAN_F8R2_FB16_Msk (0x1UL << CAN_F8R2_FB16_Pos)
6009#define CAN_F8R2_FB16 CAN_F8R2_FB16_Msk
6010#define CAN_F8R2_FB17_Pos (17U)
6011#define CAN_F8R2_FB17_Msk (0x1UL << CAN_F8R2_FB17_Pos)
6012#define CAN_F8R2_FB17 CAN_F8R2_FB17_Msk
6013#define CAN_F8R2_FB18_Pos (18U)
6014#define CAN_F8R2_FB18_Msk (0x1UL << CAN_F8R2_FB18_Pos)
6015#define CAN_F8R2_FB18 CAN_F8R2_FB18_Msk
6016#define CAN_F8R2_FB19_Pos (19U)
6017#define CAN_F8R2_FB19_Msk (0x1UL << CAN_F8R2_FB19_Pos)
6018#define CAN_F8R2_FB19 CAN_F8R2_FB19_Msk
6019#define CAN_F8R2_FB20_Pos (20U)
6020#define CAN_F8R2_FB20_Msk (0x1UL << CAN_F8R2_FB20_Pos)
6021#define CAN_F8R2_FB20 CAN_F8R2_FB20_Msk
6022#define CAN_F8R2_FB21_Pos (21U)
6023#define CAN_F8R2_FB21_Msk (0x1UL << CAN_F8R2_FB21_Pos)
6024#define CAN_F8R2_FB21 CAN_F8R2_FB21_Msk
6025#define CAN_F8R2_FB22_Pos (22U)
6026#define CAN_F8R2_FB22_Msk (0x1UL << CAN_F8R2_FB22_Pos)
6027#define CAN_F8R2_FB22 CAN_F8R2_FB22_Msk
6028#define CAN_F8R2_FB23_Pos (23U)
6029#define CAN_F8R2_FB23_Msk (0x1UL << CAN_F8R2_FB23_Pos)
6030#define CAN_F8R2_FB23 CAN_F8R2_FB23_Msk
6031#define CAN_F8R2_FB24_Pos (24U)
6032#define CAN_F8R2_FB24_Msk (0x1UL << CAN_F8R2_FB24_Pos)
6033#define CAN_F8R2_FB24 CAN_F8R2_FB24_Msk
6034#define CAN_F8R2_FB25_Pos (25U)
6035#define CAN_F8R2_FB25_Msk (0x1UL << CAN_F8R2_FB25_Pos)
6036#define CAN_F8R2_FB25 CAN_F8R2_FB25_Msk
6037#define CAN_F8R2_FB26_Pos (26U)
6038#define CAN_F8R2_FB26_Msk (0x1UL << CAN_F8R2_FB26_Pos)
6039#define CAN_F8R2_FB26 CAN_F8R2_FB26_Msk
6040#define CAN_F8R2_FB27_Pos (27U)
6041#define CAN_F8R2_FB27_Msk (0x1UL << CAN_F8R2_FB27_Pos)
6042#define CAN_F8R2_FB27 CAN_F8R2_FB27_Msk
6043#define CAN_F8R2_FB28_Pos (28U)
6044#define CAN_F8R2_FB28_Msk (0x1UL << CAN_F8R2_FB28_Pos)
6045#define CAN_F8R2_FB28 CAN_F8R2_FB28_Msk
6046#define CAN_F8R2_FB29_Pos (29U)
6047#define CAN_F8R2_FB29_Msk (0x1UL << CAN_F8R2_FB29_Pos)
6048#define CAN_F8R2_FB29 CAN_F8R2_FB29_Msk
6049#define CAN_F8R2_FB30_Pos (30U)
6050#define CAN_F8R2_FB30_Msk (0x1UL << CAN_F8R2_FB30_Pos)
6051#define CAN_F8R2_FB30 CAN_F8R2_FB30_Msk
6052#define CAN_F8R2_FB31_Pos (31U)
6053#define CAN_F8R2_FB31_Msk (0x1UL << CAN_F8R2_FB31_Pos)
6054#define CAN_F8R2_FB31 CAN_F8R2_FB31_Msk
6056/******************* Bit definition for CAN_F9R2 register *******************/
6057#define CAN_F9R2_FB0_Pos (0U)
6058#define CAN_F9R2_FB0_Msk (0x1UL << CAN_F9R2_FB0_Pos)
6059#define CAN_F9R2_FB0 CAN_F9R2_FB0_Msk
6060#define CAN_F9R2_FB1_Pos (1U)
6061#define CAN_F9R2_FB1_Msk (0x1UL << CAN_F9R2_FB1_Pos)
6062#define CAN_F9R2_FB1 CAN_F9R2_FB1_Msk
6063#define CAN_F9R2_FB2_Pos (2U)
6064#define CAN_F9R2_FB2_Msk (0x1UL << CAN_F9R2_FB2_Pos)
6065#define CAN_F9R2_FB2 CAN_F9R2_FB2_Msk
6066#define CAN_F9R2_FB3_Pos (3U)
6067#define CAN_F9R2_FB3_Msk (0x1UL << CAN_F9R2_FB3_Pos)
6068#define CAN_F9R2_FB3 CAN_F9R2_FB3_Msk
6069#define CAN_F9R2_FB4_Pos (4U)
6070#define CAN_F9R2_FB4_Msk (0x1UL << CAN_F9R2_FB4_Pos)
6071#define CAN_F9R2_FB4 CAN_F9R2_FB4_Msk
6072#define CAN_F9R2_FB5_Pos (5U)
6073#define CAN_F9R2_FB5_Msk (0x1UL << CAN_F9R2_FB5_Pos)
6074#define CAN_F9R2_FB5 CAN_F9R2_FB5_Msk
6075#define CAN_F9R2_FB6_Pos (6U)
6076#define CAN_F9R2_FB6_Msk (0x1UL << CAN_F9R2_FB6_Pos)
6077#define CAN_F9R2_FB6 CAN_F9R2_FB6_Msk
6078#define CAN_F9R2_FB7_Pos (7U)
6079#define CAN_F9R2_FB7_Msk (0x1UL << CAN_F9R2_FB7_Pos)
6080#define CAN_F9R2_FB7 CAN_F9R2_FB7_Msk
6081#define CAN_F9R2_FB8_Pos (8U)
6082#define CAN_F9R2_FB8_Msk (0x1UL << CAN_F9R2_FB8_Pos)
6083#define CAN_F9R2_FB8 CAN_F9R2_FB8_Msk
6084#define CAN_F9R2_FB9_Pos (9U)
6085#define CAN_F9R2_FB9_Msk (0x1UL << CAN_F9R2_FB9_Pos)
6086#define CAN_F9R2_FB9 CAN_F9R2_FB9_Msk
6087#define CAN_F9R2_FB10_Pos (10U)
6088#define CAN_F9R2_FB10_Msk (0x1UL << CAN_F9R2_FB10_Pos)
6089#define CAN_F9R2_FB10 CAN_F9R2_FB10_Msk
6090#define CAN_F9R2_FB11_Pos (11U)
6091#define CAN_F9R2_FB11_Msk (0x1UL << CAN_F9R2_FB11_Pos)
6092#define CAN_F9R2_FB11 CAN_F9R2_FB11_Msk
6093#define CAN_F9R2_FB12_Pos (12U)
6094#define CAN_F9R2_FB12_Msk (0x1UL << CAN_F9R2_FB12_Pos)
6095#define CAN_F9R2_FB12 CAN_F9R2_FB12_Msk
6096#define CAN_F9R2_FB13_Pos (13U)
6097#define CAN_F9R2_FB13_Msk (0x1UL << CAN_F9R2_FB13_Pos)
6098#define CAN_F9R2_FB13 CAN_F9R2_FB13_Msk
6099#define CAN_F9R2_FB14_Pos (14U)
6100#define CAN_F9R2_FB14_Msk (0x1UL << CAN_F9R2_FB14_Pos)
6101#define CAN_F9R2_FB14 CAN_F9R2_FB14_Msk
6102#define CAN_F9R2_FB15_Pos (15U)
6103#define CAN_F9R2_FB15_Msk (0x1UL << CAN_F9R2_FB15_Pos)
6104#define CAN_F9R2_FB15 CAN_F9R2_FB15_Msk
6105#define CAN_F9R2_FB16_Pos (16U)
6106#define CAN_F9R2_FB16_Msk (0x1UL << CAN_F9R2_FB16_Pos)
6107#define CAN_F9R2_FB16 CAN_F9R2_FB16_Msk
6108#define CAN_F9R2_FB17_Pos (17U)
6109#define CAN_F9R2_FB17_Msk (0x1UL << CAN_F9R2_FB17_Pos)
6110#define CAN_F9R2_FB17 CAN_F9R2_FB17_Msk
6111#define CAN_F9R2_FB18_Pos (18U)
6112#define CAN_F9R2_FB18_Msk (0x1UL << CAN_F9R2_FB18_Pos)
6113#define CAN_F9R2_FB18 CAN_F9R2_FB18_Msk
6114#define CAN_F9R2_FB19_Pos (19U)
6115#define CAN_F9R2_FB19_Msk (0x1UL << CAN_F9R2_FB19_Pos)
6116#define CAN_F9R2_FB19 CAN_F9R2_FB19_Msk
6117#define CAN_F9R2_FB20_Pos (20U)
6118#define CAN_F9R2_FB20_Msk (0x1UL << CAN_F9R2_FB20_Pos)
6119#define CAN_F9R2_FB20 CAN_F9R2_FB20_Msk
6120#define CAN_F9R2_FB21_Pos (21U)
6121#define CAN_F9R2_FB21_Msk (0x1UL << CAN_F9R2_FB21_Pos)
6122#define CAN_F9R2_FB21 CAN_F9R2_FB21_Msk
6123#define CAN_F9R2_FB22_Pos (22U)
6124#define CAN_F9R2_FB22_Msk (0x1UL << CAN_F9R2_FB22_Pos)
6125#define CAN_F9R2_FB22 CAN_F9R2_FB22_Msk
6126#define CAN_F9R2_FB23_Pos (23U)
6127#define CAN_F9R2_FB23_Msk (0x1UL << CAN_F9R2_FB23_Pos)
6128#define CAN_F9R2_FB23 CAN_F9R2_FB23_Msk
6129#define CAN_F9R2_FB24_Pos (24U)
6130#define CAN_F9R2_FB24_Msk (0x1UL << CAN_F9R2_FB24_Pos)
6131#define CAN_F9R2_FB24 CAN_F9R2_FB24_Msk
6132#define CAN_F9R2_FB25_Pos (25U)
6133#define CAN_F9R2_FB25_Msk (0x1UL << CAN_F9R2_FB25_Pos)
6134#define CAN_F9R2_FB25 CAN_F9R2_FB25_Msk
6135#define CAN_F9R2_FB26_Pos (26U)
6136#define CAN_F9R2_FB26_Msk (0x1UL << CAN_F9R2_FB26_Pos)
6137#define CAN_F9R2_FB26 CAN_F9R2_FB26_Msk
6138#define CAN_F9R2_FB27_Pos (27U)
6139#define CAN_F9R2_FB27_Msk (0x1UL << CAN_F9R2_FB27_Pos)
6140#define CAN_F9R2_FB27 CAN_F9R2_FB27_Msk
6141#define CAN_F9R2_FB28_Pos (28U)
6142#define CAN_F9R2_FB28_Msk (0x1UL << CAN_F9R2_FB28_Pos)
6143#define CAN_F9R2_FB28 CAN_F9R2_FB28_Msk
6144#define CAN_F9R2_FB29_Pos (29U)
6145#define CAN_F9R2_FB29_Msk (0x1UL << CAN_F9R2_FB29_Pos)
6146#define CAN_F9R2_FB29 CAN_F9R2_FB29_Msk
6147#define CAN_F9R2_FB30_Pos (30U)
6148#define CAN_F9R2_FB30_Msk (0x1UL << CAN_F9R2_FB30_Pos)
6149#define CAN_F9R2_FB30 CAN_F9R2_FB30_Msk
6150#define CAN_F9R2_FB31_Pos (31U)
6151#define CAN_F9R2_FB31_Msk (0x1UL << CAN_F9R2_FB31_Pos)
6152#define CAN_F9R2_FB31 CAN_F9R2_FB31_Msk
6154/******************* Bit definition for CAN_F10R2 register ******************/
6155#define CAN_F10R2_FB0_Pos (0U)
6156#define CAN_F10R2_FB0_Msk (0x1UL << CAN_F10R2_FB0_Pos)
6157#define CAN_F10R2_FB0 CAN_F10R2_FB0_Msk
6158#define CAN_F10R2_FB1_Pos (1U)
6159#define CAN_F10R2_FB1_Msk (0x1UL << CAN_F10R2_FB1_Pos)
6160#define CAN_F10R2_FB1 CAN_F10R2_FB1_Msk
6161#define CAN_F10R2_FB2_Pos (2U)
6162#define CAN_F10R2_FB2_Msk (0x1UL << CAN_F10R2_FB2_Pos)
6163#define CAN_F10R2_FB2 CAN_F10R2_FB2_Msk
6164#define CAN_F10R2_FB3_Pos (3U)
6165#define CAN_F10R2_FB3_Msk (0x1UL << CAN_F10R2_FB3_Pos)
6166#define CAN_F10R2_FB3 CAN_F10R2_FB3_Msk
6167#define CAN_F10R2_FB4_Pos (4U)
6168#define CAN_F10R2_FB4_Msk (0x1UL << CAN_F10R2_FB4_Pos)
6169#define CAN_F10R2_FB4 CAN_F10R2_FB4_Msk
6170#define CAN_F10R2_FB5_Pos (5U)
6171#define CAN_F10R2_FB5_Msk (0x1UL << CAN_F10R2_FB5_Pos)
6172#define CAN_F10R2_FB5 CAN_F10R2_FB5_Msk
6173#define CAN_F10R2_FB6_Pos (6U)
6174#define CAN_F10R2_FB6_Msk (0x1UL << CAN_F10R2_FB6_Pos)
6175#define CAN_F10R2_FB6 CAN_F10R2_FB6_Msk
6176#define CAN_F10R2_FB7_Pos (7U)
6177#define CAN_F10R2_FB7_Msk (0x1UL << CAN_F10R2_FB7_Pos)
6178#define CAN_F10R2_FB7 CAN_F10R2_FB7_Msk
6179#define CAN_F10R2_FB8_Pos (8U)
6180#define CAN_F10R2_FB8_Msk (0x1UL << CAN_F10R2_FB8_Pos)
6181#define CAN_F10R2_FB8 CAN_F10R2_FB8_Msk
6182#define CAN_F10R2_FB9_Pos (9U)
6183#define CAN_F10R2_FB9_Msk (0x1UL << CAN_F10R2_FB9_Pos)
6184#define CAN_F10R2_FB9 CAN_F10R2_FB9_Msk
6185#define CAN_F10R2_FB10_Pos (10U)
6186#define CAN_F10R2_FB10_Msk (0x1UL << CAN_F10R2_FB10_Pos)
6187#define CAN_F10R2_FB10 CAN_F10R2_FB10_Msk
6188#define CAN_F10R2_FB11_Pos (11U)
6189#define CAN_F10R2_FB11_Msk (0x1UL << CAN_F10R2_FB11_Pos)
6190#define CAN_F10R2_FB11 CAN_F10R2_FB11_Msk
6191#define CAN_F10R2_FB12_Pos (12U)
6192#define CAN_F10R2_FB12_Msk (0x1UL << CAN_F10R2_FB12_Pos)
6193#define CAN_F10R2_FB12 CAN_F10R2_FB12_Msk
6194#define CAN_F10R2_FB13_Pos (13U)
6195#define CAN_F10R2_FB13_Msk (0x1UL << CAN_F10R2_FB13_Pos)
6196#define CAN_F10R2_FB13 CAN_F10R2_FB13_Msk
6197#define CAN_F10R2_FB14_Pos (14U)
6198#define CAN_F10R2_FB14_Msk (0x1UL << CAN_F10R2_FB14_Pos)
6199#define CAN_F10R2_FB14 CAN_F10R2_FB14_Msk
6200#define CAN_F10R2_FB15_Pos (15U)
6201#define CAN_F10R2_FB15_Msk (0x1UL << CAN_F10R2_FB15_Pos)
6202#define CAN_F10R2_FB15 CAN_F10R2_FB15_Msk
6203#define CAN_F10R2_FB16_Pos (16U)
6204#define CAN_F10R2_FB16_Msk (0x1UL << CAN_F10R2_FB16_Pos)
6205#define CAN_F10R2_FB16 CAN_F10R2_FB16_Msk
6206#define CAN_F10R2_FB17_Pos (17U)
6207#define CAN_F10R2_FB17_Msk (0x1UL << CAN_F10R2_FB17_Pos)
6208#define CAN_F10R2_FB17 CAN_F10R2_FB17_Msk
6209#define CAN_F10R2_FB18_Pos (18U)
6210#define CAN_F10R2_FB18_Msk (0x1UL << CAN_F10R2_FB18_Pos)
6211#define CAN_F10R2_FB18 CAN_F10R2_FB18_Msk
6212#define CAN_F10R2_FB19_Pos (19U)
6213#define CAN_F10R2_FB19_Msk (0x1UL << CAN_F10R2_FB19_Pos)
6214#define CAN_F10R2_FB19 CAN_F10R2_FB19_Msk
6215#define CAN_F10R2_FB20_Pos (20U)
6216#define CAN_F10R2_FB20_Msk (0x1UL << CAN_F10R2_FB20_Pos)
6217#define CAN_F10R2_FB20 CAN_F10R2_FB20_Msk
6218#define CAN_F10R2_FB21_Pos (21U)
6219#define CAN_F10R2_FB21_Msk (0x1UL << CAN_F10R2_FB21_Pos)
6220#define CAN_F10R2_FB21 CAN_F10R2_FB21_Msk
6221#define CAN_F10R2_FB22_Pos (22U)
6222#define CAN_F10R2_FB22_Msk (0x1UL << CAN_F10R2_FB22_Pos)
6223#define CAN_F10R2_FB22 CAN_F10R2_FB22_Msk
6224#define CAN_F10R2_FB23_Pos (23U)
6225#define CAN_F10R2_FB23_Msk (0x1UL << CAN_F10R2_FB23_Pos)
6226#define CAN_F10R2_FB23 CAN_F10R2_FB23_Msk
6227#define CAN_F10R2_FB24_Pos (24U)
6228#define CAN_F10R2_FB24_Msk (0x1UL << CAN_F10R2_FB24_Pos)
6229#define CAN_F10R2_FB24 CAN_F10R2_FB24_Msk
6230#define CAN_F10R2_FB25_Pos (25U)
6231#define CAN_F10R2_FB25_Msk (0x1UL << CAN_F10R2_FB25_Pos)
6232#define CAN_F10R2_FB25 CAN_F10R2_FB25_Msk
6233#define CAN_F10R2_FB26_Pos (26U)
6234#define CAN_F10R2_FB26_Msk (0x1UL << CAN_F10R2_FB26_Pos)
6235#define CAN_F10R2_FB26 CAN_F10R2_FB26_Msk
6236#define CAN_F10R2_FB27_Pos (27U)
6237#define CAN_F10R2_FB27_Msk (0x1UL << CAN_F10R2_FB27_Pos)
6238#define CAN_F10R2_FB27 CAN_F10R2_FB27_Msk
6239#define CAN_F10R2_FB28_Pos (28U)
6240#define CAN_F10R2_FB28_Msk (0x1UL << CAN_F10R2_FB28_Pos)
6241#define CAN_F10R2_FB28 CAN_F10R2_FB28_Msk
6242#define CAN_F10R2_FB29_Pos (29U)
6243#define CAN_F10R2_FB29_Msk (0x1UL << CAN_F10R2_FB29_Pos)
6244#define CAN_F10R2_FB29 CAN_F10R2_FB29_Msk
6245#define CAN_F10R2_FB30_Pos (30U)
6246#define CAN_F10R2_FB30_Msk (0x1UL << CAN_F10R2_FB30_Pos)
6247#define CAN_F10R2_FB30 CAN_F10R2_FB30_Msk
6248#define CAN_F10R2_FB31_Pos (31U)
6249#define CAN_F10R2_FB31_Msk (0x1UL << CAN_F10R2_FB31_Pos)
6250#define CAN_F10R2_FB31 CAN_F10R2_FB31_Msk
6252/******************* Bit definition for CAN_F11R2 register ******************/
6253#define CAN_F11R2_FB0_Pos (0U)
6254#define CAN_F11R2_FB0_Msk (0x1UL << CAN_F11R2_FB0_Pos)
6255#define CAN_F11R2_FB0 CAN_F11R2_FB0_Msk
6256#define CAN_F11R2_FB1_Pos (1U)
6257#define CAN_F11R2_FB1_Msk (0x1UL << CAN_F11R2_FB1_Pos)
6258#define CAN_F11R2_FB1 CAN_F11R2_FB1_Msk
6259#define CAN_F11R2_FB2_Pos (2U)
6260#define CAN_F11R2_FB2_Msk (0x1UL << CAN_F11R2_FB2_Pos)
6261#define CAN_F11R2_FB2 CAN_F11R2_FB2_Msk
6262#define CAN_F11R2_FB3_Pos (3U)
6263#define CAN_F11R2_FB3_Msk (0x1UL << CAN_F11R2_FB3_Pos)
6264#define CAN_F11R2_FB3 CAN_F11R2_FB3_Msk
6265#define CAN_F11R2_FB4_Pos (4U)
6266#define CAN_F11R2_FB4_Msk (0x1UL << CAN_F11R2_FB4_Pos)
6267#define CAN_F11R2_FB4 CAN_F11R2_FB4_Msk
6268#define CAN_F11R2_FB5_Pos (5U)
6269#define CAN_F11R2_FB5_Msk (0x1UL << CAN_F11R2_FB5_Pos)
6270#define CAN_F11R2_FB5 CAN_F11R2_FB5_Msk
6271#define CAN_F11R2_FB6_Pos (6U)
6272#define CAN_F11R2_FB6_Msk (0x1UL << CAN_F11R2_FB6_Pos)
6273#define CAN_F11R2_FB6 CAN_F11R2_FB6_Msk
6274#define CAN_F11R2_FB7_Pos (7U)
6275#define CAN_F11R2_FB7_Msk (0x1UL << CAN_F11R2_FB7_Pos)
6276#define CAN_F11R2_FB7 CAN_F11R2_FB7_Msk
6277#define CAN_F11R2_FB8_Pos (8U)
6278#define CAN_F11R2_FB8_Msk (0x1UL << CAN_F11R2_FB8_Pos)
6279#define CAN_F11R2_FB8 CAN_F11R2_FB8_Msk
6280#define CAN_F11R2_FB9_Pos (9U)
6281#define CAN_F11R2_FB9_Msk (0x1UL << CAN_F11R2_FB9_Pos)
6282#define CAN_F11R2_FB9 CAN_F11R2_FB9_Msk
6283#define CAN_F11R2_FB10_Pos (10U)
6284#define CAN_F11R2_FB10_Msk (0x1UL << CAN_F11R2_FB10_Pos)
6285#define CAN_F11R2_FB10 CAN_F11R2_FB10_Msk
6286#define CAN_F11R2_FB11_Pos (11U)
6287#define CAN_F11R2_FB11_Msk (0x1UL << CAN_F11R2_FB11_Pos)
6288#define CAN_F11R2_FB11 CAN_F11R2_FB11_Msk
6289#define CAN_F11R2_FB12_Pos (12U)
6290#define CAN_F11R2_FB12_Msk (0x1UL << CAN_F11R2_FB12_Pos)
6291#define CAN_F11R2_FB12 CAN_F11R2_FB12_Msk
6292#define CAN_F11R2_FB13_Pos (13U)
6293#define CAN_F11R2_FB13_Msk (0x1UL << CAN_F11R2_FB13_Pos)
6294#define CAN_F11R2_FB13 CAN_F11R2_FB13_Msk
6295#define CAN_F11R2_FB14_Pos (14U)
6296#define CAN_F11R2_FB14_Msk (0x1UL << CAN_F11R2_FB14_Pos)
6297#define CAN_F11R2_FB14 CAN_F11R2_FB14_Msk
6298#define CAN_F11R2_FB15_Pos (15U)
6299#define CAN_F11R2_FB15_Msk (0x1UL << CAN_F11R2_FB15_Pos)
6300#define CAN_F11R2_FB15 CAN_F11R2_FB15_Msk
6301#define CAN_F11R2_FB16_Pos (16U)
6302#define CAN_F11R2_FB16_Msk (0x1UL << CAN_F11R2_FB16_Pos)
6303#define CAN_F11R2_FB16 CAN_F11R2_FB16_Msk
6304#define CAN_F11R2_FB17_Pos (17U)
6305#define CAN_F11R2_FB17_Msk (0x1UL << CAN_F11R2_FB17_Pos)
6306#define CAN_F11R2_FB17 CAN_F11R2_FB17_Msk
6307#define CAN_F11R2_FB18_Pos (18U)
6308#define CAN_F11R2_FB18_Msk (0x1UL << CAN_F11R2_FB18_Pos)
6309#define CAN_F11R2_FB18 CAN_F11R2_FB18_Msk
6310#define CAN_F11R2_FB19_Pos (19U)
6311#define CAN_F11R2_FB19_Msk (0x1UL << CAN_F11R2_FB19_Pos)
6312#define CAN_F11R2_FB19 CAN_F11R2_FB19_Msk
6313#define CAN_F11R2_FB20_Pos (20U)
6314#define CAN_F11R2_FB20_Msk (0x1UL << CAN_F11R2_FB20_Pos)
6315#define CAN_F11R2_FB20 CAN_F11R2_FB20_Msk
6316#define CAN_F11R2_FB21_Pos (21U)
6317#define CAN_F11R2_FB21_Msk (0x1UL << CAN_F11R2_FB21_Pos)
6318#define CAN_F11R2_FB21 CAN_F11R2_FB21_Msk
6319#define CAN_F11R2_FB22_Pos (22U)
6320#define CAN_F11R2_FB22_Msk (0x1UL << CAN_F11R2_FB22_Pos)
6321#define CAN_F11R2_FB22 CAN_F11R2_FB22_Msk
6322#define CAN_F11R2_FB23_Pos (23U)
6323#define CAN_F11R2_FB23_Msk (0x1UL << CAN_F11R2_FB23_Pos)
6324#define CAN_F11R2_FB23 CAN_F11R2_FB23_Msk
6325#define CAN_F11R2_FB24_Pos (24U)
6326#define CAN_F11R2_FB24_Msk (0x1UL << CAN_F11R2_FB24_Pos)
6327#define CAN_F11R2_FB24 CAN_F11R2_FB24_Msk
6328#define CAN_F11R2_FB25_Pos (25U)
6329#define CAN_F11R2_FB25_Msk (0x1UL << CAN_F11R2_FB25_Pos)
6330#define CAN_F11R2_FB25 CAN_F11R2_FB25_Msk
6331#define CAN_F11R2_FB26_Pos (26U)
6332#define CAN_F11R2_FB26_Msk (0x1UL << CAN_F11R2_FB26_Pos)
6333#define CAN_F11R2_FB26 CAN_F11R2_FB26_Msk
6334#define CAN_F11R2_FB27_Pos (27U)
6335#define CAN_F11R2_FB27_Msk (0x1UL << CAN_F11R2_FB27_Pos)
6336#define CAN_F11R2_FB27 CAN_F11R2_FB27_Msk
6337#define CAN_F11R2_FB28_Pos (28U)
6338#define CAN_F11R2_FB28_Msk (0x1UL << CAN_F11R2_FB28_Pos)
6339#define CAN_F11R2_FB28 CAN_F11R2_FB28_Msk
6340#define CAN_F11R2_FB29_Pos (29U)
6341#define CAN_F11R2_FB29_Msk (0x1UL << CAN_F11R2_FB29_Pos)
6342#define CAN_F11R2_FB29 CAN_F11R2_FB29_Msk
6343#define CAN_F11R2_FB30_Pos (30U)
6344#define CAN_F11R2_FB30_Msk (0x1UL << CAN_F11R2_FB30_Pos)
6345#define CAN_F11R2_FB30 CAN_F11R2_FB30_Msk
6346#define CAN_F11R2_FB31_Pos (31U)
6347#define CAN_F11R2_FB31_Msk (0x1UL << CAN_F11R2_FB31_Pos)
6348#define CAN_F11R2_FB31 CAN_F11R2_FB31_Msk
6350/******************* Bit definition for CAN_F12R2 register ******************/
6351#define CAN_F12R2_FB0_Pos (0U)
6352#define CAN_F12R2_FB0_Msk (0x1UL << CAN_F12R2_FB0_Pos)
6353#define CAN_F12R2_FB0 CAN_F12R2_FB0_Msk
6354#define CAN_F12R2_FB1_Pos (1U)
6355#define CAN_F12R2_FB1_Msk (0x1UL << CAN_F12R2_FB1_Pos)
6356#define CAN_F12R2_FB1 CAN_F12R2_FB1_Msk
6357#define CAN_F12R2_FB2_Pos (2U)
6358#define CAN_F12R2_FB2_Msk (0x1UL << CAN_F12R2_FB2_Pos)
6359#define CAN_F12R2_FB2 CAN_F12R2_FB2_Msk
6360#define CAN_F12R2_FB3_Pos (3U)
6361#define CAN_F12R2_FB3_Msk (0x1UL << CAN_F12R2_FB3_Pos)
6362#define CAN_F12R2_FB3 CAN_F12R2_FB3_Msk
6363#define CAN_F12R2_FB4_Pos (4U)
6364#define CAN_F12R2_FB4_Msk (0x1UL << CAN_F12R2_FB4_Pos)
6365#define CAN_F12R2_FB4 CAN_F12R2_FB4_Msk
6366#define CAN_F12R2_FB5_Pos (5U)
6367#define CAN_F12R2_FB5_Msk (0x1UL << CAN_F12R2_FB5_Pos)
6368#define CAN_F12R2_FB5 CAN_F12R2_FB5_Msk
6369#define CAN_F12R2_FB6_Pos (6U)
6370#define CAN_F12R2_FB6_Msk (0x1UL << CAN_F12R2_FB6_Pos)
6371#define CAN_F12R2_FB6 CAN_F12R2_FB6_Msk
6372#define CAN_F12R2_FB7_Pos (7U)
6373#define CAN_F12R2_FB7_Msk (0x1UL << CAN_F12R2_FB7_Pos)
6374#define CAN_F12R2_FB7 CAN_F12R2_FB7_Msk
6375#define CAN_F12R2_FB8_Pos (8U)
6376#define CAN_F12R2_FB8_Msk (0x1UL << CAN_F12R2_FB8_Pos)
6377#define CAN_F12R2_FB8 CAN_F12R2_FB8_Msk
6378#define CAN_F12R2_FB9_Pos (9U)
6379#define CAN_F12R2_FB9_Msk (0x1UL << CAN_F12R2_FB9_Pos)
6380#define CAN_F12R2_FB9 CAN_F12R2_FB9_Msk
6381#define CAN_F12R2_FB10_Pos (10U)
6382#define CAN_F12R2_FB10_Msk (0x1UL << CAN_F12R2_FB10_Pos)
6383#define CAN_F12R2_FB10 CAN_F12R2_FB10_Msk
6384#define CAN_F12R2_FB11_Pos (11U)
6385#define CAN_F12R2_FB11_Msk (0x1UL << CAN_F12R2_FB11_Pos)
6386#define CAN_F12R2_FB11 CAN_F12R2_FB11_Msk
6387#define CAN_F12R2_FB12_Pos (12U)
6388#define CAN_F12R2_FB12_Msk (0x1UL << CAN_F12R2_FB12_Pos)
6389#define CAN_F12R2_FB12 CAN_F12R2_FB12_Msk
6390#define CAN_F12R2_FB13_Pos (13U)
6391#define CAN_F12R2_FB13_Msk (0x1UL << CAN_F12R2_FB13_Pos)
6392#define CAN_F12R2_FB13 CAN_F12R2_FB13_Msk
6393#define CAN_F12R2_FB14_Pos (14U)
6394#define CAN_F12R2_FB14_Msk (0x1UL << CAN_F12R2_FB14_Pos)
6395#define CAN_F12R2_FB14 CAN_F12R2_FB14_Msk
6396#define CAN_F12R2_FB15_Pos (15U)
6397#define CAN_F12R2_FB15_Msk (0x1UL << CAN_F12R2_FB15_Pos)
6398#define CAN_F12R2_FB15 CAN_F12R2_FB15_Msk
6399#define CAN_F12R2_FB16_Pos (16U)
6400#define CAN_F12R2_FB16_Msk (0x1UL << CAN_F12R2_FB16_Pos)
6401#define CAN_F12R2_FB16 CAN_F12R2_FB16_Msk
6402#define CAN_F12R2_FB17_Pos (17U)
6403#define CAN_F12R2_FB17_Msk (0x1UL << CAN_F12R2_FB17_Pos)
6404#define CAN_F12R2_FB17 CAN_F12R2_FB17_Msk
6405#define CAN_F12R2_FB18_Pos (18U)
6406#define CAN_F12R2_FB18_Msk (0x1UL << CAN_F12R2_FB18_Pos)
6407#define CAN_F12R2_FB18 CAN_F12R2_FB18_Msk
6408#define CAN_F12R2_FB19_Pos (19U)
6409#define CAN_F12R2_FB19_Msk (0x1UL << CAN_F12R2_FB19_Pos)
6410#define CAN_F12R2_FB19 CAN_F12R2_FB19_Msk
6411#define CAN_F12R2_FB20_Pos (20U)
6412#define CAN_F12R2_FB20_Msk (0x1UL << CAN_F12R2_FB20_Pos)
6413#define CAN_F12R2_FB20 CAN_F12R2_FB20_Msk
6414#define CAN_F12R2_FB21_Pos (21U)
6415#define CAN_F12R2_FB21_Msk (0x1UL << CAN_F12R2_FB21_Pos)
6416#define CAN_F12R2_FB21 CAN_F12R2_FB21_Msk
6417#define CAN_F12R2_FB22_Pos (22U)
6418#define CAN_F12R2_FB22_Msk (0x1UL << CAN_F12R2_FB22_Pos)
6419#define CAN_F12R2_FB22 CAN_F12R2_FB22_Msk
6420#define CAN_F12R2_FB23_Pos (23U)
6421#define CAN_F12R2_FB23_Msk (0x1UL << CAN_F12R2_FB23_Pos)
6422#define CAN_F12R2_FB23 CAN_F12R2_FB23_Msk
6423#define CAN_F12R2_FB24_Pos (24U)
6424#define CAN_F12R2_FB24_Msk (0x1UL << CAN_F12R2_FB24_Pos)
6425#define CAN_F12R2_FB24 CAN_F12R2_FB24_Msk
6426#define CAN_F12R2_FB25_Pos (25U)
6427#define CAN_F12R2_FB25_Msk (0x1UL << CAN_F12R2_FB25_Pos)
6428#define CAN_F12R2_FB25 CAN_F12R2_FB25_Msk
6429#define CAN_F12R2_FB26_Pos (26U)
6430#define CAN_F12R2_FB26_Msk (0x1UL << CAN_F12R2_FB26_Pos)
6431#define CAN_F12R2_FB26 CAN_F12R2_FB26_Msk
6432#define CAN_F12R2_FB27_Pos (27U)
6433#define CAN_F12R2_FB27_Msk (0x1UL << CAN_F12R2_FB27_Pos)
6434#define CAN_F12R2_FB27 CAN_F12R2_FB27_Msk
6435#define CAN_F12R2_FB28_Pos (28U)
6436#define CAN_F12R2_FB28_Msk (0x1UL << CAN_F12R2_FB28_Pos)
6437#define CAN_F12R2_FB28 CAN_F12R2_FB28_Msk
6438#define CAN_F12R2_FB29_Pos (29U)
6439#define CAN_F12R2_FB29_Msk (0x1UL << CAN_F12R2_FB29_Pos)
6440#define CAN_F12R2_FB29 CAN_F12R2_FB29_Msk
6441#define CAN_F12R2_FB30_Pos (30U)
6442#define CAN_F12R2_FB30_Msk (0x1UL << CAN_F12R2_FB30_Pos)
6443#define CAN_F12R2_FB30 CAN_F12R2_FB30_Msk
6444#define CAN_F12R2_FB31_Pos (31U)
6445#define CAN_F12R2_FB31_Msk (0x1UL << CAN_F12R2_FB31_Pos)
6446#define CAN_F12R2_FB31 CAN_F12R2_FB31_Msk
6448/******************* Bit definition for CAN_F13R2 register ******************/
6449#define CAN_F13R2_FB0_Pos (0U)
6450#define CAN_F13R2_FB0_Msk (0x1UL << CAN_F13R2_FB0_Pos)
6451#define CAN_F13R2_FB0 CAN_F13R2_FB0_Msk
6452#define CAN_F13R2_FB1_Pos (1U)
6453#define CAN_F13R2_FB1_Msk (0x1UL << CAN_F13R2_FB1_Pos)
6454#define CAN_F13R2_FB1 CAN_F13R2_FB1_Msk
6455#define CAN_F13R2_FB2_Pos (2U)
6456#define CAN_F13R2_FB2_Msk (0x1UL << CAN_F13R2_FB2_Pos)
6457#define CAN_F13R2_FB2 CAN_F13R2_FB2_Msk
6458#define CAN_F13R2_FB3_Pos (3U)
6459#define CAN_F13R2_FB3_Msk (0x1UL << CAN_F13R2_FB3_Pos)
6460#define CAN_F13R2_FB3 CAN_F13R2_FB3_Msk
6461#define CAN_F13R2_FB4_Pos (4U)
6462#define CAN_F13R2_FB4_Msk (0x1UL << CAN_F13R2_FB4_Pos)
6463#define CAN_F13R2_FB4 CAN_F13R2_FB4_Msk
6464#define CAN_F13R2_FB5_Pos (5U)
6465#define CAN_F13R2_FB5_Msk (0x1UL << CAN_F13R2_FB5_Pos)
6466#define CAN_F13R2_FB5 CAN_F13R2_FB5_Msk
6467#define CAN_F13R2_FB6_Pos (6U)
6468#define CAN_F13R2_FB6_Msk (0x1UL << CAN_F13R2_FB6_Pos)
6469#define CAN_F13R2_FB6 CAN_F13R2_FB6_Msk
6470#define CAN_F13R2_FB7_Pos (7U)
6471#define CAN_F13R2_FB7_Msk (0x1UL << CAN_F13R2_FB7_Pos)
6472#define CAN_F13R2_FB7 CAN_F13R2_FB7_Msk
6473#define CAN_F13R2_FB8_Pos (8U)
6474#define CAN_F13R2_FB8_Msk (0x1UL << CAN_F13R2_FB8_Pos)
6475#define CAN_F13R2_FB8 CAN_F13R2_FB8_Msk
6476#define CAN_F13R2_FB9_Pos (9U)
6477#define CAN_F13R2_FB9_Msk (0x1UL << CAN_F13R2_FB9_Pos)
6478#define CAN_F13R2_FB9 CAN_F13R2_FB9_Msk
6479#define CAN_F13R2_FB10_Pos (10U)
6480#define CAN_F13R2_FB10_Msk (0x1UL << CAN_F13R2_FB10_Pos)
6481#define CAN_F13R2_FB10 CAN_F13R2_FB10_Msk
6482#define CAN_F13R2_FB11_Pos (11U)
6483#define CAN_F13R2_FB11_Msk (0x1UL << CAN_F13R2_FB11_Pos)
6484#define CAN_F13R2_FB11 CAN_F13R2_FB11_Msk
6485#define CAN_F13R2_FB12_Pos (12U)
6486#define CAN_F13R2_FB12_Msk (0x1UL << CAN_F13R2_FB12_Pos)
6487#define CAN_F13R2_FB12 CAN_F13R2_FB12_Msk
6488#define CAN_F13R2_FB13_Pos (13U)
6489#define CAN_F13R2_FB13_Msk (0x1UL << CAN_F13R2_FB13_Pos)
6490#define CAN_F13R2_FB13 CAN_F13R2_FB13_Msk
6491#define CAN_F13R2_FB14_Pos (14U)
6492#define CAN_F13R2_FB14_Msk (0x1UL << CAN_F13R2_FB14_Pos)
6493#define CAN_F13R2_FB14 CAN_F13R2_FB14_Msk
6494#define CAN_F13R2_FB15_Pos (15U)
6495#define CAN_F13R2_FB15_Msk (0x1UL << CAN_F13R2_FB15_Pos)
6496#define CAN_F13R2_FB15 CAN_F13R2_FB15_Msk
6497#define CAN_F13R2_FB16_Pos (16U)
6498#define CAN_F13R2_FB16_Msk (0x1UL << CAN_F13R2_FB16_Pos)
6499#define CAN_F13R2_FB16 CAN_F13R2_FB16_Msk
6500#define CAN_F13R2_FB17_Pos (17U)
6501#define CAN_F13R2_FB17_Msk (0x1UL << CAN_F13R2_FB17_Pos)
6502#define CAN_F13R2_FB17 CAN_F13R2_FB17_Msk
6503#define CAN_F13R2_FB18_Pos (18U)
6504#define CAN_F13R2_FB18_Msk (0x1UL << CAN_F13R2_FB18_Pos)
6505#define CAN_F13R2_FB18 CAN_F13R2_FB18_Msk
6506#define CAN_F13R2_FB19_Pos (19U)
6507#define CAN_F13R2_FB19_Msk (0x1UL << CAN_F13R2_FB19_Pos)
6508#define CAN_F13R2_FB19 CAN_F13R2_FB19_Msk
6509#define CAN_F13R2_FB20_Pos (20U)
6510#define CAN_F13R2_FB20_Msk (0x1UL << CAN_F13R2_FB20_Pos)
6511#define CAN_F13R2_FB20 CAN_F13R2_FB20_Msk
6512#define CAN_F13R2_FB21_Pos (21U)
6513#define CAN_F13R2_FB21_Msk (0x1UL << CAN_F13R2_FB21_Pos)
6514#define CAN_F13R2_FB21 CAN_F13R2_FB21_Msk
6515#define CAN_F13R2_FB22_Pos (22U)
6516#define CAN_F13R2_FB22_Msk (0x1UL << CAN_F13R2_FB22_Pos)
6517#define CAN_F13R2_FB22 CAN_F13R2_FB22_Msk
6518#define CAN_F13R2_FB23_Pos (23U)
6519#define CAN_F13R2_FB23_Msk (0x1UL << CAN_F13R2_FB23_Pos)
6520#define CAN_F13R2_FB23 CAN_F13R2_FB23_Msk
6521#define CAN_F13R2_FB24_Pos (24U)
6522#define CAN_F13R2_FB24_Msk (0x1UL << CAN_F13R2_FB24_Pos)
6523#define CAN_F13R2_FB24 CAN_F13R2_FB24_Msk
6524#define CAN_F13R2_FB25_Pos (25U)
6525#define CAN_F13R2_FB25_Msk (0x1UL << CAN_F13R2_FB25_Pos)
6526#define CAN_F13R2_FB25 CAN_F13R2_FB25_Msk
6527#define CAN_F13R2_FB26_Pos (26U)
6528#define CAN_F13R2_FB26_Msk (0x1UL << CAN_F13R2_FB26_Pos)
6529#define CAN_F13R2_FB26 CAN_F13R2_FB26_Msk
6530#define CAN_F13R2_FB27_Pos (27U)
6531#define CAN_F13R2_FB27_Msk (0x1UL << CAN_F13R2_FB27_Pos)
6532#define CAN_F13R2_FB27 CAN_F13R2_FB27_Msk
6533#define CAN_F13R2_FB28_Pos (28U)
6534#define CAN_F13R2_FB28_Msk (0x1UL << CAN_F13R2_FB28_Pos)
6535#define CAN_F13R2_FB28 CAN_F13R2_FB28_Msk
6536#define CAN_F13R2_FB29_Pos (29U)
6537#define CAN_F13R2_FB29_Msk (0x1UL << CAN_F13R2_FB29_Pos)
6538#define CAN_F13R2_FB29 CAN_F13R2_FB29_Msk
6539#define CAN_F13R2_FB30_Pos (30U)
6540#define CAN_F13R2_FB30_Msk (0x1UL << CAN_F13R2_FB30_Pos)
6541#define CAN_F13R2_FB30 CAN_F13R2_FB30_Msk
6542#define CAN_F13R2_FB31_Pos (31U)
6543#define CAN_F13R2_FB31_Msk (0x1UL << CAN_F13R2_FB31_Pos)
6544#define CAN_F13R2_FB31 CAN_F13R2_FB31_Msk
6546/******************************************************************************/
6547/* */
6548/* CRC calculation unit (CRC) */
6549/* */
6550/******************************************************************************/
6551/******************* Bit definition for CRC_DR register *********************/
6552#define CRC_DR_DR_Pos (0U)
6553#define CRC_DR_DR_Msk (0xFFFFFFFFUL << CRC_DR_DR_Pos)
6554#define CRC_DR_DR CRC_DR_DR_Msk
6556/******************* Bit definition for CRC_IDR register ********************/
6557#define CRC_IDR_IDR ((uint8_t)0xFFU)
6559/******************** Bit definition for CRC_CR register ********************/
6560#define CRC_CR_RESET_Pos (0U)
6561#define CRC_CR_RESET_Msk (0x1UL << CRC_CR_RESET_Pos)
6562#define CRC_CR_RESET CRC_CR_RESET_Msk
6563#define CRC_CR_POLYSIZE_Pos (3U)
6564#define CRC_CR_POLYSIZE_Msk (0x3UL << CRC_CR_POLYSIZE_Pos)
6565#define CRC_CR_POLYSIZE CRC_CR_POLYSIZE_Msk
6566#define CRC_CR_POLYSIZE_0 (0x1UL << CRC_CR_POLYSIZE_Pos)
6567#define CRC_CR_POLYSIZE_1 (0x2UL << CRC_CR_POLYSIZE_Pos)
6568#define CRC_CR_REV_IN_Pos (5U)
6569#define CRC_CR_REV_IN_Msk (0x3UL << CRC_CR_REV_IN_Pos)
6570#define CRC_CR_REV_IN CRC_CR_REV_IN_Msk
6571#define CRC_CR_REV_IN_0 (0x1UL << CRC_CR_REV_IN_Pos)
6572#define CRC_CR_REV_IN_1 (0x2UL << CRC_CR_REV_IN_Pos)
6573#define CRC_CR_REV_OUT_Pos (7U)
6574#define CRC_CR_REV_OUT_Msk (0x1UL << CRC_CR_REV_OUT_Pos)
6575#define CRC_CR_REV_OUT CRC_CR_REV_OUT_Msk
6577/******************* Bit definition for CRC_INIT register *******************/
6578#define CRC_INIT_INIT_Pos (0U)
6579#define CRC_INIT_INIT_Msk (0xFFFFFFFFUL << CRC_INIT_INIT_Pos)
6580#define CRC_INIT_INIT CRC_INIT_INIT_Msk
6582/******************* Bit definition for CRC_POL register ********************/
6583#define CRC_POL_POL_Pos (0U)
6584#define CRC_POL_POL_Msk (0xFFFFFFFFUL << CRC_POL_POL_Pos)
6585#define CRC_POL_POL CRC_POL_POL_Msk
6587/******************************************************************************/
6588/* */
6589/* Digital to Analog Converter (DAC) */
6590/* */
6591/******************************************************************************/
6592
6593/*
6594 * @brief Specific device feature definitions (not present on all devices in the STM32F3 series)
6595 */
6596#define DAC_CHANNEL2_SUPPORT
6599/******************** Bit definition for DAC_CR register ********************/
6600#define DAC_CR_EN1_Pos (0U)
6601#define DAC_CR_EN1_Msk (0x1UL << DAC_CR_EN1_Pos)
6602#define DAC_CR_EN1 DAC_CR_EN1_Msk
6603#define DAC_CR_BOFF1_Pos (1U)
6604#define DAC_CR_BOFF1_Msk (0x1UL << DAC_CR_BOFF1_Pos)
6605#define DAC_CR_BOFF1 DAC_CR_BOFF1_Msk
6606#define DAC_CR_TEN1_Pos (2U)
6607#define DAC_CR_TEN1_Msk (0x1UL << DAC_CR_TEN1_Pos)
6608#define DAC_CR_TEN1 DAC_CR_TEN1_Msk
6610#define DAC_CR_TSEL1_Pos (3U)
6611#define DAC_CR_TSEL1_Msk (0x7UL << DAC_CR_TSEL1_Pos)
6612#define DAC_CR_TSEL1 DAC_CR_TSEL1_Msk
6613#define DAC_CR_TSEL1_0 (0x1UL << DAC_CR_TSEL1_Pos)
6614#define DAC_CR_TSEL1_1 (0x2UL << DAC_CR_TSEL1_Pos)
6615#define DAC_CR_TSEL1_2 (0x4UL << DAC_CR_TSEL1_Pos)
6617#define DAC_CR_WAVE1_Pos (6U)
6618#define DAC_CR_WAVE1_Msk (0x3UL << DAC_CR_WAVE1_Pos)
6619#define DAC_CR_WAVE1 DAC_CR_WAVE1_Msk
6620#define DAC_CR_WAVE1_0 (0x1UL << DAC_CR_WAVE1_Pos)
6621#define DAC_CR_WAVE1_1 (0x2UL << DAC_CR_WAVE1_Pos)
6623#define DAC_CR_MAMP1_Pos (8U)
6624#define DAC_CR_MAMP1_Msk (0xFUL << DAC_CR_MAMP1_Pos)
6625#define DAC_CR_MAMP1 DAC_CR_MAMP1_Msk
6626#define DAC_CR_MAMP1_0 (0x1UL << DAC_CR_MAMP1_Pos)
6627#define DAC_CR_MAMP1_1 (0x2UL << DAC_CR_MAMP1_Pos)
6628#define DAC_CR_MAMP1_2 (0x4UL << DAC_CR_MAMP1_Pos)
6629#define DAC_CR_MAMP1_3 (0x8UL << DAC_CR_MAMP1_Pos)
6631#define DAC_CR_DMAEN1_Pos (12U)
6632#define DAC_CR_DMAEN1_Msk (0x1UL << DAC_CR_DMAEN1_Pos)
6633#define DAC_CR_DMAEN1 DAC_CR_DMAEN1_Msk
6634#define DAC_CR_DMAUDRIE1_Pos (13U)
6635#define DAC_CR_DMAUDRIE1_Msk (0x1UL << DAC_CR_DMAUDRIE1_Pos)
6636#define DAC_CR_DMAUDRIE1 DAC_CR_DMAUDRIE1_Msk
6637#define DAC_CR_EN2_Pos (16U)
6638#define DAC_CR_EN2_Msk (0x1UL << DAC_CR_EN2_Pos)
6639#define DAC_CR_EN2 DAC_CR_EN2_Msk
6640#define DAC_CR_BOFF2_Pos (17U)
6641#define DAC_CR_BOFF2_Msk (0x1UL << DAC_CR_BOFF2_Pos)
6642#define DAC_CR_BOFF2 DAC_CR_BOFF2_Msk
6643#define DAC_CR_TEN2_Pos (18U)
6644#define DAC_CR_TEN2_Msk (0x1UL << DAC_CR_TEN2_Pos)
6645#define DAC_CR_TEN2 DAC_CR_TEN2_Msk
6647#define DAC_CR_TSEL2_Pos (19U)
6648#define DAC_CR_TSEL2_Msk (0x7UL << DAC_CR_TSEL2_Pos)
6649#define DAC_CR_TSEL2 DAC_CR_TSEL2_Msk
6650#define DAC_CR_TSEL2_0 (0x1UL << DAC_CR_TSEL2_Pos)
6651#define DAC_CR_TSEL2_1 (0x2UL << DAC_CR_TSEL2_Pos)
6652#define DAC_CR_TSEL2_2 (0x4UL << DAC_CR_TSEL2_Pos)
6654#define DAC_CR_WAVE2_Pos (22U)
6655#define DAC_CR_WAVE2_Msk (0x3UL << DAC_CR_WAVE2_Pos)
6656#define DAC_CR_WAVE2 DAC_CR_WAVE2_Msk
6657#define DAC_CR_WAVE2_0 (0x1UL << DAC_CR_WAVE2_Pos)
6658#define DAC_CR_WAVE2_1 (0x2UL << DAC_CR_WAVE2_Pos)
6660#define DAC_CR_MAMP2_Pos (24U)
6661#define DAC_CR_MAMP2_Msk (0xFUL << DAC_CR_MAMP2_Pos)
6662#define DAC_CR_MAMP2 DAC_CR_MAMP2_Msk
6663#define DAC_CR_MAMP2_0 (0x1UL << DAC_CR_MAMP2_Pos)
6664#define DAC_CR_MAMP2_1 (0x2UL << DAC_CR_MAMP2_Pos)
6665#define DAC_CR_MAMP2_2 (0x4UL << DAC_CR_MAMP2_Pos)
6666#define DAC_CR_MAMP2_3 (0x8UL << DAC_CR_MAMP2_Pos)
6668#define DAC_CR_DMAEN2_Pos (28U)
6669#define DAC_CR_DMAEN2_Msk (0x1UL << DAC_CR_DMAEN2_Pos)
6670#define DAC_CR_DMAEN2 DAC_CR_DMAEN2_Msk
6671#define DAC_CR_DMAUDRIE2_Pos (29U)
6672#define DAC_CR_DMAUDRIE2_Msk (0x1UL << DAC_CR_DMAUDRIE2_Pos)
6673#define DAC_CR_DMAUDRIE2 DAC_CR_DMAUDRIE2_Msk
6675/***************** Bit definition for DAC_SWTRIGR register ******************/
6676#define DAC_SWTRIGR_SWTRIG1_Pos (0U)
6677#define DAC_SWTRIGR_SWTRIG1_Msk (0x1UL << DAC_SWTRIGR_SWTRIG1_Pos)
6678#define DAC_SWTRIGR_SWTRIG1 DAC_SWTRIGR_SWTRIG1_Msk
6679#define DAC_SWTRIGR_SWTRIG2_Pos (1U)
6680#define DAC_SWTRIGR_SWTRIG2_Msk (0x1UL << DAC_SWTRIGR_SWTRIG2_Pos)
6681#define DAC_SWTRIGR_SWTRIG2 DAC_SWTRIGR_SWTRIG2_Msk
6683/***************** Bit definition for DAC_DHR12R1 register ******************/
6684#define DAC_DHR12R1_DACC1DHR_Pos (0U)
6685#define DAC_DHR12R1_DACC1DHR_Msk (0xFFFUL << DAC_DHR12R1_DACC1DHR_Pos)
6686#define DAC_DHR12R1_DACC1DHR DAC_DHR12R1_DACC1DHR_Msk
6688/***************** Bit definition for DAC_DHR12L1 register ******************/
6689#define DAC_DHR12L1_DACC1DHR_Pos (4U)
6690#define DAC_DHR12L1_DACC1DHR_Msk (0xFFFUL << DAC_DHR12L1_DACC1DHR_Pos)
6691#define DAC_DHR12L1_DACC1DHR DAC_DHR12L1_DACC1DHR_Msk
6693/****************** Bit definition for DAC_DHR8R1 register ******************/
6694#define DAC_DHR8R1_DACC1DHR_Pos (0U)
6695#define DAC_DHR8R1_DACC1DHR_Msk (0xFFUL << DAC_DHR8R1_DACC1DHR_Pos)
6696#define DAC_DHR8R1_DACC1DHR DAC_DHR8R1_DACC1DHR_Msk
6698/***************** Bit definition for DAC_DHR12R2 register ******************/
6699#define DAC_DHR12R2_DACC2DHR_Pos (0U)
6700#define DAC_DHR12R2_DACC2DHR_Msk (0xFFFUL << DAC_DHR12R2_DACC2DHR_Pos)
6701#define DAC_DHR12R2_DACC2DHR DAC_DHR12R2_DACC2DHR_Msk
6703/***************** Bit definition for DAC_DHR12L2 register ******************/
6704#define DAC_DHR12L2_DACC2DHR_Pos (4U)
6705#define DAC_DHR12L2_DACC2DHR_Msk (0xFFFUL << DAC_DHR12L2_DACC2DHR_Pos)
6706#define DAC_DHR12L2_DACC2DHR DAC_DHR12L2_DACC2DHR_Msk
6708/****************** Bit definition for DAC_DHR8R2 register ******************/
6709#define DAC_DHR8R2_DACC2DHR_Pos (0U)
6710#define DAC_DHR8R2_DACC2DHR_Msk (0xFFUL << DAC_DHR8R2_DACC2DHR_Pos)
6711#define DAC_DHR8R2_DACC2DHR DAC_DHR8R2_DACC2DHR_Msk
6713/***************** Bit definition for DAC_DHR12RD register ******************/
6714#define DAC_DHR12RD_DACC1DHR_Pos (0U)
6715#define DAC_DHR12RD_DACC1DHR_Msk (0xFFFUL << DAC_DHR12RD_DACC1DHR_Pos)
6716#define DAC_DHR12RD_DACC1DHR DAC_DHR12RD_DACC1DHR_Msk
6717#define DAC_DHR12RD_DACC2DHR_Pos (16U)
6718#define DAC_DHR12RD_DACC2DHR_Msk (0xFFFUL << DAC_DHR12RD_DACC2DHR_Pos)
6719#define DAC_DHR12RD_DACC2DHR DAC_DHR12RD_DACC2DHR_Msk
6721/***************** Bit definition for DAC_DHR12LD register ******************/
6722#define DAC_DHR12LD_DACC1DHR_Pos (4U)
6723#define DAC_DHR12LD_DACC1DHR_Msk (0xFFFUL << DAC_DHR12LD_DACC1DHR_Pos)
6724#define DAC_DHR12LD_DACC1DHR DAC_DHR12LD_DACC1DHR_Msk
6725#define DAC_DHR12LD_DACC2DHR_Pos (20U)
6726#define DAC_DHR12LD_DACC2DHR_Msk (0xFFFUL << DAC_DHR12LD_DACC2DHR_Pos)
6727#define DAC_DHR12LD_DACC2DHR DAC_DHR12LD_DACC2DHR_Msk
6729/****************** Bit definition for DAC_DHR8RD register ******************/
6730#define DAC_DHR8RD_DACC1DHR_Pos (0U)
6731#define DAC_DHR8RD_DACC1DHR_Msk (0xFFUL << DAC_DHR8RD_DACC1DHR_Pos)
6732#define DAC_DHR8RD_DACC1DHR DAC_DHR8RD_DACC1DHR_Msk
6733#define DAC_DHR8RD_DACC2DHR_Pos (8U)
6734#define DAC_DHR8RD_DACC2DHR_Msk (0xFFUL << DAC_DHR8RD_DACC2DHR_Pos)
6735#define DAC_DHR8RD_DACC2DHR DAC_DHR8RD_DACC2DHR_Msk
6737/******************* Bit definition for DAC_DOR1 register *******************/
6738#define DAC_DOR1_DACC1DOR_Pos (0U)
6739#define DAC_DOR1_DACC1DOR_Msk (0xFFFUL << DAC_DOR1_DACC1DOR_Pos)
6740#define DAC_DOR1_DACC1DOR DAC_DOR1_DACC1DOR_Msk
6742/******************* Bit definition for DAC_DOR2 register *******************/
6743#define DAC_DOR2_DACC2DOR_Pos (0U)
6744#define DAC_DOR2_DACC2DOR_Msk (0xFFFUL << DAC_DOR2_DACC2DOR_Pos)
6745#define DAC_DOR2_DACC2DOR DAC_DOR2_DACC2DOR_Msk
6747/******************** Bit definition for DAC_SR register ********************/
6748#define DAC_SR_DMAUDR1_Pos (13U)
6749#define DAC_SR_DMAUDR1_Msk (0x1UL << DAC_SR_DMAUDR1_Pos)
6750#define DAC_SR_DMAUDR1 DAC_SR_DMAUDR1_Msk
6751#define DAC_SR_DMAUDR2_Pos (29U)
6752#define DAC_SR_DMAUDR2_Msk (0x1UL << DAC_SR_DMAUDR2_Pos)
6753#define DAC_SR_DMAUDR2 DAC_SR_DMAUDR2_Msk
6755/******************************************************************************/
6756/* */
6757/* Debug MCU (DBGMCU) */
6758/* */
6759/******************************************************************************/
6760/******************** Bit definition for DBGMCU_IDCODE register *************/
6761#define DBGMCU_IDCODE_DEV_ID_Pos (0U)
6762#define DBGMCU_IDCODE_DEV_ID_Msk (0xFFFUL << DBGMCU_IDCODE_DEV_ID_Pos)
6763#define DBGMCU_IDCODE_DEV_ID DBGMCU_IDCODE_DEV_ID_Msk
6764#define DBGMCU_IDCODE_REV_ID_Pos (16U)
6765#define DBGMCU_IDCODE_REV_ID_Msk (0xFFFFUL << DBGMCU_IDCODE_REV_ID_Pos)
6766#define DBGMCU_IDCODE_REV_ID DBGMCU_IDCODE_REV_ID_Msk
6767
6768/******************** Bit definition for DBGMCU_CR register *****************/
6769#define DBGMCU_CR_DBG_SLEEP_Pos (0U)
6770#define DBGMCU_CR_DBG_SLEEP_Msk (0x1UL << DBGMCU_CR_DBG_SLEEP_Pos)
6771#define DBGMCU_CR_DBG_SLEEP DBGMCU_CR_DBG_SLEEP_Msk
6772#define DBGMCU_CR_DBG_STOP_Pos (1U)
6773#define DBGMCU_CR_DBG_STOP_Msk (0x1UL << DBGMCU_CR_DBG_STOP_Pos)
6774#define DBGMCU_CR_DBG_STOP DBGMCU_CR_DBG_STOP_Msk
6775#define DBGMCU_CR_DBG_STANDBY_Pos (2U)
6776#define DBGMCU_CR_DBG_STANDBY_Msk (0x1UL << DBGMCU_CR_DBG_STANDBY_Pos)
6777#define DBGMCU_CR_DBG_STANDBY DBGMCU_CR_DBG_STANDBY_Msk
6778#define DBGMCU_CR_TRACE_IOEN_Pos (5U)
6779#define DBGMCU_CR_TRACE_IOEN_Msk (0x1UL << DBGMCU_CR_TRACE_IOEN_Pos)
6780#define DBGMCU_CR_TRACE_IOEN DBGMCU_CR_TRACE_IOEN_Msk
6781
6782#define DBGMCU_CR_TRACE_MODE_Pos (6U)
6783#define DBGMCU_CR_TRACE_MODE_Msk (0x3UL << DBGMCU_CR_TRACE_MODE_Pos)
6784#define DBGMCU_CR_TRACE_MODE DBGMCU_CR_TRACE_MODE_Msk
6785#define DBGMCU_CR_TRACE_MODE_0 (0x1UL << DBGMCU_CR_TRACE_MODE_Pos)
6786#define DBGMCU_CR_TRACE_MODE_1 (0x2UL << DBGMCU_CR_TRACE_MODE_Pos)
6788/******************** Bit definition for DBGMCU_APB1_FZ register ************/
6789#define DBGMCU_APB1_FZ_DBG_TIM2_STOP_Pos (0U)
6790#define DBGMCU_APB1_FZ_DBG_TIM2_STOP_Msk (0x1UL << DBGMCU_APB1_FZ_DBG_TIM2_STOP_Pos)
6791#define DBGMCU_APB1_FZ_DBG_TIM2_STOP DBGMCU_APB1_FZ_DBG_TIM2_STOP_Msk
6792#define DBGMCU_APB1_FZ_DBG_TIM3_STOP_Pos (1U)
6793#define DBGMCU_APB1_FZ_DBG_TIM3_STOP_Msk (0x1UL << DBGMCU_APB1_FZ_DBG_TIM3_STOP_Pos)
6794#define DBGMCU_APB1_FZ_DBG_TIM3_STOP DBGMCU_APB1_FZ_DBG_TIM3_STOP_Msk
6795#define DBGMCU_APB1_FZ_DBG_TIM4_STOP_Pos (2U)
6796#define DBGMCU_APB1_FZ_DBG_TIM4_STOP_Msk (0x1UL << DBGMCU_APB1_FZ_DBG_TIM4_STOP_Pos)
6797#define DBGMCU_APB1_FZ_DBG_TIM4_STOP DBGMCU_APB1_FZ_DBG_TIM4_STOP_Msk
6798#define DBGMCU_APB1_FZ_DBG_TIM6_STOP_Pos (4U)
6799#define DBGMCU_APB1_FZ_DBG_TIM6_STOP_Msk (0x1UL << DBGMCU_APB1_FZ_DBG_TIM6_STOP_Pos)
6800#define DBGMCU_APB1_FZ_DBG_TIM6_STOP DBGMCU_APB1_FZ_DBG_TIM6_STOP_Msk
6801#define DBGMCU_APB1_FZ_DBG_TIM7_STOP_Pos (5U)
6802#define DBGMCU_APB1_FZ_DBG_TIM7_STOP_Msk (0x1UL << DBGMCU_APB1_FZ_DBG_TIM7_STOP_Pos)
6803#define DBGMCU_APB1_FZ_DBG_TIM7_STOP DBGMCU_APB1_FZ_DBG_TIM7_STOP_Msk
6804#define DBGMCU_APB1_FZ_DBG_RTC_STOP_Pos (10U)
6805#define DBGMCU_APB1_FZ_DBG_RTC_STOP_Msk (0x1UL << DBGMCU_APB1_FZ_DBG_RTC_STOP_Pos)
6806#define DBGMCU_APB1_FZ_DBG_RTC_STOP DBGMCU_APB1_FZ_DBG_RTC_STOP_Msk
6807#define DBGMCU_APB1_FZ_DBG_WWDG_STOP_Pos (11U)
6808#define DBGMCU_APB1_FZ_DBG_WWDG_STOP_Msk (0x1UL << DBGMCU_APB1_FZ_DBG_WWDG_STOP_Pos)
6809#define DBGMCU_APB1_FZ_DBG_WWDG_STOP DBGMCU_APB1_FZ_DBG_WWDG_STOP_Msk
6810#define DBGMCU_APB1_FZ_DBG_IWDG_STOP_Pos (12U)
6811#define DBGMCU_APB1_FZ_DBG_IWDG_STOP_Msk (0x1UL << DBGMCU_APB1_FZ_DBG_IWDG_STOP_Pos)
6812#define DBGMCU_APB1_FZ_DBG_IWDG_STOP DBGMCU_APB1_FZ_DBG_IWDG_STOP_Msk
6813#define DBGMCU_APB1_FZ_DBG_I2C1_SMBUS_TIMEOUT_Pos (21U)
6814#define DBGMCU_APB1_FZ_DBG_I2C1_SMBUS_TIMEOUT_Msk (0x1UL << DBGMCU_APB1_FZ_DBG_I2C1_SMBUS_TIMEOUT_Pos)
6815#define DBGMCU_APB1_FZ_DBG_I2C1_SMBUS_TIMEOUT DBGMCU_APB1_FZ_DBG_I2C1_SMBUS_TIMEOUT_Msk
6816#define DBGMCU_APB1_FZ_DBG_I2C2_SMBUS_TIMEOUT_Pos (22U)
6817#define DBGMCU_APB1_FZ_DBG_I2C2_SMBUS_TIMEOUT_Msk (0x1UL << DBGMCU_APB1_FZ_DBG_I2C2_SMBUS_TIMEOUT_Pos)
6818#define DBGMCU_APB1_FZ_DBG_I2C2_SMBUS_TIMEOUT DBGMCU_APB1_FZ_DBG_I2C2_SMBUS_TIMEOUT_Msk
6819#define DBGMCU_APB1_FZ_DBG_I2C3_SMBUS_TIMEOUT_Pos (30U)
6820#define DBGMCU_APB1_FZ_DBG_I2C3_SMBUS_TIMEOUT_Msk (0x1UL << DBGMCU_APB1_FZ_DBG_I2C3_SMBUS_TIMEOUT_Pos)
6821#define DBGMCU_APB1_FZ_DBG_I2C3_SMBUS_TIMEOUT DBGMCU_APB1_FZ_DBG_I2C3_SMBUS_TIMEOUT_Msk
6822#define DBGMCU_APB1_FZ_DBG_CAN_STOP_Pos (25U)
6823#define DBGMCU_APB1_FZ_DBG_CAN_STOP_Msk (0x1UL << DBGMCU_APB1_FZ_DBG_CAN_STOP_Pos)
6824#define DBGMCU_APB1_FZ_DBG_CAN_STOP DBGMCU_APB1_FZ_DBG_CAN_STOP_Msk
6825
6826/******************** Bit definition for DBGMCU_APB2_FZ register ************/
6827#define DBGMCU_APB2_FZ_DBG_TIM1_STOP_Pos (0U)
6828#define DBGMCU_APB2_FZ_DBG_TIM1_STOP_Msk (0x1UL << DBGMCU_APB2_FZ_DBG_TIM1_STOP_Pos)
6829#define DBGMCU_APB2_FZ_DBG_TIM1_STOP DBGMCU_APB2_FZ_DBG_TIM1_STOP_Msk
6830#define DBGMCU_APB2_FZ_DBG_TIM8_STOP_Pos (1U)
6831#define DBGMCU_APB2_FZ_DBG_TIM8_STOP_Msk (0x1UL << DBGMCU_APB2_FZ_DBG_TIM8_STOP_Pos)
6832#define DBGMCU_APB2_FZ_DBG_TIM8_STOP DBGMCU_APB2_FZ_DBG_TIM8_STOP_Msk
6833#define DBGMCU_APB2_FZ_DBG_TIM15_STOP_Pos (2U)
6834#define DBGMCU_APB2_FZ_DBG_TIM15_STOP_Msk (0x1UL << DBGMCU_APB2_FZ_DBG_TIM15_STOP_Pos)
6835#define DBGMCU_APB2_FZ_DBG_TIM15_STOP DBGMCU_APB2_FZ_DBG_TIM15_STOP_Msk
6836#define DBGMCU_APB2_FZ_DBG_TIM16_STOP_Pos (3U)
6837#define DBGMCU_APB2_FZ_DBG_TIM16_STOP_Msk (0x1UL << DBGMCU_APB2_FZ_DBG_TIM16_STOP_Pos)
6838#define DBGMCU_APB2_FZ_DBG_TIM16_STOP DBGMCU_APB2_FZ_DBG_TIM16_STOP_Msk
6839#define DBGMCU_APB2_FZ_DBG_TIM17_STOP_Pos (4U)
6840#define DBGMCU_APB2_FZ_DBG_TIM17_STOP_Msk (0x1UL << DBGMCU_APB2_FZ_DBG_TIM17_STOP_Pos)
6841#define DBGMCU_APB2_FZ_DBG_TIM17_STOP DBGMCU_APB2_FZ_DBG_TIM17_STOP_Msk
6842#define DBGMCU_APB2_FZ_DBG_TIM20_STOP_Pos (5U)
6843#define DBGMCU_APB2_FZ_DBG_TIM20_STOP_Msk (0x1UL << DBGMCU_APB2_FZ_DBG_TIM20_STOP_Pos)
6844#define DBGMCU_APB2_FZ_DBG_TIM20_STOP DBGMCU_APB2_FZ_DBG_TIM20_STOP_Msk
6845
6846/******************************************************************************/
6847/* */
6848/* DMA Controller (DMA) */
6849/* */
6850/******************************************************************************/
6851/******************* Bit definition for DMA_ISR register ********************/
6852#define DMA_ISR_GIF1_Pos (0U)
6853#define DMA_ISR_GIF1_Msk (0x1UL << DMA_ISR_GIF1_Pos)
6854#define DMA_ISR_GIF1 DMA_ISR_GIF1_Msk
6855#define DMA_ISR_TCIF1_Pos (1U)
6856#define DMA_ISR_TCIF1_Msk (0x1UL << DMA_ISR_TCIF1_Pos)
6857#define DMA_ISR_TCIF1 DMA_ISR_TCIF1_Msk
6858#define DMA_ISR_HTIF1_Pos (2U)
6859#define DMA_ISR_HTIF1_Msk (0x1UL << DMA_ISR_HTIF1_Pos)
6860#define DMA_ISR_HTIF1 DMA_ISR_HTIF1_Msk
6861#define DMA_ISR_TEIF1_Pos (3U)
6862#define DMA_ISR_TEIF1_Msk (0x1UL << DMA_ISR_TEIF1_Pos)
6863#define DMA_ISR_TEIF1 DMA_ISR_TEIF1_Msk
6864#define DMA_ISR_GIF2_Pos (4U)
6865#define DMA_ISR_GIF2_Msk (0x1UL << DMA_ISR_GIF2_Pos)
6866#define DMA_ISR_GIF2 DMA_ISR_GIF2_Msk
6867#define DMA_ISR_TCIF2_Pos (5U)
6868#define DMA_ISR_TCIF2_Msk (0x1UL << DMA_ISR_TCIF2_Pos)
6869#define DMA_ISR_TCIF2 DMA_ISR_TCIF2_Msk
6870#define DMA_ISR_HTIF2_Pos (6U)
6871#define DMA_ISR_HTIF2_Msk (0x1UL << DMA_ISR_HTIF2_Pos)
6872#define DMA_ISR_HTIF2 DMA_ISR_HTIF2_Msk
6873#define DMA_ISR_TEIF2_Pos (7U)
6874#define DMA_ISR_TEIF2_Msk (0x1UL << DMA_ISR_TEIF2_Pos)
6875#define DMA_ISR_TEIF2 DMA_ISR_TEIF2_Msk
6876#define DMA_ISR_GIF3_Pos (8U)
6877#define DMA_ISR_GIF3_Msk (0x1UL << DMA_ISR_GIF3_Pos)
6878#define DMA_ISR_GIF3 DMA_ISR_GIF3_Msk
6879#define DMA_ISR_TCIF3_Pos (9U)
6880#define DMA_ISR_TCIF3_Msk (0x1UL << DMA_ISR_TCIF3_Pos)
6881#define DMA_ISR_TCIF3 DMA_ISR_TCIF3_Msk
6882#define DMA_ISR_HTIF3_Pos (10U)
6883#define DMA_ISR_HTIF3_Msk (0x1UL << DMA_ISR_HTIF3_Pos)
6884#define DMA_ISR_HTIF3 DMA_ISR_HTIF3_Msk
6885#define DMA_ISR_TEIF3_Pos (11U)
6886#define DMA_ISR_TEIF3_Msk (0x1UL << DMA_ISR_TEIF3_Pos)
6887#define DMA_ISR_TEIF3 DMA_ISR_TEIF3_Msk
6888#define DMA_ISR_GIF4_Pos (12U)
6889#define DMA_ISR_GIF4_Msk (0x1UL << DMA_ISR_GIF4_Pos)
6890#define DMA_ISR_GIF4 DMA_ISR_GIF4_Msk
6891#define DMA_ISR_TCIF4_Pos (13U)
6892#define DMA_ISR_TCIF4_Msk (0x1UL << DMA_ISR_TCIF4_Pos)
6893#define DMA_ISR_TCIF4 DMA_ISR_TCIF4_Msk
6894#define DMA_ISR_HTIF4_Pos (14U)
6895#define DMA_ISR_HTIF4_Msk (0x1UL << DMA_ISR_HTIF4_Pos)
6896#define DMA_ISR_HTIF4 DMA_ISR_HTIF4_Msk
6897#define DMA_ISR_TEIF4_Pos (15U)
6898#define DMA_ISR_TEIF4_Msk (0x1UL << DMA_ISR_TEIF4_Pos)
6899#define DMA_ISR_TEIF4 DMA_ISR_TEIF4_Msk
6900#define DMA_ISR_GIF5_Pos (16U)
6901#define DMA_ISR_GIF5_Msk (0x1UL << DMA_ISR_GIF5_Pos)
6902#define DMA_ISR_GIF5 DMA_ISR_GIF5_Msk
6903#define DMA_ISR_TCIF5_Pos (17U)
6904#define DMA_ISR_TCIF5_Msk (0x1UL << DMA_ISR_TCIF5_Pos)
6905#define DMA_ISR_TCIF5 DMA_ISR_TCIF5_Msk
6906#define DMA_ISR_HTIF5_Pos (18U)
6907#define DMA_ISR_HTIF5_Msk (0x1UL << DMA_ISR_HTIF5_Pos)
6908#define DMA_ISR_HTIF5 DMA_ISR_HTIF5_Msk
6909#define DMA_ISR_TEIF5_Pos (19U)
6910#define DMA_ISR_TEIF5_Msk (0x1UL << DMA_ISR_TEIF5_Pos)
6911#define DMA_ISR_TEIF5 DMA_ISR_TEIF5_Msk
6912#define DMA_ISR_GIF6_Pos (20U)
6913#define DMA_ISR_GIF6_Msk (0x1UL << DMA_ISR_GIF6_Pos)
6914#define DMA_ISR_GIF6 DMA_ISR_GIF6_Msk
6915#define DMA_ISR_TCIF6_Pos (21U)
6916#define DMA_ISR_TCIF6_Msk (0x1UL << DMA_ISR_TCIF6_Pos)
6917#define DMA_ISR_TCIF6 DMA_ISR_TCIF6_Msk
6918#define DMA_ISR_HTIF6_Pos (22U)
6919#define DMA_ISR_HTIF6_Msk (0x1UL << DMA_ISR_HTIF6_Pos)
6920#define DMA_ISR_HTIF6 DMA_ISR_HTIF6_Msk
6921#define DMA_ISR_TEIF6_Pos (23U)
6922#define DMA_ISR_TEIF6_Msk (0x1UL << DMA_ISR_TEIF6_Pos)
6923#define DMA_ISR_TEIF6 DMA_ISR_TEIF6_Msk
6924#define DMA_ISR_GIF7_Pos (24U)
6925#define DMA_ISR_GIF7_Msk (0x1UL << DMA_ISR_GIF7_Pos)
6926#define DMA_ISR_GIF7 DMA_ISR_GIF7_Msk
6927#define DMA_ISR_TCIF7_Pos (25U)
6928#define DMA_ISR_TCIF7_Msk (0x1UL << DMA_ISR_TCIF7_Pos)
6929#define DMA_ISR_TCIF7 DMA_ISR_TCIF7_Msk
6930#define DMA_ISR_HTIF7_Pos (26U)
6931#define DMA_ISR_HTIF7_Msk (0x1UL << DMA_ISR_HTIF7_Pos)
6932#define DMA_ISR_HTIF7 DMA_ISR_HTIF7_Msk
6933#define DMA_ISR_TEIF7_Pos (27U)
6934#define DMA_ISR_TEIF7_Msk (0x1UL << DMA_ISR_TEIF7_Pos)
6935#define DMA_ISR_TEIF7 DMA_ISR_TEIF7_Msk
6937/******************* Bit definition for DMA_IFCR register *******************/
6938#define DMA_IFCR_CGIF1_Pos (0U)
6939#define DMA_IFCR_CGIF1_Msk (0x1UL << DMA_IFCR_CGIF1_Pos)
6940#define DMA_IFCR_CGIF1 DMA_IFCR_CGIF1_Msk
6941#define DMA_IFCR_CTCIF1_Pos (1U)
6942#define DMA_IFCR_CTCIF1_Msk (0x1UL << DMA_IFCR_CTCIF1_Pos)
6943#define DMA_IFCR_CTCIF1 DMA_IFCR_CTCIF1_Msk
6944#define DMA_IFCR_CHTIF1_Pos (2U)
6945#define DMA_IFCR_CHTIF1_Msk (0x1UL << DMA_IFCR_CHTIF1_Pos)
6946#define DMA_IFCR_CHTIF1 DMA_IFCR_CHTIF1_Msk
6947#define DMA_IFCR_CTEIF1_Pos (3U)
6948#define DMA_IFCR_CTEIF1_Msk (0x1UL << DMA_IFCR_CTEIF1_Pos)
6949#define DMA_IFCR_CTEIF1 DMA_IFCR_CTEIF1_Msk
6950#define DMA_IFCR_CGIF2_Pos (4U)
6951#define DMA_IFCR_CGIF2_Msk (0x1UL << DMA_IFCR_CGIF2_Pos)
6952#define DMA_IFCR_CGIF2 DMA_IFCR_CGIF2_Msk
6953#define DMA_IFCR_CTCIF2_Pos (5U)
6954#define DMA_IFCR_CTCIF2_Msk (0x1UL << DMA_IFCR_CTCIF2_Pos)
6955#define DMA_IFCR_CTCIF2 DMA_IFCR_CTCIF2_Msk
6956#define DMA_IFCR_CHTIF2_Pos (6U)
6957#define DMA_IFCR_CHTIF2_Msk (0x1UL << DMA_IFCR_CHTIF2_Pos)
6958#define DMA_IFCR_CHTIF2 DMA_IFCR_CHTIF2_Msk
6959#define DMA_IFCR_CTEIF2_Pos (7U)
6960#define DMA_IFCR_CTEIF2_Msk (0x1UL << DMA_IFCR_CTEIF2_Pos)
6961#define DMA_IFCR_CTEIF2 DMA_IFCR_CTEIF2_Msk
6962#define DMA_IFCR_CGIF3_Pos (8U)
6963#define DMA_IFCR_CGIF3_Msk (0x1UL << DMA_IFCR_CGIF3_Pos)
6964#define DMA_IFCR_CGIF3 DMA_IFCR_CGIF3_Msk
6965#define DMA_IFCR_CTCIF3_Pos (9U)
6966#define DMA_IFCR_CTCIF3_Msk (0x1UL << DMA_IFCR_CTCIF3_Pos)
6967#define DMA_IFCR_CTCIF3 DMA_IFCR_CTCIF3_Msk
6968#define DMA_IFCR_CHTIF3_Pos (10U)
6969#define DMA_IFCR_CHTIF3_Msk (0x1UL << DMA_IFCR_CHTIF3_Pos)
6970#define DMA_IFCR_CHTIF3 DMA_IFCR_CHTIF3_Msk
6971#define DMA_IFCR_CTEIF3_Pos (11U)
6972#define DMA_IFCR_CTEIF3_Msk (0x1UL << DMA_IFCR_CTEIF3_Pos)
6973#define DMA_IFCR_CTEIF3 DMA_IFCR_CTEIF3_Msk
6974#define DMA_IFCR_CGIF4_Pos (12U)
6975#define DMA_IFCR_CGIF4_Msk (0x1UL << DMA_IFCR_CGIF4_Pos)
6976#define DMA_IFCR_CGIF4 DMA_IFCR_CGIF4_Msk
6977#define DMA_IFCR_CTCIF4_Pos (13U)
6978#define DMA_IFCR_CTCIF4_Msk (0x1UL << DMA_IFCR_CTCIF4_Pos)
6979#define DMA_IFCR_CTCIF4 DMA_IFCR_CTCIF4_Msk
6980#define DMA_IFCR_CHTIF4_Pos (14U)
6981#define DMA_IFCR_CHTIF4_Msk (0x1UL << DMA_IFCR_CHTIF4_Pos)
6982#define DMA_IFCR_CHTIF4 DMA_IFCR_CHTIF4_Msk
6983#define DMA_IFCR_CTEIF4_Pos (15U)
6984#define DMA_IFCR_CTEIF4_Msk (0x1UL << DMA_IFCR_CTEIF4_Pos)
6985#define DMA_IFCR_CTEIF4 DMA_IFCR_CTEIF4_Msk
6986#define DMA_IFCR_CGIF5_Pos (16U)
6987#define DMA_IFCR_CGIF5_Msk (0x1UL << DMA_IFCR_CGIF5_Pos)
6988#define DMA_IFCR_CGIF5 DMA_IFCR_CGIF5_Msk
6989#define DMA_IFCR_CTCIF5_Pos (17U)
6990#define DMA_IFCR_CTCIF5_Msk (0x1UL << DMA_IFCR_CTCIF5_Pos)
6991#define DMA_IFCR_CTCIF5 DMA_IFCR_CTCIF5_Msk
6992#define DMA_IFCR_CHTIF5_Pos (18U)
6993#define DMA_IFCR_CHTIF5_Msk (0x1UL << DMA_IFCR_CHTIF5_Pos)
6994#define DMA_IFCR_CHTIF5 DMA_IFCR_CHTIF5_Msk
6995#define DMA_IFCR_CTEIF5_Pos (19U)
6996#define DMA_IFCR_CTEIF5_Msk (0x1UL << DMA_IFCR_CTEIF5_Pos)
6997#define DMA_IFCR_CTEIF5 DMA_IFCR_CTEIF5_Msk
6998#define DMA_IFCR_CGIF6_Pos (20U)
6999#define DMA_IFCR_CGIF6_Msk (0x1UL << DMA_IFCR_CGIF6_Pos)
7000#define DMA_IFCR_CGIF6 DMA_IFCR_CGIF6_Msk
7001#define DMA_IFCR_CTCIF6_Pos (21U)
7002#define DMA_IFCR_CTCIF6_Msk (0x1UL << DMA_IFCR_CTCIF6_Pos)
7003#define DMA_IFCR_CTCIF6 DMA_IFCR_CTCIF6_Msk
7004#define DMA_IFCR_CHTIF6_Pos (22U)
7005#define DMA_IFCR_CHTIF6_Msk (0x1UL << DMA_IFCR_CHTIF6_Pos)
7006#define DMA_IFCR_CHTIF6 DMA_IFCR_CHTIF6_Msk
7007#define DMA_IFCR_CTEIF6_Pos (23U)
7008#define DMA_IFCR_CTEIF6_Msk (0x1UL << DMA_IFCR_CTEIF6_Pos)
7009#define DMA_IFCR_CTEIF6 DMA_IFCR_CTEIF6_Msk
7010#define DMA_IFCR_CGIF7_Pos (24U)
7011#define DMA_IFCR_CGIF7_Msk (0x1UL << DMA_IFCR_CGIF7_Pos)
7012#define DMA_IFCR_CGIF7 DMA_IFCR_CGIF7_Msk
7013#define DMA_IFCR_CTCIF7_Pos (25U)
7014#define DMA_IFCR_CTCIF7_Msk (0x1UL << DMA_IFCR_CTCIF7_Pos)
7015#define DMA_IFCR_CTCIF7 DMA_IFCR_CTCIF7_Msk
7016#define DMA_IFCR_CHTIF7_Pos (26U)
7017#define DMA_IFCR_CHTIF7_Msk (0x1UL << DMA_IFCR_CHTIF7_Pos)
7018#define DMA_IFCR_CHTIF7 DMA_IFCR_CHTIF7_Msk
7019#define DMA_IFCR_CTEIF7_Pos (27U)
7020#define DMA_IFCR_CTEIF7_Msk (0x1UL << DMA_IFCR_CTEIF7_Pos)
7021#define DMA_IFCR_CTEIF7 DMA_IFCR_CTEIF7_Msk
7023/******************* Bit definition for DMA_CCR register ********************/
7024#define DMA_CCR_EN_Pos (0U)
7025#define DMA_CCR_EN_Msk (0x1UL << DMA_CCR_EN_Pos)
7026#define DMA_CCR_EN DMA_CCR_EN_Msk
7027#define DMA_CCR_TCIE_Pos (1U)
7028#define DMA_CCR_TCIE_Msk (0x1UL << DMA_CCR_TCIE_Pos)
7029#define DMA_CCR_TCIE DMA_CCR_TCIE_Msk
7030#define DMA_CCR_HTIE_Pos (2U)
7031#define DMA_CCR_HTIE_Msk (0x1UL << DMA_CCR_HTIE_Pos)
7032#define DMA_CCR_HTIE DMA_CCR_HTIE_Msk
7033#define DMA_CCR_TEIE_Pos (3U)
7034#define DMA_CCR_TEIE_Msk (0x1UL << DMA_CCR_TEIE_Pos)
7035#define DMA_CCR_TEIE DMA_CCR_TEIE_Msk
7036#define DMA_CCR_DIR_Pos (4U)
7037#define DMA_CCR_DIR_Msk (0x1UL << DMA_CCR_DIR_Pos)
7038#define DMA_CCR_DIR DMA_CCR_DIR_Msk
7039#define DMA_CCR_CIRC_Pos (5U)
7040#define DMA_CCR_CIRC_Msk (0x1UL << DMA_CCR_CIRC_Pos)
7041#define DMA_CCR_CIRC DMA_CCR_CIRC_Msk
7042#define DMA_CCR_PINC_Pos (6U)
7043#define DMA_CCR_PINC_Msk (0x1UL << DMA_CCR_PINC_Pos)
7044#define DMA_CCR_PINC DMA_CCR_PINC_Msk
7045#define DMA_CCR_MINC_Pos (7U)
7046#define DMA_CCR_MINC_Msk (0x1UL << DMA_CCR_MINC_Pos)
7047#define DMA_CCR_MINC DMA_CCR_MINC_Msk
7049#define DMA_CCR_PSIZE_Pos (8U)
7050#define DMA_CCR_PSIZE_Msk (0x3UL << DMA_CCR_PSIZE_Pos)
7051#define DMA_CCR_PSIZE DMA_CCR_PSIZE_Msk
7052#define DMA_CCR_PSIZE_0 (0x1UL << DMA_CCR_PSIZE_Pos)
7053#define DMA_CCR_PSIZE_1 (0x2UL << DMA_CCR_PSIZE_Pos)
7055#define DMA_CCR_MSIZE_Pos (10U)
7056#define DMA_CCR_MSIZE_Msk (0x3UL << DMA_CCR_MSIZE_Pos)
7057#define DMA_CCR_MSIZE DMA_CCR_MSIZE_Msk
7058#define DMA_CCR_MSIZE_0 (0x1UL << DMA_CCR_MSIZE_Pos)
7059#define DMA_CCR_MSIZE_1 (0x2UL << DMA_CCR_MSIZE_Pos)
7061#define DMA_CCR_PL_Pos (12U)
7062#define DMA_CCR_PL_Msk (0x3UL << DMA_CCR_PL_Pos)
7063#define DMA_CCR_PL DMA_CCR_PL_Msk
7064#define DMA_CCR_PL_0 (0x1UL << DMA_CCR_PL_Pos)
7065#define DMA_CCR_PL_1 (0x2UL << DMA_CCR_PL_Pos)
7067#define DMA_CCR_MEM2MEM_Pos (14U)
7068#define DMA_CCR_MEM2MEM_Msk (0x1UL << DMA_CCR_MEM2MEM_Pos)
7069#define DMA_CCR_MEM2MEM DMA_CCR_MEM2MEM_Msk
7071/****************** Bit definition for DMA_CNDTR register *******************/
7072#define DMA_CNDTR_NDT_Pos (0U)
7073#define DMA_CNDTR_NDT_Msk (0xFFFFUL << DMA_CNDTR_NDT_Pos)
7074#define DMA_CNDTR_NDT DMA_CNDTR_NDT_Msk
7076/****************** Bit definition for DMA_CPAR register ********************/
7077#define DMA_CPAR_PA_Pos (0U)
7078#define DMA_CPAR_PA_Msk (0xFFFFFFFFUL << DMA_CPAR_PA_Pos)
7079#define DMA_CPAR_PA DMA_CPAR_PA_Msk
7081/****************** Bit definition for DMA_CMAR register ********************/
7082#define DMA_CMAR_MA_Pos (0U)
7083#define DMA_CMAR_MA_Msk (0xFFFFFFFFUL << DMA_CMAR_MA_Pos)
7084#define DMA_CMAR_MA DMA_CMAR_MA_Msk
7086/******************************************************************************/
7087/* */
7088/* External Interrupt/Event Controller (EXTI) */
7089/* */
7090/******************************************************************************/
7091/******************* Bit definition for EXTI_IMR register *******************/
7092#define EXTI_IMR_MR0_Pos (0U)
7093#define EXTI_IMR_MR0_Msk (0x1UL << EXTI_IMR_MR0_Pos)
7094#define EXTI_IMR_MR0 EXTI_IMR_MR0_Msk
7095#define EXTI_IMR_MR1_Pos (1U)
7096#define EXTI_IMR_MR1_Msk (0x1UL << EXTI_IMR_MR1_Pos)
7097#define EXTI_IMR_MR1 EXTI_IMR_MR1_Msk
7098#define EXTI_IMR_MR2_Pos (2U)
7099#define EXTI_IMR_MR2_Msk (0x1UL << EXTI_IMR_MR2_Pos)
7100#define EXTI_IMR_MR2 EXTI_IMR_MR2_Msk
7101#define EXTI_IMR_MR3_Pos (3U)
7102#define EXTI_IMR_MR3_Msk (0x1UL << EXTI_IMR_MR3_Pos)
7103#define EXTI_IMR_MR3 EXTI_IMR_MR3_Msk
7104#define EXTI_IMR_MR4_Pos (4U)
7105#define EXTI_IMR_MR4_Msk (0x1UL << EXTI_IMR_MR4_Pos)
7106#define EXTI_IMR_MR4 EXTI_IMR_MR4_Msk
7107#define EXTI_IMR_MR5_Pos (5U)
7108#define EXTI_IMR_MR5_Msk (0x1UL << EXTI_IMR_MR5_Pos)
7109#define EXTI_IMR_MR5 EXTI_IMR_MR5_Msk
7110#define EXTI_IMR_MR6_Pos (6U)
7111#define EXTI_IMR_MR6_Msk (0x1UL << EXTI_IMR_MR6_Pos)
7112#define EXTI_IMR_MR6 EXTI_IMR_MR6_Msk
7113#define EXTI_IMR_MR7_Pos (7U)
7114#define EXTI_IMR_MR7_Msk (0x1UL << EXTI_IMR_MR7_Pos)
7115#define EXTI_IMR_MR7 EXTI_IMR_MR7_Msk
7116#define EXTI_IMR_MR8_Pos (8U)
7117#define EXTI_IMR_MR8_Msk (0x1UL << EXTI_IMR_MR8_Pos)
7118#define EXTI_IMR_MR8 EXTI_IMR_MR8_Msk
7119#define EXTI_IMR_MR9_Pos (9U)
7120#define EXTI_IMR_MR9_Msk (0x1UL << EXTI_IMR_MR9_Pos)
7121#define EXTI_IMR_MR9 EXTI_IMR_MR9_Msk
7122#define EXTI_IMR_MR10_Pos (10U)
7123#define EXTI_IMR_MR10_Msk (0x1UL << EXTI_IMR_MR10_Pos)
7124#define EXTI_IMR_MR10 EXTI_IMR_MR10_Msk
7125#define EXTI_IMR_MR11_Pos (11U)
7126#define EXTI_IMR_MR11_Msk (0x1UL << EXTI_IMR_MR11_Pos)
7127#define EXTI_IMR_MR11 EXTI_IMR_MR11_Msk
7128#define EXTI_IMR_MR12_Pos (12U)
7129#define EXTI_IMR_MR12_Msk (0x1UL << EXTI_IMR_MR12_Pos)
7130#define EXTI_IMR_MR12 EXTI_IMR_MR12_Msk
7131#define EXTI_IMR_MR13_Pos (13U)
7132#define EXTI_IMR_MR13_Msk (0x1UL << EXTI_IMR_MR13_Pos)
7133#define EXTI_IMR_MR13 EXTI_IMR_MR13_Msk
7134#define EXTI_IMR_MR14_Pos (14U)
7135#define EXTI_IMR_MR14_Msk (0x1UL << EXTI_IMR_MR14_Pos)
7136#define EXTI_IMR_MR14 EXTI_IMR_MR14_Msk
7137#define EXTI_IMR_MR15_Pos (15U)
7138#define EXTI_IMR_MR15_Msk (0x1UL << EXTI_IMR_MR15_Pos)
7139#define EXTI_IMR_MR15 EXTI_IMR_MR15_Msk
7140#define EXTI_IMR_MR16_Pos (16U)
7141#define EXTI_IMR_MR16_Msk (0x1UL << EXTI_IMR_MR16_Pos)
7142#define EXTI_IMR_MR16 EXTI_IMR_MR16_Msk
7143#define EXTI_IMR_MR17_Pos (17U)
7144#define EXTI_IMR_MR17_Msk (0x1UL << EXTI_IMR_MR17_Pos)
7145#define EXTI_IMR_MR17 EXTI_IMR_MR17_Msk
7146#define EXTI_IMR_MR18_Pos (18U)
7147#define EXTI_IMR_MR18_Msk (0x1UL << EXTI_IMR_MR18_Pos)
7148#define EXTI_IMR_MR18 EXTI_IMR_MR18_Msk
7149#define EXTI_IMR_MR19_Pos (19U)
7150#define EXTI_IMR_MR19_Msk (0x1UL << EXTI_IMR_MR19_Pos)
7151#define EXTI_IMR_MR19 EXTI_IMR_MR19_Msk
7152#define EXTI_IMR_MR20_Pos (20U)
7153#define EXTI_IMR_MR20_Msk (0x1UL << EXTI_IMR_MR20_Pos)
7154#define EXTI_IMR_MR20 EXTI_IMR_MR20_Msk
7155#define EXTI_IMR_MR21_Pos (21U)
7156#define EXTI_IMR_MR21_Msk (0x1UL << EXTI_IMR_MR21_Pos)
7157#define EXTI_IMR_MR21 EXTI_IMR_MR21_Msk
7158#define EXTI_IMR_MR22_Pos (22U)
7159#define EXTI_IMR_MR22_Msk (0x1UL << EXTI_IMR_MR22_Pos)
7160#define EXTI_IMR_MR22 EXTI_IMR_MR22_Msk
7161#define EXTI_IMR_MR23_Pos (23U)
7162#define EXTI_IMR_MR23_Msk (0x1UL << EXTI_IMR_MR23_Pos)
7163#define EXTI_IMR_MR23 EXTI_IMR_MR23_Msk
7164#define EXTI_IMR_MR24_Pos (24U)
7165#define EXTI_IMR_MR24_Msk (0x1UL << EXTI_IMR_MR24_Pos)
7166#define EXTI_IMR_MR24 EXTI_IMR_MR24_Msk
7167#define EXTI_IMR_MR25_Pos (25U)
7168#define EXTI_IMR_MR25_Msk (0x1UL << EXTI_IMR_MR25_Pos)
7169#define EXTI_IMR_MR25 EXTI_IMR_MR25_Msk
7170#define EXTI_IMR_MR26_Pos (26U)
7171#define EXTI_IMR_MR26_Msk (0x1UL << EXTI_IMR_MR26_Pos)
7172#define EXTI_IMR_MR26 EXTI_IMR_MR26_Msk
7173#define EXTI_IMR_MR27_Pos (27U)
7174#define EXTI_IMR_MR27_Msk (0x1UL << EXTI_IMR_MR27_Pos)
7175#define EXTI_IMR_MR27 EXTI_IMR_MR27_Msk
7176#define EXTI_IMR_MR28_Pos (28U)
7177#define EXTI_IMR_MR28_Msk (0x1UL << EXTI_IMR_MR28_Pos)
7178#define EXTI_IMR_MR28 EXTI_IMR_MR28_Msk
7179#define EXTI_IMR_MR29_Pos (29U)
7180#define EXTI_IMR_MR29_Msk (0x1UL << EXTI_IMR_MR29_Pos)
7181#define EXTI_IMR_MR29 EXTI_IMR_MR29_Msk
7182#define EXTI_IMR_MR30_Pos (30U)
7183#define EXTI_IMR_MR30_Msk (0x1UL << EXTI_IMR_MR30_Pos)
7184#define EXTI_IMR_MR30 EXTI_IMR_MR30_Msk
7185#define EXTI_IMR_MR31_Pos (31U)
7186#define EXTI_IMR_MR31_Msk (0x1UL << EXTI_IMR_MR31_Pos)
7187#define EXTI_IMR_MR31 EXTI_IMR_MR31_Msk
7189/* References Defines */
7190#define EXTI_IMR_IM0 EXTI_IMR_MR0
7191#define EXTI_IMR_IM1 EXTI_IMR_MR1
7192#define EXTI_IMR_IM2 EXTI_IMR_MR2
7193#define EXTI_IMR_IM3 EXTI_IMR_MR3
7194#define EXTI_IMR_IM4 EXTI_IMR_MR4
7195#define EXTI_IMR_IM5 EXTI_IMR_MR5
7196#define EXTI_IMR_IM6 EXTI_IMR_MR6
7197#define EXTI_IMR_IM7 EXTI_IMR_MR7
7198#define EXTI_IMR_IM8 EXTI_IMR_MR8
7199#define EXTI_IMR_IM9 EXTI_IMR_MR9
7200#define EXTI_IMR_IM10 EXTI_IMR_MR10
7201#define EXTI_IMR_IM11 EXTI_IMR_MR11
7202#define EXTI_IMR_IM12 EXTI_IMR_MR12
7203#define EXTI_IMR_IM13 EXTI_IMR_MR13
7204#define EXTI_IMR_IM14 EXTI_IMR_MR14
7205#define EXTI_IMR_IM15 EXTI_IMR_MR15
7206#define EXTI_IMR_IM16 EXTI_IMR_MR16
7207#define EXTI_IMR_IM17 EXTI_IMR_MR17
7208#if defined(EXTI_IMR_MR18)
7209#define EXTI_IMR_IM18 EXTI_IMR_MR18
7210#endif
7211#define EXTI_IMR_IM19 EXTI_IMR_MR19
7212#define EXTI_IMR_IM20 EXTI_IMR_MR20
7213#if defined(EXTI_IMR_MR21)
7214#define EXTI_IMR_IM21 EXTI_IMR_MR21
7215#endif
7216#define EXTI_IMR_IM22 EXTI_IMR_MR22
7217#define EXTI_IMR_IM23 EXTI_IMR_MR23
7218#if defined(EXTI_IMR_MR24)
7219#define EXTI_IMR_IM24 EXTI_IMR_MR24
7220#endif
7221#define EXTI_IMR_IM25 EXTI_IMR_MR25
7222#if defined(EXTI_IMR_MR26)
7223#define EXTI_IMR_IM26 EXTI_IMR_MR26
7224#endif
7225#if defined(EXTI_IMR_MR27)
7226#define EXTI_IMR_IM27 EXTI_IMR_MR27
7227#endif
7228#if defined(EXTI_IMR_MR28)
7229#define EXTI_IMR_IM28 EXTI_IMR_MR28
7230#endif
7231#if defined(EXTI_IMR_MR29)
7232#define EXTI_IMR_IM29 EXTI_IMR_MR29
7233#endif
7234#if defined(EXTI_IMR_MR30)
7235#define EXTI_IMR_IM30 EXTI_IMR_MR30
7236#endif
7237#if defined(EXTI_IMR_MR31)
7238#define EXTI_IMR_IM31 EXTI_IMR_MR31
7239#endif
7240
7241#define EXTI_IMR_IM_Pos (0U)
7242#define EXTI_IMR_IM_Msk (0xFFFFFFFFUL << EXTI_IMR_IM_Pos)
7243#define EXTI_IMR_IM EXTI_IMR_IM_Msk
7245/******************* Bit definition for EXTI_EMR register *******************/
7246#define EXTI_EMR_MR0_Pos (0U)
7247#define EXTI_EMR_MR0_Msk (0x1UL << EXTI_EMR_MR0_Pos)
7248#define EXTI_EMR_MR0 EXTI_EMR_MR0_Msk
7249#define EXTI_EMR_MR1_Pos (1U)
7250#define EXTI_EMR_MR1_Msk (0x1UL << EXTI_EMR_MR1_Pos)
7251#define EXTI_EMR_MR1 EXTI_EMR_MR1_Msk
7252#define EXTI_EMR_MR2_Pos (2U)
7253#define EXTI_EMR_MR2_Msk (0x1UL << EXTI_EMR_MR2_Pos)
7254#define EXTI_EMR_MR2 EXTI_EMR_MR2_Msk
7255#define EXTI_EMR_MR3_Pos (3U)
7256#define EXTI_EMR_MR3_Msk (0x1UL << EXTI_EMR_MR3_Pos)
7257#define EXTI_EMR_MR3 EXTI_EMR_MR3_Msk
7258#define EXTI_EMR_MR4_Pos (4U)
7259#define EXTI_EMR_MR4_Msk (0x1UL << EXTI_EMR_MR4_Pos)
7260#define EXTI_EMR_MR4 EXTI_EMR_MR4_Msk
7261#define EXTI_EMR_MR5_Pos (5U)
7262#define EXTI_EMR_MR5_Msk (0x1UL << EXTI_EMR_MR5_Pos)
7263#define EXTI_EMR_MR5 EXTI_EMR_MR5_Msk
7264#define EXTI_EMR_MR6_Pos (6U)
7265#define EXTI_EMR_MR6_Msk (0x1UL << EXTI_EMR_MR6_Pos)
7266#define EXTI_EMR_MR6 EXTI_EMR_MR6_Msk
7267#define EXTI_EMR_MR7_Pos (7U)
7268#define EXTI_EMR_MR7_Msk (0x1UL << EXTI_EMR_MR7_Pos)
7269#define EXTI_EMR_MR7 EXTI_EMR_MR7_Msk
7270#define EXTI_EMR_MR8_Pos (8U)
7271#define EXTI_EMR_MR8_Msk (0x1UL << EXTI_EMR_MR8_Pos)
7272#define EXTI_EMR_MR8 EXTI_EMR_MR8_Msk
7273#define EXTI_EMR_MR9_Pos (9U)
7274#define EXTI_EMR_MR9_Msk (0x1UL << EXTI_EMR_MR9_Pos)
7275#define EXTI_EMR_MR9 EXTI_EMR_MR9_Msk
7276#define EXTI_EMR_MR10_Pos (10U)
7277#define EXTI_EMR_MR10_Msk (0x1UL << EXTI_EMR_MR10_Pos)
7278#define EXTI_EMR_MR10 EXTI_EMR_MR10_Msk
7279#define EXTI_EMR_MR11_Pos (11U)
7280#define EXTI_EMR_MR11_Msk (0x1UL << EXTI_EMR_MR11_Pos)
7281#define EXTI_EMR_MR11 EXTI_EMR_MR11_Msk
7282#define EXTI_EMR_MR12_Pos (12U)
7283#define EXTI_EMR_MR12_Msk (0x1UL << EXTI_EMR_MR12_Pos)
7284#define EXTI_EMR_MR12 EXTI_EMR_MR12_Msk
7285#define EXTI_EMR_MR13_Pos (13U)
7286#define EXTI_EMR_MR13_Msk (0x1UL << EXTI_EMR_MR13_Pos)
7287#define EXTI_EMR_MR13 EXTI_EMR_MR13_Msk
7288#define EXTI_EMR_MR14_Pos (14U)
7289#define EXTI_EMR_MR14_Msk (0x1UL << EXTI_EMR_MR14_Pos)
7290#define EXTI_EMR_MR14 EXTI_EMR_MR14_Msk
7291#define EXTI_EMR_MR15_Pos (15U)
7292#define EXTI_EMR_MR15_Msk (0x1UL << EXTI_EMR_MR15_Pos)
7293#define EXTI_EMR_MR15 EXTI_EMR_MR15_Msk
7294#define EXTI_EMR_MR16_Pos (16U)
7295#define EXTI_EMR_MR16_Msk (0x1UL << EXTI_EMR_MR16_Pos)
7296#define EXTI_EMR_MR16 EXTI_EMR_MR16_Msk
7297#define EXTI_EMR_MR17_Pos (17U)
7298#define EXTI_EMR_MR17_Msk (0x1UL << EXTI_EMR_MR17_Pos)
7299#define EXTI_EMR_MR17 EXTI_EMR_MR17_Msk
7300#define EXTI_EMR_MR18_Pos (18U)
7301#define EXTI_EMR_MR18_Msk (0x1UL << EXTI_EMR_MR18_Pos)
7302#define EXTI_EMR_MR18 EXTI_EMR_MR18_Msk
7303#define EXTI_EMR_MR19_Pos (19U)
7304#define EXTI_EMR_MR19_Msk (0x1UL << EXTI_EMR_MR19_Pos)
7305#define EXTI_EMR_MR19 EXTI_EMR_MR19_Msk
7306#define EXTI_EMR_MR20_Pos (20U)
7307#define EXTI_EMR_MR20_Msk (0x1UL << EXTI_EMR_MR20_Pos)
7308#define EXTI_EMR_MR20 EXTI_EMR_MR20_Msk
7309#define EXTI_EMR_MR21_Pos (21U)
7310#define EXTI_EMR_MR21_Msk (0x1UL << EXTI_EMR_MR21_Pos)
7311#define EXTI_EMR_MR21 EXTI_EMR_MR21_Msk
7312#define EXTI_EMR_MR22_Pos (22U)
7313#define EXTI_EMR_MR22_Msk (0x1UL << EXTI_EMR_MR22_Pos)
7314#define EXTI_EMR_MR22 EXTI_EMR_MR22_Msk
7315#define EXTI_EMR_MR23_Pos (23U)
7316#define EXTI_EMR_MR23_Msk (0x1UL << EXTI_EMR_MR23_Pos)
7317#define EXTI_EMR_MR23 EXTI_EMR_MR23_Msk
7318#define EXTI_EMR_MR24_Pos (24U)
7319#define EXTI_EMR_MR24_Msk (0x1UL << EXTI_EMR_MR24_Pos)
7320#define EXTI_EMR_MR24 EXTI_EMR_MR24_Msk
7321#define EXTI_EMR_MR25_Pos (25U)
7322#define EXTI_EMR_MR25_Msk (0x1UL << EXTI_EMR_MR25_Pos)
7323#define EXTI_EMR_MR25 EXTI_EMR_MR25_Msk
7324#define EXTI_EMR_MR26_Pos (26U)
7325#define EXTI_EMR_MR26_Msk (0x1UL << EXTI_EMR_MR26_Pos)
7326#define EXTI_EMR_MR26 EXTI_EMR_MR26_Msk
7327#define EXTI_EMR_MR27_Pos (27U)
7328#define EXTI_EMR_MR27_Msk (0x1UL << EXTI_EMR_MR27_Pos)
7329#define EXTI_EMR_MR27 EXTI_EMR_MR27_Msk
7330#define EXTI_EMR_MR28_Pos (28U)
7331#define EXTI_EMR_MR28_Msk (0x1UL << EXTI_EMR_MR28_Pos)
7332#define EXTI_EMR_MR28 EXTI_EMR_MR28_Msk
7333#define EXTI_EMR_MR29_Pos (29U)
7334#define EXTI_EMR_MR29_Msk (0x1UL << EXTI_EMR_MR29_Pos)
7335#define EXTI_EMR_MR29 EXTI_EMR_MR29_Msk
7336#define EXTI_EMR_MR30_Pos (30U)
7337#define EXTI_EMR_MR30_Msk (0x1UL << EXTI_EMR_MR30_Pos)
7338#define EXTI_EMR_MR30 EXTI_EMR_MR30_Msk
7339#define EXTI_EMR_MR31_Pos (31U)
7340#define EXTI_EMR_MR31_Msk (0x1UL << EXTI_EMR_MR31_Pos)
7341#define EXTI_EMR_MR31 EXTI_EMR_MR31_Msk
7343/* References Defines */
7344#define EXTI_EMR_EM0 EXTI_EMR_MR0
7345#define EXTI_EMR_EM1 EXTI_EMR_MR1
7346#define EXTI_EMR_EM2 EXTI_EMR_MR2
7347#define EXTI_EMR_EM3 EXTI_EMR_MR3
7348#define EXTI_EMR_EM4 EXTI_EMR_MR4
7349#define EXTI_EMR_EM5 EXTI_EMR_MR5
7350#define EXTI_EMR_EM6 EXTI_EMR_MR6
7351#define EXTI_EMR_EM7 EXTI_EMR_MR7
7352#define EXTI_EMR_EM8 EXTI_EMR_MR8
7353#define EXTI_EMR_EM9 EXTI_EMR_MR9
7354#define EXTI_EMR_EM10 EXTI_EMR_MR10
7355#define EXTI_EMR_EM11 EXTI_EMR_MR11
7356#define EXTI_EMR_EM12 EXTI_EMR_MR12
7357#define EXTI_EMR_EM13 EXTI_EMR_MR13
7358#define EXTI_EMR_EM14 EXTI_EMR_MR14
7359#define EXTI_EMR_EM15 EXTI_EMR_MR15
7360#define EXTI_EMR_EM16 EXTI_EMR_MR16
7361#define EXTI_EMR_EM17 EXTI_EMR_MR17
7362#if defined(EXTI_EMR_MR18)
7363#define EXTI_EMR_EM18 EXTI_EMR_MR18
7364#endif
7365#define EXTI_EMR_EM19 EXTI_EMR_MR19
7366#define EXTI_EMR_EM20 EXTI_EMR_MR20
7367#if defined(EXTI_EMR_MR21)
7368#define EXTI_EMR_EM21 EXTI_EMR_MR21
7369#endif
7370#define EXTI_EMR_EM22 EXTI_EMR_MR22
7371#define EXTI_EMR_EM23 EXTI_EMR_MR23
7372#if defined(EXTI_EMR_MR24)
7373#define EXTI_EMR_EM24 EXTI_EMR_MR24
7374#endif
7375#define EXTI_EMR_EM25 EXTI_EMR_MR25
7376#if defined(EXTI_EMR_MR26)
7377#define EXTI_EMR_EM26 EXTI_EMR_MR26
7378#endif
7379#if defined(EXTI_EMR_MR27)
7380#define EXTI_EMR_EM27 EXTI_EMR_MR27
7381#endif
7382#if defined(EXTI_EMR_MR28)
7383#define EXTI_EMR_EM28 EXTI_EMR_MR28
7384#endif
7385#if defined(EXTI_EMR_MR29)
7386#define EXTI_EMR_EM29 EXTI_EMR_MR29
7387#endif
7388#if defined(EXTI_EMR_MR30)
7389#define EXTI_EMR_EM30 EXTI_EMR_MR30
7390#endif
7391#if defined(EXTI_EMR_MR31)
7392#define EXTI_EMR_EM31 EXTI_EMR_MR31
7393#endif
7394
7395/****************** Bit definition for EXTI_RTSR register *******************/
7396#define EXTI_RTSR_TR0_Pos (0U)
7397#define EXTI_RTSR_TR0_Msk (0x1UL << EXTI_RTSR_TR0_Pos)
7398#define EXTI_RTSR_TR0 EXTI_RTSR_TR0_Msk
7399#define EXTI_RTSR_TR1_Pos (1U)
7400#define EXTI_RTSR_TR1_Msk (0x1UL << EXTI_RTSR_TR1_Pos)
7401#define EXTI_RTSR_TR1 EXTI_RTSR_TR1_Msk
7402#define EXTI_RTSR_TR2_Pos (2U)
7403#define EXTI_RTSR_TR2_Msk (0x1UL << EXTI_RTSR_TR2_Pos)
7404#define EXTI_RTSR_TR2 EXTI_RTSR_TR2_Msk
7405#define EXTI_RTSR_TR3_Pos (3U)
7406#define EXTI_RTSR_TR3_Msk (0x1UL << EXTI_RTSR_TR3_Pos)
7407#define EXTI_RTSR_TR3 EXTI_RTSR_TR3_Msk
7408#define EXTI_RTSR_TR4_Pos (4U)
7409#define EXTI_RTSR_TR4_Msk (0x1UL << EXTI_RTSR_TR4_Pos)
7410#define EXTI_RTSR_TR4 EXTI_RTSR_TR4_Msk
7411#define EXTI_RTSR_TR5_Pos (5U)
7412#define EXTI_RTSR_TR5_Msk (0x1UL << EXTI_RTSR_TR5_Pos)
7413#define EXTI_RTSR_TR5 EXTI_RTSR_TR5_Msk
7414#define EXTI_RTSR_TR6_Pos (6U)
7415#define EXTI_RTSR_TR6_Msk (0x1UL << EXTI_RTSR_TR6_Pos)
7416#define EXTI_RTSR_TR6 EXTI_RTSR_TR6_Msk
7417#define EXTI_RTSR_TR7_Pos (7U)
7418#define EXTI_RTSR_TR7_Msk (0x1UL << EXTI_RTSR_TR7_Pos)
7419#define EXTI_RTSR_TR7 EXTI_RTSR_TR7_Msk
7420#define EXTI_RTSR_TR8_Pos (8U)
7421#define EXTI_RTSR_TR8_Msk (0x1UL << EXTI_RTSR_TR8_Pos)
7422#define EXTI_RTSR_TR8 EXTI_RTSR_TR8_Msk
7423#define EXTI_RTSR_TR9_Pos (9U)
7424#define EXTI_RTSR_TR9_Msk (0x1UL << EXTI_RTSR_TR9_Pos)
7425#define EXTI_RTSR_TR9 EXTI_RTSR_TR9_Msk
7426#define EXTI_RTSR_TR10_Pos (10U)
7427#define EXTI_RTSR_TR10_Msk (0x1UL << EXTI_RTSR_TR10_Pos)
7428#define EXTI_RTSR_TR10 EXTI_RTSR_TR10_Msk
7429#define EXTI_RTSR_TR11_Pos (11U)
7430#define EXTI_RTSR_TR11_Msk (0x1UL << EXTI_RTSR_TR11_Pos)
7431#define EXTI_RTSR_TR11 EXTI_RTSR_TR11_Msk
7432#define EXTI_RTSR_TR12_Pos (12U)
7433#define EXTI_RTSR_TR12_Msk (0x1UL << EXTI_RTSR_TR12_Pos)
7434#define EXTI_RTSR_TR12 EXTI_RTSR_TR12_Msk
7435#define EXTI_RTSR_TR13_Pos (13U)
7436#define EXTI_RTSR_TR13_Msk (0x1UL << EXTI_RTSR_TR13_Pos)
7437#define EXTI_RTSR_TR13 EXTI_RTSR_TR13_Msk
7438#define EXTI_RTSR_TR14_Pos (14U)
7439#define EXTI_RTSR_TR14_Msk (0x1UL << EXTI_RTSR_TR14_Pos)
7440#define EXTI_RTSR_TR14 EXTI_RTSR_TR14_Msk
7441#define EXTI_RTSR_TR15_Pos (15U)
7442#define EXTI_RTSR_TR15_Msk (0x1UL << EXTI_RTSR_TR15_Pos)
7443#define EXTI_RTSR_TR15 EXTI_RTSR_TR15_Msk
7444#define EXTI_RTSR_TR16_Pos (16U)
7445#define EXTI_RTSR_TR16_Msk (0x1UL << EXTI_RTSR_TR16_Pos)
7446#define EXTI_RTSR_TR16 EXTI_RTSR_TR16_Msk
7447#define EXTI_RTSR_TR17_Pos (17U)
7448#define EXTI_RTSR_TR17_Msk (0x1UL << EXTI_RTSR_TR17_Pos)
7449#define EXTI_RTSR_TR17 EXTI_RTSR_TR17_Msk
7450#define EXTI_RTSR_TR18_Pos (18U)
7451#define EXTI_RTSR_TR18_Msk (0x1UL << EXTI_RTSR_TR18_Pos)
7452#define EXTI_RTSR_TR18 EXTI_RTSR_TR18_Msk
7453#define EXTI_RTSR_TR19_Pos (19U)
7454#define EXTI_RTSR_TR19_Msk (0x1UL << EXTI_RTSR_TR19_Pos)
7455#define EXTI_RTSR_TR19 EXTI_RTSR_TR19_Msk
7456#define EXTI_RTSR_TR20_Pos (20U)
7457#define EXTI_RTSR_TR20_Msk (0x1UL << EXTI_RTSR_TR20_Pos)
7458#define EXTI_RTSR_TR20 EXTI_RTSR_TR20_Msk
7459#define EXTI_RTSR_TR21_Pos (21U)
7460#define EXTI_RTSR_TR21_Msk (0x1UL << EXTI_RTSR_TR21_Pos)
7461#define EXTI_RTSR_TR21 EXTI_RTSR_TR21_Msk
7462#define EXTI_RTSR_TR22_Pos (22U)
7463#define EXTI_RTSR_TR22_Msk (0x1UL << EXTI_RTSR_TR22_Pos)
7464#define EXTI_RTSR_TR22 EXTI_RTSR_TR22_Msk
7465#define EXTI_RTSR_TR29_Pos (29U)
7466#define EXTI_RTSR_TR29_Msk (0x1UL << EXTI_RTSR_TR29_Pos)
7467#define EXTI_RTSR_TR29 EXTI_RTSR_TR29_Msk
7468#define EXTI_RTSR_TR30_Pos (30U)
7469#define EXTI_RTSR_TR30_Msk (0x1UL << EXTI_RTSR_TR30_Pos)
7470#define EXTI_RTSR_TR30 EXTI_RTSR_TR30_Msk
7471#define EXTI_RTSR_TR31_Pos (31U)
7472#define EXTI_RTSR_TR31_Msk (0x1UL << EXTI_RTSR_TR31_Pos)
7473#define EXTI_RTSR_TR31 EXTI_RTSR_TR31_Msk
7475/* References Defines */
7476#define EXTI_RTSR_RT0 EXTI_RTSR_TR0
7477#define EXTI_RTSR_RT1 EXTI_RTSR_TR1
7478#define EXTI_RTSR_RT2 EXTI_RTSR_TR2
7479#define EXTI_RTSR_RT3 EXTI_RTSR_TR3
7480#define EXTI_RTSR_RT4 EXTI_RTSR_TR4
7481#define EXTI_RTSR_RT5 EXTI_RTSR_TR5
7482#define EXTI_RTSR_RT6 EXTI_RTSR_TR6
7483#define EXTI_RTSR_RT7 EXTI_RTSR_TR7
7484#define EXTI_RTSR_RT8 EXTI_RTSR_TR8
7485#define EXTI_RTSR_RT9 EXTI_RTSR_TR9
7486#define EXTI_RTSR_RT10 EXTI_RTSR_TR10
7487#define EXTI_RTSR_RT11 EXTI_RTSR_TR11
7488#define EXTI_RTSR_RT12 EXTI_RTSR_TR12
7489#define EXTI_RTSR_RT13 EXTI_RTSR_TR13
7490#define EXTI_RTSR_RT14 EXTI_RTSR_TR14
7491#define EXTI_RTSR_RT15 EXTI_RTSR_TR15
7492#define EXTI_RTSR_RT16 EXTI_RTSR_TR16
7493#define EXTI_RTSR_RT17 EXTI_RTSR_TR17
7494#if defined(EXTI_RTSR_TR18)
7495#define EXTI_RTSR_RT18 EXTI_RTSR_TR18
7496#endif
7497#define EXTI_RTSR_RT19 EXTI_RTSR_TR19
7498#define EXTI_RTSR_RT20 EXTI_RTSR_TR20
7499#if defined(EXTI_RTSR_TR21)
7500#define EXTI_RTSR_RT21 EXTI_RTSR_TR21
7501#endif
7502#define EXTI_RTSR_RT22 EXTI_RTSR_TR22
7503#if defined(EXTI_RTSR_TR23)
7504#define EXTI_RTSR_RT23 EXTI_RTSR_TR23
7505#endif
7506#if defined(EXTI_RTSR_TR24)
7507#define EXTI_RTSR_RT24 EXTI_RTSR_TR24
7508#endif
7509#if defined(EXTI_RTSR_TR25)
7510#define EXTI_RTSR_RT25 EXTI_RTSR_TR25
7511#endif
7512#if defined(EXTI_RTSR_TR26)
7513#define EXTI_RTSR_RT26 EXTI_RTSR_TR26
7514#endif
7515#if defined(EXTI_RTSR_TR27)
7516#define EXTI_RTSR_RT27 EXTI_RTSR_TR27
7517#endif
7518#if defined(EXTI_RTSR_TR28)
7519#define EXTI_RTSR_RT28 EXTI_RTSR_TR28
7520#endif
7521#if defined(EXTI_RTSR_TR29)
7522#define EXTI_RTSR_RT29 EXTI_RTSR_TR29
7523#endif
7524#if defined(EXTI_RTSR_TR30)
7525#define EXTI_RTSR_RT30 EXTI_RTSR_TR30
7526#endif
7527#if defined(EXTI_RTSR_TR31)
7528#define EXTI_RTSR_RT31 EXTI_RTSR_TR31
7529#endif
7530
7531/****************** Bit definition for EXTI_FTSR register *******************/
7532#define EXTI_FTSR_TR0_Pos (0U)
7533#define EXTI_FTSR_TR0_Msk (0x1UL << EXTI_FTSR_TR0_Pos)
7534#define EXTI_FTSR_TR0 EXTI_FTSR_TR0_Msk
7535#define EXTI_FTSR_TR1_Pos (1U)
7536#define EXTI_FTSR_TR1_Msk (0x1UL << EXTI_FTSR_TR1_Pos)
7537#define EXTI_FTSR_TR1 EXTI_FTSR_TR1_Msk
7538#define EXTI_FTSR_TR2_Pos (2U)
7539#define EXTI_FTSR_TR2_Msk (0x1UL << EXTI_FTSR_TR2_Pos)
7540#define EXTI_FTSR_TR2 EXTI_FTSR_TR2_Msk
7541#define EXTI_FTSR_TR3_Pos (3U)
7542#define EXTI_FTSR_TR3_Msk (0x1UL << EXTI_FTSR_TR3_Pos)
7543#define EXTI_FTSR_TR3 EXTI_FTSR_TR3_Msk
7544#define EXTI_FTSR_TR4_Pos (4U)
7545#define EXTI_FTSR_TR4_Msk (0x1UL << EXTI_FTSR_TR4_Pos)
7546#define EXTI_FTSR_TR4 EXTI_FTSR_TR4_Msk
7547#define EXTI_FTSR_TR5_Pos (5U)
7548#define EXTI_FTSR_TR5_Msk (0x1UL << EXTI_FTSR_TR5_Pos)
7549#define EXTI_FTSR_TR5 EXTI_FTSR_TR5_Msk
7550#define EXTI_FTSR_TR6_Pos (6U)
7551#define EXTI_FTSR_TR6_Msk (0x1UL << EXTI_FTSR_TR6_Pos)
7552#define EXTI_FTSR_TR6 EXTI_FTSR_TR6_Msk
7553#define EXTI_FTSR_TR7_Pos (7U)
7554#define EXTI_FTSR_TR7_Msk (0x1UL << EXTI_FTSR_TR7_Pos)
7555#define EXTI_FTSR_TR7 EXTI_FTSR_TR7_Msk
7556#define EXTI_FTSR_TR8_Pos (8U)
7557#define EXTI_FTSR_TR8_Msk (0x1UL << EXTI_FTSR_TR8_Pos)
7558#define EXTI_FTSR_TR8 EXTI_FTSR_TR8_Msk
7559#define EXTI_FTSR_TR9_Pos (9U)
7560#define EXTI_FTSR_TR9_Msk (0x1UL << EXTI_FTSR_TR9_Pos)
7561#define EXTI_FTSR_TR9 EXTI_FTSR_TR9_Msk
7562#define EXTI_FTSR_TR10_Pos (10U)
7563#define EXTI_FTSR_TR10_Msk (0x1UL << EXTI_FTSR_TR10_Pos)
7564#define EXTI_FTSR_TR10 EXTI_FTSR_TR10_Msk
7565#define EXTI_FTSR_TR11_Pos (11U)
7566#define EXTI_FTSR_TR11_Msk (0x1UL << EXTI_FTSR_TR11_Pos)
7567#define EXTI_FTSR_TR11 EXTI_FTSR_TR11_Msk
7568#define EXTI_FTSR_TR12_Pos (12U)
7569#define EXTI_FTSR_TR12_Msk (0x1UL << EXTI_FTSR_TR12_Pos)
7570#define EXTI_FTSR_TR12 EXTI_FTSR_TR12_Msk
7571#define EXTI_FTSR_TR13_Pos (13U)
7572#define EXTI_FTSR_TR13_Msk (0x1UL << EXTI_FTSR_TR13_Pos)
7573#define EXTI_FTSR_TR13 EXTI_FTSR_TR13_Msk
7574#define EXTI_FTSR_TR14_Pos (14U)
7575#define EXTI_FTSR_TR14_Msk (0x1UL << EXTI_FTSR_TR14_Pos)
7576#define EXTI_FTSR_TR14 EXTI_FTSR_TR14_Msk
7577#define EXTI_FTSR_TR15_Pos (15U)
7578#define EXTI_FTSR_TR15_Msk (0x1UL << EXTI_FTSR_TR15_Pos)
7579#define EXTI_FTSR_TR15 EXTI_FTSR_TR15_Msk
7580#define EXTI_FTSR_TR16_Pos (16U)
7581#define EXTI_FTSR_TR16_Msk (0x1UL << EXTI_FTSR_TR16_Pos)
7582#define EXTI_FTSR_TR16 EXTI_FTSR_TR16_Msk
7583#define EXTI_FTSR_TR17_Pos (17U)
7584#define EXTI_FTSR_TR17_Msk (0x1UL << EXTI_FTSR_TR17_Pos)
7585#define EXTI_FTSR_TR17 EXTI_FTSR_TR17_Msk
7586#define EXTI_FTSR_TR18_Pos (18U)
7587#define EXTI_FTSR_TR18_Msk (0x1UL << EXTI_FTSR_TR18_Pos)
7588#define EXTI_FTSR_TR18 EXTI_FTSR_TR18_Msk
7589#define EXTI_FTSR_TR19_Pos (19U)
7590#define EXTI_FTSR_TR19_Msk (0x1UL << EXTI_FTSR_TR19_Pos)
7591#define EXTI_FTSR_TR19 EXTI_FTSR_TR19_Msk
7592#define EXTI_FTSR_TR20_Pos (20U)
7593#define EXTI_FTSR_TR20_Msk (0x1UL << EXTI_FTSR_TR20_Pos)
7594#define EXTI_FTSR_TR20 EXTI_FTSR_TR20_Msk
7595#define EXTI_FTSR_TR21_Pos (21U)
7596#define EXTI_FTSR_TR21_Msk (0x1UL << EXTI_FTSR_TR21_Pos)
7597#define EXTI_FTSR_TR21 EXTI_FTSR_TR21_Msk
7598#define EXTI_FTSR_TR22_Pos (22U)
7599#define EXTI_FTSR_TR22_Msk (0x1UL << EXTI_FTSR_TR22_Pos)
7600#define EXTI_FTSR_TR22 EXTI_FTSR_TR22_Msk
7601#define EXTI_FTSR_TR29_Pos (29U)
7602#define EXTI_FTSR_TR29_Msk (0x1UL << EXTI_FTSR_TR29_Pos)
7603#define EXTI_FTSR_TR29 EXTI_FTSR_TR29_Msk
7604#define EXTI_FTSR_TR30_Pos (30U)
7605#define EXTI_FTSR_TR30_Msk (0x1UL << EXTI_FTSR_TR30_Pos)
7606#define EXTI_FTSR_TR30 EXTI_FTSR_TR30_Msk
7607#define EXTI_FTSR_TR31_Pos (31U)
7608#define EXTI_FTSR_TR31_Msk (0x1UL << EXTI_FTSR_TR31_Pos)
7609#define EXTI_FTSR_TR31 EXTI_FTSR_TR31_Msk
7611/* References Defines */
7612#define EXTI_FTSR_FT0 EXTI_FTSR_TR0
7613#define EXTI_FTSR_FT1 EXTI_FTSR_TR1
7614#define EXTI_FTSR_FT2 EXTI_FTSR_TR2
7615#define EXTI_FTSR_FT3 EXTI_FTSR_TR3
7616#define EXTI_FTSR_FT4 EXTI_FTSR_TR4
7617#define EXTI_FTSR_FT5 EXTI_FTSR_TR5
7618#define EXTI_FTSR_FT6 EXTI_FTSR_TR6
7619#define EXTI_FTSR_FT7 EXTI_FTSR_TR7
7620#define EXTI_FTSR_FT8 EXTI_FTSR_TR8
7621#define EXTI_FTSR_FT9 EXTI_FTSR_TR9
7622#define EXTI_FTSR_FT10 EXTI_FTSR_TR10
7623#define EXTI_FTSR_FT11 EXTI_FTSR_TR11
7624#define EXTI_FTSR_FT12 EXTI_FTSR_TR12
7625#define EXTI_FTSR_FT13 EXTI_FTSR_TR13
7626#define EXTI_FTSR_FT14 EXTI_FTSR_TR14
7627#define EXTI_FTSR_FT15 EXTI_FTSR_TR15
7628#define EXTI_FTSR_FT16 EXTI_FTSR_TR16
7629#define EXTI_FTSR_FT17 EXTI_FTSR_TR17
7630#if defined(EXTI_FTSR_TR18)
7631#define EXTI_FTSR_FT18 EXTI_FTSR_TR18
7632#endif
7633#define EXTI_FTSR_FT19 EXTI_FTSR_TR19
7634#define EXTI_FTSR_FT20 EXTI_FTSR_TR20
7635#if defined(EXTI_FTSR_TR21)
7636#define EXTI_FTSR_FT21 EXTI_FTSR_TR21
7637#endif
7638#define EXTI_FTSR_FT22 EXTI_FTSR_TR22
7639#if defined(EXTI_FTSR_TR23)
7640#define EXTI_FTSR_FT23 EXTI_FTSR_TR23
7641#endif
7642#if defined(EXTI_FTSR_TR24)
7643#define EXTI_FTSR_FT24 EXTI_FTSR_TR24
7644#endif
7645#if defined(EXTI_FTSR_TR25)
7646#define EXTI_FTSR_FT25 EXTI_FTSR_TR25
7647#endif
7648#if defined(EXTI_FTSR_TR26)
7649#define EXTI_FTSR_FT26 EXTI_FTSR_TR26
7650#endif
7651#if defined(EXTI_FTSR_TR27)
7652#define EXTI_FTSR_FT27 EXTI_FTSR_TR27
7653#endif
7654#if defined(EXTI_FTSR_TR28)
7655#define EXTI_FTSR_FT28 EXTI_FTSR_TR28
7656#endif
7657#if defined(EXTI_FTSR_TR29)
7658#define EXTI_FTSR_FT29 EXTI_FTSR_TR29
7659#endif
7660#if defined(EXTI_FTSR_TR30)
7661#define EXTI_FTSR_FT30 EXTI_FTSR_TR30
7662#endif
7663#if defined(EXTI_FTSR_TR31)
7664#define EXTI_FTSR_FT31 EXTI_FTSR_TR31
7665#endif
7666
7667/****************** Bit definition for EXTI_SWIER register ******************/
7668#define EXTI_SWIER_SWIER0_Pos (0U)
7669#define EXTI_SWIER_SWIER0_Msk (0x1UL << EXTI_SWIER_SWIER0_Pos)
7670#define EXTI_SWIER_SWIER0 EXTI_SWIER_SWIER0_Msk
7671#define EXTI_SWIER_SWIER1_Pos (1U)
7672#define EXTI_SWIER_SWIER1_Msk (0x1UL << EXTI_SWIER_SWIER1_Pos)
7673#define EXTI_SWIER_SWIER1 EXTI_SWIER_SWIER1_Msk
7674#define EXTI_SWIER_SWIER2_Pos (2U)
7675#define EXTI_SWIER_SWIER2_Msk (0x1UL << EXTI_SWIER_SWIER2_Pos)
7676#define EXTI_SWIER_SWIER2 EXTI_SWIER_SWIER2_Msk
7677#define EXTI_SWIER_SWIER3_Pos (3U)
7678#define EXTI_SWIER_SWIER3_Msk (0x1UL << EXTI_SWIER_SWIER3_Pos)
7679#define EXTI_SWIER_SWIER3 EXTI_SWIER_SWIER3_Msk
7680#define EXTI_SWIER_SWIER4_Pos (4U)
7681#define EXTI_SWIER_SWIER4_Msk (0x1UL << EXTI_SWIER_SWIER4_Pos)
7682#define EXTI_SWIER_SWIER4 EXTI_SWIER_SWIER4_Msk
7683#define EXTI_SWIER_SWIER5_Pos (5U)
7684#define EXTI_SWIER_SWIER5_Msk (0x1UL << EXTI_SWIER_SWIER5_Pos)
7685#define EXTI_SWIER_SWIER5 EXTI_SWIER_SWIER5_Msk
7686#define EXTI_SWIER_SWIER6_Pos (6U)
7687#define EXTI_SWIER_SWIER6_Msk (0x1UL << EXTI_SWIER_SWIER6_Pos)
7688#define EXTI_SWIER_SWIER6 EXTI_SWIER_SWIER6_Msk
7689#define EXTI_SWIER_SWIER7_Pos (7U)
7690#define EXTI_SWIER_SWIER7_Msk (0x1UL << EXTI_SWIER_SWIER7_Pos)
7691#define EXTI_SWIER_SWIER7 EXTI_SWIER_SWIER7_Msk
7692#define EXTI_SWIER_SWIER8_Pos (8U)
7693#define EXTI_SWIER_SWIER8_Msk (0x1UL << EXTI_SWIER_SWIER8_Pos)
7694#define EXTI_SWIER_SWIER8 EXTI_SWIER_SWIER8_Msk
7695#define EXTI_SWIER_SWIER9_Pos (9U)
7696#define EXTI_SWIER_SWIER9_Msk (0x1UL << EXTI_SWIER_SWIER9_Pos)
7697#define EXTI_SWIER_SWIER9 EXTI_SWIER_SWIER9_Msk
7698#define EXTI_SWIER_SWIER10_Pos (10U)
7699#define EXTI_SWIER_SWIER10_Msk (0x1UL << EXTI_SWIER_SWIER10_Pos)
7700#define EXTI_SWIER_SWIER10 EXTI_SWIER_SWIER10_Msk
7701#define EXTI_SWIER_SWIER11_Pos (11U)
7702#define EXTI_SWIER_SWIER11_Msk (0x1UL << EXTI_SWIER_SWIER11_Pos)
7703#define EXTI_SWIER_SWIER11 EXTI_SWIER_SWIER11_Msk
7704#define EXTI_SWIER_SWIER12_Pos (12U)
7705#define EXTI_SWIER_SWIER12_Msk (0x1UL << EXTI_SWIER_SWIER12_Pos)
7706#define EXTI_SWIER_SWIER12 EXTI_SWIER_SWIER12_Msk
7707#define EXTI_SWIER_SWIER13_Pos (13U)
7708#define EXTI_SWIER_SWIER13_Msk (0x1UL << EXTI_SWIER_SWIER13_Pos)
7709#define EXTI_SWIER_SWIER13 EXTI_SWIER_SWIER13_Msk
7710#define EXTI_SWIER_SWIER14_Pos (14U)
7711#define EXTI_SWIER_SWIER14_Msk (0x1UL << EXTI_SWIER_SWIER14_Pos)
7712#define EXTI_SWIER_SWIER14 EXTI_SWIER_SWIER14_Msk
7713#define EXTI_SWIER_SWIER15_Pos (15U)
7714#define EXTI_SWIER_SWIER15_Msk (0x1UL << EXTI_SWIER_SWIER15_Pos)
7715#define EXTI_SWIER_SWIER15 EXTI_SWIER_SWIER15_Msk
7716#define EXTI_SWIER_SWIER16_Pos (16U)
7717#define EXTI_SWIER_SWIER16_Msk (0x1UL << EXTI_SWIER_SWIER16_Pos)
7718#define EXTI_SWIER_SWIER16 EXTI_SWIER_SWIER16_Msk
7719#define EXTI_SWIER_SWIER17_Pos (17U)
7720#define EXTI_SWIER_SWIER17_Msk (0x1UL << EXTI_SWIER_SWIER17_Pos)
7721#define EXTI_SWIER_SWIER17 EXTI_SWIER_SWIER17_Msk
7722#define EXTI_SWIER_SWIER18_Pos (18U)
7723#define EXTI_SWIER_SWIER18_Msk (0x1UL << EXTI_SWIER_SWIER18_Pos)
7724#define EXTI_SWIER_SWIER18 EXTI_SWIER_SWIER18_Msk
7725#define EXTI_SWIER_SWIER19_Pos (19U)
7726#define EXTI_SWIER_SWIER19_Msk (0x1UL << EXTI_SWIER_SWIER19_Pos)
7727#define EXTI_SWIER_SWIER19 EXTI_SWIER_SWIER19_Msk
7728#define EXTI_SWIER_SWIER20_Pos (20U)
7729#define EXTI_SWIER_SWIER20_Msk (0x1UL << EXTI_SWIER_SWIER20_Pos)
7730#define EXTI_SWIER_SWIER20 EXTI_SWIER_SWIER20_Msk
7731#define EXTI_SWIER_SWIER21_Pos (21U)
7732#define EXTI_SWIER_SWIER21_Msk (0x1UL << EXTI_SWIER_SWIER21_Pos)
7733#define EXTI_SWIER_SWIER21 EXTI_SWIER_SWIER21_Msk
7734#define EXTI_SWIER_SWIER22_Pos (22U)
7735#define EXTI_SWIER_SWIER22_Msk (0x1UL << EXTI_SWIER_SWIER22_Pos)
7736#define EXTI_SWIER_SWIER22 EXTI_SWIER_SWIER22_Msk
7737#define EXTI_SWIER_SWIER29_Pos (29U)
7738#define EXTI_SWIER_SWIER29_Msk (0x1UL << EXTI_SWIER_SWIER29_Pos)
7739#define EXTI_SWIER_SWIER29 EXTI_SWIER_SWIER29_Msk
7740#define EXTI_SWIER_SWIER30_Pos (30U)
7741#define EXTI_SWIER_SWIER30_Msk (0x1UL << EXTI_SWIER_SWIER30_Pos)
7742#define EXTI_SWIER_SWIER30 EXTI_SWIER_SWIER30_Msk
7743#define EXTI_SWIER_SWIER31_Pos (31U)
7744#define EXTI_SWIER_SWIER31_Msk (0x1UL << EXTI_SWIER_SWIER31_Pos)
7745#define EXTI_SWIER_SWIER31 EXTI_SWIER_SWIER31_Msk
7747/* References Defines */
7748#define EXTI_SWIER_SWI0 EXTI_SWIER_SWIER0
7749#define EXTI_SWIER_SWI1 EXTI_SWIER_SWIER1
7750#define EXTI_SWIER_SWI2 EXTI_SWIER_SWIER2
7751#define EXTI_SWIER_SWI3 EXTI_SWIER_SWIER3
7752#define EXTI_SWIER_SWI4 EXTI_SWIER_SWIER4
7753#define EXTI_SWIER_SWI5 EXTI_SWIER_SWIER5
7754#define EXTI_SWIER_SWI6 EXTI_SWIER_SWIER6
7755#define EXTI_SWIER_SWI7 EXTI_SWIER_SWIER7
7756#define EXTI_SWIER_SWI8 EXTI_SWIER_SWIER8
7757#define EXTI_SWIER_SWI9 EXTI_SWIER_SWIER9
7758#define EXTI_SWIER_SWI10 EXTI_SWIER_SWIER10
7759#define EXTI_SWIER_SWI11 EXTI_SWIER_SWIER11
7760#define EXTI_SWIER_SWI12 EXTI_SWIER_SWIER12
7761#define EXTI_SWIER_SWI13 EXTI_SWIER_SWIER13
7762#define EXTI_SWIER_SWI14 EXTI_SWIER_SWIER14
7763#define EXTI_SWIER_SWI15 EXTI_SWIER_SWIER15
7764#define EXTI_SWIER_SWI16 EXTI_SWIER_SWIER16
7765#define EXTI_SWIER_SWI17 EXTI_SWIER_SWIER17
7766#if defined(EXTI_SWIER_SWIER18)
7767#define EXTI_SWIER_SWI18 EXTI_SWIER_SWIER18
7768#endif
7769#define EXTI_SWIER_SWI19 EXTI_SWIER_SWIER19
7770#define EXTI_SWIER_SWI20 EXTI_SWIER_SWIER20
7771#if defined(EXTI_SWIER_SWIER21)
7772#define EXTI_SWIER_SWI21 EXTI_SWIER_SWIER21
7773#endif
7774#define EXTI_SWIER_SWI22 EXTI_SWIER_SWIER22
7775#if defined(EXTI_SWIER_SWIER23)
7776#define EXTI_SWIER_SWI23 EXTI_SWIER_SWIER23
7777#endif
7778#if defined(EXTI_SWIER_SWIER24)
7779#define EXTI_SWIER_SWI24 EXTI_SWIER_SWIER24
7780#endif
7781#if defined(EXTI_SWIER_SWIER25)
7782#define EXTI_SWIER_SWI25 EXTI_SWIER_SWIER25
7783#endif
7784#if defined(EXTI_SWIER_SWIER26)
7785#define EXTI_SWIER_SWI26 EXTI_SWIER_SWIER26
7786#endif
7787#if defined(EXTI_SWIER_SWIER27)
7788#define EXTI_SWIER_SWI27 EXTI_SWIER_SWIER27
7789#endif
7790#if defined(EXTI_SWIER_SWIER28)
7791#define EXTI_SWIER_SWI28 EXTI_SWIER_SWIER28
7792#endif
7793#if defined(EXTI_SWIER_SWIER29)
7794#define EXTI_SWIER_SWI29 EXTI_SWIER_SWIER29
7795#endif
7796#if defined(EXTI_SWIER_SWIER30)
7797#define EXTI_SWIER_SWI30 EXTI_SWIER_SWIER30
7798#endif
7799#if defined(EXTI_SWIER_SWIER31)
7800#define EXTI_SWIER_SWI31 EXTI_SWIER_SWIER31
7801#endif
7802
7803/******************* Bit definition for EXTI_PR register ********************/
7804#define EXTI_PR_PR0_Pos (0U)
7805#define EXTI_PR_PR0_Msk (0x1UL << EXTI_PR_PR0_Pos)
7806#define EXTI_PR_PR0 EXTI_PR_PR0_Msk
7807#define EXTI_PR_PR1_Pos (1U)
7808#define EXTI_PR_PR1_Msk (0x1UL << EXTI_PR_PR1_Pos)
7809#define EXTI_PR_PR1 EXTI_PR_PR1_Msk
7810#define EXTI_PR_PR2_Pos (2U)
7811#define EXTI_PR_PR2_Msk (0x1UL << EXTI_PR_PR2_Pos)
7812#define EXTI_PR_PR2 EXTI_PR_PR2_Msk
7813#define EXTI_PR_PR3_Pos (3U)
7814#define EXTI_PR_PR3_Msk (0x1UL << EXTI_PR_PR3_Pos)
7815#define EXTI_PR_PR3 EXTI_PR_PR3_Msk
7816#define EXTI_PR_PR4_Pos (4U)
7817#define EXTI_PR_PR4_Msk (0x1UL << EXTI_PR_PR4_Pos)
7818#define EXTI_PR_PR4 EXTI_PR_PR4_Msk
7819#define EXTI_PR_PR5_Pos (5U)
7820#define EXTI_PR_PR5_Msk (0x1UL << EXTI_PR_PR5_Pos)
7821#define EXTI_PR_PR5 EXTI_PR_PR5_Msk
7822#define EXTI_PR_PR6_Pos (6U)
7823#define EXTI_PR_PR6_Msk (0x1UL << EXTI_PR_PR6_Pos)
7824#define EXTI_PR_PR6 EXTI_PR_PR6_Msk
7825#define EXTI_PR_PR7_Pos (7U)
7826#define EXTI_PR_PR7_Msk (0x1UL << EXTI_PR_PR7_Pos)
7827#define EXTI_PR_PR7 EXTI_PR_PR7_Msk
7828#define EXTI_PR_PR8_Pos (8U)
7829#define EXTI_PR_PR8_Msk (0x1UL << EXTI_PR_PR8_Pos)
7830#define EXTI_PR_PR8 EXTI_PR_PR8_Msk
7831#define EXTI_PR_PR9_Pos (9U)
7832#define EXTI_PR_PR9_Msk (0x1UL << EXTI_PR_PR9_Pos)
7833#define EXTI_PR_PR9 EXTI_PR_PR9_Msk
7834#define EXTI_PR_PR10_Pos (10U)
7835#define EXTI_PR_PR10_Msk (0x1UL << EXTI_PR_PR10_Pos)
7836#define EXTI_PR_PR10 EXTI_PR_PR10_Msk
7837#define EXTI_PR_PR11_Pos (11U)
7838#define EXTI_PR_PR11_Msk (0x1UL << EXTI_PR_PR11_Pos)
7839#define EXTI_PR_PR11 EXTI_PR_PR11_Msk
7840#define EXTI_PR_PR12_Pos (12U)
7841#define EXTI_PR_PR12_Msk (0x1UL << EXTI_PR_PR12_Pos)
7842#define EXTI_PR_PR12 EXTI_PR_PR12_Msk
7843#define EXTI_PR_PR13_Pos (13U)
7844#define EXTI_PR_PR13_Msk (0x1UL << EXTI_PR_PR13_Pos)
7845#define EXTI_PR_PR13 EXTI_PR_PR13_Msk
7846#define EXTI_PR_PR14_Pos (14U)
7847#define EXTI_PR_PR14_Msk (0x1UL << EXTI_PR_PR14_Pos)
7848#define EXTI_PR_PR14 EXTI_PR_PR14_Msk
7849#define EXTI_PR_PR15_Pos (15U)
7850#define EXTI_PR_PR15_Msk (0x1UL << EXTI_PR_PR15_Pos)
7851#define EXTI_PR_PR15 EXTI_PR_PR15_Msk
7852#define EXTI_PR_PR16_Pos (16U)
7853#define EXTI_PR_PR16_Msk (0x1UL << EXTI_PR_PR16_Pos)
7854#define EXTI_PR_PR16 EXTI_PR_PR16_Msk
7855#define EXTI_PR_PR17_Pos (17U)
7856#define EXTI_PR_PR17_Msk (0x1UL << EXTI_PR_PR17_Pos)
7857#define EXTI_PR_PR17 EXTI_PR_PR17_Msk
7858#define EXTI_PR_PR18_Pos (18U)
7859#define EXTI_PR_PR18_Msk (0x1UL << EXTI_PR_PR18_Pos)
7860#define EXTI_PR_PR18 EXTI_PR_PR18_Msk
7861#define EXTI_PR_PR19_Pos (19U)
7862#define EXTI_PR_PR19_Msk (0x1UL << EXTI_PR_PR19_Pos)
7863#define EXTI_PR_PR19 EXTI_PR_PR19_Msk
7864#define EXTI_PR_PR20_Pos (20U)
7865#define EXTI_PR_PR20_Msk (0x1UL << EXTI_PR_PR20_Pos)
7866#define EXTI_PR_PR20 EXTI_PR_PR20_Msk
7867#define EXTI_PR_PR21_Pos (21U)
7868#define EXTI_PR_PR21_Msk (0x1UL << EXTI_PR_PR21_Pos)
7869#define EXTI_PR_PR21 EXTI_PR_PR21_Msk
7870#define EXTI_PR_PR22_Pos (22U)
7871#define EXTI_PR_PR22_Msk (0x1UL << EXTI_PR_PR22_Pos)
7872#define EXTI_PR_PR22 EXTI_PR_PR22_Msk
7873#define EXTI_PR_PR29_Pos (29U)
7874#define EXTI_PR_PR29_Msk (0x1UL << EXTI_PR_PR29_Pos)
7875#define EXTI_PR_PR29 EXTI_PR_PR29_Msk
7876#define EXTI_PR_PR30_Pos (30U)
7877#define EXTI_PR_PR30_Msk (0x1UL << EXTI_PR_PR30_Pos)
7878#define EXTI_PR_PR30 EXTI_PR_PR30_Msk
7879#define EXTI_PR_PR31_Pos (31U)
7880#define EXTI_PR_PR31_Msk (0x1UL << EXTI_PR_PR31_Pos)
7881#define EXTI_PR_PR31 EXTI_PR_PR31_Msk
7883/* References Defines */
7884#define EXTI_PR_PIF0 EXTI_PR_PR0
7885#define EXTI_PR_PIF1 EXTI_PR_PR1
7886#define EXTI_PR_PIF2 EXTI_PR_PR2
7887#define EXTI_PR_PIF3 EXTI_PR_PR3
7888#define EXTI_PR_PIF4 EXTI_PR_PR4
7889#define EXTI_PR_PIF5 EXTI_PR_PR5
7890#define EXTI_PR_PIF6 EXTI_PR_PR6
7891#define EXTI_PR_PIF6 EXTI_PR_PR6
7892#define EXTI_PR_PIF7 EXTI_PR_PR7
7893#define EXTI_PR_PIF8 EXTI_PR_PR8
7894#define EXTI_PR_PIF9 EXTI_PR_PR9
7895#define EXTI_PR_PIF10 EXTI_PR_PR10
7896#define EXTI_PR_PIF11 EXTI_PR_PR11
7897#define EXTI_PR_PIF12 EXTI_PR_PR12
7898#define EXTI_PR_PIF13 EXTI_PR_PR13
7899#define EXTI_PR_PIF14 EXTI_PR_PR14
7900#define EXTI_PR_PIF15 EXTI_PR_PR15
7901#define EXTI_PR_PIF16 EXTI_PR_PR16
7902#define EXTI_PR_PIF17 EXTI_PR_PR17
7903#if defined(EXTI_PR_PR18)
7904#define EXTI_PR_PIF18 EXTI_PR_PR18
7905#endif
7906#define EXTI_PR_PIF19 EXTI_PR_PR19
7907#define EXTI_PR_PIF20 EXTI_PR_PR20
7908#if defined(EXTI_PR_PR21)
7909#define EXTI_PR_PIF21 EXTI_PR_PR21
7910#endif
7911#define EXTI_PR_PIF22 EXTI_PR_PR22
7912#if defined(EXTI_PR_PR23)
7913#define EXTI_PR_PIF23 EXTI_PR_PR23
7914#endif
7915#if defined(EXTI_PR_PR24)
7916#define EXTI_PR_PIF24 EXTI_PR_PR24
7917#endif
7918#if defined(EXTI_PR_PR25)
7919#define EXTI_PR_PIF25 EXTI_PR_PR25
7920#endif
7921#if defined(EXTI_PR_PR26)
7922#define EXTI_PR_PIF26 EXTI_PR_PR26
7923#endif
7924#if defined(EXTI_PR_PR27)
7925#define EXTI_PR_PIF27 EXTI_PR_PR27
7926#endif
7927#if defined(EXTI_PR_PR28)
7928#define EXTI_PR_PIF28 EXTI_PR_PR28
7929#endif
7930#if defined(EXTI_PR_PR29)
7931#define EXTI_PR_PIF29 EXTI_PR_PR29
7932#endif
7933#if defined(EXTI_PR_PR30)
7934#define EXTI_PR_PIF30 EXTI_PR_PR30
7935#endif
7936#if defined(EXTI_PR_PR31)
7937#define EXTI_PR_PIF31 EXTI_PR_PR31
7938#endif
7939
7940#define EXTI_32_63_SUPPORT /* EXTI support more than 32 lines */
7941
7942/******************* Bit definition for EXTI_IMR2 register ******************/
7943#define EXTI_IMR2_MR32_Pos (0U)
7944#define EXTI_IMR2_MR32_Msk (0x1UL << EXTI_IMR2_MR32_Pos)
7945#define EXTI_IMR2_MR32 EXTI_IMR2_MR32_Msk
7946#define EXTI_IMR2_MR33_Pos (1U)
7947#define EXTI_IMR2_MR33_Msk (0x1UL << EXTI_IMR2_MR33_Pos)
7948#define EXTI_IMR2_MR33 EXTI_IMR2_MR33_Msk
7949#define EXTI_IMR2_MR34_Pos (2U)
7950#define EXTI_IMR2_MR34_Msk (0x1UL << EXTI_IMR2_MR34_Pos)
7951#define EXTI_IMR2_MR34 EXTI_IMR2_MR34_Msk
7952#define EXTI_IMR2_MR35_Pos (3U)
7953#define EXTI_IMR2_MR35_Msk (0x1UL << EXTI_IMR2_MR35_Pos)
7954#define EXTI_IMR2_MR35 EXTI_IMR2_MR35_Msk
7956/* References Defines */
7957
7958#define EXTI_IMR2_IM32 EXTI_IMR2_MR32
7959#if defined(EXTI_IMR2_MR33)
7960#define EXTI_IMR2_IM33 EXTI_IMR2_MR33
7961#endif
7962#if defined(EXTI_IMR2_MR34)
7963#define EXTI_IMR2_IM34 EXTI_IMR2_MR34
7964#endif
7965#if defined(EXTI_IMR2_MR35)
7966#define EXTI_IMR2_IM35 EXTI_IMR2_MR35
7967#endif
7968
7969#if defined(EXTI_IMR2_MR33) && defined(EXTI_IMR2_MR34) && defined(EXTI_IMR2_MR35)
7970#define EXTI_IMR2_IM_Pos (0U)
7971#define EXTI_IMR2_IM_Msk (0xFUL << EXTI_IMR2_IM_Pos)
7972#define EXTI_IMR2_IM EXTI_IMR2_IM_Msk
7973#elif defined(EXTI_IMR2_MR34) && defined(EXTI_IMR2_MR35)
7974#define EXTI_IMR2_IM_Pos (0U)
7975#define EXTI_IMR2_IM_Msk (0xDUL << EXTI_IMR2_IM_Pos)
7976#define EXTI_IMR2_IM EXTI_IMR2_IM_Msk
7977#else
7978#define EXTI_IMR2_IM_Pos (0U)
7979#define EXTI_IMR2_IM_Msk (0x1UL << EXTI_IMR2_IM_Pos)
7980#define EXTI_IMR2_IM EXTI_IMR2_IM_Msk
7981#endif
7982
7983/******************* Bit definition for EXTI_EMR2 ****************************/
7984#define EXTI_EMR2_MR32_Pos (0U)
7985#define EXTI_EMR2_MR32_Msk (0x1UL << EXTI_EMR2_MR32_Pos)
7986#define EXTI_EMR2_MR32 EXTI_EMR2_MR32_Msk
7987#define EXTI_EMR2_MR33_Pos (1U)
7988#define EXTI_EMR2_MR33_Msk (0x1UL << EXTI_EMR2_MR33_Pos)
7989#define EXTI_EMR2_MR33 EXTI_EMR2_MR33_Msk
7990#define EXTI_EMR2_MR34_Pos (2U)
7991#define EXTI_EMR2_MR34_Msk (0x1UL << EXTI_EMR2_MR34_Pos)
7992#define EXTI_EMR2_MR34 EXTI_EMR2_MR34_Msk
7993#define EXTI_EMR2_MR35_Pos (3U)
7994#define EXTI_EMR2_MR35_Msk (0x1UL << EXTI_EMR2_MR35_Pos)
7995#define EXTI_EMR2_MR35 EXTI_EMR2_MR35_Msk
7997/* References Defines */
7998#define EXTI_EMR2_EM32 EXTI_EMR2_MR32
7999#if defined(EXTI_EMR2_MR33)
8000#define EXTI_EMR2_EM33 EXTI_EMR2_MR33
8001#endif
8002#if defined(EXTI_EMR2_MR34)
8003#define EXTI_EMR2_EM34 EXTI_EMR2_MR34
8004#endif
8005#if defined(EXTI_EMR2_MR35)
8006#define EXTI_EMR2_EM35 EXTI_EMR2_MR35
8007#endif
8008
8009#if defined(EXTI_EMR2_MR33) && defined(EXTI_EMR2_MR34) && defined(EXTI_EMR2_MR35)
8010#define EXTI_EMR2_EM_Pos (0U)
8011#define EXTI_EMR2_EM_Msk (0xFUL << EXTI_EMR2_EM_Pos)
8012#define EXTI_EMR2_EM EXTI_EMR2_EM_Msk
8013#elif defined(EXTI_EMR2_MR34) && defined(EXTI_EMR2_MR35)
8014#define EXTI_EMR2_EM_Pos (0U)
8015#define EXTI_EMR2_EM_Msk (0xDUL << EXTI_EMR2_EM_Pos)
8016#define EXTI_EMR2_EM EXTI_EMR2_EM_Msk
8017#else
8018#define EXTI_EMR2_EM_Pos (0U)
8019#define EXTI_EMR2_EM_Msk (0x1UL << EXTI_EMR2_EM_Pos)
8020#define EXTI_EMR2_EM EXTI_EMR2_EM_Msk
8021#endif
8022
8023/****************** Bit definition for EXTI_RTSR2 register ********************/
8024#define EXTI_RTSR2_TR32_Pos (0U)
8025#define EXTI_RTSR2_TR32_Msk (0x1UL << EXTI_RTSR2_TR32_Pos)
8026#define EXTI_RTSR2_TR32 EXTI_RTSR2_TR32_Msk
8027#define EXTI_RTSR2_TR33_Pos (1U)
8028#define EXTI_RTSR2_TR33_Msk (0x1UL << EXTI_RTSR2_TR33_Pos)
8029#define EXTI_RTSR2_TR33 EXTI_RTSR2_TR33_Msk
8031/* References Defines */
8032#define EXTI_RTSR2_RT32 EXTI_RTSR2_TR32
8033#if defined(EXTI_RTSR2_TR33)
8034#define EXTI_RTSR2_RT33 EXTI_RTSR2_TR33
8035#endif
8036#if defined(EXTI_RTSR2_TR34)
8037#define EXTI_RTSR2_RT34 EXTI_RTSR2_TR34
8038#endif
8039#if defined(EXTI_RTSR2_TR35)
8040#define EXTI_RTSR2_RT35 EXTI_RTSR2_TR35
8041#endif
8042
8043/****************** Bit definition for EXTI_FTSR2 register ******************/
8044#define EXTI_FTSR2_TR32_Pos (0U)
8045#define EXTI_FTSR2_TR32_Msk (0x1UL << EXTI_FTSR2_TR32_Pos)
8046#define EXTI_FTSR2_TR32 EXTI_FTSR2_TR32_Msk
8047#define EXTI_FTSR2_TR33_Pos (1U)
8048#define EXTI_FTSR2_TR33_Msk (0x1UL << EXTI_FTSR2_TR33_Pos)
8049#define EXTI_FTSR2_TR33 EXTI_FTSR2_TR33_Msk
8051/* References Defines */
8052#define EXTI_FTSR2_FT32 EXTI_FTSR2_TR32
8053#if defined(EXTI_FTSR2_TR33)
8054#define EXTI_FTSR2_FT33 EXTI_FTSR2_TR33
8055#endif
8056#if defined(EXTI_FTSR2_TR34)
8057#define EXTI_FTSR2_FT34 EXTI_FTSR2_TR34
8058#endif
8059#if defined(EXTI_FTSR2_TR35)
8060#define EXTI_FTSR2_FT35 EXTI_FTSR2_TR35
8061#endif
8062
8063/****************** Bit definition for EXTI_SWIER2 register *****************/
8064#define EXTI_SWIER2_SWIER32_Pos (0U)
8065#define EXTI_SWIER2_SWIER32_Msk (0x1UL << EXTI_SWIER2_SWIER32_Pos)
8066#define EXTI_SWIER2_SWIER32 EXTI_SWIER2_SWIER32_Msk
8067#define EXTI_SWIER2_SWIER33_Pos (1U)
8068#define EXTI_SWIER2_SWIER33_Msk (0x1UL << EXTI_SWIER2_SWIER33_Pos)
8069#define EXTI_SWIER2_SWIER33 EXTI_SWIER2_SWIER33_Msk
8071/* References Defines */
8072#define EXTI_SWIER2_SWI32 EXTI_SWIER2_SWIER32
8073#if defined(EXTI_SWIER2_SWIER33)
8074#define EXTI_SWIER2_SWI33 EXTI_SWIER2_SWIER33
8075#endif
8076#if defined(EXTI_SWIER2_SWIER34)
8077#define EXTI_SWIER2_SWI34 EXTI_SWIER2_SWIER34
8078#endif
8079#if defined(EXTI_SWIER2_SWIER35)
8080#define EXTI_SWIER2_SWI35 EXTI_SWIER2_SWIER35
8081#endif
8082
8083/******************* Bit definition for EXTI_PR2 register *******************/
8084#define EXTI_PR2_PR32_Pos (0U)
8085#define EXTI_PR2_PR32_Msk (0x1UL << EXTI_PR2_PR32_Pos)
8086#define EXTI_PR2_PR32 EXTI_PR2_PR32_Msk
8087#define EXTI_PR2_PR33_Pos (1U)
8088#define EXTI_PR2_PR33_Msk (0x1UL << EXTI_PR2_PR33_Pos)
8089#define EXTI_PR2_PR33 EXTI_PR2_PR33_Msk
8091/* References Defines */
8092#define EXTI_PR2_PIF32 EXTI_PR2_PR32
8093#if defined(EXTI_PR2_PR33)
8094#define EXTI_PR2_PIF33 EXTI_PR2_PR33
8095#endif
8096#if defined(EXTI_PR2_PR34)
8097#define EXTI_PR2_PIF34 EXTI_PR2_PR34
8098#endif
8099#if defined(EXTI_PR2_PR35)
8100#define EXTI_PR2_PIF35 EXTI_PR2_PR35
8101#endif
8102
8103
8104/******************************************************************************/
8105/* */
8106/* FLASH */
8107/* */
8108/******************************************************************************/
8109/******************* Bit definition for FLASH_ACR register ******************/
8110#define FLASH_ACR_LATENCY_Pos (0U)
8111#define FLASH_ACR_LATENCY_Msk (0x7UL << FLASH_ACR_LATENCY_Pos)
8112#define FLASH_ACR_LATENCY FLASH_ACR_LATENCY_Msk
8113#define FLASH_ACR_LATENCY_0 (0x1UL << FLASH_ACR_LATENCY_Pos)
8114#define FLASH_ACR_LATENCY_1 (0x2UL << FLASH_ACR_LATENCY_Pos)
8115#define FLASH_ACR_LATENCY_2 (0x4UL << FLASH_ACR_LATENCY_Pos)
8117#define FLASH_ACR_HLFCYA_Pos (3U)
8118#define FLASH_ACR_HLFCYA_Msk (0x1UL << FLASH_ACR_HLFCYA_Pos)
8119#define FLASH_ACR_HLFCYA FLASH_ACR_HLFCYA_Msk
8120#define FLASH_ACR_PRFTBE_Pos (4U)
8121#define FLASH_ACR_PRFTBE_Msk (0x1UL << FLASH_ACR_PRFTBE_Pos)
8122#define FLASH_ACR_PRFTBE FLASH_ACR_PRFTBE_Msk
8123#define FLASH_ACR_PRFTBS_Pos (5U)
8124#define FLASH_ACR_PRFTBS_Msk (0x1UL << FLASH_ACR_PRFTBS_Pos)
8125#define FLASH_ACR_PRFTBS FLASH_ACR_PRFTBS_Msk
8127/****************** Bit definition for FLASH_KEYR register ******************/
8128#define FLASH_KEYR_FKEYR_Pos (0U)
8129#define FLASH_KEYR_FKEYR_Msk (0xFFFFFFFFUL << FLASH_KEYR_FKEYR_Pos)
8130#define FLASH_KEYR_FKEYR FLASH_KEYR_FKEYR_Msk
8132#define RDP_KEY_Pos (0U)
8133#define RDP_KEY_Msk (0xA5UL << RDP_KEY_Pos)
8134#define RDP_KEY RDP_KEY_Msk
8135#define FLASH_KEY1_Pos (0U)
8136#define FLASH_KEY1_Msk (0x45670123UL << FLASH_KEY1_Pos)
8137#define FLASH_KEY1 FLASH_KEY1_Msk
8138#define FLASH_KEY2_Pos (0U)
8139#define FLASH_KEY2_Msk (0xCDEF89ABUL << FLASH_KEY2_Pos)
8140#define FLASH_KEY2 FLASH_KEY2_Msk
8142/***************** Bit definition for FLASH_OPTKEYR register ****************/
8143#define FLASH_OPTKEYR_OPTKEYR_Pos (0U)
8144#define FLASH_OPTKEYR_OPTKEYR_Msk (0xFFFFFFFFUL << FLASH_OPTKEYR_OPTKEYR_Pos)
8145#define FLASH_OPTKEYR_OPTKEYR FLASH_OPTKEYR_OPTKEYR_Msk
8147#define FLASH_OPTKEY1 FLASH_KEY1
8148#define FLASH_OPTKEY2 FLASH_KEY2
8150/****************** Bit definition for FLASH_SR register *******************/
8151#define FLASH_SR_BSY_Pos (0U)
8152#define FLASH_SR_BSY_Msk (0x1UL << FLASH_SR_BSY_Pos)
8153#define FLASH_SR_BSY FLASH_SR_BSY_Msk
8154#define FLASH_SR_PGERR_Pos (2U)
8155#define FLASH_SR_PGERR_Msk (0x1UL << FLASH_SR_PGERR_Pos)
8156#define FLASH_SR_PGERR FLASH_SR_PGERR_Msk
8157#define FLASH_SR_WRPERR_Pos (4U)
8158#define FLASH_SR_WRPERR_Msk (0x1UL << FLASH_SR_WRPERR_Pos)
8159#define FLASH_SR_WRPERR FLASH_SR_WRPERR_Msk
8160#define FLASH_SR_EOP_Pos (5U)
8161#define FLASH_SR_EOP_Msk (0x1UL << FLASH_SR_EOP_Pos)
8162#define FLASH_SR_EOP FLASH_SR_EOP_Msk
8164/******************* Bit definition for FLASH_CR register *******************/
8165#define FLASH_CR_PG_Pos (0U)
8166#define FLASH_CR_PG_Msk (0x1UL << FLASH_CR_PG_Pos)
8167#define FLASH_CR_PG FLASH_CR_PG_Msk
8168#define FLASH_CR_PER_Pos (1U)
8169#define FLASH_CR_PER_Msk (0x1UL << FLASH_CR_PER_Pos)
8170#define FLASH_CR_PER FLASH_CR_PER_Msk
8171#define FLASH_CR_MER_Pos (2U)
8172#define FLASH_CR_MER_Msk (0x1UL << FLASH_CR_MER_Pos)
8173#define FLASH_CR_MER FLASH_CR_MER_Msk
8174#define FLASH_CR_OPTPG_Pos (4U)
8175#define FLASH_CR_OPTPG_Msk (0x1UL << FLASH_CR_OPTPG_Pos)
8176#define FLASH_CR_OPTPG FLASH_CR_OPTPG_Msk
8177#define FLASH_CR_OPTER_Pos (5U)
8178#define FLASH_CR_OPTER_Msk (0x1UL << FLASH_CR_OPTER_Pos)
8179#define FLASH_CR_OPTER FLASH_CR_OPTER_Msk
8180#define FLASH_CR_STRT_Pos (6U)
8181#define FLASH_CR_STRT_Msk (0x1UL << FLASH_CR_STRT_Pos)
8182#define FLASH_CR_STRT FLASH_CR_STRT_Msk
8183#define FLASH_CR_LOCK_Pos (7U)
8184#define FLASH_CR_LOCK_Msk (0x1UL << FLASH_CR_LOCK_Pos)
8185#define FLASH_CR_LOCK FLASH_CR_LOCK_Msk
8186#define FLASH_CR_OPTWRE_Pos (9U)
8187#define FLASH_CR_OPTWRE_Msk (0x1UL << FLASH_CR_OPTWRE_Pos)
8188#define FLASH_CR_OPTWRE FLASH_CR_OPTWRE_Msk
8189#define FLASH_CR_ERRIE_Pos (10U)
8190#define FLASH_CR_ERRIE_Msk (0x1UL << FLASH_CR_ERRIE_Pos)
8191#define FLASH_CR_ERRIE FLASH_CR_ERRIE_Msk
8192#define FLASH_CR_EOPIE_Pos (12U)
8193#define FLASH_CR_EOPIE_Msk (0x1UL << FLASH_CR_EOPIE_Pos)
8194#define FLASH_CR_EOPIE FLASH_CR_EOPIE_Msk
8195#define FLASH_CR_OBL_LAUNCH_Pos (13U)
8196#define FLASH_CR_OBL_LAUNCH_Msk (0x1UL << FLASH_CR_OBL_LAUNCH_Pos)
8197#define FLASH_CR_OBL_LAUNCH FLASH_CR_OBL_LAUNCH_Msk
8199/******************* Bit definition for FLASH_AR register *******************/
8200#define FLASH_AR_FAR_Pos (0U)
8201#define FLASH_AR_FAR_Msk (0xFFFFFFFFUL << FLASH_AR_FAR_Pos)
8202#define FLASH_AR_FAR FLASH_AR_FAR_Msk
8204/****************** Bit definition for FLASH_OBR register *******************/
8205#define FLASH_OBR_OPTERR_Pos (0U)
8206#define FLASH_OBR_OPTERR_Msk (0x1UL << FLASH_OBR_OPTERR_Pos)
8207#define FLASH_OBR_OPTERR FLASH_OBR_OPTERR_Msk
8208#define FLASH_OBR_RDPRT_Pos (1U)
8209#define FLASH_OBR_RDPRT_Msk (0x3UL << FLASH_OBR_RDPRT_Pos)
8210#define FLASH_OBR_RDPRT FLASH_OBR_RDPRT_Msk
8211#define FLASH_OBR_RDPRT_1 (0x1UL << FLASH_OBR_RDPRT_Pos)
8212#define FLASH_OBR_RDPRT_2 (0x3UL << FLASH_OBR_RDPRT_Pos)
8214#define FLASH_OBR_USER_Pos (8U)
8215#define FLASH_OBR_USER_Msk (0x77UL << FLASH_OBR_USER_Pos)
8216#define FLASH_OBR_USER FLASH_OBR_USER_Msk
8217#define FLASH_OBR_IWDG_SW_Pos (8U)
8218#define FLASH_OBR_IWDG_SW_Msk (0x1UL << FLASH_OBR_IWDG_SW_Pos)
8219#define FLASH_OBR_IWDG_SW FLASH_OBR_IWDG_SW_Msk
8220#define FLASH_OBR_nRST_STOP_Pos (9U)
8221#define FLASH_OBR_nRST_STOP_Msk (0x1UL << FLASH_OBR_nRST_STOP_Pos)
8222#define FLASH_OBR_nRST_STOP FLASH_OBR_nRST_STOP_Msk
8223#define FLASH_OBR_nRST_STDBY_Pos (10U)
8224#define FLASH_OBR_nRST_STDBY_Msk (0x1UL << FLASH_OBR_nRST_STDBY_Pos)
8225#define FLASH_OBR_nRST_STDBY FLASH_OBR_nRST_STDBY_Msk
8226#define FLASH_OBR_nBOOT1_Pos (12U)
8227#define FLASH_OBR_nBOOT1_Msk (0x1UL << FLASH_OBR_nBOOT1_Pos)
8228#define FLASH_OBR_nBOOT1 FLASH_OBR_nBOOT1_Msk
8229#define FLASH_OBR_VDDA_MONITOR_Pos (13U)
8230#define FLASH_OBR_VDDA_MONITOR_Msk (0x1UL << FLASH_OBR_VDDA_MONITOR_Pos)
8231#define FLASH_OBR_VDDA_MONITOR FLASH_OBR_VDDA_MONITOR_Msk
8232#define FLASH_OBR_SRAM_PE_Pos (14U)
8233#define FLASH_OBR_SRAM_PE_Msk (0x1UL << FLASH_OBR_SRAM_PE_Pos)
8234#define FLASH_OBR_SRAM_PE FLASH_OBR_SRAM_PE_Msk
8235#define FLASH_OBR_DATA0_Pos (16U)
8236#define FLASH_OBR_DATA0_Msk (0xFFUL << FLASH_OBR_DATA0_Pos)
8237#define FLASH_OBR_DATA0 FLASH_OBR_DATA0_Msk
8238#define FLASH_OBR_DATA1_Pos (24U)
8239#define FLASH_OBR_DATA1_Msk (0xFFUL << FLASH_OBR_DATA1_Pos)
8240#define FLASH_OBR_DATA1 FLASH_OBR_DATA1_Msk
8242/* Legacy defines */
8243#define FLASH_OBR_WDG_SW FLASH_OBR_IWDG_SW
8244
8245/****************** Bit definition for FLASH_WRPR register ******************/
8246#define FLASH_WRPR_WRP_Pos (0U)
8247#define FLASH_WRPR_WRP_Msk (0xFFFFFFFFUL << FLASH_WRPR_WRP_Pos)
8248#define FLASH_WRPR_WRP FLASH_WRPR_WRP_Msk
8250/*----------------------------------------------------------------------------*/
8251
8252/****************** Bit definition for OB_RDP register **********************/
8253#define OB_RDP_RDP_Pos (0U)
8254#define OB_RDP_RDP_Msk (0xFFUL << OB_RDP_RDP_Pos)
8255#define OB_RDP_RDP OB_RDP_RDP_Msk
8256#define OB_RDP_nRDP_Pos (8U)
8257#define OB_RDP_nRDP_Msk (0xFFUL << OB_RDP_nRDP_Pos)
8258#define OB_RDP_nRDP OB_RDP_nRDP_Msk
8260/****************** Bit definition for OB_USER register *********************/
8261#define OB_USER_USER_Pos (16U)
8262#define OB_USER_USER_Msk (0xFFUL << OB_USER_USER_Pos)
8263#define OB_USER_USER OB_USER_USER_Msk
8264#define OB_USER_nUSER_Pos (24U)
8265#define OB_USER_nUSER_Msk (0xFFUL << OB_USER_nUSER_Pos)
8266#define OB_USER_nUSER OB_USER_nUSER_Msk
8268/****************** Bit definition for FLASH_WRP0 register ******************/
8269#define OB_WRP0_WRP0_Pos (0U)
8270#define OB_WRP0_WRP0_Msk (0xFFUL << OB_WRP0_WRP0_Pos)
8271#define OB_WRP0_WRP0 OB_WRP0_WRP0_Msk
8272#define OB_WRP0_nWRP0_Pos (8U)
8273#define OB_WRP0_nWRP0_Msk (0xFFUL << OB_WRP0_nWRP0_Pos)
8274#define OB_WRP0_nWRP0 OB_WRP0_nWRP0_Msk
8276/****************** Bit definition for FLASH_WRP1 register ******************/
8277#define OB_WRP1_WRP1_Pos (16U)
8278#define OB_WRP1_WRP1_Msk (0xFFUL << OB_WRP1_WRP1_Pos)
8279#define OB_WRP1_WRP1 OB_WRP1_WRP1_Msk
8280#define OB_WRP1_nWRP1_Pos (24U)
8281#define OB_WRP1_nWRP1_Msk (0xFFUL << OB_WRP1_nWRP1_Pos)
8282#define OB_WRP1_nWRP1 OB_WRP1_nWRP1_Msk
8284/****************** Bit definition for FLASH_WRP2 register ******************/
8285#define OB_WRP2_WRP2_Pos (0U)
8286#define OB_WRP2_WRP2_Msk (0xFFUL << OB_WRP2_WRP2_Pos)
8287#define OB_WRP2_WRP2 OB_WRP2_WRP2_Msk
8288#define OB_WRP2_nWRP2_Pos (8U)
8289#define OB_WRP2_nWRP2_Msk (0xFFUL << OB_WRP2_nWRP2_Pos)
8290#define OB_WRP2_nWRP2 OB_WRP2_nWRP2_Msk
8292/****************** Bit definition for FLASH_WRP3 register ******************/
8293#define OB_WRP3_WRP3_Pos (16U)
8294#define OB_WRP3_WRP3_Msk (0xFFUL << OB_WRP3_WRP3_Pos)
8295#define OB_WRP3_WRP3 OB_WRP3_WRP3_Msk
8296#define OB_WRP3_nWRP3_Pos (24U)
8297#define OB_WRP3_nWRP3_Msk (0xFFUL << OB_WRP3_nWRP3_Pos)
8298#define OB_WRP3_nWRP3 OB_WRP3_nWRP3_Msk
8300/******************************************************************************/
8301/* */
8302/* Flexible Memory Controller */
8303/* */
8304/******************************************************************************/
8305/****************** Bit definition for FMC_BCRx register *******************/
8306#define FMC_BCRx_MBKEN_Pos (0U)
8307#define FMC_BCRx_MBKEN_Msk (0x1UL << FMC_BCRx_MBKEN_Pos)
8308#define FMC_BCRx_MBKEN FMC_BCRx_MBKEN_Msk
8309#define FMC_BCRx_MUXEN_Pos (1U)
8310#define FMC_BCRx_MUXEN_Msk (0x1UL << FMC_BCRx_MUXEN_Pos)
8311#define FMC_BCRx_MUXEN FMC_BCRx_MUXEN_Msk
8313#define FMC_BCRx_MTYP_Pos (2U)
8314#define FMC_BCRx_MTYP_Msk (0x3UL << FMC_BCRx_MTYP_Pos)
8315#define FMC_BCRx_MTYP FMC_BCRx_MTYP_Msk
8316#define FMC_BCRx_MTYP_0 (0x1UL << FMC_BCRx_MTYP_Pos)
8317#define FMC_BCRx_MTYP_1 (0x2UL << FMC_BCRx_MTYP_Pos)
8319#define FMC_BCRx_MWID_Pos (4U)
8320#define FMC_BCRx_MWID_Msk (0x3UL << FMC_BCRx_MWID_Pos)
8321#define FMC_BCRx_MWID FMC_BCRx_MWID_Msk
8322#define FMC_BCRx_MWID_0 (0x1UL << FMC_BCRx_MWID_Pos)
8323#define FMC_BCRx_MWID_1 (0x2UL << FMC_BCRx_MWID_Pos)
8325#define FMC_BCRx_FACCEN_Pos (6U)
8326#define FMC_BCRx_FACCEN_Msk (0x1UL << FMC_BCRx_FACCEN_Pos)
8327#define FMC_BCRx_FACCEN FMC_BCRx_FACCEN_Msk
8328#define FMC_BCRx_BURSTEN_Pos (8U)
8329#define FMC_BCRx_BURSTEN_Msk (0x1UL << FMC_BCRx_BURSTEN_Pos)
8330#define FMC_BCRx_BURSTEN FMC_BCRx_BURSTEN_Msk
8331#define FMC_BCRx_WAITPOL_Pos (9U)
8332#define FMC_BCRx_WAITPOL_Msk (0x1UL << FMC_BCRx_WAITPOL_Pos)
8333#define FMC_BCRx_WAITPOL FMC_BCRx_WAITPOL_Msk
8334#define FMC_BCRx_WRAPMOD_Pos (10U)
8335#define FMC_BCRx_WRAPMOD_Msk (0x1UL << FMC_BCRx_WRAPMOD_Pos)
8336#define FMC_BCRx_WRAPMOD FMC_BCRx_WRAPMOD_Msk
8337#define FMC_BCRx_WAITCFG_Pos (11U)
8338#define FMC_BCRx_WAITCFG_Msk (0x1UL << FMC_BCRx_WAITCFG_Pos)
8339#define FMC_BCRx_WAITCFG FMC_BCRx_WAITCFG_Msk
8340#define FMC_BCRx_WREN_Pos (12U)
8341#define FMC_BCRx_WREN_Msk (0x1UL << FMC_BCRx_WREN_Pos)
8342#define FMC_BCRx_WREN FMC_BCRx_WREN_Msk
8343#define FMC_BCRx_WAITEN_Pos (13U)
8344#define FMC_BCRx_WAITEN_Msk (0x1UL << FMC_BCRx_WAITEN_Pos)
8345#define FMC_BCRx_WAITEN FMC_BCRx_WAITEN_Msk
8346#define FMC_BCRx_EXTMOD_Pos (14U)
8347#define FMC_BCRx_EXTMOD_Msk (0x1UL << FMC_BCRx_EXTMOD_Pos)
8348#define FMC_BCRx_EXTMOD FMC_BCRx_EXTMOD_Msk
8349#define FMC_BCRx_ASYNCWAIT_Pos (15U)
8350#define FMC_BCRx_ASYNCWAIT_Msk (0x1UL << FMC_BCRx_ASYNCWAIT_Pos)
8351#define FMC_BCRx_ASYNCWAIT FMC_BCRx_ASYNCWAIT_Msk
8352#define FMC_BCRx_CBURSTRW_Pos (19U)
8353#define FMC_BCRx_CBURSTRW_Msk (0x1UL << FMC_BCRx_CBURSTRW_Pos)
8354#define FMC_BCRx_CBURSTRW FMC_BCRx_CBURSTRW_Msk
8356/****************** Bit definition for FMC_BCR1 register *******************/
8357#define FMC_BCR1_MBKEN_Pos (0U)
8358#define FMC_BCR1_MBKEN_Msk (0x1UL << FMC_BCR1_MBKEN_Pos)
8359#define FMC_BCR1_MBKEN FMC_BCR1_MBKEN_Msk
8360#define FMC_BCR1_MUXEN_Pos (1U)
8361#define FMC_BCR1_MUXEN_Msk (0x1UL << FMC_BCR1_MUXEN_Pos)
8362#define FMC_BCR1_MUXEN FMC_BCR1_MUXEN_Msk
8364#define FMC_BCR1_MTYP_Pos (2U)
8365#define FMC_BCR1_MTYP_Msk (0x3UL << FMC_BCR1_MTYP_Pos)
8366#define FMC_BCR1_MTYP FMC_BCR1_MTYP_Msk
8367#define FMC_BCR1_MTYP_0 (0x1UL << FMC_BCR1_MTYP_Pos)
8368#define FMC_BCR1_MTYP_1 (0x2UL << FMC_BCR1_MTYP_Pos)
8370#define FMC_BCR1_MWID_Pos (4U)
8371#define FMC_BCR1_MWID_Msk (0x3UL << FMC_BCR1_MWID_Pos)
8372#define FMC_BCR1_MWID FMC_BCR1_MWID_Msk
8373#define FMC_BCR1_MWID_0 (0x1UL << FMC_BCR1_MWID_Pos)
8374#define FMC_BCR1_MWID_1 (0x2UL << FMC_BCR1_MWID_Pos)
8376#define FMC_BCR1_FACCEN_Pos (6U)
8377#define FMC_BCR1_FACCEN_Msk (0x1UL << FMC_BCR1_FACCEN_Pos)
8378#define FMC_BCR1_FACCEN FMC_BCR1_FACCEN_Msk
8379#define FMC_BCR1_BURSTEN_Pos (8U)
8380#define FMC_BCR1_BURSTEN_Msk (0x1UL << FMC_BCR1_BURSTEN_Pos)
8381#define FMC_BCR1_BURSTEN FMC_BCR1_BURSTEN_Msk
8382#define FMC_BCR1_WAITPOL_Pos (9U)
8383#define FMC_BCR1_WAITPOL_Msk (0x1UL << FMC_BCR1_WAITPOL_Pos)
8384#define FMC_BCR1_WAITPOL FMC_BCR1_WAITPOL_Msk
8385#define FMC_BCR1_WRAPMOD_Pos (10U)
8386#define FMC_BCR1_WRAPMOD_Msk (0x1UL << FMC_BCR1_WRAPMOD_Pos)
8387#define FMC_BCR1_WRAPMOD FMC_BCR1_WRAPMOD_Msk
8388#define FMC_BCR1_WAITCFG_Pos (11U)
8389#define FMC_BCR1_WAITCFG_Msk (0x1UL << FMC_BCR1_WAITCFG_Pos)
8390#define FMC_BCR1_WAITCFG FMC_BCR1_WAITCFG_Msk
8391#define FMC_BCR1_WREN_Pos (12U)
8392#define FMC_BCR1_WREN_Msk (0x1UL << FMC_BCR1_WREN_Pos)
8393#define FMC_BCR1_WREN FMC_BCR1_WREN_Msk
8394#define FMC_BCR1_WAITEN_Pos (13U)
8395#define FMC_BCR1_WAITEN_Msk (0x1UL << FMC_BCR1_WAITEN_Pos)
8396#define FMC_BCR1_WAITEN FMC_BCR1_WAITEN_Msk
8397#define FMC_BCR1_EXTMOD_Pos (14U)
8398#define FMC_BCR1_EXTMOD_Msk (0x1UL << FMC_BCR1_EXTMOD_Pos)
8399#define FMC_BCR1_EXTMOD FMC_BCR1_EXTMOD_Msk
8400#define FMC_BCR1_ASYNCWAIT_Pos (15U)
8401#define FMC_BCR1_ASYNCWAIT_Msk (0x1UL << FMC_BCR1_ASYNCWAIT_Pos)
8402#define FMC_BCR1_ASYNCWAIT FMC_BCR1_ASYNCWAIT_Msk
8403#define FMC_BCR1_CBURSTRW_Pos (19U)
8404#define FMC_BCR1_CBURSTRW_Msk (0x1UL << FMC_BCR1_CBURSTRW_Pos)
8405#define FMC_BCR1_CBURSTRW FMC_BCR1_CBURSTRW_Msk
8406#define FMC_BCR1_CCLKEN_Pos (20U)
8407#define FMC_BCR1_CCLKEN_Msk (0x1UL << FMC_BCR1_CCLKEN_Pos)
8408#define FMC_BCR1_CCLKEN FMC_BCR1_CCLKEN_Msk
8410/****************** Bit definition for FMC_BCR2 register *******************/
8411#define FMC_BCR2_MBKEN_Pos (0U)
8412#define FMC_BCR2_MBKEN_Msk (0x1UL << FMC_BCR2_MBKEN_Pos)
8413#define FMC_BCR2_MBKEN FMC_BCR2_MBKEN_Msk
8414#define FMC_BCR2_MUXEN_Pos (1U)
8415#define FMC_BCR2_MUXEN_Msk (0x1UL << FMC_BCR2_MUXEN_Pos)
8416#define FMC_BCR2_MUXEN FMC_BCR2_MUXEN_Msk
8418#define FMC_BCR2_MTYP_Pos (2U)
8419#define FMC_BCR2_MTYP_Msk (0x3UL << FMC_BCR2_MTYP_Pos)
8420#define FMC_BCR2_MTYP FMC_BCR2_MTYP_Msk
8421#define FMC_BCR2_MTYP_0 (0x1UL << FMC_BCR2_MTYP_Pos)
8422#define FMC_BCR2_MTYP_1 (0x2UL << FMC_BCR2_MTYP_Pos)
8424#define FMC_BCR2_MWID_Pos (4U)
8425#define FMC_BCR2_MWID_Msk (0x3UL << FMC_BCR2_MWID_Pos)
8426#define FMC_BCR2_MWID FMC_BCR2_MWID_Msk
8427#define FMC_BCR2_MWID_0 (0x1UL << FMC_BCR2_MWID_Pos)
8428#define FMC_BCR2_MWID_1 (0x2UL << FMC_BCR2_MWID_Pos)
8430#define FMC_BCR2_FACCEN_Pos (6U)
8431#define FMC_BCR2_FACCEN_Msk (0x1UL << FMC_BCR2_FACCEN_Pos)
8432#define FMC_BCR2_FACCEN FMC_BCR2_FACCEN_Msk
8433#define FMC_BCR2_BURSTEN_Pos (8U)
8434#define FMC_BCR2_BURSTEN_Msk (0x1UL << FMC_BCR2_BURSTEN_Pos)
8435#define FMC_BCR2_BURSTEN FMC_BCR2_BURSTEN_Msk
8436#define FMC_BCR2_WAITPOL_Pos (9U)
8437#define FMC_BCR2_WAITPOL_Msk (0x1UL << FMC_BCR2_WAITPOL_Pos)
8438#define FMC_BCR2_WAITPOL FMC_BCR2_WAITPOL_Msk
8439#define FMC_BCR2_WRAPMOD_Pos (10U)
8440#define FMC_BCR2_WRAPMOD_Msk (0x1UL << FMC_BCR2_WRAPMOD_Pos)
8441#define FMC_BCR2_WRAPMOD FMC_BCR2_WRAPMOD_Msk
8442#define FMC_BCR2_WAITCFG_Pos (11U)
8443#define FMC_BCR2_WAITCFG_Msk (0x1UL << FMC_BCR2_WAITCFG_Pos)
8444#define FMC_BCR2_WAITCFG FMC_BCR2_WAITCFG_Msk
8445#define FMC_BCR2_WREN_Pos (12U)
8446#define FMC_BCR2_WREN_Msk (0x1UL << FMC_BCR2_WREN_Pos)
8447#define FMC_BCR2_WREN FMC_BCR2_WREN_Msk
8448#define FMC_BCR2_WAITEN_Pos (13U)
8449#define FMC_BCR2_WAITEN_Msk (0x1UL << FMC_BCR2_WAITEN_Pos)
8450#define FMC_BCR2_WAITEN FMC_BCR2_WAITEN_Msk
8451#define FMC_BCR2_EXTMOD_Pos (14U)
8452#define FMC_BCR2_EXTMOD_Msk (0x1UL << FMC_BCR2_EXTMOD_Pos)
8453#define FMC_BCR2_EXTMOD FMC_BCR2_EXTMOD_Msk
8454#define FMC_BCR2_ASYNCWAIT_Pos (15U)
8455#define FMC_BCR2_ASYNCWAIT_Msk (0x1UL << FMC_BCR2_ASYNCWAIT_Pos)
8456#define FMC_BCR2_ASYNCWAIT FMC_BCR2_ASYNCWAIT_Msk
8457#define FMC_BCR2_CBURSTRW_Pos (19U)
8458#define FMC_BCR2_CBURSTRW_Msk (0x1UL << FMC_BCR2_CBURSTRW_Pos)
8459#define FMC_BCR2_CBURSTRW FMC_BCR2_CBURSTRW_Msk
8461/****************** Bit definition for FMC_BCR3 register *******************/
8462#define FMC_BCR3_MBKEN_Pos (0U)
8463#define FMC_BCR3_MBKEN_Msk (0x1UL << FMC_BCR3_MBKEN_Pos)
8464#define FMC_BCR3_MBKEN FMC_BCR3_MBKEN_Msk
8465#define FMC_BCR3_MUXEN_Pos (1U)
8466#define FMC_BCR3_MUXEN_Msk (0x1UL << FMC_BCR3_MUXEN_Pos)
8467#define FMC_BCR3_MUXEN FMC_BCR3_MUXEN_Msk
8469#define FMC_BCR3_MTYP_Pos (2U)
8470#define FMC_BCR3_MTYP_Msk (0x3UL << FMC_BCR3_MTYP_Pos)
8471#define FMC_BCR3_MTYP FMC_BCR3_MTYP_Msk
8472#define FMC_BCR3_MTYP_0 (0x1UL << FMC_BCR3_MTYP_Pos)
8473#define FMC_BCR3_MTYP_1 (0x2UL << FMC_BCR3_MTYP_Pos)
8475#define FMC_BCR3_MWID_Pos (4U)
8476#define FMC_BCR3_MWID_Msk (0x3UL << FMC_BCR3_MWID_Pos)
8477#define FMC_BCR3_MWID FMC_BCR3_MWID_Msk
8478#define FMC_BCR3_MWID_0 (0x1UL << FMC_BCR3_MWID_Pos)
8479#define FMC_BCR3_MWID_1 (0x2UL << FMC_BCR3_MWID_Pos)
8481#define FMC_BCR3_FACCEN_Pos (6U)
8482#define FMC_BCR3_FACCEN_Msk (0x1UL << FMC_BCR3_FACCEN_Pos)
8483#define FMC_BCR3_FACCEN FMC_BCR3_FACCEN_Msk
8484#define FMC_BCR3_BURSTEN_Pos (8U)
8485#define FMC_BCR3_BURSTEN_Msk (0x1UL << FMC_BCR3_BURSTEN_Pos)
8486#define FMC_BCR3_BURSTEN FMC_BCR3_BURSTEN_Msk
8487#define FMC_BCR3_WAITPOL_Pos (9U)
8488#define FMC_BCR3_WAITPOL_Msk (0x1UL << FMC_BCR3_WAITPOL_Pos)
8489#define FMC_BCR3_WAITPOL FMC_BCR3_WAITPOL_Msk
8490#define FMC_BCR3_WRAPMOD_Pos (10U)
8491#define FMC_BCR3_WRAPMOD_Msk (0x1UL << FMC_BCR3_WRAPMOD_Pos)
8492#define FMC_BCR3_WRAPMOD FMC_BCR3_WRAPMOD_Msk
8493#define FMC_BCR3_WAITCFG_Pos (11U)
8494#define FMC_BCR3_WAITCFG_Msk (0x1UL << FMC_BCR3_WAITCFG_Pos)
8495#define FMC_BCR3_WAITCFG FMC_BCR3_WAITCFG_Msk
8496#define FMC_BCR3_WREN_Pos (12U)
8497#define FMC_BCR3_WREN_Msk (0x1UL << FMC_BCR3_WREN_Pos)
8498#define FMC_BCR3_WREN FMC_BCR3_WREN_Msk
8499#define FMC_BCR3_WAITEN_Pos (13U)
8500#define FMC_BCR3_WAITEN_Msk (0x1UL << FMC_BCR3_WAITEN_Pos)
8501#define FMC_BCR3_WAITEN FMC_BCR3_WAITEN_Msk
8502#define FMC_BCR3_EXTMOD_Pos (14U)
8503#define FMC_BCR3_EXTMOD_Msk (0x1UL << FMC_BCR3_EXTMOD_Pos)
8504#define FMC_BCR3_EXTMOD FMC_BCR3_EXTMOD_Msk
8505#define FMC_BCR3_ASYNCWAIT_Pos (15U)
8506#define FMC_BCR3_ASYNCWAIT_Msk (0x1UL << FMC_BCR3_ASYNCWAIT_Pos)
8507#define FMC_BCR3_ASYNCWAIT FMC_BCR3_ASYNCWAIT_Msk
8508#define FMC_BCR3_CBURSTRW_Pos (19U)
8509#define FMC_BCR3_CBURSTRW_Msk (0x1UL << FMC_BCR3_CBURSTRW_Pos)
8510#define FMC_BCR3_CBURSTRW FMC_BCR3_CBURSTRW_Msk
8512/****************** Bit definition for FMC_BCR4 register *******************/
8513#define FMC_BCR4_MBKEN_Pos (0U)
8514#define FMC_BCR4_MBKEN_Msk (0x1UL << FMC_BCR4_MBKEN_Pos)
8515#define FMC_BCR4_MBKEN FMC_BCR4_MBKEN_Msk
8516#define FMC_BCR4_MUXEN_Pos (1U)
8517#define FMC_BCR4_MUXEN_Msk (0x1UL << FMC_BCR4_MUXEN_Pos)
8518#define FMC_BCR4_MUXEN FMC_BCR4_MUXEN_Msk
8520#define FMC_BCR4_MTYP_Pos (2U)
8521#define FMC_BCR4_MTYP_Msk (0x3UL << FMC_BCR4_MTYP_Pos)
8522#define FMC_BCR4_MTYP FMC_BCR4_MTYP_Msk
8523#define FMC_BCR4_MTYP_0 (0x1UL << FMC_BCR4_MTYP_Pos)
8524#define FMC_BCR4_MTYP_1 (0x2UL << FMC_BCR4_MTYP_Pos)
8526#define FMC_BCR4_MWID_Pos (4U)
8527#define FMC_BCR4_MWID_Msk (0x3UL << FMC_BCR4_MWID_Pos)
8528#define FMC_BCR4_MWID FMC_BCR4_MWID_Msk
8529#define FMC_BCR4_MWID_0 (0x1UL << FMC_BCR4_MWID_Pos)
8530#define FMC_BCR4_MWID_1 (0x2UL << FMC_BCR4_MWID_Pos)
8532#define FMC_BCR4_FACCEN_Pos (6U)
8533#define FMC_BCR4_FACCEN_Msk (0x1UL << FMC_BCR4_FACCEN_Pos)
8534#define FMC_BCR4_FACCEN FMC_BCR4_FACCEN_Msk
8535#define FMC_BCR4_BURSTEN_Pos (8U)
8536#define FMC_BCR4_BURSTEN_Msk (0x1UL << FMC_BCR4_BURSTEN_Pos)
8537#define FMC_BCR4_BURSTEN FMC_BCR4_BURSTEN_Msk
8538#define FMC_BCR4_WAITPOL_Pos (9U)
8539#define FMC_BCR4_WAITPOL_Msk (0x1UL << FMC_BCR4_WAITPOL_Pos)
8540#define FMC_BCR4_WAITPOL FMC_BCR4_WAITPOL_Msk
8541#define FMC_BCR4_WRAPMOD_Pos (10U)
8542#define FMC_BCR4_WRAPMOD_Msk (0x1UL << FMC_BCR4_WRAPMOD_Pos)
8543#define FMC_BCR4_WRAPMOD FMC_BCR4_WRAPMOD_Msk
8544#define FMC_BCR4_WAITCFG_Pos (11U)
8545#define FMC_BCR4_WAITCFG_Msk (0x1UL << FMC_BCR4_WAITCFG_Pos)
8546#define FMC_BCR4_WAITCFG FMC_BCR4_WAITCFG_Msk
8547#define FMC_BCR4_WREN_Pos (12U)
8548#define FMC_BCR4_WREN_Msk (0x1UL << FMC_BCR4_WREN_Pos)
8549#define FMC_BCR4_WREN FMC_BCR4_WREN_Msk
8550#define FMC_BCR4_WAITEN_Pos (13U)
8551#define FMC_BCR4_WAITEN_Msk (0x1UL << FMC_BCR4_WAITEN_Pos)
8552#define FMC_BCR4_WAITEN FMC_BCR4_WAITEN_Msk
8553#define FMC_BCR4_EXTMOD_Pos (14U)
8554#define FMC_BCR4_EXTMOD_Msk (0x1UL << FMC_BCR4_EXTMOD_Pos)
8555#define FMC_BCR4_EXTMOD FMC_BCR4_EXTMOD_Msk
8556#define FMC_BCR4_ASYNCWAIT_Pos (15U)
8557#define FMC_BCR4_ASYNCWAIT_Msk (0x1UL << FMC_BCR4_ASYNCWAIT_Pos)
8558#define FMC_BCR4_ASYNCWAIT FMC_BCR4_ASYNCWAIT_Msk
8559#define FMC_BCR4_CBURSTRW_Pos (19U)
8560#define FMC_BCR4_CBURSTRW_Msk (0x1UL << FMC_BCR4_CBURSTRW_Pos)
8561#define FMC_BCR4_CBURSTRW FMC_BCR4_CBURSTRW_Msk
8563/****************** Bit definition for FMC_BTRx register ******************/
8564#define FMC_BTRx_ADDSET_Pos (0U)
8565#define FMC_BTRx_ADDSET_Msk (0xFUL << FMC_BTRx_ADDSET_Pos)
8566#define FMC_BTRx_ADDSET FMC_BTRx_ADDSET_Msk
8567#define FMC_BTRx_ADDSET_0 (0x1UL << FMC_BTRx_ADDSET_Pos)
8568#define FMC_BTRx_ADDSET_1 (0x2UL << FMC_BTRx_ADDSET_Pos)
8569#define FMC_BTRx_ADDSET_2 (0x4UL << FMC_BTRx_ADDSET_Pos)
8570#define FMC_BTR_ADDSET_3 (0x00000008U)
8572#define FMC_BTRx_ADDHLD_Pos (4U)
8573#define FMC_BTRx_ADDHLD_Msk (0xFUL << FMC_BTRx_ADDHLD_Pos)
8574#define FMC_BTRx_ADDHLD FMC_BTRx_ADDHLD_Msk
8575#define FMC_BTRx_ADDHLD_0 (0x1UL << FMC_BTRx_ADDHLD_Pos)
8576#define FMC_BTRx_ADDHLD_1 (0x2UL << FMC_BTRx_ADDHLD_Pos)
8577#define FMC_BTRx_ADDHLD_2 (0x4UL << FMC_BTRx_ADDHLD_Pos)
8578#define FMC_BTRx_ADDHLD_3 (0x8UL << FMC_BTRx_ADDHLD_Pos)
8580#define FMC_BTRx_DATAST_Pos (8U)
8581#define FMC_BTRx_DATAST_Msk (0xFFUL << FMC_BTRx_DATAST_Pos)
8582#define FMC_BTRx_DATAST FMC_BTRx_DATAST_Msk
8583#define FMC_BTR_DATAST_0 (0x00000100U)
8584#define FMC_BTRx_DATAST_1 (0x00000200U)
8585#define FMC_BTRx_DATAST_2 (0x00000400U)
8586#define FMC_BTRx_DATAST_3 (0x00000800U)
8587#define FMC_BTRx_DATAST_4 (0x00001000U)
8588#define FMC_BTRx_DATAST_5 (0x00002000U)
8589#define FMC_BTRx_DATAST_6 (0x00004000U)
8590#define FMC_BTRx_DATAST_7 (0x00008000U)
8592#define FMC_BTRx_BUSTURN_Pos (16U)
8593#define FMC_BTRx_BUSTURN_Msk (0xFUL << FMC_BTRx_BUSTURN_Pos)
8594#define FMC_BTRx_BUSTURN FMC_BTRx_BUSTURN_Msk
8595#define FMC_BTRx_BUSTURN_0 (0x1UL << FMC_BTRx_BUSTURN_Pos)
8596#define FMC_BTRx_BUSTURN_1 (0x2UL << FMC_BTRx_BUSTURN_Pos)
8597#define FMC_BTRx_BUSTURN_2 (0x4UL << FMC_BTRx_BUSTURN_Pos)
8598#define FMC_BTRx_BUSTURN_3 (0x8UL << FMC_BTRx_BUSTURN_Pos)
8600#define FMC_BTRx_CLKDIV_Pos (20U)
8601#define FMC_BTRx_CLKDIV_Msk (0xFUL << FMC_BTRx_CLKDIV_Pos)
8602#define FMC_BTRx_CLKDIV FMC_BTRx_CLKDIV_Msk
8603#define FMC_BTRx_CLKDIV_0 (0x1UL << FMC_BTRx_CLKDIV_Pos)
8604#define FMC_BTRx_CLKDIV_1 (0x2UL << FMC_BTRx_CLKDIV_Pos)
8605#define FMC_BTRx_CLKDIV_2 (0x4UL << FMC_BTRx_CLKDIV_Pos)
8606#define FMC_BTRx_CLKDIV_3 (0x8UL << FMC_BTRx_CLKDIV_Pos)
8608#define FMC_BTRx_DATLAT_Pos (24U)
8609#define FMC_BTRx_DATLAT_Msk (0xFUL << FMC_BTRx_DATLAT_Pos)
8610#define FMC_BTRx_DATLAT FMC_BTRx_DATLAT_Msk
8611#define FMC_BTRx_DATLAT_0 (0x1UL << FMC_BTRx_DATLAT_Pos)
8612#define FMC_BTRx_DATLAT_1 (0x2UL << FMC_BTRx_DATLAT_Pos)
8613#define FMC_BTRx_DATLAT_2 (0x4UL << FMC_BTRx_DATLAT_Pos)
8614#define FMC_BTRx_DATLAT_3 (0x8UL << FMC_BTRx_DATLAT_Pos)
8616#define FMC_BTRx_ACCMOD_Pos (28U)
8617#define FMC_BTRx_ACCMOD_Msk (0x3UL << FMC_BTRx_ACCMOD_Pos)
8618#define FMC_BTRx_ACCMOD FMC_BTRx_ACCMOD_Msk
8619#define FMC_BTRx_ACCMOD_0 (0x1UL << FMC_BTRx_ACCMOD_Pos)
8620#define FMC_BTRx_ACCMOD_1 (0x2UL << FMC_BTRx_ACCMOD_Pos)
8622/****************** Bit definition for FMC_BTR1 register ******************/
8623#define FMC_BTR1_ADDSET_Pos (0U)
8624#define FMC_BTR1_ADDSET_Msk (0xFUL << FMC_BTR1_ADDSET_Pos)
8625#define FMC_BTR1_ADDSET FMC_BTR1_ADDSET_Msk
8626#define FMC_BTR1_ADDSET_0 (0x1UL << FMC_BTR1_ADDSET_Pos)
8627#define FMC_BTR1_ADDSET_1 (0x2UL << FMC_BTR1_ADDSET_Pos)
8628#define FMC_BTR1_ADDSET_2 (0x4UL << FMC_BTR1_ADDSET_Pos)
8629#define FMC_BTR1_ADDSET_3 (0x8UL << FMC_BTR1_ADDSET_Pos)
8631#define FMC_BTR1_ADDHLD_Pos (4U)
8632#define FMC_BTR1_ADDHLD_Msk (0xFUL << FMC_BTR1_ADDHLD_Pos)
8633#define FMC_BTR1_ADDHLD FMC_BTR1_ADDHLD_Msk
8634#define FMC_BTR1_ADDHLD_0 (0x1UL << FMC_BTR1_ADDHLD_Pos)
8635#define FMC_BTR1_ADDHLD_1 (0x2UL << FMC_BTR1_ADDHLD_Pos)
8636#define FMC_BTR1_ADDHLD_2 (0x4UL << FMC_BTR1_ADDHLD_Pos)
8637#define FMC_BTR1_ADDHLD_3 (0x8UL << FMC_BTR1_ADDHLD_Pos)
8639#define FMC_BTR1_DATAST_Pos (8U)
8640#define FMC_BTR1_DATAST_Msk (0xFFUL << FMC_BTR1_DATAST_Pos)
8641#define FMC_BTR1_DATAST FMC_BTR1_DATAST_Msk
8642#define FMC_BTR1_DATAST_0 (0x01UL << FMC_BTR1_DATAST_Pos)
8643#define FMC_BTR1_DATAST_1 (0x02UL << FMC_BTR1_DATAST_Pos)
8644#define FMC_BTR1_DATAST_2 (0x04UL << FMC_BTR1_DATAST_Pos)
8645#define FMC_BTR1_DATAST_3 (0x08UL << FMC_BTR1_DATAST_Pos)
8646#define FMC_BTR1_DATAST_4 (0x10UL << FMC_BTR1_DATAST_Pos)
8647#define FMC_BTR1_DATAST_5 (0x20UL << FMC_BTR1_DATAST_Pos)
8648#define FMC_BTR1_DATAST_6 (0x40UL << FMC_BTR1_DATAST_Pos)
8649#define FMC_BTR1_DATAST_7 (0x80UL << FMC_BTR1_DATAST_Pos)
8651#define FMC_BTR1_BUSTURN_Pos (16U)
8652#define FMC_BTR1_BUSTURN_Msk (0xFUL << FMC_BTR1_BUSTURN_Pos)
8653#define FMC_BTR1_BUSTURN FMC_BTR1_BUSTURN_Msk
8654#define FMC_BTR1_BUSTURN_0 (0x1UL << FMC_BTR1_BUSTURN_Pos)
8655#define FMC_BTR1_BUSTURN_1 (0x2UL << FMC_BTR1_BUSTURN_Pos)
8656#define FMC_BTR1_BUSTURN_2 (0x4UL << FMC_BTR1_BUSTURN_Pos)
8657#define FMC_BTR1_BUSTURN_3 (0x8UL << FMC_BTR1_BUSTURN_Pos)
8659#define FMC_BTR1_CLKDIV_Pos (20U)
8660#define FMC_BTR1_CLKDIV_Msk (0xFUL << FMC_BTR1_CLKDIV_Pos)
8661#define FMC_BTR1_CLKDIV FMC_BTR1_CLKDIV_Msk
8662#define FMC_BTR1_CLKDIV_0 (0x1UL << FMC_BTR1_CLKDIV_Pos)
8663#define FMC_BTR1_CLKDIV_1 (0x2UL << FMC_BTR1_CLKDIV_Pos)
8664#define FMC_BTR1_CLKDIV_2 (0x4UL << FMC_BTR1_CLKDIV_Pos)
8665#define FMC_BTR1_CLKDIV_3 (0x8UL << FMC_BTR1_CLKDIV_Pos)
8667#define FMC_BTR1_DATLAT_Pos (24U)
8668#define FMC_BTR1_DATLAT_Msk (0xFUL << FMC_BTR1_DATLAT_Pos)
8669#define FMC_BTR1_DATLAT FMC_BTR1_DATLAT_Msk
8670#define FMC_BTR1_DATLAT_0 (0x1UL << FMC_BTR1_DATLAT_Pos)
8671#define FMC_BTR1_DATLAT_1 (0x2UL << FMC_BTR1_DATLAT_Pos)
8672#define FMC_BTR1_DATLAT_2 (0x4UL << FMC_BTR1_DATLAT_Pos)
8673#define FMC_BTR1_DATLAT_3 (0x8UL << FMC_BTR1_DATLAT_Pos)
8675#define FMC_BTR1_ACCMOD_Pos (28U)
8676#define FMC_BTR1_ACCMOD_Msk (0x3UL << FMC_BTR1_ACCMOD_Pos)
8677#define FMC_BTR1_ACCMOD FMC_BTR1_ACCMOD_Msk
8678#define FMC_BTR1_ACCMOD_0 (0x1UL << FMC_BTR1_ACCMOD_Pos)
8679#define FMC_BTR1_ACCMOD_1 (0x2UL << FMC_BTR1_ACCMOD_Pos)
8681/****************** Bit definition for FMC_BTR2 register *******************/
8682#define FMC_BTR2_ADDSET_Pos (0U)
8683#define FMC_BTR2_ADDSET_Msk (0xFUL << FMC_BTR2_ADDSET_Pos)
8684#define FMC_BTR2_ADDSET FMC_BTR2_ADDSET_Msk
8685#define FMC_BTR2_ADDSET_0 (0x1UL << FMC_BTR2_ADDSET_Pos)
8686#define FMC_BTR2_ADDSET_1 (0x2UL << FMC_BTR2_ADDSET_Pos)
8687#define FMC_BTR2_ADDSET_2 (0x4UL << FMC_BTR2_ADDSET_Pos)
8688#define FMC_BTR2_ADDSET_3 (0x8UL << FMC_BTR2_ADDSET_Pos)
8690#define FMC_BTR2_ADDHLD_Pos (4U)
8691#define FMC_BTR2_ADDHLD_Msk (0xFUL << FMC_BTR2_ADDHLD_Pos)
8692#define FMC_BTR2_ADDHLD FMC_BTR2_ADDHLD_Msk
8693#define FMC_BTR2_ADDHLD_0 (0x1UL << FMC_BTR2_ADDHLD_Pos)
8694#define FMC_BTR2_ADDHLD_1 (0x2UL << FMC_BTR2_ADDHLD_Pos)
8695#define FMC_BTR2_ADDHLD_2 (0x4UL << FMC_BTR2_ADDHLD_Pos)
8696#define FMC_BTR2_ADDHLD_3 (0x8UL << FMC_BTR2_ADDHLD_Pos)
8698#define FMC_BTR2_DATAST_Pos (8U)
8699#define FMC_BTR2_DATAST_Msk (0xFFUL << FMC_BTR2_DATAST_Pos)
8700#define FMC_BTR2_DATAST FMC_BTR2_DATAST_Msk
8701#define FMC_BTR2_DATAST_0 (0x01UL << FMC_BTR2_DATAST_Pos)
8702#define FMC_BTR2_DATAST_1 (0x02UL << FMC_BTR2_DATAST_Pos)
8703#define FMC_BTR2_DATAST_2 (0x04UL << FMC_BTR2_DATAST_Pos)
8704#define FMC_BTR2_DATAST_3 (0x08UL << FMC_BTR2_DATAST_Pos)
8705#define FMC_BTR2_DATAST_4 (0x10UL << FMC_BTR2_DATAST_Pos)
8706#define FMC_BTR2_DATAST_5 (0x20UL << FMC_BTR2_DATAST_Pos)
8707#define FMC_BTR2_DATAST_6 (0x40UL << FMC_BTR2_DATAST_Pos)
8708#define FMC_BTR2_DATAST_7 (0x80UL << FMC_BTR2_DATAST_Pos)
8710#define FMC_BTR2_BUSTURN_Pos (16U)
8711#define FMC_BTR2_BUSTURN_Msk (0xFUL << FMC_BTR2_BUSTURN_Pos)
8712#define FMC_BTR2_BUSTURN FMC_BTR2_BUSTURN_Msk
8713#define FMC_BTR2_BUSTURN_0 (0x1UL << FMC_BTR2_BUSTURN_Pos)
8714#define FMC_BTR2_BUSTURN_1 (0x2UL << FMC_BTR2_BUSTURN_Pos)
8715#define FMC_BTR2_BUSTURN_2 (0x4UL << FMC_BTR2_BUSTURN_Pos)
8716#define FMC_BTR2_BUSTURN_3 (0x8UL << FMC_BTR2_BUSTURN_Pos)
8718#define FMC_BTR2_CLKDIV_Pos (20U)
8719#define FMC_BTR2_CLKDIV_Msk (0xFUL << FMC_BTR2_CLKDIV_Pos)
8720#define FMC_BTR2_CLKDIV FMC_BTR2_CLKDIV_Msk
8721#define FMC_BTR2_CLKDIV_0 (0x1UL << FMC_BTR2_CLKDIV_Pos)
8722#define FMC_BTR2_CLKDIV_1 (0x2UL << FMC_BTR2_CLKDIV_Pos)
8723#define FMC_BTR2_CLKDIV_2 (0x4UL << FMC_BTR2_CLKDIV_Pos)
8724#define FMC_BTR2_CLKDIV_3 (0x8UL << FMC_BTR2_CLKDIV_Pos)
8726#define FMC_BTR2_DATLAT_Pos (24U)
8727#define FMC_BTR2_DATLAT_Msk (0xFUL << FMC_BTR2_DATLAT_Pos)
8728#define FMC_BTR2_DATLAT FMC_BTR2_DATLAT_Msk
8729#define FMC_BTR2_DATLAT_0 (0x1UL << FMC_BTR2_DATLAT_Pos)
8730#define FMC_BTR2_DATLAT_1 (0x2UL << FMC_BTR2_DATLAT_Pos)
8731#define FMC_BTR2_DATLAT_2 (0x4UL << FMC_BTR2_DATLAT_Pos)
8732#define FMC_BTR2_DATLAT_3 (0x8UL << FMC_BTR2_DATLAT_Pos)
8734#define FMC_BTR2_ACCMOD_Pos (28U)
8735#define FMC_BTR2_ACCMOD_Msk (0x3UL << FMC_BTR2_ACCMOD_Pos)
8736#define FMC_BTR2_ACCMOD FMC_BTR2_ACCMOD_Msk
8737#define FMC_BTR2_ACCMOD_0 (0x1UL << FMC_BTR2_ACCMOD_Pos)
8738#define FMC_BTR2_ACCMOD_1 (0x2UL << FMC_BTR2_ACCMOD_Pos)
8740/******************* Bit definition for FMC_BTR3 register *******************/
8741#define FMC_BTR3_ADDSET_Pos (0U)
8742#define FMC_BTR3_ADDSET_Msk (0xFUL << FMC_BTR3_ADDSET_Pos)
8743#define FMC_BTR3_ADDSET FMC_BTR3_ADDSET_Msk
8744#define FMC_BTR3_ADDSET_0 (0x1UL << FMC_BTR3_ADDSET_Pos)
8745#define FMC_BTR3_ADDSET_1 (0x2UL << FMC_BTR3_ADDSET_Pos)
8746#define FMC_BTR3_ADDSET_2 (0x4UL << FMC_BTR3_ADDSET_Pos)
8747#define FMC_BTR3_ADDSET_3 (0x8UL << FMC_BTR3_ADDSET_Pos)
8749#define FMC_BTR3_ADDHLD_Pos (4U)
8750#define FMC_BTR3_ADDHLD_Msk (0xFUL << FMC_BTR3_ADDHLD_Pos)
8751#define FMC_BTR3_ADDHLD FMC_BTR3_ADDHLD_Msk
8752#define FMC_BTR3_ADDHLD_0 (0x1UL << FMC_BTR3_ADDHLD_Pos)
8753#define FMC_BTR3_ADDHLD_1 (0x2UL << FMC_BTR3_ADDHLD_Pos)
8754#define FMC_BTR3_ADDHLD_2 (0x4UL << FMC_BTR3_ADDHLD_Pos)
8755#define FMC_BTR3_ADDHLD_3 (0x8UL << FMC_BTR3_ADDHLD_Pos)
8757#define FMC_BTR3_DATAST_Pos (8U)
8758#define FMC_BTR3_DATAST_Msk (0xFFUL << FMC_BTR3_DATAST_Pos)
8759#define FMC_BTR3_DATAST FMC_BTR3_DATAST_Msk
8760#define FMC_BTR3_DATAST_0 (0x01UL << FMC_BTR3_DATAST_Pos)
8761#define FMC_BTR3_DATAST_1 (0x02UL << FMC_BTR3_DATAST_Pos)
8762#define FMC_BTR3_DATAST_2 (0x04UL << FMC_BTR3_DATAST_Pos)
8763#define FMC_BTR3_DATAST_3 (0x08UL << FMC_BTR3_DATAST_Pos)
8764#define FMC_BTR3_DATAST_4 (0x10UL << FMC_BTR3_DATAST_Pos)
8765#define FMC_BTR3_DATAST_5 (0x20UL << FMC_BTR3_DATAST_Pos)
8766#define FMC_BTR3_DATAST_6 (0x40UL << FMC_BTR3_DATAST_Pos)
8767#define FMC_BTR3_DATAST_7 (0x80UL << FMC_BTR3_DATAST_Pos)
8769#define FMC_BTR3_BUSTURN_Pos (16U)
8770#define FMC_BTR3_BUSTURN_Msk (0xFUL << FMC_BTR3_BUSTURN_Pos)
8771#define FMC_BTR3_BUSTURN FMC_BTR3_BUSTURN_Msk
8772#define FMC_BTR3_BUSTURN_0 (0x1UL << FMC_BTR3_BUSTURN_Pos)
8773#define FMC_BTR3_BUSTURN_1 (0x2UL << FMC_BTR3_BUSTURN_Pos)
8774#define FMC_BTR3_BUSTURN_2 (0x4UL << FMC_BTR3_BUSTURN_Pos)
8775#define FMC_BTR3_BUSTURN_3 (0x8UL << FMC_BTR3_BUSTURN_Pos)
8777#define FMC_BTR3_CLKDIV_Pos (20U)
8778#define FMC_BTR3_CLKDIV_Msk (0xFUL << FMC_BTR3_CLKDIV_Pos)
8779#define FMC_BTR3_CLKDIV FMC_BTR3_CLKDIV_Msk
8780#define FMC_BTR3_CLKDIV_0 (0x1UL << FMC_BTR3_CLKDIV_Pos)
8781#define FMC_BTR3_CLKDIV_1 (0x2UL << FMC_BTR3_CLKDIV_Pos)
8782#define FMC_BTR3_CLKDIV_2 (0x4UL << FMC_BTR3_CLKDIV_Pos)
8783#define FMC_BTR3_CLKDIV_3 (0x8UL << FMC_BTR3_CLKDIV_Pos)
8785#define FMC_BTR3_DATLAT_Pos (24U)
8786#define FMC_BTR3_DATLAT_Msk (0xFUL << FMC_BTR3_DATLAT_Pos)
8787#define FMC_BTR3_DATLAT FMC_BTR3_DATLAT_Msk
8788#define FMC_BTR3_DATLAT_0 (0x1UL << FMC_BTR3_DATLAT_Pos)
8789#define FMC_BTR3_DATLAT_1 (0x2UL << FMC_BTR3_DATLAT_Pos)
8790#define FMC_BTR3_DATLAT_2 (0x4UL << FMC_BTR3_DATLAT_Pos)
8791#define FMC_BTR3_DATLAT_3 (0x8UL << FMC_BTR3_DATLAT_Pos)
8793#define FMC_BTR3_ACCMOD_Pos (28U)
8794#define FMC_BTR3_ACCMOD_Msk (0x3UL << FMC_BTR3_ACCMOD_Pos)
8795#define FMC_BTR3_ACCMOD FMC_BTR3_ACCMOD_Msk
8796#define FMC_BTR3_ACCMOD_0 (0x1UL << FMC_BTR3_ACCMOD_Pos)
8797#define FMC_BTR3_ACCMOD_1 (0x2UL << FMC_BTR3_ACCMOD_Pos)
8799/****************** Bit definition for FMC_BTR4 register *******************/
8800#define FMC_BTR4_ADDSET_Pos (0U)
8801#define FMC_BTR4_ADDSET_Msk (0xFUL << FMC_BTR4_ADDSET_Pos)
8802#define FMC_BTR4_ADDSET FMC_BTR4_ADDSET_Msk
8803#define FMC_BTR4_ADDSET_0 (0x1UL << FMC_BTR4_ADDSET_Pos)
8804#define FMC_BTR4_ADDSET_1 (0x2UL << FMC_BTR4_ADDSET_Pos)
8805#define FMC_BTR4_ADDSET_2 (0x4UL << FMC_BTR4_ADDSET_Pos)
8806#define FMC_BTR4_ADDSET_3 (0x8UL << FMC_BTR4_ADDSET_Pos)
8808#define FMC_BTR4_ADDHLD_Pos (4U)
8809#define FMC_BTR4_ADDHLD_Msk (0xFUL << FMC_BTR4_ADDHLD_Pos)
8810#define FMC_BTR4_ADDHLD FMC_BTR4_ADDHLD_Msk
8811#define FMC_BTR4_ADDHLD_0 (0x1UL << FMC_BTR4_ADDHLD_Pos)
8812#define FMC_BTR4_ADDHLD_1 (0x2UL << FMC_BTR4_ADDHLD_Pos)
8813#define FMC_BTR4_ADDHLD_2 (0x4UL << FMC_BTR4_ADDHLD_Pos)
8814#define FMC_BTR4_ADDHLD_3 (0x8UL << FMC_BTR4_ADDHLD_Pos)
8816#define FMC_BTR4_DATAST_Pos (8U)
8817#define FMC_BTR4_DATAST_Msk (0xFFUL << FMC_BTR4_DATAST_Pos)
8818#define FMC_BTR4_DATAST FMC_BTR4_DATAST_Msk
8819#define FMC_BTR4_DATAST_0 (0x01UL << FMC_BTR4_DATAST_Pos)
8820#define FMC_BTR4_DATAST_1 (0x02UL << FMC_BTR4_DATAST_Pos)
8821#define FMC_BTR4_DATAST_2 (0x04UL << FMC_BTR4_DATAST_Pos)
8822#define FMC_BTR4_DATAST_3 (0x08UL << FMC_BTR4_DATAST_Pos)
8823#define FMC_BTR4_DATAST_4 (0x10UL << FMC_BTR4_DATAST_Pos)
8824#define FMC_BTR4_DATAST_5 (0x20UL << FMC_BTR4_DATAST_Pos)
8825#define FMC_BTR4_DATAST_6 (0x40UL << FMC_BTR4_DATAST_Pos)
8826#define FMC_BTR4_DATAST_7 (0x80UL << FMC_BTR4_DATAST_Pos)
8828#define FMC_BTR4_BUSTURN_Pos (16U)
8829#define FMC_BTR4_BUSTURN_Msk (0xFUL << FMC_BTR4_BUSTURN_Pos)
8830#define FMC_BTR4_BUSTURN FMC_BTR4_BUSTURN_Msk
8831#define FMC_BTR4_BUSTURN_0 (0x1UL << FMC_BTR4_BUSTURN_Pos)
8832#define FMC_BTR4_BUSTURN_1 (0x2UL << FMC_BTR4_BUSTURN_Pos)
8833#define FMC_BTR4_BUSTURN_2 (0x4UL << FMC_BTR4_BUSTURN_Pos)
8834#define FMC_BTR4_BUSTURN_3 (0x8UL << FMC_BTR4_BUSTURN_Pos)
8836#define FMC_BTR4_CLKDIV_Pos (20U)
8837#define FMC_BTR4_CLKDIV_Msk (0xFUL << FMC_BTR4_CLKDIV_Pos)
8838#define FMC_BTR4_CLKDIV FMC_BTR4_CLKDIV_Msk
8839#define FMC_BTR4_CLKDIV_0 (0x1UL << FMC_BTR4_CLKDIV_Pos)
8840#define FMC_BTR4_CLKDIV_1 (0x2UL << FMC_BTR4_CLKDIV_Pos)
8841#define FMC_BTR4_CLKDIV_2 (0x4UL << FMC_BTR4_CLKDIV_Pos)
8842#define FMC_BTR4_CLKDIV_3 (0x8UL << FMC_BTR4_CLKDIV_Pos)
8844#define FMC_BTR4_DATLAT_Pos (24U)
8845#define FMC_BTR4_DATLAT_Msk (0xFUL << FMC_BTR4_DATLAT_Pos)
8846#define FMC_BTR4_DATLAT FMC_BTR4_DATLAT_Msk
8847#define FMC_BTR4_DATLAT_0 (0x1UL << FMC_BTR4_DATLAT_Pos)
8848#define FMC_BTR4_DATLAT_1 (0x2UL << FMC_BTR4_DATLAT_Pos)
8849#define FMC_BTR4_DATLAT_2 (0x4UL << FMC_BTR4_DATLAT_Pos)
8850#define FMC_BTR4_DATLAT_3 (0x8UL << FMC_BTR4_DATLAT_Pos)
8852#define FMC_BTR4_ACCMOD_Pos (28U)
8853#define FMC_BTR4_ACCMOD_Msk (0x3UL << FMC_BTR4_ACCMOD_Pos)
8854#define FMC_BTR4_ACCMOD FMC_BTR4_ACCMOD_Msk
8855#define FMC_BTR4_ACCMOD_0 (0x1UL << FMC_BTR4_ACCMOD_Pos)
8856#define FMC_BTR4_ACCMOD_1 (0x2UL << FMC_BTR4_ACCMOD_Pos)
8858/****************** Bit definition for FMC_BWTRx register ******************/
8859#define FMC_BWTRx_ADDSET_Pos (0U)
8860#define FMC_BWTRx_ADDSET_Msk (0xFUL << FMC_BWTRx_ADDSET_Pos)
8861#define FMC_BWTRx_ADDSET FMC_BWTRx_ADDSET_Msk
8862#define FMC_BWTRx_ADDSET_0 (0x1UL << FMC_BWTRx_ADDSET_Pos)
8863#define FMC_BWTRx_ADDSET_1 (0x2UL << FMC_BWTRx_ADDSET_Pos)
8864#define FMC_BWTRx_ADDSET_2 (0x4UL << FMC_BWTRx_ADDSET_Pos)
8865#define FMC_BWTRx_ADDSET_3 (0x8UL << FMC_BWTRx_ADDSET_Pos)
8867#define FMC_BWTRx_ADDHLD_Pos (4U)
8868#define FMC_BWTRx_ADDHLD_Msk (0xFUL << FMC_BWTRx_ADDHLD_Pos)
8869#define FMC_BWTRx_ADDHLD FMC_BWTRx_ADDHLD_Msk
8870#define FMC_BWTRx_ADDHLD_0 (0x1UL << FMC_BWTRx_ADDHLD_Pos)
8871#define FMC_BWTRx_ADDHLD_1 (0x2UL << FMC_BWTRx_ADDHLD_Pos)
8872#define FMC_BWTRx_ADDHLD_2 (0x4UL << FMC_BWTRx_ADDHLD_Pos)
8873#define FMC_BWTRx_ADDHLD_3 (0x8UL << FMC_BWTRx_ADDHLD_Pos)
8875#define FMC_BWTRx_DATAST_Pos (8U)
8876#define FMC_BWTRx_DATAST_Msk (0xFFUL << FMC_BWTRx_DATAST_Pos)
8877#define FMC_BWTRx_DATAST FMC_BWTRx_DATAST_Msk
8878#define FMC_BWTRx_DATAST_0 (0x01UL << FMC_BWTRx_DATAST_Pos)
8879#define FMC_BWTRx_DATAST_1 (0x02UL << FMC_BWTRx_DATAST_Pos)
8880#define FMC_BWTRx_DATAST_2 (0x04UL << FMC_BWTRx_DATAST_Pos)
8881#define FMC_BWTRx_DATAST_3 (0x08UL << FMC_BWTRx_DATAST_Pos)
8882#define FMC_BWTRx_DATAST_4 (0x10UL << FMC_BWTRx_DATAST_Pos)
8883#define FMC_BWTRx_DATAST_5 (0x20UL << FMC_BWTRx_DATAST_Pos)
8884#define FMC_BWTRx_DATAST_6 (0x40UL << FMC_BWTRx_DATAST_Pos)
8885#define FMC_BWTRx_DATAST_7 (0x80UL << FMC_BWTRx_DATAST_Pos)
8887#define FMC_BWTRx_ACCMOD_Pos (28U)
8888#define FMC_BWTRx_ACCMOD_Msk (0x3UL << FMC_BWTRx_ACCMOD_Pos)
8889#define FMC_BWTRx_ACCMOD FMC_BWTRx_ACCMOD_Msk
8890#define FMC_BWTRx_ACCMOD_0 (0x1UL << FMC_BWTRx_ACCMOD_Pos)
8891#define FMC_BWTRx_ACCMOD_1 (0x2UL << FMC_BWTRx_ACCMOD_Pos)
8893/* Old Bit definition for FMC_BWTRx register maintained for legacy purpose */
8894#define FMC_BWTRx_ADDSETx FMC_BWTRx_ADDSET
8895#define FMC_BWTRx_ADDSETx_0 FMC_BWTRx_ADDSET_0
8896#define FMC_BWTRx_ADDSETx_1 FMC_BWTRx_ADDSET_1
8897#define FMC_BWTRx_ADDSETx_2 FMC_BWTRx_ADDSET_2
8898#define FMC_BWTRx_ADDSETx_3 FMC_BWTRx_ADDSET_3
8899
8900#define FMC_BWTRx_ADDHLDx FMC_BWTRx_ADDHLD
8901#define FMC_BWTRx_ADDHLDx_0 FMC_BWTRx_ADDHLD_0
8902#define FMC_BWTRx_ADDHLDx_1 FMC_BWTRx_ADDHLD_1
8903#define FMC_BWTRx_ADDHLDx_2 FMC_BWTRx_ADDHLD_2
8904#define FMC_BWTRx_ADDHLDx_3 FMC_BWTRx_ADDHLD_3
8905
8906#define FMC_BWTRx_DATASTx FMC_BWTRx_DATAST
8907#define FMC_BWTRx_DATASTx_0 FMC_BWTRx_DATAST_0
8908#define FMC_BWTRx_DATASTx_1 FMC_BWTRx_DATAST_1
8909#define FMC_BWTRx_DATASTx_2 FMC_BWTRx_DATAST_2
8910#define FMC_BWTRx_DATASTx_3 FMC_BWTRx_DATAST_3
8911#define FMC_BWTRx_DATASTx_4 FMC_BWTRx_DATAST_4
8912#define FMC_BWTRx_DATASTx_5 FMC_BWTRx_DATAST_5
8913#define FMC_BWTRx_DATASTx_6 FMC_BWTRx_DATAST_6
8914#define FMC_BWTRx_DATASTx_7 FMC_BWTRx_DATAST_7
8915
8916#define FMC_BWTRx_ACCMODx FMC_BWTRx_ACCMOD
8917#define FMC_BWTRx_ACCMODx_0 FMC_BWTRx_ACCMOD_0
8918#define FMC_BWTRx_ACCMODx_1 FMC_BWTRx_ACCMOD_1
8919
8920/****************** Bit definition for FMC_BWTR1 register ******************/
8921#define FMC_BWTR1_ADDSET_Pos (0U)
8922#define FMC_BWTR1_ADDSET_Msk (0xFUL << FMC_BWTR1_ADDSET_Pos)
8923#define FMC_BWTR1_ADDSET FMC_BWTR1_ADDSET_Msk
8924#define FMC_BWTR1_ADDSET_0 (0x1UL << FMC_BWTR1_ADDSET_Pos)
8925#define FMC_BWTR1_ADDSET_1 (0x2UL << FMC_BWTR1_ADDSET_Pos)
8926#define FMC_BWTR1_ADDSET_2 (0x4UL << FMC_BWTR1_ADDSET_Pos)
8927#define FMC_BWTR1_ADDSET_3 (0x8UL << FMC_BWTR1_ADDSET_Pos)
8929#define FMC_BWTR1_ADDHLD_Pos (4U)
8930#define FMC_BWTR1_ADDHLD_Msk (0xFUL << FMC_BWTR1_ADDHLD_Pos)
8931#define FMC_BWTR1_ADDHLD FMC_BWTR1_ADDHLD_Msk
8932#define FMC_BWTR1_ADDHLD_0 (0x1UL << FMC_BWTR1_ADDHLD_Pos)
8933#define FMC_BWTR1_ADDHLD_1 (0x2UL << FMC_BWTR1_ADDHLD_Pos)
8934#define FMC_BWTR1_ADDHLD_2 (0x4UL << FMC_BWTR1_ADDHLD_Pos)
8935#define FMC_BWTR1_ADDHLD_3 (0x8UL << FMC_BWTR1_ADDHLD_Pos)
8937#define FMC_BWTR1_DATAST_Pos (8U)
8938#define FMC_BWTR1_DATAST_Msk (0xFFUL << FMC_BWTR1_DATAST_Pos)
8939#define FMC_BWTR1_DATAST FMC_BWTR1_DATAST_Msk
8940#define FMC_BWTR1_DATAST_0 (0x01UL << FMC_BWTR1_DATAST_Pos)
8941#define FMC_BWTR1_DATAST_1 (0x02UL << FMC_BWTR1_DATAST_Pos)
8942#define FMC_BWTR1_DATAST_2 (0x04UL << FMC_BWTR1_DATAST_Pos)
8943#define FMC_BWTR1_DATAST_3 (0x08UL << FMC_BWTR1_DATAST_Pos)
8944#define FMC_BWTR1_DATAST_4 (0x10UL << FMC_BWTR1_DATAST_Pos)
8945#define FMC_BWTR1_DATAST_5 (0x20UL << FMC_BWTR1_DATAST_Pos)
8946#define FMC_BWTR1_DATAST_6 (0x40UL << FMC_BWTR1_DATAST_Pos)
8947#define FMC_BWTR1_DATAST_7 (0x80UL << FMC_BWTR1_DATAST_Pos)
8949#define FMC_BWTR1_CLKDIV_Pos (20U)
8950#define FMC_BWTR1_CLKDIV_Msk (0xFUL << FMC_BWTR1_CLKDIV_Pos)
8951#define FMC_BWTR1_CLKDIV FMC_BWTR1_CLKDIV_Msk
8952#define FMC_BWTR1_CLKDIV_0 (0x1UL << FMC_BWTR1_CLKDIV_Pos)
8953#define FMC_BWTR1_CLKDIV_1 (0x2UL << FMC_BWTR1_CLKDIV_Pos)
8954#define FMC_BWTR1_CLKDIV_2 (0x4UL << FMC_BWTR1_CLKDIV_Pos)
8955#define FMC_BWTR1_CLKDIV_3 (0x8UL << FMC_BWTR1_CLKDIV_Pos)
8957#define FMC_BWTR1_DATLAT_Pos (24U)
8958#define FMC_BWTR1_DATLAT_Msk (0xFUL << FMC_BWTR1_DATLAT_Pos)
8959#define FMC_BWTR1_DATLAT FMC_BWTR1_DATLAT_Msk
8960#define FMC_BWTR1_DATLAT_0 (0x1UL << FMC_BWTR1_DATLAT_Pos)
8961#define FMC_BWTR1_DATLAT_1 (0x2UL << FMC_BWTR1_DATLAT_Pos)
8962#define FMC_BWTR1_DATLAT_2 (0x4UL << FMC_BWTR1_DATLAT_Pos)
8963#define FMC_BWTR1_DATLAT_3 (0x8UL << FMC_BWTR1_DATLAT_Pos)
8965#define FMC_BWTR1_ACCMOD_Pos (28U)
8966#define FMC_BWTR1_ACCMOD_Msk (0x3UL << FMC_BWTR1_ACCMOD_Pos)
8967#define FMC_BWTR1_ACCMOD FMC_BWTR1_ACCMOD_Msk
8968#define FMC_BWTR1_ACCMOD_0 (0x1UL << FMC_BWTR1_ACCMOD_Pos)
8969#define FMC_BWTR1_ACCMOD_1 (0x2UL << FMC_BWTR1_ACCMOD_Pos)
8971/****************** Bit definition for FMC_BWTR2 register ******************/
8972#define FMC_BWTR2_ADDSET_Pos (0U)
8973#define FMC_BWTR2_ADDSET_Msk (0xFUL << FMC_BWTR2_ADDSET_Pos)
8974#define FMC_BWTR2_ADDSET FMC_BWTR2_ADDSET_Msk
8975#define FMC_BWTR2_ADDSET_0 (0x1UL << FMC_BWTR2_ADDSET_Pos)
8976#define FMC_BWTR2_ADDSET_1 (0x2UL << FMC_BWTR2_ADDSET_Pos)
8977#define FMC_BWTR2_ADDSET_2 (0x4UL << FMC_BWTR2_ADDSET_Pos)
8978#define FMC_BWTR2_ADDSET_3 (0x8UL << FMC_BWTR2_ADDSET_Pos)
8980#define FMC_BWTR2_ADDHLD_Pos (4U)
8981#define FMC_BWTR2_ADDHLD_Msk (0xFUL << FMC_BWTR2_ADDHLD_Pos)
8982#define FMC_BWTR2_ADDHLD FMC_BWTR2_ADDHLD_Msk
8983#define FMC_BWTR2_ADDHLD_0 (0x1UL << FMC_BWTR2_ADDHLD_Pos)
8984#define FMC_BWTR2_ADDHLD_1 (0x2UL << FMC_BWTR2_ADDHLD_Pos)
8985#define FMC_BWTR2_ADDHLD_2 (0x4UL << FMC_BWTR2_ADDHLD_Pos)
8986#define FMC_BWTR2_ADDHLD_3 (0x8UL << FMC_BWTR2_ADDHLD_Pos)
8988#define FMC_BWTR2_DATAST_Pos (8U)
8989#define FMC_BWTR2_DATAST_Msk (0xFFUL << FMC_BWTR2_DATAST_Pos)
8990#define FMC_BWTR2_DATAST FMC_BWTR2_DATAST_Msk
8991#define FMC_BWTR2_DATAST_0 (0x01UL << FMC_BWTR2_DATAST_Pos)
8992#define FMC_BWTR2_DATAST_1 (0x02UL << FMC_BWTR2_DATAST_Pos)
8993#define FMC_BWTR2_DATAST_2 (0x04UL << FMC_BWTR2_DATAST_Pos)
8994#define FMC_BWTR2_DATAST_3 (0x08UL << FMC_BWTR2_DATAST_Pos)
8995#define FMC_BWTR2_DATAST_4 (0x10UL << FMC_BWTR2_DATAST_Pos)
8996#define FMC_BWTR2_DATAST_5 (0x20UL << FMC_BWTR2_DATAST_Pos)
8997#define FMC_BWTR2_DATAST_6 (0x40UL << FMC_BWTR2_DATAST_Pos)
8998#define FMC_BWTR2_DATAST_7 (0x80UL << FMC_BWTR2_DATAST_Pos)
9000#define FMC_BWTR2_CLKDIV_Pos (20U)
9001#define FMC_BWTR2_CLKDIV_Msk (0xFUL << FMC_BWTR2_CLKDIV_Pos)
9002#define FMC_BWTR2_CLKDIV FMC_BWTR2_CLKDIV_Msk
9003#define FMC_BWTR2_CLKDIV_0 (0x1UL << FMC_BWTR2_CLKDIV_Pos)
9004#define FMC_BWTR2_CLKDIV_1 (0x2UL << FMC_BWTR2_CLKDIV_Pos)
9005#define FMC_BWTR2_CLKDIV_2 (0x4UL << FMC_BWTR2_CLKDIV_Pos)
9006#define FMC_BWTR2_CLKDIV_3 (0x8UL << FMC_BWTR2_CLKDIV_Pos)
9008#define FMC_BWTR2_DATLAT_Pos (24U)
9009#define FMC_BWTR2_DATLAT_Msk (0xFUL << FMC_BWTR2_DATLAT_Pos)
9010#define FMC_BWTR2_DATLAT FMC_BWTR2_DATLAT_Msk
9011#define FMC_BWTR2_DATLAT_0 (0x1UL << FMC_BWTR2_DATLAT_Pos)
9012#define FMC_BWTR2_DATLAT_1 (0x2UL << FMC_BWTR2_DATLAT_Pos)
9013#define FMC_BWTR2_DATLAT_2 (0x4UL << FMC_BWTR2_DATLAT_Pos)
9014#define FMC_BWTR2_DATLAT_3 (0x8UL << FMC_BWTR2_DATLAT_Pos)
9016#define FMC_BWTR2_ACCMOD_Pos (28U)
9017#define FMC_BWTR2_ACCMOD_Msk (0x3UL << FMC_BWTR2_ACCMOD_Pos)
9018#define FMC_BWTR2_ACCMOD FMC_BWTR2_ACCMOD_Msk
9019#define FMC_BWTR2_ACCMOD_0 (0x1UL << FMC_BWTR2_ACCMOD_Pos)
9020#define FMC_BWTR2_ACCMOD_1 (0x2UL << FMC_BWTR2_ACCMOD_Pos)
9022/****************** Bit definition for FMC_BWTR3 register ******************/
9023#define FMC_BWTR3_ADDSET_Pos (0U)
9024#define FMC_BWTR3_ADDSET_Msk (0xFUL << FMC_BWTR3_ADDSET_Pos)
9025#define FMC_BWTR3_ADDSET FMC_BWTR3_ADDSET_Msk
9026#define FMC_BWTR3_ADDSET_0 (0x1UL << FMC_BWTR3_ADDSET_Pos)
9027#define FMC_BWTR3_ADDSET_1 (0x2UL << FMC_BWTR3_ADDSET_Pos)
9028#define FMC_BWTR3_ADDSET_2 (0x4UL << FMC_BWTR3_ADDSET_Pos)
9029#define FMC_BWTR3_ADDSET_3 (0x8UL << FMC_BWTR3_ADDSET_Pos)
9031#define FMC_BWTR3_ADDHLD_Pos (4U)
9032#define FMC_BWTR3_ADDHLD_Msk (0xFUL << FMC_BWTR3_ADDHLD_Pos)
9033#define FMC_BWTR3_ADDHLD FMC_BWTR3_ADDHLD_Msk
9034#define FMC_BWTR3_ADDHLD_0 (0x1UL << FMC_BWTR3_ADDHLD_Pos)
9035#define FMC_BWTR3_ADDHLD_1 (0x2UL << FMC_BWTR3_ADDHLD_Pos)
9036#define FMC_BWTR3_ADDHLD_2 (0x4UL << FMC_BWTR3_ADDHLD_Pos)
9037#define FMC_BWTR3_ADDHLD_3 (0x8UL << FMC_BWTR3_ADDHLD_Pos)
9039#define FMC_BWTR3_DATAST_Pos (8U)
9040#define FMC_BWTR3_DATAST_Msk (0xFFUL << FMC_BWTR3_DATAST_Pos)
9041#define FMC_BWTR3_DATAST FMC_BWTR3_DATAST_Msk
9042#define FMC_BWTR3_DATAST_0 (0x01UL << FMC_BWTR3_DATAST_Pos)
9043#define FMC_BWTR3_DATAST_1 (0x02UL << FMC_BWTR3_DATAST_Pos)
9044#define FMC_BWTR3_DATAST_2 (0x04UL << FMC_BWTR3_DATAST_Pos)
9045#define FMC_BWTR3_DATAST_3 (0x08UL << FMC_BWTR3_DATAST_Pos)
9046#define FMC_BWTR3_DATAST_4 (0x10UL << FMC_BWTR3_DATAST_Pos)
9047#define FMC_BWTR3_DATAST_5 (0x20UL << FMC_BWTR3_DATAST_Pos)
9048#define FMC_BWTR3_DATAST_6 (0x40UL << FMC_BWTR3_DATAST_Pos)
9049#define FMC_BWTR3_DATAST_7 (0x80UL << FMC_BWTR3_DATAST_Pos)
9051#define FMC_BWTR3_CLKDIV_Pos (20U)
9052#define FMC_BWTR3_CLKDIV_Msk (0xFUL << FMC_BWTR3_CLKDIV_Pos)
9053#define FMC_BWTR3_CLKDIV FMC_BWTR3_CLKDIV_Msk
9054#define FMC_BWTR3_CLKDIV_0 (0x1UL << FMC_BWTR3_CLKDIV_Pos)
9055#define FMC_BWTR3_CLKDIV_1 (0x2UL << FMC_BWTR3_CLKDIV_Pos)
9056#define FMC_BWTR3_CLKDIV_2 (0x4UL << FMC_BWTR3_CLKDIV_Pos)
9057#define FMC_BWTR3_CLKDIV_3 (0x8UL << FMC_BWTR3_CLKDIV_Pos)
9059#define FMC_BWTR3_DATLAT_Pos (24U)
9060#define FMC_BWTR3_DATLAT_Msk (0xFUL << FMC_BWTR3_DATLAT_Pos)
9061#define FMC_BWTR3_DATLAT FMC_BWTR3_DATLAT_Msk
9062#define FMC_BWTR3_DATLAT_0 (0x1UL << FMC_BWTR3_DATLAT_Pos)
9063#define FMC_BWTR3_DATLAT_1 (0x2UL << FMC_BWTR3_DATLAT_Pos)
9064#define FMC_BWTR3_DATLAT_2 (0x4UL << FMC_BWTR3_DATLAT_Pos)
9065#define FMC_BWTR3_DATLAT_3 (0x8UL << FMC_BWTR3_DATLAT_Pos)
9067#define FMC_BWTR3_ACCMOD_Pos (28U)
9068#define FMC_BWTR3_ACCMOD_Msk (0x3UL << FMC_BWTR3_ACCMOD_Pos)
9069#define FMC_BWTR3_ACCMOD FMC_BWTR3_ACCMOD_Msk
9070#define FMC_BWTR3_ACCMOD_0 (0x1UL << FMC_BWTR3_ACCMOD_Pos)
9071#define FMC_BWTR3_ACCMOD_1 (0x2UL << FMC_BWTR3_ACCMOD_Pos)
9073/****************** Bit definition for FMC_BWTR4 register ******************/
9074#define FMC_BWTR4_ADDSET_Pos (0U)
9075#define FMC_BWTR4_ADDSET_Msk (0xFUL << FMC_BWTR4_ADDSET_Pos)
9076#define FMC_BWTR4_ADDSET FMC_BWTR4_ADDSET_Msk
9077#define FMC_BWTR4_ADDSET_0 (0x1UL << FMC_BWTR4_ADDSET_Pos)
9078#define FMC_BWTR4_ADDSET_1 (0x2UL << FMC_BWTR4_ADDSET_Pos)
9079#define FMC_BWTR4_ADDSET_2 (0x4UL << FMC_BWTR4_ADDSET_Pos)
9080#define FMC_BWTR4_ADDSET_3 (0x8UL << FMC_BWTR4_ADDSET_Pos)
9082#define FMC_BWTR4_ADDHLD_Pos (4U)
9083#define FMC_BWTR4_ADDHLD_Msk (0xFUL << FMC_BWTR4_ADDHLD_Pos)
9084#define FMC_BWTR4_ADDHLD FMC_BWTR4_ADDHLD_Msk
9085#define FMC_BWTR4_ADDHLD_0 (0x1UL << FMC_BWTR4_ADDHLD_Pos)
9086#define FMC_BWTR4_ADDHLD_1 (0x2UL << FMC_BWTR4_ADDHLD_Pos)
9087#define FMC_BWTR4_ADDHLD_2 (0x4UL << FMC_BWTR4_ADDHLD_Pos)
9088#define FMC_BWTR4_ADDHLD_3 (0x8UL << FMC_BWTR4_ADDHLD_Pos)
9090#define FMC_BWTR4_DATAST_Pos (8U)
9091#define FMC_BWTR4_DATAST_Msk (0xFFUL << FMC_BWTR4_DATAST_Pos)
9092#define FMC_BWTR4_DATAST FMC_BWTR4_DATAST_Msk
9093#define FMC_BWTR4_DATAST_0 (0x01UL << FMC_BWTR4_DATAST_Pos)
9094#define FMC_BWTR4_DATAST_1 (0x02UL << FMC_BWTR4_DATAST_Pos)
9095#define FMC_BWTR4_DATAST_2 (0x04UL << FMC_BWTR4_DATAST_Pos)
9096#define FMC_BWTR4_DATAST_3 (0x08UL << FMC_BWTR4_DATAST_Pos)
9097#define FMC_BWTR4_DATAST_4 (0x10UL << FMC_BWTR4_DATAST_Pos)
9098#define FMC_BWTR4_DATAST_5 (0x20UL << FMC_BWTR4_DATAST_Pos)
9099#define FMC_BWTR4_DATAST_6 (0x40UL << FMC_BWTR4_DATAST_Pos)
9100#define FMC_BWTR4_DATAST_7 (0x80UL << FMC_BWTR4_DATAST_Pos)
9102#define FMC_BWTR4_CLKDIV_Pos (20U)
9103#define FMC_BWTR4_CLKDIV_Msk (0xFUL << FMC_BWTR4_CLKDIV_Pos)
9104#define FMC_BWTR4_CLKDIV FMC_BWTR4_CLKDIV_Msk
9105#define FMC_BWTR4_CLKDIV_0 (0x1UL << FMC_BWTR4_CLKDIV_Pos)
9106#define FMC_BWTR4_CLKDIV_1 (0x2UL << FMC_BWTR4_CLKDIV_Pos)
9107#define FMC_BWTR4_CLKDIV_2 (0x4UL << FMC_BWTR4_CLKDIV_Pos)
9108#define FMC_BWTR4_CLKDIV_3 (0x8UL << FMC_BWTR4_CLKDIV_Pos)
9110#define FMC_BWTR4_DATLAT_Pos (24U)
9111#define FMC_BWTR4_DATLAT_Msk (0xFUL << FMC_BWTR4_DATLAT_Pos)
9112#define FMC_BWTR4_DATLAT FMC_BWTR4_DATLAT_Msk
9113#define FMC_BWTR4_DATLAT_0 (0x1UL << FMC_BWTR4_DATLAT_Pos)
9114#define FMC_BWTR4_DATLAT_1 (0x2UL << FMC_BWTR4_DATLAT_Pos)
9115#define FMC_BWTR4_DATLAT_2 (0x4UL << FMC_BWTR4_DATLAT_Pos)
9116#define FMC_BWTR4_DATLAT_3 (0x8UL << FMC_BWTR4_DATLAT_Pos)
9118#define FMC_BWTR4_ACCMOD_Pos (28U)
9119#define FMC_BWTR4_ACCMOD_Msk (0x3UL << FMC_BWTR4_ACCMOD_Pos)
9120#define FMC_BWTR4_ACCMOD FMC_BWTR4_ACCMOD_Msk
9121#define FMC_BWTR4_ACCMOD_0 (0x1UL << FMC_BWTR4_ACCMOD_Pos)
9122#define FMC_BWTR4_ACCMOD_1 (0x2UL << FMC_BWTR4_ACCMOD_Pos)
9124/****************** Bit definition for FMC_PCRx register *******************/
9125#define FMC_PCRx_PWAITEN_Pos (1U)
9126#define FMC_PCRx_PWAITEN_Msk (0x1UL << FMC_PCRx_PWAITEN_Pos)
9127#define FMC_PCRx_PWAITEN FMC_PCRx_PWAITEN_Msk
9128#define FMC_PCRx_PBKEN_Pos (2U)
9129#define FMC_PCRx_PBKEN_Msk (0x1UL << FMC_PCRx_PBKEN_Pos)
9130#define FMC_PCRx_PBKEN FMC_PCRx_PBKEN_Msk
9131#define FMC_PCRx_PTYP_Pos (3U)
9132#define FMC_PCRx_PTYP_Msk (0x1UL << FMC_PCRx_PTYP_Pos)
9133#define FMC_PCRx_PTYP FMC_PCRx_PTYP_Msk
9135#define FMC_PCRx_PWID_Pos (4U)
9136#define FMC_PCRx_PWID_Msk (0x3UL << FMC_PCRx_PWID_Pos)
9137#define FMC_PCRx_PWID FMC_PCRx_PWID_Msk
9138#define FMC_PCRx_PWID_0 (0x1UL << FMC_PCRx_PWID_Pos)
9139#define FMC_PCRx_PWID_1 (0x2UL << FMC_PCRx_PWID_Pos)
9141#define FMC_PCRx_ECCEN_Pos (6U)
9142#define FMC_PCRx_ECCEN_Msk (0x1UL << FMC_PCRx_ECCEN_Pos)
9143#define FMC_PCRx_ECCEN FMC_PCRx_ECCEN_Msk
9145#define FMC_PCRx_TCLR_Pos (9U)
9146#define FMC_PCRx_TCLR_Msk (0xFUL << FMC_PCRx_TCLR_Pos)
9147#define FMC_PCRx_TCLR FMC_PCRx_TCLR_Msk
9148#define FMC_PCRx_TCLR_0 (0x1UL << FMC_PCRx_TCLR_Pos)
9149#define FMC_PCRx_TCLR_1 (0x2UL << FMC_PCRx_TCLR_Pos)
9150#define FMC_PCRx_TCLR_2 (0x4UL << FMC_PCRx_TCLR_Pos)
9151#define FMC_PCRx_TCLR_3 (0x8UL << FMC_PCRx_TCLR_Pos)
9153#define FMC_PCRx_TAR_Pos (13U)
9154#define FMC_PCRx_TAR_Msk (0xFUL << FMC_PCRx_TAR_Pos)
9155#define FMC_PCRx_TAR FMC_PCRx_TAR_Msk
9156#define FMC_PCRx_TAR_0 (0x1UL << FMC_PCRx_TAR_Pos)
9157#define FMC_PCRx_TAR_1 (0x2UL << FMC_PCRx_TAR_Pos)
9158#define FMC_PCRx_TAR_2 (0x4UL << FMC_PCRx_TAR_Pos)
9159#define FMC_PCRx_TAR_3 (0x8UL << FMC_PCRx_TAR_Pos)
9161#define FMC_PCRx_ECCPS_Pos (17U)
9162#define FMC_PCRx_ECCPS_Msk (0x7UL << FMC_PCRx_ECCPS_Pos)
9163#define FMC_PCRx_ECCPS FMC_PCRx_ECCPS_Msk
9164#define FMC_PCRx_ECCPS_0 (0x1UL << FMC_PCRx_ECCPS_Pos)
9165#define FMC_PCRx_ECCPS_1 (0x2UL << FMC_PCRx_ECCPS_Pos)
9166#define FMC_PCRx_ECCPS_2 (0x4UL << FMC_PCRx_ECCPS_Pos)
9168/****************** Bit definition for FMC_PCR2 register *******************/
9169#define FMC_PCR2_PWAITEN_Pos (1U)
9170#define FMC_PCR2_PWAITEN_Msk (0x1UL << FMC_PCR2_PWAITEN_Pos)
9171#define FMC_PCR2_PWAITEN FMC_PCR2_PWAITEN_Msk
9172#define FMC_PCR2_PBKEN_Pos (2U)
9173#define FMC_PCR2_PBKEN_Msk (0x1UL << FMC_PCR2_PBKEN_Pos)
9174#define FMC_PCR2_PBKEN FMC_PCR2_PBKEN_Msk
9175#define FMC_PCR2_PTYP_Pos (3U)
9176#define FMC_PCR2_PTYP_Msk (0x1UL << FMC_PCR2_PTYP_Pos)
9177#define FMC_PCR2_PTYP FMC_PCR2_PTYP_Msk
9179#define FMC_PCR2_PWID_Pos (4U)
9180#define FMC_PCR2_PWID_Msk (0x3UL << FMC_PCR2_PWID_Pos)
9181#define FMC_PCR2_PWID FMC_PCR2_PWID_Msk
9182#define FMC_PCR2_PWID_0 (0x1UL << FMC_PCR2_PWID_Pos)
9183#define FMC_PCR2_PWID_1 (0x2UL << FMC_PCR2_PWID_Pos)
9185#define FMC_PCR2_ECCEN_Pos (6U)
9186#define FMC_PCR2_ECCEN_Msk (0x1UL << FMC_PCR2_ECCEN_Pos)
9187#define FMC_PCR2_ECCEN FMC_PCR2_ECCEN_Msk
9189#define FMC_PCR2_TCLR_Pos (9U)
9190#define FMC_PCR2_TCLR_Msk (0xFUL << FMC_PCR2_TCLR_Pos)
9191#define FMC_PCR2_TCLR FMC_PCR2_TCLR_Msk
9192#define FMC_PCR2_TCLR_0 (0x1UL << FMC_PCR2_TCLR_Pos)
9193#define FMC_PCR2_TCLR_1 (0x2UL << FMC_PCR2_TCLR_Pos)
9194#define FMC_PCR2_TCLR_2 (0x4UL << FMC_PCR2_TCLR_Pos)
9195#define FMC_PCR2_TCLR_3 (0x8UL << FMC_PCR2_TCLR_Pos)
9197#define FMC_PCR2_TAR_Pos (13U)
9198#define FMC_PCR2_TAR_Msk (0xFUL << FMC_PCR2_TAR_Pos)
9199#define FMC_PCR2_TAR FMC_PCR2_TAR_Msk
9200#define FMC_PCR2_TAR_0 (0x1UL << FMC_PCR2_TAR_Pos)
9201#define FMC_PCR2_TAR_1 (0x2UL << FMC_PCR2_TAR_Pos)
9202#define FMC_PCR2_TAR_2 (0x4UL << FMC_PCR2_TAR_Pos)
9203#define FMC_PCR2_TAR_3 (0x8UL << FMC_PCR2_TAR_Pos)
9205#define FMC_PCR2_ECCPS_Pos (17U)
9206#define FMC_PCR2_ECCPS_Msk (0x7UL << FMC_PCR2_ECCPS_Pos)
9207#define FMC_PCR2_ECCPS FMC_PCR2_ECCPS_Msk
9208#define FMC_PCR2_ECCPS_0 (0x1UL << FMC_PCR2_ECCPS_Pos)
9209#define FMC_PCR2_ECCPS_1 (0x2UL << FMC_PCR2_ECCPS_Pos)
9210#define FMC_PCR2_ECCPS_2 (0x4UL << FMC_PCR2_ECCPS_Pos)
9212/****************** Bit definition for FMC_PCR3 register *******************/
9213#define FMC_PCR3_PWAITEN_Pos (1U)
9214#define FMC_PCR3_PWAITEN_Msk (0x1UL << FMC_PCR3_PWAITEN_Pos)
9215#define FMC_PCR3_PWAITEN FMC_PCR3_PWAITEN_Msk
9216#define FMC_PCR3_PBKEN_Pos (2U)
9217#define FMC_PCR3_PBKEN_Msk (0x1UL << FMC_PCR3_PBKEN_Pos)
9218#define FMC_PCR3_PBKEN FMC_PCR3_PBKEN_Msk
9219#define FMC_PCR3_PTYP_Pos (3U)
9220#define FMC_PCR3_PTYP_Msk (0x1UL << FMC_PCR3_PTYP_Pos)
9221#define FMC_PCR3_PTYP FMC_PCR3_PTYP_Msk
9223#define FMC_PCR3_PWID_Pos (4U)
9224#define FMC_PCR3_PWID_Msk (0x3UL << FMC_PCR3_PWID_Pos)
9225#define FMC_PCR3_PWID FMC_PCR3_PWID_Msk
9226#define FMC_PCR3_PWID_0 (0x1UL << FMC_PCR3_PWID_Pos)
9227#define FMC_PCR3_PWID_1 (0x2UL << FMC_PCR3_PWID_Pos)
9229#define FMC_PCR3_ECCEN_Pos (6U)
9230#define FMC_PCR3_ECCEN_Msk (0x1UL << FMC_PCR3_ECCEN_Pos)
9231#define FMC_PCR3_ECCEN FMC_PCR3_ECCEN_Msk
9233#define FMC_PCR3_TCLR_Pos (9U)
9234#define FMC_PCR3_TCLR_Msk (0xFUL << FMC_PCR3_TCLR_Pos)
9235#define FMC_PCR3_TCLR FMC_PCR3_TCLR_Msk
9236#define FMC_PCR3_TCLR_0 (0x1UL << FMC_PCR3_TCLR_Pos)
9237#define FMC_PCR3_TCLR_1 (0x2UL << FMC_PCR3_TCLR_Pos)
9238#define FMC_PCR3_TCLR_2 (0x4UL << FMC_PCR3_TCLR_Pos)
9239#define FMC_PCR3_TCLR_3 (0x8UL << FMC_PCR3_TCLR_Pos)
9241#define FMC_PCR3_TAR_Pos (13U)
9242#define FMC_PCR3_TAR_Msk (0xFUL << FMC_PCR3_TAR_Pos)
9243#define FMC_PCR3_TAR FMC_PCR3_TAR_Msk
9244#define FMC_PCR3_TAR_0 (0x1UL << FMC_PCR3_TAR_Pos)
9245#define FMC_PCR3_TAR_1 (0x2UL << FMC_PCR3_TAR_Pos)
9246#define FMC_PCR3_TAR_2 (0x4UL << FMC_PCR3_TAR_Pos)
9247#define FMC_PCR3_TAR_3 (0x8UL << FMC_PCR3_TAR_Pos)
9249#define FMC_PCR3_ECCPS_Pos (17U)
9250#define FMC_PCR3_ECCPS_Msk (0x7UL << FMC_PCR3_ECCPS_Pos)
9251#define FMC_PCR3_ECCPS FMC_PCR3_ECCPS_Msk
9252#define FMC_PCR3_ECCPS_0 (0x1UL << FMC_PCR3_ECCPS_Pos)
9253#define FMC_PCR3_ECCPS_1 (0x2UL << FMC_PCR3_ECCPS_Pos)
9254#define FMC_PCR3_ECCPS_2 (0x4UL << FMC_PCR3_ECCPS_Pos)
9256/****************** Bit definition for FMC_PCR4 register *******************/
9257#define FMC_PCR4_PWAITEN_Pos (1U)
9258#define FMC_PCR4_PWAITEN_Msk (0x1UL << FMC_PCR4_PWAITEN_Pos)
9259#define FMC_PCR4_PWAITEN FMC_PCR4_PWAITEN_Msk
9260#define FMC_PCR4_PBKEN_Pos (2U)
9261#define FMC_PCR4_PBKEN_Msk (0x1UL << FMC_PCR4_PBKEN_Pos)
9262#define FMC_PCR4_PBKEN FMC_PCR4_PBKEN_Msk
9263#define FMC_PCR4_PTYP_Pos (3U)
9264#define FMC_PCR4_PTYP_Msk (0x1UL << FMC_PCR4_PTYP_Pos)
9265#define FMC_PCR4_PTYP FMC_PCR4_PTYP_Msk
9267#define FMC_PCR4_PWID_Pos (4U)
9268#define FMC_PCR4_PWID_Msk (0x3UL << FMC_PCR4_PWID_Pos)
9269#define FMC_PCR4_PWID FMC_PCR4_PWID_Msk
9270#define FMC_PCR4_PWID_0 (0x1UL << FMC_PCR4_PWID_Pos)
9271#define FMC_PCR4_PWID_1 (0x2UL << FMC_PCR4_PWID_Pos)
9273#define FMC_PCR4_ECCEN_Pos (6U)
9274#define FMC_PCR4_ECCEN_Msk (0x1UL << FMC_PCR4_ECCEN_Pos)
9275#define FMC_PCR4_ECCEN FMC_PCR4_ECCEN_Msk
9277#define FMC_PCR4_TCLR_Pos (9U)
9278#define FMC_PCR4_TCLR_Msk (0xFUL << FMC_PCR4_TCLR_Pos)
9279#define FMC_PCR4_TCLR FMC_PCR4_TCLR_Msk
9280#define FMC_PCR4_TCLR_0 (0x1UL << FMC_PCR4_TCLR_Pos)
9281#define FMC_PCR4_TCLR_1 (0x2UL << FMC_PCR4_TCLR_Pos)
9282#define FMC_PCR4_TCLR_2 (0x4UL << FMC_PCR4_TCLR_Pos)
9283#define FMC_PCR4_TCLR_3 (0x8UL << FMC_PCR4_TCLR_Pos)
9285#define FMC_PCR4_TAR_Pos (13U)
9286#define FMC_PCR4_TAR_Msk (0xFUL << FMC_PCR4_TAR_Pos)
9287#define FMC_PCR4_TAR FMC_PCR4_TAR_Msk
9288#define FMC_PCR4_TAR_0 (0x1UL << FMC_PCR4_TAR_Pos)
9289#define FMC_PCR4_TAR_1 (0x2UL << FMC_PCR4_TAR_Pos)
9290#define FMC_PCR4_TAR_2 (0x4UL << FMC_PCR4_TAR_Pos)
9291#define FMC_PCR4_TAR_3 (0x8UL << FMC_PCR4_TAR_Pos)
9293#define FMC_PCR4_ECCPS_Pos (17U)
9294#define FMC_PCR4_ECCPS_Msk (0x7UL << FMC_PCR4_ECCPS_Pos)
9295#define FMC_PCR4_ECCPS FMC_PCR4_ECCPS_Msk
9296#define FMC_PCR4_ECCPS_0 (0x1UL << FMC_PCR4_ECCPS_Pos)
9297#define FMC_PCR4_ECCPS_1 (0x2UL << FMC_PCR4_ECCPS_Pos)
9298#define FMC_PCR4_ECCPS_2 (0x4UL << FMC_PCR4_ECCPS_Pos)
9300/******************* Bit definition for FMC_SRx register *******************/
9301#define FMC_SRx_IRS_Pos (0U)
9302#define FMC_SRx_IRS_Msk (0x1UL << FMC_SRx_IRS_Pos)
9303#define FMC_SRx_IRS FMC_SRx_IRS_Msk
9304#define FMC_SRx_ILS_Pos (1U)
9305#define FMC_SRx_ILS_Msk (0x1UL << FMC_SRx_ILS_Pos)
9306#define FMC_SRx_ILS FMC_SRx_ILS_Msk
9307#define FMC_SRx_IFS_Pos (2U)
9308#define FMC_SRx_IFS_Msk (0x1UL << FMC_SRx_IFS_Pos)
9309#define FMC_SRx_IFS FMC_SRx_IFS_Msk
9310#define FMC_SRx_IREN_Pos (3U)
9311#define FMC_SRx_IREN_Msk (0x1UL << FMC_SRx_IREN_Pos)
9312#define FMC_SRx_IREN FMC_SRx_IREN_Msk
9313#define FMC_SRx_ILEN_Pos (4U)
9314#define FMC_SRx_ILEN_Msk (0x1UL << FMC_SRx_ILEN_Pos)
9315#define FMC_SRx_ILEN FMC_SRx_ILEN_Msk
9316#define FMC_SRx_IFEN_Pos (5U)
9317#define FMC_SRx_IFEN_Msk (0x1UL << FMC_SRx_IFEN_Pos)
9318#define FMC_SRx_IFEN FMC_SRx_IFEN_Msk
9319#define FMC_SRx_FEMPT_Pos (6U)
9320#define FMC_SRx_FEMPT_Msk (0x1UL << FMC_SRx_FEMPT_Pos)
9321#define FMC_SRx_FEMPT FMC_SRx_FEMPT_Msk
9323/******************* Bit definition for FMC_SR2 register *******************/
9324#define FMC_SR2_IRS_Pos (0U)
9325#define FMC_SR2_IRS_Msk (0x1UL << FMC_SR2_IRS_Pos)
9326#define FMC_SR2_IRS FMC_SR2_IRS_Msk
9327#define FMC_SR2_ILS_Pos (1U)
9328#define FMC_SR2_ILS_Msk (0x1UL << FMC_SR2_ILS_Pos)
9329#define FMC_SR2_ILS FMC_SR2_ILS_Msk
9330#define FMC_SR2_IFS_Pos (2U)
9331#define FMC_SR2_IFS_Msk (0x1UL << FMC_SR2_IFS_Pos)
9332#define FMC_SR2_IFS FMC_SR2_IFS_Msk
9333#define FMC_SR2_IREN_Pos (3U)
9334#define FMC_SR2_IREN_Msk (0x1UL << FMC_SR2_IREN_Pos)
9335#define FMC_SR2_IREN FMC_SR2_IREN_Msk
9336#define FMC_SR2_ILEN_Pos (4U)
9337#define FMC_SR2_ILEN_Msk (0x1UL << FMC_SR2_ILEN_Pos)
9338#define FMC_SR2_ILEN FMC_SR2_ILEN_Msk
9339#define FMC_SR2_IFEN_Pos (5U)
9340#define FMC_SR2_IFEN_Msk (0x1UL << FMC_SR2_IFEN_Pos)
9341#define FMC_SR2_IFEN FMC_SR2_IFEN_Msk
9342#define FMC_SR2_FEMPT_Pos (6U)
9343#define FMC_SR2_FEMPT_Msk (0x1UL << FMC_SR2_FEMPT_Pos)
9344#define FMC_SR2_FEMPT FMC_SR2_FEMPT_Msk
9346/******************* Bit definition for FMC_SR3 register *******************/
9347#define FMC_SR3_IRS_Pos (0U)
9348#define FMC_SR3_IRS_Msk (0x1UL << FMC_SR3_IRS_Pos)
9349#define FMC_SR3_IRS FMC_SR3_IRS_Msk
9350#define FMC_SR3_ILS_Pos (1U)
9351#define FMC_SR3_ILS_Msk (0x1UL << FMC_SR3_ILS_Pos)
9352#define FMC_SR3_ILS FMC_SR3_ILS_Msk
9353#define FMC_SR3_IFS_Pos (2U)
9354#define FMC_SR3_IFS_Msk (0x1UL << FMC_SR3_IFS_Pos)
9355#define FMC_SR3_IFS FMC_SR3_IFS_Msk
9356#define FMC_SR3_IREN_Pos (3U)
9357#define FMC_SR3_IREN_Msk (0x1UL << FMC_SR3_IREN_Pos)
9358#define FMC_SR3_IREN FMC_SR3_IREN_Msk
9359#define FMC_SR3_ILEN_Pos (4U)
9360#define FMC_SR3_ILEN_Msk (0x1UL << FMC_SR3_ILEN_Pos)
9361#define FMC_SR3_ILEN FMC_SR3_ILEN_Msk
9362#define FMC_SR3_IFEN_Pos (5U)
9363#define FMC_SR3_IFEN_Msk (0x1UL << FMC_SR3_IFEN_Pos)
9364#define FMC_SR3_IFEN FMC_SR3_IFEN_Msk
9365#define FMC_SR3_FEMPT_Pos (6U)
9366#define FMC_SR3_FEMPT_Msk (0x1UL << FMC_SR3_FEMPT_Pos)
9367#define FMC_SR3_FEMPT FMC_SR3_FEMPT_Msk
9369/******************* Bit definition for FMC_SR4 register *******************/
9370#define FMC_SR4_IRS_Pos (0U)
9371#define FMC_SR4_IRS_Msk (0x1UL << FMC_SR4_IRS_Pos)
9372#define FMC_SR4_IRS FMC_SR4_IRS_Msk
9373#define FMC_SR4_ILS_Pos (1U)
9374#define FMC_SR4_ILS_Msk (0x1UL << FMC_SR4_ILS_Pos)
9375#define FMC_SR4_ILS FMC_SR4_ILS_Msk
9376#define FMC_SR4_IFS_Pos (2U)
9377#define FMC_SR4_IFS_Msk (0x1UL << FMC_SR4_IFS_Pos)
9378#define FMC_SR4_IFS FMC_SR4_IFS_Msk
9379#define FMC_SR4_IREN_Pos (3U)
9380#define FMC_SR4_IREN_Msk (0x1UL << FMC_SR4_IREN_Pos)
9381#define FMC_SR4_IREN FMC_SR4_IREN_Msk
9382#define FMC_SR4_ILEN_Pos (4U)
9383#define FMC_SR4_ILEN_Msk (0x1UL << FMC_SR4_ILEN_Pos)
9384#define FMC_SR4_ILEN FMC_SR4_ILEN_Msk
9385#define FMC_SR4_IFEN_Pos (5U)
9386#define FMC_SR4_IFEN_Msk (0x1UL << FMC_SR4_IFEN_Pos)
9387#define FMC_SR4_IFEN FMC_SR4_IFEN_Msk
9388#define FMC_SR4_FEMPT_Pos (6U)
9389#define FMC_SR4_FEMPT_Msk (0x1UL << FMC_SR4_FEMPT_Pos)
9390#define FMC_SR4_FEMPT FMC_SR4_FEMPT_Msk
9392/****************** Bit definition for FMC_PMEMx register ******************/
9393#define FMC_PMEMx_MEMSETx_Pos (0U)
9394#define FMC_PMEMx_MEMSETx_Msk (0xFFUL << FMC_PMEMx_MEMSETx_Pos)
9395#define FMC_PMEMx_MEMSETx FMC_PMEMx_MEMSETx_Msk
9396#define FMC_PMEMx_MEMSETx_0 (0x01UL << FMC_PMEMx_MEMSETx_Pos)
9397#define FMC_PMEMx_MEMSETx_1 (0x02UL << FMC_PMEMx_MEMSETx_Pos)
9398#define FMC_PMEMx_MEMSETx_2 (0x04UL << FMC_PMEMx_MEMSETx_Pos)
9399#define FMC_PMEMx_MEMSETx_3 (0x08UL << FMC_PMEMx_MEMSETx_Pos)
9400#define FMC_PMEMx_MEMSETx_4 (0x10UL << FMC_PMEMx_MEMSETx_Pos)
9401#define FMC_PMEMx_MEMSETx_5 (0x20UL << FMC_PMEMx_MEMSETx_Pos)
9402#define FMC_PMEMx_MEMSETx_6 (0x40UL << FMC_PMEMx_MEMSETx_Pos)
9403#define FMC_PMEMx_MEMSETx_7 (0x80UL << FMC_PMEMx_MEMSETx_Pos)
9405#define FMC_PMEMx_MEMWAITx_Pos (8U)
9406#define FMC_PMEMx_MEMWAITx_Msk (0xFFUL << FMC_PMEMx_MEMWAITx_Pos)
9407#define FMC_PMEMx_MEMWAITx FMC_PMEMx_MEMWAITx_Msk
9408#define FMC_PMEMx_MEMWAITx_0 (0x01UL << FMC_PMEMx_MEMWAITx_Pos)
9409#define FMC_PMEMx_MEMWAITx_1 (0x02UL << FMC_PMEMx_MEMWAITx_Pos)
9410#define FMC_PMEMx_MEMWAITx_2 (0x04UL << FMC_PMEMx_MEMWAITx_Pos)
9411#define FMC_PMEMx_MEMWAITx_3 (0x08UL << FMC_PMEMx_MEMWAITx_Pos)
9412#define FMC_PMEMx_MEMWAITx_4 (0x10UL << FMC_PMEMx_MEMWAITx_Pos)
9413#define FMC_PMEMx_MEMWAITx_5 (0x20UL << FMC_PMEMx_MEMWAITx_Pos)
9414#define FMC_PMEMx_MEMWAITx_6 (0x40UL << FMC_PMEMx_MEMWAITx_Pos)
9415#define FMC_PMEMx_MEMWAITx_7 (0x80UL << FMC_PMEMx_MEMWAITx_Pos)
9417#define FMC_PMEMx_MEMHOLDx_Pos (16U)
9418#define FMC_PMEMx_MEMHOLDx_Msk (0xFFUL << FMC_PMEMx_MEMHOLDx_Pos)
9419#define FMC_PMEMx_MEMHOLDx FMC_PMEMx_MEMHOLDx_Msk
9420#define FMC_PMEMx_MEMHOLDx_0 (0x01UL << FMC_PMEMx_MEMHOLDx_Pos)
9421#define FMC_PMEMx_MEMHOLDx_1 (0x02UL << FMC_PMEMx_MEMHOLDx_Pos)
9422#define FMC_PMEMx_MEMHOLDx_2 (0x04UL << FMC_PMEMx_MEMHOLDx_Pos)
9423#define FMC_PMEMx_MEMHOLDx_3 (0x08UL << FMC_PMEMx_MEMHOLDx_Pos)
9424#define FMC_PMEMx_MEMHOLDx_4 (0x10UL << FMC_PMEMx_MEMHOLDx_Pos)
9425#define FMC_PMEMx_MEMHOLDx_5 (0x20UL << FMC_PMEMx_MEMHOLDx_Pos)
9426#define FMC_PMEMx_MEMHOLDx_6 (0x40UL << FMC_PMEMx_MEMHOLDx_Pos)
9427#define FMC_PMEMx_MEMHOLDx_7 (0x80UL << FMC_PMEMx_MEMHOLDx_Pos)
9429#define FMC_PMEMx_MEMHIZx_Pos (24U)
9430#define FMC_PMEMx_MEMHIZx_Msk (0xFFUL << FMC_PMEMx_MEMHIZx_Pos)
9431#define FMC_PMEMx_MEMHIZx FMC_PMEMx_MEMHIZx_Msk
9432#define FMC_PMEMx_MEMHIZx_0 (0x01UL << FMC_PMEMx_MEMHIZx_Pos)
9433#define FMC_PMEMx_MEMHIZx_1 (0x02UL << FMC_PMEMx_MEMHIZx_Pos)
9434#define FMC_PMEMx_MEMHIZx_2 (0x04UL << FMC_PMEMx_MEMHIZx_Pos)
9435#define FMC_PMEMx_MEMHIZx_3 (0x08UL << FMC_PMEMx_MEMHIZx_Pos)
9436#define FMC_PMEMx_MEMHIZx_4 (0x10UL << FMC_PMEMx_MEMHIZx_Pos)
9437#define FMC_PMEMx_MEMHIZx_5 (0x20UL << FMC_PMEMx_MEMHIZx_Pos)
9438#define FMC_PMEMx_MEMHIZx_6 (0x40UL << FMC_PMEMx_MEMHIZx_Pos)
9439#define FMC_PMEMx_MEMHIZx_7 (0x80UL << FMC_PMEMx_MEMHIZx_Pos)
9441/****************** Bit definition for FMC_PMEM2 register ******************/
9442#define FMC_PMEM2_MEMSET2_Pos (0U)
9443#define FMC_PMEM2_MEMSET2_Msk (0xFFUL << FMC_PMEM2_MEMSET2_Pos)
9444#define FMC_PMEM2_MEMSET2 FMC_PMEM2_MEMSET2_Msk
9445#define FMC_PMEM2_MEMSET2_0 (0x01UL << FMC_PMEM2_MEMSET2_Pos)
9446#define FMC_PMEM2_MEMSET2_1 (0x02UL << FMC_PMEM2_MEMSET2_Pos)
9447#define FMC_PMEM2_MEMSET2_2 (0x04UL << FMC_PMEM2_MEMSET2_Pos)
9448#define FMC_PMEM2_MEMSET2_3 (0x08UL << FMC_PMEM2_MEMSET2_Pos)
9449#define FMC_PMEM2_MEMSET2_4 (0x10UL << FMC_PMEM2_MEMSET2_Pos)
9450#define FMC_PMEM2_MEMSET2_5 (0x20UL << FMC_PMEM2_MEMSET2_Pos)
9451#define FMC_PMEM2_MEMSET2_6 (0x40UL << FMC_PMEM2_MEMSET2_Pos)
9452#define FMC_PMEM2_MEMSET2_7 (0x80UL << FMC_PMEM2_MEMSET2_Pos)
9454#define FMC_PMEM2_MEMWAIT2_Pos (8U)
9455#define FMC_PMEM2_MEMWAIT2_Msk (0xFFUL << FMC_PMEM2_MEMWAIT2_Pos)
9456#define FMC_PMEM2_MEMWAIT2 FMC_PMEM2_MEMWAIT2_Msk
9457#define FMC_PMEM2_MEMWAIT2_0 (0x01UL << FMC_PMEM2_MEMWAIT2_Pos)
9458#define FMC_PMEM2_MEMWAIT2_1 (0x02UL << FMC_PMEM2_MEMWAIT2_Pos)
9459#define FMC_PMEM2_MEMWAIT2_2 (0x04UL << FMC_PMEM2_MEMWAIT2_Pos)
9460#define FMC_PMEM2_MEMWAIT2_3 (0x08UL << FMC_PMEM2_MEMWAIT2_Pos)
9461#define FMC_PMEM2_MEMWAIT2_4 (0x10UL << FMC_PMEM2_MEMWAIT2_Pos)
9462#define FMC_PMEM2_MEMWAIT2_5 (0x20UL << FMC_PMEM2_MEMWAIT2_Pos)
9463#define FMC_PMEM2_MEMWAIT2_6 (0x40UL << FMC_PMEM2_MEMWAIT2_Pos)
9464#define FMC_PMEM2_MEMWAIT2_7 (0x80UL << FMC_PMEM2_MEMWAIT2_Pos)
9466#define FMC_PMEM2_MEMHOLD2_Pos (16U)
9467#define FMC_PMEM2_MEMHOLD2_Msk (0xFFUL << FMC_PMEM2_MEMHOLD2_Pos)
9468#define FMC_PMEM2_MEMHOLD2 FMC_PMEM2_MEMHOLD2_Msk
9469#define FMC_PMEM2_MEMHOLD2_0 (0x01UL << FMC_PMEM2_MEMHOLD2_Pos)
9470#define FMC_PMEM2_MEMHOLD2_1 (0x02UL << FMC_PMEM2_MEMHOLD2_Pos)
9471#define FMC_PMEM2_MEMHOLD2_2 (0x04UL << FMC_PMEM2_MEMHOLD2_Pos)
9472#define FMC_PMEM2_MEMHOLD2_3 (0x08UL << FMC_PMEM2_MEMHOLD2_Pos)
9473#define FMC_PMEM2_MEMHOLD2_4 (0x10UL << FMC_PMEM2_MEMHOLD2_Pos)
9474#define FMC_PMEM2_MEMHOLD2_5 (0x20UL << FMC_PMEM2_MEMHOLD2_Pos)
9475#define FMC_PMEM2_MEMHOLD2_6 (0x40UL << FMC_PMEM2_MEMHOLD2_Pos)
9476#define FMC_PMEM2_MEMHOLD2_7 (0x80UL << FMC_PMEM2_MEMHOLD2_Pos)
9478#define FMC_PMEM2_MEMHIZ2_Pos (24U)
9479#define FMC_PMEM2_MEMHIZ2_Msk (0xFFUL << FMC_PMEM2_MEMHIZ2_Pos)
9480#define FMC_PMEM2_MEMHIZ2 FMC_PMEM2_MEMHIZ2_Msk
9481#define FMC_PMEM2_MEMHIZ2_0 (0x01UL << FMC_PMEM2_MEMHIZ2_Pos)
9482#define FMC_PMEM2_MEMHIZ2_1 (0x02UL << FMC_PMEM2_MEMHIZ2_Pos)
9483#define FMC_PMEM2_MEMHIZ2_2 (0x04UL << FMC_PMEM2_MEMHIZ2_Pos)
9484#define FMC_PMEM2_MEMHIZ2_3 (0x08UL << FMC_PMEM2_MEMHIZ2_Pos)
9485#define FMC_PMEM2_MEMHIZ2_4 (0x10UL << FMC_PMEM2_MEMHIZ2_Pos)
9486#define FMC_PMEM2_MEMHIZ2_5 (0x20UL << FMC_PMEM2_MEMHIZ2_Pos)
9487#define FMC_PMEM2_MEMHIZ2_6 (0x40UL << FMC_PMEM2_MEMHIZ2_Pos)
9488#define FMC_PMEM2_MEMHIZ2_7 (0x80UL << FMC_PMEM2_MEMHIZ2_Pos)
9490/****************** Bit definition for FMC_PMEM3 register ******************/
9491#define FMC_PMEM3_MEMSET3_Pos (0U)
9492#define FMC_PMEM3_MEMSET3_Msk (0xFFUL << FMC_PMEM3_MEMSET3_Pos)
9493#define FMC_PMEM3_MEMSET3 FMC_PMEM3_MEMSET3_Msk
9494#define FMC_PMEM3_MEMSET3_0 (0x01UL << FMC_PMEM3_MEMSET3_Pos)
9495#define FMC_PMEM3_MEMSET3_1 (0x02UL << FMC_PMEM3_MEMSET3_Pos)
9496#define FMC_PMEM3_MEMSET3_2 (0x04UL << FMC_PMEM3_MEMSET3_Pos)
9497#define FMC_PMEM3_MEMSET3_3 (0x08UL << FMC_PMEM3_MEMSET3_Pos)
9498#define FMC_PMEM3_MEMSET3_4 (0x10UL << FMC_PMEM3_MEMSET3_Pos)
9499#define FMC_PMEM3_MEMSET3_5 (0x20UL << FMC_PMEM3_MEMSET3_Pos)
9500#define FMC_PMEM3_MEMSET3_6 (0x40UL << FMC_PMEM3_MEMSET3_Pos)
9501#define FMC_PMEM3_MEMSET3_7 (0x80UL << FMC_PMEM3_MEMSET3_Pos)
9503#define FMC_PMEM3_MEMWAIT3_Pos (8U)
9504#define FMC_PMEM3_MEMWAIT3_Msk (0xFFUL << FMC_PMEM3_MEMWAIT3_Pos)
9505#define FMC_PMEM3_MEMWAIT3 FMC_PMEM3_MEMWAIT3_Msk
9506#define FMC_PMEM3_MEMWAIT3_0 (0x01UL << FMC_PMEM3_MEMWAIT3_Pos)
9507#define FMC_PMEM3_MEMWAIT3_1 (0x02UL << FMC_PMEM3_MEMWAIT3_Pos)
9508#define FMC_PMEM3_MEMWAIT3_2 (0x04UL << FMC_PMEM3_MEMWAIT3_Pos)
9509#define FMC_PMEM3_MEMWAIT3_3 (0x08UL << FMC_PMEM3_MEMWAIT3_Pos)
9510#define FMC_PMEM3_MEMWAIT3_4 (0x10UL << FMC_PMEM3_MEMWAIT3_Pos)
9511#define FMC_PMEM3_MEMWAIT3_5 (0x20UL << FMC_PMEM3_MEMWAIT3_Pos)
9512#define FMC_PMEM3_MEMWAIT3_6 (0x40UL << FMC_PMEM3_MEMWAIT3_Pos)
9513#define FMC_PMEM3_MEMWAIT3_7 (0x80UL << FMC_PMEM3_MEMWAIT3_Pos)
9515#define FMC_PMEM3_MEMHOLD3_Pos (16U)
9516#define FMC_PMEM3_MEMHOLD3_Msk (0xFFUL << FMC_PMEM3_MEMHOLD3_Pos)
9517#define FMC_PMEM3_MEMHOLD3 FMC_PMEM3_MEMHOLD3_Msk
9518#define FMC_PMEM3_MEMHOLD3_0 (0x01UL << FMC_PMEM3_MEMHOLD3_Pos)
9519#define FMC_PMEM3_MEMHOLD3_1 (0x02UL << FMC_PMEM3_MEMHOLD3_Pos)
9520#define FMC_PMEM3_MEMHOLD3_2 (0x04UL << FMC_PMEM3_MEMHOLD3_Pos)
9521#define FMC_PMEM3_MEMHOLD3_3 (0x08UL << FMC_PMEM3_MEMHOLD3_Pos)
9522#define FMC_PMEM3_MEMHOLD3_4 (0x10UL << FMC_PMEM3_MEMHOLD3_Pos)
9523#define FMC_PMEM3_MEMHOLD3_5 (0x20UL << FMC_PMEM3_MEMHOLD3_Pos)
9524#define FMC_PMEM3_MEMHOLD3_6 (0x40UL << FMC_PMEM3_MEMHOLD3_Pos)
9525#define FMC_PMEM3_MEMHOLD3_7 (0x80UL << FMC_PMEM3_MEMHOLD3_Pos)
9527#define FMC_PMEM3_MEMHIZ3_Pos (24U)
9528#define FMC_PMEM3_MEMHIZ3_Msk (0xFFUL << FMC_PMEM3_MEMHIZ3_Pos)
9529#define FMC_PMEM3_MEMHIZ3 FMC_PMEM3_MEMHIZ3_Msk
9530#define FMC_PMEM3_MEMHIZ3_0 (0x01UL << FMC_PMEM3_MEMHIZ3_Pos)
9531#define FMC_PMEM3_MEMHIZ3_1 (0x02UL << FMC_PMEM3_MEMHIZ3_Pos)
9532#define FMC_PMEM3_MEMHIZ3_2 (0x04UL << FMC_PMEM3_MEMHIZ3_Pos)
9533#define FMC_PMEM3_MEMHIZ3_3 (0x08UL << FMC_PMEM3_MEMHIZ3_Pos)
9534#define FMC_PMEM3_MEMHIZ3_4 (0x10UL << FMC_PMEM3_MEMHIZ3_Pos)
9535#define FMC_PMEM3_MEMHIZ3_5 (0x20UL << FMC_PMEM3_MEMHIZ3_Pos)
9536#define FMC_PMEM3_MEMHIZ3_6 (0x40UL << FMC_PMEM3_MEMHIZ3_Pos)
9537#define FMC_PMEM3_MEMHIZ3_7 (0x80UL << FMC_PMEM3_MEMHIZ3_Pos)
9539/****************** Bit definition for FMC_PMEM4 register ******************/
9540#define FMC_PMEM4_MEMSET4_Pos (0U)
9541#define FMC_PMEM4_MEMSET4_Msk (0xFFUL << FMC_PMEM4_MEMSET4_Pos)
9542#define FMC_PMEM4_MEMSET4 FMC_PMEM4_MEMSET4_Msk
9543#define FMC_PMEM4_MEMSET4_0 (0x01UL << FMC_PMEM4_MEMSET4_Pos)
9544#define FMC_PMEM4_MEMSET4_1 (0x02UL << FMC_PMEM4_MEMSET4_Pos)
9545#define FMC_PMEM4_MEMSET4_2 (0x04UL << FMC_PMEM4_MEMSET4_Pos)
9546#define FMC_PMEM4_MEMSET4_3 (0x08UL << FMC_PMEM4_MEMSET4_Pos)
9547#define FMC_PMEM4_MEMSET4_4 (0x10UL << FMC_PMEM4_MEMSET4_Pos)
9548#define FMC_PMEM4_MEMSET4_5 (0x20UL << FMC_PMEM4_MEMSET4_Pos)
9549#define FMC_PMEM4_MEMSET4_6 (0x40UL << FMC_PMEM4_MEMSET4_Pos)
9550#define FMC_PMEM4_MEMSET4_7 (0x80UL << FMC_PMEM4_MEMSET4_Pos)
9552#define FMC_PMEM4_MEMWAIT4_Pos (8U)
9553#define FMC_PMEM4_MEMWAIT4_Msk (0xFFUL << FMC_PMEM4_MEMWAIT4_Pos)
9554#define FMC_PMEM4_MEMWAIT4 FMC_PMEM4_MEMWAIT4_Msk
9555#define FMC_PMEM4_MEMWAIT4_0 (0x01UL << FMC_PMEM4_MEMWAIT4_Pos)
9556#define FMC_PMEM4_MEMWAIT4_1 (0x02UL << FMC_PMEM4_MEMWAIT4_Pos)
9557#define FMC_PMEM4_MEMWAIT4_2 (0x04UL << FMC_PMEM4_MEMWAIT4_Pos)
9558#define FMC_PMEM4_MEMWAIT4_3 (0x08UL << FMC_PMEM4_MEMWAIT4_Pos)
9559#define FMC_PMEM4_MEMWAIT4_4 (0x10UL << FMC_PMEM4_MEMWAIT4_Pos)
9560#define FMC_PMEM4_MEMWAIT4_5 (0x20UL << FMC_PMEM4_MEMWAIT4_Pos)
9561#define FMC_PMEM4_MEMWAIT4_6 (0x40UL << FMC_PMEM4_MEMWAIT4_Pos)
9562#define FMC_PMEM4_MEMWAIT4_7 (0x80UL << FMC_PMEM4_MEMWAIT4_Pos)
9564#define FMC_PMEM4_MEMHOLD4_Pos (16U)
9565#define FMC_PMEM4_MEMHOLD4_Msk (0xFFUL << FMC_PMEM4_MEMHOLD4_Pos)
9566#define FMC_PMEM4_MEMHOLD4 FMC_PMEM4_MEMHOLD4_Msk
9567#define FMC_PMEM4_MEMHOLD4_0 (0x01UL << FMC_PMEM4_MEMHOLD4_Pos)
9568#define FMC_PMEM4_MEMHOLD4_1 (0x02UL << FMC_PMEM4_MEMHOLD4_Pos)
9569#define FMC_PMEM4_MEMHOLD4_2 (0x04UL << FMC_PMEM4_MEMHOLD4_Pos)
9570#define FMC_PMEM4_MEMHOLD4_3 (0x08UL << FMC_PMEM4_MEMHOLD4_Pos)
9571#define FMC_PMEM4_MEMHOLD4_4 (0x10UL << FMC_PMEM4_MEMHOLD4_Pos)
9572#define FMC_PMEM4_MEMHOLD4_5 (0x20UL << FMC_PMEM4_MEMHOLD4_Pos)
9573#define FMC_PMEM4_MEMHOLD4_6 (0x40UL << FMC_PMEM4_MEMHOLD4_Pos)
9574#define FMC_PMEM4_MEMHOLD4_7 (0x80UL << FMC_PMEM4_MEMHOLD4_Pos)
9576#define FMC_PMEM4_MEMHIZ4_Pos (24U)
9577#define FMC_PMEM4_MEMHIZ4_Msk (0xFFUL << FMC_PMEM4_MEMHIZ4_Pos)
9578#define FMC_PMEM4_MEMHIZ4 FMC_PMEM4_MEMHIZ4_Msk
9579#define FMC_PMEM4_MEMHIZ4_0 (0x01UL << FMC_PMEM4_MEMHIZ4_Pos)
9580#define FMC_PMEM4_MEMHIZ4_1 (0x02UL << FMC_PMEM4_MEMHIZ4_Pos)
9581#define FMC_PMEM4_MEMHIZ4_2 (0x04UL << FMC_PMEM4_MEMHIZ4_Pos)
9582#define FMC_PMEM4_MEMHIZ4_3 (0x08UL << FMC_PMEM4_MEMHIZ4_Pos)
9583#define FMC_PMEM4_MEMHIZ4_4 (0x10UL << FMC_PMEM4_MEMHIZ4_Pos)
9584#define FMC_PMEM4_MEMHIZ4_5 (0x20UL << FMC_PMEM4_MEMHIZ4_Pos)
9585#define FMC_PMEM4_MEMHIZ4_6 (0x40UL << FMC_PMEM4_MEMHIZ4_Pos)
9586#define FMC_PMEM4_MEMHIZ4_7 (0x80UL << FMC_PMEM4_MEMHIZ4_Pos)
9588/****************** Bit definition for FMC_PATTx register ******************/
9589#define FMC_PATTx_ATTSETx_Pos (0U)
9590#define FMC_PATTx_ATTSETx_Msk (0xFFUL << FMC_PATTx_ATTSETx_Pos)
9591#define FMC_PATTx_ATTSETx FMC_PATTx_ATTSETx_Msk
9592#define FMC_PATTx_ATTSETx_0 (0x01UL << FMC_PATTx_ATTSETx_Pos)
9593#define FMC_PATTx_ATTSETx_1 (0x02UL << FMC_PATTx_ATTSETx_Pos)
9594#define FMC_PATTx_ATTSETx_2 (0x04UL << FMC_PATTx_ATTSETx_Pos)
9595#define FMC_PATTx_ATTSETx_3 (0x08UL << FMC_PATTx_ATTSETx_Pos)
9596#define FMC_PATTx_ATTSETx_4 (0x10UL << FMC_PATTx_ATTSETx_Pos)
9597#define FMC_PATTx_ATTSETx_5 (0x20UL << FMC_PATTx_ATTSETx_Pos)
9598#define FMC_PATTx_ATTSETx_6 (0x40UL << FMC_PATTx_ATTSETx_Pos)
9599#define FMC_PATTx_ATTSETx_7 (0x80UL << FMC_PATTx_ATTSETx_Pos)
9601#define FMC_PATTx_ATTWAITx_Pos (8U)
9602#define FMC_PATTx_ATTWAITx_Msk (0xFFUL << FMC_PATTx_ATTWAITx_Pos)
9603#define FMC_PATTx_ATTWAITx FMC_PATTx_ATTWAITx_Msk
9604#define FMC_PATTx_ATTWAITx_0 (0x01UL << FMC_PATTx_ATTWAITx_Pos)
9605#define FMC_PATTx_ATTWAITx_1 (0x02UL << FMC_PATTx_ATTWAITx_Pos)
9606#define FMC_PATTx_ATTWAITx_2 (0x04UL << FMC_PATTx_ATTWAITx_Pos)
9607#define FMC_PATTx_ATTWAITx_3 (0x08UL << FMC_PATTx_ATTWAITx_Pos)
9608#define FMC_PATTx_ATTWAITx_4 (0x10UL << FMC_PATTx_ATTWAITx_Pos)
9609#define FMC_PATTx_ATTWAITx_5 (0x20UL << FMC_PATTx_ATTWAITx_Pos)
9610#define FMC_PATTx_ATTWAITx_6 (0x40UL << FMC_PATTx_ATTWAITx_Pos)
9611#define FMC_PATTx_ATTWAITx_7 (0x80UL << FMC_PATTx_ATTWAITx_Pos)
9613#define FMC_PATTx_ATTHOLDx_Pos (16U)
9614#define FMC_PATTx_ATTHOLDx_Msk (0xFFUL << FMC_PATTx_ATTHOLDx_Pos)
9615#define FMC_PATTx_ATTHOLDx FMC_PATTx_ATTHOLDx_Msk
9616#define FMC_PATTx_ATTHOLDx_0 (0x01UL << FMC_PATTx_ATTHOLDx_Pos)
9617#define FMC_PATTx_ATTHOLDx_1 (0x02UL << FMC_PATTx_ATTHOLDx_Pos)
9618#define FMC_PATTx_ATTHOLDx_2 (0x04UL << FMC_PATTx_ATTHOLDx_Pos)
9619#define FMC_PATTx_ATTHOLDx_3 (0x08UL << FMC_PATTx_ATTHOLDx_Pos)
9620#define FMC_PATTx_ATTHOLDx_4 (0x10UL << FMC_PATTx_ATTHOLDx_Pos)
9621#define FMC_PATTx_ATTHOLDx_5 (0x20UL << FMC_PATTx_ATTHOLDx_Pos)
9622#define FMC_PATTx_ATTHOLDx_6 (0x40UL << FMC_PATTx_ATTHOLDx_Pos)
9623#define FMC_PATTx_ATTHOLDx_7 (0x80UL << FMC_PATTx_ATTHOLDx_Pos)
9625#define FMC_PATTx_ATTHIZx_Pos (24U)
9626#define FMC_PATTx_ATTHIZx_Msk (0xFFUL << FMC_PATTx_ATTHIZx_Pos)
9627#define FMC_PATTx_ATTHIZx FMC_PATTx_ATTHIZx_Msk
9628#define FMC_PATTx_ATTHIZx_0 (0x01UL << FMC_PATTx_ATTHIZx_Pos)
9629#define FMC_PATTx_ATTHIZx_1 (0x02UL << FMC_PATTx_ATTHIZx_Pos)
9630#define FMC_PATTx_ATTHIZx_2 (0x04UL << FMC_PATTx_ATTHIZx_Pos)
9631#define FMC_PATTx_ATTHIZx_3 (0x08UL << FMC_PATTx_ATTHIZx_Pos)
9632#define FMC_PATTx_ATTHIZx_4 (0x10UL << FMC_PATTx_ATTHIZx_Pos)
9633#define FMC_PATTx_ATTHIZx_5 (0x20UL << FMC_PATTx_ATTHIZx_Pos)
9634#define FMC_PATTx_ATTHIZx_6 (0x40UL << FMC_PATTx_ATTHIZx_Pos)
9635#define FMC_PATTx_ATTHIZx_7 (0x80UL << FMC_PATTx_ATTHIZx_Pos)
9637/****************** Bit definition for FMC_PATT2 register ******************/
9638#define FMC_PATT2_ATTSET2_Pos (0U)
9639#define FMC_PATT2_ATTSET2_Msk (0xFFUL << FMC_PATT2_ATTSET2_Pos)
9640#define FMC_PATT2_ATTSET2 FMC_PATT2_ATTSET2_Msk
9641#define FMC_PATT2_ATTSET2_0 (0x01UL << FMC_PATT2_ATTSET2_Pos)
9642#define FMC_PATT2_ATTSET2_1 (0x02UL << FMC_PATT2_ATTSET2_Pos)
9643#define FMC_PATT2_ATTSET2_2 (0x04UL << FMC_PATT2_ATTSET2_Pos)
9644#define FMC_PATT2_ATTSET2_3 (0x08UL << FMC_PATT2_ATTSET2_Pos)
9645#define FMC_PATT2_ATTSET2_4 (0x10UL << FMC_PATT2_ATTSET2_Pos)
9646#define FMC_PATT2_ATTSET2_5 (0x20UL << FMC_PATT2_ATTSET2_Pos)
9647#define FMC_PATT2_ATTSET2_6 (0x40UL << FMC_PATT2_ATTSET2_Pos)
9648#define FMC_PATT2_ATTSET2_7 (0x80UL << FMC_PATT2_ATTSET2_Pos)
9650#define FMC_PATT2_ATTWAIT2_Pos (8U)
9651#define FMC_PATT2_ATTWAIT2_Msk (0xFFUL << FMC_PATT2_ATTWAIT2_Pos)
9652#define FMC_PATT2_ATTWAIT2 FMC_PATT2_ATTWAIT2_Msk
9653#define FMC_PATT2_ATTWAIT2_0 (0x01UL << FMC_PATT2_ATTWAIT2_Pos)
9654#define FMC_PATT2_ATTWAIT2_1 (0x02UL << FMC_PATT2_ATTWAIT2_Pos)
9655#define FMC_PATT2_ATTWAIT2_2 (0x04UL << FMC_PATT2_ATTWAIT2_Pos)
9656#define FMC_PATT2_ATTWAIT2_3 (0x08UL << FMC_PATT2_ATTWAIT2_Pos)
9657#define FMC_PATT2_ATTWAIT2_4 (0x10UL << FMC_PATT2_ATTWAIT2_Pos)
9658#define FMC_PATT2_ATTWAIT2_5 (0x20UL << FMC_PATT2_ATTWAIT2_Pos)
9659#define FMC_PATT2_ATTWAIT2_6 (0x40UL << FMC_PATT2_ATTWAIT2_Pos)
9660#define FMC_PATT2_ATTWAIT2_7 (0x80UL << FMC_PATT2_ATTWAIT2_Pos)
9662#define FMC_PATT2_ATTHOLD2_Pos (16U)
9663#define FMC_PATT2_ATTHOLD2_Msk (0xFFUL << FMC_PATT2_ATTHOLD2_Pos)
9664#define FMC_PATT2_ATTHOLD2 FMC_PATT2_ATTHOLD2_Msk
9665#define FMC_PATT2_ATTHOLD2_0 (0x01UL << FMC_PATT2_ATTHOLD2_Pos)
9666#define FMC_PATT2_ATTHOLD2_1 (0x02UL << FMC_PATT2_ATTHOLD2_Pos)
9667#define FMC_PATT2_ATTHOLD2_2 (0x04UL << FMC_PATT2_ATTHOLD2_Pos)
9668#define FMC_PATT2_ATTHOLD2_3 (0x08UL << FMC_PATT2_ATTHOLD2_Pos)
9669#define FMC_PATT2_ATTHOLD2_4 (0x10UL << FMC_PATT2_ATTHOLD2_Pos)
9670#define FMC_PATT2_ATTHOLD2_5 (0x20UL << FMC_PATT2_ATTHOLD2_Pos)
9671#define FMC_PATT2_ATTHOLD2_6 (0x40UL << FMC_PATT2_ATTHOLD2_Pos)
9672#define FMC_PATT2_ATTHOLD2_7 (0x80UL << FMC_PATT2_ATTHOLD2_Pos)
9674#define FMC_PATT2_ATTHIZ2_Pos (24U)
9675#define FMC_PATT2_ATTHIZ2_Msk (0xFFUL << FMC_PATT2_ATTHIZ2_Pos)
9676#define FMC_PATT2_ATTHIZ2 FMC_PATT2_ATTHIZ2_Msk
9677#define FMC_PATT2_ATTHIZ2_0 (0x01UL << FMC_PATT2_ATTHIZ2_Pos)
9678#define FMC_PATT2_ATTHIZ2_1 (0x02UL << FMC_PATT2_ATTHIZ2_Pos)
9679#define FMC_PATT2_ATTHIZ2_2 (0x04UL << FMC_PATT2_ATTHIZ2_Pos)
9680#define FMC_PATT2_ATTHIZ2_3 (0x08UL << FMC_PATT2_ATTHIZ2_Pos)
9681#define FMC_PATT2_ATTHIZ2_4 (0x10UL << FMC_PATT2_ATTHIZ2_Pos)
9682#define FMC_PATT2_ATTHIZ2_5 (0x20UL << FMC_PATT2_ATTHIZ2_Pos)
9683#define FMC_PATT2_ATTHIZ2_6 (0x40UL << FMC_PATT2_ATTHIZ2_Pos)
9684#define FMC_PATT2_ATTHIZ2_7 (0x80UL << FMC_PATT2_ATTHIZ2_Pos)
9686/****************** Bit definition for FMC_PATT3 register ******************/
9687#define FMC_PATT3_ATTSET3_Pos (0U)
9688#define FMC_PATT3_ATTSET3_Msk (0xFFUL << FMC_PATT3_ATTSET3_Pos)
9689#define FMC_PATT3_ATTSET3 FMC_PATT3_ATTSET3_Msk
9690#define FMC_PATT3_ATTSET3_0 (0x01UL << FMC_PATT3_ATTSET3_Pos)
9691#define FMC_PATT3_ATTSET3_1 (0x02UL << FMC_PATT3_ATTSET3_Pos)
9692#define FMC_PATT3_ATTSET3_2 (0x04UL << FMC_PATT3_ATTSET3_Pos)
9693#define FMC_PATT3_ATTSET3_3 (0x08UL << FMC_PATT3_ATTSET3_Pos)
9694#define FMC_PATT3_ATTSET3_4 (0x10UL << FMC_PATT3_ATTSET3_Pos)
9695#define FMC_PATT3_ATTSET3_5 (0x20UL << FMC_PATT3_ATTSET3_Pos)
9696#define FMC_PATT3_ATTSET3_6 (0x40UL << FMC_PATT3_ATTSET3_Pos)
9697#define FMC_PATT3_ATTSET3_7 (0x80UL << FMC_PATT3_ATTSET3_Pos)
9699#define FMC_PATT3_ATTWAIT3_Pos (8U)
9700#define FMC_PATT3_ATTWAIT3_Msk (0xFFUL << FMC_PATT3_ATTWAIT3_Pos)
9701#define FMC_PATT3_ATTWAIT3 FMC_PATT3_ATTWAIT3_Msk
9702#define FMC_PATT3_ATTWAIT3_0 (0x01UL << FMC_PATT3_ATTWAIT3_Pos)
9703#define FMC_PATT3_ATTWAIT3_1 (0x02UL << FMC_PATT3_ATTWAIT3_Pos)
9704#define FMC_PATT3_ATTWAIT3_2 (0x04UL << FMC_PATT3_ATTWAIT3_Pos)
9705#define FMC_PATT3_ATTWAIT3_3 (0x08UL << FMC_PATT3_ATTWAIT3_Pos)
9706#define FMC_PATT3_ATTWAIT3_4 (0x10UL << FMC_PATT3_ATTWAIT3_Pos)
9707#define FMC_PATT3_ATTWAIT3_5 (0x20UL << FMC_PATT3_ATTWAIT3_Pos)
9708#define FMC_PATT3_ATTWAIT3_6 (0x40UL << FMC_PATT3_ATTWAIT3_Pos)
9709#define FMC_PATT3_ATTWAIT3_7 (0x80UL << FMC_PATT3_ATTWAIT3_Pos)
9711#define FMC_PATT3_ATTHOLD3_Pos (16U)
9712#define FMC_PATT3_ATTHOLD3_Msk (0xFFUL << FMC_PATT3_ATTHOLD3_Pos)
9713#define FMC_PATT3_ATTHOLD3 FMC_PATT3_ATTHOLD3_Msk
9714#define FMC_PATT3_ATTHOLD3_0 (0x01UL << FMC_PATT3_ATTHOLD3_Pos)
9715#define FMC_PATT3_ATTHOLD3_1 (0x02UL << FMC_PATT3_ATTHOLD3_Pos)
9716#define FMC_PATT3_ATTHOLD3_2 (0x04UL << FMC_PATT3_ATTHOLD3_Pos)
9717#define FMC_PATT3_ATTHOLD3_3 (0x08UL << FMC_PATT3_ATTHOLD3_Pos)
9718#define FMC_PATT3_ATTHOLD3_4 (0x10UL << FMC_PATT3_ATTHOLD3_Pos)
9719#define FMC_PATT3_ATTHOLD3_5 (0x20UL << FMC_PATT3_ATTHOLD3_Pos)
9720#define FMC_PATT3_ATTHOLD3_6 (0x40UL << FMC_PATT3_ATTHOLD3_Pos)
9721#define FMC_PATT3_ATTHOLD3_7 (0x80UL << FMC_PATT3_ATTHOLD3_Pos)
9723#define FMC_PATT3_ATTHIZ3_Pos (24U)
9724#define FMC_PATT3_ATTHIZ3_Msk (0xFFUL << FMC_PATT3_ATTHIZ3_Pos)
9725#define FMC_PATT3_ATTHIZ3 FMC_PATT3_ATTHIZ3_Msk
9726#define FMC_PATT3_ATTHIZ3_0 (0x01UL << FMC_PATT3_ATTHIZ3_Pos)
9727#define FMC_PATT3_ATTHIZ3_1 (0x02UL << FMC_PATT3_ATTHIZ3_Pos)
9728#define FMC_PATT3_ATTHIZ3_2 (0x04UL << FMC_PATT3_ATTHIZ3_Pos)
9729#define FMC_PATT3_ATTHIZ3_3 (0x08UL << FMC_PATT3_ATTHIZ3_Pos)
9730#define FMC_PATT3_ATTHIZ3_4 (0x10UL << FMC_PATT3_ATTHIZ3_Pos)
9731#define FMC_PATT3_ATTHIZ3_5 (0x20UL << FMC_PATT3_ATTHIZ3_Pos)
9732#define FMC_PATT3_ATTHIZ3_6 (0x40UL << FMC_PATT3_ATTHIZ3_Pos)
9733#define FMC_PATT3_ATTHIZ3_7 (0x80UL << FMC_PATT3_ATTHIZ3_Pos)
9735/****************** Bit definition for FMC_PATT4 register ******************/
9736#define FMC_PATT4_ATTSET4_Pos (0U)
9737#define FMC_PATT4_ATTSET4_Msk (0xFFUL << FMC_PATT4_ATTSET4_Pos)
9738#define FMC_PATT4_ATTSET4 FMC_PATT4_ATTSET4_Msk
9739#define FMC_PATT4_ATTSET4_0 (0x01UL << FMC_PATT4_ATTSET4_Pos)
9740#define FMC_PATT4_ATTSET4_1 (0x02UL << FMC_PATT4_ATTSET4_Pos)
9741#define FMC_PATT4_ATTSET4_2 (0x04UL << FMC_PATT4_ATTSET4_Pos)
9742#define FMC_PATT4_ATTSET4_3 (0x08UL << FMC_PATT4_ATTSET4_Pos)
9743#define FMC_PATT4_ATTSET4_4 (0x10UL << FMC_PATT4_ATTSET4_Pos)
9744#define FMC_PATT4_ATTSET4_5 (0x20UL << FMC_PATT4_ATTSET4_Pos)
9745#define FMC_PATT4_ATTSET4_6 (0x40UL << FMC_PATT4_ATTSET4_Pos)
9746#define FMC_PATT4_ATTSET4_7 (0x80UL << FMC_PATT4_ATTSET4_Pos)
9748#define FMC_PATT4_ATTWAIT4_Pos (8U)
9749#define FMC_PATT4_ATTWAIT4_Msk (0xFFUL << FMC_PATT4_ATTWAIT4_Pos)
9750#define FMC_PATT4_ATTWAIT4 FMC_PATT4_ATTWAIT4_Msk
9751#define FMC_PATT4_ATTWAIT4_0 (0x01UL << FMC_PATT4_ATTWAIT4_Pos)
9752#define FMC_PATT4_ATTWAIT4_1 (0x02UL << FMC_PATT4_ATTWAIT4_Pos)
9753#define FMC_PATT4_ATTWAIT4_2 (0x04UL << FMC_PATT4_ATTWAIT4_Pos)
9754#define FMC_PATT4_ATTWAIT4_3 (0x08UL << FMC_PATT4_ATTWAIT4_Pos)
9755#define FMC_PATT4_ATTWAIT4_4 (0x10UL << FMC_PATT4_ATTWAIT4_Pos)
9756#define FMC_PATT4_ATTWAIT4_5 (0x20UL << FMC_PATT4_ATTWAIT4_Pos)
9757#define FMC_PATT4_ATTWAIT4_6 (0x40UL << FMC_PATT4_ATTWAIT4_Pos)
9758#define FMC_PATT4_ATTWAIT4_7 (0x80UL << FMC_PATT4_ATTWAIT4_Pos)
9760#define FMC_PATT4_ATTHOLD4_Pos (16U)
9761#define FMC_PATT4_ATTHOLD4_Msk (0xFFUL << FMC_PATT4_ATTHOLD4_Pos)
9762#define FMC_PATT4_ATTHOLD4 FMC_PATT4_ATTHOLD4_Msk
9763#define FMC_PATT4_ATTHOLD4_0 (0x01UL << FMC_PATT4_ATTHOLD4_Pos)
9764#define FMC_PATT4_ATTHOLD4_1 (0x02UL << FMC_PATT4_ATTHOLD4_Pos)
9765#define FMC_PATT4_ATTHOLD4_2 (0x04UL << FMC_PATT4_ATTHOLD4_Pos)
9766#define FMC_PATT4_ATTHOLD4_3 (0x08UL << FMC_PATT4_ATTHOLD4_Pos)
9767#define FMC_PATT4_ATTHOLD4_4 (0x10UL << FMC_PATT4_ATTHOLD4_Pos)
9768#define FMC_PATT4_ATTHOLD4_5 (0x20UL << FMC_PATT4_ATTHOLD4_Pos)
9769#define FMC_PATT4_ATTHOLD4_6 (0x40UL << FMC_PATT4_ATTHOLD4_Pos)
9770#define FMC_PATT4_ATTHOLD4_7 (0x80UL << FMC_PATT4_ATTHOLD4_Pos)
9772#define FMC_PATT4_ATTHIZ4_Pos (24U)
9773#define FMC_PATT4_ATTHIZ4_Msk (0xFFUL << FMC_PATT4_ATTHIZ4_Pos)
9774#define FMC_PATT4_ATTHIZ4 FMC_PATT4_ATTHIZ4_Msk
9775#define FMC_PATT4_ATTHIZ4_0 (0x01UL << FMC_PATT4_ATTHIZ4_Pos)
9776#define FMC_PATT4_ATTHIZ4_1 (0x02UL << FMC_PATT4_ATTHIZ4_Pos)
9777#define FMC_PATT4_ATTHIZ4_2 (0x04UL << FMC_PATT4_ATTHIZ4_Pos)
9778#define FMC_PATT4_ATTHIZ4_3 (0x08UL << FMC_PATT4_ATTHIZ4_Pos)
9779#define FMC_PATT4_ATTHIZ4_4 (0x10UL << FMC_PATT4_ATTHIZ4_Pos)
9780#define FMC_PATT4_ATTHIZ4_5 (0x20UL << FMC_PATT4_ATTHIZ4_Pos)
9781#define FMC_PATT4_ATTHIZ4_6 (0x40UL << FMC_PATT4_ATTHIZ4_Pos)
9782#define FMC_PATT4_ATTHIZ4_7 (0x80UL << FMC_PATT4_ATTHIZ4_Pos)
9784/****************** Bit definition for FMC_PIO4 register *******************/
9785#define FMC_PIO4_IOSET4_Pos (0U)
9786#define FMC_PIO4_IOSET4_Msk (0xFFUL << FMC_PIO4_IOSET4_Pos)
9787#define FMC_PIO4_IOSET4 FMC_PIO4_IOSET4_Msk
9788#define FMC_PIO4_IOSET4_0 (0x01UL << FMC_PIO4_IOSET4_Pos)
9789#define FMC_PIO4_IOSET4_1 (0x02UL << FMC_PIO4_IOSET4_Pos)
9790#define FMC_PIO4_IOSET4_2 (0x04UL << FMC_PIO4_IOSET4_Pos)
9791#define FMC_PIO4_IOSET4_3 (0x08UL << FMC_PIO4_IOSET4_Pos)
9792#define FMC_PIO4_IOSET4_4 (0x10UL << FMC_PIO4_IOSET4_Pos)
9793#define FMC_PIO4_IOSET4_5 (0x20UL << FMC_PIO4_IOSET4_Pos)
9794#define FMC_PIO4_IOSET4_6 (0x40UL << FMC_PIO4_IOSET4_Pos)
9795#define FMC_PIO4_IOSET4_7 (0x80UL << FMC_PIO4_IOSET4_Pos)
9797#define FMC_PIO4_IOWAIT4_Pos (8U)
9798#define FMC_PIO4_IOWAIT4_Msk (0xFFUL << FMC_PIO4_IOWAIT4_Pos)
9799#define FMC_PIO4_IOWAIT4 FMC_PIO4_IOWAIT4_Msk
9800#define FMC_PIO4_IOWAIT4_0 (0x01UL << FMC_PIO4_IOWAIT4_Pos)
9801#define FMC_PIO4_IOWAIT4_1 (0x02UL << FMC_PIO4_IOWAIT4_Pos)
9802#define FMC_PIO4_IOWAIT4_2 (0x04UL << FMC_PIO4_IOWAIT4_Pos)
9803#define FMC_PIO4_IOWAIT4_3 (0x08UL << FMC_PIO4_IOWAIT4_Pos)
9804#define FMC_PIO4_IOWAIT4_4 (0x10UL << FMC_PIO4_IOWAIT4_Pos)
9805#define FMC_PIO4_IOWAIT4_5 (0x20UL << FMC_PIO4_IOWAIT4_Pos)
9806#define FMC_PIO4_IOWAIT4_6 (0x40UL << FMC_PIO4_IOWAIT4_Pos)
9807#define FMC_PIO4_IOWAIT4_7 (0x80UL << FMC_PIO4_IOWAIT4_Pos)
9809#define FMC_PIO4_IOHOLD4_Pos (16U)
9810#define FMC_PIO4_IOHOLD4_Msk (0xFFUL << FMC_PIO4_IOHOLD4_Pos)
9811#define FMC_PIO4_IOHOLD4 FMC_PIO4_IOHOLD4_Msk
9812#define FMC_PIO4_IOHOLD4_0 (0x01UL << FMC_PIO4_IOHOLD4_Pos)
9813#define FMC_PIO4_IOHOLD4_1 (0x02UL << FMC_PIO4_IOHOLD4_Pos)
9814#define FMC_PIO4_IOHOLD4_2 (0x04UL << FMC_PIO4_IOHOLD4_Pos)
9815#define FMC_PIO4_IOHOLD4_3 (0x08UL << FMC_PIO4_IOHOLD4_Pos)
9816#define FMC_PIO4_IOHOLD4_4 (0x10UL << FMC_PIO4_IOHOLD4_Pos)
9817#define FMC_PIO4_IOHOLD4_5 (0x20UL << FMC_PIO4_IOHOLD4_Pos)
9818#define FMC_PIO4_IOHOLD4_6 (0x40UL << FMC_PIO4_IOHOLD4_Pos)
9819#define FMC_PIO4_IOHOLD4_7 (0x80UL << FMC_PIO4_IOHOLD4_Pos)
9821#define FMC_PIO4_IOHIZ4_Pos (24U)
9822#define FMC_PIO4_IOHIZ4_Msk (0xFFUL << FMC_PIO4_IOHIZ4_Pos)
9823#define FMC_PIO4_IOHIZ4 FMC_PIO4_IOHIZ4_Msk
9824#define FMC_PIO4_IOHIZ4_0 (0x01UL << FMC_PIO4_IOHIZ4_Pos)
9825#define FMC_PIO4_IOHIZ4_1 (0x02UL << FMC_PIO4_IOHIZ4_Pos)
9826#define FMC_PIO4_IOHIZ4_2 (0x04UL << FMC_PIO4_IOHIZ4_Pos)
9827#define FMC_PIO4_IOHIZ4_3 (0x08UL << FMC_PIO4_IOHIZ4_Pos)
9828#define FMC_PIO4_IOHIZ4_4 (0x10UL << FMC_PIO4_IOHIZ4_Pos)
9829#define FMC_PIO4_IOHIZ4_5 (0x20UL << FMC_PIO4_IOHIZ4_Pos)
9830#define FMC_PIO4_IOHIZ4_6 (0x40UL << FMC_PIO4_IOHIZ4_Pos)
9831#define FMC_PIO4_IOHIZ4_7 (0x80UL << FMC_PIO4_IOHIZ4_Pos)
9833/****************** Bit definition for FMC_ECCR2 register ******************/
9834#define FMC_ECCR2_ECC2_Pos (0U)
9835#define FMC_ECCR2_ECC2_Msk (0xFFFFFFFFUL << FMC_ECCR2_ECC2_Pos)
9836#define FMC_ECCR2_ECC2 FMC_ECCR2_ECC2_Msk
9838/****************** Bit definition for FMC_ECCR3 register ******************/
9839#define FMC_ECCR3_ECC3_Pos (0U)
9840#define FMC_ECCR3_ECC3_Msk (0xFFFFFFFFUL << FMC_ECCR3_ECC3_Pos)
9841#define FMC_ECCR3_ECC3 FMC_ECCR3_ECC3_Msk
9843/******************************************************************************/
9844/* */
9845/* General Purpose I/O (GPIO) */
9846/* */
9847/******************************************************************************/
9848/******************* Bit definition for GPIO_MODER register *****************/
9849#define GPIO_MODER_MODER0_Pos (0U)
9850#define GPIO_MODER_MODER0_Msk (0x3UL << GPIO_MODER_MODER0_Pos)
9851#define GPIO_MODER_MODER0 GPIO_MODER_MODER0_Msk
9852#define GPIO_MODER_MODER0_0 (0x1UL << GPIO_MODER_MODER0_Pos)
9853#define GPIO_MODER_MODER0_1 (0x2UL << GPIO_MODER_MODER0_Pos)
9854#define GPIO_MODER_MODER1_Pos (2U)
9855#define GPIO_MODER_MODER1_Msk (0x3UL << GPIO_MODER_MODER1_Pos)
9856#define GPIO_MODER_MODER1 GPIO_MODER_MODER1_Msk
9857#define GPIO_MODER_MODER1_0 (0x1UL << GPIO_MODER_MODER1_Pos)
9858#define GPIO_MODER_MODER1_1 (0x2UL << GPIO_MODER_MODER1_Pos)
9859#define GPIO_MODER_MODER2_Pos (4U)
9860#define GPIO_MODER_MODER2_Msk (0x3UL << GPIO_MODER_MODER2_Pos)
9861#define GPIO_MODER_MODER2 GPIO_MODER_MODER2_Msk
9862#define GPIO_MODER_MODER2_0 (0x1UL << GPIO_MODER_MODER2_Pos)
9863#define GPIO_MODER_MODER2_1 (0x2UL << GPIO_MODER_MODER2_Pos)
9864#define GPIO_MODER_MODER3_Pos (6U)
9865#define GPIO_MODER_MODER3_Msk (0x3UL << GPIO_MODER_MODER3_Pos)
9866#define GPIO_MODER_MODER3 GPIO_MODER_MODER3_Msk
9867#define GPIO_MODER_MODER3_0 (0x1UL << GPIO_MODER_MODER3_Pos)
9868#define GPIO_MODER_MODER3_1 (0x2UL << GPIO_MODER_MODER3_Pos)
9869#define GPIO_MODER_MODER4_Pos (8U)
9870#define GPIO_MODER_MODER4_Msk (0x3UL << GPIO_MODER_MODER4_Pos)
9871#define GPIO_MODER_MODER4 GPIO_MODER_MODER4_Msk
9872#define GPIO_MODER_MODER4_0 (0x1UL << GPIO_MODER_MODER4_Pos)
9873#define GPIO_MODER_MODER4_1 (0x2UL << GPIO_MODER_MODER4_Pos)
9874#define GPIO_MODER_MODER5_Pos (10U)
9875#define GPIO_MODER_MODER5_Msk (0x3UL << GPIO_MODER_MODER5_Pos)
9876#define GPIO_MODER_MODER5 GPIO_MODER_MODER5_Msk
9877#define GPIO_MODER_MODER5_0 (0x1UL << GPIO_MODER_MODER5_Pos)
9878#define GPIO_MODER_MODER5_1 (0x2UL << GPIO_MODER_MODER5_Pos)
9879#define GPIO_MODER_MODER6_Pos (12U)
9880#define GPIO_MODER_MODER6_Msk (0x3UL << GPIO_MODER_MODER6_Pos)
9881#define GPIO_MODER_MODER6 GPIO_MODER_MODER6_Msk
9882#define GPIO_MODER_MODER6_0 (0x1UL << GPIO_MODER_MODER6_Pos)
9883#define GPIO_MODER_MODER6_1 (0x2UL << GPIO_MODER_MODER6_Pos)
9884#define GPIO_MODER_MODER7_Pos (14U)
9885#define GPIO_MODER_MODER7_Msk (0x3UL << GPIO_MODER_MODER7_Pos)
9886#define GPIO_MODER_MODER7 GPIO_MODER_MODER7_Msk
9887#define GPIO_MODER_MODER7_0 (0x1UL << GPIO_MODER_MODER7_Pos)
9888#define GPIO_MODER_MODER7_1 (0x2UL << GPIO_MODER_MODER7_Pos)
9889#define GPIO_MODER_MODER8_Pos (16U)
9890#define GPIO_MODER_MODER8_Msk (0x3UL << GPIO_MODER_MODER8_Pos)
9891#define GPIO_MODER_MODER8 GPIO_MODER_MODER8_Msk
9892#define GPIO_MODER_MODER8_0 (0x1UL << GPIO_MODER_MODER8_Pos)
9893#define GPIO_MODER_MODER8_1 (0x2UL << GPIO_MODER_MODER8_Pos)
9894#define GPIO_MODER_MODER9_Pos (18U)
9895#define GPIO_MODER_MODER9_Msk (0x3UL << GPIO_MODER_MODER9_Pos)
9896#define GPIO_MODER_MODER9 GPIO_MODER_MODER9_Msk
9897#define GPIO_MODER_MODER9_0 (0x1UL << GPIO_MODER_MODER9_Pos)
9898#define GPIO_MODER_MODER9_1 (0x2UL << GPIO_MODER_MODER9_Pos)
9899#define GPIO_MODER_MODER10_Pos (20U)
9900#define GPIO_MODER_MODER10_Msk (0x3UL << GPIO_MODER_MODER10_Pos)
9901#define GPIO_MODER_MODER10 GPIO_MODER_MODER10_Msk
9902#define GPIO_MODER_MODER10_0 (0x1UL << GPIO_MODER_MODER10_Pos)
9903#define GPIO_MODER_MODER10_1 (0x2UL << GPIO_MODER_MODER10_Pos)
9904#define GPIO_MODER_MODER11_Pos (22U)
9905#define GPIO_MODER_MODER11_Msk (0x3UL << GPIO_MODER_MODER11_Pos)
9906#define GPIO_MODER_MODER11 GPIO_MODER_MODER11_Msk
9907#define GPIO_MODER_MODER11_0 (0x1UL << GPIO_MODER_MODER11_Pos)
9908#define GPIO_MODER_MODER11_1 (0x2UL << GPIO_MODER_MODER11_Pos)
9909#define GPIO_MODER_MODER12_Pos (24U)
9910#define GPIO_MODER_MODER12_Msk (0x3UL << GPIO_MODER_MODER12_Pos)
9911#define GPIO_MODER_MODER12 GPIO_MODER_MODER12_Msk
9912#define GPIO_MODER_MODER12_0 (0x1UL << GPIO_MODER_MODER12_Pos)
9913#define GPIO_MODER_MODER12_1 (0x2UL << GPIO_MODER_MODER12_Pos)
9914#define GPIO_MODER_MODER13_Pos (26U)
9915#define GPIO_MODER_MODER13_Msk (0x3UL << GPIO_MODER_MODER13_Pos)
9916#define GPIO_MODER_MODER13 GPIO_MODER_MODER13_Msk
9917#define GPIO_MODER_MODER13_0 (0x1UL << GPIO_MODER_MODER13_Pos)
9918#define GPIO_MODER_MODER13_1 (0x2UL << GPIO_MODER_MODER13_Pos)
9919#define GPIO_MODER_MODER14_Pos (28U)
9920#define GPIO_MODER_MODER14_Msk (0x3UL << GPIO_MODER_MODER14_Pos)
9921#define GPIO_MODER_MODER14 GPIO_MODER_MODER14_Msk
9922#define GPIO_MODER_MODER14_0 (0x1UL << GPIO_MODER_MODER14_Pos)
9923#define GPIO_MODER_MODER14_1 (0x2UL << GPIO_MODER_MODER14_Pos)
9924#define GPIO_MODER_MODER15_Pos (30U)
9925#define GPIO_MODER_MODER15_Msk (0x3UL << GPIO_MODER_MODER15_Pos)
9926#define GPIO_MODER_MODER15 GPIO_MODER_MODER15_Msk
9927#define GPIO_MODER_MODER15_0 (0x1UL << GPIO_MODER_MODER15_Pos)
9928#define GPIO_MODER_MODER15_1 (0x2UL << GPIO_MODER_MODER15_Pos)
9930/****************** Bit definition for GPIO_OTYPER register *****************/
9931#define GPIO_OTYPER_OT_0 (0x00000001U)
9932#define GPIO_OTYPER_OT_1 (0x00000002U)
9933#define GPIO_OTYPER_OT_2 (0x00000004U)
9934#define GPIO_OTYPER_OT_3 (0x00000008U)
9935#define GPIO_OTYPER_OT_4 (0x00000010U)
9936#define GPIO_OTYPER_OT_5 (0x00000020U)
9937#define GPIO_OTYPER_OT_6 (0x00000040U)
9938#define GPIO_OTYPER_OT_7 (0x00000080U)
9939#define GPIO_OTYPER_OT_8 (0x00000100U)
9940#define GPIO_OTYPER_OT_9 (0x00000200U)
9941#define GPIO_OTYPER_OT_10 (0x00000400U)
9942#define GPIO_OTYPER_OT_11 (0x00000800U)
9943#define GPIO_OTYPER_OT_12 (0x00001000U)
9944#define GPIO_OTYPER_OT_13 (0x00002000U)
9945#define GPIO_OTYPER_OT_14 (0x00004000U)
9946#define GPIO_OTYPER_OT_15 (0x00008000U)
9947
9948/**************** Bit definition for GPIO_OSPEEDR register ******************/
9949#define GPIO_OSPEEDER_OSPEEDR0_Pos (0U)
9950#define GPIO_OSPEEDER_OSPEEDR0_Msk (0x3UL << GPIO_OSPEEDER_OSPEEDR0_Pos)
9951#define GPIO_OSPEEDER_OSPEEDR0 GPIO_OSPEEDER_OSPEEDR0_Msk
9952#define GPIO_OSPEEDER_OSPEEDR0_0 (0x1UL << GPIO_OSPEEDER_OSPEEDR0_Pos)
9953#define GPIO_OSPEEDER_OSPEEDR0_1 (0x2UL << GPIO_OSPEEDER_OSPEEDR0_Pos)
9954#define GPIO_OSPEEDER_OSPEEDR1_Pos (2U)
9955#define GPIO_OSPEEDER_OSPEEDR1_Msk (0x3UL << GPIO_OSPEEDER_OSPEEDR1_Pos)
9956#define GPIO_OSPEEDER_OSPEEDR1 GPIO_OSPEEDER_OSPEEDR1_Msk
9957#define GPIO_OSPEEDER_OSPEEDR1_0 (0x1UL << GPIO_OSPEEDER_OSPEEDR1_Pos)
9958#define GPIO_OSPEEDER_OSPEEDR1_1 (0x2UL << GPIO_OSPEEDER_OSPEEDR1_Pos)
9959#define GPIO_OSPEEDER_OSPEEDR2_Pos (4U)
9960#define GPIO_OSPEEDER_OSPEEDR2_Msk (0x3UL << GPIO_OSPEEDER_OSPEEDR2_Pos)
9961#define GPIO_OSPEEDER_OSPEEDR2 GPIO_OSPEEDER_OSPEEDR2_Msk
9962#define GPIO_OSPEEDER_OSPEEDR2_0 (0x1UL << GPIO_OSPEEDER_OSPEEDR2_Pos)
9963#define GPIO_OSPEEDER_OSPEEDR2_1 (0x2UL << GPIO_OSPEEDER_OSPEEDR2_Pos)
9964#define GPIO_OSPEEDER_OSPEEDR3_Pos (6U)
9965#define GPIO_OSPEEDER_OSPEEDR3_Msk (0x3UL << GPIO_OSPEEDER_OSPEEDR3_Pos)
9966#define GPIO_OSPEEDER_OSPEEDR3 GPIO_OSPEEDER_OSPEEDR3_Msk
9967#define GPIO_OSPEEDER_OSPEEDR3_0 (0x1UL << GPIO_OSPEEDER_OSPEEDR3_Pos)
9968#define GPIO_OSPEEDER_OSPEEDR3_1 (0x2UL << GPIO_OSPEEDER_OSPEEDR3_Pos)
9969#define GPIO_OSPEEDER_OSPEEDR4_Pos (8U)
9970#define GPIO_OSPEEDER_OSPEEDR4_Msk (0x3UL << GPIO_OSPEEDER_OSPEEDR4_Pos)
9971#define GPIO_OSPEEDER_OSPEEDR4 GPIO_OSPEEDER_OSPEEDR4_Msk
9972#define GPIO_OSPEEDER_OSPEEDR4_0 (0x1UL << GPIO_OSPEEDER_OSPEEDR4_Pos)
9973#define GPIO_OSPEEDER_OSPEEDR4_1 (0x2UL << GPIO_OSPEEDER_OSPEEDR4_Pos)
9974#define GPIO_OSPEEDER_OSPEEDR5_Pos (10U)
9975#define GPIO_OSPEEDER_OSPEEDR5_Msk (0x3UL << GPIO_OSPEEDER_OSPEEDR5_Pos)
9976#define GPIO_OSPEEDER_OSPEEDR5 GPIO_OSPEEDER_OSPEEDR5_Msk
9977#define GPIO_OSPEEDER_OSPEEDR5_0 (0x1UL << GPIO_OSPEEDER_OSPEEDR5_Pos)
9978#define GPIO_OSPEEDER_OSPEEDR5_1 (0x2UL << GPIO_OSPEEDER_OSPEEDR5_Pos)
9979#define GPIO_OSPEEDER_OSPEEDR6_Pos (12U)
9980#define GPIO_OSPEEDER_OSPEEDR6_Msk (0x3UL << GPIO_OSPEEDER_OSPEEDR6_Pos)
9981#define GPIO_OSPEEDER_OSPEEDR6 GPIO_OSPEEDER_OSPEEDR6_Msk
9982#define GPIO_OSPEEDER_OSPEEDR6_0 (0x1UL << GPIO_OSPEEDER_OSPEEDR6_Pos)
9983#define GPIO_OSPEEDER_OSPEEDR6_1 (0x2UL << GPIO_OSPEEDER_OSPEEDR6_Pos)
9984#define GPIO_OSPEEDER_OSPEEDR7_Pos (14U)
9985#define GPIO_OSPEEDER_OSPEEDR7_Msk (0x3UL << GPIO_OSPEEDER_OSPEEDR7_Pos)
9986#define GPIO_OSPEEDER_OSPEEDR7 GPIO_OSPEEDER_OSPEEDR7_Msk
9987#define GPIO_OSPEEDER_OSPEEDR7_0 (0x1UL << GPIO_OSPEEDER_OSPEEDR7_Pos)
9988#define GPIO_OSPEEDER_OSPEEDR7_1 (0x2UL << GPIO_OSPEEDER_OSPEEDR7_Pos)
9989#define GPIO_OSPEEDER_OSPEEDR8_Pos (16U)
9990#define GPIO_OSPEEDER_OSPEEDR8_Msk (0x3UL << GPIO_OSPEEDER_OSPEEDR8_Pos)
9991#define GPIO_OSPEEDER_OSPEEDR8 GPIO_OSPEEDER_OSPEEDR8_Msk
9992#define GPIO_OSPEEDER_OSPEEDR8_0 (0x1UL << GPIO_OSPEEDER_OSPEEDR8_Pos)
9993#define GPIO_OSPEEDER_OSPEEDR8_1 (0x2UL << GPIO_OSPEEDER_OSPEEDR8_Pos)
9994#define GPIO_OSPEEDER_OSPEEDR9_Pos (18U)
9995#define GPIO_OSPEEDER_OSPEEDR9_Msk (0x3UL << GPIO_OSPEEDER_OSPEEDR9_Pos)
9996#define GPIO_OSPEEDER_OSPEEDR9 GPIO_OSPEEDER_OSPEEDR9_Msk
9997#define GPIO_OSPEEDER_OSPEEDR9_0 (0x1UL << GPIO_OSPEEDER_OSPEEDR9_Pos)
9998#define GPIO_OSPEEDER_OSPEEDR9_1 (0x2UL << GPIO_OSPEEDER_OSPEEDR9_Pos)
9999#define GPIO_OSPEEDER_OSPEEDR10_Pos (20U)
10000#define GPIO_OSPEEDER_OSPEEDR10_Msk (0x3UL << GPIO_OSPEEDER_OSPEEDR10_Pos)
10001#define GPIO_OSPEEDER_OSPEEDR10 GPIO_OSPEEDER_OSPEEDR10_Msk
10002#define GPIO_OSPEEDER_OSPEEDR10_0 (0x1UL << GPIO_OSPEEDER_OSPEEDR10_Pos)
10003#define GPIO_OSPEEDER_OSPEEDR10_1 (0x2UL << GPIO_OSPEEDER_OSPEEDR10_Pos)
10004#define GPIO_OSPEEDER_OSPEEDR11_Pos (22U)
10005#define GPIO_OSPEEDER_OSPEEDR11_Msk (0x3UL << GPIO_OSPEEDER_OSPEEDR11_Pos)
10006#define GPIO_OSPEEDER_OSPEEDR11 GPIO_OSPEEDER_OSPEEDR11_Msk
10007#define GPIO_OSPEEDER_OSPEEDR11_0 (0x1UL << GPIO_OSPEEDER_OSPEEDR11_Pos)
10008#define GPIO_OSPEEDER_OSPEEDR11_1 (0x2UL << GPIO_OSPEEDER_OSPEEDR11_Pos)
10009#define GPIO_OSPEEDER_OSPEEDR12_Pos (24U)
10010#define GPIO_OSPEEDER_OSPEEDR12_Msk (0x3UL << GPIO_OSPEEDER_OSPEEDR12_Pos)
10011#define GPIO_OSPEEDER_OSPEEDR12 GPIO_OSPEEDER_OSPEEDR12_Msk
10012#define GPIO_OSPEEDER_OSPEEDR12_0 (0x1UL << GPIO_OSPEEDER_OSPEEDR12_Pos)
10013#define GPIO_OSPEEDER_OSPEEDR12_1 (0x2UL << GPIO_OSPEEDER_OSPEEDR12_Pos)
10014#define GPIO_OSPEEDER_OSPEEDR13_Pos (26U)
10015#define GPIO_OSPEEDER_OSPEEDR13_Msk (0x3UL << GPIO_OSPEEDER_OSPEEDR13_Pos)
10016#define GPIO_OSPEEDER_OSPEEDR13 GPIO_OSPEEDER_OSPEEDR13_Msk
10017#define GPIO_OSPEEDER_OSPEEDR13_0 (0x1UL << GPIO_OSPEEDER_OSPEEDR13_Pos)
10018#define GPIO_OSPEEDER_OSPEEDR13_1 (0x2UL << GPIO_OSPEEDER_OSPEEDR13_Pos)
10019#define GPIO_OSPEEDER_OSPEEDR14_Pos (28U)
10020#define GPIO_OSPEEDER_OSPEEDR14_Msk (0x3UL << GPIO_OSPEEDER_OSPEEDR14_Pos)
10021#define GPIO_OSPEEDER_OSPEEDR14 GPIO_OSPEEDER_OSPEEDR14_Msk
10022#define GPIO_OSPEEDER_OSPEEDR14_0 (0x1UL << GPIO_OSPEEDER_OSPEEDR14_Pos)
10023#define GPIO_OSPEEDER_OSPEEDR14_1 (0x2UL << GPIO_OSPEEDER_OSPEEDR14_Pos)
10024#define GPIO_OSPEEDER_OSPEEDR15_Pos (30U)
10025#define GPIO_OSPEEDER_OSPEEDR15_Msk (0x3UL << GPIO_OSPEEDER_OSPEEDR15_Pos)
10026#define GPIO_OSPEEDER_OSPEEDR15 GPIO_OSPEEDER_OSPEEDR15_Msk
10027#define GPIO_OSPEEDER_OSPEEDR15_0 (0x1UL << GPIO_OSPEEDER_OSPEEDR15_Pos)
10028#define GPIO_OSPEEDER_OSPEEDR15_1 (0x2UL << GPIO_OSPEEDER_OSPEEDR15_Pos)
10030/******************* Bit definition for GPIO_PUPDR register ******************/
10031#define GPIO_PUPDR_PUPDR0_Pos (0U)
10032#define GPIO_PUPDR_PUPDR0_Msk (0x3UL << GPIO_PUPDR_PUPDR0_Pos)
10033#define GPIO_PUPDR_PUPDR0 GPIO_PUPDR_PUPDR0_Msk
10034#define GPIO_PUPDR_PUPDR0_0 (0x1UL << GPIO_PUPDR_PUPDR0_Pos)
10035#define GPIO_PUPDR_PUPDR0_1 (0x2UL << GPIO_PUPDR_PUPDR0_Pos)
10036#define GPIO_PUPDR_PUPDR1_Pos (2U)
10037#define GPIO_PUPDR_PUPDR1_Msk (0x3UL << GPIO_PUPDR_PUPDR1_Pos)
10038#define GPIO_PUPDR_PUPDR1 GPIO_PUPDR_PUPDR1_Msk
10039#define GPIO_PUPDR_PUPDR1_0 (0x1UL << GPIO_PUPDR_PUPDR1_Pos)
10040#define GPIO_PUPDR_PUPDR1_1 (0x2UL << GPIO_PUPDR_PUPDR1_Pos)
10041#define GPIO_PUPDR_PUPDR2_Pos (4U)
10042#define GPIO_PUPDR_PUPDR2_Msk (0x3UL << GPIO_PUPDR_PUPDR2_Pos)
10043#define GPIO_PUPDR_PUPDR2 GPIO_PUPDR_PUPDR2_Msk
10044#define GPIO_PUPDR_PUPDR2_0 (0x1UL << GPIO_PUPDR_PUPDR2_Pos)
10045#define GPIO_PUPDR_PUPDR2_1 (0x2UL << GPIO_PUPDR_PUPDR2_Pos)
10046#define GPIO_PUPDR_PUPDR3_Pos (6U)
10047#define GPIO_PUPDR_PUPDR3_Msk (0x3UL << GPIO_PUPDR_PUPDR3_Pos)
10048#define GPIO_PUPDR_PUPDR3 GPIO_PUPDR_PUPDR3_Msk
10049#define GPIO_PUPDR_PUPDR3_0 (0x1UL << GPIO_PUPDR_PUPDR3_Pos)
10050#define GPIO_PUPDR_PUPDR3_1 (0x2UL << GPIO_PUPDR_PUPDR3_Pos)
10051#define GPIO_PUPDR_PUPDR4_Pos (8U)
10052#define GPIO_PUPDR_PUPDR4_Msk (0x3UL << GPIO_PUPDR_PUPDR4_Pos)
10053#define GPIO_PUPDR_PUPDR4 GPIO_PUPDR_PUPDR4_Msk
10054#define GPIO_PUPDR_PUPDR4_0 (0x1UL << GPIO_PUPDR_PUPDR4_Pos)
10055#define GPIO_PUPDR_PUPDR4_1 (0x2UL << GPIO_PUPDR_PUPDR4_Pos)
10056#define GPIO_PUPDR_PUPDR5_Pos (10U)
10057#define GPIO_PUPDR_PUPDR5_Msk (0x3UL << GPIO_PUPDR_PUPDR5_Pos)
10058#define GPIO_PUPDR_PUPDR5 GPIO_PUPDR_PUPDR5_Msk
10059#define GPIO_PUPDR_PUPDR5_0 (0x1UL << GPIO_PUPDR_PUPDR5_Pos)
10060#define GPIO_PUPDR_PUPDR5_1 (0x2UL << GPIO_PUPDR_PUPDR5_Pos)
10061#define GPIO_PUPDR_PUPDR6_Pos (12U)
10062#define GPIO_PUPDR_PUPDR6_Msk (0x3UL << GPIO_PUPDR_PUPDR6_Pos)
10063#define GPIO_PUPDR_PUPDR6 GPIO_PUPDR_PUPDR6_Msk
10064#define GPIO_PUPDR_PUPDR6_0 (0x1UL << GPIO_PUPDR_PUPDR6_Pos)
10065#define GPIO_PUPDR_PUPDR6_1 (0x2UL << GPIO_PUPDR_PUPDR6_Pos)
10066#define GPIO_PUPDR_PUPDR7_Pos (14U)
10067#define GPIO_PUPDR_PUPDR7_Msk (0x3UL << GPIO_PUPDR_PUPDR7_Pos)
10068#define GPIO_PUPDR_PUPDR7 GPIO_PUPDR_PUPDR7_Msk
10069#define GPIO_PUPDR_PUPDR7_0 (0x1UL << GPIO_PUPDR_PUPDR7_Pos)
10070#define GPIO_PUPDR_PUPDR7_1 (0x2UL << GPIO_PUPDR_PUPDR7_Pos)
10071#define GPIO_PUPDR_PUPDR8_Pos (16U)
10072#define GPIO_PUPDR_PUPDR8_Msk (0x3UL << GPIO_PUPDR_PUPDR8_Pos)
10073#define GPIO_PUPDR_PUPDR8 GPIO_PUPDR_PUPDR8_Msk
10074#define GPIO_PUPDR_PUPDR8_0 (0x1UL << GPIO_PUPDR_PUPDR8_Pos)
10075#define GPIO_PUPDR_PUPDR8_1 (0x2UL << GPIO_PUPDR_PUPDR8_Pos)
10076#define GPIO_PUPDR_PUPDR9_Pos (18U)
10077#define GPIO_PUPDR_PUPDR9_Msk (0x3UL << GPIO_PUPDR_PUPDR9_Pos)
10078#define GPIO_PUPDR_PUPDR9 GPIO_PUPDR_PUPDR9_Msk
10079#define GPIO_PUPDR_PUPDR9_0 (0x1UL << GPIO_PUPDR_PUPDR9_Pos)
10080#define GPIO_PUPDR_PUPDR9_1 (0x2UL << GPIO_PUPDR_PUPDR9_Pos)
10081#define GPIO_PUPDR_PUPDR10_Pos (20U)
10082#define GPIO_PUPDR_PUPDR10_Msk (0x3UL << GPIO_PUPDR_PUPDR10_Pos)
10083#define GPIO_PUPDR_PUPDR10 GPIO_PUPDR_PUPDR10_Msk
10084#define GPIO_PUPDR_PUPDR10_0 (0x1UL << GPIO_PUPDR_PUPDR10_Pos)
10085#define GPIO_PUPDR_PUPDR10_1 (0x2UL << GPIO_PUPDR_PUPDR10_Pos)
10086#define GPIO_PUPDR_PUPDR11_Pos (22U)
10087#define GPIO_PUPDR_PUPDR11_Msk (0x3UL << GPIO_PUPDR_PUPDR11_Pos)
10088#define GPIO_PUPDR_PUPDR11 GPIO_PUPDR_PUPDR11_Msk
10089#define GPIO_PUPDR_PUPDR11_0 (0x1UL << GPIO_PUPDR_PUPDR11_Pos)
10090#define GPIO_PUPDR_PUPDR11_1 (0x2UL << GPIO_PUPDR_PUPDR11_Pos)
10091#define GPIO_PUPDR_PUPDR12_Pos (24U)
10092#define GPIO_PUPDR_PUPDR12_Msk (0x3UL << GPIO_PUPDR_PUPDR12_Pos)
10093#define GPIO_PUPDR_PUPDR12 GPIO_PUPDR_PUPDR12_Msk
10094#define GPIO_PUPDR_PUPDR12_0 (0x1UL << GPIO_PUPDR_PUPDR12_Pos)
10095#define GPIO_PUPDR_PUPDR12_1 (0x2UL << GPIO_PUPDR_PUPDR12_Pos)
10096#define GPIO_PUPDR_PUPDR13_Pos (26U)
10097#define GPIO_PUPDR_PUPDR13_Msk (0x3UL << GPIO_PUPDR_PUPDR13_Pos)
10098#define GPIO_PUPDR_PUPDR13 GPIO_PUPDR_PUPDR13_Msk
10099#define GPIO_PUPDR_PUPDR13_0 (0x1UL << GPIO_PUPDR_PUPDR13_Pos)
10100#define GPIO_PUPDR_PUPDR13_1 (0x2UL << GPIO_PUPDR_PUPDR13_Pos)
10101#define GPIO_PUPDR_PUPDR14_Pos (28U)
10102#define GPIO_PUPDR_PUPDR14_Msk (0x3UL << GPIO_PUPDR_PUPDR14_Pos)
10103#define GPIO_PUPDR_PUPDR14 GPIO_PUPDR_PUPDR14_Msk
10104#define GPIO_PUPDR_PUPDR14_0 (0x1UL << GPIO_PUPDR_PUPDR14_Pos)
10105#define GPIO_PUPDR_PUPDR14_1 (0x2UL << GPIO_PUPDR_PUPDR14_Pos)
10106#define GPIO_PUPDR_PUPDR15_Pos (30U)
10107#define GPIO_PUPDR_PUPDR15_Msk (0x3UL << GPIO_PUPDR_PUPDR15_Pos)
10108#define GPIO_PUPDR_PUPDR15 GPIO_PUPDR_PUPDR15_Msk
10109#define GPIO_PUPDR_PUPDR15_0 (0x1UL << GPIO_PUPDR_PUPDR15_Pos)
10110#define GPIO_PUPDR_PUPDR15_1 (0x2UL << GPIO_PUPDR_PUPDR15_Pos)
10112/******************* Bit definition for GPIO_IDR register *******************/
10113#define GPIO_IDR_0 (0x00000001U)
10114#define GPIO_IDR_1 (0x00000002U)
10115#define GPIO_IDR_2 (0x00000004U)
10116#define GPIO_IDR_3 (0x00000008U)
10117#define GPIO_IDR_4 (0x00000010U)
10118#define GPIO_IDR_5 (0x00000020U)
10119#define GPIO_IDR_6 (0x00000040U)
10120#define GPIO_IDR_7 (0x00000080U)
10121#define GPIO_IDR_8 (0x00000100U)
10122#define GPIO_IDR_9 (0x00000200U)
10123#define GPIO_IDR_10 (0x00000400U)
10124#define GPIO_IDR_11 (0x00000800U)
10125#define GPIO_IDR_12 (0x00001000U)
10126#define GPIO_IDR_13 (0x00002000U)
10127#define GPIO_IDR_14 (0x00004000U)
10128#define GPIO_IDR_15 (0x00008000U)
10129
10130/****************** Bit definition for GPIO_ODR register ********************/
10131#define GPIO_ODR_0 (0x00000001U)
10132#define GPIO_ODR_1 (0x00000002U)
10133#define GPIO_ODR_2 (0x00000004U)
10134#define GPIO_ODR_3 (0x00000008U)
10135#define GPIO_ODR_4 (0x00000010U)
10136#define GPIO_ODR_5 (0x00000020U)
10137#define GPIO_ODR_6 (0x00000040U)
10138#define GPIO_ODR_7 (0x00000080U)
10139#define GPIO_ODR_8 (0x00000100U)
10140#define GPIO_ODR_9 (0x00000200U)
10141#define GPIO_ODR_10 (0x00000400U)
10142#define GPIO_ODR_11 (0x00000800U)
10143#define GPIO_ODR_12 (0x00001000U)
10144#define GPIO_ODR_13 (0x00002000U)
10145#define GPIO_ODR_14 (0x00004000U)
10146#define GPIO_ODR_15 (0x00008000U)
10147
10148/****************** Bit definition for GPIO_BSRR register ********************/
10149#define GPIO_BSRR_BS_0 (0x00000001U)
10150#define GPIO_BSRR_BS_1 (0x00000002U)
10151#define GPIO_BSRR_BS_2 (0x00000004U)
10152#define GPIO_BSRR_BS_3 (0x00000008U)
10153#define GPIO_BSRR_BS_4 (0x00000010U)
10154#define GPIO_BSRR_BS_5 (0x00000020U)
10155#define GPIO_BSRR_BS_6 (0x00000040U)
10156#define GPIO_BSRR_BS_7 (0x00000080U)
10157#define GPIO_BSRR_BS_8 (0x00000100U)
10158#define GPIO_BSRR_BS_9 (0x00000200U)
10159#define GPIO_BSRR_BS_10 (0x00000400U)
10160#define GPIO_BSRR_BS_11 (0x00000800U)
10161#define GPIO_BSRR_BS_12 (0x00001000U)
10162#define GPIO_BSRR_BS_13 (0x00002000U)
10163#define GPIO_BSRR_BS_14 (0x00004000U)
10164#define GPIO_BSRR_BS_15 (0x00008000U)
10165#define GPIO_BSRR_BR_0 (0x00010000U)
10166#define GPIO_BSRR_BR_1 (0x00020000U)
10167#define GPIO_BSRR_BR_2 (0x00040000U)
10168#define GPIO_BSRR_BR_3 (0x00080000U)
10169#define GPIO_BSRR_BR_4 (0x00100000U)
10170#define GPIO_BSRR_BR_5 (0x00200000U)
10171#define GPIO_BSRR_BR_6 (0x00400000U)
10172#define GPIO_BSRR_BR_7 (0x00800000U)
10173#define GPIO_BSRR_BR_8 (0x01000000U)
10174#define GPIO_BSRR_BR_9 (0x02000000U)
10175#define GPIO_BSRR_BR_10 (0x04000000U)
10176#define GPIO_BSRR_BR_11 (0x08000000U)
10177#define GPIO_BSRR_BR_12 (0x10000000U)
10178#define GPIO_BSRR_BR_13 (0x20000000U)
10179#define GPIO_BSRR_BR_14 (0x40000000U)
10180#define GPIO_BSRR_BR_15 (0x80000000U)
10181
10182/****************** Bit definition for GPIO_LCKR register ********************/
10183#define GPIO_LCKR_LCK0_Pos (0U)
10184#define GPIO_LCKR_LCK0_Msk (0x1UL << GPIO_LCKR_LCK0_Pos)
10185#define GPIO_LCKR_LCK0 GPIO_LCKR_LCK0_Msk
10186#define GPIO_LCKR_LCK1_Pos (1U)
10187#define GPIO_LCKR_LCK1_Msk (0x1UL << GPIO_LCKR_LCK1_Pos)
10188#define GPIO_LCKR_LCK1 GPIO_LCKR_LCK1_Msk
10189#define GPIO_LCKR_LCK2_Pos (2U)
10190#define GPIO_LCKR_LCK2_Msk (0x1UL << GPIO_LCKR_LCK2_Pos)
10191#define GPIO_LCKR_LCK2 GPIO_LCKR_LCK2_Msk
10192#define GPIO_LCKR_LCK3_Pos (3U)
10193#define GPIO_LCKR_LCK3_Msk (0x1UL << GPIO_LCKR_LCK3_Pos)
10194#define GPIO_LCKR_LCK3 GPIO_LCKR_LCK3_Msk
10195#define GPIO_LCKR_LCK4_Pos (4U)
10196#define GPIO_LCKR_LCK4_Msk (0x1UL << GPIO_LCKR_LCK4_Pos)
10197#define GPIO_LCKR_LCK4 GPIO_LCKR_LCK4_Msk
10198#define GPIO_LCKR_LCK5_Pos (5U)
10199#define GPIO_LCKR_LCK5_Msk (0x1UL << GPIO_LCKR_LCK5_Pos)
10200#define GPIO_LCKR_LCK5 GPIO_LCKR_LCK5_Msk
10201#define GPIO_LCKR_LCK6_Pos (6U)
10202#define GPIO_LCKR_LCK6_Msk (0x1UL << GPIO_LCKR_LCK6_Pos)
10203#define GPIO_LCKR_LCK6 GPIO_LCKR_LCK6_Msk
10204#define GPIO_LCKR_LCK7_Pos (7U)
10205#define GPIO_LCKR_LCK7_Msk (0x1UL << GPIO_LCKR_LCK7_Pos)
10206#define GPIO_LCKR_LCK7 GPIO_LCKR_LCK7_Msk
10207#define GPIO_LCKR_LCK8_Pos (8U)
10208#define GPIO_LCKR_LCK8_Msk (0x1UL << GPIO_LCKR_LCK8_Pos)
10209#define GPIO_LCKR_LCK8 GPIO_LCKR_LCK8_Msk
10210#define GPIO_LCKR_LCK9_Pos (9U)
10211#define GPIO_LCKR_LCK9_Msk (0x1UL << GPIO_LCKR_LCK9_Pos)
10212#define GPIO_LCKR_LCK9 GPIO_LCKR_LCK9_Msk
10213#define GPIO_LCKR_LCK10_Pos (10U)
10214#define GPIO_LCKR_LCK10_Msk (0x1UL << GPIO_LCKR_LCK10_Pos)
10215#define GPIO_LCKR_LCK10 GPIO_LCKR_LCK10_Msk
10216#define GPIO_LCKR_LCK11_Pos (11U)
10217#define GPIO_LCKR_LCK11_Msk (0x1UL << GPIO_LCKR_LCK11_Pos)
10218#define GPIO_LCKR_LCK11 GPIO_LCKR_LCK11_Msk
10219#define GPIO_LCKR_LCK12_Pos (12U)
10220#define GPIO_LCKR_LCK12_Msk (0x1UL << GPIO_LCKR_LCK12_Pos)
10221#define GPIO_LCKR_LCK12 GPIO_LCKR_LCK12_Msk
10222#define GPIO_LCKR_LCK13_Pos (13U)
10223#define GPIO_LCKR_LCK13_Msk (0x1UL << GPIO_LCKR_LCK13_Pos)
10224#define GPIO_LCKR_LCK13 GPIO_LCKR_LCK13_Msk
10225#define GPIO_LCKR_LCK14_Pos (14U)
10226#define GPIO_LCKR_LCK14_Msk (0x1UL << GPIO_LCKR_LCK14_Pos)
10227#define GPIO_LCKR_LCK14 GPIO_LCKR_LCK14_Msk
10228#define GPIO_LCKR_LCK15_Pos (15U)
10229#define GPIO_LCKR_LCK15_Msk (0x1UL << GPIO_LCKR_LCK15_Pos)
10230#define GPIO_LCKR_LCK15 GPIO_LCKR_LCK15_Msk
10231#define GPIO_LCKR_LCKK_Pos (16U)
10232#define GPIO_LCKR_LCKK_Msk (0x1UL << GPIO_LCKR_LCKK_Pos)
10233#define GPIO_LCKR_LCKK GPIO_LCKR_LCKK_Msk
10234
10235/****************** Bit definition for GPIO_AFRL register ********************/
10236#define GPIO_AFRL_AFRL0_Pos (0U)
10237#define GPIO_AFRL_AFRL0_Msk (0xFUL << GPIO_AFRL_AFRL0_Pos)
10238#define GPIO_AFRL_AFRL0 GPIO_AFRL_AFRL0_Msk
10239#define GPIO_AFRL_AFRL1_Pos (4U)
10240#define GPIO_AFRL_AFRL1_Msk (0xFUL << GPIO_AFRL_AFRL1_Pos)
10241#define GPIO_AFRL_AFRL1 GPIO_AFRL_AFRL1_Msk
10242#define GPIO_AFRL_AFRL2_Pos (8U)
10243#define GPIO_AFRL_AFRL2_Msk (0xFUL << GPIO_AFRL_AFRL2_Pos)
10244#define GPIO_AFRL_AFRL2 GPIO_AFRL_AFRL2_Msk
10245#define GPIO_AFRL_AFRL3_Pos (12U)
10246#define GPIO_AFRL_AFRL3_Msk (0xFUL << GPIO_AFRL_AFRL3_Pos)
10247#define GPIO_AFRL_AFRL3 GPIO_AFRL_AFRL3_Msk
10248#define GPIO_AFRL_AFRL4_Pos (16U)
10249#define GPIO_AFRL_AFRL4_Msk (0xFUL << GPIO_AFRL_AFRL4_Pos)
10250#define GPIO_AFRL_AFRL4 GPIO_AFRL_AFRL4_Msk
10251#define GPIO_AFRL_AFRL5_Pos (20U)
10252#define GPIO_AFRL_AFRL5_Msk (0xFUL << GPIO_AFRL_AFRL5_Pos)
10253#define GPIO_AFRL_AFRL5 GPIO_AFRL_AFRL5_Msk
10254#define GPIO_AFRL_AFRL6_Pos (24U)
10255#define GPIO_AFRL_AFRL6_Msk (0xFUL << GPIO_AFRL_AFRL6_Pos)
10256#define GPIO_AFRL_AFRL6 GPIO_AFRL_AFRL6_Msk
10257#define GPIO_AFRL_AFRL7_Pos (28U)
10258#define GPIO_AFRL_AFRL7_Msk (0xFUL << GPIO_AFRL_AFRL7_Pos)
10259#define GPIO_AFRL_AFRL7 GPIO_AFRL_AFRL7_Msk
10260
10261/****************** Bit definition for GPIO_AFRH register ********************/
10262#define GPIO_AFRH_AFRH0_Pos (0U)
10263#define GPIO_AFRH_AFRH0_Msk (0xFUL << GPIO_AFRH_AFRH0_Pos)
10264#define GPIO_AFRH_AFRH0 GPIO_AFRH_AFRH0_Msk
10265#define GPIO_AFRH_AFRH1_Pos (4U)
10266#define GPIO_AFRH_AFRH1_Msk (0xFUL << GPIO_AFRH_AFRH1_Pos)
10267#define GPIO_AFRH_AFRH1 GPIO_AFRH_AFRH1_Msk
10268#define GPIO_AFRH_AFRH2_Pos (8U)
10269#define GPIO_AFRH_AFRH2_Msk (0xFUL << GPIO_AFRH_AFRH2_Pos)
10270#define GPIO_AFRH_AFRH2 GPIO_AFRH_AFRH2_Msk
10271#define GPIO_AFRH_AFRH3_Pos (12U)
10272#define GPIO_AFRH_AFRH3_Msk (0xFUL << GPIO_AFRH_AFRH3_Pos)
10273#define GPIO_AFRH_AFRH3 GPIO_AFRH_AFRH3_Msk
10274#define GPIO_AFRH_AFRH4_Pos (16U)
10275#define GPIO_AFRH_AFRH4_Msk (0xFUL << GPIO_AFRH_AFRH4_Pos)
10276#define GPIO_AFRH_AFRH4 GPIO_AFRH_AFRH4_Msk
10277#define GPIO_AFRH_AFRH5_Pos (20U)
10278#define GPIO_AFRH_AFRH5_Msk (0xFUL << GPIO_AFRH_AFRH5_Pos)
10279#define GPIO_AFRH_AFRH5 GPIO_AFRH_AFRH5_Msk
10280#define GPIO_AFRH_AFRH6_Pos (24U)
10281#define GPIO_AFRH_AFRH6_Msk (0xFUL << GPIO_AFRH_AFRH6_Pos)
10282#define GPIO_AFRH_AFRH6 GPIO_AFRH_AFRH6_Msk
10283#define GPIO_AFRH_AFRH7_Pos (28U)
10284#define GPIO_AFRH_AFRH7_Msk (0xFUL << GPIO_AFRH_AFRH7_Pos)
10285#define GPIO_AFRH_AFRH7 GPIO_AFRH_AFRH7_Msk
10286
10287/****************** Bit definition for GPIO_BRR register *********************/
10288#define GPIO_BRR_BR_0 (0x00000001U)
10289#define GPIO_BRR_BR_1 (0x00000002U)
10290#define GPIO_BRR_BR_2 (0x00000004U)
10291#define GPIO_BRR_BR_3 (0x00000008U)
10292#define GPIO_BRR_BR_4 (0x00000010U)
10293#define GPIO_BRR_BR_5 (0x00000020U)
10294#define GPIO_BRR_BR_6 (0x00000040U)
10295#define GPIO_BRR_BR_7 (0x00000080U)
10296#define GPIO_BRR_BR_8 (0x00000100U)
10297#define GPIO_BRR_BR_9 (0x00000200U)
10298#define GPIO_BRR_BR_10 (0x00000400U)
10299#define GPIO_BRR_BR_11 (0x00000800U)
10300#define GPIO_BRR_BR_12 (0x00001000U)
10301#define GPIO_BRR_BR_13 (0x00002000U)
10302#define GPIO_BRR_BR_14 (0x00004000U)
10303#define GPIO_BRR_BR_15 (0x00008000U)
10304
10305/******************************************************************************/
10306/* */
10307/* Inter-integrated Circuit Interface (I2C) */
10308/* */
10309/******************************************************************************/
10310/******************* Bit definition for I2C_CR1 register *******************/
10311#define I2C_CR1_PE_Pos (0U)
10312#define I2C_CR1_PE_Msk (0x1UL << I2C_CR1_PE_Pos)
10313#define I2C_CR1_PE I2C_CR1_PE_Msk
10314#define I2C_CR1_TXIE_Pos (1U)
10315#define I2C_CR1_TXIE_Msk (0x1UL << I2C_CR1_TXIE_Pos)
10316#define I2C_CR1_TXIE I2C_CR1_TXIE_Msk
10317#define I2C_CR1_RXIE_Pos (2U)
10318#define I2C_CR1_RXIE_Msk (0x1UL << I2C_CR1_RXIE_Pos)
10319#define I2C_CR1_RXIE I2C_CR1_RXIE_Msk
10320#define I2C_CR1_ADDRIE_Pos (3U)
10321#define I2C_CR1_ADDRIE_Msk (0x1UL << I2C_CR1_ADDRIE_Pos)
10322#define I2C_CR1_ADDRIE I2C_CR1_ADDRIE_Msk
10323#define I2C_CR1_NACKIE_Pos (4U)
10324#define I2C_CR1_NACKIE_Msk (0x1UL << I2C_CR1_NACKIE_Pos)
10325#define I2C_CR1_NACKIE I2C_CR1_NACKIE_Msk
10326#define I2C_CR1_STOPIE_Pos (5U)
10327#define I2C_CR1_STOPIE_Msk (0x1UL << I2C_CR1_STOPIE_Pos)
10328#define I2C_CR1_STOPIE I2C_CR1_STOPIE_Msk
10329#define I2C_CR1_TCIE_Pos (6U)
10330#define I2C_CR1_TCIE_Msk (0x1UL << I2C_CR1_TCIE_Pos)
10331#define I2C_CR1_TCIE I2C_CR1_TCIE_Msk
10332#define I2C_CR1_ERRIE_Pos (7U)
10333#define I2C_CR1_ERRIE_Msk (0x1UL << I2C_CR1_ERRIE_Pos)
10334#define I2C_CR1_ERRIE I2C_CR1_ERRIE_Msk
10335#define I2C_CR1_DNF_Pos (8U)
10336#define I2C_CR1_DNF_Msk (0xFUL << I2C_CR1_DNF_Pos)
10337#define I2C_CR1_DNF I2C_CR1_DNF_Msk
10338#define I2C_CR1_ANFOFF_Pos (12U)
10339#define I2C_CR1_ANFOFF_Msk (0x1UL << I2C_CR1_ANFOFF_Pos)
10340#define I2C_CR1_ANFOFF I2C_CR1_ANFOFF_Msk
10341#define I2C_CR1_SWRST_Pos (13U)
10342#define I2C_CR1_SWRST_Msk (0x1UL << I2C_CR1_SWRST_Pos)
10343#define I2C_CR1_SWRST I2C_CR1_SWRST_Msk
10344#define I2C_CR1_TXDMAEN_Pos (14U)
10345#define I2C_CR1_TXDMAEN_Msk (0x1UL << I2C_CR1_TXDMAEN_Pos)
10346#define I2C_CR1_TXDMAEN I2C_CR1_TXDMAEN_Msk
10347#define I2C_CR1_RXDMAEN_Pos (15U)
10348#define I2C_CR1_RXDMAEN_Msk (0x1UL << I2C_CR1_RXDMAEN_Pos)
10349#define I2C_CR1_RXDMAEN I2C_CR1_RXDMAEN_Msk
10350#define I2C_CR1_SBC_Pos (16U)
10351#define I2C_CR1_SBC_Msk (0x1UL << I2C_CR1_SBC_Pos)
10352#define I2C_CR1_SBC I2C_CR1_SBC_Msk
10353#define I2C_CR1_NOSTRETCH_Pos (17U)
10354#define I2C_CR1_NOSTRETCH_Msk (0x1UL << I2C_CR1_NOSTRETCH_Pos)
10355#define I2C_CR1_NOSTRETCH I2C_CR1_NOSTRETCH_Msk
10356#define I2C_CR1_WUPEN_Pos (18U)
10357#define I2C_CR1_WUPEN_Msk (0x1UL << I2C_CR1_WUPEN_Pos)
10358#define I2C_CR1_WUPEN I2C_CR1_WUPEN_Msk
10359#define I2C_CR1_GCEN_Pos (19U)
10360#define I2C_CR1_GCEN_Msk (0x1UL << I2C_CR1_GCEN_Pos)
10361#define I2C_CR1_GCEN I2C_CR1_GCEN_Msk
10362#define I2C_CR1_SMBHEN_Pos (20U)
10363#define I2C_CR1_SMBHEN_Msk (0x1UL << I2C_CR1_SMBHEN_Pos)
10364#define I2C_CR1_SMBHEN I2C_CR1_SMBHEN_Msk
10365#define I2C_CR1_SMBDEN_Pos (21U)
10366#define I2C_CR1_SMBDEN_Msk (0x1UL << I2C_CR1_SMBDEN_Pos)
10367#define I2C_CR1_SMBDEN I2C_CR1_SMBDEN_Msk
10368#define I2C_CR1_ALERTEN_Pos (22U)
10369#define I2C_CR1_ALERTEN_Msk (0x1UL << I2C_CR1_ALERTEN_Pos)
10370#define I2C_CR1_ALERTEN I2C_CR1_ALERTEN_Msk
10371#define I2C_CR1_PECEN_Pos (23U)
10372#define I2C_CR1_PECEN_Msk (0x1UL << I2C_CR1_PECEN_Pos)
10373#define I2C_CR1_PECEN I2C_CR1_PECEN_Msk
10375/* Legacy defines */
10376#define I2C_CR1_DFN I2C_CR1_DNF
10377
10378/****************** Bit definition for I2C_CR2 register ********************/
10379#define I2C_CR2_SADD_Pos (0U)
10380#define I2C_CR2_SADD_Msk (0x3FFUL << I2C_CR2_SADD_Pos)
10381#define I2C_CR2_SADD I2C_CR2_SADD_Msk
10382#define I2C_CR2_RD_WRN_Pos (10U)
10383#define I2C_CR2_RD_WRN_Msk (0x1UL << I2C_CR2_RD_WRN_Pos)
10384#define I2C_CR2_RD_WRN I2C_CR2_RD_WRN_Msk
10385#define I2C_CR2_ADD10_Pos (11U)
10386#define I2C_CR2_ADD10_Msk (0x1UL << I2C_CR2_ADD10_Pos)
10387#define I2C_CR2_ADD10 I2C_CR2_ADD10_Msk
10388#define I2C_CR2_HEAD10R_Pos (12U)
10389#define I2C_CR2_HEAD10R_Msk (0x1UL << I2C_CR2_HEAD10R_Pos)
10390#define I2C_CR2_HEAD10R I2C_CR2_HEAD10R_Msk
10391#define I2C_CR2_START_Pos (13U)
10392#define I2C_CR2_START_Msk (0x1UL << I2C_CR2_START_Pos)
10393#define I2C_CR2_START I2C_CR2_START_Msk
10394#define I2C_CR2_STOP_Pos (14U)
10395#define I2C_CR2_STOP_Msk (0x1UL << I2C_CR2_STOP_Pos)
10396#define I2C_CR2_STOP I2C_CR2_STOP_Msk
10397#define I2C_CR2_NACK_Pos (15U)
10398#define I2C_CR2_NACK_Msk (0x1UL << I2C_CR2_NACK_Pos)
10399#define I2C_CR2_NACK I2C_CR2_NACK_Msk
10400#define I2C_CR2_NBYTES_Pos (16U)
10401#define I2C_CR2_NBYTES_Msk (0xFFUL << I2C_CR2_NBYTES_Pos)
10402#define I2C_CR2_NBYTES I2C_CR2_NBYTES_Msk
10403#define I2C_CR2_RELOAD_Pos (24U)
10404#define I2C_CR2_RELOAD_Msk (0x1UL << I2C_CR2_RELOAD_Pos)
10405#define I2C_CR2_RELOAD I2C_CR2_RELOAD_Msk
10406#define I2C_CR2_AUTOEND_Pos (25U)
10407#define I2C_CR2_AUTOEND_Msk (0x1UL << I2C_CR2_AUTOEND_Pos)
10408#define I2C_CR2_AUTOEND I2C_CR2_AUTOEND_Msk
10409#define I2C_CR2_PECBYTE_Pos (26U)
10410#define I2C_CR2_PECBYTE_Msk (0x1UL << I2C_CR2_PECBYTE_Pos)
10411#define I2C_CR2_PECBYTE I2C_CR2_PECBYTE_Msk
10413/******************* Bit definition for I2C_OAR1 register ******************/
10414#define I2C_OAR1_OA1_Pos (0U)
10415#define I2C_OAR1_OA1_Msk (0x3FFUL << I2C_OAR1_OA1_Pos)
10416#define I2C_OAR1_OA1 I2C_OAR1_OA1_Msk
10417#define I2C_OAR1_OA1MODE_Pos (10U)
10418#define I2C_OAR1_OA1MODE_Msk (0x1UL << I2C_OAR1_OA1MODE_Pos)
10419#define I2C_OAR1_OA1MODE I2C_OAR1_OA1MODE_Msk
10420#define I2C_OAR1_OA1EN_Pos (15U)
10421#define I2C_OAR1_OA1EN_Msk (0x1UL << I2C_OAR1_OA1EN_Pos)
10422#define I2C_OAR1_OA1EN I2C_OAR1_OA1EN_Msk
10424/******************* Bit definition for I2C_OAR2 register *******************/
10425#define I2C_OAR2_OA2_Pos (1U)
10426#define I2C_OAR2_OA2_Msk (0x7FUL << I2C_OAR2_OA2_Pos)
10427#define I2C_OAR2_OA2 I2C_OAR2_OA2_Msk
10428#define I2C_OAR2_OA2MSK_Pos (8U)
10429#define I2C_OAR2_OA2MSK_Msk (0x7UL << I2C_OAR2_OA2MSK_Pos)
10430#define I2C_OAR2_OA2MSK I2C_OAR2_OA2MSK_Msk
10431#define I2C_OAR2_OA2NOMASK (0x00000000U)
10432#define I2C_OAR2_OA2MASK01_Pos (8U)
10433#define I2C_OAR2_OA2MASK01_Msk (0x1UL << I2C_OAR2_OA2MASK01_Pos)
10434#define I2C_OAR2_OA2MASK01 I2C_OAR2_OA2MASK01_Msk
10435#define I2C_OAR2_OA2MASK02_Pos (9U)
10436#define I2C_OAR2_OA2MASK02_Msk (0x1UL << I2C_OAR2_OA2MASK02_Pos)
10437#define I2C_OAR2_OA2MASK02 I2C_OAR2_OA2MASK02_Msk
10438#define I2C_OAR2_OA2MASK03_Pos (8U)
10439#define I2C_OAR2_OA2MASK03_Msk (0x3UL << I2C_OAR2_OA2MASK03_Pos)
10440#define I2C_OAR2_OA2MASK03 I2C_OAR2_OA2MASK03_Msk
10441#define I2C_OAR2_OA2MASK04_Pos (10U)
10442#define I2C_OAR2_OA2MASK04_Msk (0x1UL << I2C_OAR2_OA2MASK04_Pos)
10443#define I2C_OAR2_OA2MASK04 I2C_OAR2_OA2MASK04_Msk
10444#define I2C_OAR2_OA2MASK05_Pos (8U)
10445#define I2C_OAR2_OA2MASK05_Msk (0x5UL << I2C_OAR2_OA2MASK05_Pos)
10446#define I2C_OAR2_OA2MASK05 I2C_OAR2_OA2MASK05_Msk
10447#define I2C_OAR2_OA2MASK06_Pos (9U)
10448#define I2C_OAR2_OA2MASK06_Msk (0x3UL << I2C_OAR2_OA2MASK06_Pos)
10449#define I2C_OAR2_OA2MASK06 I2C_OAR2_OA2MASK06_Msk
10450#define I2C_OAR2_OA2MASK07_Pos (8U)
10451#define I2C_OAR2_OA2MASK07_Msk (0x7UL << I2C_OAR2_OA2MASK07_Pos)
10452#define I2C_OAR2_OA2MASK07 I2C_OAR2_OA2MASK07_Msk
10453#define I2C_OAR2_OA2EN_Pos (15U)
10454#define I2C_OAR2_OA2EN_Msk (0x1UL << I2C_OAR2_OA2EN_Pos)
10455#define I2C_OAR2_OA2EN I2C_OAR2_OA2EN_Msk
10457/******************* Bit definition for I2C_TIMINGR register *****************/
10458#define I2C_TIMINGR_SCLL_Pos (0U)
10459#define I2C_TIMINGR_SCLL_Msk (0xFFUL << I2C_TIMINGR_SCLL_Pos)
10460#define I2C_TIMINGR_SCLL I2C_TIMINGR_SCLL_Msk
10461#define I2C_TIMINGR_SCLH_Pos (8U)
10462#define I2C_TIMINGR_SCLH_Msk (0xFFUL << I2C_TIMINGR_SCLH_Pos)
10463#define I2C_TIMINGR_SCLH I2C_TIMINGR_SCLH_Msk
10464#define I2C_TIMINGR_SDADEL_Pos (16U)
10465#define I2C_TIMINGR_SDADEL_Msk (0xFUL << I2C_TIMINGR_SDADEL_Pos)
10466#define I2C_TIMINGR_SDADEL I2C_TIMINGR_SDADEL_Msk
10467#define I2C_TIMINGR_SCLDEL_Pos (20U)
10468#define I2C_TIMINGR_SCLDEL_Msk (0xFUL << I2C_TIMINGR_SCLDEL_Pos)
10469#define I2C_TIMINGR_SCLDEL I2C_TIMINGR_SCLDEL_Msk
10470#define I2C_TIMINGR_PRESC_Pos (28U)
10471#define I2C_TIMINGR_PRESC_Msk (0xFUL << I2C_TIMINGR_PRESC_Pos)
10472#define I2C_TIMINGR_PRESC I2C_TIMINGR_PRESC_Msk
10474/******************* Bit definition for I2C_TIMEOUTR register *****************/
10475#define I2C_TIMEOUTR_TIMEOUTA_Pos (0U)
10476#define I2C_TIMEOUTR_TIMEOUTA_Msk (0xFFFUL << I2C_TIMEOUTR_TIMEOUTA_Pos)
10477#define I2C_TIMEOUTR_TIMEOUTA I2C_TIMEOUTR_TIMEOUTA_Msk
10478#define I2C_TIMEOUTR_TIDLE_Pos (12U)
10479#define I2C_TIMEOUTR_TIDLE_Msk (0x1UL << I2C_TIMEOUTR_TIDLE_Pos)
10480#define I2C_TIMEOUTR_TIDLE I2C_TIMEOUTR_TIDLE_Msk
10481#define I2C_TIMEOUTR_TIMOUTEN_Pos (15U)
10482#define I2C_TIMEOUTR_TIMOUTEN_Msk (0x1UL << I2C_TIMEOUTR_TIMOUTEN_Pos)
10483#define I2C_TIMEOUTR_TIMOUTEN I2C_TIMEOUTR_TIMOUTEN_Msk
10484#define I2C_TIMEOUTR_TIMEOUTB_Pos (16U)
10485#define I2C_TIMEOUTR_TIMEOUTB_Msk (0xFFFUL << I2C_TIMEOUTR_TIMEOUTB_Pos)
10486#define I2C_TIMEOUTR_TIMEOUTB I2C_TIMEOUTR_TIMEOUTB_Msk
10487#define I2C_TIMEOUTR_TEXTEN_Pos (31U)
10488#define I2C_TIMEOUTR_TEXTEN_Msk (0x1UL << I2C_TIMEOUTR_TEXTEN_Pos)
10489#define I2C_TIMEOUTR_TEXTEN I2C_TIMEOUTR_TEXTEN_Msk
10491/****************** Bit definition for I2C_ISR register *********************/
10492#define I2C_ISR_TXE_Pos (0U)
10493#define I2C_ISR_TXE_Msk (0x1UL << I2C_ISR_TXE_Pos)
10494#define I2C_ISR_TXE I2C_ISR_TXE_Msk
10495#define I2C_ISR_TXIS_Pos (1U)
10496#define I2C_ISR_TXIS_Msk (0x1UL << I2C_ISR_TXIS_Pos)
10497#define I2C_ISR_TXIS I2C_ISR_TXIS_Msk
10498#define I2C_ISR_RXNE_Pos (2U)
10499#define I2C_ISR_RXNE_Msk (0x1UL << I2C_ISR_RXNE_Pos)
10500#define I2C_ISR_RXNE I2C_ISR_RXNE_Msk
10501#define I2C_ISR_ADDR_Pos (3U)
10502#define I2C_ISR_ADDR_Msk (0x1UL << I2C_ISR_ADDR_Pos)
10503#define I2C_ISR_ADDR I2C_ISR_ADDR_Msk
10504#define I2C_ISR_NACKF_Pos (4U)
10505#define I2C_ISR_NACKF_Msk (0x1UL << I2C_ISR_NACKF_Pos)
10506#define I2C_ISR_NACKF I2C_ISR_NACKF_Msk
10507#define I2C_ISR_STOPF_Pos (5U)
10508#define I2C_ISR_STOPF_Msk (0x1UL << I2C_ISR_STOPF_Pos)
10509#define I2C_ISR_STOPF I2C_ISR_STOPF_Msk
10510#define I2C_ISR_TC_Pos (6U)
10511#define I2C_ISR_TC_Msk (0x1UL << I2C_ISR_TC_Pos)
10512#define I2C_ISR_TC I2C_ISR_TC_Msk
10513#define I2C_ISR_TCR_Pos (7U)
10514#define I2C_ISR_TCR_Msk (0x1UL << I2C_ISR_TCR_Pos)
10515#define I2C_ISR_TCR I2C_ISR_TCR_Msk
10516#define I2C_ISR_BERR_Pos (8U)
10517#define I2C_ISR_BERR_Msk (0x1UL << I2C_ISR_BERR_Pos)
10518#define I2C_ISR_BERR I2C_ISR_BERR_Msk
10519#define I2C_ISR_ARLO_Pos (9U)
10520#define I2C_ISR_ARLO_Msk (0x1UL << I2C_ISR_ARLO_Pos)
10521#define I2C_ISR_ARLO I2C_ISR_ARLO_Msk
10522#define I2C_ISR_OVR_Pos (10U)
10523#define I2C_ISR_OVR_Msk (0x1UL << I2C_ISR_OVR_Pos)
10524#define I2C_ISR_OVR I2C_ISR_OVR_Msk
10525#define I2C_ISR_PECERR_Pos (11U)
10526#define I2C_ISR_PECERR_Msk (0x1UL << I2C_ISR_PECERR_Pos)
10527#define I2C_ISR_PECERR I2C_ISR_PECERR_Msk
10528#define I2C_ISR_TIMEOUT_Pos (12U)
10529#define I2C_ISR_TIMEOUT_Msk (0x1UL << I2C_ISR_TIMEOUT_Pos)
10530#define I2C_ISR_TIMEOUT I2C_ISR_TIMEOUT_Msk
10531#define I2C_ISR_ALERT_Pos (13U)
10532#define I2C_ISR_ALERT_Msk (0x1UL << I2C_ISR_ALERT_Pos)
10533#define I2C_ISR_ALERT I2C_ISR_ALERT_Msk
10534#define I2C_ISR_BUSY_Pos (15U)
10535#define I2C_ISR_BUSY_Msk (0x1UL << I2C_ISR_BUSY_Pos)
10536#define I2C_ISR_BUSY I2C_ISR_BUSY_Msk
10537#define I2C_ISR_DIR_Pos (16U)
10538#define I2C_ISR_DIR_Msk (0x1UL << I2C_ISR_DIR_Pos)
10539#define I2C_ISR_DIR I2C_ISR_DIR_Msk
10540#define I2C_ISR_ADDCODE_Pos (17U)
10541#define I2C_ISR_ADDCODE_Msk (0x7FUL << I2C_ISR_ADDCODE_Pos)
10542#define I2C_ISR_ADDCODE I2C_ISR_ADDCODE_Msk
10544/****************** Bit definition for I2C_ICR register *********************/
10545#define I2C_ICR_ADDRCF_Pos (3U)
10546#define I2C_ICR_ADDRCF_Msk (0x1UL << I2C_ICR_ADDRCF_Pos)
10547#define I2C_ICR_ADDRCF I2C_ICR_ADDRCF_Msk
10548#define I2C_ICR_NACKCF_Pos (4U)
10549#define I2C_ICR_NACKCF_Msk (0x1UL << I2C_ICR_NACKCF_Pos)
10550#define I2C_ICR_NACKCF I2C_ICR_NACKCF_Msk
10551#define I2C_ICR_STOPCF_Pos (5U)
10552#define I2C_ICR_STOPCF_Msk (0x1UL << I2C_ICR_STOPCF_Pos)
10553#define I2C_ICR_STOPCF I2C_ICR_STOPCF_Msk
10554#define I2C_ICR_BERRCF_Pos (8U)
10555#define I2C_ICR_BERRCF_Msk (0x1UL << I2C_ICR_BERRCF_Pos)
10556#define I2C_ICR_BERRCF I2C_ICR_BERRCF_Msk
10557#define I2C_ICR_ARLOCF_Pos (9U)
10558#define I2C_ICR_ARLOCF_Msk (0x1UL << I2C_ICR_ARLOCF_Pos)
10559#define I2C_ICR_ARLOCF I2C_ICR_ARLOCF_Msk
10560#define I2C_ICR_OVRCF_Pos (10U)
10561#define I2C_ICR_OVRCF_Msk (0x1UL << I2C_ICR_OVRCF_Pos)
10562#define I2C_ICR_OVRCF I2C_ICR_OVRCF_Msk
10563#define I2C_ICR_PECCF_Pos (11U)
10564#define I2C_ICR_PECCF_Msk (0x1UL << I2C_ICR_PECCF_Pos)
10565#define I2C_ICR_PECCF I2C_ICR_PECCF_Msk
10566#define I2C_ICR_TIMOUTCF_Pos (12U)
10567#define I2C_ICR_TIMOUTCF_Msk (0x1UL << I2C_ICR_TIMOUTCF_Pos)
10568#define I2C_ICR_TIMOUTCF I2C_ICR_TIMOUTCF_Msk
10569#define I2C_ICR_ALERTCF_Pos (13U)
10570#define I2C_ICR_ALERTCF_Msk (0x1UL << I2C_ICR_ALERTCF_Pos)
10571#define I2C_ICR_ALERTCF I2C_ICR_ALERTCF_Msk
10573/****************** Bit definition for I2C_PECR register ********************/
10574#define I2C_PECR_PEC_Pos (0U)
10575#define I2C_PECR_PEC_Msk (0xFFUL << I2C_PECR_PEC_Pos)
10576#define I2C_PECR_PEC I2C_PECR_PEC_Msk
10578/****************** Bit definition for I2C_RXDR register *********************/
10579#define I2C_RXDR_RXDATA_Pos (0U)
10580#define I2C_RXDR_RXDATA_Msk (0xFFUL << I2C_RXDR_RXDATA_Pos)
10581#define I2C_RXDR_RXDATA I2C_RXDR_RXDATA_Msk
10583/****************** Bit definition for I2C_TXDR register *********************/
10584#define I2C_TXDR_TXDATA_Pos (0U)
10585#define I2C_TXDR_TXDATA_Msk (0xFFUL << I2C_TXDR_TXDATA_Pos)
10586#define I2C_TXDR_TXDATA I2C_TXDR_TXDATA_Msk
10589/******************************************************************************/
10590/* */
10591/* Independent WATCHDOG (IWDG) */
10592/* */
10593/******************************************************************************/
10594/******************* Bit definition for IWDG_KR register ********************/
10595#define IWDG_KR_KEY_Pos (0U)
10596#define IWDG_KR_KEY_Msk (0xFFFFUL << IWDG_KR_KEY_Pos)
10597#define IWDG_KR_KEY IWDG_KR_KEY_Msk
10599/******************* Bit definition for IWDG_PR register ********************/
10600#define IWDG_PR_PR_Pos (0U)
10601#define IWDG_PR_PR_Msk (0x7UL << IWDG_PR_PR_Pos)
10602#define IWDG_PR_PR IWDG_PR_PR_Msk
10603#define IWDG_PR_PR_0 (0x1UL << IWDG_PR_PR_Pos)
10604#define IWDG_PR_PR_1 (0x2UL << IWDG_PR_PR_Pos)
10605#define IWDG_PR_PR_2 (0x4UL << IWDG_PR_PR_Pos)
10607/******************* Bit definition for IWDG_RLR register *******************/
10608#define IWDG_RLR_RL_Pos (0U)
10609#define IWDG_RLR_RL_Msk (0xFFFUL << IWDG_RLR_RL_Pos)
10610#define IWDG_RLR_RL IWDG_RLR_RL_Msk
10612/******************* Bit definition for IWDG_SR register ********************/
10613#define IWDG_SR_PVU_Pos (0U)
10614#define IWDG_SR_PVU_Msk (0x1UL << IWDG_SR_PVU_Pos)
10615#define IWDG_SR_PVU IWDG_SR_PVU_Msk
10616#define IWDG_SR_RVU_Pos (1U)
10617#define IWDG_SR_RVU_Msk (0x1UL << IWDG_SR_RVU_Pos)
10618#define IWDG_SR_RVU IWDG_SR_RVU_Msk
10619#define IWDG_SR_WVU_Pos (2U)
10620#define IWDG_SR_WVU_Msk (0x1UL << IWDG_SR_WVU_Pos)
10621#define IWDG_SR_WVU IWDG_SR_WVU_Msk
10623/******************* Bit definition for IWDG_KR register ********************/
10624#define IWDG_WINR_WIN_Pos (0U)
10625#define IWDG_WINR_WIN_Msk (0xFFFUL << IWDG_WINR_WIN_Pos)
10626#define IWDG_WINR_WIN IWDG_WINR_WIN_Msk
10628/******************************************************************************/
10629/* */
10630/* Power Control */
10631/* */
10632/******************************************************************************/
10633#define PWR_PVD_SUPPORT
10634/******************** Bit definition for PWR_CR register ********************/
10635#define PWR_CR_LPDS_Pos (0U)
10636#define PWR_CR_LPDS_Msk (0x1UL << PWR_CR_LPDS_Pos)
10637#define PWR_CR_LPDS PWR_CR_LPDS_Msk
10638#define PWR_CR_PDDS_Pos (1U)
10639#define PWR_CR_PDDS_Msk (0x1UL << PWR_CR_PDDS_Pos)
10640#define PWR_CR_PDDS PWR_CR_PDDS_Msk
10641#define PWR_CR_CWUF_Pos (2U)
10642#define PWR_CR_CWUF_Msk (0x1UL << PWR_CR_CWUF_Pos)
10643#define PWR_CR_CWUF PWR_CR_CWUF_Msk
10644#define PWR_CR_CSBF_Pos (3U)
10645#define PWR_CR_CSBF_Msk (0x1UL << PWR_CR_CSBF_Pos)
10646#define PWR_CR_CSBF PWR_CR_CSBF_Msk
10647#define PWR_CR_PVDE_Pos (4U)
10648#define PWR_CR_PVDE_Msk (0x1UL << PWR_CR_PVDE_Pos)
10649#define PWR_CR_PVDE PWR_CR_PVDE_Msk
10651#define PWR_CR_PLS_Pos (5U)
10652#define PWR_CR_PLS_Msk (0x7UL << PWR_CR_PLS_Pos)
10653#define PWR_CR_PLS PWR_CR_PLS_Msk
10654#define PWR_CR_PLS_0 (0x1UL << PWR_CR_PLS_Pos)
10655#define PWR_CR_PLS_1 (0x2UL << PWR_CR_PLS_Pos)
10656#define PWR_CR_PLS_2 (0x4UL << PWR_CR_PLS_Pos)
10659#define PWR_CR_PLS_LEV0 (0x00000000U)
10660#define PWR_CR_PLS_LEV1 (0x00000020U)
10661#define PWR_CR_PLS_LEV2 (0x00000040U)
10662#define PWR_CR_PLS_LEV3 (0x00000060U)
10663#define PWR_CR_PLS_LEV4 (0x00000080U)
10664#define PWR_CR_PLS_LEV5 (0x000000A0U)
10665#define PWR_CR_PLS_LEV6 (0x000000C0U)
10666#define PWR_CR_PLS_LEV7 (0x000000E0U)
10668#define PWR_CR_DBP_Pos (8U)
10669#define PWR_CR_DBP_Msk (0x1UL << PWR_CR_DBP_Pos)
10670#define PWR_CR_DBP PWR_CR_DBP_Msk
10672/******************* Bit definition for PWR_CSR register ********************/
10673#define PWR_CSR_WUF_Pos (0U)
10674#define PWR_CSR_WUF_Msk (0x1UL << PWR_CSR_WUF_Pos)
10675#define PWR_CSR_WUF PWR_CSR_WUF_Msk
10676#define PWR_CSR_SBF_Pos (1U)
10677#define PWR_CSR_SBF_Msk (0x1UL << PWR_CSR_SBF_Pos)
10678#define PWR_CSR_SBF PWR_CSR_SBF_Msk
10679#define PWR_CSR_PVDO_Pos (2U)
10680#define PWR_CSR_PVDO_Msk (0x1UL << PWR_CSR_PVDO_Pos)
10681#define PWR_CSR_PVDO PWR_CSR_PVDO_Msk
10682#define PWR_CSR_VREFINTRDYF_Pos (3U)
10683#define PWR_CSR_VREFINTRDYF_Msk (0x1UL << PWR_CSR_VREFINTRDYF_Pos)
10684#define PWR_CSR_VREFINTRDYF PWR_CSR_VREFINTRDYF_Msk
10686#define PWR_CSR_EWUP1_Pos (8U)
10687#define PWR_CSR_EWUP1_Msk (0x1UL << PWR_CSR_EWUP1_Pos)
10688#define PWR_CSR_EWUP1 PWR_CSR_EWUP1_Msk
10689#define PWR_CSR_EWUP2_Pos (9U)
10690#define PWR_CSR_EWUP2_Msk (0x1UL << PWR_CSR_EWUP2_Pos)
10691#define PWR_CSR_EWUP2 PWR_CSR_EWUP2_Msk
10692#define PWR_CSR_EWUP3_Pos (10U)
10693#define PWR_CSR_EWUP3_Msk (0x1UL << PWR_CSR_EWUP3_Pos)
10694#define PWR_CSR_EWUP3 PWR_CSR_EWUP3_Msk
10696/******************************************************************************/
10697/* */
10698/* Reset and Clock Control */
10699/* */
10700/******************************************************************************/
10701/*
10702* @brief Specific device feature definitions (not present on all devices in the STM32F3 series)
10703*/
10704#define RCC_PLLSRC_PREDIV1_SUPPORT
10706/******************** Bit definition for RCC_CR register ********************/
10707#define RCC_CR_HSION_Pos (0U)
10708#define RCC_CR_HSION_Msk (0x1UL << RCC_CR_HSION_Pos)
10709#define RCC_CR_HSION RCC_CR_HSION_Msk
10710#define RCC_CR_HSIRDY_Pos (1U)
10711#define RCC_CR_HSIRDY_Msk (0x1UL << RCC_CR_HSIRDY_Pos)
10712#define RCC_CR_HSIRDY RCC_CR_HSIRDY_Msk
10713
10714#define RCC_CR_HSITRIM_Pos (3U)
10715#define RCC_CR_HSITRIM_Msk (0x1FUL << RCC_CR_HSITRIM_Pos)
10716#define RCC_CR_HSITRIM RCC_CR_HSITRIM_Msk
10717#define RCC_CR_HSITRIM_0 (0x01UL << RCC_CR_HSITRIM_Pos)
10718#define RCC_CR_HSITRIM_1 (0x02UL << RCC_CR_HSITRIM_Pos)
10719#define RCC_CR_HSITRIM_2 (0x04UL << RCC_CR_HSITRIM_Pos)
10720#define RCC_CR_HSITRIM_3 (0x08UL << RCC_CR_HSITRIM_Pos)
10721#define RCC_CR_HSITRIM_4 (0x10UL << RCC_CR_HSITRIM_Pos)
10723#define RCC_CR_HSICAL_Pos (8U)
10724#define RCC_CR_HSICAL_Msk (0xFFUL << RCC_CR_HSICAL_Pos)
10725#define RCC_CR_HSICAL RCC_CR_HSICAL_Msk
10726#define RCC_CR_HSICAL_0 (0x01UL << RCC_CR_HSICAL_Pos)
10727#define RCC_CR_HSICAL_1 (0x02UL << RCC_CR_HSICAL_Pos)
10728#define RCC_CR_HSICAL_2 (0x04UL << RCC_CR_HSICAL_Pos)
10729#define RCC_CR_HSICAL_3 (0x08UL << RCC_CR_HSICAL_Pos)
10730#define RCC_CR_HSICAL_4 (0x10UL << RCC_CR_HSICAL_Pos)
10731#define RCC_CR_HSICAL_5 (0x20UL << RCC_CR_HSICAL_Pos)
10732#define RCC_CR_HSICAL_6 (0x40UL << RCC_CR_HSICAL_Pos)
10733#define RCC_CR_HSICAL_7 (0x80UL << RCC_CR_HSICAL_Pos)
10735#define RCC_CR_HSEON_Pos (16U)
10736#define RCC_CR_HSEON_Msk (0x1UL << RCC_CR_HSEON_Pos)
10737#define RCC_CR_HSEON RCC_CR_HSEON_Msk
10738#define RCC_CR_HSERDY_Pos (17U)
10739#define RCC_CR_HSERDY_Msk (0x1UL << RCC_CR_HSERDY_Pos)
10740#define RCC_CR_HSERDY RCC_CR_HSERDY_Msk
10741#define RCC_CR_HSEBYP_Pos (18U)
10742#define RCC_CR_HSEBYP_Msk (0x1UL << RCC_CR_HSEBYP_Pos)
10743#define RCC_CR_HSEBYP RCC_CR_HSEBYP_Msk
10744#define RCC_CR_CSSON_Pos (19U)
10745#define RCC_CR_CSSON_Msk (0x1UL << RCC_CR_CSSON_Pos)
10746#define RCC_CR_CSSON RCC_CR_CSSON_Msk
10747#define RCC_CR_PLLON_Pos (24U)
10748#define RCC_CR_PLLON_Msk (0x1UL << RCC_CR_PLLON_Pos)
10749#define RCC_CR_PLLON RCC_CR_PLLON_Msk
10750#define RCC_CR_PLLRDY_Pos (25U)
10751#define RCC_CR_PLLRDY_Msk (0x1UL << RCC_CR_PLLRDY_Pos)
10752#define RCC_CR_PLLRDY RCC_CR_PLLRDY_Msk
10753
10754/******************** Bit definition for RCC_CFGR register ******************/
10756#define RCC_CFGR_SW_Pos (0U)
10757#define RCC_CFGR_SW_Msk (0x3UL << RCC_CFGR_SW_Pos)
10758#define RCC_CFGR_SW RCC_CFGR_SW_Msk
10759#define RCC_CFGR_SW_0 (0x1UL << RCC_CFGR_SW_Pos)
10760#define RCC_CFGR_SW_1 (0x2UL << RCC_CFGR_SW_Pos)
10762#define RCC_CFGR_SW_HSI (0x00000000U)
10763#define RCC_CFGR_SW_HSE (0x00000001U)
10764#define RCC_CFGR_SW_PLL (0x00000002U)
10767#define RCC_CFGR_SWS_Pos (2U)
10768#define RCC_CFGR_SWS_Msk (0x3UL << RCC_CFGR_SWS_Pos)
10769#define RCC_CFGR_SWS RCC_CFGR_SWS_Msk
10770#define RCC_CFGR_SWS_0 (0x1UL << RCC_CFGR_SWS_Pos)
10771#define RCC_CFGR_SWS_1 (0x2UL << RCC_CFGR_SWS_Pos)
10773#define RCC_CFGR_SWS_HSI (0x00000000U)
10774#define RCC_CFGR_SWS_HSE (0x00000004U)
10775#define RCC_CFGR_SWS_PLL (0x00000008U)
10778#define RCC_CFGR_HPRE_Pos (4U)
10779#define RCC_CFGR_HPRE_Msk (0xFUL << RCC_CFGR_HPRE_Pos)
10780#define RCC_CFGR_HPRE RCC_CFGR_HPRE_Msk
10781#define RCC_CFGR_HPRE_0 (0x1UL << RCC_CFGR_HPRE_Pos)
10782#define RCC_CFGR_HPRE_1 (0x2UL << RCC_CFGR_HPRE_Pos)
10783#define RCC_CFGR_HPRE_2 (0x4UL << RCC_CFGR_HPRE_Pos)
10784#define RCC_CFGR_HPRE_3 (0x8UL << RCC_CFGR_HPRE_Pos)
10786#define RCC_CFGR_HPRE_DIV1 (0x00000000U)
10787#define RCC_CFGR_HPRE_DIV2 (0x00000080U)
10788#define RCC_CFGR_HPRE_DIV4 (0x00000090U)
10789#define RCC_CFGR_HPRE_DIV8 (0x000000A0U)
10790#define RCC_CFGR_HPRE_DIV16 (0x000000B0U)
10791#define RCC_CFGR_HPRE_DIV64 (0x000000C0U)
10792#define RCC_CFGR_HPRE_DIV128 (0x000000D0U)
10793#define RCC_CFGR_HPRE_DIV256 (0x000000E0U)
10794#define RCC_CFGR_HPRE_DIV512 (0x000000F0U)
10797#define RCC_CFGR_PPRE1_Pos (8U)
10798#define RCC_CFGR_PPRE1_Msk (0x7UL << RCC_CFGR_PPRE1_Pos)
10799#define RCC_CFGR_PPRE1 RCC_CFGR_PPRE1_Msk
10800#define RCC_CFGR_PPRE1_0 (0x1UL << RCC_CFGR_PPRE1_Pos)
10801#define RCC_CFGR_PPRE1_1 (0x2UL << RCC_CFGR_PPRE1_Pos)
10802#define RCC_CFGR_PPRE1_2 (0x4UL << RCC_CFGR_PPRE1_Pos)
10804#define RCC_CFGR_PPRE1_DIV1 (0x00000000U)
10805#define RCC_CFGR_PPRE1_DIV2 (0x00000400U)
10806#define RCC_CFGR_PPRE1_DIV4 (0x00000500U)
10807#define RCC_CFGR_PPRE1_DIV8 (0x00000600U)
10808#define RCC_CFGR_PPRE1_DIV16 (0x00000700U)
10811#define RCC_CFGR_PPRE2_Pos (11U)
10812#define RCC_CFGR_PPRE2_Msk (0x7UL << RCC_CFGR_PPRE2_Pos)
10813#define RCC_CFGR_PPRE2 RCC_CFGR_PPRE2_Msk
10814#define RCC_CFGR_PPRE2_0 (0x1UL << RCC_CFGR_PPRE2_Pos)
10815#define RCC_CFGR_PPRE2_1 (0x2UL << RCC_CFGR_PPRE2_Pos)
10816#define RCC_CFGR_PPRE2_2 (0x4UL << RCC_CFGR_PPRE2_Pos)
10818#define RCC_CFGR_PPRE2_DIV1 (0x00000000U)
10819#define RCC_CFGR_PPRE2_DIV2 (0x00002000U)
10820#define RCC_CFGR_PPRE2_DIV4 (0x00002800U)
10821#define RCC_CFGR_PPRE2_DIV8 (0x00003000U)
10822#define RCC_CFGR_PPRE2_DIV16 (0x00003800U)
10824#define RCC_CFGR_PLLSRC_Pos (15U)
10825#define RCC_CFGR_PLLSRC_Msk (0x3UL << RCC_CFGR_PLLSRC_Pos)
10826#define RCC_CFGR_PLLSRC RCC_CFGR_PLLSRC_Msk
10827#define RCC_CFGR_PLLSRC_HSI_PREDIV (0x00008000U)
10828#define RCC_CFGR_PLLSRC_HSE_PREDIV (0x00010000U)
10830#define RCC_CFGR_PLLXTPRE_Pos (17U)
10831#define RCC_CFGR_PLLXTPRE_Msk (0x1UL << RCC_CFGR_PLLXTPRE_Pos)
10832#define RCC_CFGR_PLLXTPRE RCC_CFGR_PLLXTPRE_Msk
10833#define RCC_CFGR_PLLXTPRE_HSE_PREDIV_DIV1 (0x00000000U)
10834#define RCC_CFGR_PLLXTPRE_HSE_PREDIV_DIV2 (0x00020000U)
10837#define RCC_CFGR_PLLMUL_Pos (18U)
10838#define RCC_CFGR_PLLMUL_Msk (0xFUL << RCC_CFGR_PLLMUL_Pos)
10839#define RCC_CFGR_PLLMUL RCC_CFGR_PLLMUL_Msk
10840#define RCC_CFGR_PLLMUL_0 (0x1UL << RCC_CFGR_PLLMUL_Pos)
10841#define RCC_CFGR_PLLMUL_1 (0x2UL << RCC_CFGR_PLLMUL_Pos)
10842#define RCC_CFGR_PLLMUL_2 (0x4UL << RCC_CFGR_PLLMUL_Pos)
10843#define RCC_CFGR_PLLMUL_3 (0x8UL << RCC_CFGR_PLLMUL_Pos)
10845#define RCC_CFGR_PLLMUL2 (0x00000000U)
10846#define RCC_CFGR_PLLMUL3 (0x00040000U)
10847#define RCC_CFGR_PLLMUL4 (0x00080000U)
10848#define RCC_CFGR_PLLMUL5 (0x000C0000U)
10849#define RCC_CFGR_PLLMUL6 (0x00100000U)
10850#define RCC_CFGR_PLLMUL7 (0x00140000U)
10851#define RCC_CFGR_PLLMUL8 (0x00180000U)
10852#define RCC_CFGR_PLLMUL9 (0x001C0000U)
10853#define RCC_CFGR_PLLMUL10 (0x00200000U)
10854#define RCC_CFGR_PLLMUL11 (0x00240000U)
10855#define RCC_CFGR_PLLMUL12 (0x00280000U)
10856#define RCC_CFGR_PLLMUL13 (0x002C0000U)
10857#define RCC_CFGR_PLLMUL14 (0x00300000U)
10858#define RCC_CFGR_PLLMUL15 (0x00340000U)
10859#define RCC_CFGR_PLLMUL16 (0x00380000U)
10862#define RCC_CFGR_USBPRE_Pos (22U)
10863#define RCC_CFGR_USBPRE_Msk (0x1UL << RCC_CFGR_USBPRE_Pos)
10864#define RCC_CFGR_USBPRE RCC_CFGR_USBPRE_Msk
10866#define RCC_CFGR_USBPRE_DIV1_5 (0x00000000U)
10867#define RCC_CFGR_USBPRE_DIV1 (0x00400000U)
10870#define RCC_CFGR_I2SSRC_Pos (23U)
10871#define RCC_CFGR_I2SSRC_Msk (0x1UL << RCC_CFGR_I2SSRC_Pos)
10872#define RCC_CFGR_I2SSRC RCC_CFGR_I2SSRC_Msk
10874#define RCC_CFGR_I2SSRC_SYSCLK (0x00000000U)
10875#define RCC_CFGR_I2SSRC_EXT (0x00800000U)
10878#define RCC_CFGR_MCO_Pos (24U)
10879#define RCC_CFGR_MCO_Msk (0x7UL << RCC_CFGR_MCO_Pos)
10880#define RCC_CFGR_MCO RCC_CFGR_MCO_Msk
10881#define RCC_CFGR_MCO_0 (0x1UL << RCC_CFGR_MCO_Pos)
10882#define RCC_CFGR_MCO_1 (0x2UL << RCC_CFGR_MCO_Pos)
10883#define RCC_CFGR_MCO_2 (0x4UL << RCC_CFGR_MCO_Pos)
10885#define RCC_CFGR_MCO_NOCLOCK (0x00000000U)
10886#define RCC_CFGR_MCO_LSI (0x02000000U)
10887#define RCC_CFGR_MCO_LSE (0x03000000U)
10888#define RCC_CFGR_MCO_SYSCLK (0x04000000U)
10889#define RCC_CFGR_MCO_HSI (0x05000000U)
10890#define RCC_CFGR_MCO_HSE (0x06000000U)
10891#define RCC_CFGR_MCO_PLL (0x07000000U)
10893#define RCC_CFGR_MCOPRE_Pos (28U)
10894#define RCC_CFGR_MCOPRE_Msk (0x7UL << RCC_CFGR_MCOPRE_Pos)
10895#define RCC_CFGR_MCOPRE RCC_CFGR_MCOPRE_Msk
10896#define RCC_CFGR_MCOPRE_0 (0x1UL << RCC_CFGR_MCOPRE_Pos)
10897#define RCC_CFGR_MCOPRE_1 (0x2UL << RCC_CFGR_MCOPRE_Pos)
10898#define RCC_CFGR_MCOPRE_2 (0x4UL << RCC_CFGR_MCOPRE_Pos)
10900#define RCC_CFGR_MCOPRE_DIV1 (0x00000000U)
10901#define RCC_CFGR_MCOPRE_DIV2 (0x10000000U)
10902#define RCC_CFGR_MCOPRE_DIV4 (0x20000000U)
10903#define RCC_CFGR_MCOPRE_DIV8 (0x30000000U)
10904#define RCC_CFGR_MCOPRE_DIV16 (0x40000000U)
10905#define RCC_CFGR_MCOPRE_DIV32 (0x50000000U)
10906#define RCC_CFGR_MCOPRE_DIV64 (0x60000000U)
10907#define RCC_CFGR_MCOPRE_DIV128 (0x70000000U)
10909#define RCC_CFGR_PLLNODIV_Pos (31U)
10910#define RCC_CFGR_PLLNODIV_Msk (0x1UL << RCC_CFGR_PLLNODIV_Pos)
10911#define RCC_CFGR_PLLNODIV RCC_CFGR_PLLNODIV_Msk
10913/* Reference defines */
10914#define RCC_CFGR_MCOSEL RCC_CFGR_MCO
10915#define RCC_CFGR_MCOSEL_0 RCC_CFGR_MCO_0
10916#define RCC_CFGR_MCOSEL_1 RCC_CFGR_MCO_1
10917#define RCC_CFGR_MCOSEL_2 RCC_CFGR_MCO_2
10918#define RCC_CFGR_MCOSEL_NOCLOCK RCC_CFGR_MCO_NOCLOCK
10919#define RCC_CFGR_MCOSEL_LSI RCC_CFGR_MCO_LSI
10920#define RCC_CFGR_MCOSEL_LSE RCC_CFGR_MCO_LSE
10921#define RCC_CFGR_MCOSEL_SYSCLK RCC_CFGR_MCO_SYSCLK
10922#define RCC_CFGR_MCOSEL_HSI RCC_CFGR_MCO_HSI
10923#define RCC_CFGR_MCOSEL_HSE RCC_CFGR_MCO_HSE
10924#define RCC_CFGR_MCOSEL_PLL_DIV2 RCC_CFGR_MCO_PLL
10925
10926/********************* Bit definition for RCC_CIR register ********************/
10927#define RCC_CIR_LSIRDYF_Pos (0U)
10928#define RCC_CIR_LSIRDYF_Msk (0x1UL << RCC_CIR_LSIRDYF_Pos)
10929#define RCC_CIR_LSIRDYF RCC_CIR_LSIRDYF_Msk
10930#define RCC_CIR_LSERDYF_Pos (1U)
10931#define RCC_CIR_LSERDYF_Msk (0x1UL << RCC_CIR_LSERDYF_Pos)
10932#define RCC_CIR_LSERDYF RCC_CIR_LSERDYF_Msk
10933#define RCC_CIR_HSIRDYF_Pos (2U)
10934#define RCC_CIR_HSIRDYF_Msk (0x1UL << RCC_CIR_HSIRDYF_Pos)
10935#define RCC_CIR_HSIRDYF RCC_CIR_HSIRDYF_Msk
10936#define RCC_CIR_HSERDYF_Pos (3U)
10937#define RCC_CIR_HSERDYF_Msk (0x1UL << RCC_CIR_HSERDYF_Pos)
10938#define RCC_CIR_HSERDYF RCC_CIR_HSERDYF_Msk
10939#define RCC_CIR_PLLRDYF_Pos (4U)
10940#define RCC_CIR_PLLRDYF_Msk (0x1UL << RCC_CIR_PLLRDYF_Pos)
10941#define RCC_CIR_PLLRDYF RCC_CIR_PLLRDYF_Msk
10942#define RCC_CIR_CSSF_Pos (7U)
10943#define RCC_CIR_CSSF_Msk (0x1UL << RCC_CIR_CSSF_Pos)
10944#define RCC_CIR_CSSF RCC_CIR_CSSF_Msk
10945#define RCC_CIR_LSIRDYIE_Pos (8U)
10946#define RCC_CIR_LSIRDYIE_Msk (0x1UL << RCC_CIR_LSIRDYIE_Pos)
10947#define RCC_CIR_LSIRDYIE RCC_CIR_LSIRDYIE_Msk
10948#define RCC_CIR_LSERDYIE_Pos (9U)
10949#define RCC_CIR_LSERDYIE_Msk (0x1UL << RCC_CIR_LSERDYIE_Pos)
10950#define RCC_CIR_LSERDYIE RCC_CIR_LSERDYIE_Msk
10951#define RCC_CIR_HSIRDYIE_Pos (10U)
10952#define RCC_CIR_HSIRDYIE_Msk (0x1UL << RCC_CIR_HSIRDYIE_Pos)
10953#define RCC_CIR_HSIRDYIE RCC_CIR_HSIRDYIE_Msk
10954#define RCC_CIR_HSERDYIE_Pos (11U)
10955#define RCC_CIR_HSERDYIE_Msk (0x1UL << RCC_CIR_HSERDYIE_Pos)
10956#define RCC_CIR_HSERDYIE RCC_CIR_HSERDYIE_Msk
10957#define RCC_CIR_PLLRDYIE_Pos (12U)
10958#define RCC_CIR_PLLRDYIE_Msk (0x1UL << RCC_CIR_PLLRDYIE_Pos)
10959#define RCC_CIR_PLLRDYIE RCC_CIR_PLLRDYIE_Msk
10960#define RCC_CIR_LSIRDYC_Pos (16U)
10961#define RCC_CIR_LSIRDYC_Msk (0x1UL << RCC_CIR_LSIRDYC_Pos)
10962#define RCC_CIR_LSIRDYC RCC_CIR_LSIRDYC_Msk
10963#define RCC_CIR_LSERDYC_Pos (17U)
10964#define RCC_CIR_LSERDYC_Msk (0x1UL << RCC_CIR_LSERDYC_Pos)
10965#define RCC_CIR_LSERDYC RCC_CIR_LSERDYC_Msk
10966#define RCC_CIR_HSIRDYC_Pos (18U)
10967#define RCC_CIR_HSIRDYC_Msk (0x1UL << RCC_CIR_HSIRDYC_Pos)
10968#define RCC_CIR_HSIRDYC RCC_CIR_HSIRDYC_Msk
10969#define RCC_CIR_HSERDYC_Pos (19U)
10970#define RCC_CIR_HSERDYC_Msk (0x1UL << RCC_CIR_HSERDYC_Pos)
10971#define RCC_CIR_HSERDYC RCC_CIR_HSERDYC_Msk
10972#define RCC_CIR_PLLRDYC_Pos (20U)
10973#define RCC_CIR_PLLRDYC_Msk (0x1UL << RCC_CIR_PLLRDYC_Pos)
10974#define RCC_CIR_PLLRDYC RCC_CIR_PLLRDYC_Msk
10975#define RCC_CIR_CSSC_Pos (23U)
10976#define RCC_CIR_CSSC_Msk (0x1UL << RCC_CIR_CSSC_Pos)
10977#define RCC_CIR_CSSC RCC_CIR_CSSC_Msk
10979/****************** Bit definition for RCC_APB2RSTR register *****************/
10980#define RCC_APB2RSTR_SYSCFGRST_Pos (0U)
10981#define RCC_APB2RSTR_SYSCFGRST_Msk (0x1UL << RCC_APB2RSTR_SYSCFGRST_Pos)
10982#define RCC_APB2RSTR_SYSCFGRST RCC_APB2RSTR_SYSCFGRST_Msk
10983#define RCC_APB2RSTR_TIM1RST_Pos (11U)
10984#define RCC_APB2RSTR_TIM1RST_Msk (0x1UL << RCC_APB2RSTR_TIM1RST_Pos)
10985#define RCC_APB2RSTR_TIM1RST RCC_APB2RSTR_TIM1RST_Msk
10986#define RCC_APB2RSTR_SPI1RST_Pos (12U)
10987#define RCC_APB2RSTR_SPI1RST_Msk (0x1UL << RCC_APB2RSTR_SPI1RST_Pos)
10988#define RCC_APB2RSTR_SPI1RST RCC_APB2RSTR_SPI1RST_Msk
10989#define RCC_APB2RSTR_TIM8RST_Pos (13U)
10990#define RCC_APB2RSTR_TIM8RST_Msk (0x1UL << RCC_APB2RSTR_TIM8RST_Pos)
10991#define RCC_APB2RSTR_TIM8RST RCC_APB2RSTR_TIM8RST_Msk
10992#define RCC_APB2RSTR_USART1RST_Pos (14U)
10993#define RCC_APB2RSTR_USART1RST_Msk (0x1UL << RCC_APB2RSTR_USART1RST_Pos)
10994#define RCC_APB2RSTR_USART1RST RCC_APB2RSTR_USART1RST_Msk
10995#define RCC_APB2RSTR_SPI4RST_Pos (15U)
10996#define RCC_APB2RSTR_SPI4RST_Msk (0x1UL << RCC_APB2RSTR_SPI4RST_Pos)
10997#define RCC_APB2RSTR_SPI4RST RCC_APB2RSTR_SPI4RST_Msk
10998#define RCC_APB2RSTR_TIM15RST_Pos (16U)
10999#define RCC_APB2RSTR_TIM15RST_Msk (0x1UL << RCC_APB2RSTR_TIM15RST_Pos)
11000#define RCC_APB2RSTR_TIM15RST RCC_APB2RSTR_TIM15RST_Msk
11001#define RCC_APB2RSTR_TIM16RST_Pos (17U)
11002#define RCC_APB2RSTR_TIM16RST_Msk (0x1UL << RCC_APB2RSTR_TIM16RST_Pos)
11003#define RCC_APB2RSTR_TIM16RST RCC_APB2RSTR_TIM16RST_Msk
11004#define RCC_APB2RSTR_TIM17RST_Pos (18U)
11005#define RCC_APB2RSTR_TIM17RST_Msk (0x1UL << RCC_APB2RSTR_TIM17RST_Pos)
11006#define RCC_APB2RSTR_TIM17RST RCC_APB2RSTR_TIM17RST_Msk
11007#define RCC_APB2RSTR_TIM20RST_Pos (20U)
11008#define RCC_APB2RSTR_TIM20RST_Msk (0x1UL << RCC_APB2RSTR_TIM20RST_Pos)
11009#define RCC_APB2RSTR_TIM20RST RCC_APB2RSTR_TIM20RST_Msk
11011/****************** Bit definition for RCC_APB1RSTR register ******************/
11012#define RCC_APB1RSTR_TIM2RST_Pos (0U)
11013#define RCC_APB1RSTR_TIM2RST_Msk (0x1UL << RCC_APB1RSTR_TIM2RST_Pos)
11014#define RCC_APB1RSTR_TIM2RST RCC_APB1RSTR_TIM2RST_Msk
11015#define RCC_APB1RSTR_TIM3RST_Pos (1U)
11016#define RCC_APB1RSTR_TIM3RST_Msk (0x1UL << RCC_APB1RSTR_TIM3RST_Pos)
11017#define RCC_APB1RSTR_TIM3RST RCC_APB1RSTR_TIM3RST_Msk
11018#define RCC_APB1RSTR_TIM4RST_Pos (2U)
11019#define RCC_APB1RSTR_TIM4RST_Msk (0x1UL << RCC_APB1RSTR_TIM4RST_Pos)
11020#define RCC_APB1RSTR_TIM4RST RCC_APB1RSTR_TIM4RST_Msk
11021#define RCC_APB1RSTR_TIM6RST_Pos (4U)
11022#define RCC_APB1RSTR_TIM6RST_Msk (0x1UL << RCC_APB1RSTR_TIM6RST_Pos)
11023#define RCC_APB1RSTR_TIM6RST RCC_APB1RSTR_TIM6RST_Msk
11024#define RCC_APB1RSTR_TIM7RST_Pos (5U)
11025#define RCC_APB1RSTR_TIM7RST_Msk (0x1UL << RCC_APB1RSTR_TIM7RST_Pos)
11026#define RCC_APB1RSTR_TIM7RST RCC_APB1RSTR_TIM7RST_Msk
11027#define RCC_APB1RSTR_WWDGRST_Pos (11U)
11028#define RCC_APB1RSTR_WWDGRST_Msk (0x1UL << RCC_APB1RSTR_WWDGRST_Pos)
11029#define RCC_APB1RSTR_WWDGRST RCC_APB1RSTR_WWDGRST_Msk
11030#define RCC_APB1RSTR_SPI2RST_Pos (14U)
11031#define RCC_APB1RSTR_SPI2RST_Msk (0x1UL << RCC_APB1RSTR_SPI2RST_Pos)
11032#define RCC_APB1RSTR_SPI2RST RCC_APB1RSTR_SPI2RST_Msk
11033#define RCC_APB1RSTR_SPI3RST_Pos (15U)
11034#define RCC_APB1RSTR_SPI3RST_Msk (0x1UL << RCC_APB1RSTR_SPI3RST_Pos)
11035#define RCC_APB1RSTR_SPI3RST RCC_APB1RSTR_SPI3RST_Msk
11036#define RCC_APB1RSTR_USART2RST_Pos (17U)
11037#define RCC_APB1RSTR_USART2RST_Msk (0x1UL << RCC_APB1RSTR_USART2RST_Pos)
11038#define RCC_APB1RSTR_USART2RST RCC_APB1RSTR_USART2RST_Msk
11039#define RCC_APB1RSTR_USART3RST_Pos (18U)
11040#define RCC_APB1RSTR_USART3RST_Msk (0x1UL << RCC_APB1RSTR_USART3RST_Pos)
11041#define RCC_APB1RSTR_USART3RST RCC_APB1RSTR_USART3RST_Msk
11042#define RCC_APB1RSTR_UART4RST_Pos (19U)
11043#define RCC_APB1RSTR_UART4RST_Msk (0x1UL << RCC_APB1RSTR_UART4RST_Pos)
11044#define RCC_APB1RSTR_UART4RST RCC_APB1RSTR_UART4RST_Msk
11045#define RCC_APB1RSTR_UART5RST_Pos (20U)
11046#define RCC_APB1RSTR_UART5RST_Msk (0x1UL << RCC_APB1RSTR_UART5RST_Pos)
11047#define RCC_APB1RSTR_UART5RST RCC_APB1RSTR_UART5RST_Msk
11048#define RCC_APB1RSTR_I2C1RST_Pos (21U)
11049#define RCC_APB1RSTR_I2C1RST_Msk (0x1UL << RCC_APB1RSTR_I2C1RST_Pos)
11050#define RCC_APB1RSTR_I2C1RST RCC_APB1RSTR_I2C1RST_Msk
11051#define RCC_APB1RSTR_I2C2RST_Pos (22U)
11052#define RCC_APB1RSTR_I2C2RST_Msk (0x1UL << RCC_APB1RSTR_I2C2RST_Pos)
11053#define RCC_APB1RSTR_I2C2RST RCC_APB1RSTR_I2C2RST_Msk
11054#define RCC_APB1RSTR_USBRST_Pos (23U)
11055#define RCC_APB1RSTR_USBRST_Msk (0x1UL << RCC_APB1RSTR_USBRST_Pos)
11056#define RCC_APB1RSTR_USBRST RCC_APB1RSTR_USBRST_Msk
11057#define RCC_APB1RSTR_CANRST_Pos (25U)
11058#define RCC_APB1RSTR_CANRST_Msk (0x1UL << RCC_APB1RSTR_CANRST_Pos)
11059#define RCC_APB1RSTR_CANRST RCC_APB1RSTR_CANRST_Msk
11060#define RCC_APB1RSTR_PWRRST_Pos (28U)
11061#define RCC_APB1RSTR_PWRRST_Msk (0x1UL << RCC_APB1RSTR_PWRRST_Pos)
11062#define RCC_APB1RSTR_PWRRST RCC_APB1RSTR_PWRRST_Msk
11063#define RCC_APB1RSTR_DAC1RST_Pos (29U)
11064#define RCC_APB1RSTR_DAC1RST_Msk (0x1UL << RCC_APB1RSTR_DAC1RST_Pos)
11065#define RCC_APB1RSTR_DAC1RST RCC_APB1RSTR_DAC1RST_Msk
11066#define RCC_APB1RSTR_I2C3RST_Pos (30U)
11067#define RCC_APB1RSTR_I2C3RST_Msk (0x1UL << RCC_APB1RSTR_I2C3RST_Pos)
11068#define RCC_APB1RSTR_I2C3RST RCC_APB1RSTR_I2C3RST_Msk
11070/****************** Bit definition for RCC_AHBENR register ******************/
11071#define RCC_AHBENR_DMA1EN_Pos (0U)
11072#define RCC_AHBENR_DMA1EN_Msk (0x1UL << RCC_AHBENR_DMA1EN_Pos)
11073#define RCC_AHBENR_DMA1EN RCC_AHBENR_DMA1EN_Msk
11074#define RCC_AHBENR_DMA2EN_Pos (1U)
11075#define RCC_AHBENR_DMA2EN_Msk (0x1UL << RCC_AHBENR_DMA2EN_Pos)
11076#define RCC_AHBENR_DMA2EN RCC_AHBENR_DMA2EN_Msk
11077#define RCC_AHBENR_SRAMEN_Pos (2U)
11078#define RCC_AHBENR_SRAMEN_Msk (0x1UL << RCC_AHBENR_SRAMEN_Pos)
11079#define RCC_AHBENR_SRAMEN RCC_AHBENR_SRAMEN_Msk
11080#define RCC_AHBENR_FLITFEN_Pos (4U)
11081#define RCC_AHBENR_FLITFEN_Msk (0x1UL << RCC_AHBENR_FLITFEN_Pos)
11082#define RCC_AHBENR_FLITFEN RCC_AHBENR_FLITFEN_Msk
11083#define RCC_AHBENR_FMCEN_Pos (5U)
11084#define RCC_AHBENR_FMCEN_Msk (0x1UL << RCC_AHBENR_FMCEN_Pos)
11085#define RCC_AHBENR_FMCEN RCC_AHBENR_FMCEN_Msk
11086#define RCC_AHBENR_CRCEN_Pos (6U)
11087#define RCC_AHBENR_CRCEN_Msk (0x1UL << RCC_AHBENR_CRCEN_Pos)
11088#define RCC_AHBENR_CRCEN RCC_AHBENR_CRCEN_Msk
11089#define RCC_AHBENR_GPIOHEN_Pos (16U)
11090#define RCC_AHBENR_GPIOHEN_Msk (0x1UL << RCC_AHBENR_GPIOHEN_Pos)
11091#define RCC_AHBENR_GPIOHEN RCC_AHBENR_GPIOHEN_Msk
11092#define RCC_AHBENR_GPIOAEN_Pos (17U)
11093#define RCC_AHBENR_GPIOAEN_Msk (0x1UL << RCC_AHBENR_GPIOAEN_Pos)
11094#define RCC_AHBENR_GPIOAEN RCC_AHBENR_GPIOAEN_Msk
11095#define RCC_AHBENR_GPIOBEN_Pos (18U)
11096#define RCC_AHBENR_GPIOBEN_Msk (0x1UL << RCC_AHBENR_GPIOBEN_Pos)
11097#define RCC_AHBENR_GPIOBEN RCC_AHBENR_GPIOBEN_Msk
11098#define RCC_AHBENR_GPIOCEN_Pos (19U)
11099#define RCC_AHBENR_GPIOCEN_Msk (0x1UL << RCC_AHBENR_GPIOCEN_Pos)
11100#define RCC_AHBENR_GPIOCEN RCC_AHBENR_GPIOCEN_Msk
11101#define RCC_AHBENR_GPIODEN_Pos (20U)
11102#define RCC_AHBENR_GPIODEN_Msk (0x1UL << RCC_AHBENR_GPIODEN_Pos)
11103#define RCC_AHBENR_GPIODEN RCC_AHBENR_GPIODEN_Msk
11104#define RCC_AHBENR_GPIOEEN_Pos (21U)
11105#define RCC_AHBENR_GPIOEEN_Msk (0x1UL << RCC_AHBENR_GPIOEEN_Pos)
11106#define RCC_AHBENR_GPIOEEN RCC_AHBENR_GPIOEEN_Msk
11107#define RCC_AHBENR_GPIOFEN_Pos (22U)
11108#define RCC_AHBENR_GPIOFEN_Msk (0x1UL << RCC_AHBENR_GPIOFEN_Pos)
11109#define RCC_AHBENR_GPIOFEN RCC_AHBENR_GPIOFEN_Msk
11110#define RCC_AHBENR_GPIOGEN_Pos (23U)
11111#define RCC_AHBENR_GPIOGEN_Msk (0x1UL << RCC_AHBENR_GPIOGEN_Pos)
11112#define RCC_AHBENR_GPIOGEN RCC_AHBENR_GPIOGEN_Msk
11113#define RCC_AHBENR_TSCEN_Pos (24U)
11114#define RCC_AHBENR_TSCEN_Msk (0x1UL << RCC_AHBENR_TSCEN_Pos)
11115#define RCC_AHBENR_TSCEN RCC_AHBENR_TSCEN_Msk
11116#define RCC_AHBENR_ADC12EN_Pos (28U)
11117#define RCC_AHBENR_ADC12EN_Msk (0x1UL << RCC_AHBENR_ADC12EN_Pos)
11118#define RCC_AHBENR_ADC12EN RCC_AHBENR_ADC12EN_Msk
11119#define RCC_AHBENR_ADC34EN_Pos (29U)
11120#define RCC_AHBENR_ADC34EN_Msk (0x1UL << RCC_AHBENR_ADC34EN_Pos)
11121#define RCC_AHBENR_ADC34EN RCC_AHBENR_ADC34EN_Msk
11123/***************** Bit definition for RCC_APB2ENR register ******************/
11124#define RCC_APB2ENR_SYSCFGEN_Pos (0U)
11125#define RCC_APB2ENR_SYSCFGEN_Msk (0x1UL << RCC_APB2ENR_SYSCFGEN_Pos)
11126#define RCC_APB2ENR_SYSCFGEN RCC_APB2ENR_SYSCFGEN_Msk
11127#define RCC_APB2ENR_TIM1EN_Pos (11U)
11128#define RCC_APB2ENR_TIM1EN_Msk (0x1UL << RCC_APB2ENR_TIM1EN_Pos)
11129#define RCC_APB2ENR_TIM1EN RCC_APB2ENR_TIM1EN_Msk
11130#define RCC_APB2ENR_SPI1EN_Pos (12U)
11131#define RCC_APB2ENR_SPI1EN_Msk (0x1UL << RCC_APB2ENR_SPI1EN_Pos)
11132#define RCC_APB2ENR_SPI1EN RCC_APB2ENR_SPI1EN_Msk
11133#define RCC_APB2ENR_TIM8EN_Pos (13U)
11134#define RCC_APB2ENR_TIM8EN_Msk (0x1UL << RCC_APB2ENR_TIM8EN_Pos)
11135#define RCC_APB2ENR_TIM8EN RCC_APB2ENR_TIM8EN_Msk
11136#define RCC_APB2ENR_USART1EN_Pos (14U)
11137#define RCC_APB2ENR_USART1EN_Msk (0x1UL << RCC_APB2ENR_USART1EN_Pos)
11138#define RCC_APB2ENR_USART1EN RCC_APB2ENR_USART1EN_Msk
11139#define RCC_APB2ENR_SPI4EN_Pos (15U)
11140#define RCC_APB2ENR_SPI4EN_Msk (0x1UL << RCC_APB2ENR_SPI4EN_Pos)
11141#define RCC_APB2ENR_SPI4EN RCC_APB2ENR_SPI4EN_Msk
11142#define RCC_APB2ENR_TIM15EN_Pos (16U)
11143#define RCC_APB2ENR_TIM15EN_Msk (0x1UL << RCC_APB2ENR_TIM15EN_Pos)
11144#define RCC_APB2ENR_TIM15EN RCC_APB2ENR_TIM15EN_Msk
11145#define RCC_APB2ENR_TIM16EN_Pos (17U)
11146#define RCC_APB2ENR_TIM16EN_Msk (0x1UL << RCC_APB2ENR_TIM16EN_Pos)
11147#define RCC_APB2ENR_TIM16EN RCC_APB2ENR_TIM16EN_Msk
11148#define RCC_APB2ENR_TIM17EN_Pos (18U)
11149#define RCC_APB2ENR_TIM17EN_Msk (0x1UL << RCC_APB2ENR_TIM17EN_Pos)
11150#define RCC_APB2ENR_TIM17EN RCC_APB2ENR_TIM17EN_Msk
11151#define RCC_APB2ENR_TIM20EN_Pos (20U)
11152#define RCC_APB2ENR_TIM20EN_Msk (0x1UL << RCC_APB2ENR_TIM20EN_Pos)
11153#define RCC_APB2ENR_TIM20EN RCC_APB2ENR_TIM20EN_Msk
11155/****************** Bit definition for RCC_APB1ENR register ******************/
11156#define RCC_APB1ENR_TIM2EN_Pos (0U)
11157#define RCC_APB1ENR_TIM2EN_Msk (0x1UL << RCC_APB1ENR_TIM2EN_Pos)
11158#define RCC_APB1ENR_TIM2EN RCC_APB1ENR_TIM2EN_Msk
11159#define RCC_APB1ENR_TIM3EN_Pos (1U)
11160#define RCC_APB1ENR_TIM3EN_Msk (0x1UL << RCC_APB1ENR_TIM3EN_Pos)
11161#define RCC_APB1ENR_TIM3EN RCC_APB1ENR_TIM3EN_Msk
11162#define RCC_APB1ENR_TIM4EN_Pos (2U)
11163#define RCC_APB1ENR_TIM4EN_Msk (0x1UL << RCC_APB1ENR_TIM4EN_Pos)
11164#define RCC_APB1ENR_TIM4EN RCC_APB1ENR_TIM4EN_Msk
11165#define RCC_APB1ENR_TIM6EN_Pos (4U)
11166#define RCC_APB1ENR_TIM6EN_Msk (0x1UL << RCC_APB1ENR_TIM6EN_Pos)
11167#define RCC_APB1ENR_TIM6EN RCC_APB1ENR_TIM6EN_Msk
11168#define RCC_APB1ENR_TIM7EN_Pos (5U)
11169#define RCC_APB1ENR_TIM7EN_Msk (0x1UL << RCC_APB1ENR_TIM7EN_Pos)
11170#define RCC_APB1ENR_TIM7EN RCC_APB1ENR_TIM7EN_Msk
11171#define RCC_APB1ENR_WWDGEN_Pos (11U)
11172#define RCC_APB1ENR_WWDGEN_Msk (0x1UL << RCC_APB1ENR_WWDGEN_Pos)
11173#define RCC_APB1ENR_WWDGEN RCC_APB1ENR_WWDGEN_Msk
11174#define RCC_APB1ENR_SPI2EN_Pos (14U)
11175#define RCC_APB1ENR_SPI2EN_Msk (0x1UL << RCC_APB1ENR_SPI2EN_Pos)
11176#define RCC_APB1ENR_SPI2EN RCC_APB1ENR_SPI2EN_Msk
11177#define RCC_APB1ENR_SPI3EN_Pos (15U)
11178#define RCC_APB1ENR_SPI3EN_Msk (0x1UL << RCC_APB1ENR_SPI3EN_Pos)
11179#define RCC_APB1ENR_SPI3EN RCC_APB1ENR_SPI3EN_Msk
11180#define RCC_APB1ENR_USART2EN_Pos (17U)
11181#define RCC_APB1ENR_USART2EN_Msk (0x1UL << RCC_APB1ENR_USART2EN_Pos)
11182#define RCC_APB1ENR_USART2EN RCC_APB1ENR_USART2EN_Msk
11183#define RCC_APB1ENR_USART3EN_Pos (18U)
11184#define RCC_APB1ENR_USART3EN_Msk (0x1UL << RCC_APB1ENR_USART3EN_Pos)
11185#define RCC_APB1ENR_USART3EN RCC_APB1ENR_USART3EN_Msk
11186#define RCC_APB1ENR_UART4EN_Pos (19U)
11187#define RCC_APB1ENR_UART4EN_Msk (0x1UL << RCC_APB1ENR_UART4EN_Pos)
11188#define RCC_APB1ENR_UART4EN RCC_APB1ENR_UART4EN_Msk
11189#define RCC_APB1ENR_UART5EN_Pos (20U)
11190#define RCC_APB1ENR_UART5EN_Msk (0x1UL << RCC_APB1ENR_UART5EN_Pos)
11191#define RCC_APB1ENR_UART5EN RCC_APB1ENR_UART5EN_Msk
11192#define RCC_APB1ENR_I2C1EN_Pos (21U)
11193#define RCC_APB1ENR_I2C1EN_Msk (0x1UL << RCC_APB1ENR_I2C1EN_Pos)
11194#define RCC_APB1ENR_I2C1EN RCC_APB1ENR_I2C1EN_Msk
11195#define RCC_APB1ENR_I2C2EN_Pos (22U)
11196#define RCC_APB1ENR_I2C2EN_Msk (0x1UL << RCC_APB1ENR_I2C2EN_Pos)
11197#define RCC_APB1ENR_I2C2EN RCC_APB1ENR_I2C2EN_Msk
11198#define RCC_APB1ENR_USBEN_Pos (23U)
11199#define RCC_APB1ENR_USBEN_Msk (0x1UL << RCC_APB1ENR_USBEN_Pos)
11200#define RCC_APB1ENR_USBEN RCC_APB1ENR_USBEN_Msk
11201#define RCC_APB1ENR_CANEN_Pos (25U)
11202#define RCC_APB1ENR_CANEN_Msk (0x1UL << RCC_APB1ENR_CANEN_Pos)
11203#define RCC_APB1ENR_CANEN RCC_APB1ENR_CANEN_Msk
11204#define RCC_APB1ENR_PWREN_Pos (28U)
11205#define RCC_APB1ENR_PWREN_Msk (0x1UL << RCC_APB1ENR_PWREN_Pos)
11206#define RCC_APB1ENR_PWREN RCC_APB1ENR_PWREN_Msk
11207#define RCC_APB1ENR_DAC1EN_Pos (29U)
11208#define RCC_APB1ENR_DAC1EN_Msk (0x1UL << RCC_APB1ENR_DAC1EN_Pos)
11209#define RCC_APB1ENR_DAC1EN RCC_APB1ENR_DAC1EN_Msk
11210#define RCC_APB1ENR_I2C3EN_Pos (30U)
11211#define RCC_APB1ENR_I2C3EN_Msk (0x1UL << RCC_APB1ENR_I2C3EN_Pos)
11212#define RCC_APB1ENR_I2C3EN RCC_APB1ENR_I2C3EN_Msk
11214/******************** Bit definition for RCC_BDCR register ******************/
11215#define RCC_BDCR_LSE_Pos (0U)
11216#define RCC_BDCR_LSE_Msk (0x7UL << RCC_BDCR_LSE_Pos)
11217#define RCC_BDCR_LSE RCC_BDCR_LSE_Msk
11218#define RCC_BDCR_LSEON_Pos (0U)
11219#define RCC_BDCR_LSEON_Msk (0x1UL << RCC_BDCR_LSEON_Pos)
11220#define RCC_BDCR_LSEON RCC_BDCR_LSEON_Msk
11221#define RCC_BDCR_LSERDY_Pos (1U)
11222#define RCC_BDCR_LSERDY_Msk (0x1UL << RCC_BDCR_LSERDY_Pos)
11223#define RCC_BDCR_LSERDY RCC_BDCR_LSERDY_Msk
11224#define RCC_BDCR_LSEBYP_Pos (2U)
11225#define RCC_BDCR_LSEBYP_Msk (0x1UL << RCC_BDCR_LSEBYP_Pos)
11226#define RCC_BDCR_LSEBYP RCC_BDCR_LSEBYP_Msk
11228#define RCC_BDCR_LSEDRV_Pos (3U)
11229#define RCC_BDCR_LSEDRV_Msk (0x3UL << RCC_BDCR_LSEDRV_Pos)
11230#define RCC_BDCR_LSEDRV RCC_BDCR_LSEDRV_Msk
11231#define RCC_BDCR_LSEDRV_0 (0x1UL << RCC_BDCR_LSEDRV_Pos)
11232#define RCC_BDCR_LSEDRV_1 (0x2UL << RCC_BDCR_LSEDRV_Pos)
11234#define RCC_BDCR_RTCSEL_Pos (8U)
11235#define RCC_BDCR_RTCSEL_Msk (0x3UL << RCC_BDCR_RTCSEL_Pos)
11236#define RCC_BDCR_RTCSEL RCC_BDCR_RTCSEL_Msk
11237#define RCC_BDCR_RTCSEL_0 (0x1UL << RCC_BDCR_RTCSEL_Pos)
11238#define RCC_BDCR_RTCSEL_1 (0x2UL << RCC_BDCR_RTCSEL_Pos)
11241#define RCC_BDCR_RTCSEL_NOCLOCK (0x00000000U)
11242#define RCC_BDCR_RTCSEL_LSE (0x00000100U)
11243#define RCC_BDCR_RTCSEL_LSI (0x00000200U)
11244#define RCC_BDCR_RTCSEL_HSE (0x00000300U)
11246#define RCC_BDCR_RTCEN_Pos (15U)
11247#define RCC_BDCR_RTCEN_Msk (0x1UL << RCC_BDCR_RTCEN_Pos)
11248#define RCC_BDCR_RTCEN RCC_BDCR_RTCEN_Msk
11249#define RCC_BDCR_BDRST_Pos (16U)
11250#define RCC_BDCR_BDRST_Msk (0x1UL << RCC_BDCR_BDRST_Pos)
11251#define RCC_BDCR_BDRST RCC_BDCR_BDRST_Msk
11253/******************** Bit definition for RCC_CSR register *******************/
11254#define RCC_CSR_LSION_Pos (0U)
11255#define RCC_CSR_LSION_Msk (0x1UL << RCC_CSR_LSION_Pos)
11256#define RCC_CSR_LSION RCC_CSR_LSION_Msk
11257#define RCC_CSR_LSIRDY_Pos (1U)
11258#define RCC_CSR_LSIRDY_Msk (0x1UL << RCC_CSR_LSIRDY_Pos)
11259#define RCC_CSR_LSIRDY RCC_CSR_LSIRDY_Msk
11260#define RCC_CSR_V18PWRRSTF_Pos (23U)
11261#define RCC_CSR_V18PWRRSTF_Msk (0x1UL << RCC_CSR_V18PWRRSTF_Pos)
11262#define RCC_CSR_V18PWRRSTF RCC_CSR_V18PWRRSTF_Msk
11263#define RCC_CSR_RMVF_Pos (24U)
11264#define RCC_CSR_RMVF_Msk (0x1UL << RCC_CSR_RMVF_Pos)
11265#define RCC_CSR_RMVF RCC_CSR_RMVF_Msk
11266#define RCC_CSR_OBLRSTF_Pos (25U)
11267#define RCC_CSR_OBLRSTF_Msk (0x1UL << RCC_CSR_OBLRSTF_Pos)
11268#define RCC_CSR_OBLRSTF RCC_CSR_OBLRSTF_Msk
11269#define RCC_CSR_PINRSTF_Pos (26U)
11270#define RCC_CSR_PINRSTF_Msk (0x1UL << RCC_CSR_PINRSTF_Pos)
11271#define RCC_CSR_PINRSTF RCC_CSR_PINRSTF_Msk
11272#define RCC_CSR_PORRSTF_Pos (27U)
11273#define RCC_CSR_PORRSTF_Msk (0x1UL << RCC_CSR_PORRSTF_Pos)
11274#define RCC_CSR_PORRSTF RCC_CSR_PORRSTF_Msk
11275#define RCC_CSR_SFTRSTF_Pos (28U)
11276#define RCC_CSR_SFTRSTF_Msk (0x1UL << RCC_CSR_SFTRSTF_Pos)
11277#define RCC_CSR_SFTRSTF RCC_CSR_SFTRSTF_Msk
11278#define RCC_CSR_IWDGRSTF_Pos (29U)
11279#define RCC_CSR_IWDGRSTF_Msk (0x1UL << RCC_CSR_IWDGRSTF_Pos)
11280#define RCC_CSR_IWDGRSTF RCC_CSR_IWDGRSTF_Msk
11281#define RCC_CSR_WWDGRSTF_Pos (30U)
11282#define RCC_CSR_WWDGRSTF_Msk (0x1UL << RCC_CSR_WWDGRSTF_Pos)
11283#define RCC_CSR_WWDGRSTF RCC_CSR_WWDGRSTF_Msk
11284#define RCC_CSR_LPWRRSTF_Pos (31U)
11285#define RCC_CSR_LPWRRSTF_Msk (0x1UL << RCC_CSR_LPWRRSTF_Pos)
11286#define RCC_CSR_LPWRRSTF RCC_CSR_LPWRRSTF_Msk
11288/* Legacy defines */
11289#define RCC_CSR_VREGRSTF RCC_CSR_V18PWRRSTF
11290
11291/******************* Bit definition for RCC_AHBRSTR register ****************/
11292#define RCC_AHBRSTR_FMCRST_Pos (5U)
11293#define RCC_AHBRSTR_FMCRST_Msk (0x1UL << RCC_AHBRSTR_FMCRST_Pos)
11294#define RCC_AHBRSTR_FMCRST RCC_AHBRSTR_FMCRST_Msk
11295#define RCC_AHBRSTR_GPIOHRST_Pos (16U)
11296#define RCC_AHBRSTR_GPIOHRST_Msk (0x1UL << RCC_AHBRSTR_GPIOHRST_Pos)
11297#define RCC_AHBRSTR_GPIOHRST RCC_AHBRSTR_GPIOHRST_Msk
11298#define RCC_AHBRSTR_GPIOARST_Pos (17U)
11299#define RCC_AHBRSTR_GPIOARST_Msk (0x1UL << RCC_AHBRSTR_GPIOARST_Pos)
11300#define RCC_AHBRSTR_GPIOARST RCC_AHBRSTR_GPIOARST_Msk
11301#define RCC_AHBRSTR_GPIOBRST_Pos (18U)
11302#define RCC_AHBRSTR_GPIOBRST_Msk (0x1UL << RCC_AHBRSTR_GPIOBRST_Pos)
11303#define RCC_AHBRSTR_GPIOBRST RCC_AHBRSTR_GPIOBRST_Msk
11304#define RCC_AHBRSTR_GPIOCRST_Pos (19U)
11305#define RCC_AHBRSTR_GPIOCRST_Msk (0x1UL << RCC_AHBRSTR_GPIOCRST_Pos)
11306#define RCC_AHBRSTR_GPIOCRST RCC_AHBRSTR_GPIOCRST_Msk
11307#define RCC_AHBRSTR_GPIODRST_Pos (20U)
11308#define RCC_AHBRSTR_GPIODRST_Msk (0x1UL << RCC_AHBRSTR_GPIODRST_Pos)
11309#define RCC_AHBRSTR_GPIODRST RCC_AHBRSTR_GPIODRST_Msk
11310#define RCC_AHBRSTR_GPIOERST_Pos (21U)
11311#define RCC_AHBRSTR_GPIOERST_Msk (0x1UL << RCC_AHBRSTR_GPIOERST_Pos)
11312#define RCC_AHBRSTR_GPIOERST RCC_AHBRSTR_GPIOERST_Msk
11313#define RCC_AHBRSTR_GPIOFRST_Pos (22U)
11314#define RCC_AHBRSTR_GPIOFRST_Msk (0x1UL << RCC_AHBRSTR_GPIOFRST_Pos)
11315#define RCC_AHBRSTR_GPIOFRST RCC_AHBRSTR_GPIOFRST_Msk
11316#define RCC_AHBRSTR_GPIOGRST_Pos (23U)
11317#define RCC_AHBRSTR_GPIOGRST_Msk (0x1UL << RCC_AHBRSTR_GPIOGRST_Pos)
11318#define RCC_AHBRSTR_GPIOGRST RCC_AHBRSTR_GPIOGRST_Msk
11319#define RCC_AHBRSTR_TSCRST_Pos (24U)
11320#define RCC_AHBRSTR_TSCRST_Msk (0x1UL << RCC_AHBRSTR_TSCRST_Pos)
11321#define RCC_AHBRSTR_TSCRST RCC_AHBRSTR_TSCRST_Msk
11322#define RCC_AHBRSTR_ADC12RST_Pos (28U)
11323#define RCC_AHBRSTR_ADC12RST_Msk (0x1UL << RCC_AHBRSTR_ADC12RST_Pos)
11324#define RCC_AHBRSTR_ADC12RST RCC_AHBRSTR_ADC12RST_Msk
11325#define RCC_AHBRSTR_ADC34RST_Pos (29U)
11326#define RCC_AHBRSTR_ADC34RST_Msk (0x1UL << RCC_AHBRSTR_ADC34RST_Pos)
11327#define RCC_AHBRSTR_ADC34RST RCC_AHBRSTR_ADC34RST_Msk
11329/******************* Bit definition for RCC_CFGR2 register ******************/
11331#define RCC_CFGR2_PREDIV_Pos (0U)
11332#define RCC_CFGR2_PREDIV_Msk (0xFUL << RCC_CFGR2_PREDIV_Pos)
11333#define RCC_CFGR2_PREDIV RCC_CFGR2_PREDIV_Msk
11334#define RCC_CFGR2_PREDIV_0 (0x1UL << RCC_CFGR2_PREDIV_Pos)
11335#define RCC_CFGR2_PREDIV_1 (0x2UL << RCC_CFGR2_PREDIV_Pos)
11336#define RCC_CFGR2_PREDIV_2 (0x4UL << RCC_CFGR2_PREDIV_Pos)
11337#define RCC_CFGR2_PREDIV_3 (0x8UL << RCC_CFGR2_PREDIV_Pos)
11339#define RCC_CFGR2_PREDIV_DIV1 (0x00000000U)
11340#define RCC_CFGR2_PREDIV_DIV2 (0x00000001U)
11341#define RCC_CFGR2_PREDIV_DIV3 (0x00000002U)
11342#define RCC_CFGR2_PREDIV_DIV4 (0x00000003U)
11343#define RCC_CFGR2_PREDIV_DIV5 (0x00000004U)
11344#define RCC_CFGR2_PREDIV_DIV6 (0x00000005U)
11345#define RCC_CFGR2_PREDIV_DIV7 (0x00000006U)
11346#define RCC_CFGR2_PREDIV_DIV8 (0x00000007U)
11347#define RCC_CFGR2_PREDIV_DIV9 (0x00000008U)
11348#define RCC_CFGR2_PREDIV_DIV10 (0x00000009U)
11349#define RCC_CFGR2_PREDIV_DIV11 (0x0000000AU)
11350#define RCC_CFGR2_PREDIV_DIV12 (0x0000000BU)
11351#define RCC_CFGR2_PREDIV_DIV13 (0x0000000CU)
11352#define RCC_CFGR2_PREDIV_DIV14 (0x0000000DU)
11353#define RCC_CFGR2_PREDIV_DIV15 (0x0000000EU)
11354#define RCC_CFGR2_PREDIV_DIV16 (0x0000000FU)
11357#define RCC_CFGR2_ADCPRE12_Pos (4U)
11358#define RCC_CFGR2_ADCPRE12_Msk (0x1FUL << RCC_CFGR2_ADCPRE12_Pos)
11359#define RCC_CFGR2_ADCPRE12 RCC_CFGR2_ADCPRE12_Msk
11360#define RCC_CFGR2_ADCPRE12_0 (0x01UL << RCC_CFGR2_ADCPRE12_Pos)
11361#define RCC_CFGR2_ADCPRE12_1 (0x02UL << RCC_CFGR2_ADCPRE12_Pos)
11362#define RCC_CFGR2_ADCPRE12_2 (0x04UL << RCC_CFGR2_ADCPRE12_Pos)
11363#define RCC_CFGR2_ADCPRE12_3 (0x08UL << RCC_CFGR2_ADCPRE12_Pos)
11364#define RCC_CFGR2_ADCPRE12_4 (0x10UL << RCC_CFGR2_ADCPRE12_Pos)
11366#define RCC_CFGR2_ADCPRE12_NO (0x00000000U)
11367#define RCC_CFGR2_ADCPRE12_DIV1 (0x00000100U)
11368#define RCC_CFGR2_ADCPRE12_DIV2 (0x00000110U)
11369#define RCC_CFGR2_ADCPRE12_DIV4 (0x00000120U)
11370#define RCC_CFGR2_ADCPRE12_DIV6 (0x00000130U)
11371#define RCC_CFGR2_ADCPRE12_DIV8 (0x00000140U)
11372#define RCC_CFGR2_ADCPRE12_DIV10 (0x00000150U)
11373#define RCC_CFGR2_ADCPRE12_DIV12 (0x00000160U)
11374#define RCC_CFGR2_ADCPRE12_DIV16 (0x00000170U)
11375#define RCC_CFGR2_ADCPRE12_DIV32 (0x00000180U)
11376#define RCC_CFGR2_ADCPRE12_DIV64 (0x00000190U)
11377#define RCC_CFGR2_ADCPRE12_DIV128 (0x000001A0U)
11378#define RCC_CFGR2_ADCPRE12_DIV256 (0x000001B0U)
11381#define RCC_CFGR2_ADCPRE34_Pos (9U)
11382#define RCC_CFGR2_ADCPRE34_Msk (0x1FUL << RCC_CFGR2_ADCPRE34_Pos)
11383#define RCC_CFGR2_ADCPRE34 RCC_CFGR2_ADCPRE34_Msk
11384#define RCC_CFGR2_ADCPRE34_0 (0x01UL << RCC_CFGR2_ADCPRE34_Pos)
11385#define RCC_CFGR2_ADCPRE34_1 (0x02UL << RCC_CFGR2_ADCPRE34_Pos)
11386#define RCC_CFGR2_ADCPRE34_2 (0x04UL << RCC_CFGR2_ADCPRE34_Pos)
11387#define RCC_CFGR2_ADCPRE34_3 (0x08UL << RCC_CFGR2_ADCPRE34_Pos)
11388#define RCC_CFGR2_ADCPRE34_4 (0x10UL << RCC_CFGR2_ADCPRE34_Pos)
11390#define RCC_CFGR2_ADCPRE34_NO (0x00000000U)
11391#define RCC_CFGR2_ADCPRE34_DIV1 (0x00002000U)
11392#define RCC_CFGR2_ADCPRE34_DIV2 (0x00002200U)
11393#define RCC_CFGR2_ADCPRE34_DIV4 (0x00002400U)
11394#define RCC_CFGR2_ADCPRE34_DIV6 (0x00002600U)
11395#define RCC_CFGR2_ADCPRE34_DIV8 (0x00002800U)
11396#define RCC_CFGR2_ADCPRE34_DIV10 (0x00002A00U)
11397#define RCC_CFGR2_ADCPRE34_DIV12 (0x00002C00U)
11398#define RCC_CFGR2_ADCPRE34_DIV16 (0x00002E00U)
11399#define RCC_CFGR2_ADCPRE34_DIV32 (0x00003000U)
11400#define RCC_CFGR2_ADCPRE34_DIV64 (0x00003200U)
11401#define RCC_CFGR2_ADCPRE34_DIV128 (0x00003400U)
11402#define RCC_CFGR2_ADCPRE34_DIV256 (0x00003600U)
11404/******************* Bit definition for RCC_CFGR3 register ******************/
11405#define RCC_CFGR3_USART1SW_Pos (0U)
11406#define RCC_CFGR3_USART1SW_Msk (0x3UL << RCC_CFGR3_USART1SW_Pos)
11407#define RCC_CFGR3_USART1SW RCC_CFGR3_USART1SW_Msk
11408#define RCC_CFGR3_USART1SW_0 (0x1UL << RCC_CFGR3_USART1SW_Pos)
11409#define RCC_CFGR3_USART1SW_1 (0x2UL << RCC_CFGR3_USART1SW_Pos)
11411#define RCC_CFGR3_USART1SW_PCLK2 (0x00000000U)
11412#define RCC_CFGR3_USART1SW_SYSCLK (0x00000001U)
11413#define RCC_CFGR3_USART1SW_LSE (0x00000002U)
11414#define RCC_CFGR3_USART1SW_HSI (0x00000003U)
11415/* Legacy defines */
11416#define RCC_CFGR3_USART1SW_PCLK RCC_CFGR3_USART1SW_PCLK2
11417
11418#define RCC_CFGR3_I2CSW_Pos (4U)
11419#define RCC_CFGR3_I2CSW_Msk (0x7UL << RCC_CFGR3_I2CSW_Pos)
11420#define RCC_CFGR3_I2CSW RCC_CFGR3_I2CSW_Msk
11421#define RCC_CFGR3_I2C1SW_Pos (4U)
11422#define RCC_CFGR3_I2C1SW_Msk (0x1UL << RCC_CFGR3_I2C1SW_Pos)
11423#define RCC_CFGR3_I2C1SW RCC_CFGR3_I2C1SW_Msk
11424#define RCC_CFGR3_I2C2SW_Pos (5U)
11425#define RCC_CFGR3_I2C2SW_Msk (0x1UL << RCC_CFGR3_I2C2SW_Pos)
11426#define RCC_CFGR3_I2C2SW RCC_CFGR3_I2C2SW_Msk
11427#define RCC_CFGR3_I2C3SW_Pos (6U)
11428#define RCC_CFGR3_I2C3SW_Msk (0x1UL << RCC_CFGR3_I2C3SW_Pos)
11429#define RCC_CFGR3_I2C3SW RCC_CFGR3_I2C3SW_Msk
11431#define RCC_CFGR3_I2C1SW_HSI (0x00000000U)
11432#define RCC_CFGR3_I2C1SW_SYSCLK_Pos (4U)
11433#define RCC_CFGR3_I2C1SW_SYSCLK_Msk (0x1UL << RCC_CFGR3_I2C1SW_SYSCLK_Pos)
11434#define RCC_CFGR3_I2C1SW_SYSCLK RCC_CFGR3_I2C1SW_SYSCLK_Msk
11435#define RCC_CFGR3_I2C2SW_HSI (0x00000000U)
11436#define RCC_CFGR3_I2C2SW_SYSCLK_Pos (5U)
11437#define RCC_CFGR3_I2C2SW_SYSCLK_Msk (0x1UL << RCC_CFGR3_I2C2SW_SYSCLK_Pos)
11438#define RCC_CFGR3_I2C2SW_SYSCLK RCC_CFGR3_I2C2SW_SYSCLK_Msk
11439#define RCC_CFGR3_I2C3SW_HSI (0x00000000U)
11440#define RCC_CFGR3_I2C3SW_SYSCLK_Pos (6U)
11441#define RCC_CFGR3_I2C3SW_SYSCLK_Msk (0x1UL << RCC_CFGR3_I2C3SW_SYSCLK_Pos)
11442#define RCC_CFGR3_I2C3SW_SYSCLK RCC_CFGR3_I2C3SW_SYSCLK_Msk
11444#define RCC_CFGR3_TIMSW_Pos (8U)
11445#define RCC_CFGR3_TIMSW_Msk (0xAFUL << RCC_CFGR3_TIMSW_Pos)
11446#define RCC_CFGR3_TIMSW RCC_CFGR3_TIMSW_Msk
11447#define RCC_CFGR3_TIM1SW_Pos (8U)
11448#define RCC_CFGR3_TIM1SW_Msk (0x1UL << RCC_CFGR3_TIM1SW_Pos)
11449#define RCC_CFGR3_TIM1SW RCC_CFGR3_TIM1SW_Msk
11450#define RCC_CFGR3_TIM8SW_Pos (9U)
11451#define RCC_CFGR3_TIM8SW_Msk (0x1UL << RCC_CFGR3_TIM8SW_Pos)
11452#define RCC_CFGR3_TIM8SW RCC_CFGR3_TIM8SW_Msk
11453#define RCC_CFGR3_TIM15SW_Pos (10U)
11454#define RCC_CFGR3_TIM15SW_Msk (0x1UL << RCC_CFGR3_TIM15SW_Pos)
11455#define RCC_CFGR3_TIM15SW RCC_CFGR3_TIM15SW_Msk
11456#define RCC_CFGR3_TIM16SW_Pos (11U)
11457#define RCC_CFGR3_TIM16SW_Msk (0x1UL << RCC_CFGR3_TIM16SW_Pos)
11458#define RCC_CFGR3_TIM16SW RCC_CFGR3_TIM16SW_Msk
11459#define RCC_CFGR3_TIM17SW_Pos (13U)
11460#define RCC_CFGR3_TIM17SW_Msk (0x1UL << RCC_CFGR3_TIM17SW_Pos)
11461#define RCC_CFGR3_TIM17SW RCC_CFGR3_TIM17SW_Msk
11462#define RCC_CFGR3_TIM20SW_Pos (15U)
11463#define RCC_CFGR3_TIM20SW_Msk (0x1UL << RCC_CFGR3_TIM20SW_Pos)
11464#define RCC_CFGR3_TIM20SW RCC_CFGR3_TIM20SW_Msk
11465#define RCC_CFGR3_TIM2SW_Pos (24U)
11466#define RCC_CFGR3_TIM2SW_Msk (0x1UL << RCC_CFGR3_TIM2SW_Pos)
11467#define RCC_CFGR3_TIM2SW RCC_CFGR3_TIM2SW_Msk
11468#define RCC_CFGR3_TIM34SW_Pos (25U)
11469#define RCC_CFGR3_TIM34SW_Msk (0x1UL << RCC_CFGR3_TIM34SW_Pos)
11470#define RCC_CFGR3_TIM34SW RCC_CFGR3_TIM34SW_Msk
11471#define RCC_CFGR3_TIM1SW_PCLK2 (0x00000000U)
11472#define RCC_CFGR3_TIM1SW_PLL_Pos (8U)
11473#define RCC_CFGR3_TIM1SW_PLL_Msk (0x1UL << RCC_CFGR3_TIM1SW_PLL_Pos)
11474#define RCC_CFGR3_TIM1SW_PLL RCC_CFGR3_TIM1SW_PLL_Msk
11475#define RCC_CFGR3_TIM8SW_PCLK2 (0x00000000U)
11476#define RCC_CFGR3_TIM8SW_PLL_Pos (9U)
11477#define RCC_CFGR3_TIM8SW_PLL_Msk (0x1UL << RCC_CFGR3_TIM8SW_PLL_Pos)
11478#define RCC_CFGR3_TIM8SW_PLL RCC_CFGR3_TIM8SW_PLL_Msk
11479#define RCC_CFGR3_TIM15SW_PCLK2 (0x00000000U)
11480#define RCC_CFGR3_TIM15SW_PLL_Pos (10U)
11481#define RCC_CFGR3_TIM15SW_PLL_Msk (0x1UL << RCC_CFGR3_TIM15SW_PLL_Pos)
11482#define RCC_CFGR3_TIM15SW_PLL RCC_CFGR3_TIM15SW_PLL_Msk
11483#define RCC_CFGR3_TIM16SW_PCLK2 (0x00000000U)
11484#define RCC_CFGR3_TIM16SW_PLL_Pos (11U)
11485#define RCC_CFGR3_TIM16SW_PLL_Msk (0x1UL << RCC_CFGR3_TIM16SW_PLL_Pos)
11486#define RCC_CFGR3_TIM16SW_PLL RCC_CFGR3_TIM16SW_PLL_Msk
11487#define RCC_CFGR3_TIM17SW_PCLK2 (0x00000000U)
11488#define RCC_CFGR3_TIM17SW_PLL_Pos (13U)
11489#define RCC_CFGR3_TIM17SW_PLL_Msk (0x1UL << RCC_CFGR3_TIM17SW_PLL_Pos)
11490#define RCC_CFGR3_TIM17SW_PLL RCC_CFGR3_TIM17SW_PLL_Msk
11491#define RCC_CFGR3_TIM20SW_PCLK2 (0x00000000U)
11492#define RCC_CFGR3_TIM20SW_PLL_Pos (15U)
11493#define RCC_CFGR3_TIM20SW_PLL_Msk (0x1UL << RCC_CFGR3_TIM20SW_PLL_Pos)
11494#define RCC_CFGR3_TIM20SW_PLL RCC_CFGR3_TIM20SW_PLL_Msk
11496#define RCC_CFGR3_USART2SW_Pos (16U)
11497#define RCC_CFGR3_USART2SW_Msk (0x3UL << RCC_CFGR3_USART2SW_Pos)
11498#define RCC_CFGR3_USART2SW RCC_CFGR3_USART2SW_Msk
11499#define RCC_CFGR3_USART2SW_0 (0x1UL << RCC_CFGR3_USART2SW_Pos)
11500#define RCC_CFGR3_USART2SW_1 (0x2UL << RCC_CFGR3_USART2SW_Pos)
11502#define RCC_CFGR3_USART2SW_PCLK (0x00000000U)
11503#define RCC_CFGR3_USART2SW_SYSCLK (0x00010000U)
11504#define RCC_CFGR3_USART2SW_LSE (0x00020000U)
11505#define RCC_CFGR3_USART2SW_HSI (0x00030000U)
11507#define RCC_CFGR3_USART3SW_Pos (18U)
11508#define RCC_CFGR3_USART3SW_Msk (0x3UL << RCC_CFGR3_USART3SW_Pos)
11509#define RCC_CFGR3_USART3SW RCC_CFGR3_USART3SW_Msk
11510#define RCC_CFGR3_USART3SW_0 (0x1UL << RCC_CFGR3_USART3SW_Pos)
11511#define RCC_CFGR3_USART3SW_1 (0x2UL << RCC_CFGR3_USART3SW_Pos)
11513#define RCC_CFGR3_USART3SW_PCLK (0x00000000U)
11514#define RCC_CFGR3_USART3SW_SYSCLK (0x00040000U)
11515#define RCC_CFGR3_USART3SW_LSE (0x00080000U)
11516#define RCC_CFGR3_USART3SW_HSI (0x000C0000U)
11518#define RCC_CFGR3_UART4SW_Pos (20U)
11519#define RCC_CFGR3_UART4SW_Msk (0x3UL << RCC_CFGR3_UART4SW_Pos)
11520#define RCC_CFGR3_UART4SW RCC_CFGR3_UART4SW_Msk
11521#define RCC_CFGR3_UART4SW_0 (0x1UL << RCC_CFGR3_UART4SW_Pos)
11522#define RCC_CFGR3_UART4SW_1 (0x2UL << RCC_CFGR3_UART4SW_Pos)
11524#define RCC_CFGR3_UART4SW_PCLK (0x00000000U)
11525#define RCC_CFGR3_UART4SW_SYSCLK (0x00100000U)
11526#define RCC_CFGR3_UART4SW_LSE (0x00200000U)
11527#define RCC_CFGR3_UART4SW_HSI (0x00300000U)
11529#define RCC_CFGR3_UART5SW_Pos (22U)
11530#define RCC_CFGR3_UART5SW_Msk (0x3UL << RCC_CFGR3_UART5SW_Pos)
11531#define RCC_CFGR3_UART5SW RCC_CFGR3_UART5SW_Msk
11532#define RCC_CFGR3_UART5SW_0 (0x1UL << RCC_CFGR3_UART5SW_Pos)
11533#define RCC_CFGR3_UART5SW_1 (0x2UL << RCC_CFGR3_UART5SW_Pos)
11535#define RCC_CFGR3_UART5SW_PCLK (0x00000000U)
11536#define RCC_CFGR3_UART5SW_SYSCLK (0x00400000U)
11537#define RCC_CFGR3_UART5SW_LSE (0x00800000U)
11538#define RCC_CFGR3_UART5SW_HSI (0x00C00000U)
11540#define RCC_CFGR3_TIM2SW_PCLK1 (0x00000000U)
11541#define RCC_CFGR3_TIM2SW_PLL_Pos (24U)
11542#define RCC_CFGR3_TIM2SW_PLL_Msk (0x1UL << RCC_CFGR3_TIM2SW_PLL_Pos)
11543#define RCC_CFGR3_TIM2SW_PLL RCC_CFGR3_TIM2SW_PLL_Msk
11545#define RCC_CFGR3_TIM34SW_PCLK1 (0x00000000U)
11546#define RCC_CFGR3_TIM34SW_PLL_Pos (25U)
11547#define RCC_CFGR3_TIM34SW_PLL_Msk (0x1UL << RCC_CFGR3_TIM34SW_PLL_Pos)
11548#define RCC_CFGR3_TIM34SW_PLL RCC_CFGR3_TIM34SW_PLL_Msk
11550/* Legacy defines */
11551#define RCC_CFGR3_TIM1SW_HCLK RCC_CFGR3_TIM1SW_PCLK2
11552#define RCC_CFGR3_TIM8SW_HCLK RCC_CFGR3_TIM8SW_PCLK2
11553#define RCC_CFGR3_TIM15SW_HCLK RCC_CFGR3_TIM15SW_PCLK2
11554#define RCC_CFGR3_TIM16SW_HCLK RCC_CFGR3_TIM16SW_PCLK2
11555#define RCC_CFGR3_TIM17SW_HCLK RCC_CFGR3_TIM17SW_PCLK2
11556#define RCC_CFGR3_TIM20SW_HCLK RCC_CFGR3_TIM20SW_PCLK2
11557#define RCC_CFGR3_TIM2SW_HCLK RCC_CFGR3_TIM2SW_PCLK1
11558#define RCC_CFGR3_TIM34SW_HCLK RCC_CFGR3_TIM34SW_PCLK1
11559
11560/******************************************************************************/
11561/* */
11562/* Real-Time Clock (RTC) */
11563/* */
11564/******************************************************************************/
11565/*
11566* @brief Specific device feature definitions (not present on all devices in the STM32F3 series)
11567*/
11568#define RTC_TAMPER1_SUPPORT
11569#define RTC_TAMPER2_SUPPORT
11570#define RTC_TAMPER3_SUPPORT
11571#define RTC_BACKUP_SUPPORT
11572#define RTC_WAKEUP_SUPPORT
11574/******************** Bits definition for RTC_TR register *******************/
11575#define RTC_TR_PM_Pos (22U)
11576#define RTC_TR_PM_Msk (0x1UL << RTC_TR_PM_Pos)
11577#define RTC_TR_PM RTC_TR_PM_Msk
11578#define RTC_TR_HT_Pos (20U)
11579#define RTC_TR_HT_Msk (0x3UL << RTC_TR_HT_Pos)
11580#define RTC_TR_HT RTC_TR_HT_Msk
11581#define RTC_TR_HT_0 (0x1UL << RTC_TR_HT_Pos)
11582#define RTC_TR_HT_1 (0x2UL << RTC_TR_HT_Pos)
11583#define RTC_TR_HU_Pos (16U)
11584#define RTC_TR_HU_Msk (0xFUL << RTC_TR_HU_Pos)
11585#define RTC_TR_HU RTC_TR_HU_Msk
11586#define RTC_TR_HU_0 (0x1UL << RTC_TR_HU_Pos)
11587#define RTC_TR_HU_1 (0x2UL << RTC_TR_HU_Pos)
11588#define RTC_TR_HU_2 (0x4UL << RTC_TR_HU_Pos)
11589#define RTC_TR_HU_3 (0x8UL << RTC_TR_HU_Pos)
11590#define RTC_TR_MNT_Pos (12U)
11591#define RTC_TR_MNT_Msk (0x7UL << RTC_TR_MNT_Pos)
11592#define RTC_TR_MNT RTC_TR_MNT_Msk
11593#define RTC_TR_MNT_0 (0x1UL << RTC_TR_MNT_Pos)
11594#define RTC_TR_MNT_1 (0x2UL << RTC_TR_MNT_Pos)
11595#define RTC_TR_MNT_2 (0x4UL << RTC_TR_MNT_Pos)
11596#define RTC_TR_MNU_Pos (8U)
11597#define RTC_TR_MNU_Msk (0xFUL << RTC_TR_MNU_Pos)
11598#define RTC_TR_MNU RTC_TR_MNU_Msk
11599#define RTC_TR_MNU_0 (0x1UL << RTC_TR_MNU_Pos)
11600#define RTC_TR_MNU_1 (0x2UL << RTC_TR_MNU_Pos)
11601#define RTC_TR_MNU_2 (0x4UL << RTC_TR_MNU_Pos)
11602#define RTC_TR_MNU_3 (0x8UL << RTC_TR_MNU_Pos)
11603#define RTC_TR_ST_Pos (4U)
11604#define RTC_TR_ST_Msk (0x7UL << RTC_TR_ST_Pos)
11605#define RTC_TR_ST RTC_TR_ST_Msk
11606#define RTC_TR_ST_0 (0x1UL << RTC_TR_ST_Pos)
11607#define RTC_TR_ST_1 (0x2UL << RTC_TR_ST_Pos)
11608#define RTC_TR_ST_2 (0x4UL << RTC_TR_ST_Pos)
11609#define RTC_TR_SU_Pos (0U)
11610#define RTC_TR_SU_Msk (0xFUL << RTC_TR_SU_Pos)
11611#define RTC_TR_SU RTC_TR_SU_Msk
11612#define RTC_TR_SU_0 (0x1UL << RTC_TR_SU_Pos)
11613#define RTC_TR_SU_1 (0x2UL << RTC_TR_SU_Pos)
11614#define RTC_TR_SU_2 (0x4UL << RTC_TR_SU_Pos)
11615#define RTC_TR_SU_3 (0x8UL << RTC_TR_SU_Pos)
11617/******************** Bits definition for RTC_DR register *******************/
11618#define RTC_DR_YT_Pos (20U)
11619#define RTC_DR_YT_Msk (0xFUL << RTC_DR_YT_Pos)
11620#define RTC_DR_YT RTC_DR_YT_Msk
11621#define RTC_DR_YT_0 (0x1UL << RTC_DR_YT_Pos)
11622#define RTC_DR_YT_1 (0x2UL << RTC_DR_YT_Pos)
11623#define RTC_DR_YT_2 (0x4UL << RTC_DR_YT_Pos)
11624#define RTC_DR_YT_3 (0x8UL << RTC_DR_YT_Pos)
11625#define RTC_DR_YU_Pos (16U)
11626#define RTC_DR_YU_Msk (0xFUL << RTC_DR_YU_Pos)
11627#define RTC_DR_YU RTC_DR_YU_Msk
11628#define RTC_DR_YU_0 (0x1UL << RTC_DR_YU_Pos)
11629#define RTC_DR_YU_1 (0x2UL << RTC_DR_YU_Pos)
11630#define RTC_DR_YU_2 (0x4UL << RTC_DR_YU_Pos)
11631#define RTC_DR_YU_3 (0x8UL << RTC_DR_YU_Pos)
11632#define RTC_DR_WDU_Pos (13U)
11633#define RTC_DR_WDU_Msk (0x7UL << RTC_DR_WDU_Pos)
11634#define RTC_DR_WDU RTC_DR_WDU_Msk
11635#define RTC_DR_WDU_0 (0x1UL << RTC_DR_WDU_Pos)
11636#define RTC_DR_WDU_1 (0x2UL << RTC_DR_WDU_Pos)
11637#define RTC_DR_WDU_2 (0x4UL << RTC_DR_WDU_Pos)
11638#define RTC_DR_MT_Pos (12U)
11639#define RTC_DR_MT_Msk (0x1UL << RTC_DR_MT_Pos)
11640#define RTC_DR_MT RTC_DR_MT_Msk
11641#define RTC_DR_MU_Pos (8U)
11642#define RTC_DR_MU_Msk (0xFUL << RTC_DR_MU_Pos)
11643#define RTC_DR_MU RTC_DR_MU_Msk
11644#define RTC_DR_MU_0 (0x1UL << RTC_DR_MU_Pos)
11645#define RTC_DR_MU_1 (0x2UL << RTC_DR_MU_Pos)
11646#define RTC_DR_MU_2 (0x4UL << RTC_DR_MU_Pos)
11647#define RTC_DR_MU_3 (0x8UL << RTC_DR_MU_Pos)
11648#define RTC_DR_DT_Pos (4U)
11649#define RTC_DR_DT_Msk (0x3UL << RTC_DR_DT_Pos)
11650#define RTC_DR_DT RTC_DR_DT_Msk
11651#define RTC_DR_DT_0 (0x1UL << RTC_DR_DT_Pos)
11652#define RTC_DR_DT_1 (0x2UL << RTC_DR_DT_Pos)
11653#define RTC_DR_DU_Pos (0U)
11654#define RTC_DR_DU_Msk (0xFUL << RTC_DR_DU_Pos)
11655#define RTC_DR_DU RTC_DR_DU_Msk
11656#define RTC_DR_DU_0 (0x1UL << RTC_DR_DU_Pos)
11657#define RTC_DR_DU_1 (0x2UL << RTC_DR_DU_Pos)
11658#define RTC_DR_DU_2 (0x4UL << RTC_DR_DU_Pos)
11659#define RTC_DR_DU_3 (0x8UL << RTC_DR_DU_Pos)
11661/******************** Bits definition for RTC_CR register *******************/
11662#define RTC_CR_COE_Pos (23U)
11663#define RTC_CR_COE_Msk (0x1UL << RTC_CR_COE_Pos)
11664#define RTC_CR_COE RTC_CR_COE_Msk
11665#define RTC_CR_OSEL_Pos (21U)
11666#define RTC_CR_OSEL_Msk (0x3UL << RTC_CR_OSEL_Pos)
11667#define RTC_CR_OSEL RTC_CR_OSEL_Msk
11668#define RTC_CR_OSEL_0 (0x1UL << RTC_CR_OSEL_Pos)
11669#define RTC_CR_OSEL_1 (0x2UL << RTC_CR_OSEL_Pos)
11670#define RTC_CR_POL_Pos (20U)
11671#define RTC_CR_POL_Msk (0x1UL << RTC_CR_POL_Pos)
11672#define RTC_CR_POL RTC_CR_POL_Msk
11673#define RTC_CR_COSEL_Pos (19U)
11674#define RTC_CR_COSEL_Msk (0x1UL << RTC_CR_COSEL_Pos)
11675#define RTC_CR_COSEL RTC_CR_COSEL_Msk
11676#define RTC_CR_BKP_Pos (18U)
11677#define RTC_CR_BKP_Msk (0x1UL << RTC_CR_BKP_Pos)
11678#define RTC_CR_BKP RTC_CR_BKP_Msk
11679#define RTC_CR_SUB1H_Pos (17U)
11680#define RTC_CR_SUB1H_Msk (0x1UL << RTC_CR_SUB1H_Pos)
11681#define RTC_CR_SUB1H RTC_CR_SUB1H_Msk
11682#define RTC_CR_ADD1H_Pos (16U)
11683#define RTC_CR_ADD1H_Msk (0x1UL << RTC_CR_ADD1H_Pos)
11684#define RTC_CR_ADD1H RTC_CR_ADD1H_Msk
11685#define RTC_CR_TSIE_Pos (15U)
11686#define RTC_CR_TSIE_Msk (0x1UL << RTC_CR_TSIE_Pos)
11687#define RTC_CR_TSIE RTC_CR_TSIE_Msk
11688#define RTC_CR_WUTIE_Pos (14U)
11689#define RTC_CR_WUTIE_Msk (0x1UL << RTC_CR_WUTIE_Pos)
11690#define RTC_CR_WUTIE RTC_CR_WUTIE_Msk
11691#define RTC_CR_ALRBIE_Pos (13U)
11692#define RTC_CR_ALRBIE_Msk (0x1UL << RTC_CR_ALRBIE_Pos)
11693#define RTC_CR_ALRBIE RTC_CR_ALRBIE_Msk
11694#define RTC_CR_ALRAIE_Pos (12U)
11695#define RTC_CR_ALRAIE_Msk (0x1UL << RTC_CR_ALRAIE_Pos)
11696#define RTC_CR_ALRAIE RTC_CR_ALRAIE_Msk
11697#define RTC_CR_TSE_Pos (11U)
11698#define RTC_CR_TSE_Msk (0x1UL << RTC_CR_TSE_Pos)
11699#define RTC_CR_TSE RTC_CR_TSE_Msk
11700#define RTC_CR_WUTE_Pos (10U)
11701#define RTC_CR_WUTE_Msk (0x1UL << RTC_CR_WUTE_Pos)
11702#define RTC_CR_WUTE RTC_CR_WUTE_Msk
11703#define RTC_CR_ALRBE_Pos (9U)
11704#define RTC_CR_ALRBE_Msk (0x1UL << RTC_CR_ALRBE_Pos)
11705#define RTC_CR_ALRBE RTC_CR_ALRBE_Msk
11706#define RTC_CR_ALRAE_Pos (8U)
11707#define RTC_CR_ALRAE_Msk (0x1UL << RTC_CR_ALRAE_Pos)
11708#define RTC_CR_ALRAE RTC_CR_ALRAE_Msk
11709#define RTC_CR_FMT_Pos (6U)
11710#define RTC_CR_FMT_Msk (0x1UL << RTC_CR_FMT_Pos)
11711#define RTC_CR_FMT RTC_CR_FMT_Msk
11712#define RTC_CR_BYPSHAD_Pos (5U)
11713#define RTC_CR_BYPSHAD_Msk (0x1UL << RTC_CR_BYPSHAD_Pos)
11714#define RTC_CR_BYPSHAD RTC_CR_BYPSHAD_Msk
11715#define RTC_CR_REFCKON_Pos (4U)
11716#define RTC_CR_REFCKON_Msk (0x1UL << RTC_CR_REFCKON_Pos)
11717#define RTC_CR_REFCKON RTC_CR_REFCKON_Msk
11718#define RTC_CR_TSEDGE_Pos (3U)
11719#define RTC_CR_TSEDGE_Msk (0x1UL << RTC_CR_TSEDGE_Pos)
11720#define RTC_CR_TSEDGE RTC_CR_TSEDGE_Msk
11721#define RTC_CR_WUCKSEL_Pos (0U)
11722#define RTC_CR_WUCKSEL_Msk (0x7UL << RTC_CR_WUCKSEL_Pos)
11723#define RTC_CR_WUCKSEL RTC_CR_WUCKSEL_Msk
11724#define RTC_CR_WUCKSEL_0 (0x1UL << RTC_CR_WUCKSEL_Pos)
11725#define RTC_CR_WUCKSEL_1 (0x2UL << RTC_CR_WUCKSEL_Pos)
11726#define RTC_CR_WUCKSEL_2 (0x4UL << RTC_CR_WUCKSEL_Pos)
11728/* Legacy defines */
11729#define RTC_CR_BCK_Pos RTC_CR_BKP_Pos
11730#define RTC_CR_BCK_Msk RTC_CR_BKP_Msk
11731#define RTC_CR_BCK RTC_CR_BKP
11732
11733/******************** Bits definition for RTC_ISR register ******************/
11734#define RTC_ISR_RECALPF_Pos (16U)
11735#define RTC_ISR_RECALPF_Msk (0x1UL << RTC_ISR_RECALPF_Pos)
11736#define RTC_ISR_RECALPF RTC_ISR_RECALPF_Msk
11737#define RTC_ISR_TAMP3F_Pos (15U)
11738#define RTC_ISR_TAMP3F_Msk (0x1UL << RTC_ISR_TAMP3F_Pos)
11739#define RTC_ISR_TAMP3F RTC_ISR_TAMP3F_Msk
11740#define RTC_ISR_TAMP2F_Pos (14U)
11741#define RTC_ISR_TAMP2F_Msk (0x1UL << RTC_ISR_TAMP2F_Pos)
11742#define RTC_ISR_TAMP2F RTC_ISR_TAMP2F_Msk
11743#define RTC_ISR_TAMP1F_Pos (13U)
11744#define RTC_ISR_TAMP1F_Msk (0x1UL << RTC_ISR_TAMP1F_Pos)
11745#define RTC_ISR_TAMP1F RTC_ISR_TAMP1F_Msk
11746#define RTC_ISR_TSOVF_Pos (12U)
11747#define RTC_ISR_TSOVF_Msk (0x1UL << RTC_ISR_TSOVF_Pos)
11748#define RTC_ISR_TSOVF RTC_ISR_TSOVF_Msk
11749#define RTC_ISR_TSF_Pos (11U)
11750#define RTC_ISR_TSF_Msk (0x1UL << RTC_ISR_TSF_Pos)
11751#define RTC_ISR_TSF RTC_ISR_TSF_Msk
11752#define RTC_ISR_WUTF_Pos (10U)
11753#define RTC_ISR_WUTF_Msk (0x1UL << RTC_ISR_WUTF_Pos)
11754#define RTC_ISR_WUTF RTC_ISR_WUTF_Msk
11755#define RTC_ISR_ALRBF_Pos (9U)
11756#define RTC_ISR_ALRBF_Msk (0x1UL << RTC_ISR_ALRBF_Pos)
11757#define RTC_ISR_ALRBF RTC_ISR_ALRBF_Msk
11758#define RTC_ISR_ALRAF_Pos (8U)
11759#define RTC_ISR_ALRAF_Msk (0x1UL << RTC_ISR_ALRAF_Pos)
11760#define RTC_ISR_ALRAF RTC_ISR_ALRAF_Msk
11761#define RTC_ISR_INIT_Pos (7U)
11762#define RTC_ISR_INIT_Msk (0x1UL << RTC_ISR_INIT_Pos)
11763#define RTC_ISR_INIT RTC_ISR_INIT_Msk
11764#define RTC_ISR_INITF_Pos (6U)
11765#define RTC_ISR_INITF_Msk (0x1UL << RTC_ISR_INITF_Pos)
11766#define RTC_ISR_INITF RTC_ISR_INITF_Msk
11767#define RTC_ISR_RSF_Pos (5U)
11768#define RTC_ISR_RSF_Msk (0x1UL << RTC_ISR_RSF_Pos)
11769#define RTC_ISR_RSF RTC_ISR_RSF_Msk
11770#define RTC_ISR_INITS_Pos (4U)
11771#define RTC_ISR_INITS_Msk (0x1UL << RTC_ISR_INITS_Pos)
11772#define RTC_ISR_INITS RTC_ISR_INITS_Msk
11773#define RTC_ISR_SHPF_Pos (3U)
11774#define RTC_ISR_SHPF_Msk (0x1UL << RTC_ISR_SHPF_Pos)
11775#define RTC_ISR_SHPF RTC_ISR_SHPF_Msk
11776#define RTC_ISR_WUTWF_Pos (2U)
11777#define RTC_ISR_WUTWF_Msk (0x1UL << RTC_ISR_WUTWF_Pos)
11778#define RTC_ISR_WUTWF RTC_ISR_WUTWF_Msk
11779#define RTC_ISR_ALRBWF_Pos (1U)
11780#define RTC_ISR_ALRBWF_Msk (0x1UL << RTC_ISR_ALRBWF_Pos)
11781#define RTC_ISR_ALRBWF RTC_ISR_ALRBWF_Msk
11782#define RTC_ISR_ALRAWF_Pos (0U)
11783#define RTC_ISR_ALRAWF_Msk (0x1UL << RTC_ISR_ALRAWF_Pos)
11784#define RTC_ISR_ALRAWF RTC_ISR_ALRAWF_Msk
11785
11786/******************** Bits definition for RTC_PRER register *****************/
11787#define RTC_PRER_PREDIV_A_Pos (16U)
11788#define RTC_PRER_PREDIV_A_Msk (0x7FUL << RTC_PRER_PREDIV_A_Pos)
11789#define RTC_PRER_PREDIV_A RTC_PRER_PREDIV_A_Msk
11790#define RTC_PRER_PREDIV_S_Pos (0U)
11791#define RTC_PRER_PREDIV_S_Msk (0x7FFFUL << RTC_PRER_PREDIV_S_Pos)
11792#define RTC_PRER_PREDIV_S RTC_PRER_PREDIV_S_Msk
11793
11794/******************** Bits definition for RTC_WUTR register *****************/
11795#define RTC_WUTR_WUT_Pos (0U)
11796#define RTC_WUTR_WUT_Msk (0xFFFFUL << RTC_WUTR_WUT_Pos)
11797#define RTC_WUTR_WUT RTC_WUTR_WUT_Msk
11798
11799/******************** Bits definition for RTC_ALRMAR register ***************/
11800#define RTC_ALRMAR_MSK4_Pos (31U)
11801#define RTC_ALRMAR_MSK4_Msk (0x1UL << RTC_ALRMAR_MSK4_Pos)
11802#define RTC_ALRMAR_MSK4 RTC_ALRMAR_MSK4_Msk
11803#define RTC_ALRMAR_WDSEL_Pos (30U)
11804#define RTC_ALRMAR_WDSEL_Msk (0x1UL << RTC_ALRMAR_WDSEL_Pos)
11805#define RTC_ALRMAR_WDSEL RTC_ALRMAR_WDSEL_Msk
11806#define RTC_ALRMAR_DT_Pos (28U)
11807#define RTC_ALRMAR_DT_Msk (0x3UL << RTC_ALRMAR_DT_Pos)
11808#define RTC_ALRMAR_DT RTC_ALRMAR_DT_Msk
11809#define RTC_ALRMAR_DT_0 (0x1UL << RTC_ALRMAR_DT_Pos)
11810#define RTC_ALRMAR_DT_1 (0x2UL << RTC_ALRMAR_DT_Pos)
11811#define RTC_ALRMAR_DU_Pos (24U)
11812#define RTC_ALRMAR_DU_Msk (0xFUL << RTC_ALRMAR_DU_Pos)
11813#define RTC_ALRMAR_DU RTC_ALRMAR_DU_Msk
11814#define RTC_ALRMAR_DU_0 (0x1UL << RTC_ALRMAR_DU_Pos)
11815#define RTC_ALRMAR_DU_1 (0x2UL << RTC_ALRMAR_DU_Pos)
11816#define RTC_ALRMAR_DU_2 (0x4UL << RTC_ALRMAR_DU_Pos)
11817#define RTC_ALRMAR_DU_3 (0x8UL << RTC_ALRMAR_DU_Pos)
11818#define RTC_ALRMAR_MSK3_Pos (23U)
11819#define RTC_ALRMAR_MSK3_Msk (0x1UL << RTC_ALRMAR_MSK3_Pos)
11820#define RTC_ALRMAR_MSK3 RTC_ALRMAR_MSK3_Msk
11821#define RTC_ALRMAR_PM_Pos (22U)
11822#define RTC_ALRMAR_PM_Msk (0x1UL << RTC_ALRMAR_PM_Pos)
11823#define RTC_ALRMAR_PM RTC_ALRMAR_PM_Msk
11824#define RTC_ALRMAR_HT_Pos (20U)
11825#define RTC_ALRMAR_HT_Msk (0x3UL << RTC_ALRMAR_HT_Pos)
11826#define RTC_ALRMAR_HT RTC_ALRMAR_HT_Msk
11827#define RTC_ALRMAR_HT_0 (0x1UL << RTC_ALRMAR_HT_Pos)
11828#define RTC_ALRMAR_HT_1 (0x2UL << RTC_ALRMAR_HT_Pos)
11829#define RTC_ALRMAR_HU_Pos (16U)
11830#define RTC_ALRMAR_HU_Msk (0xFUL << RTC_ALRMAR_HU_Pos)
11831#define RTC_ALRMAR_HU RTC_ALRMAR_HU_Msk
11832#define RTC_ALRMAR_HU_0 (0x1UL << RTC_ALRMAR_HU_Pos)
11833#define RTC_ALRMAR_HU_1 (0x2UL << RTC_ALRMAR_HU_Pos)
11834#define RTC_ALRMAR_HU_2 (0x4UL << RTC_ALRMAR_HU_Pos)
11835#define RTC_ALRMAR_HU_3 (0x8UL << RTC_ALRMAR_HU_Pos)
11836#define RTC_ALRMAR_MSK2_Pos (15U)
11837#define RTC_ALRMAR_MSK2_Msk (0x1UL << RTC_ALRMAR_MSK2_Pos)
11838#define RTC_ALRMAR_MSK2 RTC_ALRMAR_MSK2_Msk
11839#define RTC_ALRMAR_MNT_Pos (12U)
11840#define RTC_ALRMAR_MNT_Msk (0x7UL << RTC_ALRMAR_MNT_Pos)
11841#define RTC_ALRMAR_MNT RTC_ALRMAR_MNT_Msk
11842#define RTC_ALRMAR_MNT_0 (0x1UL << RTC_ALRMAR_MNT_Pos)
11843#define RTC_ALRMAR_MNT_1 (0x2UL << RTC_ALRMAR_MNT_Pos)
11844#define RTC_ALRMAR_MNT_2 (0x4UL << RTC_ALRMAR_MNT_Pos)
11845#define RTC_ALRMAR_MNU_Pos (8U)
11846#define RTC_ALRMAR_MNU_Msk (0xFUL << RTC_ALRMAR_MNU_Pos)
11847#define RTC_ALRMAR_MNU RTC_ALRMAR_MNU_Msk
11848#define RTC_ALRMAR_MNU_0 (0x1UL << RTC_ALRMAR_MNU_Pos)
11849#define RTC_ALRMAR_MNU_1 (0x2UL << RTC_ALRMAR_MNU_Pos)
11850#define RTC_ALRMAR_MNU_2 (0x4UL << RTC_ALRMAR_MNU_Pos)
11851#define RTC_ALRMAR_MNU_3 (0x8UL << RTC_ALRMAR_MNU_Pos)
11852#define RTC_ALRMAR_MSK1_Pos (7U)
11853#define RTC_ALRMAR_MSK1_Msk (0x1UL << RTC_ALRMAR_MSK1_Pos)
11854#define RTC_ALRMAR_MSK1 RTC_ALRMAR_MSK1_Msk
11855#define RTC_ALRMAR_ST_Pos (4U)
11856#define RTC_ALRMAR_ST_Msk (0x7UL << RTC_ALRMAR_ST_Pos)
11857#define RTC_ALRMAR_ST RTC_ALRMAR_ST_Msk
11858#define RTC_ALRMAR_ST_0 (0x1UL << RTC_ALRMAR_ST_Pos)
11859#define RTC_ALRMAR_ST_1 (0x2UL << RTC_ALRMAR_ST_Pos)
11860#define RTC_ALRMAR_ST_2 (0x4UL << RTC_ALRMAR_ST_Pos)
11861#define RTC_ALRMAR_SU_Pos (0U)
11862#define RTC_ALRMAR_SU_Msk (0xFUL << RTC_ALRMAR_SU_Pos)
11863#define RTC_ALRMAR_SU RTC_ALRMAR_SU_Msk
11864#define RTC_ALRMAR_SU_0 (0x1UL << RTC_ALRMAR_SU_Pos)
11865#define RTC_ALRMAR_SU_1 (0x2UL << RTC_ALRMAR_SU_Pos)
11866#define RTC_ALRMAR_SU_2 (0x4UL << RTC_ALRMAR_SU_Pos)
11867#define RTC_ALRMAR_SU_3 (0x8UL << RTC_ALRMAR_SU_Pos)
11869/******************** Bits definition for RTC_ALRMBR register ***************/
11870#define RTC_ALRMBR_MSK4_Pos (31U)
11871#define RTC_ALRMBR_MSK4_Msk (0x1UL << RTC_ALRMBR_MSK4_Pos)
11872#define RTC_ALRMBR_MSK4 RTC_ALRMBR_MSK4_Msk
11873#define RTC_ALRMBR_WDSEL_Pos (30U)
11874#define RTC_ALRMBR_WDSEL_Msk (0x1UL << RTC_ALRMBR_WDSEL_Pos)
11875#define RTC_ALRMBR_WDSEL RTC_ALRMBR_WDSEL_Msk
11876#define RTC_ALRMBR_DT_Pos (28U)
11877#define RTC_ALRMBR_DT_Msk (0x3UL << RTC_ALRMBR_DT_Pos)
11878#define RTC_ALRMBR_DT RTC_ALRMBR_DT_Msk
11879#define RTC_ALRMBR_DT_0 (0x1UL << RTC_ALRMBR_DT_Pos)
11880#define RTC_ALRMBR_DT_1 (0x2UL << RTC_ALRMBR_DT_Pos)
11881#define RTC_ALRMBR_DU_Pos (24U)
11882#define RTC_ALRMBR_DU_Msk (0xFUL << RTC_ALRMBR_DU_Pos)
11883#define RTC_ALRMBR_DU RTC_ALRMBR_DU_Msk
11884#define RTC_ALRMBR_DU_0 (0x1UL << RTC_ALRMBR_DU_Pos)
11885#define RTC_ALRMBR_DU_1 (0x2UL << RTC_ALRMBR_DU_Pos)
11886#define RTC_ALRMBR_DU_2 (0x4UL << RTC_ALRMBR_DU_Pos)
11887#define RTC_ALRMBR_DU_3 (0x8UL << RTC_ALRMBR_DU_Pos)
11888#define RTC_ALRMBR_MSK3_Pos (23U)
11889#define RTC_ALRMBR_MSK3_Msk (0x1UL << RTC_ALRMBR_MSK3_Pos)
11890#define RTC_ALRMBR_MSK3 RTC_ALRMBR_MSK3_Msk
11891#define RTC_ALRMBR_PM_Pos (22U)
11892#define RTC_ALRMBR_PM_Msk (0x1UL << RTC_ALRMBR_PM_Pos)
11893#define RTC_ALRMBR_PM RTC_ALRMBR_PM_Msk
11894#define RTC_ALRMBR_HT_Pos (20U)
11895#define RTC_ALRMBR_HT_Msk (0x3UL << RTC_ALRMBR_HT_Pos)
11896#define RTC_ALRMBR_HT RTC_ALRMBR_HT_Msk
11897#define RTC_ALRMBR_HT_0 (0x1UL << RTC_ALRMBR_HT_Pos)
11898#define RTC_ALRMBR_HT_1 (0x2UL << RTC_ALRMBR_HT_Pos)
11899#define RTC_ALRMBR_HU_Pos (16U)
11900#define RTC_ALRMBR_HU_Msk (0xFUL << RTC_ALRMBR_HU_Pos)
11901#define RTC_ALRMBR_HU RTC_ALRMBR_HU_Msk
11902#define RTC_ALRMBR_HU_0 (0x1UL << RTC_ALRMBR_HU_Pos)
11903#define RTC_ALRMBR_HU_1 (0x2UL << RTC_ALRMBR_HU_Pos)
11904#define RTC_ALRMBR_HU_2 (0x4UL << RTC_ALRMBR_HU_Pos)
11905#define RTC_ALRMBR_HU_3 (0x8UL << RTC_ALRMBR_HU_Pos)
11906#define RTC_ALRMBR_MSK2_Pos (15U)
11907#define RTC_ALRMBR_MSK2_Msk (0x1UL << RTC_ALRMBR_MSK2_Pos)
11908#define RTC_ALRMBR_MSK2 RTC_ALRMBR_MSK2_Msk
11909#define RTC_ALRMBR_MNT_Pos (12U)
11910#define RTC_ALRMBR_MNT_Msk (0x7UL << RTC_ALRMBR_MNT_Pos)
11911#define RTC_ALRMBR_MNT RTC_ALRMBR_MNT_Msk
11912#define RTC_ALRMBR_MNT_0 (0x1UL << RTC_ALRMBR_MNT_Pos)
11913#define RTC_ALRMBR_MNT_1 (0x2UL << RTC_ALRMBR_MNT_Pos)
11914#define RTC_ALRMBR_MNT_2 (0x4UL << RTC_ALRMBR_MNT_Pos)
11915#define RTC_ALRMBR_MNU_Pos (8U)
11916#define RTC_ALRMBR_MNU_Msk (0xFUL << RTC_ALRMBR_MNU_Pos)
11917#define RTC_ALRMBR_MNU RTC_ALRMBR_MNU_Msk
11918#define RTC_ALRMBR_MNU_0 (0x1UL << RTC_ALRMBR_MNU_Pos)
11919#define RTC_ALRMBR_MNU_1 (0x2UL << RTC_ALRMBR_MNU_Pos)
11920#define RTC_ALRMBR_MNU_2 (0x4UL << RTC_ALRMBR_MNU_Pos)
11921#define RTC_ALRMBR_MNU_3 (0x8UL << RTC_ALRMBR_MNU_Pos)
11922#define RTC_ALRMBR_MSK1_Pos (7U)
11923#define RTC_ALRMBR_MSK1_Msk (0x1UL << RTC_ALRMBR_MSK1_Pos)
11924#define RTC_ALRMBR_MSK1 RTC_ALRMBR_MSK1_Msk
11925#define RTC_ALRMBR_ST_Pos (4U)
11926#define RTC_ALRMBR_ST_Msk (0x7UL << RTC_ALRMBR_ST_Pos)
11927#define RTC_ALRMBR_ST RTC_ALRMBR_ST_Msk
11928#define RTC_ALRMBR_ST_0 (0x1UL << RTC_ALRMBR_ST_Pos)
11929#define RTC_ALRMBR_ST_1 (0x2UL << RTC_ALRMBR_ST_Pos)
11930#define RTC_ALRMBR_ST_2 (0x4UL << RTC_ALRMBR_ST_Pos)
11931#define RTC_ALRMBR_SU_Pos (0U)
11932#define RTC_ALRMBR_SU_Msk (0xFUL << RTC_ALRMBR_SU_Pos)
11933#define RTC_ALRMBR_SU RTC_ALRMBR_SU_Msk
11934#define RTC_ALRMBR_SU_0 (0x1UL << RTC_ALRMBR_SU_Pos)
11935#define RTC_ALRMBR_SU_1 (0x2UL << RTC_ALRMBR_SU_Pos)
11936#define RTC_ALRMBR_SU_2 (0x4UL << RTC_ALRMBR_SU_Pos)
11937#define RTC_ALRMBR_SU_3 (0x8UL << RTC_ALRMBR_SU_Pos)
11939/******************** Bits definition for RTC_WPR register ******************/
11940#define RTC_WPR_KEY_Pos (0U)
11941#define RTC_WPR_KEY_Msk (0xFFUL << RTC_WPR_KEY_Pos)
11942#define RTC_WPR_KEY RTC_WPR_KEY_Msk
11943
11944/******************** Bits definition for RTC_SSR register ******************/
11945#define RTC_SSR_SS_Pos (0U)
11946#define RTC_SSR_SS_Msk (0xFFFFUL << RTC_SSR_SS_Pos)
11947#define RTC_SSR_SS RTC_SSR_SS_Msk
11948
11949/******************** Bits definition for RTC_SHIFTR register ***************/
11950#define RTC_SHIFTR_SUBFS_Pos (0U)
11951#define RTC_SHIFTR_SUBFS_Msk (0x7FFFUL << RTC_SHIFTR_SUBFS_Pos)
11952#define RTC_SHIFTR_SUBFS RTC_SHIFTR_SUBFS_Msk
11953#define RTC_SHIFTR_ADD1S_Pos (31U)
11954#define RTC_SHIFTR_ADD1S_Msk (0x1UL << RTC_SHIFTR_ADD1S_Pos)
11955#define RTC_SHIFTR_ADD1S RTC_SHIFTR_ADD1S_Msk
11956
11957/******************** Bits definition for RTC_TSTR register *****************/
11958#define RTC_TSTR_PM_Pos (22U)
11959#define RTC_TSTR_PM_Msk (0x1UL << RTC_TSTR_PM_Pos)
11960#define RTC_TSTR_PM RTC_TSTR_PM_Msk
11961#define RTC_TSTR_HT_Pos (20U)
11962#define RTC_TSTR_HT_Msk (0x3UL << RTC_TSTR_HT_Pos)
11963#define RTC_TSTR_HT RTC_TSTR_HT_Msk
11964#define RTC_TSTR_HT_0 (0x1UL << RTC_TSTR_HT_Pos)
11965#define RTC_TSTR_HT_1 (0x2UL << RTC_TSTR_HT_Pos)
11966#define RTC_TSTR_HU_Pos (16U)
11967#define RTC_TSTR_HU_Msk (0xFUL << RTC_TSTR_HU_Pos)
11968#define RTC_TSTR_HU RTC_TSTR_HU_Msk
11969#define RTC_TSTR_HU_0 (0x1UL << RTC_TSTR_HU_Pos)
11970#define RTC_TSTR_HU_1 (0x2UL << RTC_TSTR_HU_Pos)
11971#define RTC_TSTR_HU_2 (0x4UL << RTC_TSTR_HU_Pos)
11972#define RTC_TSTR_HU_3 (0x8UL << RTC_TSTR_HU_Pos)
11973#define RTC_TSTR_MNT_Pos (12U)
11974#define RTC_TSTR_MNT_Msk (0x7UL << RTC_TSTR_MNT_Pos)
11975#define RTC_TSTR_MNT RTC_TSTR_MNT_Msk
11976#define RTC_TSTR_MNT_0 (0x1UL << RTC_TSTR_MNT_Pos)
11977#define RTC_TSTR_MNT_1 (0x2UL << RTC_TSTR_MNT_Pos)
11978#define RTC_TSTR_MNT_2 (0x4UL << RTC_TSTR_MNT_Pos)
11979#define RTC_TSTR_MNU_Pos (8U)
11980#define RTC_TSTR_MNU_Msk (0xFUL << RTC_TSTR_MNU_Pos)
11981#define RTC_TSTR_MNU RTC_TSTR_MNU_Msk
11982#define RTC_TSTR_MNU_0 (0x1UL << RTC_TSTR_MNU_Pos)
11983#define RTC_TSTR_MNU_1 (0x2UL << RTC_TSTR_MNU_Pos)
11984#define RTC_TSTR_MNU_2 (0x4UL << RTC_TSTR_MNU_Pos)
11985#define RTC_TSTR_MNU_3 (0x8UL << RTC_TSTR_MNU_Pos)
11986#define RTC_TSTR_ST_Pos (4U)
11987#define RTC_TSTR_ST_Msk (0x7UL << RTC_TSTR_ST_Pos)
11988#define RTC_TSTR_ST RTC_TSTR_ST_Msk
11989#define RTC_TSTR_ST_0 (0x1UL << RTC_TSTR_ST_Pos)
11990#define RTC_TSTR_ST_1 (0x2UL << RTC_TSTR_ST_Pos)
11991#define RTC_TSTR_ST_2 (0x4UL << RTC_TSTR_ST_Pos)
11992#define RTC_TSTR_SU_Pos (0U)
11993#define RTC_TSTR_SU_Msk (0xFUL << RTC_TSTR_SU_Pos)
11994#define RTC_TSTR_SU RTC_TSTR_SU_Msk
11995#define RTC_TSTR_SU_0 (0x1UL << RTC_TSTR_SU_Pos)
11996#define RTC_TSTR_SU_1 (0x2UL << RTC_TSTR_SU_Pos)
11997#define RTC_TSTR_SU_2 (0x4UL << RTC_TSTR_SU_Pos)
11998#define RTC_TSTR_SU_3 (0x8UL << RTC_TSTR_SU_Pos)
12000/******************** Bits definition for RTC_TSDR register *****************/
12001#define RTC_TSDR_WDU_Pos (13U)
12002#define RTC_TSDR_WDU_Msk (0x7UL << RTC_TSDR_WDU_Pos)
12003#define RTC_TSDR_WDU RTC_TSDR_WDU_Msk
12004#define RTC_TSDR_WDU_0 (0x1UL << RTC_TSDR_WDU_Pos)
12005#define RTC_TSDR_WDU_1 (0x2UL << RTC_TSDR_WDU_Pos)
12006#define RTC_TSDR_WDU_2 (0x4UL << RTC_TSDR_WDU_Pos)
12007#define RTC_TSDR_MT_Pos (12U)
12008#define RTC_TSDR_MT_Msk (0x1UL << RTC_TSDR_MT_Pos)
12009#define RTC_TSDR_MT RTC_TSDR_MT_Msk
12010#define RTC_TSDR_MU_Pos (8U)
12011#define RTC_TSDR_MU_Msk (0xFUL << RTC_TSDR_MU_Pos)
12012#define RTC_TSDR_MU RTC_TSDR_MU_Msk
12013#define RTC_TSDR_MU_0 (0x1UL << RTC_TSDR_MU_Pos)
12014#define RTC_TSDR_MU_1 (0x2UL << RTC_TSDR_MU_Pos)
12015#define RTC_TSDR_MU_2 (0x4UL << RTC_TSDR_MU_Pos)
12016#define RTC_TSDR_MU_3 (0x8UL << RTC_TSDR_MU_Pos)
12017#define RTC_TSDR_DT_Pos (4U)
12018#define RTC_TSDR_DT_Msk (0x3UL << RTC_TSDR_DT_Pos)
12019#define RTC_TSDR_DT RTC_TSDR_DT_Msk
12020#define RTC_TSDR_DT_0 (0x1UL << RTC_TSDR_DT_Pos)
12021#define RTC_TSDR_DT_1 (0x2UL << RTC_TSDR_DT_Pos)
12022#define RTC_TSDR_DU_Pos (0U)
12023#define RTC_TSDR_DU_Msk (0xFUL << RTC_TSDR_DU_Pos)
12024#define RTC_TSDR_DU RTC_TSDR_DU_Msk
12025#define RTC_TSDR_DU_0 (0x1UL << RTC_TSDR_DU_Pos)
12026#define RTC_TSDR_DU_1 (0x2UL << RTC_TSDR_DU_Pos)
12027#define RTC_TSDR_DU_2 (0x4UL << RTC_TSDR_DU_Pos)
12028#define RTC_TSDR_DU_3 (0x8UL << RTC_TSDR_DU_Pos)
12030/******************** Bits definition for RTC_TSSSR register ****************/
12031#define RTC_TSSSR_SS_Pos (0U)
12032#define RTC_TSSSR_SS_Msk (0xFFFFUL << RTC_TSSSR_SS_Pos)
12033#define RTC_TSSSR_SS RTC_TSSSR_SS_Msk
12034
12035/******************** Bits definition for RTC_CAL register *****************/
12036#define RTC_CALR_CALP_Pos (15U)
12037#define RTC_CALR_CALP_Msk (0x1UL << RTC_CALR_CALP_Pos)
12038#define RTC_CALR_CALP RTC_CALR_CALP_Msk
12039#define RTC_CALR_CALW8_Pos (14U)
12040#define RTC_CALR_CALW8_Msk (0x1UL << RTC_CALR_CALW8_Pos)
12041#define RTC_CALR_CALW8 RTC_CALR_CALW8_Msk
12042#define RTC_CALR_CALW16_Pos (13U)
12043#define RTC_CALR_CALW16_Msk (0x1UL << RTC_CALR_CALW16_Pos)
12044#define RTC_CALR_CALW16 RTC_CALR_CALW16_Msk
12045#define RTC_CALR_CALM_Pos (0U)
12046#define RTC_CALR_CALM_Msk (0x1FFUL << RTC_CALR_CALM_Pos)
12047#define RTC_CALR_CALM RTC_CALR_CALM_Msk
12048#define RTC_CALR_CALM_0 (0x001UL << RTC_CALR_CALM_Pos)
12049#define RTC_CALR_CALM_1 (0x002UL << RTC_CALR_CALM_Pos)
12050#define RTC_CALR_CALM_2 (0x004UL << RTC_CALR_CALM_Pos)
12051#define RTC_CALR_CALM_3 (0x008UL << RTC_CALR_CALM_Pos)
12052#define RTC_CALR_CALM_4 (0x010UL << RTC_CALR_CALM_Pos)
12053#define RTC_CALR_CALM_5 (0x020UL << RTC_CALR_CALM_Pos)
12054#define RTC_CALR_CALM_6 (0x040UL << RTC_CALR_CALM_Pos)
12055#define RTC_CALR_CALM_7 (0x080UL << RTC_CALR_CALM_Pos)
12056#define RTC_CALR_CALM_8 (0x100UL << RTC_CALR_CALM_Pos)
12058/******************** Bits definition for RTC_TAFCR register ****************/
12059#define RTC_TAFCR_PC15MODE_Pos (23U)
12060#define RTC_TAFCR_PC15MODE_Msk (0x1UL << RTC_TAFCR_PC15MODE_Pos)
12061#define RTC_TAFCR_PC15MODE RTC_TAFCR_PC15MODE_Msk
12062#define RTC_TAFCR_PC15VALUE_Pos (22U)
12063#define RTC_TAFCR_PC15VALUE_Msk (0x1UL << RTC_TAFCR_PC15VALUE_Pos)
12064#define RTC_TAFCR_PC15VALUE RTC_TAFCR_PC15VALUE_Msk
12065#define RTC_TAFCR_PC14MODE_Pos (21U)
12066#define RTC_TAFCR_PC14MODE_Msk (0x1UL << RTC_TAFCR_PC14MODE_Pos)
12067#define RTC_TAFCR_PC14MODE RTC_TAFCR_PC14MODE_Msk
12068#define RTC_TAFCR_PC14VALUE_Pos (20U)
12069#define RTC_TAFCR_PC14VALUE_Msk (0x1UL << RTC_TAFCR_PC14VALUE_Pos)
12070#define RTC_TAFCR_PC14VALUE RTC_TAFCR_PC14VALUE_Msk
12071#define RTC_TAFCR_PC13MODE_Pos (19U)
12072#define RTC_TAFCR_PC13MODE_Msk (0x1UL << RTC_TAFCR_PC13MODE_Pos)
12073#define RTC_TAFCR_PC13MODE RTC_TAFCR_PC13MODE_Msk
12074#define RTC_TAFCR_PC13VALUE_Pos (18U)
12075#define RTC_TAFCR_PC13VALUE_Msk (0x1UL << RTC_TAFCR_PC13VALUE_Pos)
12076#define RTC_TAFCR_PC13VALUE RTC_TAFCR_PC13VALUE_Msk
12077#define RTC_TAFCR_TAMPPUDIS_Pos (15U)
12078#define RTC_TAFCR_TAMPPUDIS_Msk (0x1UL << RTC_TAFCR_TAMPPUDIS_Pos)
12079#define RTC_TAFCR_TAMPPUDIS RTC_TAFCR_TAMPPUDIS_Msk
12080#define RTC_TAFCR_TAMPPRCH_Pos (13U)
12081#define RTC_TAFCR_TAMPPRCH_Msk (0x3UL << RTC_TAFCR_TAMPPRCH_Pos)
12082#define RTC_TAFCR_TAMPPRCH RTC_TAFCR_TAMPPRCH_Msk
12083#define RTC_TAFCR_TAMPPRCH_0 (0x1UL << RTC_TAFCR_TAMPPRCH_Pos)
12084#define RTC_TAFCR_TAMPPRCH_1 (0x2UL << RTC_TAFCR_TAMPPRCH_Pos)
12085#define RTC_TAFCR_TAMPFLT_Pos (11U)
12086#define RTC_TAFCR_TAMPFLT_Msk (0x3UL << RTC_TAFCR_TAMPFLT_Pos)
12087#define RTC_TAFCR_TAMPFLT RTC_TAFCR_TAMPFLT_Msk
12088#define RTC_TAFCR_TAMPFLT_0 (0x1UL << RTC_TAFCR_TAMPFLT_Pos)
12089#define RTC_TAFCR_TAMPFLT_1 (0x2UL << RTC_TAFCR_TAMPFLT_Pos)
12090#define RTC_TAFCR_TAMPFREQ_Pos (8U)
12091#define RTC_TAFCR_TAMPFREQ_Msk (0x7UL << RTC_TAFCR_TAMPFREQ_Pos)
12092#define RTC_TAFCR_TAMPFREQ RTC_TAFCR_TAMPFREQ_Msk
12093#define RTC_TAFCR_TAMPFREQ_0 (0x1UL << RTC_TAFCR_TAMPFREQ_Pos)
12094#define RTC_TAFCR_TAMPFREQ_1 (0x2UL << RTC_TAFCR_TAMPFREQ_Pos)
12095#define RTC_TAFCR_TAMPFREQ_2 (0x4UL << RTC_TAFCR_TAMPFREQ_Pos)
12096#define RTC_TAFCR_TAMPTS_Pos (7U)
12097#define RTC_TAFCR_TAMPTS_Msk (0x1UL << RTC_TAFCR_TAMPTS_Pos)
12098#define RTC_TAFCR_TAMPTS RTC_TAFCR_TAMPTS_Msk
12099#define RTC_TAFCR_TAMP3TRG_Pos (6U)
12100#define RTC_TAFCR_TAMP3TRG_Msk (0x1UL << RTC_TAFCR_TAMP3TRG_Pos)
12101#define RTC_TAFCR_TAMP3TRG RTC_TAFCR_TAMP3TRG_Msk
12102#define RTC_TAFCR_TAMP3E_Pos (5U)
12103#define RTC_TAFCR_TAMP3E_Msk (0x1UL << RTC_TAFCR_TAMP3E_Pos)
12104#define RTC_TAFCR_TAMP3E RTC_TAFCR_TAMP3E_Msk
12105#define RTC_TAFCR_TAMP2TRG_Pos (4U)
12106#define RTC_TAFCR_TAMP2TRG_Msk (0x1UL << RTC_TAFCR_TAMP2TRG_Pos)
12107#define RTC_TAFCR_TAMP2TRG RTC_TAFCR_TAMP2TRG_Msk
12108#define RTC_TAFCR_TAMP2E_Pos (3U)
12109#define RTC_TAFCR_TAMP2E_Msk (0x1UL << RTC_TAFCR_TAMP2E_Pos)
12110#define RTC_TAFCR_TAMP2E RTC_TAFCR_TAMP2E_Msk
12111#define RTC_TAFCR_TAMPIE_Pos (2U)
12112#define RTC_TAFCR_TAMPIE_Msk (0x1UL << RTC_TAFCR_TAMPIE_Pos)
12113#define RTC_TAFCR_TAMPIE RTC_TAFCR_TAMPIE_Msk
12114#define RTC_TAFCR_TAMP1TRG_Pos (1U)
12115#define RTC_TAFCR_TAMP1TRG_Msk (0x1UL << RTC_TAFCR_TAMP1TRG_Pos)
12116#define RTC_TAFCR_TAMP1TRG RTC_TAFCR_TAMP1TRG_Msk
12117#define RTC_TAFCR_TAMP1E_Pos (0U)
12118#define RTC_TAFCR_TAMP1E_Msk (0x1UL << RTC_TAFCR_TAMP1E_Pos)
12119#define RTC_TAFCR_TAMP1E RTC_TAFCR_TAMP1E_Msk
12120
12121/* Reference defines */
12122#define RTC_TAFCR_ALARMOUTTYPE RTC_TAFCR_PC13VALUE
12123
12124/******************** Bits definition for RTC_ALRMASSR register *************/
12125#define RTC_ALRMASSR_MASKSS_Pos (24U)
12126#define RTC_ALRMASSR_MASKSS_Msk (0xFUL << RTC_ALRMASSR_MASKSS_Pos)
12127#define RTC_ALRMASSR_MASKSS RTC_ALRMASSR_MASKSS_Msk
12128#define RTC_ALRMASSR_MASKSS_0 (0x1UL << RTC_ALRMASSR_MASKSS_Pos)
12129#define RTC_ALRMASSR_MASKSS_1 (0x2UL << RTC_ALRMASSR_MASKSS_Pos)
12130#define RTC_ALRMASSR_MASKSS_2 (0x4UL << RTC_ALRMASSR_MASKSS_Pos)
12131#define RTC_ALRMASSR_MASKSS_3 (0x8UL << RTC_ALRMASSR_MASKSS_Pos)
12132#define RTC_ALRMASSR_SS_Pos (0U)
12133#define RTC_ALRMASSR_SS_Msk (0x7FFFUL << RTC_ALRMASSR_SS_Pos)
12134#define RTC_ALRMASSR_SS RTC_ALRMASSR_SS_Msk
12135
12136/******************** Bits definition for RTC_ALRMBSSR register *************/
12137#define RTC_ALRMBSSR_MASKSS_Pos (24U)
12138#define RTC_ALRMBSSR_MASKSS_Msk (0xFUL << RTC_ALRMBSSR_MASKSS_Pos)
12139#define RTC_ALRMBSSR_MASKSS RTC_ALRMBSSR_MASKSS_Msk
12140#define RTC_ALRMBSSR_MASKSS_0 (0x1UL << RTC_ALRMBSSR_MASKSS_Pos)
12141#define RTC_ALRMBSSR_MASKSS_1 (0x2UL << RTC_ALRMBSSR_MASKSS_Pos)
12142#define RTC_ALRMBSSR_MASKSS_2 (0x4UL << RTC_ALRMBSSR_MASKSS_Pos)
12143#define RTC_ALRMBSSR_MASKSS_3 (0x8UL << RTC_ALRMBSSR_MASKSS_Pos)
12144#define RTC_ALRMBSSR_SS_Pos (0U)
12145#define RTC_ALRMBSSR_SS_Msk (0x7FFFUL << RTC_ALRMBSSR_SS_Pos)
12146#define RTC_ALRMBSSR_SS RTC_ALRMBSSR_SS_Msk
12147
12148/******************** Bits definition for RTC_BKP0R register ****************/
12149#define RTC_BKP0R_Pos (0U)
12150#define RTC_BKP0R_Msk (0xFFFFFFFFUL << RTC_BKP0R_Pos)
12151#define RTC_BKP0R RTC_BKP0R_Msk
12152
12153/******************** Bits definition for RTC_BKP1R register ****************/
12154#define RTC_BKP1R_Pos (0U)
12155#define RTC_BKP1R_Msk (0xFFFFFFFFUL << RTC_BKP1R_Pos)
12156#define RTC_BKP1R RTC_BKP1R_Msk
12157
12158/******************** Bits definition for RTC_BKP2R register ****************/
12159#define RTC_BKP2R_Pos (0U)
12160#define RTC_BKP2R_Msk (0xFFFFFFFFUL << RTC_BKP2R_Pos)
12161#define RTC_BKP2R RTC_BKP2R_Msk
12162
12163/******************** Bits definition for RTC_BKP3R register ****************/
12164#define RTC_BKP3R_Pos (0U)
12165#define RTC_BKP3R_Msk (0xFFFFFFFFUL << RTC_BKP3R_Pos)
12166#define RTC_BKP3R RTC_BKP3R_Msk
12167
12168/******************** Bits definition for RTC_BKP4R register ****************/
12169#define RTC_BKP4R_Pos (0U)
12170#define RTC_BKP4R_Msk (0xFFFFFFFFUL << RTC_BKP4R_Pos)
12171#define RTC_BKP4R RTC_BKP4R_Msk
12172
12173/******************** Bits definition for RTC_BKP5R register ****************/
12174#define RTC_BKP5R_Pos (0U)
12175#define RTC_BKP5R_Msk (0xFFFFFFFFUL << RTC_BKP5R_Pos)
12176#define RTC_BKP5R RTC_BKP5R_Msk
12177
12178/******************** Bits definition for RTC_BKP6R register ****************/
12179#define RTC_BKP6R_Pos (0U)
12180#define RTC_BKP6R_Msk (0xFFFFFFFFUL << RTC_BKP6R_Pos)
12181#define RTC_BKP6R RTC_BKP6R_Msk
12182
12183/******************** Bits definition for RTC_BKP7R register ****************/
12184#define RTC_BKP7R_Pos (0U)
12185#define RTC_BKP7R_Msk (0xFFFFFFFFUL << RTC_BKP7R_Pos)
12186#define RTC_BKP7R RTC_BKP7R_Msk
12187
12188/******************** Bits definition for RTC_BKP8R register ****************/
12189#define RTC_BKP8R_Pos (0U)
12190#define RTC_BKP8R_Msk (0xFFFFFFFFUL << RTC_BKP8R_Pos)
12191#define RTC_BKP8R RTC_BKP8R_Msk
12192
12193/******************** Bits definition for RTC_BKP9R register ****************/
12194#define RTC_BKP9R_Pos (0U)
12195#define RTC_BKP9R_Msk (0xFFFFFFFFUL << RTC_BKP9R_Pos)
12196#define RTC_BKP9R RTC_BKP9R_Msk
12197
12198/******************** Bits definition for RTC_BKP10R register ***************/
12199#define RTC_BKP10R_Pos (0U)
12200#define RTC_BKP10R_Msk (0xFFFFFFFFUL << RTC_BKP10R_Pos)
12201#define RTC_BKP10R RTC_BKP10R_Msk
12202
12203/******************** Bits definition for RTC_BKP11R register ***************/
12204#define RTC_BKP11R_Pos (0U)
12205#define RTC_BKP11R_Msk (0xFFFFFFFFUL << RTC_BKP11R_Pos)
12206#define RTC_BKP11R RTC_BKP11R_Msk
12207
12208/******************** Bits definition for RTC_BKP12R register ***************/
12209#define RTC_BKP12R_Pos (0U)
12210#define RTC_BKP12R_Msk (0xFFFFFFFFUL << RTC_BKP12R_Pos)
12211#define RTC_BKP12R RTC_BKP12R_Msk
12212
12213/******************** Bits definition for RTC_BKP13R register ***************/
12214#define RTC_BKP13R_Pos (0U)
12215#define RTC_BKP13R_Msk (0xFFFFFFFFUL << RTC_BKP13R_Pos)
12216#define RTC_BKP13R RTC_BKP13R_Msk
12217
12218/******************** Bits definition for RTC_BKP14R register ***************/
12219#define RTC_BKP14R_Pos (0U)
12220#define RTC_BKP14R_Msk (0xFFFFFFFFUL << RTC_BKP14R_Pos)
12221#define RTC_BKP14R RTC_BKP14R_Msk
12222
12223/******************** Bits definition for RTC_BKP15R register ***************/
12224#define RTC_BKP15R_Pos (0U)
12225#define RTC_BKP15R_Msk (0xFFFFFFFFUL << RTC_BKP15R_Pos)
12226#define RTC_BKP15R RTC_BKP15R_Msk
12227
12228/******************** Number of backup registers ******************************/
12229#define RTC_BKP_NUMBER 16
12230
12231/******************************************************************************/
12232/* */
12233/* Serial Peripheral Interface (SPI) */
12234/* */
12235/******************************************************************************/
12236
12237/*
12238 * @brief Specific device feature definitions (not present on all devices in the STM32F3 series)
12239 */
12240#define SPI_I2S_SUPPORT
12241#define SPI_I2S_FULLDUPLEX_SUPPORT
12243/******************* Bit definition for SPI_CR1 register ********************/
12244#define SPI_CR1_CPHA_Pos (0U)
12245#define SPI_CR1_CPHA_Msk (0x1UL << SPI_CR1_CPHA_Pos)
12246#define SPI_CR1_CPHA SPI_CR1_CPHA_Msk
12247#define SPI_CR1_CPOL_Pos (1U)
12248#define SPI_CR1_CPOL_Msk (0x1UL << SPI_CR1_CPOL_Pos)
12249#define SPI_CR1_CPOL SPI_CR1_CPOL_Msk
12250#define SPI_CR1_MSTR_Pos (2U)
12251#define SPI_CR1_MSTR_Msk (0x1UL << SPI_CR1_MSTR_Pos)
12252#define SPI_CR1_MSTR SPI_CR1_MSTR_Msk
12253#define SPI_CR1_BR_Pos (3U)
12254#define SPI_CR1_BR_Msk (0x7UL << SPI_CR1_BR_Pos)
12255#define SPI_CR1_BR SPI_CR1_BR_Msk
12256#define SPI_CR1_BR_0 (0x1UL << SPI_CR1_BR_Pos)
12257#define SPI_CR1_BR_1 (0x2UL << SPI_CR1_BR_Pos)
12258#define SPI_CR1_BR_2 (0x4UL << SPI_CR1_BR_Pos)
12259#define SPI_CR1_SPE_Pos (6U)
12260#define SPI_CR1_SPE_Msk (0x1UL << SPI_CR1_SPE_Pos)
12261#define SPI_CR1_SPE SPI_CR1_SPE_Msk
12262#define SPI_CR1_LSBFIRST_Pos (7U)
12263#define SPI_CR1_LSBFIRST_Msk (0x1UL << SPI_CR1_LSBFIRST_Pos)
12264#define SPI_CR1_LSBFIRST SPI_CR1_LSBFIRST_Msk
12265#define SPI_CR1_SSI_Pos (8U)
12266#define SPI_CR1_SSI_Msk (0x1UL << SPI_CR1_SSI_Pos)
12267#define SPI_CR1_SSI SPI_CR1_SSI_Msk
12268#define SPI_CR1_SSM_Pos (9U)
12269#define SPI_CR1_SSM_Msk (0x1UL << SPI_CR1_SSM_Pos)
12270#define SPI_CR1_SSM SPI_CR1_SSM_Msk
12271#define SPI_CR1_RXONLY_Pos (10U)
12272#define SPI_CR1_RXONLY_Msk (0x1UL << SPI_CR1_RXONLY_Pos)
12273#define SPI_CR1_RXONLY SPI_CR1_RXONLY_Msk
12274#define SPI_CR1_CRCL_Pos (11U)
12275#define SPI_CR1_CRCL_Msk (0x1UL << SPI_CR1_CRCL_Pos)
12276#define SPI_CR1_CRCL SPI_CR1_CRCL_Msk
12277#define SPI_CR1_CRCNEXT_Pos (12U)
12278#define SPI_CR1_CRCNEXT_Msk (0x1UL << SPI_CR1_CRCNEXT_Pos)
12279#define SPI_CR1_CRCNEXT SPI_CR1_CRCNEXT_Msk
12280#define SPI_CR1_CRCEN_Pos (13U)
12281#define SPI_CR1_CRCEN_Msk (0x1UL << SPI_CR1_CRCEN_Pos)
12282#define SPI_CR1_CRCEN SPI_CR1_CRCEN_Msk
12283#define SPI_CR1_BIDIOE_Pos (14U)
12284#define SPI_CR1_BIDIOE_Msk (0x1UL << SPI_CR1_BIDIOE_Pos)
12285#define SPI_CR1_BIDIOE SPI_CR1_BIDIOE_Msk
12286#define SPI_CR1_BIDIMODE_Pos (15U)
12287#define SPI_CR1_BIDIMODE_Msk (0x1UL << SPI_CR1_BIDIMODE_Pos)
12288#define SPI_CR1_BIDIMODE SPI_CR1_BIDIMODE_Msk
12290/******************* Bit definition for SPI_CR2 register ********************/
12291#define SPI_CR2_RXDMAEN_Pos (0U)
12292#define SPI_CR2_RXDMAEN_Msk (0x1UL << SPI_CR2_RXDMAEN_Pos)
12293#define SPI_CR2_RXDMAEN SPI_CR2_RXDMAEN_Msk
12294#define SPI_CR2_TXDMAEN_Pos (1U)
12295#define SPI_CR2_TXDMAEN_Msk (0x1UL << SPI_CR2_TXDMAEN_Pos)
12296#define SPI_CR2_TXDMAEN SPI_CR2_TXDMAEN_Msk
12297#define SPI_CR2_SSOE_Pos (2U)
12298#define SPI_CR2_SSOE_Msk (0x1UL << SPI_CR2_SSOE_Pos)
12299#define SPI_CR2_SSOE SPI_CR2_SSOE_Msk
12300#define SPI_CR2_NSSP_Pos (3U)
12301#define SPI_CR2_NSSP_Msk (0x1UL << SPI_CR2_NSSP_Pos)
12302#define SPI_CR2_NSSP SPI_CR2_NSSP_Msk
12303#define SPI_CR2_FRF_Pos (4U)
12304#define SPI_CR2_FRF_Msk (0x1UL << SPI_CR2_FRF_Pos)
12305#define SPI_CR2_FRF SPI_CR2_FRF_Msk
12306#define SPI_CR2_ERRIE_Pos (5U)
12307#define SPI_CR2_ERRIE_Msk (0x1UL << SPI_CR2_ERRIE_Pos)
12308#define SPI_CR2_ERRIE SPI_CR2_ERRIE_Msk
12309#define SPI_CR2_RXNEIE_Pos (6U)
12310#define SPI_CR2_RXNEIE_Msk (0x1UL << SPI_CR2_RXNEIE_Pos)
12311#define SPI_CR2_RXNEIE SPI_CR2_RXNEIE_Msk
12312#define SPI_CR2_TXEIE_Pos (7U)
12313#define SPI_CR2_TXEIE_Msk (0x1UL << SPI_CR2_TXEIE_Pos)
12314#define SPI_CR2_TXEIE SPI_CR2_TXEIE_Msk
12315#define SPI_CR2_DS_Pos (8U)
12316#define SPI_CR2_DS_Msk (0xFUL << SPI_CR2_DS_Pos)
12317#define SPI_CR2_DS SPI_CR2_DS_Msk
12318#define SPI_CR2_DS_0 (0x1UL << SPI_CR2_DS_Pos)
12319#define SPI_CR2_DS_1 (0x2UL << SPI_CR2_DS_Pos)
12320#define SPI_CR2_DS_2 (0x4UL << SPI_CR2_DS_Pos)
12321#define SPI_CR2_DS_3 (0x8UL << SPI_CR2_DS_Pos)
12322#define SPI_CR2_FRXTH_Pos (12U)
12323#define SPI_CR2_FRXTH_Msk (0x1UL << SPI_CR2_FRXTH_Pos)
12324#define SPI_CR2_FRXTH SPI_CR2_FRXTH_Msk
12325#define SPI_CR2_LDMARX_Pos (13U)
12326#define SPI_CR2_LDMARX_Msk (0x1UL << SPI_CR2_LDMARX_Pos)
12327#define SPI_CR2_LDMARX SPI_CR2_LDMARX_Msk
12328#define SPI_CR2_LDMATX_Pos (14U)
12329#define SPI_CR2_LDMATX_Msk (0x1UL << SPI_CR2_LDMATX_Pos)
12330#define SPI_CR2_LDMATX SPI_CR2_LDMATX_Msk
12332/******************** Bit definition for SPI_SR register ********************/
12333#define SPI_SR_RXNE_Pos (0U)
12334#define SPI_SR_RXNE_Msk (0x1UL << SPI_SR_RXNE_Pos)
12335#define SPI_SR_RXNE SPI_SR_RXNE_Msk
12336#define SPI_SR_TXE_Pos (1U)
12337#define SPI_SR_TXE_Msk (0x1UL << SPI_SR_TXE_Pos)
12338#define SPI_SR_TXE SPI_SR_TXE_Msk
12339#define SPI_SR_CHSIDE_Pos (2U)
12340#define SPI_SR_CHSIDE_Msk (0x1UL << SPI_SR_CHSIDE_Pos)
12341#define SPI_SR_CHSIDE SPI_SR_CHSIDE_Msk
12342#define SPI_SR_UDR_Pos (3U)
12343#define SPI_SR_UDR_Msk (0x1UL << SPI_SR_UDR_Pos)
12344#define SPI_SR_UDR SPI_SR_UDR_Msk
12345#define SPI_SR_CRCERR_Pos (4U)
12346#define SPI_SR_CRCERR_Msk (0x1UL << SPI_SR_CRCERR_Pos)
12347#define SPI_SR_CRCERR SPI_SR_CRCERR_Msk
12348#define SPI_SR_MODF_Pos (5U)
12349#define SPI_SR_MODF_Msk (0x1UL << SPI_SR_MODF_Pos)
12350#define SPI_SR_MODF SPI_SR_MODF_Msk
12351#define SPI_SR_OVR_Pos (6U)
12352#define SPI_SR_OVR_Msk (0x1UL << SPI_SR_OVR_Pos)
12353#define SPI_SR_OVR SPI_SR_OVR_Msk
12354#define SPI_SR_BSY_Pos (7U)
12355#define SPI_SR_BSY_Msk (0x1UL << SPI_SR_BSY_Pos)
12356#define SPI_SR_BSY SPI_SR_BSY_Msk
12357#define SPI_SR_FRE_Pos (8U)
12358#define SPI_SR_FRE_Msk (0x1UL << SPI_SR_FRE_Pos)
12359#define SPI_SR_FRE SPI_SR_FRE_Msk
12360#define SPI_SR_FRLVL_Pos (9U)
12361#define SPI_SR_FRLVL_Msk (0x3UL << SPI_SR_FRLVL_Pos)
12362#define SPI_SR_FRLVL SPI_SR_FRLVL_Msk
12363#define SPI_SR_FRLVL_0 (0x1UL << SPI_SR_FRLVL_Pos)
12364#define SPI_SR_FRLVL_1 (0x2UL << SPI_SR_FRLVL_Pos)
12365#define SPI_SR_FTLVL_Pos (11U)
12366#define SPI_SR_FTLVL_Msk (0x3UL << SPI_SR_FTLVL_Pos)
12367#define SPI_SR_FTLVL SPI_SR_FTLVL_Msk
12368#define SPI_SR_FTLVL_0 (0x1UL << SPI_SR_FTLVL_Pos)
12369#define SPI_SR_FTLVL_1 (0x2UL << SPI_SR_FTLVL_Pos)
12371/******************** Bit definition for SPI_DR register ********************/
12372#define SPI_DR_DR_Pos (0U)
12373#define SPI_DR_DR_Msk (0xFFFFUL << SPI_DR_DR_Pos)
12374#define SPI_DR_DR SPI_DR_DR_Msk
12376/******************* Bit definition for SPI_CRCPR register ******************/
12377#define SPI_CRCPR_CRCPOLY_Pos (0U)
12378#define SPI_CRCPR_CRCPOLY_Msk (0xFFFFUL << SPI_CRCPR_CRCPOLY_Pos)
12379#define SPI_CRCPR_CRCPOLY SPI_CRCPR_CRCPOLY_Msk
12381/****************** Bit definition for SPI_RXCRCR register ******************/
12382#define SPI_RXCRCR_RXCRC_Pos (0U)
12383#define SPI_RXCRCR_RXCRC_Msk (0xFFFFUL << SPI_RXCRCR_RXCRC_Pos)
12384#define SPI_RXCRCR_RXCRC SPI_RXCRCR_RXCRC_Msk
12386/****************** Bit definition for SPI_TXCRCR register ******************/
12387#define SPI_TXCRCR_TXCRC_Pos (0U)
12388#define SPI_TXCRCR_TXCRC_Msk (0xFFFFUL << SPI_TXCRCR_TXCRC_Pos)
12389#define SPI_TXCRCR_TXCRC SPI_TXCRCR_TXCRC_Msk
12391/****************** Bit definition for SPI_I2SCFGR register *****************/
12392#define SPI_I2SCFGR_CHLEN_Pos (0U)
12393#define SPI_I2SCFGR_CHLEN_Msk (0x1UL << SPI_I2SCFGR_CHLEN_Pos)
12394#define SPI_I2SCFGR_CHLEN SPI_I2SCFGR_CHLEN_Msk
12395#define SPI_I2SCFGR_DATLEN_Pos (1U)
12396#define SPI_I2SCFGR_DATLEN_Msk (0x3UL << SPI_I2SCFGR_DATLEN_Pos)
12397#define SPI_I2SCFGR_DATLEN SPI_I2SCFGR_DATLEN_Msk
12398#define SPI_I2SCFGR_DATLEN_0 (0x1UL << SPI_I2SCFGR_DATLEN_Pos)
12399#define SPI_I2SCFGR_DATLEN_1 (0x2UL << SPI_I2SCFGR_DATLEN_Pos)
12400#define SPI_I2SCFGR_CKPOL_Pos (3U)
12401#define SPI_I2SCFGR_CKPOL_Msk (0x1UL << SPI_I2SCFGR_CKPOL_Pos)
12402#define SPI_I2SCFGR_CKPOL SPI_I2SCFGR_CKPOL_Msk
12403#define SPI_I2SCFGR_I2SSTD_Pos (4U)
12404#define SPI_I2SCFGR_I2SSTD_Msk (0x3UL << SPI_I2SCFGR_I2SSTD_Pos)
12405#define SPI_I2SCFGR_I2SSTD SPI_I2SCFGR_I2SSTD_Msk
12406#define SPI_I2SCFGR_I2SSTD_0 (0x1UL << SPI_I2SCFGR_I2SSTD_Pos)
12407#define SPI_I2SCFGR_I2SSTD_1 (0x2UL << SPI_I2SCFGR_I2SSTD_Pos)
12408#define SPI_I2SCFGR_PCMSYNC_Pos (7U)
12409#define SPI_I2SCFGR_PCMSYNC_Msk (0x1UL << SPI_I2SCFGR_PCMSYNC_Pos)
12410#define SPI_I2SCFGR_PCMSYNC SPI_I2SCFGR_PCMSYNC_Msk
12411#define SPI_I2SCFGR_I2SCFG_Pos (8U)
12412#define SPI_I2SCFGR_I2SCFG_Msk (0x3UL << SPI_I2SCFGR_I2SCFG_Pos)
12413#define SPI_I2SCFGR_I2SCFG SPI_I2SCFGR_I2SCFG_Msk
12414#define SPI_I2SCFGR_I2SCFG_0 (0x1UL << SPI_I2SCFGR_I2SCFG_Pos)
12415#define SPI_I2SCFGR_I2SCFG_1 (0x2UL << SPI_I2SCFGR_I2SCFG_Pos)
12416#define SPI_I2SCFGR_I2SE_Pos (10U)
12417#define SPI_I2SCFGR_I2SE_Msk (0x1UL << SPI_I2SCFGR_I2SE_Pos)
12418#define SPI_I2SCFGR_I2SE SPI_I2SCFGR_I2SE_Msk
12419#define SPI_I2SCFGR_I2SMOD_Pos (11U)
12420#define SPI_I2SCFGR_I2SMOD_Msk (0x1UL << SPI_I2SCFGR_I2SMOD_Pos)
12421#define SPI_I2SCFGR_I2SMOD SPI_I2SCFGR_I2SMOD_Msk
12423/****************** Bit definition for SPI_I2SPR register *******************/
12424#define SPI_I2SPR_I2SDIV_Pos (0U)
12425#define SPI_I2SPR_I2SDIV_Msk (0xFFUL << SPI_I2SPR_I2SDIV_Pos)
12426#define SPI_I2SPR_I2SDIV SPI_I2SPR_I2SDIV_Msk
12427#define SPI_I2SPR_ODD_Pos (8U)
12428#define SPI_I2SPR_ODD_Msk (0x1UL << SPI_I2SPR_ODD_Pos)
12429#define SPI_I2SPR_ODD SPI_I2SPR_ODD_Msk
12430#define SPI_I2SPR_MCKOE_Pos (9U)
12431#define SPI_I2SPR_MCKOE_Msk (0x1UL << SPI_I2SPR_MCKOE_Pos)
12432#define SPI_I2SPR_MCKOE SPI_I2SPR_MCKOE_Msk
12434/******************************************************************************/
12435/* */
12436/* System Configuration(SYSCFG) */
12437/* */
12438/******************************************************************************/
12439/***************** Bit definition for SYSCFG_CFGR1 register ****************/
12440#define SYSCFG_CFGR1_MEM_MODE_Pos (0U)
12441#define SYSCFG_CFGR1_MEM_MODE_Msk (0x7UL << SYSCFG_CFGR1_MEM_MODE_Pos)
12442#define SYSCFG_CFGR1_MEM_MODE SYSCFG_CFGR1_MEM_MODE_Msk
12443#define SYSCFG_CFGR1_MEM_MODE_0 (0x00000001U)
12444#define SYSCFG_CFGR1_MEM_MODE_1 (0x00000002U)
12445#define SYSCFG_CFGR1_MEM_MODE_2 (0x00000004U)
12446#define SYSCFG_CFGR1_USB_IT_RMP_Pos (5U)
12447#define SYSCFG_CFGR1_USB_IT_RMP_Msk (0x1UL << SYSCFG_CFGR1_USB_IT_RMP_Pos)
12448#define SYSCFG_CFGR1_USB_IT_RMP SYSCFG_CFGR1_USB_IT_RMP_Msk
12449#define SYSCFG_CFGR1_TIM1_ITR3_RMP_Pos (6U)
12450#define SYSCFG_CFGR1_TIM1_ITR3_RMP_Msk (0x1UL << SYSCFG_CFGR1_TIM1_ITR3_RMP_Pos)
12451#define SYSCFG_CFGR1_TIM1_ITR3_RMP SYSCFG_CFGR1_TIM1_ITR3_RMP_Msk
12452#define SYSCFG_CFGR1_DAC1_TRIG1_RMP_Pos (7U)
12453#define SYSCFG_CFGR1_DAC1_TRIG1_RMP_Msk (0x1UL << SYSCFG_CFGR1_DAC1_TRIG1_RMP_Pos)
12454#define SYSCFG_CFGR1_DAC1_TRIG1_RMP SYSCFG_CFGR1_DAC1_TRIG1_RMP_Msk
12455#define SYSCFG_CFGR1_DMA_RMP_Pos (8U)
12456#define SYSCFG_CFGR1_DMA_RMP_Msk (0x79UL << SYSCFG_CFGR1_DMA_RMP_Pos)
12457#define SYSCFG_CFGR1_DMA_RMP SYSCFG_CFGR1_DMA_RMP_Msk
12458#define SYSCFG_CFGR1_ADC24_DMA_RMP_Pos (8U)
12459#define SYSCFG_CFGR1_ADC24_DMA_RMP_Msk (0x1UL << SYSCFG_CFGR1_ADC24_DMA_RMP_Pos)
12460#define SYSCFG_CFGR1_ADC24_DMA_RMP SYSCFG_CFGR1_ADC24_DMA_RMP_Msk
12461#define SYSCFG_CFGR1_TIM16_DMA_RMP_Pos (11U)
12462#define SYSCFG_CFGR1_TIM16_DMA_RMP_Msk (0x1UL << SYSCFG_CFGR1_TIM16_DMA_RMP_Pos)
12463#define SYSCFG_CFGR1_TIM16_DMA_RMP SYSCFG_CFGR1_TIM16_DMA_RMP_Msk
12464#define SYSCFG_CFGR1_TIM17_DMA_RMP_Pos (12U)
12465#define SYSCFG_CFGR1_TIM17_DMA_RMP_Msk (0x1UL << SYSCFG_CFGR1_TIM17_DMA_RMP_Pos)
12466#define SYSCFG_CFGR1_TIM17_DMA_RMP SYSCFG_CFGR1_TIM17_DMA_RMP_Msk
12467#define SYSCFG_CFGR1_TIM6DAC1Ch1_DMA_RMP_Pos (13U)
12468#define SYSCFG_CFGR1_TIM6DAC1Ch1_DMA_RMP_Msk (0x1UL << SYSCFG_CFGR1_TIM6DAC1Ch1_DMA_RMP_Pos)
12469#define SYSCFG_CFGR1_TIM6DAC1Ch1_DMA_RMP SYSCFG_CFGR1_TIM6DAC1Ch1_DMA_RMP_Msk
12470#define SYSCFG_CFGR1_TIM7DAC1Ch2_DMA_RMP_Pos (14U)
12471#define SYSCFG_CFGR1_TIM7DAC1Ch2_DMA_RMP_Msk (0x1UL << SYSCFG_CFGR1_TIM7DAC1Ch2_DMA_RMP_Pos)
12472#define SYSCFG_CFGR1_TIM7DAC1Ch2_DMA_RMP SYSCFG_CFGR1_TIM7DAC1Ch2_DMA_RMP_Msk
12473#define SYSCFG_CFGR1_I2C_PB6_FMP_Pos (16U)
12474#define SYSCFG_CFGR1_I2C_PB6_FMP_Msk (0x1UL << SYSCFG_CFGR1_I2C_PB6_FMP_Pos)
12475#define SYSCFG_CFGR1_I2C_PB6_FMP SYSCFG_CFGR1_I2C_PB6_FMP_Msk
12476#define SYSCFG_CFGR1_I2C_PB7_FMP_Pos (17U)
12477#define SYSCFG_CFGR1_I2C_PB7_FMP_Msk (0x1UL << SYSCFG_CFGR1_I2C_PB7_FMP_Pos)
12478#define SYSCFG_CFGR1_I2C_PB7_FMP SYSCFG_CFGR1_I2C_PB7_FMP_Msk
12479#define SYSCFG_CFGR1_I2C_PB8_FMP_Pos (18U)
12480#define SYSCFG_CFGR1_I2C_PB8_FMP_Msk (0x1UL << SYSCFG_CFGR1_I2C_PB8_FMP_Pos)
12481#define SYSCFG_CFGR1_I2C_PB8_FMP SYSCFG_CFGR1_I2C_PB8_FMP_Msk
12482#define SYSCFG_CFGR1_I2C_PB9_FMP_Pos (19U)
12483#define SYSCFG_CFGR1_I2C_PB9_FMP_Msk (0x1UL << SYSCFG_CFGR1_I2C_PB9_FMP_Pos)
12484#define SYSCFG_CFGR1_I2C_PB9_FMP SYSCFG_CFGR1_I2C_PB9_FMP_Msk
12485#define SYSCFG_CFGR1_I2C1_FMP_Pos (20U)
12486#define SYSCFG_CFGR1_I2C1_FMP_Msk (0x1UL << SYSCFG_CFGR1_I2C1_FMP_Pos)
12487#define SYSCFG_CFGR1_I2C1_FMP SYSCFG_CFGR1_I2C1_FMP_Msk
12488#define SYSCFG_CFGR1_I2C2_FMP_Pos (21U)
12489#define SYSCFG_CFGR1_I2C2_FMP_Msk (0x1UL << SYSCFG_CFGR1_I2C2_FMP_Pos)
12490#define SYSCFG_CFGR1_I2C2_FMP SYSCFG_CFGR1_I2C2_FMP_Msk
12491#define SYSCFG_CFGR1_ENCODER_MODE_Pos (22U)
12492#define SYSCFG_CFGR1_ENCODER_MODE_Msk (0x3UL << SYSCFG_CFGR1_ENCODER_MODE_Pos)
12493#define SYSCFG_CFGR1_ENCODER_MODE SYSCFG_CFGR1_ENCODER_MODE_Msk
12494#define SYSCFG_CFGR1_ENCODER_MODE_0 (0x1UL << SYSCFG_CFGR1_ENCODER_MODE_Pos)
12495#define SYSCFG_CFGR1_ENCODER_MODE_1 (0x2UL << SYSCFG_CFGR1_ENCODER_MODE_Pos)
12496#define SYSCFG_CFGR1_ENCODER_MODE_TIM2_Pos (22U)
12497#define SYSCFG_CFGR1_ENCODER_MODE_TIM2_Msk (0x1UL << SYSCFG_CFGR1_ENCODER_MODE_TIM2_Pos)
12498#define SYSCFG_CFGR1_ENCODER_MODE_TIM2 SYSCFG_CFGR1_ENCODER_MODE_TIM2_Msk
12499#define SYSCFG_CFGR1_ENCODER_MODE_TIM3_Pos (23U)
12500#define SYSCFG_CFGR1_ENCODER_MODE_TIM3_Msk (0x1UL << SYSCFG_CFGR1_ENCODER_MODE_TIM3_Pos)
12501#define SYSCFG_CFGR1_ENCODER_MODE_TIM3 SYSCFG_CFGR1_ENCODER_MODE_TIM3_Msk
12502#define SYSCFG_CFGR1_I2C3_FMP_Pos (24U)
12503#define SYSCFG_CFGR1_I2C3_FMP_Msk (0x1UL << SYSCFG_CFGR1_I2C3_FMP_Pos)
12504#define SYSCFG_CFGR1_I2C3_FMP SYSCFG_CFGR1_I2C3_FMP_Msk
12505#define SYSCFG_CFGR1_FPU_IE_Pos (26U)
12506#define SYSCFG_CFGR1_FPU_IE_Msk (0x3FUL << SYSCFG_CFGR1_FPU_IE_Pos)
12507#define SYSCFG_CFGR1_FPU_IE SYSCFG_CFGR1_FPU_IE_Msk
12508#define SYSCFG_CFGR1_FPU_IE_0 (0x01UL << SYSCFG_CFGR1_FPU_IE_Pos)
12509#define SYSCFG_CFGR1_FPU_IE_1 (0x02UL << SYSCFG_CFGR1_FPU_IE_Pos)
12510#define SYSCFG_CFGR1_FPU_IE_2 (0x04UL << SYSCFG_CFGR1_FPU_IE_Pos)
12511#define SYSCFG_CFGR1_FPU_IE_3 (0x08UL << SYSCFG_CFGR1_FPU_IE_Pos)
12512#define SYSCFG_CFGR1_FPU_IE_4 (0x10UL << SYSCFG_CFGR1_FPU_IE_Pos)
12513#define SYSCFG_CFGR1_FPU_IE_5 (0x20UL << SYSCFG_CFGR1_FPU_IE_Pos)
12515/***************** Bit definition for SYSCFG_RCR register *******************/
12516#define SYSCFG_RCR_PAGE0_Pos (0U)
12517#define SYSCFG_RCR_PAGE0_Msk (0x1UL << SYSCFG_RCR_PAGE0_Pos)
12518#define SYSCFG_RCR_PAGE0 SYSCFG_RCR_PAGE0_Msk
12519#define SYSCFG_RCR_PAGE1_Pos (1U)
12520#define SYSCFG_RCR_PAGE1_Msk (0x1UL << SYSCFG_RCR_PAGE1_Pos)
12521#define SYSCFG_RCR_PAGE1 SYSCFG_RCR_PAGE1_Msk
12522#define SYSCFG_RCR_PAGE2_Pos (2U)
12523#define SYSCFG_RCR_PAGE2_Msk (0x1UL << SYSCFG_RCR_PAGE2_Pos)
12524#define SYSCFG_RCR_PAGE2 SYSCFG_RCR_PAGE2_Msk
12525#define SYSCFG_RCR_PAGE3_Pos (3U)
12526#define SYSCFG_RCR_PAGE3_Msk (0x1UL << SYSCFG_RCR_PAGE3_Pos)
12527#define SYSCFG_RCR_PAGE3 SYSCFG_RCR_PAGE3_Msk
12528#define SYSCFG_RCR_PAGE4_Pos (4U)
12529#define SYSCFG_RCR_PAGE4_Msk (0x1UL << SYSCFG_RCR_PAGE4_Pos)
12530#define SYSCFG_RCR_PAGE4 SYSCFG_RCR_PAGE4_Msk
12531#define SYSCFG_RCR_PAGE5_Pos (5U)
12532#define SYSCFG_RCR_PAGE5_Msk (0x1UL << SYSCFG_RCR_PAGE5_Pos)
12533#define SYSCFG_RCR_PAGE5 SYSCFG_RCR_PAGE5_Msk
12534#define SYSCFG_RCR_PAGE6_Pos (6U)
12535#define SYSCFG_RCR_PAGE6_Msk (0x1UL << SYSCFG_RCR_PAGE6_Pos)
12536#define SYSCFG_RCR_PAGE6 SYSCFG_RCR_PAGE6_Msk
12537#define SYSCFG_RCR_PAGE7_Pos (7U)
12538#define SYSCFG_RCR_PAGE7_Msk (0x1UL << SYSCFG_RCR_PAGE7_Pos)
12539#define SYSCFG_RCR_PAGE7 SYSCFG_RCR_PAGE7_Msk
12540#define SYSCFG_RCR_PAGE8_Pos (8U)
12541#define SYSCFG_RCR_PAGE8_Msk (0x1UL << SYSCFG_RCR_PAGE8_Pos)
12542#define SYSCFG_RCR_PAGE8 SYSCFG_RCR_PAGE8_Msk
12543#define SYSCFG_RCR_PAGE9_Pos (9U)
12544#define SYSCFG_RCR_PAGE9_Msk (0x1UL << SYSCFG_RCR_PAGE9_Pos)
12545#define SYSCFG_RCR_PAGE9 SYSCFG_RCR_PAGE9_Msk
12546#define SYSCFG_RCR_PAGE10_Pos (10U)
12547#define SYSCFG_RCR_PAGE10_Msk (0x1UL << SYSCFG_RCR_PAGE10_Pos)
12548#define SYSCFG_RCR_PAGE10 SYSCFG_RCR_PAGE10_Msk
12549#define SYSCFG_RCR_PAGE11_Pos (11U)
12550#define SYSCFG_RCR_PAGE11_Msk (0x1UL << SYSCFG_RCR_PAGE11_Pos)
12551#define SYSCFG_RCR_PAGE11 SYSCFG_RCR_PAGE11_Msk
12552#define SYSCFG_RCR_PAGE12_Pos (12U)
12553#define SYSCFG_RCR_PAGE12_Msk (0x1UL << SYSCFG_RCR_PAGE12_Pos)
12554#define SYSCFG_RCR_PAGE12 SYSCFG_RCR_PAGE12_Msk
12555#define SYSCFG_RCR_PAGE13_Pos (13U)
12556#define SYSCFG_RCR_PAGE13_Msk (0x1UL << SYSCFG_RCR_PAGE13_Pos)
12557#define SYSCFG_RCR_PAGE13 SYSCFG_RCR_PAGE13_Msk
12558#define SYSCFG_RCR_PAGE14_Pos (14U)
12559#define SYSCFG_RCR_PAGE14_Msk (0x1UL << SYSCFG_RCR_PAGE14_Pos)
12560#define SYSCFG_RCR_PAGE14 SYSCFG_RCR_PAGE14_Msk
12561#define SYSCFG_RCR_PAGE15_Pos (15U)
12562#define SYSCFG_RCR_PAGE15_Msk (0x1UL << SYSCFG_RCR_PAGE15_Pos)
12563#define SYSCFG_RCR_PAGE15 SYSCFG_RCR_PAGE15_Msk
12565/***************** Bit definition for SYSCFG_EXTICR1 register ***************/
12566#define SYSCFG_EXTICR1_EXTI0_Pos (0U)
12567#define SYSCFG_EXTICR1_EXTI0_Msk (0xFUL << SYSCFG_EXTICR1_EXTI0_Pos)
12568#define SYSCFG_EXTICR1_EXTI0 SYSCFG_EXTICR1_EXTI0_Msk
12569#define SYSCFG_EXTICR1_EXTI1_Pos (4U)
12570#define SYSCFG_EXTICR1_EXTI1_Msk (0xFUL << SYSCFG_EXTICR1_EXTI1_Pos)
12571#define SYSCFG_EXTICR1_EXTI1 SYSCFG_EXTICR1_EXTI1_Msk
12572#define SYSCFG_EXTICR1_EXTI2_Pos (8U)
12573#define SYSCFG_EXTICR1_EXTI2_Msk (0xFUL << SYSCFG_EXTICR1_EXTI2_Pos)
12574#define SYSCFG_EXTICR1_EXTI2 SYSCFG_EXTICR1_EXTI2_Msk
12575#define SYSCFG_EXTICR1_EXTI3_Pos (12U)
12576#define SYSCFG_EXTICR1_EXTI3_Msk (0xFUL << SYSCFG_EXTICR1_EXTI3_Pos)
12577#define SYSCFG_EXTICR1_EXTI3 SYSCFG_EXTICR1_EXTI3_Msk
12582#define SYSCFG_EXTICR1_EXTI0_PA (0x00000000U)
12583#define SYSCFG_EXTICR1_EXTI0_PB (0x00000001U)
12584#define SYSCFG_EXTICR1_EXTI0_PC (0x00000002U)
12585#define SYSCFG_EXTICR1_EXTI0_PD (0x00000003U)
12586#define SYSCFG_EXTICR1_EXTI0_PE (0x00000004U)
12587#define SYSCFG_EXTICR1_EXTI0_PF (0x00000005U)
12588#define SYSCFG_EXTICR1_EXTI0_PG (0x00000006U)
12589#define SYSCFG_EXTICR1_EXTI0_PH (0x00000007U)
12594#define SYSCFG_EXTICR1_EXTI1_PA (0x00000000U)
12595#define SYSCFG_EXTICR1_EXTI1_PB (0x00000010U)
12596#define SYSCFG_EXTICR1_EXTI1_PC (0x00000020U)
12597#define SYSCFG_EXTICR1_EXTI1_PD (0x00000030U)
12598#define SYSCFG_EXTICR1_EXTI1_PE (0x00000040U)
12599#define SYSCFG_EXTICR1_EXTI1_PF (0x00000050U)
12600#define SYSCFG_EXTICR1_EXTI1_PG (0x00000060U)
12601#define SYSCFG_EXTICR1_EXTI1_PH (0x00000070U)
12606#define SYSCFG_EXTICR1_EXTI2_PA (0x00000000U)
12607#define SYSCFG_EXTICR1_EXTI2_PB (0x00000100U)
12608#define SYSCFG_EXTICR1_EXTI2_PC (0x00000200U)
12609#define SYSCFG_EXTICR1_EXTI2_PD (0x00000300U)
12610#define SYSCFG_EXTICR1_EXTI2_PE (0x00000400U)
12611#define SYSCFG_EXTICR1_EXTI2_PF (0x00000500U)
12612#define SYSCFG_EXTICR1_EXTI2_PG (0x00000600U)
12617#define SYSCFG_EXTICR1_EXTI3_PA (0x00000000U)
12618#define SYSCFG_EXTICR1_EXTI3_PB (0x00001000U)
12619#define SYSCFG_EXTICR1_EXTI3_PC (0x00002000U)
12620#define SYSCFG_EXTICR1_EXTI3_PD (0x00003000U)
12621#define SYSCFG_EXTICR1_EXTI3_PE (0x00004000U)
12622#define SYSCFG_EXTICR1_EXTI3_PF (0x00005000U)
12623#define SYSCFG_EXTICR1_EXTI3_PG (0x00006000U)
12625/***************** Bit definition for SYSCFG_EXTICR2 register ***************/
12626#define SYSCFG_EXTICR2_EXTI4_Pos (0U)
12627#define SYSCFG_EXTICR2_EXTI4_Msk (0xFUL << SYSCFG_EXTICR2_EXTI4_Pos)
12628#define SYSCFG_EXTICR2_EXTI4 SYSCFG_EXTICR2_EXTI4_Msk
12629#define SYSCFG_EXTICR2_EXTI5_Pos (4U)
12630#define SYSCFG_EXTICR2_EXTI5_Msk (0xFUL << SYSCFG_EXTICR2_EXTI5_Pos)
12631#define SYSCFG_EXTICR2_EXTI5 SYSCFG_EXTICR2_EXTI5_Msk
12632#define SYSCFG_EXTICR2_EXTI6_Pos (8U)
12633#define SYSCFG_EXTICR2_EXTI6_Msk (0xFUL << SYSCFG_EXTICR2_EXTI6_Pos)
12634#define SYSCFG_EXTICR2_EXTI6 SYSCFG_EXTICR2_EXTI6_Msk
12635#define SYSCFG_EXTICR2_EXTI7_Pos (12U)
12636#define SYSCFG_EXTICR2_EXTI7_Msk (0xFUL << SYSCFG_EXTICR2_EXTI7_Pos)
12637#define SYSCFG_EXTICR2_EXTI7 SYSCFG_EXTICR2_EXTI7_Msk
12642#define SYSCFG_EXTICR2_EXTI4_PA (0x00000000U)
12643#define SYSCFG_EXTICR2_EXTI4_PB (0x00000001U)
12644#define SYSCFG_EXTICR2_EXTI4_PC (0x00000002U)
12645#define SYSCFG_EXTICR2_EXTI4_PD (0x00000003U)
12646#define SYSCFG_EXTICR2_EXTI4_PE (0x00000004U)
12647#define SYSCFG_EXTICR2_EXTI4_PF (0x00000005U)
12648#define SYSCFG_EXTICR2_EXTI4_PG (0x00000006U)
12649#define SYSCFG_EXTICR2_EXTI4_PH (0x00000007U)
12654#define SYSCFG_EXTICR2_EXTI5_PA (0x00000000U)
12655#define SYSCFG_EXTICR2_EXTI5_PB (0x00000010U)
12656#define SYSCFG_EXTICR2_EXTI5_PC (0x00000020U)
12657#define SYSCFG_EXTICR2_EXTI5_PD (0x00000030U)
12658#define SYSCFG_EXTICR2_EXTI5_PE (0x00000040U)
12659#define SYSCFG_EXTICR2_EXTI5_PF (0x00000050U)
12660#define SYSCFG_EXTICR2_EXTI5_PG (0x00000060U)
12665#define SYSCFG_EXTICR2_EXTI6_PA (0x00000000U)
12666#define SYSCFG_EXTICR2_EXTI6_PB (0x00000100U)
12667#define SYSCFG_EXTICR2_EXTI6_PC (0x00000200U)
12668#define SYSCFG_EXTICR2_EXTI6_PD (0x00000300U)
12669#define SYSCFG_EXTICR2_EXTI6_PE (0x00000400U)
12670#define SYSCFG_EXTICR2_EXTI6_PF (0x00000500U)
12671#define SYSCFG_EXTICR2_EXTI6_PG (0x00000600U)
12676#define SYSCFG_EXTICR2_EXTI7_PA (0x00000000U)
12677#define SYSCFG_EXTICR2_EXTI7_PB (0x00001000U)
12678#define SYSCFG_EXTICR2_EXTI7_PC (0x00002000U)
12679#define SYSCFG_EXTICR2_EXTI7_PD (0x00003000U)
12680#define SYSCFG_EXTICR2_EXTI7_PE (0x00004000U)
12681#define SYSCFG_EXTICR2_EXTI7_PF (0x00005000U)
12682#define SYSCFG_EXTICR2_EXTI7_PG (0x00006000U)
12684/***************** Bit definition for SYSCFG_EXTICR3 register ***************/
12685#define SYSCFG_EXTICR3_EXTI8_Pos (0U)
12686#define SYSCFG_EXTICR3_EXTI8_Msk (0xFUL << SYSCFG_EXTICR3_EXTI8_Pos)
12687#define SYSCFG_EXTICR3_EXTI8 SYSCFG_EXTICR3_EXTI8_Msk
12688#define SYSCFG_EXTICR3_EXTI9_Pos (4U)
12689#define SYSCFG_EXTICR3_EXTI9_Msk (0xFUL << SYSCFG_EXTICR3_EXTI9_Pos)
12690#define SYSCFG_EXTICR3_EXTI9 SYSCFG_EXTICR3_EXTI9_Msk
12691#define SYSCFG_EXTICR3_EXTI10_Pos (8U)
12692#define SYSCFG_EXTICR3_EXTI10_Msk (0xFUL << SYSCFG_EXTICR3_EXTI10_Pos)
12693#define SYSCFG_EXTICR3_EXTI10 SYSCFG_EXTICR3_EXTI10_Msk
12694#define SYSCFG_EXTICR3_EXTI11_Pos (12U)
12695#define SYSCFG_EXTICR3_EXTI11_Msk (0xFUL << SYSCFG_EXTICR3_EXTI11_Pos)
12696#define SYSCFG_EXTICR3_EXTI11 SYSCFG_EXTICR3_EXTI11_Msk
12701#define SYSCFG_EXTICR3_EXTI8_PA (0x00000000U)
12702#define SYSCFG_EXTICR3_EXTI8_PB (0x00000001U)
12703#define SYSCFG_EXTICR3_EXTI8_PC (0x00000002U)
12704#define SYSCFG_EXTICR3_EXTI8_PD (0x00000003U)
12705#define SYSCFG_EXTICR3_EXTI8_PE (0x00000004U)
12706#define SYSCFG_EXTICR3_EXTI8_PF (0x00000005U)
12707#define SYSCFG_EXTICR3_EXTI8_PG (0x00000006U)
12712#define SYSCFG_EXTICR3_EXTI9_PA (0x00000000U)
12713#define SYSCFG_EXTICR3_EXTI9_PB (0x00000010U)
12714#define SYSCFG_EXTICR3_EXTI9_PC (0x00000020U)
12715#define SYSCFG_EXTICR3_EXTI9_PD (0x00000030U)
12716#define SYSCFG_EXTICR3_EXTI9_PE (0x00000040U)
12717#define SYSCFG_EXTICR3_EXTI9_PF (0x00000050U)
12718#define SYSCFG_EXTICR3_EXTI9_PG (0x00000060U)
12723#define SYSCFG_EXTICR3_EXTI10_PA (0x00000000U)
12724#define SYSCFG_EXTICR3_EXTI10_PB (0x00000100U)
12725#define SYSCFG_EXTICR3_EXTI10_PC (0x00000200U)
12726#define SYSCFG_EXTICR3_EXTI10_PD (0x00000300U)
12727#define SYSCFG_EXTICR3_EXTI10_PE (0x00000400U)
12728#define SYSCFG_EXTICR3_EXTI10_PF (0x00000500U)
12729#define SYSCFG_EXTICR3_EXTI10_PG (0x00000600U)
12734#define SYSCFG_EXTICR3_EXTI11_PA (0x00000000U)
12735#define SYSCFG_EXTICR3_EXTI11_PB (0x00001000U)
12736#define SYSCFG_EXTICR3_EXTI11_PC (0x00002000U)
12737#define SYSCFG_EXTICR3_EXTI11_PD (0x00003000U)
12738#define SYSCFG_EXTICR3_EXTI11_PE (0x00004000U)
12739#define SYSCFG_EXTICR3_EXTI11_PF (0x00005000U)
12740#define SYSCFG_EXTICR3_EXTI11_PG (0x00006000U)
12742/***************** Bit definition for SYSCFG_EXTICR4 register *****************/
12743#define SYSCFG_EXTICR4_EXTI12_Pos (0U)
12744#define SYSCFG_EXTICR4_EXTI12_Msk (0xFUL << SYSCFG_EXTICR4_EXTI12_Pos)
12745#define SYSCFG_EXTICR4_EXTI12 SYSCFG_EXTICR4_EXTI12_Msk
12746#define SYSCFG_EXTICR4_EXTI13_Pos (4U)
12747#define SYSCFG_EXTICR4_EXTI13_Msk (0xFUL << SYSCFG_EXTICR4_EXTI13_Pos)
12748#define SYSCFG_EXTICR4_EXTI13 SYSCFG_EXTICR4_EXTI13_Msk
12749#define SYSCFG_EXTICR4_EXTI14_Pos (8U)
12750#define SYSCFG_EXTICR4_EXTI14_Msk (0xFUL << SYSCFG_EXTICR4_EXTI14_Pos)
12751#define SYSCFG_EXTICR4_EXTI14 SYSCFG_EXTICR4_EXTI14_Msk
12752#define SYSCFG_EXTICR4_EXTI15_Pos (12U)
12753#define SYSCFG_EXTICR4_EXTI15_Msk (0xFUL << SYSCFG_EXTICR4_EXTI15_Pos)
12754#define SYSCFG_EXTICR4_EXTI15 SYSCFG_EXTICR4_EXTI15_Msk
12759#define SYSCFG_EXTICR4_EXTI12_PA (0x00000000U)
12760#define SYSCFG_EXTICR4_EXTI12_PB (0x00000001U)
12761#define SYSCFG_EXTICR4_EXTI12_PC (0x00000002U)
12762#define SYSCFG_EXTICR4_EXTI12_PD (0x00000003U)
12763#define SYSCFG_EXTICR4_EXTI12_PE (0x00000004U)
12764#define SYSCFG_EXTICR4_EXTI12_PF (0x00000005U)
12765#define SYSCFG_EXTICR4_EXTI12_PG (0x00000006U)
12770#define SYSCFG_EXTICR4_EXTI13_PA (0x00000000U)
12771#define SYSCFG_EXTICR4_EXTI13_PB (0x00000010U)
12772#define SYSCFG_EXTICR4_EXTI13_PC (0x00000020U)
12773#define SYSCFG_EXTICR4_EXTI13_PD (0x00000030U)
12774#define SYSCFG_EXTICR4_EXTI13_PE (0x00000040U)
12775#define SYSCFG_EXTICR4_EXTI13_PF (0x00000050U)
12776#define SYSCFG_EXTICR4_EXTI13_PG (0x00000060U)
12781#define SYSCFG_EXTICR4_EXTI14_PA (0x00000000U)
12782#define SYSCFG_EXTICR4_EXTI14_PB (0x00000100U)
12783#define SYSCFG_EXTICR4_EXTI14_PC (0x00000200U)
12784#define SYSCFG_EXTICR4_EXTI14_PD (0x00000300U)
12785#define SYSCFG_EXTICR4_EXTI14_PE (0x00000400U)
12786#define SYSCFG_EXTICR4_EXTI14_PF (0x00000500U)
12787#define SYSCFG_EXTICR4_EXTI14_PG (0x00000600U)
12792#define SYSCFG_EXTICR4_EXTI15_PA (0x00000000U)
12793#define SYSCFG_EXTICR4_EXTI15_PB (0x00001000U)
12794#define SYSCFG_EXTICR4_EXTI15_PC (0x00002000U)
12795#define SYSCFG_EXTICR4_EXTI15_PD (0x00003000U)
12796#define SYSCFG_EXTICR4_EXTI15_PE (0x00004000U)
12797#define SYSCFG_EXTICR4_EXTI15_PF (0x00005000U)
12798#define SYSCFG_EXTICR4_EXTI15_PG (0x00006000U)
12800/***************** Bit definition for SYSCFG_CFGR2 register ****************/
12801#define SYSCFG_CFGR2_LOCKUP_LOCK_Pos (0U)
12802#define SYSCFG_CFGR2_LOCKUP_LOCK_Msk (0x1UL << SYSCFG_CFGR2_LOCKUP_LOCK_Pos)
12803#define SYSCFG_CFGR2_LOCKUP_LOCK SYSCFG_CFGR2_LOCKUP_LOCK_Msk
12804#define SYSCFG_CFGR2_SRAM_PARITY_LOCK_Pos (1U)
12805#define SYSCFG_CFGR2_SRAM_PARITY_LOCK_Msk (0x1UL << SYSCFG_CFGR2_SRAM_PARITY_LOCK_Pos)
12806#define SYSCFG_CFGR2_SRAM_PARITY_LOCK SYSCFG_CFGR2_SRAM_PARITY_LOCK_Msk
12807#define SYSCFG_CFGR2_PVD_LOCK_Pos (2U)
12808#define SYSCFG_CFGR2_PVD_LOCK_Msk (0x1UL << SYSCFG_CFGR2_PVD_LOCK_Pos)
12809#define SYSCFG_CFGR2_PVD_LOCK SYSCFG_CFGR2_PVD_LOCK_Msk
12810#define SYSCFG_CFGR2_BYP_ADDR_PAR_Pos (4U)
12811#define SYSCFG_CFGR2_BYP_ADDR_PAR_Msk (0x1UL << SYSCFG_CFGR2_BYP_ADDR_PAR_Pos)
12812#define SYSCFG_CFGR2_BYP_ADDR_PAR SYSCFG_CFGR2_BYP_ADDR_PAR_Msk
12813#define SYSCFG_CFGR2_SRAM_PE_Pos (8U)
12814#define SYSCFG_CFGR2_SRAM_PE_Msk (0x1UL << SYSCFG_CFGR2_SRAM_PE_Pos)
12815#define SYSCFG_CFGR2_SRAM_PE SYSCFG_CFGR2_SRAM_PE_Msk
12816/***************** Bit definition for SYSCFG_CFGR4 register *****************/
12817#define SYSCFG_CFGR4_ADC12_EXT2_RMP_Pos (0U)
12818#define SYSCFG_CFGR4_ADC12_EXT2_RMP_Msk (0x1UL << SYSCFG_CFGR4_ADC12_EXT2_RMP_Pos)
12819#define SYSCFG_CFGR4_ADC12_EXT2_RMP SYSCFG_CFGR4_ADC12_EXT2_RMP_Msk
12820#define SYSCFG_CFGR4_ADC12_EXT3_RMP_Pos (1U)
12821#define SYSCFG_CFGR4_ADC12_EXT3_RMP_Msk (0x1UL << SYSCFG_CFGR4_ADC12_EXT3_RMP_Pos)
12822#define SYSCFG_CFGR4_ADC12_EXT3_RMP SYSCFG_CFGR4_ADC12_EXT3_RMP_Msk
12823#define SYSCFG_CFGR4_ADC12_EXT5_RMP_Pos (2U)
12824#define SYSCFG_CFGR4_ADC12_EXT5_RMP_Msk (0x1UL << SYSCFG_CFGR4_ADC12_EXT5_RMP_Pos)
12825#define SYSCFG_CFGR4_ADC12_EXT5_RMP SYSCFG_CFGR4_ADC12_EXT5_RMP_Msk
12826#define SYSCFG_CFGR4_ADC12_EXT13_RMP_Pos (3U)
12827#define SYSCFG_CFGR4_ADC12_EXT13_RMP_Msk (0x1UL << SYSCFG_CFGR4_ADC12_EXT13_RMP_Pos)
12828#define SYSCFG_CFGR4_ADC12_EXT13_RMP SYSCFG_CFGR4_ADC12_EXT13_RMP_Msk
12829#define SYSCFG_CFGR4_ADC12_EXT15_RMP_Pos (4U)
12830#define SYSCFG_CFGR4_ADC12_EXT15_RMP_Msk (0x1UL << SYSCFG_CFGR4_ADC12_EXT15_RMP_Pos)
12831#define SYSCFG_CFGR4_ADC12_EXT15_RMP SYSCFG_CFGR4_ADC12_EXT15_RMP_Msk
12832#define SYSCFG_CFGR4_ADC12_JEXT3_RMP_Pos (5U)
12833#define SYSCFG_CFGR4_ADC12_JEXT3_RMP_Msk (0x1UL << SYSCFG_CFGR4_ADC12_JEXT3_RMP_Pos)
12834#define SYSCFG_CFGR4_ADC12_JEXT3_RMP SYSCFG_CFGR4_ADC12_JEXT3_RMP_Msk
12835#define SYSCFG_CFGR4_ADC12_JEXT6_RMP_Pos (6U)
12836#define SYSCFG_CFGR4_ADC12_JEXT6_RMP_Msk (0x1UL << SYSCFG_CFGR4_ADC12_JEXT6_RMP_Pos)
12837#define SYSCFG_CFGR4_ADC12_JEXT6_RMP SYSCFG_CFGR4_ADC12_JEXT6_RMP_Msk
12838#define SYSCFG_CFGR4_ADC12_JEXT13_RMP_Pos (7U)
12839#define SYSCFG_CFGR4_ADC12_JEXT13_RMP_Msk (0x1UL << SYSCFG_CFGR4_ADC12_JEXT13_RMP_Pos)
12840#define SYSCFG_CFGR4_ADC12_JEXT13_RMP SYSCFG_CFGR4_ADC12_JEXT13_RMP_Msk
12841#define SYSCFG_CFGR4_ADC34_EXT5_RMP_Pos (8U)
12842#define SYSCFG_CFGR4_ADC34_EXT5_RMP_Msk (0x1UL << SYSCFG_CFGR4_ADC34_EXT5_RMP_Pos)
12843#define SYSCFG_CFGR4_ADC34_EXT5_RMP SYSCFG_CFGR4_ADC34_EXT5_RMP_Msk
12844#define SYSCFG_CFGR4_ADC34_EXT6_RMP_Pos (9U)
12845#define SYSCFG_CFGR4_ADC34_EXT6_RMP_Msk (0x1UL << SYSCFG_CFGR4_ADC34_EXT6_RMP_Pos)
12846#define SYSCFG_CFGR4_ADC34_EXT6_RMP SYSCFG_CFGR4_ADC34_EXT6_RMP_Msk
12847#define SYSCFG_CFGR4_ADC34_EXT15_RMP_Pos (10U)
12848#define SYSCFG_CFGR4_ADC34_EXT15_RMP_Msk (0x1UL << SYSCFG_CFGR4_ADC34_EXT15_RMP_Pos)
12849#define SYSCFG_CFGR4_ADC34_EXT15_RMP SYSCFG_CFGR4_ADC34_EXT15_RMP_Msk
12850#define SYSCFG_CFGR4_ADC34_JEXT5_RMP_Pos (11U)
12851#define SYSCFG_CFGR4_ADC34_JEXT5_RMP_Msk (0x1UL << SYSCFG_CFGR4_ADC34_JEXT5_RMP_Pos)
12852#define SYSCFG_CFGR4_ADC34_JEXT5_RMP SYSCFG_CFGR4_ADC34_JEXT5_RMP_Msk
12853#define SYSCFG_CFGR4_ADC34_JEXT11_RMP_Pos (12U)
12854#define SYSCFG_CFGR4_ADC34_JEXT11_RMP_Msk (0x1UL << SYSCFG_CFGR4_ADC34_JEXT11_RMP_Pos)
12855#define SYSCFG_CFGR4_ADC34_JEXT11_RMP SYSCFG_CFGR4_ADC34_JEXT11_RMP_Msk
12856#define SYSCFG_CFGR4_ADC34_JEXT14_RMP_Pos (13U)
12857#define SYSCFG_CFGR4_ADC34_JEXT14_RMP_Msk (0x1UL << SYSCFG_CFGR4_ADC34_JEXT14_RMP_Pos)
12858#define SYSCFG_CFGR4_ADC34_JEXT14_RMP SYSCFG_CFGR4_ADC34_JEXT14_RMP_Msk
12860/******************************************************************************/
12861/* */
12862/* TIM */
12863/* */
12864/******************************************************************************/
12865/******************* Bit definition for TIM_CR1 register ********************/
12866#define TIM_CR1_CEN_Pos (0U)
12867#define TIM_CR1_CEN_Msk (0x1UL << TIM_CR1_CEN_Pos)
12868#define TIM_CR1_CEN TIM_CR1_CEN_Msk
12869#define TIM_CR1_UDIS_Pos (1U)
12870#define TIM_CR1_UDIS_Msk (0x1UL << TIM_CR1_UDIS_Pos)
12871#define TIM_CR1_UDIS TIM_CR1_UDIS_Msk
12872#define TIM_CR1_URS_Pos (2U)
12873#define TIM_CR1_URS_Msk (0x1UL << TIM_CR1_URS_Pos)
12874#define TIM_CR1_URS TIM_CR1_URS_Msk
12875#define TIM_CR1_OPM_Pos (3U)
12876#define TIM_CR1_OPM_Msk (0x1UL << TIM_CR1_OPM_Pos)
12877#define TIM_CR1_OPM TIM_CR1_OPM_Msk
12878#define TIM_CR1_DIR_Pos (4U)
12879#define TIM_CR1_DIR_Msk (0x1UL << TIM_CR1_DIR_Pos)
12880#define TIM_CR1_DIR TIM_CR1_DIR_Msk
12882#define TIM_CR1_CMS_Pos (5U)
12883#define TIM_CR1_CMS_Msk (0x3UL << TIM_CR1_CMS_Pos)
12884#define TIM_CR1_CMS TIM_CR1_CMS_Msk
12885#define TIM_CR1_CMS_0 (0x1UL << TIM_CR1_CMS_Pos)
12886#define TIM_CR1_CMS_1 (0x2UL << TIM_CR1_CMS_Pos)
12888#define TIM_CR1_ARPE_Pos (7U)
12889#define TIM_CR1_ARPE_Msk (0x1UL << TIM_CR1_ARPE_Pos)
12890#define TIM_CR1_ARPE TIM_CR1_ARPE_Msk
12892#define TIM_CR1_CKD_Pos (8U)
12893#define TIM_CR1_CKD_Msk (0x3UL << TIM_CR1_CKD_Pos)
12894#define TIM_CR1_CKD TIM_CR1_CKD_Msk
12895#define TIM_CR1_CKD_0 (0x1UL << TIM_CR1_CKD_Pos)
12896#define TIM_CR1_CKD_1 (0x2UL << TIM_CR1_CKD_Pos)
12898#define TIM_CR1_UIFREMAP_Pos (11U)
12899#define TIM_CR1_UIFREMAP_Msk (0x1UL << TIM_CR1_UIFREMAP_Pos)
12900#define TIM_CR1_UIFREMAP TIM_CR1_UIFREMAP_Msk
12902/******************* Bit definition for TIM_CR2 register ********************/
12903#define TIM_CR2_CCPC_Pos (0U)
12904#define TIM_CR2_CCPC_Msk (0x1UL << TIM_CR2_CCPC_Pos)
12905#define TIM_CR2_CCPC TIM_CR2_CCPC_Msk
12906#define TIM_CR2_CCUS_Pos (2U)
12907#define TIM_CR2_CCUS_Msk (0x1UL << TIM_CR2_CCUS_Pos)
12908#define TIM_CR2_CCUS TIM_CR2_CCUS_Msk
12909#define TIM_CR2_CCDS_Pos (3U)
12910#define TIM_CR2_CCDS_Msk (0x1UL << TIM_CR2_CCDS_Pos)
12911#define TIM_CR2_CCDS TIM_CR2_CCDS_Msk
12913#define TIM_CR2_MMS_Pos (4U)
12914#define TIM_CR2_MMS_Msk (0x7UL << TIM_CR2_MMS_Pos)
12915#define TIM_CR2_MMS TIM_CR2_MMS_Msk
12916#define TIM_CR2_MMS_0 (0x1UL << TIM_CR2_MMS_Pos)
12917#define TIM_CR2_MMS_1 (0x2UL << TIM_CR2_MMS_Pos)
12918#define TIM_CR2_MMS_2 (0x4UL << TIM_CR2_MMS_Pos)
12920#define TIM_CR2_TI1S_Pos (7U)
12921#define TIM_CR2_TI1S_Msk (0x1UL << TIM_CR2_TI1S_Pos)
12922#define TIM_CR2_TI1S TIM_CR2_TI1S_Msk
12923#define TIM_CR2_OIS1_Pos (8U)
12924#define TIM_CR2_OIS1_Msk (0x1UL << TIM_CR2_OIS1_Pos)
12925#define TIM_CR2_OIS1 TIM_CR2_OIS1_Msk
12926#define TIM_CR2_OIS1N_Pos (9U)
12927#define TIM_CR2_OIS1N_Msk (0x1UL << TIM_CR2_OIS1N_Pos)
12928#define TIM_CR2_OIS1N TIM_CR2_OIS1N_Msk
12929#define TIM_CR2_OIS2_Pos (10U)
12930#define TIM_CR2_OIS2_Msk (0x1UL << TIM_CR2_OIS2_Pos)
12931#define TIM_CR2_OIS2 TIM_CR2_OIS2_Msk
12932#define TIM_CR2_OIS2N_Pos (11U)
12933#define TIM_CR2_OIS2N_Msk (0x1UL << TIM_CR2_OIS2N_Pos)
12934#define TIM_CR2_OIS2N TIM_CR2_OIS2N_Msk
12935#define TIM_CR2_OIS3_Pos (12U)
12936#define TIM_CR2_OIS3_Msk (0x1UL << TIM_CR2_OIS3_Pos)
12937#define TIM_CR2_OIS3 TIM_CR2_OIS3_Msk
12938#define TIM_CR2_OIS3N_Pos (13U)
12939#define TIM_CR2_OIS3N_Msk (0x1UL << TIM_CR2_OIS3N_Pos)
12940#define TIM_CR2_OIS3N TIM_CR2_OIS3N_Msk
12941#define TIM_CR2_OIS4_Pos (14U)
12942#define TIM_CR2_OIS4_Msk (0x1UL << TIM_CR2_OIS4_Pos)
12943#define TIM_CR2_OIS4 TIM_CR2_OIS4_Msk
12945#define TIM_CR2_OIS5_Pos (16U)
12946#define TIM_CR2_OIS5_Msk (0x1UL << TIM_CR2_OIS5_Pos)
12947#define TIM_CR2_OIS5 TIM_CR2_OIS5_Msk
12948#define TIM_CR2_OIS6_Pos (18U)
12949#define TIM_CR2_OIS6_Msk (0x1UL << TIM_CR2_OIS6_Pos)
12950#define TIM_CR2_OIS6 TIM_CR2_OIS6_Msk
12952#define TIM_CR2_MMS2_Pos (20U)
12953#define TIM_CR2_MMS2_Msk (0xFUL << TIM_CR2_MMS2_Pos)
12954#define TIM_CR2_MMS2 TIM_CR2_MMS2_Msk
12955#define TIM_CR2_MMS2_0 (0x1UL << TIM_CR2_MMS2_Pos)
12956#define TIM_CR2_MMS2_1 (0x2UL << TIM_CR2_MMS2_Pos)
12957#define TIM_CR2_MMS2_2 (0x4UL << TIM_CR2_MMS2_Pos)
12958#define TIM_CR2_MMS2_3 (0x8UL << TIM_CR2_MMS2_Pos)
12960/******************* Bit definition for TIM_SMCR register *******************/
12961#define TIM_SMCR_SMS_Pos (0U)
12962#define TIM_SMCR_SMS_Msk (0x10007UL << TIM_SMCR_SMS_Pos)
12963#define TIM_SMCR_SMS TIM_SMCR_SMS_Msk
12964#define TIM_SMCR_SMS_0 (0x00000001U)
12965#define TIM_SMCR_SMS_1 (0x00000002U)
12966#define TIM_SMCR_SMS_2 (0x00000004U)
12967#define TIM_SMCR_SMS_3 (0x00010000U)
12969#define TIM_SMCR_OCCS_Pos (3U)
12970#define TIM_SMCR_OCCS_Msk (0x1UL << TIM_SMCR_OCCS_Pos)
12971#define TIM_SMCR_OCCS TIM_SMCR_OCCS_Msk
12973#define TIM_SMCR_TS_Pos (4U)
12974#define TIM_SMCR_TS_Msk (0x7UL << TIM_SMCR_TS_Pos)
12975#define TIM_SMCR_TS TIM_SMCR_TS_Msk
12976#define TIM_SMCR_TS_0 (0x1UL << TIM_SMCR_TS_Pos)
12977#define TIM_SMCR_TS_1 (0x2UL << TIM_SMCR_TS_Pos)
12978#define TIM_SMCR_TS_2 (0x4UL << TIM_SMCR_TS_Pos)
12980#define TIM_SMCR_MSM_Pos (7U)
12981#define TIM_SMCR_MSM_Msk (0x1UL << TIM_SMCR_MSM_Pos)
12982#define TIM_SMCR_MSM TIM_SMCR_MSM_Msk
12984#define TIM_SMCR_ETF_Pos (8U)
12985#define TIM_SMCR_ETF_Msk (0xFUL << TIM_SMCR_ETF_Pos)
12986#define TIM_SMCR_ETF TIM_SMCR_ETF_Msk
12987#define TIM_SMCR_ETF_0 (0x1UL << TIM_SMCR_ETF_Pos)
12988#define TIM_SMCR_ETF_1 (0x2UL << TIM_SMCR_ETF_Pos)
12989#define TIM_SMCR_ETF_2 (0x4UL << TIM_SMCR_ETF_Pos)
12990#define TIM_SMCR_ETF_3 (0x8UL << TIM_SMCR_ETF_Pos)
12992#define TIM_SMCR_ETPS_Pos (12U)
12993#define TIM_SMCR_ETPS_Msk (0x3UL << TIM_SMCR_ETPS_Pos)
12994#define TIM_SMCR_ETPS TIM_SMCR_ETPS_Msk
12995#define TIM_SMCR_ETPS_0 (0x1UL << TIM_SMCR_ETPS_Pos)
12996#define TIM_SMCR_ETPS_1 (0x2UL << TIM_SMCR_ETPS_Pos)
12998#define TIM_SMCR_ECE_Pos (14U)
12999#define TIM_SMCR_ECE_Msk (0x1UL << TIM_SMCR_ECE_Pos)
13000#define TIM_SMCR_ECE TIM_SMCR_ECE_Msk
13001#define TIM_SMCR_ETP_Pos (15U)
13002#define TIM_SMCR_ETP_Msk (0x1UL << TIM_SMCR_ETP_Pos)
13003#define TIM_SMCR_ETP TIM_SMCR_ETP_Msk
13005/******************* Bit definition for TIM_DIER register *******************/
13006#define TIM_DIER_UIE_Pos (0U)
13007#define TIM_DIER_UIE_Msk (0x1UL << TIM_DIER_UIE_Pos)
13008#define TIM_DIER_UIE TIM_DIER_UIE_Msk
13009#define TIM_DIER_CC1IE_Pos (1U)
13010#define TIM_DIER_CC1IE_Msk (0x1UL << TIM_DIER_CC1IE_Pos)
13011#define TIM_DIER_CC1IE TIM_DIER_CC1IE_Msk
13012#define TIM_DIER_CC2IE_Pos (2U)
13013#define TIM_DIER_CC2IE_Msk (0x1UL << TIM_DIER_CC2IE_Pos)
13014#define TIM_DIER_CC2IE TIM_DIER_CC2IE_Msk
13015#define TIM_DIER_CC3IE_Pos (3U)
13016#define TIM_DIER_CC3IE_Msk (0x1UL << TIM_DIER_CC3IE_Pos)
13017#define TIM_DIER_CC3IE TIM_DIER_CC3IE_Msk
13018#define TIM_DIER_CC4IE_Pos (4U)
13019#define TIM_DIER_CC4IE_Msk (0x1UL << TIM_DIER_CC4IE_Pos)
13020#define TIM_DIER_CC4IE TIM_DIER_CC4IE_Msk
13021#define TIM_DIER_COMIE_Pos (5U)
13022#define TIM_DIER_COMIE_Msk (0x1UL << TIM_DIER_COMIE_Pos)
13023#define TIM_DIER_COMIE TIM_DIER_COMIE_Msk
13024#define TIM_DIER_TIE_Pos (6U)
13025#define TIM_DIER_TIE_Msk (0x1UL << TIM_DIER_TIE_Pos)
13026#define TIM_DIER_TIE TIM_DIER_TIE_Msk
13027#define TIM_DIER_BIE_Pos (7U)
13028#define TIM_DIER_BIE_Msk (0x1UL << TIM_DIER_BIE_Pos)
13029#define TIM_DIER_BIE TIM_DIER_BIE_Msk
13030#define TIM_DIER_UDE_Pos (8U)
13031#define TIM_DIER_UDE_Msk (0x1UL << TIM_DIER_UDE_Pos)
13032#define TIM_DIER_UDE TIM_DIER_UDE_Msk
13033#define TIM_DIER_CC1DE_Pos (9U)
13034#define TIM_DIER_CC1DE_Msk (0x1UL << TIM_DIER_CC1DE_Pos)
13035#define TIM_DIER_CC1DE TIM_DIER_CC1DE_Msk
13036#define TIM_DIER_CC2DE_Pos (10U)
13037#define TIM_DIER_CC2DE_Msk (0x1UL << TIM_DIER_CC2DE_Pos)
13038#define TIM_DIER_CC2DE TIM_DIER_CC2DE_Msk
13039#define TIM_DIER_CC3DE_Pos (11U)
13040#define TIM_DIER_CC3DE_Msk (0x1UL << TIM_DIER_CC3DE_Pos)
13041#define TIM_DIER_CC3DE TIM_DIER_CC3DE_Msk
13042#define TIM_DIER_CC4DE_Pos (12U)
13043#define TIM_DIER_CC4DE_Msk (0x1UL << TIM_DIER_CC4DE_Pos)
13044#define TIM_DIER_CC4DE TIM_DIER_CC4DE_Msk
13045#define TIM_DIER_COMDE_Pos (13U)
13046#define TIM_DIER_COMDE_Msk (0x1UL << TIM_DIER_COMDE_Pos)
13047#define TIM_DIER_COMDE TIM_DIER_COMDE_Msk
13048#define TIM_DIER_TDE_Pos (14U)
13049#define TIM_DIER_TDE_Msk (0x1UL << TIM_DIER_TDE_Pos)
13050#define TIM_DIER_TDE TIM_DIER_TDE_Msk
13052/******************** Bit definition for TIM_SR register ********************/
13053#define TIM_SR_UIF_Pos (0U)
13054#define TIM_SR_UIF_Msk (0x1UL << TIM_SR_UIF_Pos)
13055#define TIM_SR_UIF TIM_SR_UIF_Msk
13056#define TIM_SR_CC1IF_Pos (1U)
13057#define TIM_SR_CC1IF_Msk (0x1UL << TIM_SR_CC1IF_Pos)
13058#define TIM_SR_CC1IF TIM_SR_CC1IF_Msk
13059#define TIM_SR_CC2IF_Pos (2U)
13060#define TIM_SR_CC2IF_Msk (0x1UL << TIM_SR_CC2IF_Pos)
13061#define TIM_SR_CC2IF TIM_SR_CC2IF_Msk
13062#define TIM_SR_CC3IF_Pos (3U)
13063#define TIM_SR_CC3IF_Msk (0x1UL << TIM_SR_CC3IF_Pos)
13064#define TIM_SR_CC3IF TIM_SR_CC3IF_Msk
13065#define TIM_SR_CC4IF_Pos (4U)
13066#define TIM_SR_CC4IF_Msk (0x1UL << TIM_SR_CC4IF_Pos)
13067#define TIM_SR_CC4IF TIM_SR_CC4IF_Msk
13068#define TIM_SR_COMIF_Pos (5U)
13069#define TIM_SR_COMIF_Msk (0x1UL << TIM_SR_COMIF_Pos)
13070#define TIM_SR_COMIF TIM_SR_COMIF_Msk
13071#define TIM_SR_TIF_Pos (6U)
13072#define TIM_SR_TIF_Msk (0x1UL << TIM_SR_TIF_Pos)
13073#define TIM_SR_TIF TIM_SR_TIF_Msk
13074#define TIM_SR_BIF_Pos (7U)
13075#define TIM_SR_BIF_Msk (0x1UL << TIM_SR_BIF_Pos)
13076#define TIM_SR_BIF TIM_SR_BIF_Msk
13077#define TIM_SR_B2IF_Pos (8U)
13078#define TIM_SR_B2IF_Msk (0x1UL << TIM_SR_B2IF_Pos)
13079#define TIM_SR_B2IF TIM_SR_B2IF_Msk
13080#define TIM_SR_CC1OF_Pos (9U)
13081#define TIM_SR_CC1OF_Msk (0x1UL << TIM_SR_CC1OF_Pos)
13082#define TIM_SR_CC1OF TIM_SR_CC1OF_Msk
13083#define TIM_SR_CC2OF_Pos (10U)
13084#define TIM_SR_CC2OF_Msk (0x1UL << TIM_SR_CC2OF_Pos)
13085#define TIM_SR_CC2OF TIM_SR_CC2OF_Msk
13086#define TIM_SR_CC3OF_Pos (11U)
13087#define TIM_SR_CC3OF_Msk (0x1UL << TIM_SR_CC3OF_Pos)
13088#define TIM_SR_CC3OF TIM_SR_CC3OF_Msk
13089#define TIM_SR_CC4OF_Pos (12U)
13090#define TIM_SR_CC4OF_Msk (0x1UL << TIM_SR_CC4OF_Pos)
13091#define TIM_SR_CC4OF TIM_SR_CC4OF_Msk
13092#define TIM_SR_CC5IF_Pos (16U)
13093#define TIM_SR_CC5IF_Msk (0x1UL << TIM_SR_CC5IF_Pos)
13094#define TIM_SR_CC5IF TIM_SR_CC5IF_Msk
13095#define TIM_SR_CC6IF_Pos (17U)
13096#define TIM_SR_CC6IF_Msk (0x1UL << TIM_SR_CC6IF_Pos)
13097#define TIM_SR_CC6IF TIM_SR_CC6IF_Msk
13099/******************* Bit definition for TIM_EGR register ********************/
13100#define TIM_EGR_UG_Pos (0U)
13101#define TIM_EGR_UG_Msk (0x1UL << TIM_EGR_UG_Pos)
13102#define TIM_EGR_UG TIM_EGR_UG_Msk
13103#define TIM_EGR_CC1G_Pos (1U)
13104#define TIM_EGR_CC1G_Msk (0x1UL << TIM_EGR_CC1G_Pos)
13105#define TIM_EGR_CC1G TIM_EGR_CC1G_Msk
13106#define TIM_EGR_CC2G_Pos (2U)
13107#define TIM_EGR_CC2G_Msk (0x1UL << TIM_EGR_CC2G_Pos)
13108#define TIM_EGR_CC2G TIM_EGR_CC2G_Msk
13109#define TIM_EGR_CC3G_Pos (3U)
13110#define TIM_EGR_CC3G_Msk (0x1UL << TIM_EGR_CC3G_Pos)
13111#define TIM_EGR_CC3G TIM_EGR_CC3G_Msk
13112#define TIM_EGR_CC4G_Pos (4U)
13113#define TIM_EGR_CC4G_Msk (0x1UL << TIM_EGR_CC4G_Pos)
13114#define TIM_EGR_CC4G TIM_EGR_CC4G_Msk
13115#define TIM_EGR_COMG_Pos (5U)
13116#define TIM_EGR_COMG_Msk (0x1UL << TIM_EGR_COMG_Pos)
13117#define TIM_EGR_COMG TIM_EGR_COMG_Msk
13118#define TIM_EGR_TG_Pos (6U)
13119#define TIM_EGR_TG_Msk (0x1UL << TIM_EGR_TG_Pos)
13120#define TIM_EGR_TG TIM_EGR_TG_Msk
13121#define TIM_EGR_BG_Pos (7U)
13122#define TIM_EGR_BG_Msk (0x1UL << TIM_EGR_BG_Pos)
13123#define TIM_EGR_BG TIM_EGR_BG_Msk
13124#define TIM_EGR_B2G_Pos (8U)
13125#define TIM_EGR_B2G_Msk (0x1UL << TIM_EGR_B2G_Pos)
13126#define TIM_EGR_B2G TIM_EGR_B2G_Msk
13128/****************** Bit definition for TIM_CCMR1 register *******************/
13129#define TIM_CCMR1_CC1S_Pos (0U)
13130#define TIM_CCMR1_CC1S_Msk (0x3UL << TIM_CCMR1_CC1S_Pos)
13131#define TIM_CCMR1_CC1S TIM_CCMR1_CC1S_Msk
13132#define TIM_CCMR1_CC1S_0 (0x1UL << TIM_CCMR1_CC1S_Pos)
13133#define TIM_CCMR1_CC1S_1 (0x2UL << TIM_CCMR1_CC1S_Pos)
13135#define TIM_CCMR1_OC1FE_Pos (2U)
13136#define TIM_CCMR1_OC1FE_Msk (0x1UL << TIM_CCMR1_OC1FE_Pos)
13137#define TIM_CCMR1_OC1FE TIM_CCMR1_OC1FE_Msk
13138#define TIM_CCMR1_OC1PE_Pos (3U)
13139#define TIM_CCMR1_OC1PE_Msk (0x1UL << TIM_CCMR1_OC1PE_Pos)
13140#define TIM_CCMR1_OC1PE TIM_CCMR1_OC1PE_Msk
13142#define TIM_CCMR1_OC1M_Pos (4U)
13143#define TIM_CCMR1_OC1M_Msk (0x1007UL << TIM_CCMR1_OC1M_Pos)
13144#define TIM_CCMR1_OC1M TIM_CCMR1_OC1M_Msk
13145#define TIM_CCMR1_OC1M_0 (0x00000010U)
13146#define TIM_CCMR1_OC1M_1 (0x00000020U)
13147#define TIM_CCMR1_OC1M_2 (0x00000040U)
13148#define TIM_CCMR1_OC1M_3 (0x00010000U)
13150#define TIM_CCMR1_OC1CE_Pos (7U)
13151#define TIM_CCMR1_OC1CE_Msk (0x1UL << TIM_CCMR1_OC1CE_Pos)
13152#define TIM_CCMR1_OC1CE TIM_CCMR1_OC1CE_Msk
13154#define TIM_CCMR1_CC2S_Pos (8U)
13155#define TIM_CCMR1_CC2S_Msk (0x3UL << TIM_CCMR1_CC2S_Pos)
13156#define TIM_CCMR1_CC2S TIM_CCMR1_CC2S_Msk
13157#define TIM_CCMR1_CC2S_0 (0x1UL << TIM_CCMR1_CC2S_Pos)
13158#define TIM_CCMR1_CC2S_1 (0x2UL << TIM_CCMR1_CC2S_Pos)
13160#define TIM_CCMR1_OC2FE_Pos (10U)
13161#define TIM_CCMR1_OC2FE_Msk (0x1UL << TIM_CCMR1_OC2FE_Pos)
13162#define TIM_CCMR1_OC2FE TIM_CCMR1_OC2FE_Msk
13163#define TIM_CCMR1_OC2PE_Pos (11U)
13164#define TIM_CCMR1_OC2PE_Msk (0x1UL << TIM_CCMR1_OC2PE_Pos)
13165#define TIM_CCMR1_OC2PE TIM_CCMR1_OC2PE_Msk
13167#define TIM_CCMR1_OC2M_Pos (12U)
13168#define TIM_CCMR1_OC2M_Msk (0x1007UL << TIM_CCMR1_OC2M_Pos)
13169#define TIM_CCMR1_OC2M TIM_CCMR1_OC2M_Msk
13170#define TIM_CCMR1_OC2M_0 (0x00001000U)
13171#define TIM_CCMR1_OC2M_1 (0x00002000U)
13172#define TIM_CCMR1_OC2M_2 (0x00004000U)
13173#define TIM_CCMR1_OC2M_3 (0x01000000U)
13175#define TIM_CCMR1_OC2CE_Pos (15U)
13176#define TIM_CCMR1_OC2CE_Msk (0x1UL << TIM_CCMR1_OC2CE_Pos)
13177#define TIM_CCMR1_OC2CE TIM_CCMR1_OC2CE_Msk
13179/*----------------------------------------------------------------------------*/
13180
13181#define TIM_CCMR1_IC1PSC_Pos (2U)
13182#define TIM_CCMR1_IC1PSC_Msk (0x3UL << TIM_CCMR1_IC1PSC_Pos)
13183#define TIM_CCMR1_IC1PSC TIM_CCMR1_IC1PSC_Msk
13184#define TIM_CCMR1_IC1PSC_0 (0x1UL << TIM_CCMR1_IC1PSC_Pos)
13185#define TIM_CCMR1_IC1PSC_1 (0x2UL << TIM_CCMR1_IC1PSC_Pos)
13187#define TIM_CCMR1_IC1F_Pos (4U)
13188#define TIM_CCMR1_IC1F_Msk (0xFUL << TIM_CCMR1_IC1F_Pos)
13189#define TIM_CCMR1_IC1F TIM_CCMR1_IC1F_Msk
13190#define TIM_CCMR1_IC1F_0 (0x1UL << TIM_CCMR1_IC1F_Pos)
13191#define TIM_CCMR1_IC1F_1 (0x2UL << TIM_CCMR1_IC1F_Pos)
13192#define TIM_CCMR1_IC1F_2 (0x4UL << TIM_CCMR1_IC1F_Pos)
13193#define TIM_CCMR1_IC1F_3 (0x8UL << TIM_CCMR1_IC1F_Pos)
13195#define TIM_CCMR1_IC2PSC_Pos (10U)
13196#define TIM_CCMR1_IC2PSC_Msk (0x3UL << TIM_CCMR1_IC2PSC_Pos)
13197#define TIM_CCMR1_IC2PSC TIM_CCMR1_IC2PSC_Msk
13198#define TIM_CCMR1_IC2PSC_0 (0x1UL << TIM_CCMR1_IC2PSC_Pos)
13199#define TIM_CCMR1_IC2PSC_1 (0x2UL << TIM_CCMR1_IC2PSC_Pos)
13201#define TIM_CCMR1_IC2F_Pos (12U)
13202#define TIM_CCMR1_IC2F_Msk (0xFUL << TIM_CCMR1_IC2F_Pos)
13203#define TIM_CCMR1_IC2F TIM_CCMR1_IC2F_Msk
13204#define TIM_CCMR1_IC2F_0 (0x1UL << TIM_CCMR1_IC2F_Pos)
13205#define TIM_CCMR1_IC2F_1 (0x2UL << TIM_CCMR1_IC2F_Pos)
13206#define TIM_CCMR1_IC2F_2 (0x4UL << TIM_CCMR1_IC2F_Pos)
13207#define TIM_CCMR1_IC2F_3 (0x8UL << TIM_CCMR1_IC2F_Pos)
13209/****************** Bit definition for TIM_CCMR2 register *******************/
13210#define TIM_CCMR2_CC3S_Pos (0U)
13211#define TIM_CCMR2_CC3S_Msk (0x3UL << TIM_CCMR2_CC3S_Pos)
13212#define TIM_CCMR2_CC3S TIM_CCMR2_CC3S_Msk
13213#define TIM_CCMR2_CC3S_0 (0x1UL << TIM_CCMR2_CC3S_Pos)
13214#define TIM_CCMR2_CC3S_1 (0x2UL << TIM_CCMR2_CC3S_Pos)
13216#define TIM_CCMR2_OC3FE_Pos (2U)
13217#define TIM_CCMR2_OC3FE_Msk (0x1UL << TIM_CCMR2_OC3FE_Pos)
13218#define TIM_CCMR2_OC3FE TIM_CCMR2_OC3FE_Msk
13219#define TIM_CCMR2_OC3PE_Pos (3U)
13220#define TIM_CCMR2_OC3PE_Msk (0x1UL << TIM_CCMR2_OC3PE_Pos)
13221#define TIM_CCMR2_OC3PE TIM_CCMR2_OC3PE_Msk
13223#define TIM_CCMR2_OC3M_Pos (4U)
13224#define TIM_CCMR2_OC3M_Msk (0x1007UL << TIM_CCMR2_OC3M_Pos)
13225#define TIM_CCMR2_OC3M TIM_CCMR2_OC3M_Msk
13226#define TIM_CCMR2_OC3M_0 (0x00000010U)
13227#define TIM_CCMR2_OC3M_1 (0x00000020U)
13228#define TIM_CCMR2_OC3M_2 (0x00000040U)
13229#define TIM_CCMR2_OC3M_3 (0x00010000U)
13231#define TIM_CCMR2_OC3CE_Pos (7U)
13232#define TIM_CCMR2_OC3CE_Msk (0x1UL << TIM_CCMR2_OC3CE_Pos)
13233#define TIM_CCMR2_OC3CE TIM_CCMR2_OC3CE_Msk
13235#define TIM_CCMR2_CC4S_Pos (8U)
13236#define TIM_CCMR2_CC4S_Msk (0x3UL << TIM_CCMR2_CC4S_Pos)
13237#define TIM_CCMR2_CC4S TIM_CCMR2_CC4S_Msk
13238#define TIM_CCMR2_CC4S_0 (0x1UL << TIM_CCMR2_CC4S_Pos)
13239#define TIM_CCMR2_CC4S_1 (0x2UL << TIM_CCMR2_CC4S_Pos)
13241#define TIM_CCMR2_OC4FE_Pos (10U)
13242#define TIM_CCMR2_OC4FE_Msk (0x1UL << TIM_CCMR2_OC4FE_Pos)
13243#define TIM_CCMR2_OC4FE TIM_CCMR2_OC4FE_Msk
13244#define TIM_CCMR2_OC4PE_Pos (11U)
13245#define TIM_CCMR2_OC4PE_Msk (0x1UL << TIM_CCMR2_OC4PE_Pos)
13246#define TIM_CCMR2_OC4PE TIM_CCMR2_OC4PE_Msk
13248#define TIM_CCMR2_OC4M_Pos (12U)
13249#define TIM_CCMR2_OC4M_Msk (0x1007UL << TIM_CCMR2_OC4M_Pos)
13250#define TIM_CCMR2_OC4M TIM_CCMR2_OC4M_Msk
13251#define TIM_CCMR2_OC4M_0 (0x00001000U)
13252#define TIM_CCMR2_OC4M_1 (0x00002000U)
13253#define TIM_CCMR2_OC4M_2 (0x00004000U)
13254#define TIM_CCMR2_OC4M_3 (0x01000000U)
13256#define TIM_CCMR2_OC4CE_Pos (15U)
13257#define TIM_CCMR2_OC4CE_Msk (0x1UL << TIM_CCMR2_OC4CE_Pos)
13258#define TIM_CCMR2_OC4CE TIM_CCMR2_OC4CE_Msk
13260/*----------------------------------------------------------------------------*/
13261
13262#define TIM_CCMR2_IC3PSC_Pos (2U)
13263#define TIM_CCMR2_IC3PSC_Msk (0x3UL << TIM_CCMR2_IC3PSC_Pos)
13264#define TIM_CCMR2_IC3PSC TIM_CCMR2_IC3PSC_Msk
13265#define TIM_CCMR2_IC3PSC_0 (0x1UL << TIM_CCMR2_IC3PSC_Pos)
13266#define TIM_CCMR2_IC3PSC_1 (0x2UL << TIM_CCMR2_IC3PSC_Pos)
13268#define TIM_CCMR2_IC3F_Pos (4U)
13269#define TIM_CCMR2_IC3F_Msk (0xFUL << TIM_CCMR2_IC3F_Pos)
13270#define TIM_CCMR2_IC3F TIM_CCMR2_IC3F_Msk
13271#define TIM_CCMR2_IC3F_0 (0x1UL << TIM_CCMR2_IC3F_Pos)
13272#define TIM_CCMR2_IC3F_1 (0x2UL << TIM_CCMR2_IC3F_Pos)
13273#define TIM_CCMR2_IC3F_2 (0x4UL << TIM_CCMR2_IC3F_Pos)
13274#define TIM_CCMR2_IC3F_3 (0x8UL << TIM_CCMR2_IC3F_Pos)
13276#define TIM_CCMR2_IC4PSC_Pos (10U)
13277#define TIM_CCMR2_IC4PSC_Msk (0x3UL << TIM_CCMR2_IC4PSC_Pos)
13278#define TIM_CCMR2_IC4PSC TIM_CCMR2_IC4PSC_Msk
13279#define TIM_CCMR2_IC4PSC_0 (0x1UL << TIM_CCMR2_IC4PSC_Pos)
13280#define TIM_CCMR2_IC4PSC_1 (0x2UL << TIM_CCMR2_IC4PSC_Pos)
13282#define TIM_CCMR2_IC4F_Pos (12U)
13283#define TIM_CCMR2_IC4F_Msk (0xFUL << TIM_CCMR2_IC4F_Pos)
13284#define TIM_CCMR2_IC4F TIM_CCMR2_IC4F_Msk
13285#define TIM_CCMR2_IC4F_0 (0x1UL << TIM_CCMR2_IC4F_Pos)
13286#define TIM_CCMR2_IC4F_1 (0x2UL << TIM_CCMR2_IC4F_Pos)
13287#define TIM_CCMR2_IC4F_2 (0x4UL << TIM_CCMR2_IC4F_Pos)
13288#define TIM_CCMR2_IC4F_3 (0x8UL << TIM_CCMR2_IC4F_Pos)
13290/******************* Bit definition for TIM_CCER register *******************/
13291#define TIM_CCER_CC1E_Pos (0U)
13292#define TIM_CCER_CC1E_Msk (0x1UL << TIM_CCER_CC1E_Pos)
13293#define TIM_CCER_CC1E TIM_CCER_CC1E_Msk
13294#define TIM_CCER_CC1P_Pos (1U)
13295#define TIM_CCER_CC1P_Msk (0x1UL << TIM_CCER_CC1P_Pos)
13296#define TIM_CCER_CC1P TIM_CCER_CC1P_Msk
13297#define TIM_CCER_CC1NE_Pos (2U)
13298#define TIM_CCER_CC1NE_Msk (0x1UL << TIM_CCER_CC1NE_Pos)
13299#define TIM_CCER_CC1NE TIM_CCER_CC1NE_Msk
13300#define TIM_CCER_CC1NP_Pos (3U)
13301#define TIM_CCER_CC1NP_Msk (0x1UL << TIM_CCER_CC1NP_Pos)
13302#define TIM_CCER_CC1NP TIM_CCER_CC1NP_Msk
13303#define TIM_CCER_CC2E_Pos (4U)
13304#define TIM_CCER_CC2E_Msk (0x1UL << TIM_CCER_CC2E_Pos)
13305#define TIM_CCER_CC2E TIM_CCER_CC2E_Msk
13306#define TIM_CCER_CC2P_Pos (5U)
13307#define TIM_CCER_CC2P_Msk (0x1UL << TIM_CCER_CC2P_Pos)
13308#define TIM_CCER_CC2P TIM_CCER_CC2P_Msk
13309#define TIM_CCER_CC2NE_Pos (6U)
13310#define TIM_CCER_CC2NE_Msk (0x1UL << TIM_CCER_CC2NE_Pos)
13311#define TIM_CCER_CC2NE TIM_CCER_CC2NE_Msk
13312#define TIM_CCER_CC2NP_Pos (7U)
13313#define TIM_CCER_CC2NP_Msk (0x1UL << TIM_CCER_CC2NP_Pos)
13314#define TIM_CCER_CC2NP TIM_CCER_CC2NP_Msk
13315#define TIM_CCER_CC3E_Pos (8U)
13316#define TIM_CCER_CC3E_Msk (0x1UL << TIM_CCER_CC3E_Pos)
13317#define TIM_CCER_CC3E TIM_CCER_CC3E_Msk
13318#define TIM_CCER_CC3P_Pos (9U)
13319#define TIM_CCER_CC3P_Msk (0x1UL << TIM_CCER_CC3P_Pos)
13320#define TIM_CCER_CC3P TIM_CCER_CC3P_Msk
13321#define TIM_CCER_CC3NE_Pos (10U)
13322#define TIM_CCER_CC3NE_Msk (0x1UL << TIM_CCER_CC3NE_Pos)
13323#define TIM_CCER_CC3NE TIM_CCER_CC3NE_Msk
13324#define TIM_CCER_CC3NP_Pos (11U)
13325#define TIM_CCER_CC3NP_Msk (0x1UL << TIM_CCER_CC3NP_Pos)
13326#define TIM_CCER_CC3NP TIM_CCER_CC3NP_Msk
13327#define TIM_CCER_CC4E_Pos (12U)
13328#define TIM_CCER_CC4E_Msk (0x1UL << TIM_CCER_CC4E_Pos)
13329#define TIM_CCER_CC4E TIM_CCER_CC4E_Msk
13330#define TIM_CCER_CC4P_Pos (13U)
13331#define TIM_CCER_CC4P_Msk (0x1UL << TIM_CCER_CC4P_Pos)
13332#define TIM_CCER_CC4P TIM_CCER_CC4P_Msk
13333#define TIM_CCER_CC4NP_Pos (15U)
13334#define TIM_CCER_CC4NP_Msk (0x1UL << TIM_CCER_CC4NP_Pos)
13335#define TIM_CCER_CC4NP TIM_CCER_CC4NP_Msk
13336#define TIM_CCER_CC5E_Pos (16U)
13337#define TIM_CCER_CC5E_Msk (0x1UL << TIM_CCER_CC5E_Pos)
13338#define TIM_CCER_CC5E TIM_CCER_CC5E_Msk
13339#define TIM_CCER_CC5P_Pos (17U)
13340#define TIM_CCER_CC5P_Msk (0x1UL << TIM_CCER_CC5P_Pos)
13341#define TIM_CCER_CC5P TIM_CCER_CC5P_Msk
13342#define TIM_CCER_CC6E_Pos (20U)
13343#define TIM_CCER_CC6E_Msk (0x1UL << TIM_CCER_CC6E_Pos)
13344#define TIM_CCER_CC6E TIM_CCER_CC6E_Msk
13345#define TIM_CCER_CC6P_Pos (21U)
13346#define TIM_CCER_CC6P_Msk (0x1UL << TIM_CCER_CC6P_Pos)
13347#define TIM_CCER_CC6P TIM_CCER_CC6P_Msk
13349/******************* Bit definition for TIM_CNT register ********************/
13350#define TIM_CNT_CNT_Pos (0U)
13351#define TIM_CNT_CNT_Msk (0xFFFFFFFFUL << TIM_CNT_CNT_Pos)
13352#define TIM_CNT_CNT TIM_CNT_CNT_Msk
13353#define TIM_CNT_UIFCPY_Pos (31U)
13354#define TIM_CNT_UIFCPY_Msk (0x1UL << TIM_CNT_UIFCPY_Pos)
13355#define TIM_CNT_UIFCPY TIM_CNT_UIFCPY_Msk
13357/******************* Bit definition for TIM_PSC register ********************/
13358#define TIM_PSC_PSC_Pos (0U)
13359#define TIM_PSC_PSC_Msk (0xFFFFUL << TIM_PSC_PSC_Pos)
13360#define TIM_PSC_PSC TIM_PSC_PSC_Msk
13362/******************* Bit definition for TIM_ARR register ********************/
13363#define TIM_ARR_ARR_Pos (0U)
13364#define TIM_ARR_ARR_Msk (0xFFFFFFFFUL << TIM_ARR_ARR_Pos)
13365#define TIM_ARR_ARR TIM_ARR_ARR_Msk
13367/******************* Bit definition for TIM_RCR register ********************/
13368#define TIM_RCR_REP_Pos (0U)
13369#define TIM_RCR_REP_Msk (0xFFFFUL << TIM_RCR_REP_Pos)
13370#define TIM_RCR_REP TIM_RCR_REP_Msk
13372/******************* Bit definition for TIM_CCR1 register *******************/
13373#define TIM_CCR1_CCR1_Pos (0U)
13374#define TIM_CCR1_CCR1_Msk (0xFFFFUL << TIM_CCR1_CCR1_Pos)
13375#define TIM_CCR1_CCR1 TIM_CCR1_CCR1_Msk
13377/******************* Bit definition for TIM_CCR2 register *******************/
13378#define TIM_CCR2_CCR2_Pos (0U)
13379#define TIM_CCR2_CCR2_Msk (0xFFFFUL << TIM_CCR2_CCR2_Pos)
13380#define TIM_CCR2_CCR2 TIM_CCR2_CCR2_Msk
13382/******************* Bit definition for TIM_CCR3 register *******************/
13383#define TIM_CCR3_CCR3_Pos (0U)
13384#define TIM_CCR3_CCR3_Msk (0xFFFFUL << TIM_CCR3_CCR3_Pos)
13385#define TIM_CCR3_CCR3 TIM_CCR3_CCR3_Msk
13387/******************* Bit definition for TIM_CCR4 register *******************/
13388#define TIM_CCR4_CCR4_Pos (0U)
13389#define TIM_CCR4_CCR4_Msk (0xFFFFUL << TIM_CCR4_CCR4_Pos)
13390#define TIM_CCR4_CCR4 TIM_CCR4_CCR4_Msk
13392/******************* Bit definition for TIM_CCR5 register *******************/
13393#define TIM_CCR5_CCR5_Pos (0U)
13394#define TIM_CCR5_CCR5_Msk (0xFFFFFFFFUL << TIM_CCR5_CCR5_Pos)
13395#define TIM_CCR5_CCR5 TIM_CCR5_CCR5_Msk
13396#define TIM_CCR5_GC5C1_Pos (29U)
13397#define TIM_CCR5_GC5C1_Msk (0x1UL << TIM_CCR5_GC5C1_Pos)
13398#define TIM_CCR5_GC5C1 TIM_CCR5_GC5C1_Msk
13399#define TIM_CCR5_GC5C2_Pos (30U)
13400#define TIM_CCR5_GC5C2_Msk (0x1UL << TIM_CCR5_GC5C2_Pos)
13401#define TIM_CCR5_GC5C2 TIM_CCR5_GC5C2_Msk
13402#define TIM_CCR5_GC5C3_Pos (31U)
13403#define TIM_CCR5_GC5C3_Msk (0x1UL << TIM_CCR5_GC5C3_Pos)
13404#define TIM_CCR5_GC5C3 TIM_CCR5_GC5C3_Msk
13406/******************* Bit definition for TIM_CCR6 register *******************/
13407#define TIM_CCR6_CCR6_Pos (0U)
13408#define TIM_CCR6_CCR6_Msk (0xFFFFUL << TIM_CCR6_CCR6_Pos)
13409#define TIM_CCR6_CCR6 TIM_CCR6_CCR6_Msk
13411/******************* Bit definition for TIM_BDTR register *******************/
13412#define TIM_BDTR_DTG_Pos (0U)
13413#define TIM_BDTR_DTG_Msk (0xFFUL << TIM_BDTR_DTG_Pos)
13414#define TIM_BDTR_DTG TIM_BDTR_DTG_Msk
13415#define TIM_BDTR_DTG_0 (0x01UL << TIM_BDTR_DTG_Pos)
13416#define TIM_BDTR_DTG_1 (0x02UL << TIM_BDTR_DTG_Pos)
13417#define TIM_BDTR_DTG_2 (0x04UL << TIM_BDTR_DTG_Pos)
13418#define TIM_BDTR_DTG_3 (0x08UL << TIM_BDTR_DTG_Pos)
13419#define TIM_BDTR_DTG_4 (0x10UL << TIM_BDTR_DTG_Pos)
13420#define TIM_BDTR_DTG_5 (0x20UL << TIM_BDTR_DTG_Pos)
13421#define TIM_BDTR_DTG_6 (0x40UL << TIM_BDTR_DTG_Pos)
13422#define TIM_BDTR_DTG_7 (0x80UL << TIM_BDTR_DTG_Pos)
13424#define TIM_BDTR_LOCK_Pos (8U)
13425#define TIM_BDTR_LOCK_Msk (0x3UL << TIM_BDTR_LOCK_Pos)
13426#define TIM_BDTR_LOCK TIM_BDTR_LOCK_Msk
13427#define TIM_BDTR_LOCK_0 (0x1UL << TIM_BDTR_LOCK_Pos)
13428#define TIM_BDTR_LOCK_1 (0x2UL << TIM_BDTR_LOCK_Pos)
13430#define TIM_BDTR_OSSI_Pos (10U)
13431#define TIM_BDTR_OSSI_Msk (0x1UL << TIM_BDTR_OSSI_Pos)
13432#define TIM_BDTR_OSSI TIM_BDTR_OSSI_Msk
13433#define TIM_BDTR_OSSR_Pos (11U)
13434#define TIM_BDTR_OSSR_Msk (0x1UL << TIM_BDTR_OSSR_Pos)
13435#define TIM_BDTR_OSSR TIM_BDTR_OSSR_Msk
13436#define TIM_BDTR_BKE_Pos (12U)
13437#define TIM_BDTR_BKE_Msk (0x1UL << TIM_BDTR_BKE_Pos)
13438#define TIM_BDTR_BKE TIM_BDTR_BKE_Msk
13439#define TIM_BDTR_BKP_Pos (13U)
13440#define TIM_BDTR_BKP_Msk (0x1UL << TIM_BDTR_BKP_Pos)
13441#define TIM_BDTR_BKP TIM_BDTR_BKP_Msk
13442#define TIM_BDTR_AOE_Pos (14U)
13443#define TIM_BDTR_AOE_Msk (0x1UL << TIM_BDTR_AOE_Pos)
13444#define TIM_BDTR_AOE TIM_BDTR_AOE_Msk
13445#define TIM_BDTR_MOE_Pos (15U)
13446#define TIM_BDTR_MOE_Msk (0x1UL << TIM_BDTR_MOE_Pos)
13447#define TIM_BDTR_MOE TIM_BDTR_MOE_Msk
13449#define TIM_BDTR_BKF_Pos (16U)
13450#define TIM_BDTR_BKF_Msk (0xFUL << TIM_BDTR_BKF_Pos)
13451#define TIM_BDTR_BKF TIM_BDTR_BKF_Msk
13452#define TIM_BDTR_BK2F_Pos (20U)
13453#define TIM_BDTR_BK2F_Msk (0xFUL << TIM_BDTR_BK2F_Pos)
13454#define TIM_BDTR_BK2F TIM_BDTR_BK2F_Msk
13456#define TIM_BDTR_BK2E_Pos (24U)
13457#define TIM_BDTR_BK2E_Msk (0x1UL << TIM_BDTR_BK2E_Pos)
13458#define TIM_BDTR_BK2E TIM_BDTR_BK2E_Msk
13459#define TIM_BDTR_BK2P_Pos (25U)
13460#define TIM_BDTR_BK2P_Msk (0x1UL << TIM_BDTR_BK2P_Pos)
13461#define TIM_BDTR_BK2P TIM_BDTR_BK2P_Msk
13463/******************* Bit definition for TIM_DCR register ********************/
13464#define TIM_DCR_DBA_Pos (0U)
13465#define TIM_DCR_DBA_Msk (0x1FUL << TIM_DCR_DBA_Pos)
13466#define TIM_DCR_DBA TIM_DCR_DBA_Msk
13467#define TIM_DCR_DBA_0 (0x01UL << TIM_DCR_DBA_Pos)
13468#define TIM_DCR_DBA_1 (0x02UL << TIM_DCR_DBA_Pos)
13469#define TIM_DCR_DBA_2 (0x04UL << TIM_DCR_DBA_Pos)
13470#define TIM_DCR_DBA_3 (0x08UL << TIM_DCR_DBA_Pos)
13471#define TIM_DCR_DBA_4 (0x10UL << TIM_DCR_DBA_Pos)
13473#define TIM_DCR_DBL_Pos (8U)
13474#define TIM_DCR_DBL_Msk (0x1FUL << TIM_DCR_DBL_Pos)
13475#define TIM_DCR_DBL TIM_DCR_DBL_Msk
13476#define TIM_DCR_DBL_0 (0x01UL << TIM_DCR_DBL_Pos)
13477#define TIM_DCR_DBL_1 (0x02UL << TIM_DCR_DBL_Pos)
13478#define TIM_DCR_DBL_2 (0x04UL << TIM_DCR_DBL_Pos)
13479#define TIM_DCR_DBL_3 (0x08UL << TIM_DCR_DBL_Pos)
13480#define TIM_DCR_DBL_4 (0x10UL << TIM_DCR_DBL_Pos)
13482/******************* Bit definition for TIM_DMAR register *******************/
13483#define TIM_DMAR_DMAB_Pos (0U)
13484#define TIM_DMAR_DMAB_Msk (0xFFFFUL << TIM_DMAR_DMAB_Pos)
13485#define TIM_DMAR_DMAB TIM_DMAR_DMAB_Msk
13487/******************* Bit definition for TIM16_OR register *********************/
13488#define TIM16_OR_TI1_RMP_Pos (0U)
13489#define TIM16_OR_TI1_RMP_Msk (0x3UL << TIM16_OR_TI1_RMP_Pos)
13490#define TIM16_OR_TI1_RMP TIM16_OR_TI1_RMP_Msk
13491#define TIM16_OR_TI1_RMP_0 (0x1UL << TIM16_OR_TI1_RMP_Pos)
13492#define TIM16_OR_TI1_RMP_1 (0x2UL << TIM16_OR_TI1_RMP_Pos)
13494/******************* Bit definition for TIM1_OR register *********************/
13495#define TIM1_OR_ETR_RMP_Pos (0U)
13496#define TIM1_OR_ETR_RMP_Msk (0xFUL << TIM1_OR_ETR_RMP_Pos)
13497#define TIM1_OR_ETR_RMP TIM1_OR_ETR_RMP_Msk
13498#define TIM1_OR_ETR_RMP_0 (0x1UL << TIM1_OR_ETR_RMP_Pos)
13499#define TIM1_OR_ETR_RMP_1 (0x2UL << TIM1_OR_ETR_RMP_Pos)
13500#define TIM1_OR_ETR_RMP_2 (0x4UL << TIM1_OR_ETR_RMP_Pos)
13501#define TIM1_OR_ETR_RMP_3 (0x8UL << TIM1_OR_ETR_RMP_Pos)
13503/******************* Bit definition for TIM8_OR register *********************/
13504#define TIM8_OR_ETR_RMP_Pos (0U)
13505#define TIM8_OR_ETR_RMP_Msk (0xFUL << TIM8_OR_ETR_RMP_Pos)
13506#define TIM8_OR_ETR_RMP TIM8_OR_ETR_RMP_Msk
13507#define TIM8_OR_ETR_RMP_0 (0x1UL << TIM8_OR_ETR_RMP_Pos)
13508#define TIM8_OR_ETR_RMP_1 (0x2UL << TIM8_OR_ETR_RMP_Pos)
13509#define TIM8_OR_ETR_RMP_2 (0x4UL << TIM8_OR_ETR_RMP_Pos)
13510#define TIM8_OR_ETR_RMP_3 (0x8UL << TIM8_OR_ETR_RMP_Pos)
13512/******************* Bit definition for TIM20_OR register *******************/
13513#define TIM20_OR_ETR_RMP_Pos (0U)
13514#define TIM20_OR_ETR_RMP_Msk (0xFUL << TIM20_OR_ETR_RMP_Pos)
13515#define TIM20_OR_ETR_RMP TIM20_OR_ETR_RMP_Msk
13516#define TIM20_OR_ETR_RMP_0 (0x1UL << TIM20_OR_ETR_RMP_Pos)
13517#define TIM20_OR_ETR_RMP_1 (0x2UL << TIM20_OR_ETR_RMP_Pos)
13518#define TIM20_OR_ETR_RMP_2 (0x4UL << TIM20_OR_ETR_RMP_Pos)
13519#define TIM20_OR_ETR_RMP_3 (0x8UL << TIM20_OR_ETR_RMP_Pos)
13521/****************** Bit definition for TIM_CCMR3 register *******************/
13522#define TIM_CCMR3_OC5FE_Pos (2U)
13523#define TIM_CCMR3_OC5FE_Msk (0x1UL << TIM_CCMR3_OC5FE_Pos)
13524#define TIM_CCMR3_OC5FE TIM_CCMR3_OC5FE_Msk
13525#define TIM_CCMR3_OC5PE_Pos (3U)
13526#define TIM_CCMR3_OC5PE_Msk (0x1UL << TIM_CCMR3_OC5PE_Pos)
13527#define TIM_CCMR3_OC5PE TIM_CCMR3_OC5PE_Msk
13529#define TIM_CCMR3_OC5M_Pos (4U)
13530#define TIM_CCMR3_OC5M_Msk (0x1007UL << TIM_CCMR3_OC5M_Pos)
13531#define TIM_CCMR3_OC5M TIM_CCMR3_OC5M_Msk
13532#define TIM_CCMR3_OC5M_0 (0x0001UL << TIM_CCMR3_OC5M_Pos)
13533#define TIM_CCMR3_OC5M_1 (0x0002UL << TIM_CCMR3_OC5M_Pos)
13534#define TIM_CCMR3_OC5M_2 (0x0004UL << TIM_CCMR3_OC5M_Pos)
13535#define TIM_CCMR3_OC5M_3 (0x1000UL << TIM_CCMR3_OC5M_Pos)
13537#define TIM_CCMR3_OC5CE_Pos (7U)
13538#define TIM_CCMR3_OC5CE_Msk (0x1UL << TIM_CCMR3_OC5CE_Pos)
13539#define TIM_CCMR3_OC5CE TIM_CCMR3_OC5CE_Msk
13541#define TIM_CCMR3_OC6FE_Pos (10U)
13542#define TIM_CCMR3_OC6FE_Msk (0x1UL << TIM_CCMR3_OC6FE_Pos)
13543#define TIM_CCMR3_OC6FE TIM_CCMR3_OC6FE_Msk
13544#define TIM_CCMR3_OC6PE_Pos (11U)
13545#define TIM_CCMR3_OC6PE_Msk (0x1UL << TIM_CCMR3_OC6PE_Pos)
13546#define TIM_CCMR3_OC6PE TIM_CCMR3_OC6PE_Msk
13548#define TIM_CCMR3_OC6M_Pos (12U)
13549#define TIM_CCMR3_OC6M_Msk (0x1007UL << TIM_CCMR3_OC6M_Pos)
13550#define TIM_CCMR3_OC6M TIM_CCMR3_OC6M_Msk
13551#define TIM_CCMR3_OC6M_0 (0x0001UL << TIM_CCMR3_OC6M_Pos)
13552#define TIM_CCMR3_OC6M_1 (0x0002UL << TIM_CCMR3_OC6M_Pos)
13553#define TIM_CCMR3_OC6M_2 (0x0004UL << TIM_CCMR3_OC6M_Pos)
13554#define TIM_CCMR3_OC6M_3 (0x1000UL << TIM_CCMR3_OC6M_Pos)
13556#define TIM_CCMR3_OC6CE_Pos (15U)
13557#define TIM_CCMR3_OC6CE_Msk (0x1UL << TIM_CCMR3_OC6CE_Pos)
13558#define TIM_CCMR3_OC6CE TIM_CCMR3_OC6CE_Msk
13560/******************************************************************************/
13561/* */
13562/* Touch Sensing Controller (TSC) */
13563/* */
13564/******************************************************************************/
13565/******************* Bit definition for TSC_CR register *********************/
13566#define TSC_CR_TSCE_Pos (0U)
13567#define TSC_CR_TSCE_Msk (0x1UL << TSC_CR_TSCE_Pos)
13568#define TSC_CR_TSCE TSC_CR_TSCE_Msk
13569#define TSC_CR_START_Pos (1U)
13570#define TSC_CR_START_Msk (0x1UL << TSC_CR_START_Pos)
13571#define TSC_CR_START TSC_CR_START_Msk
13572#define TSC_CR_AM_Pos (2U)
13573#define TSC_CR_AM_Msk (0x1UL << TSC_CR_AM_Pos)
13574#define TSC_CR_AM TSC_CR_AM_Msk
13575#define TSC_CR_SYNCPOL_Pos (3U)
13576#define TSC_CR_SYNCPOL_Msk (0x1UL << TSC_CR_SYNCPOL_Pos)
13577#define TSC_CR_SYNCPOL TSC_CR_SYNCPOL_Msk
13578#define TSC_CR_IODEF_Pos (4U)
13579#define TSC_CR_IODEF_Msk (0x1UL << TSC_CR_IODEF_Pos)
13580#define TSC_CR_IODEF TSC_CR_IODEF_Msk
13582#define TSC_CR_MCV_Pos (5U)
13583#define TSC_CR_MCV_Msk (0x7UL << TSC_CR_MCV_Pos)
13584#define TSC_CR_MCV TSC_CR_MCV_Msk
13585#define TSC_CR_MCV_0 (0x1UL << TSC_CR_MCV_Pos)
13586#define TSC_CR_MCV_1 (0x2UL << TSC_CR_MCV_Pos)
13587#define TSC_CR_MCV_2 (0x4UL << TSC_CR_MCV_Pos)
13589#define TSC_CR_PGPSC_Pos (12U)
13590#define TSC_CR_PGPSC_Msk (0x7UL << TSC_CR_PGPSC_Pos)
13591#define TSC_CR_PGPSC TSC_CR_PGPSC_Msk
13592#define TSC_CR_PGPSC_0 (0x1UL << TSC_CR_PGPSC_Pos)
13593#define TSC_CR_PGPSC_1 (0x2UL << TSC_CR_PGPSC_Pos)
13594#define TSC_CR_PGPSC_2 (0x4UL << TSC_CR_PGPSC_Pos)
13596#define TSC_CR_SSPSC_Pos (15U)
13597#define TSC_CR_SSPSC_Msk (0x1UL << TSC_CR_SSPSC_Pos)
13598#define TSC_CR_SSPSC TSC_CR_SSPSC_Msk
13599#define TSC_CR_SSE_Pos (16U)
13600#define TSC_CR_SSE_Msk (0x1UL << TSC_CR_SSE_Pos)
13601#define TSC_CR_SSE TSC_CR_SSE_Msk
13603#define TSC_CR_SSD_Pos (17U)
13604#define TSC_CR_SSD_Msk (0x7FUL << TSC_CR_SSD_Pos)
13605#define TSC_CR_SSD TSC_CR_SSD_Msk
13606#define TSC_CR_SSD_0 (0x01UL << TSC_CR_SSD_Pos)
13607#define TSC_CR_SSD_1 (0x02UL << TSC_CR_SSD_Pos)
13608#define TSC_CR_SSD_2 (0x04UL << TSC_CR_SSD_Pos)
13609#define TSC_CR_SSD_3 (0x08UL << TSC_CR_SSD_Pos)
13610#define TSC_CR_SSD_4 (0x10UL << TSC_CR_SSD_Pos)
13611#define TSC_CR_SSD_5 (0x20UL << TSC_CR_SSD_Pos)
13612#define TSC_CR_SSD_6 (0x40UL << TSC_CR_SSD_Pos)
13614#define TSC_CR_CTPL_Pos (24U)
13615#define TSC_CR_CTPL_Msk (0xFUL << TSC_CR_CTPL_Pos)
13616#define TSC_CR_CTPL TSC_CR_CTPL_Msk
13617#define TSC_CR_CTPL_0 (0x1UL << TSC_CR_CTPL_Pos)
13618#define TSC_CR_CTPL_1 (0x2UL << TSC_CR_CTPL_Pos)
13619#define TSC_CR_CTPL_2 (0x4UL << TSC_CR_CTPL_Pos)
13620#define TSC_CR_CTPL_3 (0x8UL << TSC_CR_CTPL_Pos)
13622#define TSC_CR_CTPH_Pos (28U)
13623#define TSC_CR_CTPH_Msk (0xFUL << TSC_CR_CTPH_Pos)
13624#define TSC_CR_CTPH TSC_CR_CTPH_Msk
13625#define TSC_CR_CTPH_0 (0x1UL << TSC_CR_CTPH_Pos)
13626#define TSC_CR_CTPH_1 (0x2UL << TSC_CR_CTPH_Pos)
13627#define TSC_CR_CTPH_2 (0x4UL << TSC_CR_CTPH_Pos)
13628#define TSC_CR_CTPH_3 (0x8UL << TSC_CR_CTPH_Pos)
13630/******************* Bit definition for TSC_IER register ********************/
13631#define TSC_IER_EOAIE_Pos (0U)
13632#define TSC_IER_EOAIE_Msk (0x1UL << TSC_IER_EOAIE_Pos)
13633#define TSC_IER_EOAIE TSC_IER_EOAIE_Msk
13634#define TSC_IER_MCEIE_Pos (1U)
13635#define TSC_IER_MCEIE_Msk (0x1UL << TSC_IER_MCEIE_Pos)
13636#define TSC_IER_MCEIE TSC_IER_MCEIE_Msk
13638/******************* Bit definition for TSC_ICR register ********************/
13639#define TSC_ICR_EOAIC_Pos (0U)
13640#define TSC_ICR_EOAIC_Msk (0x1UL << TSC_ICR_EOAIC_Pos)
13641#define TSC_ICR_EOAIC TSC_ICR_EOAIC_Msk
13642#define TSC_ICR_MCEIC_Pos (1U)
13643#define TSC_ICR_MCEIC_Msk (0x1UL << TSC_ICR_MCEIC_Pos)
13644#define TSC_ICR_MCEIC TSC_ICR_MCEIC_Msk
13646/******************* Bit definition for TSC_ISR register ********************/
13647#define TSC_ISR_EOAF_Pos (0U)
13648#define TSC_ISR_EOAF_Msk (0x1UL << TSC_ISR_EOAF_Pos)
13649#define TSC_ISR_EOAF TSC_ISR_EOAF_Msk
13650#define TSC_ISR_MCEF_Pos (1U)
13651#define TSC_ISR_MCEF_Msk (0x1UL << TSC_ISR_MCEF_Pos)
13652#define TSC_ISR_MCEF TSC_ISR_MCEF_Msk
13654/******************* Bit definition for TSC_IOHCR register ******************/
13655#define TSC_IOHCR_G1_IO1_Pos (0U)
13656#define TSC_IOHCR_G1_IO1_Msk (0x1UL << TSC_IOHCR_G1_IO1_Pos)
13657#define TSC_IOHCR_G1_IO1 TSC_IOHCR_G1_IO1_Msk
13658#define TSC_IOHCR_G1_IO2_Pos (1U)
13659#define TSC_IOHCR_G1_IO2_Msk (0x1UL << TSC_IOHCR_G1_IO2_Pos)
13660#define TSC_IOHCR_G1_IO2 TSC_IOHCR_G1_IO2_Msk
13661#define TSC_IOHCR_G1_IO3_Pos (2U)
13662#define TSC_IOHCR_G1_IO3_Msk (0x1UL << TSC_IOHCR_G1_IO3_Pos)
13663#define TSC_IOHCR_G1_IO3 TSC_IOHCR_G1_IO3_Msk
13664#define TSC_IOHCR_G1_IO4_Pos (3U)
13665#define TSC_IOHCR_G1_IO4_Msk (0x1UL << TSC_IOHCR_G1_IO4_Pos)
13666#define TSC_IOHCR_G1_IO4 TSC_IOHCR_G1_IO4_Msk
13667#define TSC_IOHCR_G2_IO1_Pos (4U)
13668#define TSC_IOHCR_G2_IO1_Msk (0x1UL << TSC_IOHCR_G2_IO1_Pos)
13669#define TSC_IOHCR_G2_IO1 TSC_IOHCR_G2_IO1_Msk
13670#define TSC_IOHCR_G2_IO2_Pos (5U)
13671#define TSC_IOHCR_G2_IO2_Msk (0x1UL << TSC_IOHCR_G2_IO2_Pos)
13672#define TSC_IOHCR_G2_IO2 TSC_IOHCR_G2_IO2_Msk
13673#define TSC_IOHCR_G2_IO3_Pos (6U)
13674#define TSC_IOHCR_G2_IO3_Msk (0x1UL << TSC_IOHCR_G2_IO3_Pos)
13675#define TSC_IOHCR_G2_IO3 TSC_IOHCR_G2_IO3_Msk
13676#define TSC_IOHCR_G2_IO4_Pos (7U)
13677#define TSC_IOHCR_G2_IO4_Msk (0x1UL << TSC_IOHCR_G2_IO4_Pos)
13678#define TSC_IOHCR_G2_IO4 TSC_IOHCR_G2_IO4_Msk
13679#define TSC_IOHCR_G3_IO1_Pos (8U)
13680#define TSC_IOHCR_G3_IO1_Msk (0x1UL << TSC_IOHCR_G3_IO1_Pos)
13681#define TSC_IOHCR_G3_IO1 TSC_IOHCR_G3_IO1_Msk
13682#define TSC_IOHCR_G3_IO2_Pos (9U)
13683#define TSC_IOHCR_G3_IO2_Msk (0x1UL << TSC_IOHCR_G3_IO2_Pos)
13684#define TSC_IOHCR_G3_IO2 TSC_IOHCR_G3_IO2_Msk
13685#define TSC_IOHCR_G3_IO3_Pos (10U)
13686#define TSC_IOHCR_G3_IO3_Msk (0x1UL << TSC_IOHCR_G3_IO3_Pos)
13687#define TSC_IOHCR_G3_IO3 TSC_IOHCR_G3_IO3_Msk
13688#define TSC_IOHCR_G3_IO4_Pos (11U)
13689#define TSC_IOHCR_G3_IO4_Msk (0x1UL << TSC_IOHCR_G3_IO4_Pos)
13690#define TSC_IOHCR_G3_IO4 TSC_IOHCR_G3_IO4_Msk
13691#define TSC_IOHCR_G4_IO1_Pos (12U)
13692#define TSC_IOHCR_G4_IO1_Msk (0x1UL << TSC_IOHCR_G4_IO1_Pos)
13693#define TSC_IOHCR_G4_IO1 TSC_IOHCR_G4_IO1_Msk
13694#define TSC_IOHCR_G4_IO2_Pos (13U)
13695#define TSC_IOHCR_G4_IO2_Msk (0x1UL << TSC_IOHCR_G4_IO2_Pos)
13696#define TSC_IOHCR_G4_IO2 TSC_IOHCR_G4_IO2_Msk
13697#define TSC_IOHCR_G4_IO3_Pos (14U)
13698#define TSC_IOHCR_G4_IO3_Msk (0x1UL << TSC_IOHCR_G4_IO3_Pos)
13699#define TSC_IOHCR_G4_IO3 TSC_IOHCR_G4_IO3_Msk
13700#define TSC_IOHCR_G4_IO4_Pos (15U)
13701#define TSC_IOHCR_G4_IO4_Msk (0x1UL << TSC_IOHCR_G4_IO4_Pos)
13702#define TSC_IOHCR_G4_IO4 TSC_IOHCR_G4_IO4_Msk
13703#define TSC_IOHCR_G5_IO1_Pos (16U)
13704#define TSC_IOHCR_G5_IO1_Msk (0x1UL << TSC_IOHCR_G5_IO1_Pos)
13705#define TSC_IOHCR_G5_IO1 TSC_IOHCR_G5_IO1_Msk
13706#define TSC_IOHCR_G5_IO2_Pos (17U)
13707#define TSC_IOHCR_G5_IO2_Msk (0x1UL << TSC_IOHCR_G5_IO2_Pos)
13708#define TSC_IOHCR_G5_IO2 TSC_IOHCR_G5_IO2_Msk
13709#define TSC_IOHCR_G5_IO3_Pos (18U)
13710#define TSC_IOHCR_G5_IO3_Msk (0x1UL << TSC_IOHCR_G5_IO3_Pos)
13711#define TSC_IOHCR_G5_IO3 TSC_IOHCR_G5_IO3_Msk
13712#define TSC_IOHCR_G5_IO4_Pos (19U)
13713#define TSC_IOHCR_G5_IO4_Msk (0x1UL << TSC_IOHCR_G5_IO4_Pos)
13714#define TSC_IOHCR_G5_IO4 TSC_IOHCR_G5_IO4_Msk
13715#define TSC_IOHCR_G6_IO1_Pos (20U)
13716#define TSC_IOHCR_G6_IO1_Msk (0x1UL << TSC_IOHCR_G6_IO1_Pos)
13717#define TSC_IOHCR_G6_IO1 TSC_IOHCR_G6_IO1_Msk
13718#define TSC_IOHCR_G6_IO2_Pos (21U)
13719#define TSC_IOHCR_G6_IO2_Msk (0x1UL << TSC_IOHCR_G6_IO2_Pos)
13720#define TSC_IOHCR_G6_IO2 TSC_IOHCR_G6_IO2_Msk
13721#define TSC_IOHCR_G6_IO3_Pos (22U)
13722#define TSC_IOHCR_G6_IO3_Msk (0x1UL << TSC_IOHCR_G6_IO3_Pos)
13723#define TSC_IOHCR_G6_IO3 TSC_IOHCR_G6_IO3_Msk
13724#define TSC_IOHCR_G6_IO4_Pos (23U)
13725#define TSC_IOHCR_G6_IO4_Msk (0x1UL << TSC_IOHCR_G6_IO4_Pos)
13726#define TSC_IOHCR_G6_IO4 TSC_IOHCR_G6_IO4_Msk
13727#define TSC_IOHCR_G7_IO1_Pos (24U)
13728#define TSC_IOHCR_G7_IO1_Msk (0x1UL << TSC_IOHCR_G7_IO1_Pos)
13729#define TSC_IOHCR_G7_IO1 TSC_IOHCR_G7_IO1_Msk
13730#define TSC_IOHCR_G7_IO2_Pos (25U)
13731#define TSC_IOHCR_G7_IO2_Msk (0x1UL << TSC_IOHCR_G7_IO2_Pos)
13732#define TSC_IOHCR_G7_IO2 TSC_IOHCR_G7_IO2_Msk
13733#define TSC_IOHCR_G7_IO3_Pos (26U)
13734#define TSC_IOHCR_G7_IO3_Msk (0x1UL << TSC_IOHCR_G7_IO3_Pos)
13735#define TSC_IOHCR_G7_IO3 TSC_IOHCR_G7_IO3_Msk
13736#define TSC_IOHCR_G7_IO4_Pos (27U)
13737#define TSC_IOHCR_G7_IO4_Msk (0x1UL << TSC_IOHCR_G7_IO4_Pos)
13738#define TSC_IOHCR_G7_IO4 TSC_IOHCR_G7_IO4_Msk
13739#define TSC_IOHCR_G8_IO1_Pos (28U)
13740#define TSC_IOHCR_G8_IO1_Msk (0x1UL << TSC_IOHCR_G8_IO1_Pos)
13741#define TSC_IOHCR_G8_IO1 TSC_IOHCR_G8_IO1_Msk
13742#define TSC_IOHCR_G8_IO2_Pos (29U)
13743#define TSC_IOHCR_G8_IO2_Msk (0x1UL << TSC_IOHCR_G8_IO2_Pos)
13744#define TSC_IOHCR_G8_IO2 TSC_IOHCR_G8_IO2_Msk
13745#define TSC_IOHCR_G8_IO3_Pos (30U)
13746#define TSC_IOHCR_G8_IO3_Msk (0x1UL << TSC_IOHCR_G8_IO3_Pos)
13747#define TSC_IOHCR_G8_IO3 TSC_IOHCR_G8_IO3_Msk
13748#define TSC_IOHCR_G8_IO4_Pos (31U)
13749#define TSC_IOHCR_G8_IO4_Msk (0x1UL << TSC_IOHCR_G8_IO4_Pos)
13750#define TSC_IOHCR_G8_IO4 TSC_IOHCR_G8_IO4_Msk
13752/******************* Bit definition for TSC_IOASCR register *****************/
13753#define TSC_IOASCR_G1_IO1_Pos (0U)
13754#define TSC_IOASCR_G1_IO1_Msk (0x1UL << TSC_IOASCR_G1_IO1_Pos)
13755#define TSC_IOASCR_G1_IO1 TSC_IOASCR_G1_IO1_Msk
13756#define TSC_IOASCR_G1_IO2_Pos (1U)
13757#define TSC_IOASCR_G1_IO2_Msk (0x1UL << TSC_IOASCR_G1_IO2_Pos)
13758#define TSC_IOASCR_G1_IO2 TSC_IOASCR_G1_IO2_Msk
13759#define TSC_IOASCR_G1_IO3_Pos (2U)
13760#define TSC_IOASCR_G1_IO3_Msk (0x1UL << TSC_IOASCR_G1_IO3_Pos)
13761#define TSC_IOASCR_G1_IO3 TSC_IOASCR_G1_IO3_Msk
13762#define TSC_IOASCR_G1_IO4_Pos (3U)
13763#define TSC_IOASCR_G1_IO4_Msk (0x1UL << TSC_IOASCR_G1_IO4_Pos)
13764#define TSC_IOASCR_G1_IO4 TSC_IOASCR_G1_IO4_Msk
13765#define TSC_IOASCR_G2_IO1_Pos (4U)
13766#define TSC_IOASCR_G2_IO1_Msk (0x1UL << TSC_IOASCR_G2_IO1_Pos)
13767#define TSC_IOASCR_G2_IO1 TSC_IOASCR_G2_IO1_Msk
13768#define TSC_IOASCR_G2_IO2_Pos (5U)
13769#define TSC_IOASCR_G2_IO2_Msk (0x1UL << TSC_IOASCR_G2_IO2_Pos)
13770#define TSC_IOASCR_G2_IO2 TSC_IOASCR_G2_IO2_Msk
13771#define TSC_IOASCR_G2_IO3_Pos (6U)
13772#define TSC_IOASCR_G2_IO3_Msk (0x1UL << TSC_IOASCR_G2_IO3_Pos)
13773#define TSC_IOASCR_G2_IO3 TSC_IOASCR_G2_IO3_Msk
13774#define TSC_IOASCR_G2_IO4_Pos (7U)
13775#define TSC_IOASCR_G2_IO4_Msk (0x1UL << TSC_IOASCR_G2_IO4_Pos)
13776#define TSC_IOASCR_G2_IO4 TSC_IOASCR_G2_IO4_Msk
13777#define TSC_IOASCR_G3_IO1_Pos (8U)
13778#define TSC_IOASCR_G3_IO1_Msk (0x1UL << TSC_IOASCR_G3_IO1_Pos)
13779#define TSC_IOASCR_G3_IO1 TSC_IOASCR_G3_IO1_Msk
13780#define TSC_IOASCR_G3_IO2_Pos (9U)
13781#define TSC_IOASCR_G3_IO2_Msk (0x1UL << TSC_IOASCR_G3_IO2_Pos)
13782#define TSC_IOASCR_G3_IO2 TSC_IOASCR_G3_IO2_Msk
13783#define TSC_IOASCR_G3_IO3_Pos (10U)
13784#define TSC_IOASCR_G3_IO3_Msk (0x1UL << TSC_IOASCR_G3_IO3_Pos)
13785#define TSC_IOASCR_G3_IO3 TSC_IOASCR_G3_IO3_Msk
13786#define TSC_IOASCR_G3_IO4_Pos (11U)
13787#define TSC_IOASCR_G3_IO4_Msk (0x1UL << TSC_IOASCR_G3_IO4_Pos)
13788#define TSC_IOASCR_G3_IO4 TSC_IOASCR_G3_IO4_Msk
13789#define TSC_IOASCR_G4_IO1_Pos (12U)
13790#define TSC_IOASCR_G4_IO1_Msk (0x1UL << TSC_IOASCR_G4_IO1_Pos)
13791#define TSC_IOASCR_G4_IO1 TSC_IOASCR_G4_IO1_Msk
13792#define TSC_IOASCR_G4_IO2_Pos (13U)
13793#define TSC_IOASCR_G4_IO2_Msk (0x1UL << TSC_IOASCR_G4_IO2_Pos)
13794#define TSC_IOASCR_G4_IO2 TSC_IOASCR_G4_IO2_Msk
13795#define TSC_IOASCR_G4_IO3_Pos (14U)
13796#define TSC_IOASCR_G4_IO3_Msk (0x1UL << TSC_IOASCR_G4_IO3_Pos)
13797#define TSC_IOASCR_G4_IO3 TSC_IOASCR_G4_IO3_Msk
13798#define TSC_IOASCR_G4_IO4_Pos (15U)
13799#define TSC_IOASCR_G4_IO4_Msk (0x1UL << TSC_IOASCR_G4_IO4_Pos)
13800#define TSC_IOASCR_G4_IO4 TSC_IOASCR_G4_IO4_Msk
13801#define TSC_IOASCR_G5_IO1_Pos (16U)
13802#define TSC_IOASCR_G5_IO1_Msk (0x1UL << TSC_IOASCR_G5_IO1_Pos)
13803#define TSC_IOASCR_G5_IO1 TSC_IOASCR_G5_IO1_Msk
13804#define TSC_IOASCR_G5_IO2_Pos (17U)
13805#define TSC_IOASCR_G5_IO2_Msk (0x1UL << TSC_IOASCR_G5_IO2_Pos)
13806#define TSC_IOASCR_G5_IO2 TSC_IOASCR_G5_IO2_Msk
13807#define TSC_IOASCR_G5_IO3_Pos (18U)
13808#define TSC_IOASCR_G5_IO3_Msk (0x1UL << TSC_IOASCR_G5_IO3_Pos)
13809#define TSC_IOASCR_G5_IO3 TSC_IOASCR_G5_IO3_Msk
13810#define TSC_IOASCR_G5_IO4_Pos (19U)
13811#define TSC_IOASCR_G5_IO4_Msk (0x1UL << TSC_IOASCR_G5_IO4_Pos)
13812#define TSC_IOASCR_G5_IO4 TSC_IOASCR_G5_IO4_Msk
13813#define TSC_IOASCR_G6_IO1_Pos (20U)
13814#define TSC_IOASCR_G6_IO1_Msk (0x1UL << TSC_IOASCR_G6_IO1_Pos)
13815#define TSC_IOASCR_G6_IO1 TSC_IOASCR_G6_IO1_Msk
13816#define TSC_IOASCR_G6_IO2_Pos (21U)
13817#define TSC_IOASCR_G6_IO2_Msk (0x1UL << TSC_IOASCR_G6_IO2_Pos)
13818#define TSC_IOASCR_G6_IO2 TSC_IOASCR_G6_IO2_Msk
13819#define TSC_IOASCR_G6_IO3_Pos (22U)
13820#define TSC_IOASCR_G6_IO3_Msk (0x1UL << TSC_IOASCR_G6_IO3_Pos)
13821#define TSC_IOASCR_G6_IO3 TSC_IOASCR_G6_IO3_Msk
13822#define TSC_IOASCR_G6_IO4_Pos (23U)
13823#define TSC_IOASCR_G6_IO4_Msk (0x1UL << TSC_IOASCR_G6_IO4_Pos)
13824#define TSC_IOASCR_G6_IO4 TSC_IOASCR_G6_IO4_Msk
13825#define TSC_IOASCR_G7_IO1_Pos (24U)
13826#define TSC_IOASCR_G7_IO1_Msk (0x1UL << TSC_IOASCR_G7_IO1_Pos)
13827#define TSC_IOASCR_G7_IO1 TSC_IOASCR_G7_IO1_Msk
13828#define TSC_IOASCR_G7_IO2_Pos (25U)
13829#define TSC_IOASCR_G7_IO2_Msk (0x1UL << TSC_IOASCR_G7_IO2_Pos)
13830#define TSC_IOASCR_G7_IO2 TSC_IOASCR_G7_IO2_Msk
13831#define TSC_IOASCR_G7_IO3_Pos (26U)
13832#define TSC_IOASCR_G7_IO3_Msk (0x1UL << TSC_IOASCR_G7_IO3_Pos)
13833#define TSC_IOASCR_G7_IO3 TSC_IOASCR_G7_IO3_Msk
13834#define TSC_IOASCR_G7_IO4_Pos (27U)
13835#define TSC_IOASCR_G7_IO4_Msk (0x1UL << TSC_IOASCR_G7_IO4_Pos)
13836#define TSC_IOASCR_G7_IO4 TSC_IOASCR_G7_IO4_Msk
13837#define TSC_IOASCR_G8_IO1_Pos (28U)
13838#define TSC_IOASCR_G8_IO1_Msk (0x1UL << TSC_IOASCR_G8_IO1_Pos)
13839#define TSC_IOASCR_G8_IO1 TSC_IOASCR_G8_IO1_Msk
13840#define TSC_IOASCR_G8_IO2_Pos (29U)
13841#define TSC_IOASCR_G8_IO2_Msk (0x1UL << TSC_IOASCR_G8_IO2_Pos)
13842#define TSC_IOASCR_G8_IO2 TSC_IOASCR_G8_IO2_Msk
13843#define TSC_IOASCR_G8_IO3_Pos (30U)
13844#define TSC_IOASCR_G8_IO3_Msk (0x1UL << TSC_IOASCR_G8_IO3_Pos)
13845#define TSC_IOASCR_G8_IO3 TSC_IOASCR_G8_IO3_Msk
13846#define TSC_IOASCR_G8_IO4_Pos (31U)
13847#define TSC_IOASCR_G8_IO4_Msk (0x1UL << TSC_IOASCR_G8_IO4_Pos)
13848#define TSC_IOASCR_G8_IO4 TSC_IOASCR_G8_IO4_Msk
13850/******************* Bit definition for TSC_IOSCR register ******************/
13851#define TSC_IOSCR_G1_IO1_Pos (0U)
13852#define TSC_IOSCR_G1_IO1_Msk (0x1UL << TSC_IOSCR_G1_IO1_Pos)
13853#define TSC_IOSCR_G1_IO1 TSC_IOSCR_G1_IO1_Msk
13854#define TSC_IOSCR_G1_IO2_Pos (1U)
13855#define TSC_IOSCR_G1_IO2_Msk (0x1UL << TSC_IOSCR_G1_IO2_Pos)
13856#define TSC_IOSCR_G1_IO2 TSC_IOSCR_G1_IO2_Msk
13857#define TSC_IOSCR_G1_IO3_Pos (2U)
13858#define TSC_IOSCR_G1_IO3_Msk (0x1UL << TSC_IOSCR_G1_IO3_Pos)
13859#define TSC_IOSCR_G1_IO3 TSC_IOSCR_G1_IO3_Msk
13860#define TSC_IOSCR_G1_IO4_Pos (3U)
13861#define TSC_IOSCR_G1_IO4_Msk (0x1UL << TSC_IOSCR_G1_IO4_Pos)
13862#define TSC_IOSCR_G1_IO4 TSC_IOSCR_G1_IO4_Msk
13863#define TSC_IOSCR_G2_IO1_Pos (4U)
13864#define TSC_IOSCR_G2_IO1_Msk (0x1UL << TSC_IOSCR_G2_IO1_Pos)
13865#define TSC_IOSCR_G2_IO1 TSC_IOSCR_G2_IO1_Msk
13866#define TSC_IOSCR_G2_IO2_Pos (5U)
13867#define TSC_IOSCR_G2_IO2_Msk (0x1UL << TSC_IOSCR_G2_IO2_Pos)
13868#define TSC_IOSCR_G2_IO2 TSC_IOSCR_G2_IO2_Msk
13869#define TSC_IOSCR_G2_IO3_Pos (6U)
13870#define TSC_IOSCR_G2_IO3_Msk (0x1UL << TSC_IOSCR_G2_IO3_Pos)
13871#define TSC_IOSCR_G2_IO3 TSC_IOSCR_G2_IO3_Msk
13872#define TSC_IOSCR_G2_IO4_Pos (7U)
13873#define TSC_IOSCR_G2_IO4_Msk (0x1UL << TSC_IOSCR_G2_IO4_Pos)
13874#define TSC_IOSCR_G2_IO4 TSC_IOSCR_G2_IO4_Msk
13875#define TSC_IOSCR_G3_IO1_Pos (8U)
13876#define TSC_IOSCR_G3_IO1_Msk (0x1UL << TSC_IOSCR_G3_IO1_Pos)
13877#define TSC_IOSCR_G3_IO1 TSC_IOSCR_G3_IO1_Msk
13878#define TSC_IOSCR_G3_IO2_Pos (9U)
13879#define TSC_IOSCR_G3_IO2_Msk (0x1UL << TSC_IOSCR_G3_IO2_Pos)
13880#define TSC_IOSCR_G3_IO2 TSC_IOSCR_G3_IO2_Msk
13881#define TSC_IOSCR_G3_IO3_Pos (10U)
13882#define TSC_IOSCR_G3_IO3_Msk (0x1UL << TSC_IOSCR_G3_IO3_Pos)
13883#define TSC_IOSCR_G3_IO3 TSC_IOSCR_G3_IO3_Msk
13884#define TSC_IOSCR_G3_IO4_Pos (11U)
13885#define TSC_IOSCR_G3_IO4_Msk (0x1UL << TSC_IOSCR_G3_IO4_Pos)
13886#define TSC_IOSCR_G3_IO4 TSC_IOSCR_G3_IO4_Msk
13887#define TSC_IOSCR_G4_IO1_Pos (12U)
13888#define TSC_IOSCR_G4_IO1_Msk (0x1UL << TSC_IOSCR_G4_IO1_Pos)
13889#define TSC_IOSCR_G4_IO1 TSC_IOSCR_G4_IO1_Msk
13890#define TSC_IOSCR_G4_IO2_Pos (13U)
13891#define TSC_IOSCR_G4_IO2_Msk (0x1UL << TSC_IOSCR_G4_IO2_Pos)
13892#define TSC_IOSCR_G4_IO2 TSC_IOSCR_G4_IO2_Msk
13893#define TSC_IOSCR_G4_IO3_Pos (14U)
13894#define TSC_IOSCR_G4_IO3_Msk (0x1UL << TSC_IOSCR_G4_IO3_Pos)
13895#define TSC_IOSCR_G4_IO3 TSC_IOSCR_G4_IO3_Msk
13896#define TSC_IOSCR_G4_IO4_Pos (15U)
13897#define TSC_IOSCR_G4_IO4_Msk (0x1UL << TSC_IOSCR_G4_IO4_Pos)
13898#define TSC_IOSCR_G4_IO4 TSC_IOSCR_G4_IO4_Msk
13899#define TSC_IOSCR_G5_IO1_Pos (16U)
13900#define TSC_IOSCR_G5_IO1_Msk (0x1UL << TSC_IOSCR_G5_IO1_Pos)
13901#define TSC_IOSCR_G5_IO1 TSC_IOSCR_G5_IO1_Msk
13902#define TSC_IOSCR_G5_IO2_Pos (17U)
13903#define TSC_IOSCR_G5_IO2_Msk (0x1UL << TSC_IOSCR_G5_IO2_Pos)
13904#define TSC_IOSCR_G5_IO2 TSC_IOSCR_G5_IO2_Msk
13905#define TSC_IOSCR_G5_IO3_Pos (18U)
13906#define TSC_IOSCR_G5_IO3_Msk (0x1UL << TSC_IOSCR_G5_IO3_Pos)
13907#define TSC_IOSCR_G5_IO3 TSC_IOSCR_G5_IO3_Msk
13908#define TSC_IOSCR_G5_IO4_Pos (19U)
13909#define TSC_IOSCR_G5_IO4_Msk (0x1UL << TSC_IOSCR_G5_IO4_Pos)
13910#define TSC_IOSCR_G5_IO4 TSC_IOSCR_G5_IO4_Msk
13911#define TSC_IOSCR_G6_IO1_Pos (20U)
13912#define TSC_IOSCR_G6_IO1_Msk (0x1UL << TSC_IOSCR_G6_IO1_Pos)
13913#define TSC_IOSCR_G6_IO1 TSC_IOSCR_G6_IO1_Msk
13914#define TSC_IOSCR_G6_IO2_Pos (21U)
13915#define TSC_IOSCR_G6_IO2_Msk (0x1UL << TSC_IOSCR_G6_IO2_Pos)
13916#define TSC_IOSCR_G6_IO2 TSC_IOSCR_G6_IO2_Msk
13917#define TSC_IOSCR_G6_IO3_Pos (22U)
13918#define TSC_IOSCR_G6_IO3_Msk (0x1UL << TSC_IOSCR_G6_IO3_Pos)
13919#define TSC_IOSCR_G6_IO3 TSC_IOSCR_G6_IO3_Msk
13920#define TSC_IOSCR_G6_IO4_Pos (23U)
13921#define TSC_IOSCR_G6_IO4_Msk (0x1UL << TSC_IOSCR_G6_IO4_Pos)
13922#define TSC_IOSCR_G6_IO4 TSC_IOSCR_G6_IO4_Msk
13923#define TSC_IOSCR_G7_IO1_Pos (24U)
13924#define TSC_IOSCR_G7_IO1_Msk (0x1UL << TSC_IOSCR_G7_IO1_Pos)
13925#define TSC_IOSCR_G7_IO1 TSC_IOSCR_G7_IO1_Msk
13926#define TSC_IOSCR_G7_IO2_Pos (25U)
13927#define TSC_IOSCR_G7_IO2_Msk (0x1UL << TSC_IOSCR_G7_IO2_Pos)
13928#define TSC_IOSCR_G7_IO2 TSC_IOSCR_G7_IO2_Msk
13929#define TSC_IOSCR_G7_IO3_Pos (26U)
13930#define TSC_IOSCR_G7_IO3_Msk (0x1UL << TSC_IOSCR_G7_IO3_Pos)
13931#define TSC_IOSCR_G7_IO3 TSC_IOSCR_G7_IO3_Msk
13932#define TSC_IOSCR_G7_IO4_Pos (27U)
13933#define TSC_IOSCR_G7_IO4_Msk (0x1UL << TSC_IOSCR_G7_IO4_Pos)
13934#define TSC_IOSCR_G7_IO4 TSC_IOSCR_G7_IO4_Msk
13935#define TSC_IOSCR_G8_IO1_Pos (28U)
13936#define TSC_IOSCR_G8_IO1_Msk (0x1UL << TSC_IOSCR_G8_IO1_Pos)
13937#define TSC_IOSCR_G8_IO1 TSC_IOSCR_G8_IO1_Msk
13938#define TSC_IOSCR_G8_IO2_Pos (29U)
13939#define TSC_IOSCR_G8_IO2_Msk (0x1UL << TSC_IOSCR_G8_IO2_Pos)
13940#define TSC_IOSCR_G8_IO2 TSC_IOSCR_G8_IO2_Msk
13941#define TSC_IOSCR_G8_IO3_Pos (30U)
13942#define TSC_IOSCR_G8_IO3_Msk (0x1UL << TSC_IOSCR_G8_IO3_Pos)
13943#define TSC_IOSCR_G8_IO3 TSC_IOSCR_G8_IO3_Msk
13944#define TSC_IOSCR_G8_IO4_Pos (31U)
13945#define TSC_IOSCR_G8_IO4_Msk (0x1UL << TSC_IOSCR_G8_IO4_Pos)
13946#define TSC_IOSCR_G8_IO4 TSC_IOSCR_G8_IO4_Msk
13948/******************* Bit definition for TSC_IOCCR register ******************/
13949#define TSC_IOCCR_G1_IO1_Pos (0U)
13950#define TSC_IOCCR_G1_IO1_Msk (0x1UL << TSC_IOCCR_G1_IO1_Pos)
13951#define TSC_IOCCR_G1_IO1 TSC_IOCCR_G1_IO1_Msk
13952#define TSC_IOCCR_G1_IO2_Pos (1U)
13953#define TSC_IOCCR_G1_IO2_Msk (0x1UL << TSC_IOCCR_G1_IO2_Pos)
13954#define TSC_IOCCR_G1_IO2 TSC_IOCCR_G1_IO2_Msk
13955#define TSC_IOCCR_G1_IO3_Pos (2U)
13956#define TSC_IOCCR_G1_IO3_Msk (0x1UL << TSC_IOCCR_G1_IO3_Pos)
13957#define TSC_IOCCR_G1_IO3 TSC_IOCCR_G1_IO3_Msk
13958#define TSC_IOCCR_G1_IO4_Pos (3U)
13959#define TSC_IOCCR_G1_IO4_Msk (0x1UL << TSC_IOCCR_G1_IO4_Pos)
13960#define TSC_IOCCR_G1_IO4 TSC_IOCCR_G1_IO4_Msk
13961#define TSC_IOCCR_G2_IO1_Pos (4U)
13962#define TSC_IOCCR_G2_IO1_Msk (0x1UL << TSC_IOCCR_G2_IO1_Pos)
13963#define TSC_IOCCR_G2_IO1 TSC_IOCCR_G2_IO1_Msk
13964#define TSC_IOCCR_G2_IO2_Pos (5U)
13965#define TSC_IOCCR_G2_IO2_Msk (0x1UL << TSC_IOCCR_G2_IO2_Pos)
13966#define TSC_IOCCR_G2_IO2 TSC_IOCCR_G2_IO2_Msk
13967#define TSC_IOCCR_G2_IO3_Pos (6U)
13968#define TSC_IOCCR_G2_IO3_Msk (0x1UL << TSC_IOCCR_G2_IO3_Pos)
13969#define TSC_IOCCR_G2_IO3 TSC_IOCCR_G2_IO3_Msk
13970#define TSC_IOCCR_G2_IO4_Pos (7U)
13971#define TSC_IOCCR_G2_IO4_Msk (0x1UL << TSC_IOCCR_G2_IO4_Pos)
13972#define TSC_IOCCR_G2_IO4 TSC_IOCCR_G2_IO4_Msk
13973#define TSC_IOCCR_G3_IO1_Pos (8U)
13974#define TSC_IOCCR_G3_IO1_Msk (0x1UL << TSC_IOCCR_G3_IO1_Pos)
13975#define TSC_IOCCR_G3_IO1 TSC_IOCCR_G3_IO1_Msk
13976#define TSC_IOCCR_G3_IO2_Pos (9U)
13977#define TSC_IOCCR_G3_IO2_Msk (0x1UL << TSC_IOCCR_G3_IO2_Pos)
13978#define TSC_IOCCR_G3_IO2 TSC_IOCCR_G3_IO2_Msk
13979#define TSC_IOCCR_G3_IO3_Pos (10U)
13980#define TSC_IOCCR_G3_IO3_Msk (0x1UL << TSC_IOCCR_G3_IO3_Pos)
13981#define TSC_IOCCR_G3_IO3 TSC_IOCCR_G3_IO3_Msk
13982#define TSC_IOCCR_G3_IO4_Pos (11U)
13983#define TSC_IOCCR_G3_IO4_Msk (0x1UL << TSC_IOCCR_G3_IO4_Pos)
13984#define TSC_IOCCR_G3_IO4 TSC_IOCCR_G3_IO4_Msk
13985#define TSC_IOCCR_G4_IO1_Pos (12U)
13986#define TSC_IOCCR_G4_IO1_Msk (0x1UL << TSC_IOCCR_G4_IO1_Pos)
13987#define TSC_IOCCR_G4_IO1 TSC_IOCCR_G4_IO1_Msk
13988#define TSC_IOCCR_G4_IO2_Pos (13U)
13989#define TSC_IOCCR_G4_IO2_Msk (0x1UL << TSC_IOCCR_G4_IO2_Pos)
13990#define TSC_IOCCR_G4_IO2 TSC_IOCCR_G4_IO2_Msk
13991#define TSC_IOCCR_G4_IO3_Pos (14U)
13992#define TSC_IOCCR_G4_IO3_Msk (0x1UL << TSC_IOCCR_G4_IO3_Pos)
13993#define TSC_IOCCR_G4_IO3 TSC_IOCCR_G4_IO3_Msk
13994#define TSC_IOCCR_G4_IO4_Pos (15U)
13995#define TSC_IOCCR_G4_IO4_Msk (0x1UL << TSC_IOCCR_G4_IO4_Pos)
13996#define TSC_IOCCR_G4_IO4 TSC_IOCCR_G4_IO4_Msk
13997#define TSC_IOCCR_G5_IO1_Pos (16U)
13998#define TSC_IOCCR_G5_IO1_Msk (0x1UL << TSC_IOCCR_G5_IO1_Pos)
13999#define TSC_IOCCR_G5_IO1 TSC_IOCCR_G5_IO1_Msk
14000#define TSC_IOCCR_G5_IO2_Pos (17U)
14001#define TSC_IOCCR_G5_IO2_Msk (0x1UL << TSC_IOCCR_G5_IO2_Pos)
14002#define TSC_IOCCR_G5_IO2 TSC_IOCCR_G5_IO2_Msk
14003#define TSC_IOCCR_G5_IO3_Pos (18U)
14004#define TSC_IOCCR_G5_IO3_Msk (0x1UL << TSC_IOCCR_G5_IO3_Pos)
14005#define TSC_IOCCR_G5_IO3 TSC_IOCCR_G5_IO3_Msk
14006#define TSC_IOCCR_G5_IO4_Pos (19U)
14007#define TSC_IOCCR_G5_IO4_Msk (0x1UL << TSC_IOCCR_G5_IO4_Pos)
14008#define TSC_IOCCR_G5_IO4 TSC_IOCCR_G5_IO4_Msk
14009#define TSC_IOCCR_G6_IO1_Pos (20U)
14010#define TSC_IOCCR_G6_IO1_Msk (0x1UL << TSC_IOCCR_G6_IO1_Pos)
14011#define TSC_IOCCR_G6_IO1 TSC_IOCCR_G6_IO1_Msk
14012#define TSC_IOCCR_G6_IO2_Pos (21U)
14013#define TSC_IOCCR_G6_IO2_Msk (0x1UL << TSC_IOCCR_G6_IO2_Pos)
14014#define TSC_IOCCR_G6_IO2 TSC_IOCCR_G6_IO2_Msk
14015#define TSC_IOCCR_G6_IO3_Pos (22U)
14016#define TSC_IOCCR_G6_IO3_Msk (0x1UL << TSC_IOCCR_G6_IO3_Pos)
14017#define TSC_IOCCR_G6_IO3 TSC_IOCCR_G6_IO3_Msk
14018#define TSC_IOCCR_G6_IO4_Pos (23U)
14019#define TSC_IOCCR_G6_IO4_Msk (0x1UL << TSC_IOCCR_G6_IO4_Pos)
14020#define TSC_IOCCR_G6_IO4 TSC_IOCCR_G6_IO4_Msk
14021#define TSC_IOCCR_G7_IO1_Pos (24U)
14022#define TSC_IOCCR_G7_IO1_Msk (0x1UL << TSC_IOCCR_G7_IO1_Pos)
14023#define TSC_IOCCR_G7_IO1 TSC_IOCCR_G7_IO1_Msk
14024#define TSC_IOCCR_G7_IO2_Pos (25U)
14025#define TSC_IOCCR_G7_IO2_Msk (0x1UL << TSC_IOCCR_G7_IO2_Pos)
14026#define TSC_IOCCR_G7_IO2 TSC_IOCCR_G7_IO2_Msk
14027#define TSC_IOCCR_G7_IO3_Pos (26U)
14028#define TSC_IOCCR_G7_IO3_Msk (0x1UL << TSC_IOCCR_G7_IO3_Pos)
14029#define TSC_IOCCR_G7_IO3 TSC_IOCCR_G7_IO3_Msk
14030#define TSC_IOCCR_G7_IO4_Pos (27U)
14031#define TSC_IOCCR_G7_IO4_Msk (0x1UL << TSC_IOCCR_G7_IO4_Pos)
14032#define TSC_IOCCR_G7_IO4 TSC_IOCCR_G7_IO4_Msk
14033#define TSC_IOCCR_G8_IO1_Pos (28U)
14034#define TSC_IOCCR_G8_IO1_Msk (0x1UL << TSC_IOCCR_G8_IO1_Pos)
14035#define TSC_IOCCR_G8_IO1 TSC_IOCCR_G8_IO1_Msk
14036#define TSC_IOCCR_G8_IO2_Pos (29U)
14037#define TSC_IOCCR_G8_IO2_Msk (0x1UL << TSC_IOCCR_G8_IO2_Pos)
14038#define TSC_IOCCR_G8_IO2 TSC_IOCCR_G8_IO2_Msk
14039#define TSC_IOCCR_G8_IO3_Pos (30U)
14040#define TSC_IOCCR_G8_IO3_Msk (0x1UL << TSC_IOCCR_G8_IO3_Pos)
14041#define TSC_IOCCR_G8_IO3 TSC_IOCCR_G8_IO3_Msk
14042#define TSC_IOCCR_G8_IO4_Pos (31U)
14043#define TSC_IOCCR_G8_IO4_Msk (0x1UL << TSC_IOCCR_G8_IO4_Pos)
14044#define TSC_IOCCR_G8_IO4 TSC_IOCCR_G8_IO4_Msk
14046/******************* Bit definition for TSC_IOGCSR register *****************/
14047#define TSC_IOGCSR_G1E_Pos (0U)
14048#define TSC_IOGCSR_G1E_Msk (0x1UL << TSC_IOGCSR_G1E_Pos)
14049#define TSC_IOGCSR_G1E TSC_IOGCSR_G1E_Msk
14050#define TSC_IOGCSR_G2E_Pos (1U)
14051#define TSC_IOGCSR_G2E_Msk (0x1UL << TSC_IOGCSR_G2E_Pos)
14052#define TSC_IOGCSR_G2E TSC_IOGCSR_G2E_Msk
14053#define TSC_IOGCSR_G3E_Pos (2U)
14054#define TSC_IOGCSR_G3E_Msk (0x1UL << TSC_IOGCSR_G3E_Pos)
14055#define TSC_IOGCSR_G3E TSC_IOGCSR_G3E_Msk
14056#define TSC_IOGCSR_G4E_Pos (3U)
14057#define TSC_IOGCSR_G4E_Msk (0x1UL << TSC_IOGCSR_G4E_Pos)
14058#define TSC_IOGCSR_G4E TSC_IOGCSR_G4E_Msk
14059#define TSC_IOGCSR_G5E_Pos (4U)
14060#define TSC_IOGCSR_G5E_Msk (0x1UL << TSC_IOGCSR_G5E_Pos)
14061#define TSC_IOGCSR_G5E TSC_IOGCSR_G5E_Msk
14062#define TSC_IOGCSR_G6E_Pos (5U)
14063#define TSC_IOGCSR_G6E_Msk (0x1UL << TSC_IOGCSR_G6E_Pos)
14064#define TSC_IOGCSR_G6E TSC_IOGCSR_G6E_Msk
14065#define TSC_IOGCSR_G7E_Pos (6U)
14066#define TSC_IOGCSR_G7E_Msk (0x1UL << TSC_IOGCSR_G7E_Pos)
14067#define TSC_IOGCSR_G7E TSC_IOGCSR_G7E_Msk
14068#define TSC_IOGCSR_G8E_Pos (7U)
14069#define TSC_IOGCSR_G8E_Msk (0x1UL << TSC_IOGCSR_G8E_Pos)
14070#define TSC_IOGCSR_G8E TSC_IOGCSR_G8E_Msk
14071#define TSC_IOGCSR_G1S_Pos (16U)
14072#define TSC_IOGCSR_G1S_Msk (0x1UL << TSC_IOGCSR_G1S_Pos)
14073#define TSC_IOGCSR_G1S TSC_IOGCSR_G1S_Msk
14074#define TSC_IOGCSR_G2S_Pos (17U)
14075#define TSC_IOGCSR_G2S_Msk (0x1UL << TSC_IOGCSR_G2S_Pos)
14076#define TSC_IOGCSR_G2S TSC_IOGCSR_G2S_Msk
14077#define TSC_IOGCSR_G3S_Pos (18U)
14078#define TSC_IOGCSR_G3S_Msk (0x1UL << TSC_IOGCSR_G3S_Pos)
14079#define TSC_IOGCSR_G3S TSC_IOGCSR_G3S_Msk
14080#define TSC_IOGCSR_G4S_Pos (19U)
14081#define TSC_IOGCSR_G4S_Msk (0x1UL << TSC_IOGCSR_G4S_Pos)
14082#define TSC_IOGCSR_G4S TSC_IOGCSR_G4S_Msk
14083#define TSC_IOGCSR_G5S_Pos (20U)
14084#define TSC_IOGCSR_G5S_Msk (0x1UL << TSC_IOGCSR_G5S_Pos)
14085#define TSC_IOGCSR_G5S TSC_IOGCSR_G5S_Msk
14086#define TSC_IOGCSR_G6S_Pos (21U)
14087#define TSC_IOGCSR_G6S_Msk (0x1UL << TSC_IOGCSR_G6S_Pos)
14088#define TSC_IOGCSR_G6S TSC_IOGCSR_G6S_Msk
14089#define TSC_IOGCSR_G7S_Pos (22U)
14090#define TSC_IOGCSR_G7S_Msk (0x1UL << TSC_IOGCSR_G7S_Pos)
14091#define TSC_IOGCSR_G7S TSC_IOGCSR_G7S_Msk
14092#define TSC_IOGCSR_G8S_Pos (23U)
14093#define TSC_IOGCSR_G8S_Msk (0x1UL << TSC_IOGCSR_G8S_Pos)
14094#define TSC_IOGCSR_G8S TSC_IOGCSR_G8S_Msk
14096/******************* Bit definition for TSC_IOGXCR register *****************/
14097#define TSC_IOGXCR_CNT_Pos (0U)
14098#define TSC_IOGXCR_CNT_Msk (0x3FFFUL << TSC_IOGXCR_CNT_Pos)
14099#define TSC_IOGXCR_CNT TSC_IOGXCR_CNT_Msk
14101/******************************************************************************/
14102/* */
14103/* Universal Synchronous Asynchronous Receiver Transmitter (USART) */
14104/* */
14105/******************************************************************************/
14106
14107/*
14108* @brief Specific device feature definitions (not present on all devices in the STM32F3 series)
14109*/
14110
14111/* Support of 7 bits data length feature */
14112#define USART_7BITS_SUPPORT
14113
14114/****************** Bit definition for USART_CR1 register *******************/
14115#define USART_CR1_UE_Pos (0U)
14116#define USART_CR1_UE_Msk (0x1UL << USART_CR1_UE_Pos)
14117#define USART_CR1_UE USART_CR1_UE_Msk
14118#define USART_CR1_UESM_Pos (1U)
14119#define USART_CR1_UESM_Msk (0x1UL << USART_CR1_UESM_Pos)
14120#define USART_CR1_UESM USART_CR1_UESM_Msk
14121#define USART_CR1_RE_Pos (2U)
14122#define USART_CR1_RE_Msk (0x1UL << USART_CR1_RE_Pos)
14123#define USART_CR1_RE USART_CR1_RE_Msk
14124#define USART_CR1_TE_Pos (3U)
14125#define USART_CR1_TE_Msk (0x1UL << USART_CR1_TE_Pos)
14126#define USART_CR1_TE USART_CR1_TE_Msk
14127#define USART_CR1_IDLEIE_Pos (4U)
14128#define USART_CR1_IDLEIE_Msk (0x1UL << USART_CR1_IDLEIE_Pos)
14129#define USART_CR1_IDLEIE USART_CR1_IDLEIE_Msk
14130#define USART_CR1_RXNEIE_Pos (5U)
14131#define USART_CR1_RXNEIE_Msk (0x1UL << USART_CR1_RXNEIE_Pos)
14132#define USART_CR1_RXNEIE USART_CR1_RXNEIE_Msk
14133#define USART_CR1_TCIE_Pos (6U)
14134#define USART_CR1_TCIE_Msk (0x1UL << USART_CR1_TCIE_Pos)
14135#define USART_CR1_TCIE USART_CR1_TCIE_Msk
14136#define USART_CR1_TXEIE_Pos (7U)
14137#define USART_CR1_TXEIE_Msk (0x1UL << USART_CR1_TXEIE_Pos)
14138#define USART_CR1_TXEIE USART_CR1_TXEIE_Msk
14139#define USART_CR1_PEIE_Pos (8U)
14140#define USART_CR1_PEIE_Msk (0x1UL << USART_CR1_PEIE_Pos)
14141#define USART_CR1_PEIE USART_CR1_PEIE_Msk
14142#define USART_CR1_PS_Pos (9U)
14143#define USART_CR1_PS_Msk (0x1UL << USART_CR1_PS_Pos)
14144#define USART_CR1_PS USART_CR1_PS_Msk
14145#define USART_CR1_PCE_Pos (10U)
14146#define USART_CR1_PCE_Msk (0x1UL << USART_CR1_PCE_Pos)
14147#define USART_CR1_PCE USART_CR1_PCE_Msk
14148#define USART_CR1_WAKE_Pos (11U)
14149#define USART_CR1_WAKE_Msk (0x1UL << USART_CR1_WAKE_Pos)
14150#define USART_CR1_WAKE USART_CR1_WAKE_Msk
14151#define USART_CR1_M0_Pos (12U)
14152#define USART_CR1_M0_Msk (0x1UL << USART_CR1_M0_Pos)
14153#define USART_CR1_M0 USART_CR1_M0_Msk
14154#define USART_CR1_MME_Pos (13U)
14155#define USART_CR1_MME_Msk (0x1UL << USART_CR1_MME_Pos)
14156#define USART_CR1_MME USART_CR1_MME_Msk
14157#define USART_CR1_CMIE_Pos (14U)
14158#define USART_CR1_CMIE_Msk (0x1UL << USART_CR1_CMIE_Pos)
14159#define USART_CR1_CMIE USART_CR1_CMIE_Msk
14160#define USART_CR1_OVER8_Pos (15U)
14161#define USART_CR1_OVER8_Msk (0x1UL << USART_CR1_OVER8_Pos)
14162#define USART_CR1_OVER8 USART_CR1_OVER8_Msk
14163#define USART_CR1_DEDT_Pos (16U)
14164#define USART_CR1_DEDT_Msk (0x1FUL << USART_CR1_DEDT_Pos)
14165#define USART_CR1_DEDT USART_CR1_DEDT_Msk
14166#define USART_CR1_DEDT_0 (0x01UL << USART_CR1_DEDT_Pos)
14167#define USART_CR1_DEDT_1 (0x02UL << USART_CR1_DEDT_Pos)
14168#define USART_CR1_DEDT_2 (0x04UL << USART_CR1_DEDT_Pos)
14169#define USART_CR1_DEDT_3 (0x08UL << USART_CR1_DEDT_Pos)
14170#define USART_CR1_DEDT_4 (0x10UL << USART_CR1_DEDT_Pos)
14171#define USART_CR1_DEAT_Pos (21U)
14172#define USART_CR1_DEAT_Msk (0x1FUL << USART_CR1_DEAT_Pos)
14173#define USART_CR1_DEAT USART_CR1_DEAT_Msk
14174#define USART_CR1_DEAT_0 (0x01UL << USART_CR1_DEAT_Pos)
14175#define USART_CR1_DEAT_1 (0x02UL << USART_CR1_DEAT_Pos)
14176#define USART_CR1_DEAT_2 (0x04UL << USART_CR1_DEAT_Pos)
14177#define USART_CR1_DEAT_3 (0x08UL << USART_CR1_DEAT_Pos)
14178#define USART_CR1_DEAT_4 (0x10UL << USART_CR1_DEAT_Pos)
14179#define USART_CR1_RTOIE_Pos (26U)
14180#define USART_CR1_RTOIE_Msk (0x1UL << USART_CR1_RTOIE_Pos)
14181#define USART_CR1_RTOIE USART_CR1_RTOIE_Msk
14182#define USART_CR1_EOBIE_Pos (27U)
14183#define USART_CR1_EOBIE_Msk (0x1UL << USART_CR1_EOBIE_Pos)
14184#define USART_CR1_EOBIE USART_CR1_EOBIE_Msk
14185#define USART_CR1_M1_Pos (28U)
14186#define USART_CR1_M1_Msk (0x1UL << USART_CR1_M1_Pos)
14187#define USART_CR1_M1 USART_CR1_M1_Msk
14188#define USART_CR1_M_Pos (12U)
14189#define USART_CR1_M_Msk (0x10001UL << USART_CR1_M_Pos)
14190#define USART_CR1_M USART_CR1_M_Msk
14192/****************** Bit definition for USART_CR2 register *******************/
14193#define USART_CR2_ADDM7_Pos (4U)
14194#define USART_CR2_ADDM7_Msk (0x1UL << USART_CR2_ADDM7_Pos)
14195#define USART_CR2_ADDM7 USART_CR2_ADDM7_Msk
14196#define USART_CR2_LBDL_Pos (5U)
14197#define USART_CR2_LBDL_Msk (0x1UL << USART_CR2_LBDL_Pos)
14198#define USART_CR2_LBDL USART_CR2_LBDL_Msk
14199#define USART_CR2_LBDIE_Pos (6U)
14200#define USART_CR2_LBDIE_Msk (0x1UL << USART_CR2_LBDIE_Pos)
14201#define USART_CR2_LBDIE USART_CR2_LBDIE_Msk
14202#define USART_CR2_LBCL_Pos (8U)
14203#define USART_CR2_LBCL_Msk (0x1UL << USART_CR2_LBCL_Pos)
14204#define USART_CR2_LBCL USART_CR2_LBCL_Msk
14205#define USART_CR2_CPHA_Pos (9U)
14206#define USART_CR2_CPHA_Msk (0x1UL << USART_CR2_CPHA_Pos)
14207#define USART_CR2_CPHA USART_CR2_CPHA_Msk
14208#define USART_CR2_CPOL_Pos (10U)
14209#define USART_CR2_CPOL_Msk (0x1UL << USART_CR2_CPOL_Pos)
14210#define USART_CR2_CPOL USART_CR2_CPOL_Msk
14211#define USART_CR2_CLKEN_Pos (11U)
14212#define USART_CR2_CLKEN_Msk (0x1UL << USART_CR2_CLKEN_Pos)
14213#define USART_CR2_CLKEN USART_CR2_CLKEN_Msk
14214#define USART_CR2_STOP_Pos (12U)
14215#define USART_CR2_STOP_Msk (0x3UL << USART_CR2_STOP_Pos)
14216#define USART_CR2_STOP USART_CR2_STOP_Msk
14217#define USART_CR2_STOP_0 (0x1UL << USART_CR2_STOP_Pos)
14218#define USART_CR2_STOP_1 (0x2UL << USART_CR2_STOP_Pos)
14219#define USART_CR2_LINEN_Pos (14U)
14220#define USART_CR2_LINEN_Msk (0x1UL << USART_CR2_LINEN_Pos)
14221#define USART_CR2_LINEN USART_CR2_LINEN_Msk
14222#define USART_CR2_SWAP_Pos (15U)
14223#define USART_CR2_SWAP_Msk (0x1UL << USART_CR2_SWAP_Pos)
14224#define USART_CR2_SWAP USART_CR2_SWAP_Msk
14225#define USART_CR2_RXINV_Pos (16U)
14226#define USART_CR2_RXINV_Msk (0x1UL << USART_CR2_RXINV_Pos)
14227#define USART_CR2_RXINV USART_CR2_RXINV_Msk
14228#define USART_CR2_TXINV_Pos (17U)
14229#define USART_CR2_TXINV_Msk (0x1UL << USART_CR2_TXINV_Pos)
14230#define USART_CR2_TXINV USART_CR2_TXINV_Msk
14231#define USART_CR2_DATAINV_Pos (18U)
14232#define USART_CR2_DATAINV_Msk (0x1UL << USART_CR2_DATAINV_Pos)
14233#define USART_CR2_DATAINV USART_CR2_DATAINV_Msk
14234#define USART_CR2_MSBFIRST_Pos (19U)
14235#define USART_CR2_MSBFIRST_Msk (0x1UL << USART_CR2_MSBFIRST_Pos)
14236#define USART_CR2_MSBFIRST USART_CR2_MSBFIRST_Msk
14237#define USART_CR2_ABREN_Pos (20U)
14238#define USART_CR2_ABREN_Msk (0x1UL << USART_CR2_ABREN_Pos)
14239#define USART_CR2_ABREN USART_CR2_ABREN_Msk
14240#define USART_CR2_ABRMODE_Pos (21U)
14241#define USART_CR2_ABRMODE_Msk (0x3UL << USART_CR2_ABRMODE_Pos)
14242#define USART_CR2_ABRMODE USART_CR2_ABRMODE_Msk
14243#define USART_CR2_ABRMODE_0 (0x1UL << USART_CR2_ABRMODE_Pos)
14244#define USART_CR2_ABRMODE_1 (0x2UL << USART_CR2_ABRMODE_Pos)
14245#define USART_CR2_RTOEN_Pos (23U)
14246#define USART_CR2_RTOEN_Msk (0x1UL << USART_CR2_RTOEN_Pos)
14247#define USART_CR2_RTOEN USART_CR2_RTOEN_Msk
14248#define USART_CR2_ADD_Pos (24U)
14249#define USART_CR2_ADD_Msk (0xFFUL << USART_CR2_ADD_Pos)
14250#define USART_CR2_ADD USART_CR2_ADD_Msk
14252/****************** Bit definition for USART_CR3 register *******************/
14253#define USART_CR3_EIE_Pos (0U)
14254#define USART_CR3_EIE_Msk (0x1UL << USART_CR3_EIE_Pos)
14255#define USART_CR3_EIE USART_CR3_EIE_Msk
14256#define USART_CR3_IREN_Pos (1U)
14257#define USART_CR3_IREN_Msk (0x1UL << USART_CR3_IREN_Pos)
14258#define USART_CR3_IREN USART_CR3_IREN_Msk
14259#define USART_CR3_IRLP_Pos (2U)
14260#define USART_CR3_IRLP_Msk (0x1UL << USART_CR3_IRLP_Pos)
14261#define USART_CR3_IRLP USART_CR3_IRLP_Msk
14262#define USART_CR3_HDSEL_Pos (3U)
14263#define USART_CR3_HDSEL_Msk (0x1UL << USART_CR3_HDSEL_Pos)
14264#define USART_CR3_HDSEL USART_CR3_HDSEL_Msk
14265#define USART_CR3_NACK_Pos (4U)
14266#define USART_CR3_NACK_Msk (0x1UL << USART_CR3_NACK_Pos)
14267#define USART_CR3_NACK USART_CR3_NACK_Msk
14268#define USART_CR3_SCEN_Pos (5U)
14269#define USART_CR3_SCEN_Msk (0x1UL << USART_CR3_SCEN_Pos)
14270#define USART_CR3_SCEN USART_CR3_SCEN_Msk
14271#define USART_CR3_DMAR_Pos (6U)
14272#define USART_CR3_DMAR_Msk (0x1UL << USART_CR3_DMAR_Pos)
14273#define USART_CR3_DMAR USART_CR3_DMAR_Msk
14274#define USART_CR3_DMAT_Pos (7U)
14275#define USART_CR3_DMAT_Msk (0x1UL << USART_CR3_DMAT_Pos)
14276#define USART_CR3_DMAT USART_CR3_DMAT_Msk
14277#define USART_CR3_RTSE_Pos (8U)
14278#define USART_CR3_RTSE_Msk (0x1UL << USART_CR3_RTSE_Pos)
14279#define USART_CR3_RTSE USART_CR3_RTSE_Msk
14280#define USART_CR3_CTSE_Pos (9U)
14281#define USART_CR3_CTSE_Msk (0x1UL << USART_CR3_CTSE_Pos)
14282#define USART_CR3_CTSE USART_CR3_CTSE_Msk
14283#define USART_CR3_CTSIE_Pos (10U)
14284#define USART_CR3_CTSIE_Msk (0x1UL << USART_CR3_CTSIE_Pos)
14285#define USART_CR3_CTSIE USART_CR3_CTSIE_Msk
14286#define USART_CR3_ONEBIT_Pos (11U)
14287#define USART_CR3_ONEBIT_Msk (0x1UL << USART_CR3_ONEBIT_Pos)
14288#define USART_CR3_ONEBIT USART_CR3_ONEBIT_Msk
14289#define USART_CR3_OVRDIS_Pos (12U)
14290#define USART_CR3_OVRDIS_Msk (0x1UL << USART_CR3_OVRDIS_Pos)
14291#define USART_CR3_OVRDIS USART_CR3_OVRDIS_Msk
14292#define USART_CR3_DDRE_Pos (13U)
14293#define USART_CR3_DDRE_Msk (0x1UL << USART_CR3_DDRE_Pos)
14294#define USART_CR3_DDRE USART_CR3_DDRE_Msk
14295#define USART_CR3_DEM_Pos (14U)
14296#define USART_CR3_DEM_Msk (0x1UL << USART_CR3_DEM_Pos)
14297#define USART_CR3_DEM USART_CR3_DEM_Msk
14298#define USART_CR3_DEP_Pos (15U)
14299#define USART_CR3_DEP_Msk (0x1UL << USART_CR3_DEP_Pos)
14300#define USART_CR3_DEP USART_CR3_DEP_Msk
14301#define USART_CR3_SCARCNT_Pos (17U)
14302#define USART_CR3_SCARCNT_Msk (0x7UL << USART_CR3_SCARCNT_Pos)
14303#define USART_CR3_SCARCNT USART_CR3_SCARCNT_Msk
14304#define USART_CR3_SCARCNT_0 (0x1UL << USART_CR3_SCARCNT_Pos)
14305#define USART_CR3_SCARCNT_1 (0x2UL << USART_CR3_SCARCNT_Pos)
14306#define USART_CR3_SCARCNT_2 (0x4UL << USART_CR3_SCARCNT_Pos)
14307#define USART_CR3_WUS_Pos (20U)
14308#define USART_CR3_WUS_Msk (0x3UL << USART_CR3_WUS_Pos)
14309#define USART_CR3_WUS USART_CR3_WUS_Msk
14310#define USART_CR3_WUS_0 (0x1UL << USART_CR3_WUS_Pos)
14311#define USART_CR3_WUS_1 (0x2UL << USART_CR3_WUS_Pos)
14312#define USART_CR3_WUFIE_Pos (22U)
14313#define USART_CR3_WUFIE_Msk (0x1UL << USART_CR3_WUFIE_Pos)
14314#define USART_CR3_WUFIE USART_CR3_WUFIE_Msk
14316/****************** Bit definition for USART_BRR register *******************/
14317#define USART_BRR_DIV_FRACTION_Pos (0U)
14318#define USART_BRR_DIV_FRACTION_Msk (0xFUL << USART_BRR_DIV_FRACTION_Pos)
14319#define USART_BRR_DIV_FRACTION USART_BRR_DIV_FRACTION_Msk
14320#define USART_BRR_DIV_MANTISSA_Pos (4U)
14321#define USART_BRR_DIV_MANTISSA_Msk (0xFFFUL << USART_BRR_DIV_MANTISSA_Pos)
14322#define USART_BRR_DIV_MANTISSA USART_BRR_DIV_MANTISSA_Msk
14324/****************** Bit definition for USART_GTPR register ******************/
14325#define USART_GTPR_PSC_Pos (0U)
14326#define USART_GTPR_PSC_Msk (0xFFUL << USART_GTPR_PSC_Pos)
14327#define USART_GTPR_PSC USART_GTPR_PSC_Msk
14328#define USART_GTPR_GT_Pos (8U)
14329#define USART_GTPR_GT_Msk (0xFFUL << USART_GTPR_GT_Pos)
14330#define USART_GTPR_GT USART_GTPR_GT_Msk
14333/******************* Bit definition for USART_RTOR register *****************/
14334#define USART_RTOR_RTO_Pos (0U)
14335#define USART_RTOR_RTO_Msk (0xFFFFFFUL << USART_RTOR_RTO_Pos)
14336#define USART_RTOR_RTO USART_RTOR_RTO_Msk
14337#define USART_RTOR_BLEN_Pos (24U)
14338#define USART_RTOR_BLEN_Msk (0xFFUL << USART_RTOR_BLEN_Pos)
14339#define USART_RTOR_BLEN USART_RTOR_BLEN_Msk
14341/******************* Bit definition for USART_RQR register ******************/
14342#define USART_RQR_ABRRQ_Pos (0U)
14343#define USART_RQR_ABRRQ_Msk (0x1UL << USART_RQR_ABRRQ_Pos)
14344#define USART_RQR_ABRRQ USART_RQR_ABRRQ_Msk
14345#define USART_RQR_SBKRQ_Pos (1U)
14346#define USART_RQR_SBKRQ_Msk (0x1UL << USART_RQR_SBKRQ_Pos)
14347#define USART_RQR_SBKRQ USART_RQR_SBKRQ_Msk
14348#define USART_RQR_MMRQ_Pos (2U)
14349#define USART_RQR_MMRQ_Msk (0x1UL << USART_RQR_MMRQ_Pos)
14350#define USART_RQR_MMRQ USART_RQR_MMRQ_Msk
14351#define USART_RQR_RXFRQ_Pos (3U)
14352#define USART_RQR_RXFRQ_Msk (0x1UL << USART_RQR_RXFRQ_Pos)
14353#define USART_RQR_RXFRQ USART_RQR_RXFRQ_Msk
14354#define USART_RQR_TXFRQ_Pos (4U)
14355#define USART_RQR_TXFRQ_Msk (0x1UL << USART_RQR_TXFRQ_Pos)
14356#define USART_RQR_TXFRQ USART_RQR_TXFRQ_Msk
14358/******************* Bit definition for USART_ISR register ******************/
14359#define USART_ISR_PE_Pos (0U)
14360#define USART_ISR_PE_Msk (0x1UL << USART_ISR_PE_Pos)
14361#define USART_ISR_PE USART_ISR_PE_Msk
14362#define USART_ISR_FE_Pos (1U)
14363#define USART_ISR_FE_Msk (0x1UL << USART_ISR_FE_Pos)
14364#define USART_ISR_FE USART_ISR_FE_Msk
14365#define USART_ISR_NE_Pos (2U)
14366#define USART_ISR_NE_Msk (0x1UL << USART_ISR_NE_Pos)
14367#define USART_ISR_NE USART_ISR_NE_Msk
14368#define USART_ISR_ORE_Pos (3U)
14369#define USART_ISR_ORE_Msk (0x1UL << USART_ISR_ORE_Pos)
14370#define USART_ISR_ORE USART_ISR_ORE_Msk
14371#define USART_ISR_IDLE_Pos (4U)
14372#define USART_ISR_IDLE_Msk (0x1UL << USART_ISR_IDLE_Pos)
14373#define USART_ISR_IDLE USART_ISR_IDLE_Msk
14374#define USART_ISR_RXNE_Pos (5U)
14375#define USART_ISR_RXNE_Msk (0x1UL << USART_ISR_RXNE_Pos)
14376#define USART_ISR_RXNE USART_ISR_RXNE_Msk
14377#define USART_ISR_TC_Pos (6U)
14378#define USART_ISR_TC_Msk (0x1UL << USART_ISR_TC_Pos)
14379#define USART_ISR_TC USART_ISR_TC_Msk
14380#define USART_ISR_TXE_Pos (7U)
14381#define USART_ISR_TXE_Msk (0x1UL << USART_ISR_TXE_Pos)
14382#define USART_ISR_TXE USART_ISR_TXE_Msk
14383#define USART_ISR_LBDF_Pos (8U)
14384#define USART_ISR_LBDF_Msk (0x1UL << USART_ISR_LBDF_Pos)
14385#define USART_ISR_LBDF USART_ISR_LBDF_Msk
14386#define USART_ISR_CTSIF_Pos (9U)
14387#define USART_ISR_CTSIF_Msk (0x1UL << USART_ISR_CTSIF_Pos)
14388#define USART_ISR_CTSIF USART_ISR_CTSIF_Msk
14389#define USART_ISR_CTS_Pos (10U)
14390#define USART_ISR_CTS_Msk (0x1UL << USART_ISR_CTS_Pos)
14391#define USART_ISR_CTS USART_ISR_CTS_Msk
14392#define USART_ISR_RTOF_Pos (11U)
14393#define USART_ISR_RTOF_Msk (0x1UL << USART_ISR_RTOF_Pos)
14394#define USART_ISR_RTOF USART_ISR_RTOF_Msk
14395#define USART_ISR_EOBF_Pos (12U)
14396#define USART_ISR_EOBF_Msk (0x1UL << USART_ISR_EOBF_Pos)
14397#define USART_ISR_EOBF USART_ISR_EOBF_Msk
14398#define USART_ISR_ABRE_Pos (14U)
14399#define USART_ISR_ABRE_Msk (0x1UL << USART_ISR_ABRE_Pos)
14400#define USART_ISR_ABRE USART_ISR_ABRE_Msk
14401#define USART_ISR_ABRF_Pos (15U)
14402#define USART_ISR_ABRF_Msk (0x1UL << USART_ISR_ABRF_Pos)
14403#define USART_ISR_ABRF USART_ISR_ABRF_Msk
14404#define USART_ISR_BUSY_Pos (16U)
14405#define USART_ISR_BUSY_Msk (0x1UL << USART_ISR_BUSY_Pos)
14406#define USART_ISR_BUSY USART_ISR_BUSY_Msk
14407#define USART_ISR_CMF_Pos (17U)
14408#define USART_ISR_CMF_Msk (0x1UL << USART_ISR_CMF_Pos)
14409#define USART_ISR_CMF USART_ISR_CMF_Msk
14410#define USART_ISR_SBKF_Pos (18U)
14411#define USART_ISR_SBKF_Msk (0x1UL << USART_ISR_SBKF_Pos)
14412#define USART_ISR_SBKF USART_ISR_SBKF_Msk
14413#define USART_ISR_RWU_Pos (19U)
14414#define USART_ISR_RWU_Msk (0x1UL << USART_ISR_RWU_Pos)
14415#define USART_ISR_RWU USART_ISR_RWU_Msk
14416#define USART_ISR_WUF_Pos (20U)
14417#define USART_ISR_WUF_Msk (0x1UL << USART_ISR_WUF_Pos)
14418#define USART_ISR_WUF USART_ISR_WUF_Msk
14419#define USART_ISR_TEACK_Pos (21U)
14420#define USART_ISR_TEACK_Msk (0x1UL << USART_ISR_TEACK_Pos)
14421#define USART_ISR_TEACK USART_ISR_TEACK_Msk
14422#define USART_ISR_REACK_Pos (22U)
14423#define USART_ISR_REACK_Msk (0x1UL << USART_ISR_REACK_Pos)
14424#define USART_ISR_REACK USART_ISR_REACK_Msk
14426/******************* Bit definition for USART_ICR register ******************/
14427#define USART_ICR_PECF_Pos (0U)
14428#define USART_ICR_PECF_Msk (0x1UL << USART_ICR_PECF_Pos)
14429#define USART_ICR_PECF USART_ICR_PECF_Msk
14430#define USART_ICR_FECF_Pos (1U)
14431#define USART_ICR_FECF_Msk (0x1UL << USART_ICR_FECF_Pos)
14432#define USART_ICR_FECF USART_ICR_FECF_Msk
14433#define USART_ICR_NCF_Pos (2U)
14434#define USART_ICR_NCF_Msk (0x1UL << USART_ICR_NCF_Pos)
14435#define USART_ICR_NCF USART_ICR_NCF_Msk
14436#define USART_ICR_ORECF_Pos (3U)
14437#define USART_ICR_ORECF_Msk (0x1UL << USART_ICR_ORECF_Pos)
14438#define USART_ICR_ORECF USART_ICR_ORECF_Msk
14439#define USART_ICR_IDLECF_Pos (4U)
14440#define USART_ICR_IDLECF_Msk (0x1UL << USART_ICR_IDLECF_Pos)
14441#define USART_ICR_IDLECF USART_ICR_IDLECF_Msk
14442#define USART_ICR_TCCF_Pos (6U)
14443#define USART_ICR_TCCF_Msk (0x1UL << USART_ICR_TCCF_Pos)
14444#define USART_ICR_TCCF USART_ICR_TCCF_Msk
14445#define USART_ICR_LBDCF_Pos (8U)
14446#define USART_ICR_LBDCF_Msk (0x1UL << USART_ICR_LBDCF_Pos)
14447#define USART_ICR_LBDCF USART_ICR_LBDCF_Msk
14448#define USART_ICR_CTSCF_Pos (9U)
14449#define USART_ICR_CTSCF_Msk (0x1UL << USART_ICR_CTSCF_Pos)
14450#define USART_ICR_CTSCF USART_ICR_CTSCF_Msk
14451#define USART_ICR_RTOCF_Pos (11U)
14452#define USART_ICR_RTOCF_Msk (0x1UL << USART_ICR_RTOCF_Pos)
14453#define USART_ICR_RTOCF USART_ICR_RTOCF_Msk
14454#define USART_ICR_EOBCF_Pos (12U)
14455#define USART_ICR_EOBCF_Msk (0x1UL << USART_ICR_EOBCF_Pos)
14456#define USART_ICR_EOBCF USART_ICR_EOBCF_Msk
14457#define USART_ICR_CMCF_Pos (17U)
14458#define USART_ICR_CMCF_Msk (0x1UL << USART_ICR_CMCF_Pos)
14459#define USART_ICR_CMCF USART_ICR_CMCF_Msk
14460#define USART_ICR_WUCF_Pos (20U)
14461#define USART_ICR_WUCF_Msk (0x1UL << USART_ICR_WUCF_Pos)
14462#define USART_ICR_WUCF USART_ICR_WUCF_Msk
14464/******************* Bit definition for USART_RDR register ******************/
14465#define USART_RDR_RDR_Pos (0U)
14466#define USART_RDR_RDR_Msk (0x1FFUL << USART_RDR_RDR_Pos)
14467#define USART_RDR_RDR USART_RDR_RDR_Msk
14469/******************* Bit definition for USART_TDR register ******************/
14470#define USART_TDR_TDR_Pos (0U)
14471#define USART_TDR_TDR_Msk (0x1FFUL << USART_TDR_TDR_Pos)
14472#define USART_TDR_TDR USART_TDR_TDR_Msk
14474/******************************************************************************/
14475/* */
14476/* USB Device General registers */
14477/* */
14478/******************************************************************************/
14479#define USB_CNTR (USB_BASE + 0x40U)
14480#define USB_ISTR (USB_BASE + 0x44U)
14481#define USB_FNR (USB_BASE + 0x48U)
14482#define USB_DADDR (USB_BASE + 0x4CU)
14483#define USB_BTABLE (USB_BASE + 0x50U)
14484#define USB_LPMCSR (USB_BASE + 0x54U)
14486/**************************** ISTR interrupt events *************************/
14487#define USB_ISTR_CTR ((uint16_t)0x8000U)
14488#define USB_ISTR_PMAOVR ((uint16_t)0x4000U)
14489#define USB_ISTR_ERR ((uint16_t)0x2000U)
14490#define USB_ISTR_WKUP ((uint16_t)0x1000U)
14491#define USB_ISTR_SUSP ((uint16_t)0x0800U)
14492#define USB_ISTR_RESET ((uint16_t)0x0400U)
14493#define USB_ISTR_SOF ((uint16_t)0x0200U)
14494#define USB_ISTR_ESOF ((uint16_t)0x0100U)
14495#define USB_ISTR_L1REQ ((uint16_t)0x0080U)
14496#define USB_ISTR_DIR ((uint16_t)0x0010U)
14497#define USB_ISTR_EP_ID ((uint16_t)0x000FU)
14499/* Legacy defines */
14500#define USB_ISTR_PMAOVRM USB_ISTR_PMAOVR
14501
14502#define USB_CLR_CTR (~USB_ISTR_CTR)
14503#define USB_CLR_PMAOVR (~USB_ISTR_PMAOVR)
14504#define USB_CLR_ERR (~USB_ISTR_ERR)
14505#define USB_CLR_WKUP (~USB_ISTR_WKUP)
14506#define USB_CLR_SUSP (~USB_ISTR_SUSP)
14507#define USB_CLR_RESET (~USB_ISTR_RESET)
14508#define USB_CLR_SOF (~USB_ISTR_SOF)
14509#define USB_CLR_ESOF (~USB_ISTR_ESOF)
14510#define USB_CLR_L1REQ (~USB_ISTR_L1REQ)
14512/* Legacy defines */
14513#define USB_CLR_PMAOVRM USB_CLR_PMAOVR
14514
14515/************************* CNTR control register bits definitions ***********/
14516#define USB_CNTR_CTRM ((uint16_t)0x8000U)
14517#define USB_CNTR_PMAOVR ((uint16_t)0x4000U)
14518#define USB_CNTR_ERRM ((uint16_t)0x2000U)
14519#define USB_CNTR_WKUPM ((uint16_t)0x1000U)
14520#define USB_CNTR_SUSPM ((uint16_t)0x0800U)
14521#define USB_CNTR_RESETM ((uint16_t)0x0400U)
14522#define USB_CNTR_SOFM ((uint16_t)0x0200U)
14523#define USB_CNTR_ESOFM ((uint16_t)0x0100U)
14524#define USB_CNTR_L1REQM ((uint16_t)0x0080U)
14525#define USB_CNTR_L1RESUME ((uint16_t)0x0020U)
14526#define USB_CNTR_RESUME ((uint16_t)0x0010U)
14527#define USB_CNTR_FSUSP ((uint16_t)0x0008U)
14528#define USB_CNTR_LPMODE ((uint16_t)0x0004U)
14529#define USB_CNTR_PDWN ((uint16_t)0x0002U)
14530#define USB_CNTR_FRES ((uint16_t)0x0001U)
14532/* Legacy defines */
14533#define USB_CNTR_PMAOVRM USB_CNTR_PMAOVR
14534#define USB_CNTR_LP_MODE USB_CNTR_LPMODE
14535
14536/*************************** LPM register bits definitions ******************/
14537#define USB_LPMCSR_BESL ((uint16_t)0x00F0U)
14538#define USB_LPMCSR_REMWAKE ((uint16_t)0x0008U)
14539#define USB_LPMCSR_LPMACK ((uint16_t)0x0002U)
14540#define USB_LPMCSR_LMPEN ((uint16_t)0x0001U)
14542/******************** FNR Frame Number Register bit definitions ************/
14543#define USB_FNR_RXDP ((uint16_t)0x8000U)
14544#define USB_FNR_RXDM ((uint16_t)0x4000U)
14545#define USB_FNR_LCK ((uint16_t)0x2000U)
14546#define USB_FNR_LSOF ((uint16_t)0x1800U)
14547#define USB_FNR_FN ((uint16_t)0x07FFU)
14549/******************** DADDR Device ADDRess bit definitions ****************/
14550#define USB_DADDR_EF ((uint8_t)0x80U)
14551#define USB_DADDR_ADD ((uint8_t)0x7FU)
14553/****************************** Endpoint register *************************/
14554#define USB_EP0R USB_BASE
14555#define USB_EP1R (USB_BASE + 0x04U)
14556#define USB_EP2R (USB_BASE + 0x08U)
14557#define USB_EP3R (USB_BASE + 0x0CU)
14558#define USB_EP4R (USB_BASE + 0x10U)
14559#define USB_EP5R (USB_BASE + 0x14U)
14560#define USB_EP6R (USB_BASE + 0x18U)
14561#define USB_EP7R (USB_BASE + 0x1CU)
14562/* bit positions */
14563#define USB_EP_CTR_RX ((uint16_t)0x8000U)
14564#define USB_EP_DTOG_RX ((uint16_t)0x4000U)
14565#define USB_EPRX_STAT ((uint16_t)0x3000U)
14566#define USB_EP_SETUP ((uint16_t)0x0800U)
14567#define USB_EP_T_FIELD ((uint16_t)0x0600U)
14568#define USB_EP_KIND ((uint16_t)0x0100U)
14569#define USB_EP_CTR_TX ((uint16_t)0x0080U)
14570#define USB_EP_DTOG_TX ((uint16_t)0x0040U)
14571#define USB_EPTX_STAT ((uint16_t)0x0030U)
14572#define USB_EPADDR_FIELD ((uint16_t)0x000FU)
14574/* EndPoint REGister MASK (no toggle fields) */
14575#define USB_EPREG_MASK (USB_EP_CTR_RX|USB_EP_SETUP|USB_EP_T_FIELD|USB_EP_KIND|USB_EP_CTR_TX|USB_EPADDR_FIELD)
14577#define USB_EP_TYPE_MASK ((uint16_t)0x0600U)
14578#define USB_EP_BULK ((uint16_t)0x0000U)
14579#define USB_EP_CONTROL ((uint16_t)0x0200U)
14580#define USB_EP_ISOCHRONOUS ((uint16_t)0x0400U)
14581#define USB_EP_INTERRUPT ((uint16_t)0x0600U)
14582#define USB_EP_T_MASK ((uint16_t) ~USB_EP_T_FIELD & USB_EPREG_MASK)
14583
14584#define USB_EPKIND_MASK ((uint16_t) ~USB_EP_KIND & USB_EPREG_MASK)
14586#define USB_EP_TX_DIS ((uint16_t)0x0000U)
14587#define USB_EP_TX_STALL ((uint16_t)0x0010U)
14588#define USB_EP_TX_NAK ((uint16_t)0x0020U)
14589#define USB_EP_TX_VALID ((uint16_t)0x0030U)
14590#define USB_EPTX_DTOG1 ((uint16_t)0x0010U)
14591#define USB_EPTX_DTOG2 ((uint16_t)0x0020U)
14592#define USB_EPTX_DTOGMASK (USB_EPTX_STAT|USB_EPREG_MASK)
14594#define USB_EP_RX_DIS ((uint16_t)0x0000U)
14595#define USB_EP_RX_STALL ((uint16_t)0x1000U)
14596#define USB_EP_RX_NAK ((uint16_t)0x2000U)
14597#define USB_EP_RX_VALID ((uint16_t)0x3000U)
14598#define USB_EPRX_DTOG1 ((uint16_t)0x1000U)
14599#define USB_EPRX_DTOG2 ((uint16_t)0x2000U)
14600#define USB_EPRX_DTOGMASK (USB_EPRX_STAT|USB_EPREG_MASK)
14601
14602/******************************************************************************/
14603/* */
14604/* Window WATCHDOG */
14605/* */
14606/******************************************************************************/
14607/******************* Bit definition for WWDG_CR register ********************/
14608#define WWDG_CR_T_Pos (0U)
14609#define WWDG_CR_T_Msk (0x7FUL << WWDG_CR_T_Pos)
14610#define WWDG_CR_T WWDG_CR_T_Msk
14611#define WWDG_CR_T_0 (0x01UL << WWDG_CR_T_Pos)
14612#define WWDG_CR_T_1 (0x02UL << WWDG_CR_T_Pos)
14613#define WWDG_CR_T_2 (0x04UL << WWDG_CR_T_Pos)
14614#define WWDG_CR_T_3 (0x08UL << WWDG_CR_T_Pos)
14615#define WWDG_CR_T_4 (0x10UL << WWDG_CR_T_Pos)
14616#define WWDG_CR_T_5 (0x20UL << WWDG_CR_T_Pos)
14617#define WWDG_CR_T_6 (0x40UL << WWDG_CR_T_Pos)
14619/* Legacy defines */
14620#define WWDG_CR_T0 WWDG_CR_T_0
14621#define WWDG_CR_T1 WWDG_CR_T_1
14622#define WWDG_CR_T2 WWDG_CR_T_2
14623#define WWDG_CR_T3 WWDG_CR_T_3
14624#define WWDG_CR_T4 WWDG_CR_T_4
14625#define WWDG_CR_T5 WWDG_CR_T_5
14626#define WWDG_CR_T6 WWDG_CR_T_6
14627
14628#define WWDG_CR_WDGA_Pos (7U)
14629#define WWDG_CR_WDGA_Msk (0x1UL << WWDG_CR_WDGA_Pos)
14630#define WWDG_CR_WDGA WWDG_CR_WDGA_Msk
14632/******************* Bit definition for WWDG_CFR register *******************/
14633#define WWDG_CFR_W_Pos (0U)
14634#define WWDG_CFR_W_Msk (0x7FUL << WWDG_CFR_W_Pos)
14635#define WWDG_CFR_W WWDG_CFR_W_Msk
14636#define WWDG_CFR_W_0 (0x01UL << WWDG_CFR_W_Pos)
14637#define WWDG_CFR_W_1 (0x02UL << WWDG_CFR_W_Pos)
14638#define WWDG_CFR_W_2 (0x04UL << WWDG_CFR_W_Pos)
14639#define WWDG_CFR_W_3 (0x08UL << WWDG_CFR_W_Pos)
14640#define WWDG_CFR_W_4 (0x10UL << WWDG_CFR_W_Pos)
14641#define WWDG_CFR_W_5 (0x20UL << WWDG_CFR_W_Pos)
14642#define WWDG_CFR_W_6 (0x40UL << WWDG_CFR_W_Pos)
14644/* Legacy defines */
14645#define WWDG_CFR_W0 WWDG_CFR_W_0
14646#define WWDG_CFR_W1 WWDG_CFR_W_1
14647#define WWDG_CFR_W2 WWDG_CFR_W_2
14648#define WWDG_CFR_W3 WWDG_CFR_W_3
14649#define WWDG_CFR_W4 WWDG_CFR_W_4
14650#define WWDG_CFR_W5 WWDG_CFR_W_5
14651#define WWDG_CFR_W6 WWDG_CFR_W_6
14652
14653#define WWDG_CFR_WDGTB_Pos (7U)
14654#define WWDG_CFR_WDGTB_Msk (0x3UL << WWDG_CFR_WDGTB_Pos)
14655#define WWDG_CFR_WDGTB WWDG_CFR_WDGTB_Msk
14656#define WWDG_CFR_WDGTB_0 (0x1UL << WWDG_CFR_WDGTB_Pos)
14657#define WWDG_CFR_WDGTB_1 (0x2UL << WWDG_CFR_WDGTB_Pos)
14659/* Legacy defines */
14660#define WWDG_CFR_WDGTB0 WWDG_CFR_WDGTB_0
14661#define WWDG_CFR_WDGTB1 WWDG_CFR_WDGTB_1
14662
14663#define WWDG_CFR_EWI_Pos (9U)
14664#define WWDG_CFR_EWI_Msk (0x1UL << WWDG_CFR_EWI_Pos)
14665#define WWDG_CFR_EWI WWDG_CFR_EWI_Msk
14667/******************* Bit definition for WWDG_SR register ********************/
14668#define WWDG_SR_EWIF_Pos (0U)
14669#define WWDG_SR_EWIF_Msk (0x1UL << WWDG_SR_EWIF_Pos)
14670#define WWDG_SR_EWIF WWDG_SR_EWIF_Msk
14684/****************************** ADC Instances *********************************/
14685#define IS_ADC_ALL_INSTANCE(INSTANCE) (((INSTANCE) == ADC1) || \
14686 ((INSTANCE) == ADC2) || \
14687 ((INSTANCE) == ADC3) || \
14688 ((INSTANCE) == ADC4))
14689
14690#define IS_ADC_MULTIMODE_MASTER_INSTANCE(INSTANCE) (((INSTANCE) == ADC1) || \
14691 ((INSTANCE) == ADC3))
14692
14693#define IS_ADC_COMMON_INSTANCE(INSTANCE) (((INSTANCE) == ADC12_COMMON) || \
14694 ((INSTANCE) == ADC34_COMMON))
14695
14696/****************************** CAN Instances *********************************/
14697#define IS_CAN_ALL_INSTANCE(INSTANCE) ((INSTANCE) == CAN)
14698
14699/****************************** COMP Instances ********************************/
14700#define IS_COMP_ALL_INSTANCE(INSTANCE) (((INSTANCE) == COMP1) || \
14701 ((INSTANCE) == COMP2) || \
14702 ((INSTANCE) == COMP3) || \
14703 ((INSTANCE) == COMP4) || \
14704 ((INSTANCE) == COMP5) || \
14705 ((INSTANCE) == COMP6) || \
14706 ((INSTANCE) == COMP7))
14707
14708#define IS_COMP_COMMON_INSTANCE(COMMON_INSTANCE) (((COMMON_INSTANCE) == COMP12_COMMON) || \
14709 ((COMMON_INSTANCE) == COMP34_COMMON) || \
14710 ((COMMON_INSTANCE) == COMP56_COMMON))
14711
14712
14713/******************** COMP Instances with window mode capability **************/
14714#define IS_COMP_WINDOWMODE_INSTANCE(INSTANCE) (((INSTANCE) == COMP2) || \
14715 ((INSTANCE) == COMP4) || \
14716 ((INSTANCE) == COMP6))
14717
14718/****************************** CRC Instances *********************************/
14719#define IS_CRC_ALL_INSTANCE(INSTANCE) ((INSTANCE) == CRC)
14720
14721/****************************** DAC Instances *********************************/
14722#define IS_DAC_ALL_INSTANCE(INSTANCE) ((INSTANCE) == DAC1)
14723
14724#define IS_DAC_CHANNEL_INSTANCE(INSTANCE, CHANNEL) \
14725 ((((INSTANCE) == DAC1) && \
14726 (((CHANNEL) == DAC_CHANNEL_1) || \
14727 ((CHANNEL) == DAC_CHANNEL_2))))
14728
14729/****************************** DMA Instances *********************************/
14730#define IS_DMA_ALL_INSTANCE(INSTANCE) (((INSTANCE) == DMA1_Channel1) || \
14731 ((INSTANCE) == DMA1_Channel2) || \
14732 ((INSTANCE) == DMA1_Channel3) || \
14733 ((INSTANCE) == DMA1_Channel4) || \
14734 ((INSTANCE) == DMA1_Channel5) || \
14735 ((INSTANCE) == DMA1_Channel6) || \
14736 ((INSTANCE) == DMA1_Channel7) || \
14737 ((INSTANCE) == DMA2_Channel1) || \
14738 ((INSTANCE) == DMA2_Channel2) || \
14739 ((INSTANCE) == DMA2_Channel3) || \
14740 ((INSTANCE) == DMA2_Channel4) || \
14741 ((INSTANCE) == DMA2_Channel5))
14742
14743/****************************** GPIO Instances ********************************/
14744#define IS_GPIO_ALL_INSTANCE(INSTANCE) (((INSTANCE) == GPIOA) || \
14745 ((INSTANCE) == GPIOB) || \
14746 ((INSTANCE) == GPIOC) || \
14747 ((INSTANCE) == GPIOD) || \
14748 ((INSTANCE) == GPIOE) || \
14749 ((INSTANCE) == GPIOF) || \
14750 ((INSTANCE) == GPIOG) || \
14751 ((INSTANCE) == GPIOH))
14752
14753#define IS_GPIO_AF_INSTANCE(INSTANCE) (((INSTANCE) == GPIOA) || \
14754 ((INSTANCE) == GPIOB) || \
14755 ((INSTANCE) == GPIOC) || \
14756 ((INSTANCE) == GPIOD) || \
14757 ((INSTANCE) == GPIOE) || \
14758 ((INSTANCE) == GPIOF) || \
14759 ((INSTANCE) == GPIOG) || \
14760 ((INSTANCE) == GPIOH))
14761
14762#define IS_GPIO_LOCK_INSTANCE(INSTANCE) (((INSTANCE) == GPIOA) || \
14763 ((INSTANCE) == GPIOB) || \
14764 ((INSTANCE) == GPIOC) || \
14765 ((INSTANCE) == GPIOD) || \
14766 ((INSTANCE) == GPIOE) || \
14767 ((INSTANCE) == GPIOF) || \
14768 ((INSTANCE) == GPIOG) || \
14769 ((INSTANCE) == GPIOH))
14770
14771/****************************** I2C Instances *********************************/
14772#define IS_I2C_ALL_INSTANCE(INSTANCE) (((INSTANCE) == I2C1) || \
14773 ((INSTANCE) == I2C2) || \
14774 ((INSTANCE) == I2C3))
14775
14776/****************** I2C Instances : wakeup capability from stop modes *********/
14777#define IS_I2C_WAKEUP_FROMSTOP_INSTANCE(INSTANCE) IS_I2C_ALL_INSTANCE(INSTANCE)
14778
14779/****************************** I2S Instances *********************************/
14780#define IS_I2S_ALL_INSTANCE(INSTANCE) (((INSTANCE) == SPI2) || \
14781 ((INSTANCE) == SPI3))
14782#define IS_I2S_EXT_ALL_INSTANCE(INSTANCE) (((INSTANCE) == I2S2ext) || \
14783 ((INSTANCE) == I2S3ext))
14784
14785/****************************** OPAMP Instances *******************************/
14786#define IS_OPAMP_ALL_INSTANCE(INSTANCE) (((INSTANCE) == OPAMP1) || \
14787 ((INSTANCE) == OPAMP2) || \
14788 ((INSTANCE) == OPAMP3) || \
14789 ((INSTANCE) == OPAMP4))
14790
14791/****************************** IWDG Instances ********************************/
14792#define IS_IWDG_ALL_INSTANCE(INSTANCE) ((INSTANCE) == IWDG)
14793
14794/****************************** RTC Instances *********************************/
14795#define IS_RTC_ALL_INSTANCE(INSTANCE) ((INSTANCE) == RTC)
14796
14797/****************************** SMBUS Instances *******************************/
14798#define IS_SMBUS_ALL_INSTANCE(INSTANCE) (((INSTANCE) == I2C1) || \
14799 ((INSTANCE) == I2C2) || \
14800 ((INSTANCE) == I2C3))
14801
14802/****************************** SPI Instances *********************************/
14803#define IS_SPI_ALL_INSTANCE(INSTANCE) (((INSTANCE) == SPI1) || \
14804 ((INSTANCE) == SPI2) || \
14805 ((INSTANCE) == SPI3) || \
14806 ((INSTANCE) == SPI4))
14807
14808/******************* TIM Instances : All supported instances ******************/
14809#define IS_TIM_INSTANCE(INSTANCE)\
14810 (((INSTANCE) == TIM1) || \
14811 ((INSTANCE) == TIM2) || \
14812 ((INSTANCE) == TIM3) || \
14813 ((INSTANCE) == TIM4) || \
14814 ((INSTANCE) == TIM6) || \
14815 ((INSTANCE) == TIM7) || \
14816 ((INSTANCE) == TIM8) || \
14817 ((INSTANCE) == TIM15) || \
14818 ((INSTANCE) == TIM16) || \
14819 ((INSTANCE) == TIM17) || \
14820 ((INSTANCE) == TIM20))
14821
14822/******************* TIM Instances : at least 1 capture/compare channel *******/
14823#define IS_TIM_CC1_INSTANCE(INSTANCE)\
14824 (((INSTANCE) == TIM1) || \
14825 ((INSTANCE) == TIM2) || \
14826 ((INSTANCE) == TIM3) || \
14827 ((INSTANCE) == TIM4) || \
14828 ((INSTANCE) == TIM8) || \
14829 ((INSTANCE) == TIM15) || \
14830 ((INSTANCE) == TIM16) || \
14831 ((INSTANCE) == TIM17) || \
14832 ((INSTANCE) == TIM20))
14833
14834/****************** TIM Instances : at least 2 capture/compare channels *******/
14835#define IS_TIM_CC2_INSTANCE(INSTANCE)\
14836 (((INSTANCE) == TIM1) || \
14837 ((INSTANCE) == TIM2) || \
14838 ((INSTANCE) == TIM3) || \
14839 ((INSTANCE) == TIM4) || \
14840 ((INSTANCE) == TIM8) || \
14841 ((INSTANCE) == TIM15) || \
14842 ((INSTANCE) == TIM20))
14843
14844/****************** TIM Instances : at least 3 capture/compare channels *******/
14845#define IS_TIM_CC3_INSTANCE(INSTANCE)\
14846 (((INSTANCE) == TIM1) || \
14847 ((INSTANCE) == TIM2) || \
14848 ((INSTANCE) == TIM3) || \
14849 ((INSTANCE) == TIM4) || \
14850 ((INSTANCE) == TIM8) || \
14851 ((INSTANCE) == TIM20))
14852
14853/****************** TIM Instances : at least 4 capture/compare channels *******/
14854#define IS_TIM_CC4_INSTANCE(INSTANCE)\
14855 (((INSTANCE) == TIM1) || \
14856 ((INSTANCE) == TIM2) || \
14857 ((INSTANCE) == TIM3) || \
14858 ((INSTANCE) == TIM4) || \
14859 ((INSTANCE) == TIM8) || \
14860 ((INSTANCE) == TIM20))
14861
14862/****************** TIM Instances : at least 5 capture/compare channels *******/
14863#define IS_TIM_CC5_INSTANCE(INSTANCE)\
14864 (((INSTANCE) == TIM1) || \
14865 ((INSTANCE) == TIM8) || \
14866 ((INSTANCE) == TIM20))
14867
14868/****************** TIM Instances : at least 6 capture/compare channels *******/
14869#define IS_TIM_CC6_INSTANCE(INSTANCE)\
14870 (((INSTANCE) == TIM1) || \
14871 ((INSTANCE) == TIM8) || \
14872 ((INSTANCE) == TIM20))
14873
14874/************************** TIM Instances : Advanced-control timers ***********/
14875
14876/****************** TIM Instances : Advanced timer instances *******************/
14877#define IS_TIM_ADVANCED_INSTANCE(INSTANCE)\
14878 (((INSTANCE) == TIM1) || \
14879 ((INSTANCE) == TIM8) || \
14880 ((INSTANCE) == TIM20))
14881
14882/****************** TIM Instances : supporting clock selection ****************/
14883#define IS_TIM_CLOCK_SELECT_INSTANCE(INSTANCE)\
14884 (((INSTANCE) == TIM1) || \
14885 ((INSTANCE) == TIM2) || \
14886 ((INSTANCE) == TIM3) || \
14887 ((INSTANCE) == TIM4) || \
14888 ((INSTANCE) == TIM8) || \
14889 ((INSTANCE) == TIM15) || \
14890 ((INSTANCE) == TIM20))
14891
14892/****************** TIM Instances : supporting external clock mode 1 for ETRF input */
14893#define IS_TIM_CLOCKSOURCE_ETRMODE1_INSTANCE(INSTANCE)\
14894 (((INSTANCE) == TIM1) || \
14895 ((INSTANCE) == TIM2) || \
14896 ((INSTANCE) == TIM3) || \
14897 ((INSTANCE) == TIM4) || \
14898 ((INSTANCE) == TIM8) || \
14899 ((INSTANCE) == TIM20))
14900
14901/****************** TIM Instances : supporting external clock mode 2 **********/
14902#define IS_TIM_CLOCKSOURCE_ETRMODE2_INSTANCE(INSTANCE)\
14903 (((INSTANCE) == TIM1) || \
14904 ((INSTANCE) == TIM2) || \
14905 ((INSTANCE) == TIM3) || \
14906 ((INSTANCE) == TIM4) || \
14907 ((INSTANCE) == TIM8) || \
14908 ((INSTANCE) == TIM20))
14909
14910/****************** TIM Instances : supporting external clock mode 1 for TIX inputs*/
14911#define IS_TIM_CLOCKSOURCE_TIX_INSTANCE(INSTANCE)\
14912 (((INSTANCE) == TIM1) || \
14913 ((INSTANCE) == TIM2) || \
14914 ((INSTANCE) == TIM3) || \
14915 ((INSTANCE) == TIM4) || \
14916 ((INSTANCE) == TIM8) || \
14917 ((INSTANCE) == TIM15) || \
14918 ((INSTANCE) == TIM20))
14919
14920/****************** TIM Instances : supporting internal trigger inputs(ITRX) *******/
14921#define IS_TIM_CLOCKSOURCE_ITRX_INSTANCE(INSTANCE)\
14922 (((INSTANCE) == TIM1) || \
14923 ((INSTANCE) == TIM2) || \
14924 ((INSTANCE) == TIM3) || \
14925 ((INSTANCE) == TIM4) || \
14926 ((INSTANCE) == TIM8) || \
14927 ((INSTANCE) == TIM15) || \
14928 ((INSTANCE) == TIM20))
14929
14930/****************** TIM Instances : supporting OCxREF clear *******************/
14931#define IS_TIM_OCXREF_CLEAR_INSTANCE(INSTANCE)\
14932 (((INSTANCE) == TIM1) || \
14933 ((INSTANCE) == TIM2) || \
14934 ((INSTANCE) == TIM3) || \
14935 ((INSTANCE) == TIM4) || \
14936 ((INSTANCE) == TIM8) || \
14937 ((INSTANCE) == TIM20))
14938
14939/****************** TIM Instances : supporting encoder interface **************/
14940#define IS_TIM_ENCODER_INTERFACE_INSTANCE(INSTANCE)\
14941 (((INSTANCE) == TIM1) || \
14942 ((INSTANCE) == TIM2) || \
14943 ((INSTANCE) == TIM3) || \
14944 ((INSTANCE) == TIM4) || \
14945 ((INSTANCE) == TIM8) || \
14946 ((INSTANCE) == TIM20))
14947
14948/****************** TIM Instances : supporting Hall interface *****************/
14949#define IS_TIM_HALL_SENSOR_INTERFACE_INSTANCE(INSTANCE)\
14950 (((INSTANCE) == TIM1) || \
14951 ((INSTANCE) == TIM8) || \
14952 ((INSTANCE) == TIM20))
14953
14954/**************** TIM Instances : external trigger input available ************/
14955#define IS_TIM_ETR_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
14956 ((INSTANCE) == TIM2) || \
14957 ((INSTANCE) == TIM3) || \
14958 ((INSTANCE) == TIM4) || \
14959 ((INSTANCE) == TIM8) || \
14960 ((INSTANCE) == TIM20))
14961
14962/****************** TIM Instances : supporting input XOR function *************/
14963#define IS_TIM_XOR_INSTANCE(INSTANCE)\
14964 (((INSTANCE) == TIM1) || \
14965 ((INSTANCE) == TIM2) || \
14966 ((INSTANCE) == TIM3) || \
14967 ((INSTANCE) == TIM4) || \
14968 ((INSTANCE) == TIM8) || \
14969 ((INSTANCE) == TIM15) || \
14970 ((INSTANCE) == TIM20))
14971
14972/****************** TIM Instances : supporting master mode ********************/
14973#define IS_TIM_MASTER_INSTANCE(INSTANCE)\
14974 (((INSTANCE) == TIM1) || \
14975 ((INSTANCE) == TIM2) || \
14976 ((INSTANCE) == TIM3) || \
14977 ((INSTANCE) == TIM4) || \
14978 ((INSTANCE) == TIM6) || \
14979 ((INSTANCE) == TIM7) || \
14980 ((INSTANCE) == TIM8) || \
14981 ((INSTANCE) == TIM15) || \
14982 ((INSTANCE) == TIM20))
14983
14984/****************** TIM Instances : supporting slave mode *********************/
14985#define IS_TIM_SLAVE_INSTANCE(INSTANCE)\
14986 (((INSTANCE) == TIM1) || \
14987 ((INSTANCE) == TIM2) || \
14988 ((INSTANCE) == TIM3) || \
14989 ((INSTANCE) == TIM4) || \
14990 ((INSTANCE) == TIM8) || \
14991 ((INSTANCE) == TIM15) || \
14992 ((INSTANCE) == TIM20))
14993
14994/****************** TIM Instances : supporting 32 bits counter ****************/
14995#define IS_TIM_32B_COUNTER_INSTANCE(INSTANCE)\
14996 ((INSTANCE) == TIM2)
14997
14998/****************** TIM Instances : supporting DMA burst **********************/
14999#define IS_TIM_DMABURST_INSTANCE(INSTANCE)\
15000 (((INSTANCE) == TIM1) || \
15001 ((INSTANCE) == TIM2) || \
15002 ((INSTANCE) == TIM3) || \
15003 ((INSTANCE) == TIM4) || \
15004 ((INSTANCE) == TIM8) || \
15005 ((INSTANCE) == TIM15) || \
15006 ((INSTANCE) == TIM16) || \
15007 ((INSTANCE) == TIM17) || \
15008 ((INSTANCE) == TIM20))
15009
15010/****************** TIM Instances : supporting the break function *************/
15011#define IS_TIM_BREAK_INSTANCE(INSTANCE)\
15012 (((INSTANCE) == TIM1) || \
15013 ((INSTANCE) == TIM8) || \
15014 ((INSTANCE) == TIM15) || \
15015 ((INSTANCE) == TIM16) || \
15016 ((INSTANCE) == TIM17) || \
15017 ((INSTANCE) == TIM20))
15018
15019/****************** TIM Instances : supporting input/output channel(s) ********/
15020#define IS_TIM_CCX_INSTANCE(INSTANCE, CHANNEL) \
15021 ((((INSTANCE) == TIM1) && \
15022 (((CHANNEL) == TIM_CHANNEL_1) || \
15023 ((CHANNEL) == TIM_CHANNEL_2) || \
15024 ((CHANNEL) == TIM_CHANNEL_3) || \
15025 ((CHANNEL) == TIM_CHANNEL_4) || \
15026 ((CHANNEL) == TIM_CHANNEL_5) || \
15027 ((CHANNEL) == TIM_CHANNEL_6))) \
15028 || \
15029 (((INSTANCE) == TIM2) && \
15030 (((CHANNEL) == TIM_CHANNEL_1) || \
15031 ((CHANNEL) == TIM_CHANNEL_2) || \
15032 ((CHANNEL) == TIM_CHANNEL_3) || \
15033 ((CHANNEL) == TIM_CHANNEL_4))) \
15034 || \
15035 (((INSTANCE) == TIM3) && \
15036 (((CHANNEL) == TIM_CHANNEL_1) || \
15037 ((CHANNEL) == TIM_CHANNEL_2) || \
15038 ((CHANNEL) == TIM_CHANNEL_3) || \
15039 ((CHANNEL) == TIM_CHANNEL_4))) \
15040 || \
15041 (((INSTANCE) == TIM4) && \
15042 (((CHANNEL) == TIM_CHANNEL_1) || \
15043 ((CHANNEL) == TIM_CHANNEL_2) || \
15044 ((CHANNEL) == TIM_CHANNEL_3) || \
15045 ((CHANNEL) == TIM_CHANNEL_4))) \
15046 || \
15047 (((INSTANCE) == TIM8) && \
15048 (((CHANNEL) == TIM_CHANNEL_1) || \
15049 ((CHANNEL) == TIM_CHANNEL_2) || \
15050 ((CHANNEL) == TIM_CHANNEL_3) || \
15051 ((CHANNEL) == TIM_CHANNEL_4) || \
15052 ((CHANNEL) == TIM_CHANNEL_5) || \
15053 ((CHANNEL) == TIM_CHANNEL_6))) \
15054 || \
15055 (((INSTANCE) == TIM15) && \
15056 (((CHANNEL) == TIM_CHANNEL_1) || \
15057 ((CHANNEL) == TIM_CHANNEL_2))) \
15058 || \
15059 (((INSTANCE) == TIM16) && \
15060 (((CHANNEL) == TIM_CHANNEL_1))) \
15061 || \
15062 (((INSTANCE) == TIM17) && \
15063 (((CHANNEL) == TIM_CHANNEL_1))) \
15064 || \
15065 (((INSTANCE) == TIM20) && \
15066 (((CHANNEL) == TIM_CHANNEL_1) || \
15067 ((CHANNEL) == TIM_CHANNEL_2) || \
15068 ((CHANNEL) == TIM_CHANNEL_3) || \
15069 ((CHANNEL) == TIM_CHANNEL_4) || \
15070 ((CHANNEL) == TIM_CHANNEL_5) || \
15071 ((CHANNEL) == TIM_CHANNEL_6))))
15072
15073/****************** TIM Instances : supporting complementary output(s) ********/
15074#define IS_TIM_CCXN_INSTANCE(INSTANCE, CHANNEL) \
15075 ((((INSTANCE) == TIM1) && \
15076 (((CHANNEL) == TIM_CHANNEL_1) || \
15077 ((CHANNEL) == TIM_CHANNEL_2) || \
15078 ((CHANNEL) == TIM_CHANNEL_3))) \
15079 || \
15080 (((INSTANCE) == TIM8) && \
15081 (((CHANNEL) == TIM_CHANNEL_1) || \
15082 ((CHANNEL) == TIM_CHANNEL_2) || \
15083 ((CHANNEL) == TIM_CHANNEL_3))) \
15084 || \
15085 (((INSTANCE) == TIM15) && \
15086 ((CHANNEL) == TIM_CHANNEL_1)) \
15087 || \
15088 (((INSTANCE) == TIM16) && \
15089 ((CHANNEL) == TIM_CHANNEL_1)) \
15090 || \
15091 (((INSTANCE) == TIM17) && \
15092 ((CHANNEL) == TIM_CHANNEL_1)) \
15093 || \
15094 (((INSTANCE) == TIM20) && \
15095 (((CHANNEL) == TIM_CHANNEL_1) || \
15096 ((CHANNEL) == TIM_CHANNEL_2) || \
15097 ((CHANNEL) == TIM_CHANNEL_3))))
15098
15099/****************** TIM Instances : supporting counting mode selection ********/
15100#define IS_TIM_COUNTER_MODE_SELECT_INSTANCE(INSTANCE)\
15101 (((INSTANCE) == TIM1) || \
15102 ((INSTANCE) == TIM2) || \
15103 ((INSTANCE) == TIM3) || \
15104 ((INSTANCE) == TIM4) || \
15105 ((INSTANCE) == TIM8) || \
15106 ((INSTANCE) == TIM20))
15107
15108/****************** TIM Instances : supporting repetition counter *************/
15109#define IS_TIM_REPETITION_COUNTER_INSTANCE(INSTANCE)\
15110 (((INSTANCE) == TIM1) || \
15111 ((INSTANCE) == TIM8) || \
15112 ((INSTANCE) == TIM15) || \
15113 ((INSTANCE) == TIM16) || \
15114 ((INSTANCE) == TIM17) || \
15115 ((INSTANCE) == TIM20))
15116
15117/****************** TIM Instances : supporting clock division *****************/
15118#define IS_TIM_CLOCK_DIVISION_INSTANCE(INSTANCE)\
15119 (((INSTANCE) == TIM1) || \
15120 ((INSTANCE) == TIM2) || \
15121 ((INSTANCE) == TIM3) || \
15122 ((INSTANCE) == TIM4) || \
15123 ((INSTANCE) == TIM8) || \
15124 ((INSTANCE) == TIM15) || \
15125 ((INSTANCE) == TIM16) || \
15126 ((INSTANCE) == TIM17) || \
15127 ((INSTANCE) == TIM20))
15128
15129/****************** TIM Instances : supporting 2 break inputs *****************/
15130#define IS_TIM_BKIN2_INSTANCE(INSTANCE)\
15131 (((INSTANCE) == TIM1) || \
15132 ((INSTANCE) == TIM8) || \
15133 ((INSTANCE) == TIM20))
15134
15135/****************** TIM Instances : supporting ADC triggering through TRGO2 ***/
15136#define IS_TIM_TRGO2_INSTANCE(INSTANCE)\
15137 (((INSTANCE) == TIM1) || \
15138 ((INSTANCE) == TIM8) || \
15139 ((INSTANCE) == TIM20))
15140
15141/****************** TIM Instances : supporting DMA generation on Update events*/
15142#define IS_TIM_DMA_INSTANCE(INSTANCE)\
15143 (((INSTANCE) == TIM1) || \
15144 ((INSTANCE) == TIM2) || \
15145 ((INSTANCE) == TIM3) || \
15146 ((INSTANCE) == TIM4) || \
15147 ((INSTANCE) == TIM6) || \
15148 ((INSTANCE) == TIM7) || \
15149 ((INSTANCE) == TIM8) || \
15150 ((INSTANCE) == TIM15) || \
15151 ((INSTANCE) == TIM16) || \
15152 ((INSTANCE) == TIM17) || \
15153 ((INSTANCE) == TIM20))
15154
15155/****************** TIM Instances : supporting DMA generation on Capture/Compare events */
15156#define IS_TIM_DMA_CC_INSTANCE(INSTANCE)\
15157 (((INSTANCE) == TIM1) || \
15158 ((INSTANCE) == TIM2) || \
15159 ((INSTANCE) == TIM3) || \
15160 ((INSTANCE) == TIM4) || \
15161 ((INSTANCE) == TIM8) || \
15162 ((INSTANCE) == TIM15) || \
15163 ((INSTANCE) == TIM16) || \
15164 ((INSTANCE) == TIM17) || \
15165 ((INSTANCE) == TIM20))
15166
15167/****************** TIM Instances : supporting commutation event generation ***/
15168#define IS_TIM_COMMUTATION_EVENT_INSTANCE(INSTANCE)\
15169 (((INSTANCE) == TIM1) || \
15170 ((INSTANCE) == TIM8) || \
15171 ((INSTANCE) == TIM15) || \
15172 ((INSTANCE) == TIM16) || \
15173 ((INSTANCE) == TIM17) || \
15174 ((INSTANCE) == TIM20))
15175
15176/****************** TIM Instances : supporting remapping capability ***********/
15177#define IS_TIM_REMAP_INSTANCE(INSTANCE)\
15178 (((INSTANCE) == TIM1) || \
15179 ((INSTANCE) == TIM8) || \
15180 ((INSTANCE) == TIM16) || \
15181 ((INSTANCE) == TIM20))
15182
15183/****************** TIM Instances : supporting combined 3-phase PWM mode ******/
15184#define IS_TIM_COMBINED3PHASEPWM_INSTANCE(INSTANCE) \
15185 (((INSTANCE) == TIM1) || \
15186 ((INSTANCE) == TIM8) || \
15187 ((INSTANCE) == TIM20))
15188
15189/****************************** TSC Instances *********************************/
15190#define IS_TSC_ALL_INSTANCE(INSTANCE) ((INSTANCE) == TSC)
15191
15192/******************** USART Instances : Synchronous mode **********************/
15193#define IS_USART_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
15194 ((INSTANCE) == USART2) || \
15195 ((INSTANCE) == USART3))
15196
15197/****************** USART Instances : Auto Baud Rate detection ****************/
15198#define IS_USART_AUTOBAUDRATE_DETECTION_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
15199 ((INSTANCE) == USART2) || \
15200 ((INSTANCE) == USART3))
15201
15202/******************** UART Instances : Asynchronous mode **********************/
15203#define IS_UART_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
15204 ((INSTANCE) == USART2) || \
15205 ((INSTANCE) == USART3) || \
15206 ((INSTANCE) == UART4) || \
15207 ((INSTANCE) == UART5))
15208
15209/******************** UART Instances : Half-Duplex mode **********************/
15210#define IS_UART_HALFDUPLEX_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
15211 ((INSTANCE) == USART2) || \
15212 ((INSTANCE) == USART3) || \
15213 ((INSTANCE) == UART4) || \
15214 ((INSTANCE) == UART5))
15215
15216/******************** UART Instances : LIN mode **********************/
15217#define IS_UART_LIN_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
15218 ((INSTANCE) == USART2) || \
15219 ((INSTANCE) == USART3) || \
15220 ((INSTANCE) == UART4) || \
15221 ((INSTANCE) == UART5))
15222
15223/******************** UART Instances : Wake-up from Stop mode **********************/
15224#define IS_UART_WAKEUP_FROMSTOP_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
15225 ((INSTANCE) == USART2) || \
15226 ((INSTANCE) == USART3) || \
15227 ((INSTANCE) == UART4) || \
15228 ((INSTANCE) == UART5))
15229
15230/****************** UART Instances : Hardware Flow control ********************/
15231#define IS_UART_HWFLOW_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
15232 ((INSTANCE) == USART2) || \
15233 ((INSTANCE) == USART3))
15234
15235/****************** UART Instances : Auto Baud Rate detection *****************/
15236#define IS_UART_AUTOBAUDRATE_DETECTION_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
15237 ((INSTANCE) == USART2) || \
15238 ((INSTANCE) == USART3))
15239
15240/****************** UART Instances : Driver Enable ****************************/
15241#define IS_UART_DRIVER_ENABLE_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
15242 ((INSTANCE) == USART2) || \
15243 ((INSTANCE) == USART3))
15244
15245/********************* UART Instances : Smard card mode ***********************/
15246#define IS_SMARTCARD_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
15247 ((INSTANCE) == USART2) || \
15248 ((INSTANCE) == USART3))
15249
15250/*********************** UART Instances : IRDA mode ***************************/
15251#define IS_IRDA_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
15252 ((INSTANCE) == USART2) || \
15253 ((INSTANCE) == USART3) || \
15254 ((INSTANCE) == UART4) || \
15255 ((INSTANCE) == UART5))
15256
15257/******************** UART Instances : Support of continuous communication using DMA ****/
15258#define IS_UART_DMA_INSTANCE(INSTANCE) (1)
15259
15260/****************************** USB Instances *********************************/
15261#define IS_PCD_ALL_INSTANCE(INSTANCE) ((INSTANCE) == USB)
15262
15263/****************************** WWDG Instances ********************************/
15264#define IS_WWDG_ALL_INSTANCE(INSTANCE) ((INSTANCE) == WWDG)
15265
15271/******************************************************************************/
15272/* For a painless codes migration between the STM32F3xx device product */
15273/* lines, the aliases defined below are put in place to overcome the */
15274/* differences in the interrupt handlers and IRQn definitions. */
15275/* No need to update developed interrupt code when moving across */
15276/* product lines within the same STM32F3 Family */
15277/******************************************************************************/
15278
15279/* Aliases for __IRQn */
15280#define ADC1_IRQn ADC1_2_IRQn
15281#define SDADC1_IRQn ADC4_IRQn
15282#define COMP_IRQn COMP1_2_3_IRQn
15283#define COMP2_IRQn COMP1_2_3_IRQn
15284#define COMP1_2_IRQn COMP1_2_3_IRQn
15285#define COMP4_6_IRQn COMP4_5_6_IRQn
15286#define HRTIM1_FLT_IRQn I2C3_ER_IRQn
15287#define HRTIM1_TIME_IRQn I2C3_EV_IRQn
15288#define TIM15_IRQn TIM1_BRK_TIM15_IRQn
15289#define TIM18_DAC2_IRQn TIM1_CC_IRQn
15290#define TIM17_IRQn TIM1_TRG_COM_TIM17_IRQn
15291#define TIM16_IRQn TIM1_UP_TIM16_IRQn
15292#define TIM19_IRQn TIM20_UP_IRQn
15293#define TIM6_DAC1_IRQn TIM6_DAC_IRQn
15294#define TIM7_DAC2_IRQn TIM7_IRQn
15295#define TIM12_IRQn TIM8_BRK_IRQn
15296#define TIM14_IRQn TIM8_TRG_COM_IRQn
15297#define TIM13_IRQn TIM8_UP_IRQn
15298#define CEC_IRQn USBWakeUp_IRQn
15299#define USBWakeUp_IRQn USBWakeUp_RMP_IRQn
15300#define CAN_TX_IRQn USB_HP_CAN_TX_IRQn
15301#define CAN_RX0_IRQn USB_LP_CAN_RX0_IRQn
15302
15303
15304/* Aliases for __IRQHandler */
15305#define ADC1_IRQHandler ADC1_2_IRQHandler
15306#define SDADC1_IRQHandler ADC4_IRQHandler
15307#define COMP_IRQHandler COMP1_2_3_IRQHandler
15308#define COMP2_IRQHandler COMP1_2_3_IRQHandler
15309#define COMP1_2_IRQHandler COMP1_2_3_IRQHandler
15310#define COMP4_6_IRQHandler COMP4_5_6_IRQHandler
15311#define HRTIM1_FLT_IRQHandler I2C3_ER_IRQHandler
15312#define HRTIM1_TIME_IRQHandler I2C3_EV_IRQHandler
15313#define TIM15_IRQHandler TIM1_BRK_TIM15_IRQHandler
15314#define TIM18_DAC2_IRQHandler TIM1_CC_IRQHandler
15315#define TIM17_IRQHandler TIM1_TRG_COM_TIM17_IRQHandler
15316#define TIM16_IRQHandler TIM1_UP_TIM16_IRQHandler
15317#define TIM19_IRQHandler TIM20_UP_IRQHandler
15318#define TIM6_DAC1_IRQHandler TIM6_DAC_IRQHandler
15319#define TIM7_DAC2_IRQHandler TIM7_IRQHandler
15320#define TIM12_IRQHandler TIM8_BRK_IRQHandler
15321#define TIM14_IRQHandler TIM8_TRG_COM_IRQHandler
15322#define TIM13_IRQHandler TIM8_UP_IRQHandler
15323#define CEC_IRQHandler USBWakeUp_IRQHandler
15324#define USBWakeUp_IRQHandler USBWakeUp_RMP_IRQHandler
15325#define CAN_TX_IRQHandler USB_HP_CAN_TX_IRQHandler
15326#define CAN_RX0_IRQHandler USB_LP_CAN_RX0_IRQHandler
15327
15328
15329#ifdef __cplusplus
15330}
15331#endif /* __cplusplus */
15332
15333#endif /* __STM32F303xE_H */
15334
__IO
#define __IO
Definition: core_armv8mbl.h:196
core_cm4.h
CMSIS Cortex-M4 Core Peripheral Access Layer Header File.
IRQn_Type
IRQn_Type
STM32F303xE devices Interrupt Number Definition, according to the selected device in Library_configur...
Definition: stm32f303xe.h:66
TIM8_TRG_COM_IRQn
@ TIM8_TRG_COM_IRQn
Definition: stm32f303xe.h:123
COMP1_2_3_IRQn
@ COMP1_2_3_IRQn
Definition: stm32f303xe.h:138
PendSV_IRQn
@ PendSV_IRQn
Definition: stm32f303xe.h:75
USBWakeUp_RMP_IRQn
@ USBWakeUp_RMP_IRQn
Definition: stm32f303xe.h:145
DMA2_Channel4_IRQn
@ DMA2_Channel4_IRQn
Definition: stm32f303xe.h:135
RTC_WKUP_IRQn
@ RTC_WKUP_IRQn
Definition: stm32f303xe.h:81
ADC1_2_IRQn
@ ADC1_2_IRQn
Definition: stm32f303xe.h:96
DMA1_Channel2_IRQn
@ DMA1_Channel2_IRQn
Definition: stm32f303xe.h:90
ADC4_IRQn
@ ADC4_IRQn
Definition: stm32f303xe.h:137
I2C1_ER_IRQn
@ I2C1_ER_IRQn
Definition: stm32f303xe.h:110
I2C2_EV_IRQn
@ I2C2_EV_IRQn
Definition: stm32f303xe.h:111
MemoryManagement_IRQn
@ MemoryManagement_IRQn
Definition: stm32f303xe.h:70
TIM4_IRQn
@ TIM4_IRQn
Definition: stm32f303xe.h:108
TIM2_IRQn
@ TIM2_IRQn
Definition: stm32f303xe.h:106
USB_LP_CAN_RX0_IRQn
@ USB_LP_CAN_RX0_IRQn
Definition: stm32f303xe.h:98
DMA1_Channel1_IRQn
@ DMA1_Channel1_IRQn
Definition: stm32f303xe.h:89
DMA1_Channel3_IRQn
@ DMA1_Channel3_IRQn
Definition: stm32f303xe.h:91
USART2_IRQn
@ USART2_IRQn
Definition: stm32f303xe.h:116
USB_LP_IRQn
@ USB_LP_IRQn
Definition: stm32f303xe.h:144
SVCall_IRQn
@ SVCall_IRQn
Definition: stm32f303xe.h:73
SPI3_IRQn
@ SPI3_IRQn
Definition: stm32f303xe.h:127
SPI2_IRQn
@ SPI2_IRQn
Definition: stm32f303xe.h:114
TIM7_IRQn
@ TIM7_IRQn
Definition: stm32f303xe.h:131
RCC_IRQn
@ RCC_IRQn
Definition: stm32f303xe.h:83
ADC3_IRQn
@ ADC3_IRQn
Definition: stm32f303xe.h:125
TIM1_TRG_COM_TIM17_IRQn
@ TIM1_TRG_COM_TIM17_IRQn
Definition: stm32f303xe.h:104
TIM6_DAC_IRQn
@ TIM6_DAC_IRQn
Definition: stm32f303xe.h:130
I2C2_ER_IRQn
@ I2C2_ER_IRQn
Definition: stm32f303xe.h:112
TIM8_CC_IRQn
@ TIM8_CC_IRQn
Definition: stm32f303xe.h:124
DMA1_Channel7_IRQn
@ DMA1_Channel7_IRQn
Definition: stm32f303xe.h:95
UsageFault_IRQn
@ UsageFault_IRQn
Definition: stm32f303xe.h:72
SysTick_IRQn
@ SysTick_IRQn
Definition: stm32f303xe.h:76
I2C3_ER_IRQn
@ I2C3_ER_IRQn
Definition: stm32f303xe.h:142
TIM20_BRK_IRQn
@ TIM20_BRK_IRQn
Definition: stm32f303xe.h:146
I2C3_EV_IRQn
@ I2C3_EV_IRQn
Definition: stm32f303xe.h:141
BusFault_IRQn
@ BusFault_IRQn
Definition: stm32f303xe.h:71
TIM1_BRK_TIM15_IRQn
@ TIM1_BRK_TIM15_IRQn
Definition: stm32f303xe.h:102
DebugMonitor_IRQn
@ DebugMonitor_IRQn
Definition: stm32f303xe.h:74
FLASH_IRQn
@ FLASH_IRQn
Definition: stm32f303xe.h:82
WWDG_IRQn
@ WWDG_IRQn
Definition: stm32f303xe.h:78
I2C1_EV_IRQn
@ I2C1_EV_IRQn
Definition: stm32f303xe.h:109
TIM3_IRQn
@ TIM3_IRQn
Definition: stm32f303xe.h:107
CAN_RX1_IRQn
@ CAN_RX1_IRQn
Definition: stm32f303xe.h:99
EXTI15_10_IRQn
@ EXTI15_10_IRQn
Definition: stm32f303xe.h:118
USB_HP_IRQn
@ USB_HP_IRQn
Definition: stm32f303xe.h:143
SPI4_IRQn
@ SPI4_IRQn
Definition: stm32f303xe.h:151
EXTI9_5_IRQn
@ EXTI9_5_IRQn
Definition: stm32f303xe.h:101
FPU_IRQn
@ FPU_IRQn
Definition: stm32f303xe.h:150
TIM20_CC_IRQn
@ TIM20_CC_IRQn
Definition: stm32f303xe.h:149
DMA1_Channel6_IRQn
@ DMA1_Channel6_IRQn
Definition: stm32f303xe.h:94
SPI1_IRQn
@ SPI1_IRQn
Definition: stm32f303xe.h:113
PVD_IRQn
@ PVD_IRQn
Definition: stm32f303xe.h:79
HardFault_IRQn
@ HardFault_IRQn
Definition: stm32f303xe.h:69
FMC_IRQn
@ FMC_IRQn
Definition: stm32f303xe.h:126
EXTI0_IRQn
@ EXTI0_IRQn
Definition: stm32f303xe.h:84
EXTI4_IRQn
@ EXTI4_IRQn
Definition: stm32f303xe.h:88
DMA2_Channel1_IRQn
@ DMA2_Channel1_IRQn
Definition: stm32f303xe.h:132
DMA1_Channel5_IRQn
@ DMA1_Channel5_IRQn
Definition: stm32f303xe.h:93
TAMP_STAMP_IRQn
@ TAMP_STAMP_IRQn
Definition: stm32f303xe.h:80
TIM8_BRK_IRQn
@ TIM8_BRK_IRQn
Definition: stm32f303xe.h:121
DMA2_Channel5_IRQn
@ DMA2_Channel5_IRQn
Definition: stm32f303xe.h:136
UART5_IRQn
@ UART5_IRQn
Definition: stm32f303xe.h:129
DMA2_Channel2_IRQn
@ DMA2_Channel2_IRQn
Definition: stm32f303xe.h:133
COMP7_IRQn
@ COMP7_IRQn
Definition: stm32f303xe.h:140
TIM1_UP_TIM16_IRQn
@ TIM1_UP_TIM16_IRQn
Definition: stm32f303xe.h:103
USART1_IRQn
@ USART1_IRQn
Definition: stm32f303xe.h:115
DMA2_Channel3_IRQn
@ DMA2_Channel3_IRQn
Definition: stm32f303xe.h:134
USB_HP_CAN_TX_IRQn
@ USB_HP_CAN_TX_IRQn
Definition: stm32f303xe.h:97
EXTI3_IRQn
@ EXTI3_IRQn
Definition: stm32f303xe.h:87
NonMaskableInt_IRQn
@ NonMaskableInt_IRQn
Definition: stm32f303xe.h:68
UART4_IRQn
@ UART4_IRQn
Definition: stm32f303xe.h:128
TIM20_TRG_COM_IRQn
@ TIM20_TRG_COM_IRQn
Definition: stm32f303xe.h:148
DMA1_Channel4_IRQn
@ DMA1_Channel4_IRQn
Definition: stm32f303xe.h:92
EXTI1_IRQn
@ EXTI1_IRQn
Definition: stm32f303xe.h:85
EXTI2_TSC_IRQn
@ EXTI2_TSC_IRQn
Definition: stm32f303xe.h:86
TIM20_UP_IRQn
@ TIM20_UP_IRQn
Definition: stm32f303xe.h:147
TIM8_UP_IRQn
@ TIM8_UP_IRQn
Definition: stm32f303xe.h:122
TIM1_CC_IRQn
@ TIM1_CC_IRQn
Definition: stm32f303xe.h:105
COMP4_5_6_IRQn
@ COMP4_5_6_IRQn
Definition: stm32f303xe.h:139
CAN_SCE_IRQn
@ CAN_SCE_IRQn
Definition: stm32f303xe.h:100
USART3_IRQn
@ USART3_IRQn
Definition: stm32f303xe.h:117
RTC_Alarm_IRQn
@ RTC_Alarm_IRQn
Definition: stm32f303xe.h:119
USBWakeUp_IRQn
#define USBWakeUp_IRQn
Definition: stm32f303xe.h:15299
ADC_Common_TypeDef
Definition: stm32f303xe.h:213
ADC_Common_TypeDef::RESERVED
uint32_t RESERVED
Definition: stm32f303xe.h:215
ADC_Common_TypeDef::CDR
__IO uint32_t CDR
Definition: stm32f303xe.h:217
ADC_Common_TypeDef::CSR
__IO uint32_t CSR
Definition: stm32f303xe.h:214
ADC_Common_TypeDef::CCR
__IO uint32_t CCR
Definition: stm32f303xe.h:216
ADC_TypeDef
Analog to Digital Converter.
Definition: stm32f303xe.h:171
ADC_TypeDef::SQR1
__IO uint32_t SQR1
Definition: stm32f303xe.h:184
ADC_TypeDef::AWD2CR
__IO uint32_t AWD2CR
Definition: stm32f303xe.h:203
ADC_TypeDef::TR1
__IO uint32_t TR1
Definition: stm32f303xe.h:180
ADC_TypeDef::RESERVED4
uint32_t RESERVED4
Definition: stm32f303xe.h:190
ADC_TypeDef::RESERVED8
uint32_t RESERVED8
Definition: stm32f303xe.h:205
ADC_TypeDef::OFR3
__IO uint32_t OFR3
Definition: stm32f303xe.h:195
ADC_TypeDef::OFR4
__IO uint32_t OFR4
Definition: stm32f303xe.h:196
ADC_TypeDef::RESERVED2
uint32_t RESERVED2
Definition: stm32f303xe.h:183
ADC_TypeDef::RESERVED9
uint32_t RESERVED9
Definition: stm32f303xe.h:206
ADC_TypeDef::AWD3CR
__IO uint32_t AWD3CR
Definition: stm32f303xe.h:204
ADC_TypeDef::JDR3
__IO uint32_t JDR3
Definition: stm32f303xe.h:200
ADC_TypeDef::CFGR
__IO uint32_t CFGR
Definition: stm32f303xe.h:175
ADC_TypeDef::SQR3
__IO uint32_t SQR3
Definition: stm32f303xe.h:186
ADC_TypeDef::JSQR
__IO uint32_t JSQR
Definition: stm32f303xe.h:191
ADC_TypeDef::RESERVED1
uint32_t RESERVED1
Definition: stm32f303xe.h:179
ADC_TypeDef::CR
__IO uint32_t CR
Definition: stm32f303xe.h:174
ADC_TypeDef::CALFACT
__IO uint32_t CALFACT
Definition: stm32f303xe.h:208
ADC_TypeDef::SQR2
__IO uint32_t SQR2
Definition: stm32f303xe.h:185
ADC_TypeDef::DIFSEL
__IO uint32_t DIFSEL
Definition: stm32f303xe.h:207
ADC_TypeDef::SMPR1
__IO uint32_t SMPR1
Definition: stm32f303xe.h:177
ADC_TypeDef::IER
__IO uint32_t IER
Definition: stm32f303xe.h:173
ADC_TypeDef::DR
__IO uint32_t DR
Definition: stm32f303xe.h:188
ADC_TypeDef::JDR2
__IO uint32_t JDR2
Definition: stm32f303xe.h:199
ADC_TypeDef::OFR1
__IO uint32_t OFR1
Definition: stm32f303xe.h:193
ADC_TypeDef::SMPR2
__IO uint32_t SMPR2
Definition: stm32f303xe.h:178
ADC_TypeDef::TR3
__IO uint32_t TR3
Definition: stm32f303xe.h:182
ADC_TypeDef::JDR1
__IO uint32_t JDR1
Definition: stm32f303xe.h:198
ADC_TypeDef::SQR4
__IO uint32_t SQR4
Definition: stm32f303xe.h:187
ADC_TypeDef::JDR4
__IO uint32_t JDR4
Definition: stm32f303xe.h:201
ADC_TypeDef::RESERVED3
uint32_t RESERVED3
Definition: stm32f303xe.h:189
ADC_TypeDef::ISR
__IO uint32_t ISR
Definition: stm32f303xe.h:172
ADC_TypeDef::OFR2
__IO uint32_t OFR2
Definition: stm32f303xe.h:194
ADC_TypeDef::TR2
__IO uint32_t TR2
Definition: stm32f303xe.h:181
ADC_TypeDef::RESERVED0
uint32_t RESERVED0
Definition: stm32f303xe.h:176
CAN_FIFOMailBox_TypeDef
Controller Area Network FIFOMailBox.
Definition: stm32f303xe.h:236
CAN_FIFOMailBox_TypeDef::RIR
__IO uint32_t RIR
Definition: stm32f303xe.h:237
CAN_FIFOMailBox_TypeDef::RDTR
__IO uint32_t RDTR
Definition: stm32f303xe.h:238
CAN_FIFOMailBox_TypeDef::RDHR
__IO uint32_t RDHR
Definition: stm32f303xe.h:240
CAN_FIFOMailBox_TypeDef::RDLR
__IO uint32_t RDLR
Definition: stm32f303xe.h:239
CAN_FilterRegister_TypeDef
Controller Area Network FilterRegister.
Definition: stm32f303xe.h:247
CAN_FilterRegister_TypeDef::FR2
__IO uint32_t FR2
Definition: stm32f303xe.h:249
CAN_FilterRegister_TypeDef::FR1
__IO uint32_t FR1
Definition: stm32f303xe.h:248
CAN_TxMailBox_TypeDef
Controller Area Network TxMailBox.
Definition: stm32f303xe.h:225
CAN_TxMailBox_TypeDef::TIR
__IO uint32_t TIR
Definition: stm32f303xe.h:226
CAN_TxMailBox_TypeDef::TDTR
__IO uint32_t TDTR
Definition: stm32f303xe.h:227
CAN_TxMailBox_TypeDef::TDLR
__IO uint32_t TDLR
Definition: stm32f303xe.h:228
CAN_TxMailBox_TypeDef::TDHR
__IO uint32_t TDHR
Definition: stm32f303xe.h:229
CAN_TypeDef
Controller Area Network.
Definition: stm32f303xe.h:256
CAN_TypeDef::MCR
__IO uint32_t MCR
Definition: stm32f303xe.h:257
CAN_TypeDef::FMR
__IO uint32_t FMR
Definition: stm32f303xe.h:269
CAN_TypeDef::RESERVED4
uint32_t RESERVED4
Definition: stm32f303xe.h:275
CAN_TypeDef::IER
__IO uint32_t IER
Definition: stm32f303xe.h:262
CAN_TypeDef::RF1R
__IO uint32_t RF1R
Definition: stm32f303xe.h:261
CAN_TypeDef::ESR
__IO uint32_t ESR
Definition: stm32f303xe.h:263
CAN_TypeDef::RESERVED2
uint32_t RESERVED2
Definition: stm32f303xe.h:271
CAN_TypeDef::FA1R
__IO uint32_t FA1R
Definition: stm32f303xe.h:276
CAN_TypeDef::FS1R
__IO uint32_t FS1R
Definition: stm32f303xe.h:272
CAN_TypeDef::TSR
__IO uint32_t TSR
Definition: stm32f303xe.h:259
CAN_TypeDef::BTR
__IO uint32_t BTR
Definition: stm32f303xe.h:264
CAN_TypeDef::RF0R
__IO uint32_t RF0R
Definition: stm32f303xe.h:260
CAN_TypeDef::FFA1R
__IO uint32_t FFA1R
Definition: stm32f303xe.h:274
CAN_TypeDef::FM1R
__IO uint32_t FM1R
Definition: stm32f303xe.h:270
CAN_TypeDef::RESERVED3
uint32_t RESERVED3
Definition: stm32f303xe.h:273
CAN_TypeDef::MSR
__IO uint32_t MSR
Definition: stm32f303xe.h:258
COMP_Common_TypeDef
Definition: stm32f303xe.h:290
COMP_Common_TypeDef::CSR
__IO uint32_t CSR
Definition: stm32f303xe.h:291
COMP_TypeDef
Analog Comparators.
Definition: stm32f303xe.h:285
COMP_TypeDef::CSR
__IO uint32_t CSR
Definition: stm32f303xe.h:286
CRC_TypeDef
CRC calculation unit.
Definition: stm32f303xe.h:299
CRC_TypeDef::POL
__IO uint32_t POL
Definition: stm32f303xe.h:307
CRC_TypeDef::INIT
__IO uint32_t INIT
Definition: stm32f303xe.h:306
CRC_TypeDef::RESERVED2
uint32_t RESERVED2
Definition: stm32f303xe.h:305
CRC_TypeDef::DR
__IO uint32_t DR
Definition: stm32f303xe.h:300
CRC_TypeDef::RESERVED0
uint8_t RESERVED0
Definition: stm32f303xe.h:302
CRC_TypeDef::RESERVED1
uint16_t RESERVED1
Definition: stm32f303xe.h:303
CRC_TypeDef::IDR
__IO uint8_t IDR
Definition: stm32f303xe.h:301
CRC_TypeDef::CR
__IO uint32_t CR
Definition: stm32f303xe.h:304
DAC_TypeDef
Digital to Analog Converter.
Definition: stm32f303xe.h:315
DAC_TypeDef::DHR8RD
__IO uint32_t DHR8RD
Definition: stm32f303xe.h:326
DAC_TypeDef::DOR2
__IO uint32_t DOR2
Definition: stm32f303xe.h:328
DAC_TypeDef::SR
__IO uint32_t SR
Definition: stm32f303xe.h:329
DAC_TypeDef::CR
__IO uint32_t CR
Definition: stm32f303xe.h:316
DAC_TypeDef::DHR8R1
__IO uint32_t DHR8R1
Definition: stm32f303xe.h:320
DAC_TypeDef::DHR8R2
__IO uint32_t DHR8R2
Definition: stm32f303xe.h:323
DAC_TypeDef::SWTRIGR
__IO uint32_t SWTRIGR
Definition: stm32f303xe.h:317
DAC_TypeDef::DOR1
__IO uint32_t DOR1
Definition: stm32f303xe.h:327
DAC_TypeDef::DHR12L1
__IO uint32_t DHR12L1
Definition: stm32f303xe.h:319
DAC_TypeDef::DHR12L2
__IO uint32_t DHR12L2
Definition: stm32f303xe.h:322
DAC_TypeDef::DHR12R2
__IO uint32_t DHR12R2
Definition: stm32f303xe.h:321
DAC_TypeDef::DHR12LD
__IO uint32_t DHR12LD
Definition: stm32f303xe.h:325
DAC_TypeDef::DHR12R1
__IO uint32_t DHR12R1
Definition: stm32f303xe.h:318
DAC_TypeDef::DHR12RD
__IO uint32_t DHR12RD
Definition: stm32f303xe.h:324
DBGMCU_TypeDef
Debug MCU.
Definition: stm32f303xe.h:337
DBGMCU_TypeDef::APB2FZ
__IO uint32_t APB2FZ
Definition: stm32f303xe.h:341
DBGMCU_TypeDef::IDCODE
__IO uint32_t IDCODE
Definition: stm32f303xe.h:338
DBGMCU_TypeDef::CR
__IO uint32_t CR
Definition: stm32f303xe.h:339
DBGMCU_TypeDef::APB1FZ
__IO uint32_t APB1FZ
Definition: stm32f303xe.h:340
DMA_Channel_TypeDef
DMA Controller.
Definition: stm32f303xe.h:349
DMA_Channel_TypeDef::CMAR
__IO uint32_t CMAR
Definition: stm32f303xe.h:353
DMA_Channel_TypeDef::CPAR
__IO uint32_t CPAR
Definition: stm32f303xe.h:352
DMA_Channel_TypeDef::CCR
__IO uint32_t CCR
Definition: stm32f303xe.h:350
DMA_Channel_TypeDef::CNDTR
__IO uint32_t CNDTR
Definition: stm32f303xe.h:351
DMA_TypeDef
Definition: stm32f303xe.h:357
DMA_TypeDef::IFCR
__IO uint32_t IFCR
Definition: stm32f303xe.h:359
DMA_TypeDef::ISR
__IO uint32_t ISR
Definition: stm32f303xe.h:358
EXTI_TypeDef
External Interrupt/Event Controller.
Definition: stm32f303xe.h:367
EXTI_TypeDef::RESERVED1
uint32_t RESERVED1
Definition: stm32f303xe.h:374
EXTI_TypeDef::IMR2
__IO uint32_t IMR2
Definition: stm32f303xe.h:376
EXTI_TypeDef::PR
__IO uint32_t PR
Definition: stm32f303xe.h:373
EXTI_TypeDef::IMR
__IO uint32_t IMR
Definition: stm32f303xe.h:368
EXTI_TypeDef::EMR2
__IO uint32_t EMR2
Definition: stm32f303xe.h:377
EXTI_TypeDef::FTSR2
__IO uint32_t FTSR2
Definition: stm32f303xe.h:379
EXTI_TypeDef::SWIER
__IO uint32_t SWIER
Definition: stm32f303xe.h:372
EXTI_TypeDef::PR2
__IO uint32_t PR2
Definition: stm32f303xe.h:381
EXTI_TypeDef::RTSR2
__IO uint32_t RTSR2
Definition: stm32f303xe.h:378
EXTI_TypeDef::EMR
__IO uint32_t EMR
Definition: stm32f303xe.h:369
EXTI_TypeDef::RTSR
__IO uint32_t RTSR
Definition: stm32f303xe.h:370
EXTI_TypeDef::SWIER2
__IO uint32_t SWIER2
Definition: stm32f303xe.h:380
EXTI_TypeDef::RESERVED2
uint32_t RESERVED2
Definition: stm32f303xe.h:375
EXTI_TypeDef::FTSR
__IO uint32_t FTSR
Definition: stm32f303xe.h:371
FLASH_TypeDef
FLASH Registers.
Definition: stm32f303xe.h:389
FLASH_TypeDef::RESERVED
uint32_t RESERVED
Definition: stm32f303xe.h:396
FLASH_TypeDef::OBR
__IO uint32_t OBR
Definition: stm32f303xe.h:397
FLASH_TypeDef::SR
__IO uint32_t SR
Definition: stm32f303xe.h:393
FLASH_TypeDef::CR
__IO uint32_t CR
Definition: stm32f303xe.h:394
FLASH_TypeDef::OPTKEYR
__IO uint32_t OPTKEYR
Definition: stm32f303xe.h:392
FLASH_TypeDef::KEYR
__IO uint32_t KEYR
Definition: stm32f303xe.h:391
FLASH_TypeDef::AR
__IO uint32_t AR
Definition: stm32f303xe.h:395
FLASH_TypeDef::ACR
__IO uint32_t ACR
Definition: stm32f303xe.h:390
FLASH_TypeDef::WRPR
__IO uint32_t WRPR
Definition: stm32f303xe.h:398
FMC_Bank1E_TypeDef
Flexible Memory Controller Bank1E.
Definition: stm32f303xe.h:416
FMC_Bank1_TypeDef
Flexible Memory Controller.
Definition: stm32f303xe.h:407
FMC_Bank2_3_TypeDef
Flexible Memory Controller Bank2.
Definition: stm32f303xe.h:425
FMC_Bank2_3_TypeDef::RESERVED1
uint32_t RESERVED1
Definition: stm32f303xe.h:432
FMC_Bank2_3_TypeDef::SR3
__IO uint32_t SR3
Definition: stm32f303xe.h:435
FMC_Bank2_3_TypeDef::PATT3
__IO uint32_t PATT3
Definition: stm32f303xe.h:437
FMC_Bank2_3_TypeDef::RESERVED0
uint32_t RESERVED0
Definition: stm32f303xe.h:430
FMC_Bank2_3_TypeDef::PMEM2
__IO uint32_t PMEM2
Definition: stm32f303xe.h:428
FMC_Bank2_3_TypeDef::PCR2
__IO uint32_t PCR2
Definition: stm32f303xe.h:426
FMC_Bank2_3_TypeDef::RESERVED2
uint32_t RESERVED2
Definition: stm32f303xe.h:433
FMC_Bank2_3_TypeDef::PMEM3
__IO uint32_t PMEM3
Definition: stm32f303xe.h:436
FMC_Bank2_3_TypeDef::PCR3
__IO uint32_t PCR3
Definition: stm32f303xe.h:434
FMC_Bank2_3_TypeDef::ECCR2
__IO uint32_t ECCR2
Definition: stm32f303xe.h:431
FMC_Bank2_3_TypeDef::SR2
__IO uint32_t SR2
Definition: stm32f303xe.h:427
FMC_Bank2_3_TypeDef::ECCR3
__IO uint32_t ECCR3
Definition: stm32f303xe.h:439
FMC_Bank2_3_TypeDef::RESERVED3
uint32_t RESERVED3
Definition: stm32f303xe.h:438
FMC_Bank2_3_TypeDef::PATT2
__IO uint32_t PATT2
Definition: stm32f303xe.h:429
FMC_Bank4_TypeDef
Flexible Memory Controller Bank4.
Definition: stm32f303xe.h:447
FMC_Bank4_TypeDef::PMEM4
__IO uint32_t PMEM4
Definition: stm32f303xe.h:450
FMC_Bank4_TypeDef::PIO4
__IO uint32_t PIO4
Definition: stm32f303xe.h:452
FMC_Bank4_TypeDef::SR4
__IO uint32_t SR4
Definition: stm32f303xe.h:449
FMC_Bank4_TypeDef::PCR4
__IO uint32_t PCR4
Definition: stm32f303xe.h:448
FMC_Bank4_TypeDef::PATT4
__IO uint32_t PATT4
Definition: stm32f303xe.h:451
GPIO_TypeDef
General Purpose I/O.
Definition: stm32f303xe.h:475
GPIO_TypeDef::OSPEEDR
__IO uint32_t OSPEEDR
Definition: stm32f303xe.h:478
GPIO_TypeDef::PUPDR
__IO uint32_t PUPDR
Definition: stm32f303xe.h:479
GPIO_TypeDef::ODR
__IO uint32_t ODR
Definition: stm32f303xe.h:481
GPIO_TypeDef::OTYPER
__IO uint32_t OTYPER
Definition: stm32f303xe.h:477
GPIO_TypeDef::LCKR
__IO uint32_t LCKR
Definition: stm32f303xe.h:483
GPIO_TypeDef::BRR
__IO uint32_t BRR
Definition: stm32f303xe.h:485
GPIO_TypeDef::MODER
__IO uint32_t MODER
Definition: stm32f303xe.h:476
GPIO_TypeDef::BSRR
__IO uint32_t BSRR
Definition: stm32f303xe.h:482
GPIO_TypeDef::IDR
__IO uint32_t IDR
Definition: stm32f303xe.h:480
I2C_TypeDef
Inter-integrated Circuit Interface.
Definition: stm32f303xe.h:528
I2C_TypeDef::ISR
__IO uint32_t ISR
Definition: stm32f303xe.h:535
I2C_TypeDef::CR2
__IO uint32_t CR2
Definition: stm32f303xe.h:530
I2C_TypeDef::RXDR
__IO uint32_t RXDR
Definition: stm32f303xe.h:538
I2C_TypeDef::PECR
__IO uint32_t PECR
Definition: stm32f303xe.h:537
I2C_TypeDef::OAR2
__IO uint32_t OAR2
Definition: stm32f303xe.h:532
I2C_TypeDef::ICR
__IO uint32_t ICR
Definition: stm32f303xe.h:536
I2C_TypeDef::CR1
__IO uint32_t CR1
Definition: stm32f303xe.h:529
I2C_TypeDef::TIMINGR
__IO uint32_t TIMINGR
Definition: stm32f303xe.h:533
I2C_TypeDef::TIMEOUTR
__IO uint32_t TIMEOUTR
Definition: stm32f303xe.h:534
I2C_TypeDef::TXDR
__IO uint32_t TXDR
Definition: stm32f303xe.h:539
I2C_TypeDef::OAR1
__IO uint32_t OAR1
Definition: stm32f303xe.h:531
IWDG_TypeDef
Independent WATCHDOG.
Definition: stm32f303xe.h:547
IWDG_TypeDef::PR
__IO uint32_t PR
Definition: stm32f303xe.h:549
IWDG_TypeDef::KR
__IO uint32_t KR
Definition: stm32f303xe.h:548
IWDG_TypeDef::WINR
__IO uint32_t WINR
Definition: stm32f303xe.h:552
IWDG_TypeDef::SR
__IO uint32_t SR
Definition: stm32f303xe.h:551
IWDG_TypeDef::RLR
__IO uint32_t RLR
Definition: stm32f303xe.h:550
OB_TypeDef
Option Bytes Registers.
Definition: stm32f303xe.h:459
OB_TypeDef::WRP2
__IO uint16_t WRP2
Definition: stm32f303xe.h:466
OB_TypeDef::Data1
__IO uint16_t Data1
Definition: stm32f303xe.h:463
OB_TypeDef::Data0
__IO uint16_t Data0
Definition: stm32f303xe.h:462
OB_TypeDef::USER
__IO uint16_t USER
Definition: stm32f303xe.h:461
OB_TypeDef::WRP3
__IO uint16_t WRP3
Definition: stm32f303xe.h:467
OB_TypeDef::WRP0
__IO uint16_t WRP0
Definition: stm32f303xe.h:464
OB_TypeDef::WRP1
__IO uint16_t WRP1
Definition: stm32f303xe.h:465
OB_TypeDef::RDP
__IO uint16_t RDP
Definition: stm32f303xe.h:460
OPAMP_TypeDef
Operational Amplifier (OPAMP)
Definition: stm32f303xe.h:493
OPAMP_TypeDef::CSR
__IO uint32_t CSR
Definition: stm32f303xe.h:494
PWR_TypeDef
Power Control.
Definition: stm32f303xe.h:560
PWR_TypeDef::CSR
__IO uint32_t CSR
Definition: stm32f303xe.h:562
PWR_TypeDef::CR
__IO uint32_t CR
Definition: stm32f303xe.h:561
RCC_TypeDef
Reset and Clock Control.
Definition: stm32f303xe.h:569
RCC_TypeDef::BDCR
__IO uint32_t BDCR
Definition: stm32f303xe.h:578
RCC_TypeDef::CFGR
__IO uint32_t CFGR
Definition: stm32f303xe.h:571
RCC_TypeDef::APB2RSTR
__IO uint32_t APB2RSTR
Definition: stm32f303xe.h:573
RCC_TypeDef::AHBRSTR
__IO uint32_t AHBRSTR
Definition: stm32f303xe.h:580
RCC_TypeDef::APB1RSTR
__IO uint32_t APB1RSTR
Definition: stm32f303xe.h:574
RCC_TypeDef::APB2ENR
__IO uint32_t APB2ENR
Definition: stm32f303xe.h:576
RCC_TypeDef::CSR
__IO uint32_t CSR
Definition: stm32f303xe.h:579
RCC_TypeDef::AHBENR
__IO uint32_t AHBENR
Definition: stm32f303xe.h:575
RCC_TypeDef::CR
__IO uint32_t CR
Definition: stm32f303xe.h:570
RCC_TypeDef::CIR
__IO uint32_t CIR
Definition: stm32f303xe.h:572
RCC_TypeDef::APB1ENR
__IO uint32_t APB1ENR
Definition: stm32f303xe.h:577
RCC_TypeDef::CFGR3
__IO uint32_t CFGR3
Definition: stm32f303xe.h:582
RCC_TypeDef::CFGR2
__IO uint32_t CFGR2
Definition: stm32f303xe.h:581
RTC_TypeDef
Real-Time Clock.
Definition: stm32f303xe.h:590
RTC_TypeDef::RESERVED7
uint32_t RESERVED7
Definition: stm32f303xe.h:610
RTC_TypeDef::BKP8R
__IO uint32_t BKP8R
Definition: stm32f303xe.h:619
RTC_TypeDef::BKP5R
__IO uint32_t BKP5R
Definition: stm32f303xe.h:616
RTC_TypeDef::BKP13R
__IO uint32_t BKP13R
Definition: stm32f303xe.h:624
RTC_TypeDef::RESERVED0
uint32_t RESERVED0
Definition: stm32f303xe.h:597
RTC_TypeDef::TSTR
__IO uint32_t TSTR
Definition: stm32f303xe.h:603
RTC_TypeDef::TSSSR
__IO uint32_t TSSSR
Definition: stm32f303xe.h:605
RTC_TypeDef::ALRMBSSR
__IO uint32_t ALRMBSSR
Definition: stm32f303xe.h:609
RTC_TypeDef::TR
__IO uint32_t TR
Definition: stm32f303xe.h:591
RTC_TypeDef::TAFCR
__IO uint32_t TAFCR
Definition: stm32f303xe.h:607
RTC_TypeDef::BKP1R
__IO uint32_t BKP1R
Definition: stm32f303xe.h:612
RTC_TypeDef::ISR
__IO uint32_t ISR
Definition: stm32f303xe.h:594
RTC_TypeDef::PRER
__IO uint32_t PRER
Definition: stm32f303xe.h:595
RTC_TypeDef::BKP10R
__IO uint32_t BKP10R
Definition: stm32f303xe.h:621
RTC_TypeDef::SHIFTR
__IO uint32_t SHIFTR
Definition: stm32f303xe.h:602
RTC_TypeDef::BKP4R
__IO uint32_t BKP4R
Definition: stm32f303xe.h:615
RTC_TypeDef::BKP12R
__IO uint32_t BKP12R
Definition: stm32f303xe.h:623
RTC_TypeDef::CR
__IO uint32_t CR
Definition: stm32f303xe.h:593
RTC_TypeDef::BKP6R
__IO uint32_t BKP6R
Definition: stm32f303xe.h:617
RTC_TypeDef::BKP15R
__IO uint32_t BKP15R
Definition: stm32f303xe.h:626
RTC_TypeDef::DR
__IO uint32_t DR
Definition: stm32f303xe.h:592
RTC_TypeDef::BKP11R
__IO uint32_t BKP11R
Definition: stm32f303xe.h:622
RTC_TypeDef::ALRMBR
__IO uint32_t ALRMBR
Definition: stm32f303xe.h:599
RTC_TypeDef::BKP7R
__IO uint32_t BKP7R
Definition: stm32f303xe.h:618
RTC_TypeDef::TSDR
__IO uint32_t TSDR
Definition: stm32f303xe.h:604
RTC_TypeDef::BKP2R
__IO uint32_t BKP2R
Definition: stm32f303xe.h:613
RTC_TypeDef::BKP0R
__IO uint32_t BKP0R
Definition: stm32f303xe.h:611
RTC_TypeDef::BKP9R
__IO uint32_t BKP9R
Definition: stm32f303xe.h:620
RTC_TypeDef::BKP3R
__IO uint32_t BKP3R
Definition: stm32f303xe.h:614
RTC_TypeDef::ALRMASSR
__IO uint32_t ALRMASSR
Definition: stm32f303xe.h:608
RTC_TypeDef::WPR
__IO uint32_t WPR
Definition: stm32f303xe.h:600
RTC_TypeDef::ALRMAR
__IO uint32_t ALRMAR
Definition: stm32f303xe.h:598
RTC_TypeDef::WUTR
__IO uint32_t WUTR
Definition: stm32f303xe.h:596
RTC_TypeDef::BKP14R
__IO uint32_t BKP14R
Definition: stm32f303xe.h:625
RTC_TypeDef::CALR
__IO uint32_t CALR
Definition: stm32f303xe.h:606
RTC_TypeDef::SSR
__IO uint32_t SSR
Definition: stm32f303xe.h:601
SPI_TypeDef
Serial Peripheral Interface.
Definition: stm32f303xe.h:635
SPI_TypeDef::DR
__IO uint32_t DR
Definition: stm32f303xe.h:639
SPI_TypeDef::TXCRCR
__IO uint32_t TXCRCR
Definition: stm32f303xe.h:642
SPI_TypeDef::SR
__IO uint32_t SR
Definition: stm32f303xe.h:638
SPI_TypeDef::CR2
__IO uint32_t CR2
Definition: stm32f303xe.h:637
SPI_TypeDef::I2SCFGR
__IO uint32_t I2SCFGR
Definition: stm32f303xe.h:643
SPI_TypeDef::CRCPR
__IO uint32_t CRCPR
Definition: stm32f303xe.h:640
SPI_TypeDef::RXCRCR
__IO uint32_t RXCRCR
Definition: stm32f303xe.h:641
SPI_TypeDef::CR1
__IO uint32_t CR1
Definition: stm32f303xe.h:636
SPI_TypeDef::I2SPR
__IO uint32_t I2SPR
Definition: stm32f303xe.h:644
SYSCFG_TypeDef
System configuration controller.
Definition: stm32f303xe.h:502
SYSCFG_TypeDef::RESERVED4
__IO uint32_t RESERVED4
Definition: stm32f303xe.h:510
SYSCFG_TypeDef::RESERVED1
__IO uint32_t RESERVED1
Definition: stm32f303xe.h:508
SYSCFG_TypeDef::RESERVED7
__IO uint32_t RESERVED7
Definition: stm32f303xe.h:513
SYSCFG_TypeDef::RESERVED2
__IO uint32_t RESERVED2
Definition: stm32f303xe.h:509
SYSCFG_TypeDef::RESERVED0
__IO uint32_t RESERVED0
Definition: stm32f303xe.h:507
SYSCFG_TypeDef::RESERVED10
__IO uint32_t RESERVED10
Definition: stm32f303xe.h:516
SYSCFG_TypeDef::CFGR1
__IO uint32_t CFGR1
Definition: stm32f303xe.h:503
SYSCFG_TypeDef::RESERVED11
__IO uint32_t RESERVED11
Definition: stm32f303xe.h:517
SYSCFG_TypeDef::CFGR4
__IO uint32_t CFGR4
Definition: stm32f303xe.h:518
SYSCFG_TypeDef::RCR
__IO uint32_t RCR
Definition: stm32f303xe.h:504
SYSCFG_TypeDef::RESERVED6
__IO uint32_t RESERVED6
Definition: stm32f303xe.h:512
SYSCFG_TypeDef::RESERVED12
__IO uint32_t RESERVED12
Definition: stm32f303xe.h:519
SYSCFG_TypeDef::RESERVED8
__IO uint32_t RESERVED8
Definition: stm32f303xe.h:514
SYSCFG_TypeDef::CFGR2
__IO uint32_t CFGR2
Definition: stm32f303xe.h:506
SYSCFG_TypeDef::RESERVED9
__IO uint32_t RESERVED9
Definition: stm32f303xe.h:515
SYSCFG_TypeDef::RESERVED13
__IO uint32_t RESERVED13
Definition: stm32f303xe.h:520
SYSCFG_TypeDef::RESERVED5
__IO uint32_t RESERVED5
Definition: stm32f303xe.h:511
TIM_TypeDef
TIM.
Definition: stm32f303xe.h:651
TIM_TypeDef::EGR
__IO uint32_t EGR
Definition: stm32f303xe.h:657
TIM_TypeDef::CCR1
__IO uint32_t CCR1
Definition: stm32f303xe.h:665
TIM_TypeDef::CCMR1
__IO uint32_t CCMR1
Definition: stm32f303xe.h:658
TIM_TypeDef::BDTR
__IO uint32_t BDTR
Definition: stm32f303xe.h:669
TIM_TypeDef::DIER
__IO uint32_t DIER
Definition: stm32f303xe.h:655
TIM_TypeDef::CCR6
__IO uint32_t CCR6
Definition: stm32f303xe.h:675
TIM_TypeDef::CCR2
__IO uint32_t CCR2
Definition: stm32f303xe.h:666
TIM_TypeDef::CCR4
__IO uint32_t CCR4
Definition: stm32f303xe.h:668
TIM_TypeDef::SMCR
__IO uint32_t SMCR
Definition: stm32f303xe.h:654
TIM_TypeDef::ARR
__IO uint32_t ARR
Definition: stm32f303xe.h:663
TIM_TypeDef::CR2
__IO uint32_t CR2
Definition: stm32f303xe.h:653
TIM_TypeDef::CNT
__IO uint32_t CNT
Definition: stm32f303xe.h:661
TIM_TypeDef::DCR
__IO uint32_t DCR
Definition: stm32f303xe.h:670
TIM_TypeDef::CR1
__IO uint32_t CR1
Definition: stm32f303xe.h:652
TIM_TypeDef::CCMR2
__IO uint32_t CCMR2
Definition: stm32f303xe.h:659
TIM_TypeDef::CCMR3
__IO uint32_t CCMR3
Definition: stm32f303xe.h:673
TIM_TypeDef::CCR3
__IO uint32_t CCR3
Definition: stm32f303xe.h:667
TIM_TypeDef::OR
__IO uint32_t OR
Definition: stm32f303xe.h:672
TIM_TypeDef::SR
__IO uint32_t SR
Definition: stm32f303xe.h:656
TIM_TypeDef::PSC
__IO uint32_t PSC
Definition: stm32f303xe.h:662
TIM_TypeDef::RCR
__IO uint32_t RCR
Definition: stm32f303xe.h:664
TIM_TypeDef::CCER
__IO uint32_t CCER
Definition: stm32f303xe.h:660
TIM_TypeDef::CCR5
__IO uint32_t CCR5
Definition: stm32f303xe.h:674
TIM_TypeDef::DMAR
__IO uint32_t DMAR
Definition: stm32f303xe.h:671
TSC_TypeDef
Touch Sensing Controller (TSC)
Definition: stm32f303xe.h:682
TSC_TypeDef::RESERVED3
uint32_t RESERVED3
Definition: stm32f303xe.h:692
TSC_TypeDef::RESERVED1
uint32_t RESERVED1
Definition: stm32f303xe.h:688
TSC_TypeDef::ICR
__IO uint32_t ICR
Definition: stm32f303xe.h:685
TSC_TypeDef::CR
__IO uint32_t CR
Definition: stm32f303xe.h:683
TSC_TypeDef::IER
__IO uint32_t IER
Definition: stm32f303xe.h:684
TSC_TypeDef::IOHCR
__IO uint32_t IOHCR
Definition: stm32f303xe.h:687
TSC_TypeDef::RESERVED4
uint32_t RESERVED4
Definition: stm32f303xe.h:694
TSC_TypeDef::ISR
__IO uint32_t ISR
Definition: stm32f303xe.h:686
TSC_TypeDef::RESERVED2
uint32_t RESERVED2
Definition: stm32f303xe.h:690
TSC_TypeDef::IOSCR
__IO uint32_t IOSCR
Definition: stm32f303xe.h:691
TSC_TypeDef::IOGCSR
__IO uint32_t IOGCSR
Definition: stm32f303xe.h:695
TSC_TypeDef::IOCCR
__IO uint32_t IOCCR
Definition: stm32f303xe.h:693
TSC_TypeDef::IOASCR
__IO uint32_t IOASCR
Definition: stm32f303xe.h:689
USART_TypeDef
Universal Synchronous Asynchronous Receiver Transmitter.
Definition: stm32f303xe.h:704
USART_TypeDef::TDR
__IO uint16_t TDR
Definition: stm32f303xe.h:716
USART_TypeDef::RTOR
__IO uint32_t RTOR
Definition: stm32f303xe.h:710
USART_TypeDef::RESERVED1
uint16_t RESERVED1
Definition: stm32f303xe.h:715
USART_TypeDef::CR1
__IO uint32_t CR1
Definition: stm32f303xe.h:705
USART_TypeDef::BRR
__IO uint32_t BRR
Definition: stm32f303xe.h:708
USART_TypeDef::ISR
__IO uint32_t ISR
Definition: stm32f303xe.h:712
USART_TypeDef::CR2
__IO uint32_t CR2
Definition: stm32f303xe.h:706
USART_TypeDef::RDR
__IO uint16_t RDR
Definition: stm32f303xe.h:714
USART_TypeDef::ICR
__IO uint32_t ICR
Definition: stm32f303xe.h:713
USART_TypeDef::RQR
__IO uint32_t RQR
Definition: stm32f303xe.h:711
USART_TypeDef::GTPR
__IO uint32_t GTPR
Definition: stm32f303xe.h:709
USART_TypeDef::CR3
__IO uint32_t CR3
Definition: stm32f303xe.h:707
USART_TypeDef::RESERVED2
uint16_t RESERVED2
Definition: stm32f303xe.h:717
USB_TypeDef
Universal Serial Bus Full Speed Device.
Definition: stm32f303xe.h:725
USB_TypeDef::RESERVED3
__IO uint16_t RESERVED3
Definition: stm32f303xe.h:733
USB_TypeDef::RESERVED4
__IO uint16_t RESERVED4
Definition: stm32f303xe.h:735
USB_TypeDef::RESERVEDB
__IO uint16_t RESERVEDB
Definition: stm32f303xe.h:749
USB_TypeDef::EP6R
__IO uint16_t EP6R
Definition: stm32f303xe.h:738
USB_TypeDef::EP7R
__IO uint16_t EP7R
Definition: stm32f303xe.h:740
USB_TypeDef::ISTR
__IO uint16_t ISTR
Definition: stm32f303xe.h:744
USB_TypeDef::DADDR
__IO uint16_t DADDR
Definition: stm32f303xe.h:748
USB_TypeDef::CNTR
__IO uint16_t CNTR
Definition: stm32f303xe.h:742
USB_TypeDef::EP1R
__IO uint16_t EP1R
Definition: stm32f303xe.h:728
USB_TypeDef::EP2R
__IO uint16_t EP2R
Definition: stm32f303xe.h:730
USB_TypeDef::RESERVED1
__IO uint16_t RESERVED1
Definition: stm32f303xe.h:729
USB_TypeDef::BTABLE
__IO uint16_t BTABLE
Definition: stm32f303xe.h:750
USB_TypeDef::RESERVED2
__IO uint16_t RESERVED2
Definition: stm32f303xe.h:731
USB_TypeDef::EP3R
__IO uint16_t EP3R
Definition: stm32f303xe.h:732
USB_TypeDef::EP5R
__IO uint16_t EP5R
Definition: stm32f303xe.h:736
USB_TypeDef::EP4R
__IO uint16_t EP4R
Definition: stm32f303xe.h:734
USB_TypeDef::RESERVEDC
__IO uint16_t RESERVEDC
Definition: stm32f303xe.h:751
USB_TypeDef::RESERVED6
__IO uint16_t RESERVED6
Definition: stm32f303xe.h:739
USB_TypeDef::RESERVED5
__IO uint16_t RESERVED5
Definition: stm32f303xe.h:737
USB_TypeDef::RESERVED0
__IO uint16_t RESERVED0
Definition: stm32f303xe.h:727
USB_TypeDef::RESERVEDA
__IO uint16_t RESERVEDA
Definition: stm32f303xe.h:747
USB_TypeDef::EP0R
__IO uint16_t EP0R
Definition: stm32f303xe.h:726
USB_TypeDef::RESERVED8
__IO uint16_t RESERVED8
Definition: stm32f303xe.h:743
USB_TypeDef::LPMCSR
__IO uint16_t LPMCSR
Definition: stm32f303xe.h:752
USB_TypeDef::RESERVEDD
__IO uint16_t RESERVEDD
Definition: stm32f303xe.h:753
USB_TypeDef::FNR
__IO uint16_t FNR
Definition: stm32f303xe.h:746
USB_TypeDef::RESERVED9
__IO uint16_t RESERVED9
Definition: stm32f303xe.h:745
WWDG_TypeDef
Window WATCHDOG.
Definition: stm32f303xe.h:760
WWDG_TypeDef::SR
__IO uint32_t SR
Definition: stm32f303xe.h:763
WWDG_TypeDef::CR
__IO uint32_t CR
Definition: stm32f303xe.h:761
WWDG_TypeDef::CFR
__IO uint32_t CFR
Definition: stm32f303xe.h:762
system_stm32f3xx.h
CMSIS Cortex-M4 Device System Source File for STM32F3xx devices. ************************************...