FMC_Bank2_3_TypeDef Struct Reference

Flexible Memory Controller Bank2. More...

#include <stm32f303xe.h>

Public Attributes
__IO uint32_t	PCR2
__IO uint32_t	SR2
__IO uint32_t	PMEM2
__IO uint32_t	PATT2
uint32_t	RESERVED0
__IO uint32_t	ECCR2
uint32_t	RESERVED1
uint32_t	RESERVED2
__IO uint32_t	PCR3
__IO uint32_t	SR3
__IO uint32_t	PMEM3
__IO uint32_t	PATT3
uint32_t	RESERVED3
__IO uint32_t	ECCR3

Detailed Description

Flexible Memory Controller Bank2.

Member Data Documentation

ECCR2

__IO uint32_t FMC_Bank2_3_TypeDef::ECCR2

NAND Flash ECC result registers 2, Address offset: 0x74

ECCR3

__IO uint32_t FMC_Bank2_3_TypeDef::ECCR3

NAND Flash ECC result registers 3, Address offset: 0x94

PATT2

__IO uint32_t FMC_Bank2_3_TypeDef::PATT2

NAND Flash Attribute memory space timing register 2, Address offset: 0x6C

PATT3

__IO uint32_t FMC_Bank2_3_TypeDef::PATT3

NAND Flash Attribute memory space timing register 3, Address offset: 0x8C

PCR2

__IO uint32_t FMC_Bank2_3_TypeDef::PCR2

NAND Flash control register 2, Address offset: 0x60

PCR3

__IO uint32_t FMC_Bank2_3_TypeDef::PCR3

NAND Flash control register 3, Address offset: 0x80

PMEM2

__IO uint32_t FMC_Bank2_3_TypeDef::PMEM2

NAND Flash Common memory space timing register 2, Address offset: 0x68

PMEM3

__IO uint32_t FMC_Bank2_3_TypeDef::PMEM3

NAND Flash Common memory space timing register 3, Address offset: 0x88

RESERVED0

uint32_t FMC_Bank2_3_TypeDef::RESERVED0

Reserved, 0x70

RESERVED1

uint32_t FMC_Bank2_3_TypeDef::RESERVED1

Reserved, 0x78

RESERVED2

uint32_t FMC_Bank2_3_TypeDef::RESERVED2

Reserved, 0x7C

RESERVED3

uint32_t FMC_Bank2_3_TypeDef::RESERVED3

Reserved, 0x90

SR2

__IO uint32_t FMC_Bank2_3_TypeDef::SR2

NAND Flash FIFO status and interrupt register 2, Address offset: 0x64

SR3

__IO uint32_t FMC_Bank2_3_TypeDef::SR3

NAND Flash FIFO status and interrupt register 3, Address offset: 0x84

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The documentation for this struct was generated from the following file:

• Drivers/CMSIS/Device/ST/STM32F3xx/Include/stm32f303xe.h