TIM. More...

#include <stm32f303xe.h>

Public Attributes
__IO uint32_t	CR1

__IO uint32_t	CR2

__IO uint32_t	SMCR

__IO uint32_t	DIER

__IO uint32_t	SR

__IO uint32_t	EGR

__IO uint32_t	CCMR1

__IO uint32_t	CCMR2

__IO uint32_t	CCER

__IO uint32_t	CNT

__IO uint32_t	PSC

__IO uint32_t	ARR

__IO uint32_t	RCR

__IO uint32_t	CCR1

__IO uint32_t	CCR2

__IO uint32_t	CCR3

__IO uint32_t	CCR4

__IO uint32_t	BDTR

__IO uint32_t	DCR

__IO uint32_t	DMAR

__IO uint32_t	OR

__IO uint32_t	CCMR3

__IO uint32_t	CCR5

__IO uint32_t	CCR6

Detailed Description

TIM.

Member Data Documentation

◆ ARR

__IO uint32_t TIM_TypeDef::ARR

TIM auto-reload register, Address offset: 0x2C

◆ BDTR

__IO uint32_t TIM_TypeDef::BDTR

TIM break and dead-time register, Address offset: 0x44

◆ CCER

__IO uint32_t TIM_TypeDef::CCER

TIM capture/compare enable register, Address offset: 0x20

◆ CCMR1

__IO uint32_t TIM_TypeDef::CCMR1

TIM capture/compare mode register 1, Address offset: 0x18

◆ CCMR2

__IO uint32_t TIM_TypeDef::CCMR2

TIM capture/compare mode register 2, Address offset: 0x1C

◆ CCMR3

__IO uint32_t TIM_TypeDef::CCMR3

TIM capture/compare mode register 3, Address offset: 0x54

◆ CCR1

__IO uint32_t TIM_TypeDef::CCR1

TIM capture/compare register 1, Address offset: 0x34

◆ CCR2

__IO uint32_t TIM_TypeDef::CCR2

TIM capture/compare register 2, Address offset: 0x38

◆ CCR3

__IO uint32_t TIM_TypeDef::CCR3

TIM capture/compare register 3, Address offset: 0x3C

◆ CCR4

__IO uint32_t TIM_TypeDef::CCR4

TIM capture/compare register 4, Address offset: 0x40

◆ CCR5

__IO uint32_t TIM_TypeDef::CCR5

TIM capture/compare register5, Address offset: 0x58

◆ CCR6

__IO uint32_t TIM_TypeDef::CCR6

TIM capture/compare register 4, Address offset: 0x5C

◆ CNT

__IO uint32_t TIM_TypeDef::CNT

TIM counter register, Address offset: 0x24

◆ CR1

__IO uint32_t TIM_TypeDef::CR1

TIM control register 1, Address offset: 0x00

◆ CR2

__IO uint32_t TIM_TypeDef::CR2

TIM control register 2, Address offset: 0x04

◆ DCR

__IO uint32_t TIM_TypeDef::DCR

TIM DMA control register, Address offset: 0x48

◆ DIER

__IO uint32_t TIM_TypeDef::DIER

TIM DMA/interrupt enable register, Address offset: 0x0C

◆ DMAR

__IO uint32_t TIM_TypeDef::DMAR

TIM DMA address for full transfer, Address offset: 0x4C

◆ EGR

__IO uint32_t TIM_TypeDef::EGR

TIM event generation register, Address offset: 0x14

◆ OR

__IO uint32_t TIM_TypeDef::OR

TIM option register, Address offset: 0x50

◆ PSC

__IO uint32_t TIM_TypeDef::PSC

TIM prescaler, Address offset: 0x28

◆ RCR

__IO uint32_t TIM_TypeDef::RCR

TIM repetition counter register, Address offset: 0x30

◆ SMCR

__IO uint32_t TIM_TypeDef::SMCR

TIM slave mode control register, Address offset: 0x08

◆ SR

__IO uint32_t TIM_TypeDef::SR

TIM status register, Address offset: 0x10

The documentation for this struct was generated from the following file:

Drivers/CMSIS/Device/ST/STM32F3xx/Include/stm32f303xe.h

Public Attributes