RCC APB1 Clock Enable Disable

Enable or disable the Low Speed APB (APB1) peripheral clock. More...

Macros
#define	__HAL_RCC_TIM2_CLK_ENABLE()
#define	__HAL_RCC_TIM6_CLK_ENABLE()
#define	__HAL_RCC_WWDG_CLK_ENABLE()
#define	__HAL_RCC_USART2_CLK_ENABLE()
#define	__HAL_RCC_USART3_CLK_ENABLE()
#define	__HAL_RCC_I2C1_CLK_ENABLE()
#define	__HAL_RCC_PWR_CLK_ENABLE()
#define	__HAL_RCC_DAC1_CLK_ENABLE()
#define	__HAL_RCC_TIM2_CLK_DISABLE()   (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM2EN))
#define	__HAL_RCC_TIM6_CLK_DISABLE()   (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM6EN))
#define	__HAL_RCC_WWDG_CLK_DISABLE()   (RCC->APB1ENR &= ~(RCC_APB1ENR_WWDGEN))
#define	__HAL_RCC_USART2_CLK_DISABLE()   (RCC->APB1ENR &= ~(RCC_APB1ENR_USART2EN))
#define	__HAL_RCC_USART3_CLK_DISABLE()   (RCC->APB1ENR &= ~(RCC_APB1ENR_USART3EN))
#define	__HAL_RCC_I2C1_CLK_DISABLE()   (RCC->APB1ENR &= ~(RCC_APB1ENR_I2C1EN))
#define	__HAL_RCC_PWR_CLK_DISABLE()   (RCC->APB1ENR &= ~(RCC_APB1ENR_PWREN))
#define	__HAL_RCC_DAC1_CLK_DISABLE()   (RCC->APB1ENR &= ~(RCC_APB1ENR_DAC1EN))

Detailed Description

Enable or disable the Low Speed APB (APB1) peripheral clock.

Note

After reset, the peripheral clock (used for registers read/write access) is disabled and the application software has to enable this clock before using it.

Macro Definition Documentation

__HAL_RCC_DAC1_CLK_DISABLE

#define __HAL_RCC_DAC1_CLK_DISABLE

(

)

(RCC->APB1ENR &= ~(RCC_APB1ENR_DAC1EN))

__HAL_RCC_DAC1_CLK_ENABLE

#define __HAL_RCC_DAC1_CLK_ENABLE

(

)

Value:

                                        do { \
                                        __IO uint32_t tmpreg; \
                                        SET_BIT(RCC->APB1ENR, RCC_APB1ENR_DAC1EN);\
                                        /* Delay after an RCC peripheral clock enabling */ \
                                        tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_DAC1EN);\
                                        UNUSED(tmpreg); \
                                      } while(0U)

__HAL_RCC_I2C1_CLK_DISABLE

#define __HAL_RCC_I2C1_CLK_DISABLE

(

)

(RCC->APB1ENR &= ~(RCC_APB1ENR_I2C1EN))

__HAL_RCC_I2C1_CLK_ENABLE

#define __HAL_RCC_I2C1_CLK_ENABLE

(

)

Value:

                                        do { \
                                        __IO uint32_t tmpreg; \
                                        SET_BIT(RCC->APB1ENR, RCC_APB1ENR_I2C1EN);\
                                        /* Delay after an RCC peripheral clock enabling */ \
                                        tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_I2C1EN);\
                                        UNUSED(tmpreg); \
                                      } while(0U)

__HAL_RCC_PWR_CLK_DISABLE

#define __HAL_RCC_PWR_CLK_DISABLE

(

)

(RCC->APB1ENR &= ~(RCC_APB1ENR_PWREN))

__HAL_RCC_PWR_CLK_ENABLE

#define __HAL_RCC_PWR_CLK_ENABLE

(

)

Value:

                                        do { \
                                        __IO uint32_t tmpreg; \
                                        SET_BIT(RCC->APB1ENR, RCC_APB1ENR_PWREN);\
                                        /* Delay after an RCC peripheral clock enabling */ \
                                        tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_PWREN);\
                                        UNUSED(tmpreg); \
                                      } while(0U)

__HAL_RCC_TIM2_CLK_DISABLE

#define __HAL_RCC_TIM2_CLK_DISABLE

(

)

(RCC->APB1ENR &= ~(RCC_APB1ENR_TIM2EN))

__HAL_RCC_TIM2_CLK_ENABLE

#define __HAL_RCC_TIM2_CLK_ENABLE

(

)

Value:

                                        do { \
                                        __IO uint32_t tmpreg; \
                                        SET_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM2EN);\
                                        /* Delay after an RCC peripheral clock enabling */ \
                                        tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM2EN);\
                                        UNUSED(tmpreg); \
                                      } while(0U)

__HAL_RCC_TIM6_CLK_DISABLE

#define __HAL_RCC_TIM6_CLK_DISABLE

(

)

(RCC->APB1ENR &= ~(RCC_APB1ENR_TIM6EN))

__HAL_RCC_TIM6_CLK_ENABLE

#define __HAL_RCC_TIM6_CLK_ENABLE

(

)

Value:

                                        do { \
                                        __IO uint32_t tmpreg; \
                                        SET_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM6EN);\
                                        /* Delay after an RCC peripheral clock enabling */ \
                                        tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM6EN);\
                                        UNUSED(tmpreg); \
                                      } while(0U)

__HAL_RCC_USART2_CLK_DISABLE

#define __HAL_RCC_USART2_CLK_DISABLE

(

)

(RCC->APB1ENR &= ~(RCC_APB1ENR_USART2EN))

__HAL_RCC_USART2_CLK_ENABLE

#define __HAL_RCC_USART2_CLK_ENABLE

(

)

Value:

                                        do { \
                                        __IO uint32_t tmpreg; \
                                        SET_BIT(RCC->APB1ENR, RCC_APB1ENR_USART2EN);\
                                        /* Delay after an RCC peripheral clock enabling */ \
                                        tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_USART2EN);\
                                        UNUSED(tmpreg); \
                                      } while(0U)

__HAL_RCC_USART3_CLK_DISABLE

#define __HAL_RCC_USART3_CLK_DISABLE

(

)

(RCC->APB1ENR &= ~(RCC_APB1ENR_USART3EN))

__HAL_RCC_USART3_CLK_ENABLE

#define __HAL_RCC_USART3_CLK_ENABLE

(

)

Value:

                                        do { \
                                        __IO uint32_t tmpreg; \
                                        SET_BIT(RCC->APB1ENR, RCC_APB1ENR_USART3EN);\
                                        /* Delay after an RCC peripheral clock enabling */ \
                                        tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_USART3EN);\
                                        UNUSED(tmpreg); \
                                      } while(0U)

__HAL_RCC_WWDG_CLK_DISABLE

#define __HAL_RCC_WWDG_CLK_DISABLE

(

)

(RCC->APB1ENR &= ~(RCC_APB1ENR_WWDGEN))

__HAL_RCC_WWDG_CLK_ENABLE

#define __HAL_RCC_WWDG_CLK_ENABLE

(

)

Value:

                                        do { \
                                        __IO uint32_t tmpreg; \
                                        SET_BIT(RCC->APB1ENR, RCC_APB1ENR_WWDGEN);\
                                        /* Delay after an RCC peripheral clock enabling */ \
                                        tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_WWDGEN);\
                                        UNUSED(tmpreg); \
                                      } while(0U)