Enable or disable the Low Speed APB (APB1) peripheral clock.
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Enable or disable the Low Speed APB (APB1) peripheral clock.
- Note
- After reset, the peripheral clock (used for registers read/write access) is disabled and the application software has to enable this clock before using it.
◆ __HAL_RCC_DAC1_CLK_DISABLE
◆ __HAL_RCC_DAC1_CLK_ENABLE
#define __HAL_RCC_DAC1_CLK_ENABLE |
( |
| ) |
|
Value: do { \
\
UNUSED(tmpreg); \
} while(0U)
#define __IO
Definition: core_armv8mbl.h:196
#define READ_BIT(REG, BIT)
Definition: stm32f3xx.h:194
#define RCC_APB1ENR_DAC1EN
Definition: stm32f303xe.h:11209
#define RCC
Definition: stm32f303xe.h:977
◆ __HAL_RCC_I2C1_CLK_DISABLE
◆ __HAL_RCC_I2C1_CLK_ENABLE
#define __HAL_RCC_I2C1_CLK_ENABLE |
( |
| ) |
|
Value: do { \
\
UNUSED(tmpreg); \
} while(0U)
#define RCC_APB1ENR_I2C1EN
Definition: stm32f303xe.h:11194
◆ __HAL_RCC_PWR_CLK_DISABLE
◆ __HAL_RCC_PWR_CLK_ENABLE
#define __HAL_RCC_PWR_CLK_ENABLE |
( |
| ) |
|
Value: do { \
\
UNUSED(tmpreg); \
} while(0U)
#define RCC_APB1ENR_PWREN
Definition: stm32f303xe.h:11206
◆ __HAL_RCC_TIM2_CLK_DISABLE
◆ __HAL_RCC_TIM2_CLK_ENABLE
#define __HAL_RCC_TIM2_CLK_ENABLE |
( |
| ) |
|
Value: do { \
\
UNUSED(tmpreg); \
} while(0U)
#define RCC_APB1ENR_TIM2EN
Definition: stm32f303xe.h:11158
◆ __HAL_RCC_TIM6_CLK_DISABLE
◆ __HAL_RCC_TIM6_CLK_ENABLE
#define __HAL_RCC_TIM6_CLK_ENABLE |
( |
| ) |
|
Value: do { \
\
UNUSED(tmpreg); \
} while(0U)
#define RCC_APB1ENR_TIM6EN
Definition: stm32f303xe.h:11167
◆ __HAL_RCC_USART2_CLK_DISABLE
◆ __HAL_RCC_USART2_CLK_ENABLE
#define __HAL_RCC_USART2_CLK_ENABLE |
( |
| ) |
|
Value: do { \
\
UNUSED(tmpreg); \
} while(0U)
#define RCC_APB1ENR_USART2EN
Definition: stm32f303xe.h:11182
◆ __HAL_RCC_USART3_CLK_DISABLE
◆ __HAL_RCC_USART3_CLK_ENABLE
#define __HAL_RCC_USART3_CLK_ENABLE |
( |
| ) |
|
Value: do { \
\
UNUSED(tmpreg); \
} while(0U)
#define RCC_APB1ENR_USART3EN
Definition: stm32f303xe.h:11185
◆ __HAL_RCC_WWDG_CLK_DISABLE
◆ __HAL_RCC_WWDG_CLK_ENABLE
#define __HAL_RCC_WWDG_CLK_ENABLE |
( |
| ) |
|
Value: do { \
\
UNUSED(tmpreg); \
} while(0U)
#define RCC_APB1ENR_WWDGEN
Definition: stm32f303xe.h:11173