Enable or disable the High Speed APB (APB2) peripheral clock.
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Enable or disable the High Speed APB (APB2) peripheral clock.
- Note
- After reset, the peripheral clock (used for registers read/write access) is disabled and the application software has to enable this clock before using it.
◆ __HAL_RCC_SYSCFG_CLK_DISABLE
◆ __HAL_RCC_SYSCFG_CLK_ENABLE
#define __HAL_RCC_SYSCFG_CLK_ENABLE |
( |
| ) |
|
Value: do { \
\
UNUSED(tmpreg); \
} while(0U)
#define __IO
Definition: core_armv8mbl.h:196
#define READ_BIT(REG, BIT)
Definition: stm32f3xx.h:194
#define RCC_APB2ENR_SYSCFGEN
Definition: stm32f303xe.h:11126
#define RCC
Definition: stm32f303xe.h:977
◆ __HAL_RCC_TIM15_CLK_DISABLE
◆ __HAL_RCC_TIM15_CLK_ENABLE
#define __HAL_RCC_TIM15_CLK_ENABLE |
( |
| ) |
|
Value: do { \
\
UNUSED(tmpreg); \
} while(0U)
#define RCC_APB2ENR_TIM15EN
Definition: stm32f303xe.h:11144
◆ __HAL_RCC_TIM16_CLK_DISABLE
◆ __HAL_RCC_TIM16_CLK_ENABLE
#define __HAL_RCC_TIM16_CLK_ENABLE |
( |
| ) |
|
Value: do { \
\
UNUSED(tmpreg); \
} while(0U)
#define RCC_APB2ENR_TIM16EN
Definition: stm32f303xe.h:11147
◆ __HAL_RCC_TIM17_CLK_DISABLE
◆ __HAL_RCC_TIM17_CLK_ENABLE
#define __HAL_RCC_TIM17_CLK_ENABLE |
( |
| ) |
|
Value: do { \
\
UNUSED(tmpreg); \
} while(0U)
#define RCC_APB2ENR_TIM17EN
Definition: stm32f303xe.h:11150
◆ __HAL_RCC_USART1_CLK_DISABLE
◆ __HAL_RCC_USART1_CLK_ENABLE
#define __HAL_RCC_USART1_CLK_ENABLE |
( |
| ) |
|
Value: do { \
\
UNUSED(tmpreg); \
} while(0U)
#define RCC_APB2ENR_USART1EN
Definition: stm32f303xe.h:11138