PLL Configuration

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Macros
#define	__HAL_RCC_PLL_ENABLE()   (*(__IO uint32_t *) RCC_CR_PLLON_BB = ENABLE)
	Macro to enable the main PLL.
#define	__HAL_RCC_PLL_DISABLE()   (*(__IO uint32_t *) RCC_CR_PLLON_BB = DISABLE)
	Macro to disable the main PLL.
#define	__HAL_RCC_GET_PLL_OSCSOURCE()   ((uint32_t)(READ_BIT(RCC->CFGR, RCC_CFGR_PLLSRC)))
	Get oscillator clock selected as PLL input clock.

Detailed Description

Macro Definition Documentation

__HAL_RCC_GET_PLL_OSCSOURCE

#define __HAL_RCC_GET_PLL_OSCSOURCE

(

)

((uint32_t)(READ_BIT(RCC->CFGR, RCC_CFGR_PLLSRC)))

Get oscillator clock selected as PLL input clock.

Return values

The	clock source used for PLL entry. The returned value can be one of the following: RCC_PLLSOURCE_HSI HSI oscillator clock selected as PLL input clock RCC_PLLSOURCE_HSE HSE oscillator clock selected as PLL input clock

__HAL_RCC_PLL_DISABLE

#define __HAL_RCC_PLL_DISABLE

(

)

(*(__IO uint32_t *) RCC_CR_PLLON_BB = DISABLE)

Macro to disable the main PLL.

Note

The main PLL can not be disabled if it is used as system clock source

__HAL_RCC_PLL_ENABLE

#define __HAL_RCC_PLL_ENABLE

(

)

(*(__IO uint32_t *) RCC_CR_PLLON_BB = ENABLE)

Macro to enable the main PLL.

Note

After enabling the main PLL, the application software should wait on PLLRDY flag to be set indicating that PLL clock is stable and can be used as system clock source.

The main PLL is disabled by hardware when entering STOP and STANDBY modes.