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stm32f3xx_ll_dma.h
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1
19/* Define to prevent recursive inclusion -------------------------------------*/
20#ifndef __STM32F3xx_LL_DMA_H
21#define __STM32F3xx_LL_DMA_H
22
23#ifdef __cplusplus
24extern "C" {
25#endif
26
27/* Includes ------------------------------------------------------------------*/
28#include "stm32f3xx.h"
29
34#if defined (DMA1) || defined (DMA2)
35
40/* Private types -------------------------------------------------------------*/
41/* Private variables ---------------------------------------------------------*/
45/* Array used to get the DMA channel register offset versus channel index LL_DMA_CHANNEL_x */
46static const uint8_t CHANNEL_OFFSET_TAB[] =
47{
48 (uint8_t)(DMA1_Channel1_BASE - DMA1_BASE),
49 (uint8_t)(DMA1_Channel2_BASE - DMA1_BASE),
50 (uint8_t)(DMA1_Channel3_BASE - DMA1_BASE),
51 (uint8_t)(DMA1_Channel4_BASE - DMA1_BASE),
52 (uint8_t)(DMA1_Channel5_BASE - DMA1_BASE),
53 (uint8_t)(DMA1_Channel6_BASE - DMA1_BASE),
54 (uint8_t)(DMA1_Channel7_BASE - DMA1_BASE)
55};
60/* Private constants ---------------------------------------------------------*/
61/* Private macros ------------------------------------------------------------*/
62#if defined(USE_FULL_LL_DRIVER)
69#endif /*USE_FULL_LL_DRIVER*/
70
71/* Exported types ------------------------------------------------------------*/
72#if defined(USE_FULL_LL_DRIVER)
76typedef struct
77{
78 uint32_t PeriphOrM2MSrcAddress;
83 uint32_t MemoryOrM2MDstAddress;
88 uint32_t Direction;
94 uint32_t Mode;
101 uint32_t PeriphOrM2MSrcIncMode;
107 uint32_t MemoryOrM2MDstIncMode;
113 uint32_t PeriphOrM2MSrcDataSize;
119 uint32_t MemoryOrM2MDstDataSize;
125 uint32_t NbData;
132 uint32_t Priority;
137} LL_DMA_InitTypeDef;
141#endif /*USE_FULL_LL_DRIVER*/
142
143/* Exported constants --------------------------------------------------------*/
151#define LL_DMA_IFCR_CGIF1 DMA_IFCR_CGIF1
152#define LL_DMA_IFCR_CTCIF1 DMA_IFCR_CTCIF1
153#define LL_DMA_IFCR_CHTIF1 DMA_IFCR_CHTIF1
154#define LL_DMA_IFCR_CTEIF1 DMA_IFCR_CTEIF1
155#define LL_DMA_IFCR_CGIF2 DMA_IFCR_CGIF2
156#define LL_DMA_IFCR_CTCIF2 DMA_IFCR_CTCIF2
157#define LL_DMA_IFCR_CHTIF2 DMA_IFCR_CHTIF2
158#define LL_DMA_IFCR_CTEIF2 DMA_IFCR_CTEIF2
159#define LL_DMA_IFCR_CGIF3 DMA_IFCR_CGIF3
160#define LL_DMA_IFCR_CTCIF3 DMA_IFCR_CTCIF3
161#define LL_DMA_IFCR_CHTIF3 DMA_IFCR_CHTIF3
162#define LL_DMA_IFCR_CTEIF3 DMA_IFCR_CTEIF3
163#define LL_DMA_IFCR_CGIF4 DMA_IFCR_CGIF4
164#define LL_DMA_IFCR_CTCIF4 DMA_IFCR_CTCIF4
165#define LL_DMA_IFCR_CHTIF4 DMA_IFCR_CHTIF4
166#define LL_DMA_IFCR_CTEIF4 DMA_IFCR_CTEIF4
167#define LL_DMA_IFCR_CGIF5 DMA_IFCR_CGIF5
168#define LL_DMA_IFCR_CTCIF5 DMA_IFCR_CTCIF5
169#define LL_DMA_IFCR_CHTIF5 DMA_IFCR_CHTIF5
170#define LL_DMA_IFCR_CTEIF5 DMA_IFCR_CTEIF5
171#define LL_DMA_IFCR_CGIF6 DMA_IFCR_CGIF6
172#define LL_DMA_IFCR_CTCIF6 DMA_IFCR_CTCIF6
173#define LL_DMA_IFCR_CHTIF6 DMA_IFCR_CHTIF6
174#define LL_DMA_IFCR_CTEIF6 DMA_IFCR_CTEIF6
175#define LL_DMA_IFCR_CGIF7 DMA_IFCR_CGIF7
176#define LL_DMA_IFCR_CTCIF7 DMA_IFCR_CTCIF7
177#define LL_DMA_IFCR_CHTIF7 DMA_IFCR_CHTIF7
178#define LL_DMA_IFCR_CTEIF7 DMA_IFCR_CTEIF7
187#define LL_DMA_ISR_GIF1 DMA_ISR_GIF1
188#define LL_DMA_ISR_TCIF1 DMA_ISR_TCIF1
189#define LL_DMA_ISR_HTIF1 DMA_ISR_HTIF1
190#define LL_DMA_ISR_TEIF1 DMA_ISR_TEIF1
191#define LL_DMA_ISR_GIF2 DMA_ISR_GIF2
192#define LL_DMA_ISR_TCIF2 DMA_ISR_TCIF2
193#define LL_DMA_ISR_HTIF2 DMA_ISR_HTIF2
194#define LL_DMA_ISR_TEIF2 DMA_ISR_TEIF2
195#define LL_DMA_ISR_GIF3 DMA_ISR_GIF3
196#define LL_DMA_ISR_TCIF3 DMA_ISR_TCIF3
197#define LL_DMA_ISR_HTIF3 DMA_ISR_HTIF3
198#define LL_DMA_ISR_TEIF3 DMA_ISR_TEIF3
199#define LL_DMA_ISR_GIF4 DMA_ISR_GIF4
200#define LL_DMA_ISR_TCIF4 DMA_ISR_TCIF4
201#define LL_DMA_ISR_HTIF4 DMA_ISR_HTIF4
202#define LL_DMA_ISR_TEIF4 DMA_ISR_TEIF4
203#define LL_DMA_ISR_GIF5 DMA_ISR_GIF5
204#define LL_DMA_ISR_TCIF5 DMA_ISR_TCIF5
205#define LL_DMA_ISR_HTIF5 DMA_ISR_HTIF5
206#define LL_DMA_ISR_TEIF5 DMA_ISR_TEIF5
207#define LL_DMA_ISR_GIF6 DMA_ISR_GIF6
208#define LL_DMA_ISR_TCIF6 DMA_ISR_TCIF6
209#define LL_DMA_ISR_HTIF6 DMA_ISR_HTIF6
210#define LL_DMA_ISR_TEIF6 DMA_ISR_TEIF6
211#define LL_DMA_ISR_GIF7 DMA_ISR_GIF7
212#define LL_DMA_ISR_TCIF7 DMA_ISR_TCIF7
213#define LL_DMA_ISR_HTIF7 DMA_ISR_HTIF7
214#define LL_DMA_ISR_TEIF7 DMA_ISR_TEIF7
223#define LL_DMA_CCR_TCIE DMA_CCR_TCIE
224#define LL_DMA_CCR_HTIE DMA_CCR_HTIE
225#define LL_DMA_CCR_TEIE DMA_CCR_TEIE
233#define LL_DMA_CHANNEL_1 0x00000001U
234#define LL_DMA_CHANNEL_2 0x00000002U
235#define LL_DMA_CHANNEL_3 0x00000003U
236#define LL_DMA_CHANNEL_4 0x00000004U
237#define LL_DMA_CHANNEL_5 0x00000005U
238#define LL_DMA_CHANNEL_6 0x00000006U
239#define LL_DMA_CHANNEL_7 0x00000007U
240#if defined(USE_FULL_LL_DRIVER)
241#define LL_DMA_CHANNEL_ALL 0xFFFF0000U
242#endif /*USE_FULL_LL_DRIVER*/
250#define LL_DMA_DIRECTION_PERIPH_TO_MEMORY 0x00000000U
251#define LL_DMA_DIRECTION_MEMORY_TO_PERIPH DMA_CCR_DIR
252#define LL_DMA_DIRECTION_MEMORY_TO_MEMORY DMA_CCR_MEM2MEM
260#define LL_DMA_MODE_NORMAL 0x00000000U
261#define LL_DMA_MODE_CIRCULAR DMA_CCR_CIRC
269#define LL_DMA_PERIPH_INCREMENT DMA_CCR_PINC
270#define LL_DMA_PERIPH_NOINCREMENT 0x00000000U
278#define LL_DMA_MEMORY_INCREMENT DMA_CCR_MINC
279#define LL_DMA_MEMORY_NOINCREMENT 0x00000000U
287#define LL_DMA_PDATAALIGN_BYTE 0x00000000U
288#define LL_DMA_PDATAALIGN_HALFWORD DMA_CCR_PSIZE_0
289#define LL_DMA_PDATAALIGN_WORD DMA_CCR_PSIZE_1
297#define LL_DMA_MDATAALIGN_BYTE 0x00000000U
298#define LL_DMA_MDATAALIGN_HALFWORD DMA_CCR_MSIZE_0
299#define LL_DMA_MDATAALIGN_WORD DMA_CCR_MSIZE_1
307#define LL_DMA_PRIORITY_LOW 0x00000000U
308#define LL_DMA_PRIORITY_MEDIUM DMA_CCR_PL_0
309#define LL_DMA_PRIORITY_HIGH DMA_CCR_PL_1
310#define LL_DMA_PRIORITY_VERYHIGH DMA_CCR_PL
320/* Exported macro ------------------------------------------------------------*/
335#define LL_DMA_WriteReg(__INSTANCE__, __REG__, __VALUE__) WRITE_REG(__INSTANCE__->__REG__, (__VALUE__))
336
343#define LL_DMA_ReadReg(__INSTANCE__, __REG__) READ_REG(__INSTANCE__->__REG__)
356#if defined(DMA2)
357#define __LL_DMA_GET_INSTANCE(__CHANNEL_INSTANCE__) \
358(((uint32_t)(__CHANNEL_INSTANCE__) > ((uint32_t)DMA1_Channel7)) ? DMA2 : DMA1)
359#else
360#define __LL_DMA_GET_INSTANCE(__CHANNEL_INSTANCE__) (DMA1)
361#endif
362
368#if defined (DMA2)
369#if defined (DMA2_Channel6) && defined (DMA2_Channel7)
370#define __LL_DMA_GET_CHANNEL(__CHANNEL_INSTANCE__) \
371(((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)DMA1_Channel1)) ? LL_DMA_CHANNEL_1 : \
372 ((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)DMA2_Channel1)) ? LL_DMA_CHANNEL_1 : \
373 ((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)DMA1_Channel2)) ? LL_DMA_CHANNEL_2 : \
374 ((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)DMA2_Channel2)) ? LL_DMA_CHANNEL_2 : \
375 ((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)DMA1_Channel3)) ? LL_DMA_CHANNEL_3 : \
376 ((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)DMA2_Channel3)) ? LL_DMA_CHANNEL_3 : \
377 ((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)DMA1_Channel4)) ? LL_DMA_CHANNEL_4 : \
378 ((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)DMA2_Channel4)) ? LL_DMA_CHANNEL_4 : \
379 ((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)DMA1_Channel5)) ? LL_DMA_CHANNEL_5 : \
380 ((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)DMA2_Channel5)) ? LL_DMA_CHANNEL_5 : \
381 ((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)DMA1_Channel6)) ? LL_DMA_CHANNEL_6 : \
382 ((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)DMA2_Channel6)) ? LL_DMA_CHANNEL_6 : \
383 LL_DMA_CHANNEL_7)
384#else
385#define __LL_DMA_GET_CHANNEL(__CHANNEL_INSTANCE__) \
386(((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)DMA1_Channel1)) ? LL_DMA_CHANNEL_1 : \
387 ((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)DMA2_Channel1)) ? LL_DMA_CHANNEL_1 : \
388 ((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)DMA1_Channel2)) ? LL_DMA_CHANNEL_2 : \
389 ((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)DMA2_Channel2)) ? LL_DMA_CHANNEL_2 : \
390 ((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)DMA1_Channel3)) ? LL_DMA_CHANNEL_3 : \
391 ((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)DMA2_Channel3)) ? LL_DMA_CHANNEL_3 : \
392 ((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)DMA1_Channel4)) ? LL_DMA_CHANNEL_4 : \
393 ((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)DMA2_Channel4)) ? LL_DMA_CHANNEL_4 : \
394 ((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)DMA1_Channel5)) ? LL_DMA_CHANNEL_5 : \
395 ((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)DMA2_Channel5)) ? LL_DMA_CHANNEL_5 : \
396 ((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)DMA1_Channel6)) ? LL_DMA_CHANNEL_6 : \
397 LL_DMA_CHANNEL_7)
398#endif
399#else
400#define __LL_DMA_GET_CHANNEL(__CHANNEL_INSTANCE__) \
401(((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)DMA1_Channel1)) ? LL_DMA_CHANNEL_1 : \
402 ((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)DMA1_Channel2)) ? LL_DMA_CHANNEL_2 : \
403 ((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)DMA1_Channel3)) ? LL_DMA_CHANNEL_3 : \
404 ((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)DMA1_Channel4)) ? LL_DMA_CHANNEL_4 : \
405 ((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)DMA1_Channel5)) ? LL_DMA_CHANNEL_5 : \
406 ((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)DMA1_Channel6)) ? LL_DMA_CHANNEL_6 : \
407 LL_DMA_CHANNEL_7)
408#endif
409
416#if defined (DMA2)
417#if defined (DMA2_Channel6) && defined (DMA2_Channel7)
418#define __LL_DMA_GET_CHANNEL_INSTANCE(__DMA_INSTANCE__, __CHANNEL__) \
419((((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA1)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_1))) ? DMA1_Channel1 : \
420 (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA2)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_1))) ? DMA2_Channel1 : \
421 (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA1)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_2))) ? DMA1_Channel2 : \
422 (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA2)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_2))) ? DMA2_Channel2 : \
423 (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA1)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_3))) ? DMA1_Channel3 : \
424 (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA2)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_3))) ? DMA2_Channel3 : \
425 (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA1)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_4))) ? DMA1_Channel4 : \
426 (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA2)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_4))) ? DMA2_Channel4 : \
427 (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA1)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_5))) ? DMA1_Channel5 : \
428 (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA2)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_5))) ? DMA2_Channel5 : \
429 (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA1)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_6))) ? DMA1_Channel6 : \
430 (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA2)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_6))) ? DMA2_Channel6 : \
431 (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA1)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_7))) ? DMA1_Channel7 : \
432 DMA2_Channel7)
433#else
434#define __LL_DMA_GET_CHANNEL_INSTANCE(__DMA_INSTANCE__, __CHANNEL__) \
435((((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA1)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_1))) ? DMA1_Channel1 : \
436 (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA2)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_1))) ? DMA2_Channel1 : \
437 (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA1)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_2))) ? DMA1_Channel2 : \
438 (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA2)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_2))) ? DMA2_Channel2 : \
439 (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA1)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_3))) ? DMA1_Channel3 : \
440 (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA2)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_3))) ? DMA2_Channel3 : \
441 (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA1)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_4))) ? DMA1_Channel4 : \
442 (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA2)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_4))) ? DMA2_Channel4 : \
443 (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA1)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_5))) ? DMA1_Channel5 : \
444 (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA2)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_5))) ? DMA2_Channel5 : \
445 (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA1)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_6))) ? DMA1_Channel6 : \
446 DMA1_Channel7)
447#endif
448#else
449#define __LL_DMA_GET_CHANNEL_INSTANCE(__DMA_INSTANCE__, __CHANNEL__) \
450((((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA1)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_1))) ? DMA1_Channel1 : \
451 (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA1)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_2))) ? DMA1_Channel2 : \
452 (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA1)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_3))) ? DMA1_Channel3 : \
453 (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA1)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_4))) ? DMA1_Channel4 : \
454 (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA1)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_5))) ? DMA1_Channel5 : \
455 (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA1)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_6))) ? DMA1_Channel6 : \
456 DMA1_Channel7)
457#endif
458
467/* Exported functions --------------------------------------------------------*/
489__STATIC_INLINE void LL_DMA_EnableChannel(DMA_TypeDef *DMAx, uint32_t Channel)
490{
491 SET_BIT(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CCR, DMA_CCR_EN);
492}
493
508__STATIC_INLINE void LL_DMA_DisableChannel(DMA_TypeDef *DMAx, uint32_t Channel)
509{
510 CLEAR_BIT(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CCR, DMA_CCR_EN);
511}
512
527__STATIC_INLINE uint32_t LL_DMA_IsEnabledChannel(DMA_TypeDef *DMAx, uint32_t Channel)
528{
529 return (READ_BIT(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CCR,
530 DMA_CCR_EN) == (DMA_CCR_EN));
531}
532
562__STATIC_INLINE void LL_DMA_ConfigTransfer(DMA_TypeDef *DMAx, uint32_t Channel, uint32_t Configuration)
563{
564 MODIFY_REG(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CCR,
565 DMA_CCR_DIR | DMA_CCR_MEM2MEM | DMA_CCR_CIRC | DMA_CCR_PINC | DMA_CCR_MINC | DMA_CCR_PSIZE | DMA_CCR_MSIZE | DMA_CCR_PL,
566 Configuration);
567}
568
588__STATIC_INLINE void LL_DMA_SetDataTransferDirection(DMA_TypeDef *DMAx, uint32_t Channel, uint32_t Direction)
589{
590 MODIFY_REG(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CCR,
591 DMA_CCR_DIR | DMA_CCR_MEM2MEM, Direction);
592}
593
612__STATIC_INLINE uint32_t LL_DMA_GetDataTransferDirection(DMA_TypeDef *DMAx, uint32_t Channel)
613{
614 return (READ_BIT(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CCR,
615 DMA_CCR_DIR | DMA_CCR_MEM2MEM));
616}
617
637__STATIC_INLINE void LL_DMA_SetMode(DMA_TypeDef *DMAx, uint32_t Channel, uint32_t Mode)
638{
639 MODIFY_REG(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CCR, DMA_CCR_CIRC,
640 Mode);
641}
642
659__STATIC_INLINE uint32_t LL_DMA_GetMode(DMA_TypeDef *DMAx, uint32_t Channel)
660{
661 return (READ_BIT(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CCR,
662 DMA_CCR_CIRC));
663}
664
682__STATIC_INLINE void LL_DMA_SetPeriphIncMode(DMA_TypeDef *DMAx, uint32_t Channel, uint32_t PeriphOrM2MSrcIncMode)
683{
684 MODIFY_REG(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CCR, DMA_CCR_PINC,
685 PeriphOrM2MSrcIncMode);
686}
687
704__STATIC_INLINE uint32_t LL_DMA_GetPeriphIncMode(DMA_TypeDef *DMAx, uint32_t Channel)
705{
706 return (READ_BIT(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CCR,
707 DMA_CCR_PINC));
708}
709
727__STATIC_INLINE void LL_DMA_SetMemoryIncMode(DMA_TypeDef *DMAx, uint32_t Channel, uint32_t MemoryOrM2MDstIncMode)
728{
729 MODIFY_REG(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CCR, DMA_CCR_MINC,
730 MemoryOrM2MDstIncMode);
731}
732
749__STATIC_INLINE uint32_t LL_DMA_GetMemoryIncMode(DMA_TypeDef *DMAx, uint32_t Channel)
750{
751 return (READ_BIT(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CCR,
752 DMA_CCR_MINC));
753}
754
773__STATIC_INLINE void LL_DMA_SetPeriphSize(DMA_TypeDef *DMAx, uint32_t Channel, uint32_t PeriphOrM2MSrcDataSize)
774{
775 MODIFY_REG(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CCR, DMA_CCR_PSIZE,
776 PeriphOrM2MSrcDataSize);
777}
778
796__STATIC_INLINE uint32_t LL_DMA_GetPeriphSize(DMA_TypeDef *DMAx, uint32_t Channel)
797{
798 return (READ_BIT(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CCR,
799 DMA_CCR_PSIZE));
800}
801
820__STATIC_INLINE void LL_DMA_SetMemorySize(DMA_TypeDef *DMAx, uint32_t Channel, uint32_t MemoryOrM2MDstDataSize)
821{
822 MODIFY_REG(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CCR, DMA_CCR_MSIZE,
823 MemoryOrM2MDstDataSize);
824}
825
843__STATIC_INLINE uint32_t LL_DMA_GetMemorySize(DMA_TypeDef *DMAx, uint32_t Channel)
844{
845 return (READ_BIT(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CCR,
846 DMA_CCR_MSIZE));
847}
848
868__STATIC_INLINE void LL_DMA_SetChannelPriorityLevel(DMA_TypeDef *DMAx, uint32_t Channel, uint32_t Priority)
869{
870 MODIFY_REG(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CCR, DMA_CCR_PL,
871 Priority);
872}
873
892__STATIC_INLINE uint32_t LL_DMA_GetChannelPriorityLevel(DMA_TypeDef *DMAx, uint32_t Channel)
893{
894 return (READ_BIT(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CCR,
895 DMA_CCR_PL));
896}
897
915__STATIC_INLINE void LL_DMA_SetDataLength(DMA_TypeDef *DMAx, uint32_t Channel, uint32_t NbData)
916{
917 MODIFY_REG(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CNDTR,
918 DMA_CNDTR_NDT, NbData);
919}
920
937__STATIC_INLINE uint32_t LL_DMA_GetDataLength(DMA_TypeDef *DMAx, uint32_t Channel)
938{
939 return (READ_BIT(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CNDTR,
940 DMA_CNDTR_NDT));
941}
942
966__STATIC_INLINE void LL_DMA_ConfigAddresses(DMA_TypeDef *DMAx, uint32_t Channel, uint32_t SrcAddress,
967 uint32_t DstAddress, uint32_t Direction)
968{
969 /* Direction Memory to Periph */
970 if (Direction == LL_DMA_DIRECTION_MEMORY_TO_PERIPH)
971 {
972 WRITE_REG(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CMAR, SrcAddress);
973 WRITE_REG(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CPAR, DstAddress);
974 }
975 /* Direction Periph to Memory and Memory to Memory */
976 else
977 {
978 WRITE_REG(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CPAR, SrcAddress);
979 WRITE_REG(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CMAR, DstAddress);
980 }
981}
982
1000__STATIC_INLINE void LL_DMA_SetMemoryAddress(DMA_TypeDef *DMAx, uint32_t Channel, uint32_t MemoryAddress)
1001{
1002 WRITE_REG(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CMAR, MemoryAddress);
1003}
1004
1022__STATIC_INLINE void LL_DMA_SetPeriphAddress(DMA_TypeDef *DMAx, uint32_t Channel, uint32_t PeriphAddress)
1023{
1024 WRITE_REG(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CPAR, PeriphAddress);
1025}
1026
1042__STATIC_INLINE uint32_t LL_DMA_GetMemoryAddress(DMA_TypeDef *DMAx, uint32_t Channel)
1043{
1044 return (READ_REG(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CMAR));
1045}
1046
1062__STATIC_INLINE uint32_t LL_DMA_GetPeriphAddress(DMA_TypeDef *DMAx, uint32_t Channel)
1063{
1064 return (READ_REG(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CPAR));
1065}
1066
1084__STATIC_INLINE void LL_DMA_SetM2MSrcAddress(DMA_TypeDef *DMAx, uint32_t Channel, uint32_t MemoryAddress)
1085{
1086 WRITE_REG(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CPAR, MemoryAddress);
1087}
1088
1106__STATIC_INLINE void LL_DMA_SetM2MDstAddress(DMA_TypeDef *DMAx, uint32_t Channel, uint32_t MemoryAddress)
1107{
1108 WRITE_REG(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CMAR, MemoryAddress);
1109}
1110
1126__STATIC_INLINE uint32_t LL_DMA_GetM2MSrcAddress(DMA_TypeDef *DMAx, uint32_t Channel)
1127{
1128 return (READ_REG(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CPAR));
1129}
1130
1146__STATIC_INLINE uint32_t LL_DMA_GetM2MDstAddress(DMA_TypeDef *DMAx, uint32_t Channel)
1147{
1148 return (READ_REG(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CMAR));
1149}
1150
1151
1166__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_GI1(DMA_TypeDef *DMAx)
1167{
1168 return (READ_BIT(DMAx->ISR, DMA_ISR_GIF1) == (DMA_ISR_GIF1));
1169}
1170
1177__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_GI2(DMA_TypeDef *DMAx)
1178{
1179 return (READ_BIT(DMAx->ISR, DMA_ISR_GIF2) == (DMA_ISR_GIF2));
1180}
1181
1188__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_GI3(DMA_TypeDef *DMAx)
1189{
1190 return (READ_BIT(DMAx->ISR, DMA_ISR_GIF3) == (DMA_ISR_GIF3));
1191}
1192
1199__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_GI4(DMA_TypeDef *DMAx)
1200{
1201 return (READ_BIT(DMAx->ISR, DMA_ISR_GIF4) == (DMA_ISR_GIF4));
1202}
1203
1210__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_GI5(DMA_TypeDef *DMAx)
1211{
1212 return (READ_BIT(DMAx->ISR, DMA_ISR_GIF5) == (DMA_ISR_GIF5));
1213}
1214
1221__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_GI6(DMA_TypeDef *DMAx)
1222{
1223 return (READ_BIT(DMAx->ISR, DMA_ISR_GIF6) == (DMA_ISR_GIF6));
1224}
1225
1232__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_GI7(DMA_TypeDef *DMAx)
1233{
1234 return (READ_BIT(DMAx->ISR, DMA_ISR_GIF7) == (DMA_ISR_GIF7));
1235}
1236
1243__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TC1(DMA_TypeDef *DMAx)
1244{
1245 return (READ_BIT(DMAx->ISR, DMA_ISR_TCIF1) == (DMA_ISR_TCIF1));
1246}
1247
1254__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TC2(DMA_TypeDef *DMAx)
1255{
1256 return (READ_BIT(DMAx->ISR, DMA_ISR_TCIF2) == (DMA_ISR_TCIF2));
1257}
1258
1265__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TC3(DMA_TypeDef *DMAx)
1266{
1267 return (READ_BIT(DMAx->ISR, DMA_ISR_TCIF3) == (DMA_ISR_TCIF3));
1268}
1269
1276__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TC4(DMA_TypeDef *DMAx)
1277{
1278 return (READ_BIT(DMAx->ISR, DMA_ISR_TCIF4) == (DMA_ISR_TCIF4));
1279}
1280
1287__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TC5(DMA_TypeDef *DMAx)
1288{
1289 return (READ_BIT(DMAx->ISR, DMA_ISR_TCIF5) == (DMA_ISR_TCIF5));
1290}
1291
1298__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TC6(DMA_TypeDef *DMAx)
1299{
1300 return (READ_BIT(DMAx->ISR, DMA_ISR_TCIF6) == (DMA_ISR_TCIF6));
1301}
1302
1309__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TC7(DMA_TypeDef *DMAx)
1310{
1311 return (READ_BIT(DMAx->ISR, DMA_ISR_TCIF7) == (DMA_ISR_TCIF7));
1312}
1313
1320__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_HT1(DMA_TypeDef *DMAx)
1321{
1322 return (READ_BIT(DMAx->ISR, DMA_ISR_HTIF1) == (DMA_ISR_HTIF1));
1323}
1324
1331__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_HT2(DMA_TypeDef *DMAx)
1332{
1333 return (READ_BIT(DMAx->ISR, DMA_ISR_HTIF2) == (DMA_ISR_HTIF2));
1334}
1335
1342__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_HT3(DMA_TypeDef *DMAx)
1343{
1344 return (READ_BIT(DMAx->ISR, DMA_ISR_HTIF3) == (DMA_ISR_HTIF3));
1345}
1346
1353__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_HT4(DMA_TypeDef *DMAx)
1354{
1355 return (READ_BIT(DMAx->ISR, DMA_ISR_HTIF4) == (DMA_ISR_HTIF4));
1356}
1357
1364__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_HT5(DMA_TypeDef *DMAx)
1365{
1366 return (READ_BIT(DMAx->ISR, DMA_ISR_HTIF5) == (DMA_ISR_HTIF5));
1367}
1368
1375__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_HT6(DMA_TypeDef *DMAx)
1376{
1377 return (READ_BIT(DMAx->ISR, DMA_ISR_HTIF6) == (DMA_ISR_HTIF6));
1378}
1379
1386__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_HT7(DMA_TypeDef *DMAx)
1387{
1388 return (READ_BIT(DMAx->ISR, DMA_ISR_HTIF7) == (DMA_ISR_HTIF7));
1389}
1390
1397__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TE1(DMA_TypeDef *DMAx)
1398{
1399 return (READ_BIT(DMAx->ISR, DMA_ISR_TEIF1) == (DMA_ISR_TEIF1));
1400}
1401
1408__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TE2(DMA_TypeDef *DMAx)
1409{
1410 return (READ_BIT(DMAx->ISR, DMA_ISR_TEIF2) == (DMA_ISR_TEIF2));
1411}
1412
1419__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TE3(DMA_TypeDef *DMAx)
1420{
1421 return (READ_BIT(DMAx->ISR, DMA_ISR_TEIF3) == (DMA_ISR_TEIF3));
1422}
1423
1430__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TE4(DMA_TypeDef *DMAx)
1431{
1432 return (READ_BIT(DMAx->ISR, DMA_ISR_TEIF4) == (DMA_ISR_TEIF4));
1433}
1434
1441__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TE5(DMA_TypeDef *DMAx)
1442{
1443 return (READ_BIT(DMAx->ISR, DMA_ISR_TEIF5) == (DMA_ISR_TEIF5));
1444}
1445
1452__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TE6(DMA_TypeDef *DMAx)
1453{
1454 return (READ_BIT(DMAx->ISR, DMA_ISR_TEIF6) == (DMA_ISR_TEIF6));
1455}
1456
1463__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TE7(DMA_TypeDef *DMAx)
1464{
1465 return (READ_BIT(DMAx->ISR, DMA_ISR_TEIF7) == (DMA_ISR_TEIF7));
1466}
1467
1474__STATIC_INLINE void LL_DMA_ClearFlag_GI1(DMA_TypeDef *DMAx)
1475{
1476 WRITE_REG(DMAx->IFCR, DMA_IFCR_CGIF1);
1477}
1478
1485__STATIC_INLINE void LL_DMA_ClearFlag_GI2(DMA_TypeDef *DMAx)
1486{
1487 WRITE_REG(DMAx->IFCR, DMA_IFCR_CGIF2);
1488}
1489
1496__STATIC_INLINE void LL_DMA_ClearFlag_GI3(DMA_TypeDef *DMAx)
1497{
1498 WRITE_REG(DMAx->IFCR, DMA_IFCR_CGIF3);
1499}
1500
1507__STATIC_INLINE void LL_DMA_ClearFlag_GI4(DMA_TypeDef *DMAx)
1508{
1509 WRITE_REG(DMAx->IFCR, DMA_IFCR_CGIF4);
1510}
1511
1518__STATIC_INLINE void LL_DMA_ClearFlag_GI5(DMA_TypeDef *DMAx)
1519{
1520 WRITE_REG(DMAx->IFCR, DMA_IFCR_CGIF5);
1521}
1522
1529__STATIC_INLINE void LL_DMA_ClearFlag_GI6(DMA_TypeDef *DMAx)
1530{
1531 WRITE_REG(DMAx->IFCR, DMA_IFCR_CGIF6);
1532}
1533
1540__STATIC_INLINE void LL_DMA_ClearFlag_GI7(DMA_TypeDef *DMAx)
1541{
1542 WRITE_REG(DMAx->IFCR, DMA_IFCR_CGIF7);
1543}
1544
1551__STATIC_INLINE void LL_DMA_ClearFlag_TC1(DMA_TypeDef *DMAx)
1552{
1553 WRITE_REG(DMAx->IFCR, DMA_IFCR_CTCIF1);
1554}
1555
1562__STATIC_INLINE void LL_DMA_ClearFlag_TC2(DMA_TypeDef *DMAx)
1563{
1564 WRITE_REG(DMAx->IFCR, DMA_IFCR_CTCIF2);
1565}
1566
1573__STATIC_INLINE void LL_DMA_ClearFlag_TC3(DMA_TypeDef *DMAx)
1574{
1575 WRITE_REG(DMAx->IFCR, DMA_IFCR_CTCIF3);
1576}
1577
1584__STATIC_INLINE void LL_DMA_ClearFlag_TC4(DMA_TypeDef *DMAx)
1585{
1586 WRITE_REG(DMAx->IFCR, DMA_IFCR_CTCIF4);
1587}
1588
1595__STATIC_INLINE void LL_DMA_ClearFlag_TC5(DMA_TypeDef *DMAx)
1596{
1597 WRITE_REG(DMAx->IFCR, DMA_IFCR_CTCIF5);
1598}
1599
1606__STATIC_INLINE void LL_DMA_ClearFlag_TC6(DMA_TypeDef *DMAx)
1607{
1608 WRITE_REG(DMAx->IFCR, DMA_IFCR_CTCIF6);
1609}
1610
1617__STATIC_INLINE void LL_DMA_ClearFlag_TC7(DMA_TypeDef *DMAx)
1618{
1619 WRITE_REG(DMAx->IFCR, DMA_IFCR_CTCIF7);
1620}
1621
1628__STATIC_INLINE void LL_DMA_ClearFlag_HT1(DMA_TypeDef *DMAx)
1629{
1630 WRITE_REG(DMAx->IFCR, DMA_IFCR_CHTIF1);
1631}
1632
1639__STATIC_INLINE void LL_DMA_ClearFlag_HT2(DMA_TypeDef *DMAx)
1640{
1641 WRITE_REG(DMAx->IFCR, DMA_IFCR_CHTIF2);
1642}
1643
1650__STATIC_INLINE void LL_DMA_ClearFlag_HT3(DMA_TypeDef *DMAx)
1651{
1652 WRITE_REG(DMAx->IFCR, DMA_IFCR_CHTIF3);
1653}
1654
1661__STATIC_INLINE void LL_DMA_ClearFlag_HT4(DMA_TypeDef *DMAx)
1662{
1663 WRITE_REG(DMAx->IFCR, DMA_IFCR_CHTIF4);
1664}
1665
1672__STATIC_INLINE void LL_DMA_ClearFlag_HT5(DMA_TypeDef *DMAx)
1673{
1674 WRITE_REG(DMAx->IFCR, DMA_IFCR_CHTIF5);
1675}
1676
1683__STATIC_INLINE void LL_DMA_ClearFlag_HT6(DMA_TypeDef *DMAx)
1684{
1685 WRITE_REG(DMAx->IFCR, DMA_IFCR_CHTIF6);
1686}
1687
1694__STATIC_INLINE void LL_DMA_ClearFlag_HT7(DMA_TypeDef *DMAx)
1695{
1696 WRITE_REG(DMAx->IFCR, DMA_IFCR_CHTIF7);
1697}
1698
1705__STATIC_INLINE void LL_DMA_ClearFlag_TE1(DMA_TypeDef *DMAx)
1706{
1707 WRITE_REG(DMAx->IFCR, DMA_IFCR_CTEIF1);
1708}
1709
1716__STATIC_INLINE void LL_DMA_ClearFlag_TE2(DMA_TypeDef *DMAx)
1717{
1718 WRITE_REG(DMAx->IFCR, DMA_IFCR_CTEIF2);
1719}
1720
1727__STATIC_INLINE void LL_DMA_ClearFlag_TE3(DMA_TypeDef *DMAx)
1728{
1729 WRITE_REG(DMAx->IFCR, DMA_IFCR_CTEIF3);
1730}
1731
1738__STATIC_INLINE void LL_DMA_ClearFlag_TE4(DMA_TypeDef *DMAx)
1739{
1740 WRITE_REG(DMAx->IFCR, DMA_IFCR_CTEIF4);
1741}
1742
1749__STATIC_INLINE void LL_DMA_ClearFlag_TE5(DMA_TypeDef *DMAx)
1750{
1751 WRITE_REG(DMAx->IFCR, DMA_IFCR_CTEIF5);
1752}
1753
1760__STATIC_INLINE void LL_DMA_ClearFlag_TE6(DMA_TypeDef *DMAx)
1761{
1762 WRITE_REG(DMAx->IFCR, DMA_IFCR_CTEIF6);
1763}
1764
1771__STATIC_INLINE void LL_DMA_ClearFlag_TE7(DMA_TypeDef *DMAx)
1772{
1773 WRITE_REG(DMAx->IFCR, DMA_IFCR_CTEIF7);
1774}
1775
1797__STATIC_INLINE void LL_DMA_EnableIT_TC(DMA_TypeDef *DMAx, uint32_t Channel)
1798{
1799 SET_BIT(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CCR, DMA_CCR_TCIE);
1800}
1801
1816__STATIC_INLINE void LL_DMA_EnableIT_HT(DMA_TypeDef *DMAx, uint32_t Channel)
1817{
1818 SET_BIT(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CCR, DMA_CCR_HTIE);
1819}
1820
1835__STATIC_INLINE void LL_DMA_EnableIT_TE(DMA_TypeDef *DMAx, uint32_t Channel)
1836{
1837 SET_BIT(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CCR, DMA_CCR_TEIE);
1838}
1839
1854__STATIC_INLINE void LL_DMA_DisableIT_TC(DMA_TypeDef *DMAx, uint32_t Channel)
1855{
1856 CLEAR_BIT(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CCR, DMA_CCR_TCIE);
1857}
1858
1873__STATIC_INLINE void LL_DMA_DisableIT_HT(DMA_TypeDef *DMAx, uint32_t Channel)
1874{
1875 CLEAR_BIT(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CCR, DMA_CCR_HTIE);
1876}
1877
1892__STATIC_INLINE void LL_DMA_DisableIT_TE(DMA_TypeDef *DMAx, uint32_t Channel)
1893{
1894 CLEAR_BIT(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CCR, DMA_CCR_TEIE);
1895}
1896
1911__STATIC_INLINE uint32_t LL_DMA_IsEnabledIT_TC(DMA_TypeDef *DMAx, uint32_t Channel)
1912{
1913 return (READ_BIT(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CCR,
1914 DMA_CCR_TCIE) == (DMA_CCR_TCIE));
1915}
1916
1931__STATIC_INLINE uint32_t LL_DMA_IsEnabledIT_HT(DMA_TypeDef *DMAx, uint32_t Channel)
1932{
1933 return (READ_BIT(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CCR,
1934 DMA_CCR_HTIE) == (DMA_CCR_HTIE));
1935}
1936
1951__STATIC_INLINE uint32_t LL_DMA_IsEnabledIT_TE(DMA_TypeDef *DMAx, uint32_t Channel)
1952{
1953 return (READ_BIT(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CCR,
1954 DMA_CCR_TEIE) == (DMA_CCR_TEIE));
1955}
1956
1961#if defined(USE_FULL_LL_DRIVER)
1966uint32_t LL_DMA_Init(DMA_TypeDef *DMAx, uint32_t Channel, LL_DMA_InitTypeDef *DMA_InitStruct);
1967uint32_t LL_DMA_DeInit(DMA_TypeDef *DMAx, uint32_t Channel);
1968void LL_DMA_StructInit(LL_DMA_InitTypeDef *DMA_InitStruct);
1969
1973#endif /* USE_FULL_LL_DRIVER */
1974
1983#endif /* DMA1 || DMA2 */
1984
1989#ifdef __cplusplus
1990}
1991#endif
1992
1993#endif /* __STM32F3xx_LL_DMA_H */
1994
__STATIC_INLINE
#define __STATIC_INLINE
Definition: cmsis_armcc.h:59
CLEAR_BIT
#define CLEAR_BIT(REG, BIT)
Definition: stm32f3xx.h:192
SET_BIT
#define SET_BIT(REG, BIT)
Definition: stm32f3xx.h:190
WRITE_REG
#define WRITE_REG(REG, VAL)
Definition: stm32f3xx.h:198
MODIFY_REG
#define MODIFY_REG(REG, CLEARMASK, SETMASK)
Definition: stm32f3xx.h:202
READ_BIT
#define READ_BIT(REG, BIT)
Definition: stm32f3xx.h:194
READ_REG
#define READ_REG(REG)
Definition: stm32f3xx.h:200
DMA_CCR_PINC
#define DMA_CCR_PINC
Definition: stm32f303xe.h:7044
DMA_IFCR_CGIF3
#define DMA_IFCR_CGIF3
Definition: stm32f303xe.h:6964
DMA_CCR_HTIE
#define DMA_CCR_HTIE
Definition: stm32f303xe.h:7032
DMA_ISR_TEIF4
#define DMA_ISR_TEIF4
Definition: stm32f303xe.h:6899
DMA_ISR_TCIF1
#define DMA_ISR_TCIF1
Definition: stm32f303xe.h:6857
DMA_CCR_PSIZE
#define DMA_CCR_PSIZE
Definition: stm32f303xe.h:7051
DMA_IFCR_CTEIF6
#define DMA_IFCR_CTEIF6
Definition: stm32f303xe.h:7009
DMA_ISR_TEIF1
#define DMA_ISR_TEIF1
Definition: stm32f303xe.h:6863
DMA_ISR_TCIF3
#define DMA_ISR_TCIF3
Definition: stm32f303xe.h:6881
DMA_ISR_TCIF6
#define DMA_ISR_TCIF6
Definition: stm32f303xe.h:6917
DMA_IFCR_CHTIF3
#define DMA_IFCR_CHTIF3
Definition: stm32f303xe.h:6970
DMA_ISR_GIF1
#define DMA_ISR_GIF1
Definition: stm32f303xe.h:6854
DMA_IFCR_CTCIF4
#define DMA_IFCR_CTCIF4
Definition: stm32f303xe.h:6979
DMA_IFCR_CHTIF5
#define DMA_IFCR_CHTIF5
Definition: stm32f303xe.h:6994
DMA_ISR_HTIF5
#define DMA_ISR_HTIF5
Definition: stm32f303xe.h:6908
DMA_CCR_TEIE
#define DMA_CCR_TEIE
Definition: stm32f303xe.h:7035
DMA_IFCR_CHTIF2
#define DMA_IFCR_CHTIF2
Definition: stm32f303xe.h:6958
DMA_IFCR_CTEIF7
#define DMA_IFCR_CTEIF7
Definition: stm32f303xe.h:7021
DMA_ISR_HTIF6
#define DMA_ISR_HTIF6
Definition: stm32f303xe.h:6920
DMA_ISR_TEIF5
#define DMA_ISR_TEIF5
Definition: stm32f303xe.h:6911
DMA_CCR_CIRC
#define DMA_CCR_CIRC
Definition: stm32f303xe.h:7041
DMA_ISR_GIF2
#define DMA_ISR_GIF2
Definition: stm32f303xe.h:6866
DMA_ISR_TCIF7
#define DMA_ISR_TCIF7
Definition: stm32f303xe.h:6929
DMA_CCR_MSIZE
#define DMA_CCR_MSIZE
Definition: stm32f303xe.h:7057
DMA_IFCR_CTEIF2
#define DMA_IFCR_CTEIF2
Definition: stm32f303xe.h:6961
DMA_ISR_HTIF3
#define DMA_ISR_HTIF3
Definition: stm32f303xe.h:6884
DMA_IFCR_CTEIF3
#define DMA_IFCR_CTEIF3
Definition: stm32f303xe.h:6973
DMA_ISR_TEIF2
#define DMA_ISR_TEIF2
Definition: stm32f303xe.h:6875
DMA_CCR_MEM2MEM
#define DMA_CCR_MEM2MEM
Definition: stm32f303xe.h:7069
DMA_ISR_TCIF5
#define DMA_ISR_TCIF5
Definition: stm32f303xe.h:6905
DMA_ISR_HTIF1
#define DMA_ISR_HTIF1
Definition: stm32f303xe.h:6860
DMA_IFCR_CTCIF1
#define DMA_IFCR_CTCIF1
Definition: stm32f303xe.h:6943
DMA_ISR_TCIF2
#define DMA_ISR_TCIF2
Definition: stm32f303xe.h:6869
DMA_IFCR_CHTIF1
#define DMA_IFCR_CHTIF1
Definition: stm32f303xe.h:6946
DMA_ISR_HTIF4
#define DMA_ISR_HTIF4
Definition: stm32f303xe.h:6896
DMA_IFCR_CTEIF5
#define DMA_IFCR_CTEIF5
Definition: stm32f303xe.h:6997
DMA_IFCR_CTEIF4
#define DMA_IFCR_CTEIF4
Definition: stm32f303xe.h:6985
DMA_IFCR_CGIF4
#define DMA_IFCR_CGIF4
Definition: stm32f303xe.h:6976
DMA_IFCR_CGIF1
#define DMA_IFCR_CGIF1
Definition: stm32f303xe.h:6940
DMA_ISR_HTIF7
#define DMA_ISR_HTIF7
Definition: stm32f303xe.h:6932
DMA_IFCR_CGIF6
#define DMA_IFCR_CGIF6
Definition: stm32f303xe.h:7000
DMA_ISR_GIF5
#define DMA_ISR_GIF5
Definition: stm32f303xe.h:6902
DMA_IFCR_CTCIF2
#define DMA_IFCR_CTCIF2
Definition: stm32f303xe.h:6955
DMA_ISR_GIF7
#define DMA_ISR_GIF7
Definition: stm32f303xe.h:6926
DMA_ISR_HTIF2
#define DMA_ISR_HTIF2
Definition: stm32f303xe.h:6872
DMA_CCR_DIR
#define DMA_CCR_DIR
Definition: stm32f303xe.h:7038
DMA_IFCR_CGIF5
#define DMA_IFCR_CGIF5
Definition: stm32f303xe.h:6988
DMA_IFCR_CHTIF4
#define DMA_IFCR_CHTIF4
Definition: stm32f303xe.h:6982
DMA_CCR_PL
#define DMA_CCR_PL
Definition: stm32f303xe.h:7063
DMA_IFCR_CTEIF1
#define DMA_IFCR_CTEIF1
Definition: stm32f303xe.h:6949
DMA_CCR_MINC
#define DMA_CCR_MINC
Definition: stm32f303xe.h:7047
DMA_ISR_TEIF3
#define DMA_ISR_TEIF3
Definition: stm32f303xe.h:6887
DMA_IFCR_CHTIF7
#define DMA_IFCR_CHTIF7
Definition: stm32f303xe.h:7018
DMA_CCR_TCIE
#define DMA_CCR_TCIE
Definition: stm32f303xe.h:7029
DMA_IFCR_CGIF7
#define DMA_IFCR_CGIF7
Definition: stm32f303xe.h:7012
DMA_IFCR_CTCIF5
#define DMA_IFCR_CTCIF5
Definition: stm32f303xe.h:6991
DMA_IFCR_CGIF2
#define DMA_IFCR_CGIF2
Definition: stm32f303xe.h:6952
DMA_CCR_EN
#define DMA_CCR_EN
Definition: stm32f303xe.h:7026
DMA_IFCR_CTCIF7
#define DMA_IFCR_CTCIF7
Definition: stm32f303xe.h:7015
DMA_IFCR_CTCIF6
#define DMA_IFCR_CTCIF6
Definition: stm32f303xe.h:7003
DMA_ISR_GIF6
#define DMA_ISR_GIF6
Definition: stm32f303xe.h:6914
DMA_ISR_GIF3
#define DMA_ISR_GIF3
Definition: stm32f303xe.h:6878
DMA_IFCR_CTCIF3
#define DMA_IFCR_CTCIF3
Definition: stm32f303xe.h:6967
DMA_CNDTR_NDT
#define DMA_CNDTR_NDT
Definition: stm32f303xe.h:7074
DMA_ISR_TCIF4
#define DMA_ISR_TCIF4
Definition: stm32f303xe.h:6893
DMA_ISR_TEIF6
#define DMA_ISR_TEIF6
Definition: stm32f303xe.h:6923
DMA_IFCR_CHTIF6
#define DMA_IFCR_CHTIF6
Definition: stm32f303xe.h:7006
DMA_ISR_GIF4
#define DMA_ISR_GIF4
Definition: stm32f303xe.h:6890
DMA_ISR_TEIF7
#define DMA_ISR_TEIF7
Definition: stm32f303xe.h:6935
DMA1_Channel4_BASE
#define DMA1_Channel4_BASE
Definition: stm32f303xe.h:850
DMA1_Channel2_BASE
#define DMA1_Channel2_BASE
Definition: stm32f303xe.h:848
DMA1_Channel3_BASE
#define DMA1_Channel3_BASE
Definition: stm32f303xe.h:849
DMA1_Channel1_BASE
#define DMA1_Channel1_BASE
Definition: stm32f303xe.h:847
DMA1_Channel6_BASE
#define DMA1_Channel6_BASE
Definition: stm32f303xe.h:852
DMA1_BASE
#define DMA1_BASE
Definition: stm32f303xe.h:846
DMA1_Channel5_BASE
#define DMA1_Channel5_BASE
Definition: stm32f303xe.h:851
DMA1_Channel7_BASE
#define DMA1_Channel7_BASE
Definition: stm32f303xe.h:853
stm32f3xx.h
CMSIS STM32F3xx Device Peripheral Access Layer Header File.
DMA_Channel_TypeDef
DMA Controller.
Definition: stm32f303xe.h:349
DMA_TypeDef
Definition: stm32f303xe.h:357
DMA_TypeDef::IFCR
__IO uint32_t IFCR
Definition: stm32f303xe.h:359
DMA_TypeDef::ISR
__IO uint32_t ISR
Definition: stm32f303xe.h:358