20#ifndef __STM32F3xx_LL_DMA_H
21#define __STM32F3xx_LL_DMA_H
34#if defined (DMA1) || defined (DMA2)
46static const uint8_t CHANNEL_OFFSET_TAB[] =
62#if defined(USE_FULL_LL_DRIVER)
72#if defined(USE_FULL_LL_DRIVER)
78 uint32_t PeriphOrM2MSrcAddress;
83 uint32_t MemoryOrM2MDstAddress;
101 uint32_t PeriphOrM2MSrcIncMode;
107 uint32_t MemoryOrM2MDstIncMode;
113 uint32_t PeriphOrM2MSrcDataSize;
119 uint32_t MemoryOrM2MDstDataSize;
151#define LL_DMA_IFCR_CGIF1 DMA_IFCR_CGIF1
152#define LL_DMA_IFCR_CTCIF1 DMA_IFCR_CTCIF1
153#define LL_DMA_IFCR_CHTIF1 DMA_IFCR_CHTIF1
154#define LL_DMA_IFCR_CTEIF1 DMA_IFCR_CTEIF1
155#define LL_DMA_IFCR_CGIF2 DMA_IFCR_CGIF2
156#define LL_DMA_IFCR_CTCIF2 DMA_IFCR_CTCIF2
157#define LL_DMA_IFCR_CHTIF2 DMA_IFCR_CHTIF2
158#define LL_DMA_IFCR_CTEIF2 DMA_IFCR_CTEIF2
159#define LL_DMA_IFCR_CGIF3 DMA_IFCR_CGIF3
160#define LL_DMA_IFCR_CTCIF3 DMA_IFCR_CTCIF3
161#define LL_DMA_IFCR_CHTIF3 DMA_IFCR_CHTIF3
162#define LL_DMA_IFCR_CTEIF3 DMA_IFCR_CTEIF3
163#define LL_DMA_IFCR_CGIF4 DMA_IFCR_CGIF4
164#define LL_DMA_IFCR_CTCIF4 DMA_IFCR_CTCIF4
165#define LL_DMA_IFCR_CHTIF4 DMA_IFCR_CHTIF4
166#define LL_DMA_IFCR_CTEIF4 DMA_IFCR_CTEIF4
167#define LL_DMA_IFCR_CGIF5 DMA_IFCR_CGIF5
168#define LL_DMA_IFCR_CTCIF5 DMA_IFCR_CTCIF5
169#define LL_DMA_IFCR_CHTIF5 DMA_IFCR_CHTIF5
170#define LL_DMA_IFCR_CTEIF5 DMA_IFCR_CTEIF5
171#define LL_DMA_IFCR_CGIF6 DMA_IFCR_CGIF6
172#define LL_DMA_IFCR_CTCIF6 DMA_IFCR_CTCIF6
173#define LL_DMA_IFCR_CHTIF6 DMA_IFCR_CHTIF6
174#define LL_DMA_IFCR_CTEIF6 DMA_IFCR_CTEIF6
175#define LL_DMA_IFCR_CGIF7 DMA_IFCR_CGIF7
176#define LL_DMA_IFCR_CTCIF7 DMA_IFCR_CTCIF7
177#define LL_DMA_IFCR_CHTIF7 DMA_IFCR_CHTIF7
178#define LL_DMA_IFCR_CTEIF7 DMA_IFCR_CTEIF7
187#define LL_DMA_ISR_GIF1 DMA_ISR_GIF1
188#define LL_DMA_ISR_TCIF1 DMA_ISR_TCIF1
189#define LL_DMA_ISR_HTIF1 DMA_ISR_HTIF1
190#define LL_DMA_ISR_TEIF1 DMA_ISR_TEIF1
191#define LL_DMA_ISR_GIF2 DMA_ISR_GIF2
192#define LL_DMA_ISR_TCIF2 DMA_ISR_TCIF2
193#define LL_DMA_ISR_HTIF2 DMA_ISR_HTIF2
194#define LL_DMA_ISR_TEIF2 DMA_ISR_TEIF2
195#define LL_DMA_ISR_GIF3 DMA_ISR_GIF3
196#define LL_DMA_ISR_TCIF3 DMA_ISR_TCIF3
197#define LL_DMA_ISR_HTIF3 DMA_ISR_HTIF3
198#define LL_DMA_ISR_TEIF3 DMA_ISR_TEIF3
199#define LL_DMA_ISR_GIF4 DMA_ISR_GIF4
200#define LL_DMA_ISR_TCIF4 DMA_ISR_TCIF4
201#define LL_DMA_ISR_HTIF4 DMA_ISR_HTIF4
202#define LL_DMA_ISR_TEIF4 DMA_ISR_TEIF4
203#define LL_DMA_ISR_GIF5 DMA_ISR_GIF5
204#define LL_DMA_ISR_TCIF5 DMA_ISR_TCIF5
205#define LL_DMA_ISR_HTIF5 DMA_ISR_HTIF5
206#define LL_DMA_ISR_TEIF5 DMA_ISR_TEIF5
207#define LL_DMA_ISR_GIF6 DMA_ISR_GIF6
208#define LL_DMA_ISR_TCIF6 DMA_ISR_TCIF6
209#define LL_DMA_ISR_HTIF6 DMA_ISR_HTIF6
210#define LL_DMA_ISR_TEIF6 DMA_ISR_TEIF6
211#define LL_DMA_ISR_GIF7 DMA_ISR_GIF7
212#define LL_DMA_ISR_TCIF7 DMA_ISR_TCIF7
213#define LL_DMA_ISR_HTIF7 DMA_ISR_HTIF7
214#define LL_DMA_ISR_TEIF7 DMA_ISR_TEIF7
223#define LL_DMA_CCR_TCIE DMA_CCR_TCIE
224#define LL_DMA_CCR_HTIE DMA_CCR_HTIE
225#define LL_DMA_CCR_TEIE DMA_CCR_TEIE
233#define LL_DMA_CHANNEL_1 0x00000001U
234#define LL_DMA_CHANNEL_2 0x00000002U
235#define LL_DMA_CHANNEL_3 0x00000003U
236#define LL_DMA_CHANNEL_4 0x00000004U
237#define LL_DMA_CHANNEL_5 0x00000005U
238#define LL_DMA_CHANNEL_6 0x00000006U
239#define LL_DMA_CHANNEL_7 0x00000007U
240#if defined(USE_FULL_LL_DRIVER)
241#define LL_DMA_CHANNEL_ALL 0xFFFF0000U
250#define LL_DMA_DIRECTION_PERIPH_TO_MEMORY 0x00000000U
251#define LL_DMA_DIRECTION_MEMORY_TO_PERIPH DMA_CCR_DIR
252#define LL_DMA_DIRECTION_MEMORY_TO_MEMORY DMA_CCR_MEM2MEM
260#define LL_DMA_MODE_NORMAL 0x00000000U
261#define LL_DMA_MODE_CIRCULAR DMA_CCR_CIRC
269#define LL_DMA_PERIPH_INCREMENT DMA_CCR_PINC
270#define LL_DMA_PERIPH_NOINCREMENT 0x00000000U
278#define LL_DMA_MEMORY_INCREMENT DMA_CCR_MINC
279#define LL_DMA_MEMORY_NOINCREMENT 0x00000000U
287#define LL_DMA_PDATAALIGN_BYTE 0x00000000U
288#define LL_DMA_PDATAALIGN_HALFWORD DMA_CCR_PSIZE_0
289#define LL_DMA_PDATAALIGN_WORD DMA_CCR_PSIZE_1
297#define LL_DMA_MDATAALIGN_BYTE 0x00000000U
298#define LL_DMA_MDATAALIGN_HALFWORD DMA_CCR_MSIZE_0
299#define LL_DMA_MDATAALIGN_WORD DMA_CCR_MSIZE_1
307#define LL_DMA_PRIORITY_LOW 0x00000000U
308#define LL_DMA_PRIORITY_MEDIUM DMA_CCR_PL_0
309#define LL_DMA_PRIORITY_HIGH DMA_CCR_PL_1
310#define LL_DMA_PRIORITY_VERYHIGH DMA_CCR_PL
335#define LL_DMA_WriteReg(__INSTANCE__, __REG__, __VALUE__) WRITE_REG(__INSTANCE__->__REG__, (__VALUE__))
343#define LL_DMA_ReadReg(__INSTANCE__, __REG__) READ_REG(__INSTANCE__->__REG__)
357#define __LL_DMA_GET_INSTANCE(__CHANNEL_INSTANCE__) \
358(((uint32_t)(__CHANNEL_INSTANCE__) > ((uint32_t)DMA1_Channel7)) ? DMA2 : DMA1)
360#define __LL_DMA_GET_INSTANCE(__CHANNEL_INSTANCE__) (DMA1)
369#if defined (DMA2_Channel6) && defined (DMA2_Channel7)
370#define __LL_DMA_GET_CHANNEL(__CHANNEL_INSTANCE__) \
371(((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)DMA1_Channel1)) ? LL_DMA_CHANNEL_1 : \
372 ((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)DMA2_Channel1)) ? LL_DMA_CHANNEL_1 : \
373 ((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)DMA1_Channel2)) ? LL_DMA_CHANNEL_2 : \
374 ((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)DMA2_Channel2)) ? LL_DMA_CHANNEL_2 : \
375 ((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)DMA1_Channel3)) ? LL_DMA_CHANNEL_3 : \
376 ((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)DMA2_Channel3)) ? LL_DMA_CHANNEL_3 : \
377 ((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)DMA1_Channel4)) ? LL_DMA_CHANNEL_4 : \
378 ((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)DMA2_Channel4)) ? LL_DMA_CHANNEL_4 : \
379 ((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)DMA1_Channel5)) ? LL_DMA_CHANNEL_5 : \
380 ((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)DMA2_Channel5)) ? LL_DMA_CHANNEL_5 : \
381 ((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)DMA1_Channel6)) ? LL_DMA_CHANNEL_6 : \
382 ((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)DMA2_Channel6)) ? LL_DMA_CHANNEL_6 : \
385#define __LL_DMA_GET_CHANNEL(__CHANNEL_INSTANCE__) \
386(((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)DMA1_Channel1)) ? LL_DMA_CHANNEL_1 : \
387 ((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)DMA2_Channel1)) ? LL_DMA_CHANNEL_1 : \
388 ((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)DMA1_Channel2)) ? LL_DMA_CHANNEL_2 : \
389 ((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)DMA2_Channel2)) ? LL_DMA_CHANNEL_2 : \
390 ((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)DMA1_Channel3)) ? LL_DMA_CHANNEL_3 : \
391 ((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)DMA2_Channel3)) ? LL_DMA_CHANNEL_3 : \
392 ((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)DMA1_Channel4)) ? LL_DMA_CHANNEL_4 : \
393 ((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)DMA2_Channel4)) ? LL_DMA_CHANNEL_4 : \
394 ((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)DMA1_Channel5)) ? LL_DMA_CHANNEL_5 : \
395 ((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)DMA2_Channel5)) ? LL_DMA_CHANNEL_5 : \
396 ((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)DMA1_Channel6)) ? LL_DMA_CHANNEL_6 : \
400#define __LL_DMA_GET_CHANNEL(__CHANNEL_INSTANCE__) \
401(((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)DMA1_Channel1)) ? LL_DMA_CHANNEL_1 : \
402 ((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)DMA1_Channel2)) ? LL_DMA_CHANNEL_2 : \
403 ((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)DMA1_Channel3)) ? LL_DMA_CHANNEL_3 : \
404 ((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)DMA1_Channel4)) ? LL_DMA_CHANNEL_4 : \
405 ((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)DMA1_Channel5)) ? LL_DMA_CHANNEL_5 : \
406 ((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)DMA1_Channel6)) ? LL_DMA_CHANNEL_6 : \
417#if defined (DMA2_Channel6) && defined (DMA2_Channel7)
418#define __LL_DMA_GET_CHANNEL_INSTANCE(__DMA_INSTANCE__, __CHANNEL__) \
419((((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA1)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_1))) ? DMA1_Channel1 : \
420 (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA2)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_1))) ? DMA2_Channel1 : \
421 (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA1)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_2))) ? DMA1_Channel2 : \
422 (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA2)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_2))) ? DMA2_Channel2 : \
423 (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA1)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_3))) ? DMA1_Channel3 : \
424 (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA2)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_3))) ? DMA2_Channel3 : \
425 (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA1)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_4))) ? DMA1_Channel4 : \
426 (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA2)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_4))) ? DMA2_Channel4 : \
427 (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA1)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_5))) ? DMA1_Channel5 : \
428 (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA2)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_5))) ? DMA2_Channel5 : \
429 (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA1)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_6))) ? DMA1_Channel6 : \
430 (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA2)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_6))) ? DMA2_Channel6 : \
431 (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA1)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_7))) ? DMA1_Channel7 : \
434#define __LL_DMA_GET_CHANNEL_INSTANCE(__DMA_INSTANCE__, __CHANNEL__) \
435((((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA1)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_1))) ? DMA1_Channel1 : \
436 (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA2)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_1))) ? DMA2_Channel1 : \
437 (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA1)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_2))) ? DMA1_Channel2 : \
438 (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA2)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_2))) ? DMA2_Channel2 : \
439 (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA1)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_3))) ? DMA1_Channel3 : \
440 (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA2)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_3))) ? DMA2_Channel3 : \
441 (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA1)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_4))) ? DMA1_Channel4 : \
442 (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA2)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_4))) ? DMA2_Channel4 : \
443 (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA1)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_5))) ? DMA1_Channel5 : \
444 (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA2)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_5))) ? DMA2_Channel5 : \
445 (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA1)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_6))) ? DMA1_Channel6 : \
449#define __LL_DMA_GET_CHANNEL_INSTANCE(__DMA_INSTANCE__, __CHANNEL__) \
450((((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA1)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_1))) ? DMA1_Channel1 : \
451 (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA1)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_2))) ? DMA1_Channel2 : \
452 (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA1)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_3))) ? DMA1_Channel3 : \
453 (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA1)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_4))) ? DMA1_Channel4 : \
454 (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA1)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_5))) ? DMA1_Channel5 : \
455 (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA1)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_6))) ? DMA1_Channel6 : \
685 PeriphOrM2MSrcIncMode);
730 MemoryOrM2MDstIncMode);
776 PeriphOrM2MSrcDataSize);
823 MemoryOrM2MDstDataSize);
967 uint32_t DstAddress, uint32_t Direction)
970 if (Direction == LL_DMA_DIRECTION_MEMORY_TO_PERIPH)
1961#if defined(USE_FULL_LL_DRIVER)
1966uint32_t LL_DMA_Init(
DMA_TypeDef *DMAx, uint32_t Channel, LL_DMA_InitTypeDef *DMA_InitStruct);
1967uint32_t LL_DMA_DeInit(
DMA_TypeDef *DMAx, uint32_t Channel);
1968void LL_DMA_StructInit(LL_DMA_InitTypeDef *DMA_InitStruct);
#define __STATIC_INLINE
Definition: cmsis_armcc.h:59
#define CLEAR_BIT(REG, BIT)
Definition: stm32f3xx.h:192
#define SET_BIT(REG, BIT)
Definition: stm32f3xx.h:190
#define WRITE_REG(REG, VAL)
Definition: stm32f3xx.h:198
#define MODIFY_REG(REG, CLEARMASK, SETMASK)
Definition: stm32f3xx.h:202
#define READ_BIT(REG, BIT)
Definition: stm32f3xx.h:194
#define READ_REG(REG)
Definition: stm32f3xx.h:200
#define DMA_CCR_PINC
Definition: stm32f303xe.h:7044
#define DMA_IFCR_CGIF3
Definition: stm32f303xe.h:6964
#define DMA_CCR_HTIE
Definition: stm32f303xe.h:7032
#define DMA_ISR_TEIF4
Definition: stm32f303xe.h:6899
#define DMA_ISR_TCIF1
Definition: stm32f303xe.h:6857
#define DMA_CCR_PSIZE
Definition: stm32f303xe.h:7051
#define DMA_IFCR_CTEIF6
Definition: stm32f303xe.h:7009
#define DMA_ISR_TEIF1
Definition: stm32f303xe.h:6863
#define DMA_ISR_TCIF3
Definition: stm32f303xe.h:6881
#define DMA_ISR_TCIF6
Definition: stm32f303xe.h:6917
#define DMA_IFCR_CHTIF3
Definition: stm32f303xe.h:6970
#define DMA_ISR_GIF1
Definition: stm32f303xe.h:6854
#define DMA_IFCR_CTCIF4
Definition: stm32f303xe.h:6979
#define DMA_IFCR_CHTIF5
Definition: stm32f303xe.h:6994
#define DMA_ISR_HTIF5
Definition: stm32f303xe.h:6908
#define DMA_CCR_TEIE
Definition: stm32f303xe.h:7035
#define DMA_IFCR_CHTIF2
Definition: stm32f303xe.h:6958
#define DMA_IFCR_CTEIF7
Definition: stm32f303xe.h:7021
#define DMA_ISR_HTIF6
Definition: stm32f303xe.h:6920
#define DMA_ISR_TEIF5
Definition: stm32f303xe.h:6911
#define DMA_CCR_CIRC
Definition: stm32f303xe.h:7041
#define DMA_ISR_GIF2
Definition: stm32f303xe.h:6866
#define DMA_ISR_TCIF7
Definition: stm32f303xe.h:6929
#define DMA_CCR_MSIZE
Definition: stm32f303xe.h:7057
#define DMA_IFCR_CTEIF2
Definition: stm32f303xe.h:6961
#define DMA_ISR_HTIF3
Definition: stm32f303xe.h:6884
#define DMA_IFCR_CTEIF3
Definition: stm32f303xe.h:6973
#define DMA_ISR_TEIF2
Definition: stm32f303xe.h:6875
#define DMA_CCR_MEM2MEM
Definition: stm32f303xe.h:7069
#define DMA_ISR_TCIF5
Definition: stm32f303xe.h:6905
#define DMA_ISR_HTIF1
Definition: stm32f303xe.h:6860
#define DMA_IFCR_CTCIF1
Definition: stm32f303xe.h:6943
#define DMA_ISR_TCIF2
Definition: stm32f303xe.h:6869
#define DMA_IFCR_CHTIF1
Definition: stm32f303xe.h:6946
#define DMA_ISR_HTIF4
Definition: stm32f303xe.h:6896
#define DMA_IFCR_CTEIF5
Definition: stm32f303xe.h:6997
#define DMA_IFCR_CTEIF4
Definition: stm32f303xe.h:6985
#define DMA_IFCR_CGIF4
Definition: stm32f303xe.h:6976
#define DMA_IFCR_CGIF1
Definition: stm32f303xe.h:6940
#define DMA_ISR_HTIF7
Definition: stm32f303xe.h:6932
#define DMA_IFCR_CGIF6
Definition: stm32f303xe.h:7000
#define DMA_ISR_GIF5
Definition: stm32f303xe.h:6902
#define DMA_IFCR_CTCIF2
Definition: stm32f303xe.h:6955
#define DMA_ISR_GIF7
Definition: stm32f303xe.h:6926
#define DMA_ISR_HTIF2
Definition: stm32f303xe.h:6872
#define DMA_CCR_DIR
Definition: stm32f303xe.h:7038
#define DMA_IFCR_CGIF5
Definition: stm32f303xe.h:6988
#define DMA_IFCR_CHTIF4
Definition: stm32f303xe.h:6982
#define DMA_CCR_PL
Definition: stm32f303xe.h:7063
#define DMA_IFCR_CTEIF1
Definition: stm32f303xe.h:6949
#define DMA_CCR_MINC
Definition: stm32f303xe.h:7047
#define DMA_ISR_TEIF3
Definition: stm32f303xe.h:6887
#define DMA_IFCR_CHTIF7
Definition: stm32f303xe.h:7018
#define DMA_CCR_TCIE
Definition: stm32f303xe.h:7029
#define DMA_IFCR_CGIF7
Definition: stm32f303xe.h:7012
#define DMA_IFCR_CTCIF5
Definition: stm32f303xe.h:6991
#define DMA_IFCR_CGIF2
Definition: stm32f303xe.h:6952
#define DMA_CCR_EN
Definition: stm32f303xe.h:7026
#define DMA_IFCR_CTCIF7
Definition: stm32f303xe.h:7015
#define DMA_IFCR_CTCIF6
Definition: stm32f303xe.h:7003
#define DMA_ISR_GIF6
Definition: stm32f303xe.h:6914
#define DMA_ISR_GIF3
Definition: stm32f303xe.h:6878
#define DMA_IFCR_CTCIF3
Definition: stm32f303xe.h:6967
#define DMA_CNDTR_NDT
Definition: stm32f303xe.h:7074
#define DMA_ISR_TCIF4
Definition: stm32f303xe.h:6893
#define DMA_ISR_TEIF6
Definition: stm32f303xe.h:6923
#define DMA_IFCR_CHTIF6
Definition: stm32f303xe.h:7006
#define DMA_ISR_GIF4
Definition: stm32f303xe.h:6890
#define DMA_ISR_TEIF7
Definition: stm32f303xe.h:6935
#define DMA1_Channel4_BASE
Definition: stm32f303xe.h:850
#define DMA1_Channel2_BASE
Definition: stm32f303xe.h:848
#define DMA1_Channel3_BASE
Definition: stm32f303xe.h:849
#define DMA1_Channel1_BASE
Definition: stm32f303xe.h:847
#define DMA1_Channel6_BASE
Definition: stm32f303xe.h:852
#define DMA1_BASE
Definition: stm32f303xe.h:846
#define DMA1_Channel5_BASE
Definition: stm32f303xe.h:851
#define DMA1_Channel7_BASE
Definition: stm32f303xe.h:853
CMSIS STM32F3xx Device Peripheral Access Layer Header File.
DMA Controller.
Definition: stm32f303xe.h:349
Definition: stm32f303xe.h:357
__IO uint32_t IFCR
Definition: stm32f303xe.h:359
__IO uint32_t ISR
Definition: stm32f303xe.h:358