34#ifndef __STM32F3xx_LL_SYSTEM_H
35#define __STM32F3xx_LL_SYSTEM_H
48#if defined (FLASH) || defined (SYSCFG) || defined (DBGMCU)
63#define SYSCFG_OFFSET_CFGR1 0x00000000U
64#define SYSCFG_OFFSET_CFGR3 0x00000050U
67#if defined(SYSCFG_CFGR2_PVD_LOCK) && defined(SYSCFG_CFGR2_SRAM_PARITY_LOCK)
68#define SYSCFG_MASK_TIM_BREAK (SYSCFG_CFGR2_LOCKUP_LOCK | SYSCFG_CFGR2_SRAM_PARITY_LOCK | SYSCFG_CFGR2_PVD_LOCK)
69#elif defined(SYSCFG_CFGR2_PVD_LOCK) && !defined(SYSCFG_CFGR2_SRAM_PARITY_LOCK)
70#define SYSCFG_MASK_TIM_BREAK (SYSCFG_CFGR2_LOCKUP_LOCK | SYSCFG_CFGR2_PVD_LOCK)
71#elif !defined(SYSCFG_CFGR2_PVD_LOCK) && defined(SYSCFG_CFGR2_SRAM_PARITY_LOCK)
72#define SYSCFG_MASK_TIM_BREAK (SYSCFG_CFGR2_LOCKUP_LOCK | SYSCFG_CFGR2_SRAM_PARITY_LOCK)
74#define SYSCFG_MASK_TIM_BREAK (SYSCFG_CFGR2_LOCKUP_LOCK)
92#define LL_SYSCFG_REMAP_FLASH (uint32_t)0x00000000
93#define LL_SYSCFG_REMAP_SYSTEMFLASH SYSCFG_CFGR1_MEM_MODE_0
94#define LL_SYSCFG_REMAP_SRAM (SYSCFG_CFGR1_MEM_MODE_1 | SYSCFG_CFGR1_MEM_MODE_0)
96#define LL_SYSCFG_REMAP_FMC SYSCFG_CFGR1_MEM_MODE_2
102#if defined(SYSCFG_CFGR3_SPI1_RX_DMA_RMP)
106#define LL_SYSCFG_SPI1RX_RMP_DMA1_CH2 (SYSCFG_CFGR3_SPI1_RX_DMA_RMP << 16U | (uint32_t)0x00000000U)
107#define LL_SYSCFG_SPI1RX_RMP_DMA1_CH4 (SYSCFG_CFGR3_SPI1_RX_DMA_RMP << 16U | SYSCFG_CFGR3_SPI1_RX_DMA_RMP_0)
108#define LL_SYSCFG_SPI1RX_RMP_DMA1_CH6 (SYSCFG_CFGR3_SPI1_RX_DMA_RMP << 16U | SYSCFG_CFGR3_SPI1_RX_DMA_RMP_1)
109#define LL_SYSCFG_SPI1TX_RMP_DMA1_CH3 (SYSCFG_CFGR3_SPI1_TX_DMA_RMP << 16U | (uint32_t)0x00000000U)
110#define LL_SYSCFG_SPI1TX_RMP_DMA1_CH5 (SYSCFG_CFGR3_SPI1_TX_DMA_RMP << 16U | SYSCFG_CFGR3_SPI1_TX_DMA_RMP_0)
111#define LL_SYSCFG_SPI1TX_RMP_DMA1_CH7 (SYSCFG_CFGR3_SPI1_TX_DMA_RMP << 16U | SYSCFG_CFGR3_SPI1_TX_DMA_RMP_1)
117#if defined(SYSCFG_CFGR3_I2C1_RX_DMA_RMP)
121#define LL_SYSCFG_I2C1RX_RMP_DMA1_CH7 (SYSCFG_CFGR3_I2C1_RX_DMA_RMP << 16U | (uint32_t)0x00000000U)
122#define LL_SYSCFG_I2C1RX_RMP_DMA1_CH3 (SYSCFG_CFGR3_I2C1_RX_DMA_RMP << 16U | SYSCFG_CFGR3_I2C1_RX_DMA_RMP_0)
123#define LL_SYSCFG_I2C1RX_RMP_DMA1_CH5 (SYSCFG_CFGR3_I2C1_RX_DMA_RMP << 16U | SYSCFG_CFGR3_I2C1_RX_DMA_RMP_1)
124#define LL_SYSCFG_I2C1TX_RMP_DMA1_CH6 (SYSCFG_CFGR3_I2C1_TX_DMA_RMP << 16U | (uint32_t)0x00000000U)
125#define LL_SYSCFG_I2C1TX_RMP_DMA1_CH2 (SYSCFG_CFGR3_I2C1_TX_DMA_RMP << 16U | SYSCFG_CFGR3_I2C1_TX_DMA_RMP_0)
126#define LL_SYSCFG_I2C1TX_RMP_DMA1_CH4 (SYSCFG_CFGR3_I2C1_TX_DMA_RMP << 16U | SYSCFG_CFGR3_I2C1_TX_DMA_RMP_1)
133#if defined(SYSCFG_CFGR1_ADC24_DMA_RMP) || defined(SYSCFG_CFGR3_ADC2_DMA_RMP)
137#if defined (SYSCFG_CFGR1_ADC24_DMA_RMP)
138#define LL_SYSCFG_ADC24_RMP_DMA2_CH12 (SYSCFG_OFFSET_CFGR1 << 24U | SYSCFG_CFGR1_ADC24_DMA_RMP << 8U | (uint32_t)0x00000000U)
139#define LL_SYSCFG_ADC24_RMP_DMA2_CH34 (SYSCFG_OFFSET_CFGR1 << 24U | SYSCFG_CFGR1_ADC24_DMA_RMP << 8U | SYSCFG_CFGR1_ADC24_DMA_RMP)
141#if defined (SYSCFG_CFGR3_ADC2_DMA_RMP)
142#define LL_SYSCFG_ADC2_RMP_DMA1_CH2 (SYSCFG_OFFSET_CFGR3 << 24U | SYSCFG_CFGR3_ADC2_DMA_RMP_0 << 8U | (uint32_t)0x00000000U)
143#define LL_SYSCFG_ADC2_RMP_DMA1_CH4 (SYSCFG_OFFSET_CFGR3 << 24U | SYSCFG_CFGR3_ADC2_DMA_RMP_0 << 8U | SYSCFG_CFGR3_ADC2_DMA_RMP_0)
144#define LL_SYSCFG_ADC2_RMP_DMA2 (SYSCFG_OFFSET_CFGR3 << 24U | SYSCFG_CFGR3_ADC2_DMA_RMP_1 << 8U | (uint32_t)0x00000000U)
145#define LL_SYSCFG_ADC2_RMP_DMA1 (SYSCFG_OFFSET_CFGR3 << 24U | SYSCFG_CFGR3_ADC2_DMA_RMP_1 << 8U | SYSCFG_CFGR3_ADC2_DMA_RMP_1)
156#define LL_SYSCFG_DAC1_CH1_RMP_DMA2_CH3 ((SYSCFG_CFGR1_TIM6DAC1Ch1_DMA_RMP << 8U) | (uint32_t)0x00000000U)
157#define LL_SYSCFG_DAC1_CH1_RMP_DMA1_CH3 ((SYSCFG_CFGR1_TIM6DAC1Ch1_DMA_RMP << 8U) | SYSCFG_CFGR1_TIM6DAC1Ch1_DMA_RMP)
158#if defined(SYSCFG_CFGR1_TIM7DAC1Ch2_DMA_RMP)
159#define LL_SYSCFG_DAC1_OUT2_RMP_DMA2_CH4 ((SYSCFG_CFGR1_TIM7DAC1Ch2_DMA_RMP << 8U) | (uint32_t)0x00000000U)
160#define LL_SYSCFG_DAC1_OUT2_RMP_DMA1_CH4 ((SYSCFG_CFGR1_TIM7DAC1Ch2_DMA_RMP << 8U) | SYSCFG_CFGR1_TIM7DAC1Ch2_DMA_RMP)
162#if defined(SYSCFG_CFGR1_TIM18DAC2Ch1_DMA_RMP)
163#define LL_SYSCFG_DAC2_OUT1_RMP_DMA2_CH5 ((SYSCFG_CFGR1_TIM18DAC2Ch1_DMA_RMP << 8U) | (uint32_t)0x00000000U)
164#define LL_SYSCFG_DAC2_OUT1_RMP_DMA1_CH5 ((SYSCFG_CFGR1_TIM18DAC2Ch1_DMA_RMP << 8U) | SYSCFG_CFGR1_TIM18DAC2Ch1_DMA_RMP)
166#if defined(SYSCFG_CFGR1_DAC2Ch1_DMA_RMP)
167#define LL_SYSCFG_DAC2_CH1_RMP_NO ((SYSCFG_CFGR1_DAC2Ch1_DMA_RMP << 8U) | (uint32_t)0x00000000U)
168#define LL_SYSCFG_DAC2_CH1_RMP_DMA1_CH5 ((SYSCFG_CFGR1_DAC2Ch1_DMA_RMP << 8U) | SYSCFG_CFGR1_DAC2Ch1_DMA_RMP)
177#define LL_SYSCFG_TIM16_RMP_DMA1_CH3 ((SYSCFG_CFGR1_TIM16_DMA_RMP << 8U) | (uint32_t)0x00000000U)
178#define LL_SYSCFG_TIM16_RMP_DMA1_CH6 ((SYSCFG_CFGR1_TIM16_DMA_RMP << 8U) | SYSCFG_CFGR1_TIM16_DMA_RMP)
179#define LL_SYSCFG_TIM17_RMP_DMA1_CH1 ((SYSCFG_CFGR1_TIM17_DMA_RMP << 8U) | (uint32_t)0x00000000U)
180#define LL_SYSCFG_TIM17_RMP_DMA1_CH7 ((SYSCFG_CFGR1_TIM17_DMA_RMP << 8U) | SYSCFG_CFGR1_TIM17_DMA_RMP)
181#define LL_SYSCFG_TIM6_RMP_DMA2_CH3 ((SYSCFG_CFGR1_TIM6DAC1Ch1_DMA_RMP << 8U) | (uint32_t)0x00000000U)
182#define LL_SYSCFG_TIM6_RMP_DMA1_CH3 ((SYSCFG_CFGR1_TIM6DAC1Ch1_DMA_RMP << 8U) | SYSCFG_CFGR1_TIM6DAC1Ch1_DMA_RMP)
183#if defined(SYSCFG_CFGR1_TIM7DAC1Ch2_DMA_RMP)
184#define LL_SYSCFG_TIM7_RMP_DMA2_CH4 ((SYSCFG_CFGR1_TIM7DAC1Ch2_DMA_RMP << 8U) | (uint32_t)0x00000000U)
185#define LL_SYSCFG_TIM7_RMP_DMA1_CH4 ((SYSCFG_CFGR1_TIM7DAC1Ch2_DMA_RMP << 8U) | SYSCFG_CFGR1_TIM7DAC1Ch2_DMA_RMP)
187#if defined(SYSCFG_CFGR1_TIM18DAC2Ch1_DMA_RMP)
188#define LL_SYSCFG_TIM18_RMP_DMA2_CH5 ((SYSCFG_CFGR1_TIM18DAC2Ch1_DMA_RMP << 8U) | (uint32_t)0x00000000U)
189#define LL_SYSCFG_TIM18_RMP_DMA1_CH5 ((SYSCFG_CFGR1_TIM18DAC2Ch1_DMA_RMP << 8U) | SYSCFG_CFGR1_TIM18DAC2Ch1_DMA_RMP)
195#if defined(SYSCFG_CFGR1_TIM1_ITR3_RMP) || defined(SYSCFG_CFGR1_ENCODER_MODE)
199#if defined(SYSCFG_CFGR1_TIM1_ITR3_RMP)
200#define LL_SYSCFG_TIM1_ITR3_RMP_TIM4_TRGO ((SYSCFG_CFGR1_TIM1_ITR3_RMP << 8U) | (uint32_t)0x00000000U)
201#define LL_SYSCFG_TIM1_ITR3_RMP_TIM17_OC ((SYSCFG_CFGR1_TIM1_ITR3_RMP << 8U) | SYSCFG_CFGR1_TIM1_ITR3_RMP)
203#if defined(SYSCFG_CFGR1_ENCODER_MODE)
204#define LL_SYSCFG_TIM15_ENCODEMODE_NOREDIRECTION ((SYSCFG_CFGR1_ENCODER_MODE << 8U) | (uint32_t)0x00000000U)
205#define LL_SYSCFG_TIM15_ENCODEMODE_TIM2 ((SYSCFG_CFGR1_ENCODER_MODE_0 << 8U) | SYSCFG_CFGR1_ENCODER_MODE_0)
206#if defined(SYSCFG_CFGR1_ENCODER_MODE_TIM3)
207#define LL_SYSCFG_TIM15_ENCODEMODE_TIM3 ((SYSCFG_CFGR1_ENCODER_MODE_TIM3 << 8U) | SYSCFG_CFGR1_ENCODER_MODE_TIM3)
209#if defined(SYSCFG_CFGR1_ENCODER_MODE_TIM4)
210#define LL_SYSCFG_TIM15_ENCODEMODE_TIM4 ((SYSCFG_CFGR1_ENCODER_MODE_TIM4 << 8U) | SYSCFG_CFGR1_ENCODER_MODE_TIM4)
219#if defined(SYSCFG_CFGR4_ADC12_EXT2_RMP)
223#define LL_SYSCFG_ADC12_EXT2_RMP_TIM1_CC3 ((SYSCFG_CFGR4_ADC12_EXT2_RMP << 16U) | (uint32_t)0x00000000U)
224#define LL_SYSCFG_ADC12_EXT2_RMP_TIM20_TRGO ((SYSCFG_CFGR4_ADC12_EXT2_RMP << 16U) | SYSCFG_CFGR4_ADC12_EXT2_RMP)
225#define LL_SYSCFG_ADC12_EXT3_RMP_TIM2_CC2 ((SYSCFG_CFGR4_ADC12_EXT3_RMP << 16U) | (uint32_t)0x00000000U)
226#define LL_SYSCFG_ADC12_EXT3_RMP_TIM20_TRGO2 ((SYSCFG_CFGR4_ADC12_EXT3_RMP << 16U) | SYSCFG_CFGR4_ADC12_EXT3_RMP)
227#define LL_SYSCFG_ADC12_EXT5_RMP_TIM4_CC4 ((SYSCFG_CFGR4_ADC12_EXT5_RMP << 16U) | (uint32_t)0x00000000U)
228#define LL_SYSCFG_ADC12_EXT5_RMP_TIM20_CC1 ((SYSCFG_CFGR4_ADC12_EXT5_RMP << 16U) | SYSCFG_CFGR4_ADC12_EXT5_RMP)
229#define LL_SYSCFG_ADC12_EXT13_RMP_TIM6_TRGO ((SYSCFG_CFGR4_ADC12_EXT13_RMP << 16U) | (uint32_t)0x00000000U)
230#define LL_SYSCFG_ADC12_EXT13_RMP_TIM20_CC2 ((SYSCFG_CFGR4_ADC12_EXT13_RMP << 16U) | SYSCFG_CFGR4_ADC12_EXT13_RMP)
231#define LL_SYSCFG_ADC12_EXT15_RMP_TIM3_CC4 ((SYSCFG_CFGR4_ADC12_EXT15_RMP << 16U) | (uint32_t)0x00000000U)
232#define LL_SYSCFG_ADC12_EXT15_RMP_TIM20_CC3 ((SYSCFG_CFGR4_ADC12_EXT15_RMP << 16U) | SYSCFG_CFGR4_ADC12_EXT15_RMP)
233#define LL_SYSCFG_ADC12_JEXT3_RMP_TIM2_CC1 ((SYSCFG_CFGR4_ADC12_JEXT3_RMP << 16U) | (uint32_t)0x00000000U)
234#define LL_SYSCFG_ADC12_JEXT3_RMP_TIM20_TRGO ((SYSCFG_CFGR4_ADC12_JEXT3_RMP << 16U) | SYSCFG_CFGR4_ADC12_JEXT3_RMP)
235#define LL_SYSCFG_ADC12_JEXT6_RMP_EXTI_LINE_15 ((SYSCFG_CFGR4_ADC12_JEXT6_RMP << 16U) | (uint32_t)0x00000000U)
236#define LL_SYSCFG_ADC12_JEXT6_RMP_TIM20_TRGO2 ((SYSCFG_CFGR4_ADC12_JEXT6_RMP << 16U) | SYSCFG_CFGR4_ADC12_JEXT6_RMP)
237#define LL_SYSCFG_ADC12_JEXT13_RMP_TIM3_CC1 ((SYSCFG_CFGR4_ADC12_JEXT13_RMP << 16U) | (uint32_t)0x00000000U)
238#define LL_SYSCFG_ADC12_JEXT13_RMP_TIM20_CC4 ((SYSCFG_CFGR4_ADC12_JEXT13_RMP << 16U) | SYSCFG_CFGR4_ADC12_JEXT13_RMP)
239#define LL_SYSCFG_ADC34_EXT5_RMP_EXTI_LINE_2 ((SYSCFG_CFGR4_ADC34_EXT5_RMP << 16U) | (uint32_t)0x00000000U)
240#define LL_SYSCFG_ADC34_EXT5_RMP_TIM20_TRGO ((SYSCFG_CFGR4_ADC34_EXT5_RMP << 16U) | SYSCFG_CFGR4_ADC34_EXT5_RMP)
241#define LL_SYSCFG_ADC34_EXT6_RMP_TIM4_CC1 ((SYSCFG_CFGR4_ADC34_EXT6_RMP << 16U) | (uint32_t)0x00000000U)
242#define LL_SYSCFG_ADC34_EXT6_RMP_TIM20_TRGO2 ((SYSCFG_CFGR4_ADC34_EXT6_RMP << 16U) | SYSCFG_CFGR4_ADC34_EXT6_RMP)
243#define LL_SYSCFG_ADC34_EXT15_RMP_TIM2_CC1 ((SYSCFG_CFGR4_ADC34_EXT15_RMP << 16U) | (uint32_t)0x00000000U)
244#define LL_SYSCFG_ADC34_EXT15_RMP_TIM20_CC1 ((SYSCFG_CFGR4_ADC34_EXT15_RMP << 16U) | SYSCFG_CFGR4_ADC34_EXT15_RMP)
245#define LL_SYSCFG_ADC34_JEXT5_RMP_TIM4_CC3 ((SYSCFG_CFGR4_ADC34_JEXT5_RMP << 16U) | (uint32_t)0x00000000U)
246#define LL_SYSCFG_ADC34_JEXT5_RMP_TIM20_TRGO ((SYSCFG_CFGR4_ADC34_JEXT5_RMP << 16U) | SYSCFG_CFGR4_ADC34_JEXT5_RMP)
247#define LL_SYSCFG_ADC34_JEXT11_RMP_TIM1_CC3 ((SYSCFG_CFGR4_ADC34_JEXT11_RMP << 16U) | (uint32_t)0x00000000U)
248#define LL_SYSCFG_ADC34_JEXT11_RMP_TIM20_TRGO2 ((SYSCFG_CFGR4_ADC34_JEXT11_RMP << 16U) | SYSCFG_CFGR4_ADC34_JEXT11_RMP)
249#define LL_SYSCFG_ADC34_JEXT14_RMP_TIM7_TRGO ((SYSCFG_CFGR4_ADC34_JEXT14_RMP << 16U) | (uint32_t)0x00000000U)
250#define LL_SYSCFG_ADC34_JEXT14_RMP_TIM20_CC2 ((SYSCFG_CFGR4_ADC34_JEXT14_RMP << 16U) | SYSCFG_CFGR4_ADC34_JEXT14_RMP)
257#if defined(SYSCFG_CFGR1_DAC1_TRIG1_RMP) || defined(SYSCFG_CFGR3_TRIGGER_RMP)
261#if defined(SYSCFG_CFGR1_DAC1_TRIG1_RMP)
262#define LL_SYSCFG_DAC1_TRIG1_RMP_TIM8_TRGO (SYSCFG_OFFSET_CFGR1 << 24U | SYSCFG_CFGR1_DAC1_TRIG1_RMP << 4 | (uint32_t)0x00000000U)
263#define LL_SYSCFG_DAC1_TRIG1_RMP_TIM3_TRGO (SYSCFG_OFFSET_CFGR1 << 24U | SYSCFG_CFGR1_DAC1_TRIG1_RMP << 4 | SYSCFG_CFGR1_DAC1_TRIG1_RMP)
265#if defined(SYSCFG_CFGR3_DAC1_TRG3_RMP)
266#define LL_SYSCFG_DAC1_TRIG3_RMP_TIM15_TRGO (SYSCFG_OFFSET_CFGR3 << 24U | SYSCFG_CFGR3_DAC1_TRG3_RMP << 4 | (uint32_t)0x00000000U)
267#define LL_SYSCFG_DAC1_TRIG3_RMP_HRTIM1_DAC1_TRIG1 (SYSCFG_OFFSET_CFGR3 << 24U | SYSCFG_CFGR3_DAC1_TRG3_RMP << 4 | SYSCFG_CFGR3_DAC1_TRG3_RMP)
269#if defined(SYSCFG_CFGR3_DAC1_TRG5_RMP)
270#define LL_SYSCFG_DAC1_TRIG5_RMP_NO (SYSCFG_OFFSET_CFGR3 << 24U | SYSCFG_CFGR3_DAC1_TRG5_RMP << 4 | (uint32_t)0x00000000U)
271#define LL_SYSCFG_DAC1_TRIG5_RMP_HRTIM1_DAC1_TRIG2 (SYSCFG_OFFSET_CFGR3 << 24U | SYSCFG_CFGR3_DAC1_TRG5_RMP << 4 | SYSCFG_CFGR3_DAC1_TRG5_RMP)
282#define LL_SYSCFG_I2C_FASTMODEPLUS_PB6 SYSCFG_CFGR1_I2C_PB6_FMP
283#define LL_SYSCFG_I2C_FASTMODEPLUS_PB7 SYSCFG_CFGR1_I2C_PB7_FMP
284#define LL_SYSCFG_I2C_FASTMODEPLUS_PB8 SYSCFG_CFGR1_I2C_PB8_FMP
285#define LL_SYSCFG_I2C_FASTMODEPLUS_PB9 SYSCFG_CFGR1_I2C_PB9_FMP
286#define LL_SYSCFG_I2C_FASTMODEPLUS_I2C1 SYSCFG_CFGR1_I2C1_FMP
287#if defined(SYSCFG_CFGR1_I2C2_FMP)
288#define LL_SYSCFG_I2C_FASTMODEPLUS_I2C2 SYSCFG_CFGR1_I2C2_FMP
290#if defined(SYSCFG_CFGR1_I2C3_FMP)
291#define LL_SYSCFG_I2C_FASTMODEPLUS_I2C3 SYSCFG_CFGR1_I2C3_FMP
300#define LL_SYSCFG_EXTI_PORTA (uint32_t)0U
301#define LL_SYSCFG_EXTI_PORTB (uint32_t)1U
302#define LL_SYSCFG_EXTI_PORTC (uint32_t)2U
303#define LL_SYSCFG_EXTI_PORTD (uint32_t)3U
305#define LL_SYSCFG_EXTI_PORTE (uint32_t)4U
307#define LL_SYSCFG_EXTI_PORTF (uint32_t)5U
309#define LL_SYSCFG_EXTI_PORTG (uint32_t)6U
312#define LL_SYSCFG_EXTI_PORTH (uint32_t)7U
321#define LL_SYSCFG_EXTI_LINE0 (uint32_t)(0x000FU << 16U | 0U)
322#define LL_SYSCFG_EXTI_LINE1 (uint32_t)(0x00F0U << 16U | 0U)
323#define LL_SYSCFG_EXTI_LINE2 (uint32_t)(0x0F00U << 16U | 0U)
324#define LL_SYSCFG_EXTI_LINE3 (uint32_t)(0xF000U << 16U | 0U)
325#define LL_SYSCFG_EXTI_LINE4 (uint32_t)(0x000FU << 16U | 1U)
326#define LL_SYSCFG_EXTI_LINE5 (uint32_t)(0x00F0U << 16U | 1U)
327#define LL_SYSCFG_EXTI_LINE6 (uint32_t)(0x0F00U << 16U | 1U)
328#define LL_SYSCFG_EXTI_LINE7 (uint32_t)(0xF000U << 16U | 1U)
329#define LL_SYSCFG_EXTI_LINE8 (uint32_t)(0x000FU << 16U | 2U)
330#define LL_SYSCFG_EXTI_LINE9 (uint32_t)(0x00F0U << 16U | 2U)
331#define LL_SYSCFG_EXTI_LINE10 (uint32_t)(0x0F00U << 16U | 2U)
332#define LL_SYSCFG_EXTI_LINE11 (uint32_t)(0xF000U << 16U | 2U)
333#define LL_SYSCFG_EXTI_LINE12 (uint32_t)(0x000FU << 16U | 3U)
334#define LL_SYSCFG_EXTI_LINE13 (uint32_t)(0x00F0U << 16U | 3U)
335#define LL_SYSCFG_EXTI_LINE14 (uint32_t)(0x0F00U << 16U | 3U)
336#define LL_SYSCFG_EXTI_LINE15 (uint32_t)(0xF000U << 16U | 3U)
344#if defined(SYSCFG_CFGR2_PVD_LOCK)
345#define LL_SYSCFG_TIMBREAK_PVD SYSCFG_CFGR2_PVD_LOCK
347#if defined(SYSCFG_CFGR2_SRAM_PARITY_LOCK)
348#define LL_SYSCFG_TIMBREAK_SRAM_PARITY SYSCFG_CFGR2_SRAM_PARITY_LOCK
350#define LL_SYSCFG_TIMBREAK_LOCKUP SYSCFG_CFGR2_LOCKUP_LOCK
355#if defined(SYSCFG_RCR_PAGE0)
359#define LL_SYSCFG_CCMSRAMWRP_PAGE0 SYSCFG_RCR_PAGE0
360#define LL_SYSCFG_CCMSRAMWRP_PAGE1 SYSCFG_RCR_PAGE1
361#define LL_SYSCFG_CCMSRAMWRP_PAGE2 SYSCFG_RCR_PAGE2
362#define LL_SYSCFG_CCMSRAMWRP_PAGE3 SYSCFG_RCR_PAGE3
363#if defined(SYSCFG_RCR_PAGE4)
364#define LL_SYSCFG_CCMSRAMWRP_PAGE4 SYSCFG_RCR_PAGE4
365#define LL_SYSCFG_CCMSRAMWRP_PAGE5 SYSCFG_RCR_PAGE5
366#define LL_SYSCFG_CCMSRAMWRP_PAGE6 SYSCFG_RCR_PAGE6
367#define LL_SYSCFG_CCMSRAMWRP_PAGE7 SYSCFG_RCR_PAGE7
369#if defined(SYSCFG_RCR_PAGE8)
370#define LL_SYSCFG_CCMSRAMWRP_PAGE8 SYSCFG_RCR_PAGE8
371#define LL_SYSCFG_CCMSRAMWRP_PAGE9 SYSCFG_RCR_PAGE9
372#define LL_SYSCFG_CCMSRAMWRP_PAGE10 SYSCFG_RCR_PAGE10
373#define LL_SYSCFG_CCMSRAMWRP_PAGE11 SYSCFG_RCR_PAGE11
374#define LL_SYSCFG_CCMSRAMWRP_PAGE12 SYSCFG_RCR_PAGE12
375#define LL_SYSCFG_CCMSRAMWRP_PAGE13 SYSCFG_RCR_PAGE13
376#define LL_SYSCFG_CCMSRAMWRP_PAGE14 SYSCFG_RCR_PAGE14
377#define LL_SYSCFG_CCMSRAMWRP_PAGE15 SYSCFG_RCR_PAGE15
388#define LL_DBGMCU_TRACE_NONE 0x00000000U
389#define LL_DBGMCU_TRACE_ASYNCH DBGMCU_CR_TRACE_IOEN
390#define LL_DBGMCU_TRACE_SYNCH_SIZE1 (DBGMCU_CR_TRACE_IOEN | DBGMCU_CR_TRACE_MODE_0)
391#define LL_DBGMCU_TRACE_SYNCH_SIZE2 (DBGMCU_CR_TRACE_IOEN | DBGMCU_CR_TRACE_MODE_1)
392#define LL_DBGMCU_TRACE_SYNCH_SIZE4 (DBGMCU_CR_TRACE_IOEN | DBGMCU_CR_TRACE_MODE)
400#define LL_DBGMCU_APB1_GRP1_TIM2_STOP DBGMCU_APB1_FZ_DBG_TIM2_STOP
401#if defined(DBGMCU_APB1_FZ_DBG_TIM3_STOP)
402#define LL_DBGMCU_APB1_GRP1_TIM3_STOP DBGMCU_APB1_FZ_DBG_TIM3_STOP
404#if defined(DBGMCU_APB1_FZ_DBG_TIM4_STOP)
405#define LL_DBGMCU_APB1_GRP1_TIM4_STOP DBGMCU_APB1_FZ_DBG_TIM4_STOP
407#if defined(DBGMCU_APB1_FZ_DBG_TIM5_STOP)
408#define LL_DBGMCU_APB1_GRP1_TIM5_STOP DBGMCU_APB1_FZ_DBG_TIM5_STOP
410#define LL_DBGMCU_APB1_GRP1_TIM6_STOP DBGMCU_APB1_FZ_DBG_TIM6_STOP
411#if defined(DBGMCU_APB1_FZ_DBG_TIM7_STOP)
412#define LL_DBGMCU_APB1_GRP1_TIM7_STOP DBGMCU_APB1_FZ_DBG_TIM7_STOP
414#if defined(DBGMCU_APB1_FZ_DBG_TIM12_STOP)
415#define LL_DBGMCU_APB1_GRP1_TIM12_STOP DBGMCU_APB1_FZ_DBG_TIM12_STOP
417#if defined(DBGMCU_APB1_FZ_DBG_TIM13_STOP)
418#define LL_DBGMCU_APB1_GRP1_TIM13_STOP DBGMCU_APB1_FZ_DBG_TIM13_STOP
420#if defined(DBGMCU_APB1_FZ_DBG_TIM14_STOP)
421#define LL_DBGMCU_APB1_GRP1_TIM14_STOP DBGMCU_APB1_FZ_DBG_TIM14_STOP
423#if defined(DBGMCU_APB1_FZ_DBG_TIM18_STOP)
424#define LL_DBGMCU_APB1_GRP1_TIM18_STOP DBGMCU_APB1_FZ_DBG_TIM18_STOP
426#define LL_DBGMCU_APB1_GRP1_RTC_STOP DBGMCU_APB1_FZ_DBG_RTC_STOP
427#define LL_DBGMCU_APB1_GRP1_WWDG_STOP DBGMCU_APB1_FZ_DBG_WWDG_STOP
428#define LL_DBGMCU_APB1_GRP1_IWDG_STOP DBGMCU_APB1_FZ_DBG_IWDG_STOP
429#define LL_DBGMCU_APB1_GRP1_I2C1_STOP DBGMCU_APB1_FZ_DBG_I2C1_SMBUS_TIMEOUT
430#if defined(DBGMCU_APB1_FZ_DBG_I2C2_SMBUS_TIMEOUT)
431#define LL_DBGMCU_APB1_GRP1_I2C2_STOP DBGMCU_APB1_FZ_DBG_I2C2_SMBUS_TIMEOUT
433#if defined(DBGMCU_APB1_FZ_DBG_I2C3_SMBUS_TIMEOUT)
434#define LL_DBGMCU_APB1_GRP1_I2C3_STOP DBGMCU_APB1_FZ_DBG_I2C3_SMBUS_TIMEOUT
436#if defined(DBGMCU_APB1_FZ_DBG_CAN_STOP)
437#define LL_DBGMCU_APB1_GRP1_CAN_STOP DBGMCU_APB1_FZ_DBG_CAN_STOP
446#if defined(DBGMCU_APB2_FZ_DBG_TIM1_STOP)
447#define LL_DBGMCU_APB2_GRP1_TIM1_STOP DBGMCU_APB2_FZ_DBG_TIM1_STOP
449#if defined(DBGMCU_APB2_FZ_DBG_TIM8_STOP)
450#define LL_DBGMCU_APB2_GRP1_TIM8_STOP DBGMCU_APB2_FZ_DBG_TIM8_STOP
452#define LL_DBGMCU_APB2_GRP1_TIM15_STOP DBGMCU_APB2_FZ_DBG_TIM15_STOP
453#define LL_DBGMCU_APB2_GRP1_TIM16_STOP DBGMCU_APB2_FZ_DBG_TIM16_STOP
454#define LL_DBGMCU_APB2_GRP1_TIM17_STOP DBGMCU_APB2_FZ_DBG_TIM17_STOP
455#if defined(DBGMCU_APB2_FZ_DBG_TIM19_STOP)
456#define LL_DBGMCU_APB2_GRP1_TIM19_STOP DBGMCU_APB2_FZ_DBG_TIM19_STOP
458#if defined(DBGMCU_APB2_FZ_DBG_TIM20_STOP)
459#define LL_DBGMCU_APB2_GRP1_TIM20_STOP DBGMCU_APB2_FZ_DBG_TIM20_STOP
461#if defined(DBGMCU_APB2_FZ_DBG_HRTIM1_STOP)
462#define LL_DBGMCU_APB2_GRP1_HRTIM1_STOP DBGMCU_APB2_FZ_DBG_HRTIM1_STOP
471#define LL_FLASH_LATENCY_0 0x00000000U
472#define LL_FLASH_LATENCY_1 FLASH_ACR_LATENCY_0
473#define LL_FLASH_LATENCY_2 FLASH_ACR_LATENCY_1
526#if defined(SYSCFG_CFGR3_SPI1_RX_DMA_RMP)
546#if defined(SYSCFG_CFGR3_I2C1_RX_DMA_RMP)
566#if defined(SYSCFG_CFGR1_ADC24_DMA_RMP) || defined(SYSCFG_CFGR3_ADC2_DMA_RMP)
585 MODIFY_REG(*reg, (Remap & 0x00FF0000U) >> 8U, (Remap & 0x0000FFFFU));
608 MODIFY_REG(
SYSCFG->CFGR1, (Remap & 0x00FF0000U) >> 8U, (Remap & 0x0000FF00U));
630 MODIFY_REG(
SYSCFG->CFGR1, (Remap & 0x00FF0000U) >> 8U, (Remap & 0x0000FF00U));
633#if defined(SYSCFG_CFGR1_TIM1_ITR3_RMP) || defined(SYSCFG_CFGR1_ENCODER_MODE)
651 MODIFY_REG(
SYSCFG->CFGR1, (Remap & 0xFF00FF00U) >> 8U, (Remap & 0x00FF00FFU));
655#if defined(SYSCFG_CFGR4_ADC12_EXT2_RMP)
705 MODIFY_REG(
SYSCFG->CFGR4, (Remap & 0xFFFF0000U) >> 16U, (Remap & 0x0000FFFFU));
709#if defined(SYSCFG_CFGR1_DAC1_TRIG1_RMP) || defined(SYSCFG_CFGR3_TRIGGER_RMP)
728 MODIFY_REG(*reg, (Remap & 0x00F00F00U) >> 4U, (Remap & 0x000F00F0U));
732#if defined(SYSCFG_CFGR1_USB_IT_RMP)
756#if defined(SYSCFG_CFGR1_VBAT)
799__STATIC_INLINE void LL_SYSCFG_EnableFastModePlus(uint32_t ConfigFastModePlus)
825__STATIC_INLINE void LL_SYSCFG_DisableFastModePlus(uint32_t ConfigFastModePlus)
1106__STATIC_INLINE void LL_SYSCFG_SetEXTISource(uint32_t Port, uint32_t Line)
1243 return (uint32_t)(
READ_BIT(
SYSCFG->CFGR2, SYSCFG_MASK_TIM_BREAK));
1246#if defined(SYSCFG_CFGR2_BYP_ADDR_PAR)
1258#if defined(SYSCFG_CFGR2_SRAM_PE)
1280#if defined(SYSCFG_RCR_PAGE0)
1433__STATIC_INLINE void LL_DBGMCU_SetTracePinAssignment(uint32_t PinAssignment)
1495__STATIC_INLINE void LL_DBGMCU_APB1_GRP1_FreezePeriph(uint32_t Periphs)
1541__STATIC_INLINE void LL_DBGMCU_APB1_GRP1_UnFreezePeriph(uint32_t Periphs)
1569__STATIC_INLINE void LL_DBGMCU_APB2_GRP1_FreezePeriph(uint32_t Periphs)
1597__STATIC_INLINE void LL_DBGMCU_APB2_GRP1_UnFreezePeriph(uint32_t Periphs)
1667#if defined(FLASH_ACR_HLFCYA)
#define __STATIC_INLINE
Definition: cmsis_armcc.h:59
#define __IO
Definition: core_armv8mbl.h:196
#define CLEAR_BIT(REG, BIT)
Definition: stm32f3xx.h:192
#define SET_BIT(REG, BIT)
Definition: stm32f3xx.h:190
#define POSITION_VAL(VAL)
Definition: stm32f3xx.h:204
#define MODIFY_REG(REG, CLEARMASK, SETMASK)
Definition: stm32f3xx.h:202
#define READ_BIT(REG, BIT)
Definition: stm32f3xx.h:194
#define DBGMCU_CR_DBG_SLEEP
Definition: stm32f303xe.h:6771
#define SYSCFG_CFGR2_BYP_ADDR_PAR
Definition: stm32f303xe.h:12812
#define DBGMCU_CR_DBG_STANDBY
Definition: stm32f303xe.h:6777
#define FLASH_ACR_PRFTBS
Definition: stm32f303xe.h:8125
#define SYSCFG_CFGR1_USB_IT_RMP
Definition: stm32f303xe.h:12448
#define SYSCFG_CFGR1_FPU_IE_1
Definition: stm32f303xe.h:12509
#define FLASH_ACR_PRFTBE
Definition: stm32f303xe.h:8122
#define FLASH_ACR_HLFCYA
Definition: stm32f303xe.h:8119
#define DBGMCU_IDCODE_REV_ID_Pos
Definition: stm32f303xe.h:6764
#define SYSCFG_CFGR2_SRAM_PE
Definition: stm32f303xe.h:12815
#define SYSCFG_CFGR1_FPU_IE_2
Definition: stm32f303xe.h:12510
#define SYSCFG_CFGR1_FPU_IE_4
Definition: stm32f303xe.h:12512
#define DBGMCU_IDCODE_REV_ID
Definition: stm32f303xe.h:6766
#define SYSCFG_CFGR1_FPU_IE_5
Definition: stm32f303xe.h:12513
#define DBGMCU_CR_TRACE_IOEN
Definition: stm32f303xe.h:6780
#define DBGMCU_CR_TRACE_MODE
Definition: stm32f303xe.h:6784
#define SYSCFG_CFGR1_FPU_IE_0
Definition: stm32f303xe.h:12508
#define SYSCFG_CFGR1_MEM_MODE
Definition: stm32f303xe.h:12442
#define FLASH_ACR_LATENCY
Definition: stm32f303xe.h:8112
#define SYSCFG_CFGR1_FPU_IE_3
Definition: stm32f303xe.h:12511
#define DBGMCU_CR_DBG_STOP
Definition: stm32f303xe.h:6774
#define DBGMCU_IDCODE_DEV_ID
Definition: stm32f303xe.h:6763
#define SYSCFG
Definition: stm32f303xe.h:951
#define FLASH
Definition: stm32f303xe.h:978
#define DBGMCU
Definition: stm32f303xe.h:962
#define SYSCFG_BASE
Definition: stm32f303xe.h:820
CMSIS STM32F3xx Device Peripheral Access Layer Header File.