My Project
Loading...
Searching...
No Matches
stm32f3xx_ll_system.h
Go to the documentation of this file.
1
33/* Define to prevent recursive inclusion -------------------------------------*/
34#ifndef __STM32F3xx_LL_SYSTEM_H
35#define __STM32F3xx_LL_SYSTEM_H
36
37#ifdef __cplusplus
38extern "C" {
39#endif
40
41/* Includes ------------------------------------------------------------------*/
42#include "stm32f3xx.h"
43
48#if defined (FLASH) || defined (SYSCFG) || defined (DBGMCU)
49
54/* Private types -------------------------------------------------------------*/
55/* Private variables ---------------------------------------------------------*/
56
57/* Private constants ---------------------------------------------------------*/
62/* Offset used to access to SYSCFG_CFGR1 and SYSCFG_CFGR3 registers */
63#define SYSCFG_OFFSET_CFGR1 0x00000000U
64#define SYSCFG_OFFSET_CFGR3 0x00000050U
65
66/* Mask used for TIM breaks functions */
67#if defined(SYSCFG_CFGR2_PVD_LOCK) && defined(SYSCFG_CFGR2_SRAM_PARITY_LOCK)
68#define SYSCFG_MASK_TIM_BREAK (SYSCFG_CFGR2_LOCKUP_LOCK | SYSCFG_CFGR2_SRAM_PARITY_LOCK | SYSCFG_CFGR2_PVD_LOCK)
69#elif defined(SYSCFG_CFGR2_PVD_LOCK) && !defined(SYSCFG_CFGR2_SRAM_PARITY_LOCK)
70#define SYSCFG_MASK_TIM_BREAK (SYSCFG_CFGR2_LOCKUP_LOCK | SYSCFG_CFGR2_PVD_LOCK)
71#elif !defined(SYSCFG_CFGR2_PVD_LOCK) && defined(SYSCFG_CFGR2_SRAM_PARITY_LOCK)
72#define SYSCFG_MASK_TIM_BREAK (SYSCFG_CFGR2_LOCKUP_LOCK | SYSCFG_CFGR2_SRAM_PARITY_LOCK)
73#else
74#define SYSCFG_MASK_TIM_BREAK (SYSCFG_CFGR2_LOCKUP_LOCK)
75#endif /* SYSCFG_CFGR2_PVD_LOCK && SYSCFG_CFGR2_SRAM_PARITY_LOCK */
76
81/* Private macros ------------------------------------------------------------*/
82
83/* Exported types ------------------------------------------------------------*/
84/* Exported constants --------------------------------------------------------*/
92#define LL_SYSCFG_REMAP_FLASH (uint32_t)0x00000000 /* Main Flash memory mapped at 0x00000000 */
93#define LL_SYSCFG_REMAP_SYSTEMFLASH SYSCFG_CFGR1_MEM_MODE_0 /* System Flash memory mapped at 0x00000000 */
94#define LL_SYSCFG_REMAP_SRAM (SYSCFG_CFGR1_MEM_MODE_1 | SYSCFG_CFGR1_MEM_MODE_0) /* Embedded SRAM mapped at 0x00000000 */
95#if defined(FMC_BANK1)
96#define LL_SYSCFG_REMAP_FMC SYSCFG_CFGR1_MEM_MODE_2 /*<! FMC Bank (Only the first two banks) */
97#endif /* FMC_BANK1 */
102#if defined(SYSCFG_CFGR3_SPI1_RX_DMA_RMP)
106#define LL_SYSCFG_SPI1RX_RMP_DMA1_CH2 (SYSCFG_CFGR3_SPI1_RX_DMA_RMP << 16U | (uint32_t)0x00000000U)
107#define LL_SYSCFG_SPI1RX_RMP_DMA1_CH4 (SYSCFG_CFGR3_SPI1_RX_DMA_RMP << 16U | SYSCFG_CFGR3_SPI1_RX_DMA_RMP_0)
108#define LL_SYSCFG_SPI1RX_RMP_DMA1_CH6 (SYSCFG_CFGR3_SPI1_RX_DMA_RMP << 16U | SYSCFG_CFGR3_SPI1_RX_DMA_RMP_1)
109#define LL_SYSCFG_SPI1TX_RMP_DMA1_CH3 (SYSCFG_CFGR3_SPI1_TX_DMA_RMP << 16U | (uint32_t)0x00000000U)
110#define LL_SYSCFG_SPI1TX_RMP_DMA1_CH5 (SYSCFG_CFGR3_SPI1_TX_DMA_RMP << 16U | SYSCFG_CFGR3_SPI1_TX_DMA_RMP_0)
111#define LL_SYSCFG_SPI1TX_RMP_DMA1_CH7 (SYSCFG_CFGR3_SPI1_TX_DMA_RMP << 16U | SYSCFG_CFGR3_SPI1_TX_DMA_RMP_1)
115#endif /* SYSCFG_CFGR3_SPI1_RX_DMA_RMP */
116
117#if defined(SYSCFG_CFGR3_I2C1_RX_DMA_RMP)
121#define LL_SYSCFG_I2C1RX_RMP_DMA1_CH7 (SYSCFG_CFGR3_I2C1_RX_DMA_RMP << 16U | (uint32_t)0x00000000U)
122#define LL_SYSCFG_I2C1RX_RMP_DMA1_CH3 (SYSCFG_CFGR3_I2C1_RX_DMA_RMP << 16U | SYSCFG_CFGR3_I2C1_RX_DMA_RMP_0)
123#define LL_SYSCFG_I2C1RX_RMP_DMA1_CH5 (SYSCFG_CFGR3_I2C1_RX_DMA_RMP << 16U | SYSCFG_CFGR3_I2C1_RX_DMA_RMP_1)
124#define LL_SYSCFG_I2C1TX_RMP_DMA1_CH6 (SYSCFG_CFGR3_I2C1_TX_DMA_RMP << 16U | (uint32_t)0x00000000U)
125#define LL_SYSCFG_I2C1TX_RMP_DMA1_CH2 (SYSCFG_CFGR3_I2C1_TX_DMA_RMP << 16U | SYSCFG_CFGR3_I2C1_TX_DMA_RMP_0)
126#define LL_SYSCFG_I2C1TX_RMP_DMA1_CH4 (SYSCFG_CFGR3_I2C1_TX_DMA_RMP << 16U | SYSCFG_CFGR3_I2C1_TX_DMA_RMP_1)
131#endif /* SYSCFG_CFGR3_I2C1_RX_DMA_RMP */
132
133#if defined(SYSCFG_CFGR1_ADC24_DMA_RMP) || defined(SYSCFG_CFGR3_ADC2_DMA_RMP)
137#if defined (SYSCFG_CFGR1_ADC24_DMA_RMP)
138#define LL_SYSCFG_ADC24_RMP_DMA2_CH12 (SYSCFG_OFFSET_CFGR1 << 24U | SYSCFG_CFGR1_ADC24_DMA_RMP << 8U | (uint32_t)0x00000000U)
139#define LL_SYSCFG_ADC24_RMP_DMA2_CH34 (SYSCFG_OFFSET_CFGR1 << 24U | SYSCFG_CFGR1_ADC24_DMA_RMP << 8U | SYSCFG_CFGR1_ADC24_DMA_RMP)
140#endif /*SYSCFG_CFGR1_ADC24_DMA_RMP*/
141#if defined (SYSCFG_CFGR3_ADC2_DMA_RMP)
142#define LL_SYSCFG_ADC2_RMP_DMA1_CH2 (SYSCFG_OFFSET_CFGR3 << 24U | SYSCFG_CFGR3_ADC2_DMA_RMP_0 << 8U | (uint32_t)0x00000000U)
143#define LL_SYSCFG_ADC2_RMP_DMA1_CH4 (SYSCFG_OFFSET_CFGR3 << 24U | SYSCFG_CFGR3_ADC2_DMA_RMP_0 << 8U | SYSCFG_CFGR3_ADC2_DMA_RMP_0)
144#define LL_SYSCFG_ADC2_RMP_DMA2 (SYSCFG_OFFSET_CFGR3 << 24U | SYSCFG_CFGR3_ADC2_DMA_RMP_1 << 8U | (uint32_t)0x00000000U)
145#define LL_SYSCFG_ADC2_RMP_DMA1 (SYSCFG_OFFSET_CFGR3 << 24U | SYSCFG_CFGR3_ADC2_DMA_RMP_1 << 8U | SYSCFG_CFGR3_ADC2_DMA_RMP_1)
146#endif /*SYSCFG_CFGR3_ADC2_DMA_RMP*/
151#endif /* SYSCFG_CFGR1_ADC24_DMA_RMP || SYSCFG_CFGR3_ADC2_DMA_RMP */
152
156#define LL_SYSCFG_DAC1_CH1_RMP_DMA2_CH3 ((SYSCFG_CFGR1_TIM6DAC1Ch1_DMA_RMP << 8U) | (uint32_t)0x00000000U)
157#define LL_SYSCFG_DAC1_CH1_RMP_DMA1_CH3 ((SYSCFG_CFGR1_TIM6DAC1Ch1_DMA_RMP << 8U) | SYSCFG_CFGR1_TIM6DAC1Ch1_DMA_RMP)
158#if defined(SYSCFG_CFGR1_TIM7DAC1Ch2_DMA_RMP)
159#define LL_SYSCFG_DAC1_OUT2_RMP_DMA2_CH4 ((SYSCFG_CFGR1_TIM7DAC1Ch2_DMA_RMP << 8U) | (uint32_t)0x00000000U)
160#define LL_SYSCFG_DAC1_OUT2_RMP_DMA1_CH4 ((SYSCFG_CFGR1_TIM7DAC1Ch2_DMA_RMP << 8U) | SYSCFG_CFGR1_TIM7DAC1Ch2_DMA_RMP)
161#endif /*SYSCFG_CFGR1_TIM7DAC1Ch2_DMA_RMP*/
162#if defined(SYSCFG_CFGR1_TIM18DAC2Ch1_DMA_RMP)
163#define LL_SYSCFG_DAC2_OUT1_RMP_DMA2_CH5 ((SYSCFG_CFGR1_TIM18DAC2Ch1_DMA_RMP << 8U) | (uint32_t)0x00000000U)
164#define LL_SYSCFG_DAC2_OUT1_RMP_DMA1_CH5 ((SYSCFG_CFGR1_TIM18DAC2Ch1_DMA_RMP << 8U) | SYSCFG_CFGR1_TIM18DAC2Ch1_DMA_RMP)
165#endif /*SYSCFG_CFGR1_TIM18DAC2Ch1_DMA_RMP*/
166#if defined(SYSCFG_CFGR1_DAC2Ch1_DMA_RMP)
167#define LL_SYSCFG_DAC2_CH1_RMP_NO ((SYSCFG_CFGR1_DAC2Ch1_DMA_RMP << 8U) | (uint32_t)0x00000000U)
168#define LL_SYSCFG_DAC2_CH1_RMP_DMA1_CH5 ((SYSCFG_CFGR1_DAC2Ch1_DMA_RMP << 8U) | SYSCFG_CFGR1_DAC2Ch1_DMA_RMP)
169#endif /*SYSCFG_CFGR1_DAC2Ch1_DMA_RMP*/
177#define LL_SYSCFG_TIM16_RMP_DMA1_CH3 ((SYSCFG_CFGR1_TIM16_DMA_RMP << 8U) | (uint32_t)0x00000000U)
178#define LL_SYSCFG_TIM16_RMP_DMA1_CH6 ((SYSCFG_CFGR1_TIM16_DMA_RMP << 8U) | SYSCFG_CFGR1_TIM16_DMA_RMP)
179#define LL_SYSCFG_TIM17_RMP_DMA1_CH1 ((SYSCFG_CFGR1_TIM17_DMA_RMP << 8U) | (uint32_t)0x00000000U)
180#define LL_SYSCFG_TIM17_RMP_DMA1_CH7 ((SYSCFG_CFGR1_TIM17_DMA_RMP << 8U) | SYSCFG_CFGR1_TIM17_DMA_RMP)
181#define LL_SYSCFG_TIM6_RMP_DMA2_CH3 ((SYSCFG_CFGR1_TIM6DAC1Ch1_DMA_RMP << 8U) | (uint32_t)0x00000000U)
182#define LL_SYSCFG_TIM6_RMP_DMA1_CH3 ((SYSCFG_CFGR1_TIM6DAC1Ch1_DMA_RMP << 8U) | SYSCFG_CFGR1_TIM6DAC1Ch1_DMA_RMP)
183#if defined(SYSCFG_CFGR1_TIM7DAC1Ch2_DMA_RMP)
184#define LL_SYSCFG_TIM7_RMP_DMA2_CH4 ((SYSCFG_CFGR1_TIM7DAC1Ch2_DMA_RMP << 8U) | (uint32_t)0x00000000U)
185#define LL_SYSCFG_TIM7_RMP_DMA1_CH4 ((SYSCFG_CFGR1_TIM7DAC1Ch2_DMA_RMP << 8U) | SYSCFG_CFGR1_TIM7DAC1Ch2_DMA_RMP)
186#endif /*SYSCFG_CFGR1_TIM7DAC1Ch2_DMA_RMP*/
187#if defined(SYSCFG_CFGR1_TIM18DAC2Ch1_DMA_RMP)
188#define LL_SYSCFG_TIM18_RMP_DMA2_CH5 ((SYSCFG_CFGR1_TIM18DAC2Ch1_DMA_RMP << 8U) | (uint32_t)0x00000000U)
189#define LL_SYSCFG_TIM18_RMP_DMA1_CH5 ((SYSCFG_CFGR1_TIM18DAC2Ch1_DMA_RMP << 8U) | SYSCFG_CFGR1_TIM18DAC2Ch1_DMA_RMP)
190#endif /*SYSCFG_CFGR1_TIM18DAC2Ch1_DMA_RMP*/
195#if defined(SYSCFG_CFGR1_TIM1_ITR3_RMP) || defined(SYSCFG_CFGR1_ENCODER_MODE)
199#if defined(SYSCFG_CFGR1_TIM1_ITR3_RMP)
200#define LL_SYSCFG_TIM1_ITR3_RMP_TIM4_TRGO ((SYSCFG_CFGR1_TIM1_ITR3_RMP << 8U) | (uint32_t)0x00000000U)
201#define LL_SYSCFG_TIM1_ITR3_RMP_TIM17_OC ((SYSCFG_CFGR1_TIM1_ITR3_RMP << 8U) | SYSCFG_CFGR1_TIM1_ITR3_RMP)
202#endif /* SYSCFG_CFGR1_TIM1_ITR3_RMP */
203#if defined(SYSCFG_CFGR1_ENCODER_MODE)
204#define LL_SYSCFG_TIM15_ENCODEMODE_NOREDIRECTION ((SYSCFG_CFGR1_ENCODER_MODE << 8U) | (uint32_t)0x00000000U)
205#define LL_SYSCFG_TIM15_ENCODEMODE_TIM2 ((SYSCFG_CFGR1_ENCODER_MODE_0 << 8U) | SYSCFG_CFGR1_ENCODER_MODE_0)
206#if defined(SYSCFG_CFGR1_ENCODER_MODE_TIM3)
207#define LL_SYSCFG_TIM15_ENCODEMODE_TIM3 ((SYSCFG_CFGR1_ENCODER_MODE_TIM3 << 8U) | SYSCFG_CFGR1_ENCODER_MODE_TIM3)
208#endif /* SYSCFG_CFGR1_ENCODER_MODE_TIM3 */
209#if defined(SYSCFG_CFGR1_ENCODER_MODE_TIM4)
210#define LL_SYSCFG_TIM15_ENCODEMODE_TIM4 ((SYSCFG_CFGR1_ENCODER_MODE_TIM4 << 8U) | SYSCFG_CFGR1_ENCODER_MODE_TIM4)
211#endif /* SYSCFG_CFGR1_ENCODER_MODE_TIM4 */
212#endif /* SYSCFG_CFGR1_ENCODER_MODE */
217#endif /* SYSCFG_CFGR1_TIM1_ITR3_RMP || SYSCFG_CFGR1_ENCODER_MODE */
218
219#if defined(SYSCFG_CFGR4_ADC12_EXT2_RMP)
223#define LL_SYSCFG_ADC12_EXT2_RMP_TIM1_CC3 ((SYSCFG_CFGR4_ADC12_EXT2_RMP << 16U) | (uint32_t)0x00000000U)
224#define LL_SYSCFG_ADC12_EXT2_RMP_TIM20_TRGO ((SYSCFG_CFGR4_ADC12_EXT2_RMP << 16U) | SYSCFG_CFGR4_ADC12_EXT2_RMP)
225#define LL_SYSCFG_ADC12_EXT3_RMP_TIM2_CC2 ((SYSCFG_CFGR4_ADC12_EXT3_RMP << 16U) | (uint32_t)0x00000000U)
226#define LL_SYSCFG_ADC12_EXT3_RMP_TIM20_TRGO2 ((SYSCFG_CFGR4_ADC12_EXT3_RMP << 16U) | SYSCFG_CFGR4_ADC12_EXT3_RMP)
227#define LL_SYSCFG_ADC12_EXT5_RMP_TIM4_CC4 ((SYSCFG_CFGR4_ADC12_EXT5_RMP << 16U) | (uint32_t)0x00000000U)
228#define LL_SYSCFG_ADC12_EXT5_RMP_TIM20_CC1 ((SYSCFG_CFGR4_ADC12_EXT5_RMP << 16U) | SYSCFG_CFGR4_ADC12_EXT5_RMP)
229#define LL_SYSCFG_ADC12_EXT13_RMP_TIM6_TRGO ((SYSCFG_CFGR4_ADC12_EXT13_RMP << 16U) | (uint32_t)0x00000000U)
230#define LL_SYSCFG_ADC12_EXT13_RMP_TIM20_CC2 ((SYSCFG_CFGR4_ADC12_EXT13_RMP << 16U) | SYSCFG_CFGR4_ADC12_EXT13_RMP)
231#define LL_SYSCFG_ADC12_EXT15_RMP_TIM3_CC4 ((SYSCFG_CFGR4_ADC12_EXT15_RMP << 16U) | (uint32_t)0x00000000U)
232#define LL_SYSCFG_ADC12_EXT15_RMP_TIM20_CC3 ((SYSCFG_CFGR4_ADC12_EXT15_RMP << 16U) | SYSCFG_CFGR4_ADC12_EXT15_RMP)
233#define LL_SYSCFG_ADC12_JEXT3_RMP_TIM2_CC1 ((SYSCFG_CFGR4_ADC12_JEXT3_RMP << 16U) | (uint32_t)0x00000000U)
234#define LL_SYSCFG_ADC12_JEXT3_RMP_TIM20_TRGO ((SYSCFG_CFGR4_ADC12_JEXT3_RMP << 16U) | SYSCFG_CFGR4_ADC12_JEXT3_RMP)
235#define LL_SYSCFG_ADC12_JEXT6_RMP_EXTI_LINE_15 ((SYSCFG_CFGR4_ADC12_JEXT6_RMP << 16U) | (uint32_t)0x00000000U)
236#define LL_SYSCFG_ADC12_JEXT6_RMP_TIM20_TRGO2 ((SYSCFG_CFGR4_ADC12_JEXT6_RMP << 16U) | SYSCFG_CFGR4_ADC12_JEXT6_RMP)
237#define LL_SYSCFG_ADC12_JEXT13_RMP_TIM3_CC1 ((SYSCFG_CFGR4_ADC12_JEXT13_RMP << 16U) | (uint32_t)0x00000000U)
238#define LL_SYSCFG_ADC12_JEXT13_RMP_TIM20_CC4 ((SYSCFG_CFGR4_ADC12_JEXT13_RMP << 16U) | SYSCFG_CFGR4_ADC12_JEXT13_RMP)
239#define LL_SYSCFG_ADC34_EXT5_RMP_EXTI_LINE_2 ((SYSCFG_CFGR4_ADC34_EXT5_RMP << 16U) | (uint32_t)0x00000000U)
240#define LL_SYSCFG_ADC34_EXT5_RMP_TIM20_TRGO ((SYSCFG_CFGR4_ADC34_EXT5_RMP << 16U) | SYSCFG_CFGR4_ADC34_EXT5_RMP)
241#define LL_SYSCFG_ADC34_EXT6_RMP_TIM4_CC1 ((SYSCFG_CFGR4_ADC34_EXT6_RMP << 16U) | (uint32_t)0x00000000U)
242#define LL_SYSCFG_ADC34_EXT6_RMP_TIM20_TRGO2 ((SYSCFG_CFGR4_ADC34_EXT6_RMP << 16U) | SYSCFG_CFGR4_ADC34_EXT6_RMP)
243#define LL_SYSCFG_ADC34_EXT15_RMP_TIM2_CC1 ((SYSCFG_CFGR4_ADC34_EXT15_RMP << 16U) | (uint32_t)0x00000000U)
244#define LL_SYSCFG_ADC34_EXT15_RMP_TIM20_CC1 ((SYSCFG_CFGR4_ADC34_EXT15_RMP << 16U) | SYSCFG_CFGR4_ADC34_EXT15_RMP)
245#define LL_SYSCFG_ADC34_JEXT5_RMP_TIM4_CC3 ((SYSCFG_CFGR4_ADC34_JEXT5_RMP << 16U) | (uint32_t)0x00000000U)
246#define LL_SYSCFG_ADC34_JEXT5_RMP_TIM20_TRGO ((SYSCFG_CFGR4_ADC34_JEXT5_RMP << 16U) | SYSCFG_CFGR4_ADC34_JEXT5_RMP)
247#define LL_SYSCFG_ADC34_JEXT11_RMP_TIM1_CC3 ((SYSCFG_CFGR4_ADC34_JEXT11_RMP << 16U) | (uint32_t)0x00000000U)
248#define LL_SYSCFG_ADC34_JEXT11_RMP_TIM20_TRGO2 ((SYSCFG_CFGR4_ADC34_JEXT11_RMP << 16U) | SYSCFG_CFGR4_ADC34_JEXT11_RMP)
249#define LL_SYSCFG_ADC34_JEXT14_RMP_TIM7_TRGO ((SYSCFG_CFGR4_ADC34_JEXT14_RMP << 16U) | (uint32_t)0x00000000U)
250#define LL_SYSCFG_ADC34_JEXT14_RMP_TIM20_CC2 ((SYSCFG_CFGR4_ADC34_JEXT14_RMP << 16U) | SYSCFG_CFGR4_ADC34_JEXT14_RMP)
255#endif /* SYSCFG_CFGR4_ADC12_EXT2_RMP */
256
257#if defined(SYSCFG_CFGR1_DAC1_TRIG1_RMP) || defined(SYSCFG_CFGR3_TRIGGER_RMP)
261#if defined(SYSCFG_CFGR1_DAC1_TRIG1_RMP)
262#define LL_SYSCFG_DAC1_TRIG1_RMP_TIM8_TRGO (SYSCFG_OFFSET_CFGR1 << 24U | SYSCFG_CFGR1_DAC1_TRIG1_RMP << 4 | (uint32_t)0x00000000U)
263#define LL_SYSCFG_DAC1_TRIG1_RMP_TIM3_TRGO (SYSCFG_OFFSET_CFGR1 << 24U | SYSCFG_CFGR1_DAC1_TRIG1_RMP << 4 | SYSCFG_CFGR1_DAC1_TRIG1_RMP)
264#endif /* SYSCFG_CFGR1_DAC1_TRIG1_RMP */
265#if defined(SYSCFG_CFGR3_DAC1_TRG3_RMP)
266#define LL_SYSCFG_DAC1_TRIG3_RMP_TIM15_TRGO (SYSCFG_OFFSET_CFGR3 << 24U | SYSCFG_CFGR3_DAC1_TRG3_RMP << 4 | (uint32_t)0x00000000U)
267#define LL_SYSCFG_DAC1_TRIG3_RMP_HRTIM1_DAC1_TRIG1 (SYSCFG_OFFSET_CFGR3 << 24U | SYSCFG_CFGR3_DAC1_TRG3_RMP << 4 | SYSCFG_CFGR3_DAC1_TRG3_RMP)
268#endif /* SYSCFG_CFGR3_DAC1_TRG3_RMP */
269#if defined(SYSCFG_CFGR3_DAC1_TRG5_RMP)
270#define LL_SYSCFG_DAC1_TRIG5_RMP_NO (SYSCFG_OFFSET_CFGR3 << 24U | SYSCFG_CFGR3_DAC1_TRG5_RMP << 4 | (uint32_t)0x00000000U)
271#define LL_SYSCFG_DAC1_TRIG5_RMP_HRTIM1_DAC1_TRIG2 (SYSCFG_OFFSET_CFGR3 << 24U | SYSCFG_CFGR3_DAC1_TRG5_RMP << 4 | SYSCFG_CFGR3_DAC1_TRG5_RMP)
272#endif /* SYSCFG_CFGR3_DAC1_TRG5_RMP */
277#endif /* SYSCFG_CFGR1_DAC1_TRIG1_RMP || SYSCFG_CFGR3_TRIGGER_RMP */
278
282#define LL_SYSCFG_I2C_FASTMODEPLUS_PB6 SYSCFG_CFGR1_I2C_PB6_FMP
283#define LL_SYSCFG_I2C_FASTMODEPLUS_PB7 SYSCFG_CFGR1_I2C_PB7_FMP
284#define LL_SYSCFG_I2C_FASTMODEPLUS_PB8 SYSCFG_CFGR1_I2C_PB8_FMP
285#define LL_SYSCFG_I2C_FASTMODEPLUS_PB9 SYSCFG_CFGR1_I2C_PB9_FMP
286#define LL_SYSCFG_I2C_FASTMODEPLUS_I2C1 SYSCFG_CFGR1_I2C1_FMP
287#if defined(SYSCFG_CFGR1_I2C2_FMP)
288#define LL_SYSCFG_I2C_FASTMODEPLUS_I2C2 SYSCFG_CFGR1_I2C2_FMP
289#endif /*SYSCFG_CFGR1_I2C2_FMP*/
290#if defined(SYSCFG_CFGR1_I2C3_FMP)
291#define LL_SYSCFG_I2C_FASTMODEPLUS_I2C3 SYSCFG_CFGR1_I2C3_FMP
292#endif /*SYSCFG_CFGR1_I2C3_FMP*/
300#define LL_SYSCFG_EXTI_PORTA (uint32_t)0U
301#define LL_SYSCFG_EXTI_PORTB (uint32_t)1U
302#define LL_SYSCFG_EXTI_PORTC (uint32_t)2U
303#define LL_SYSCFG_EXTI_PORTD (uint32_t)3U
304#if defined(GPIOE)
305#define LL_SYSCFG_EXTI_PORTE (uint32_t)4U
306#endif /* GPIOE */
307#define LL_SYSCFG_EXTI_PORTF (uint32_t)5U
308#if defined(GPIOG)
309#define LL_SYSCFG_EXTI_PORTG (uint32_t)6U
310#endif /* GPIOG */
311#if defined(GPIOH)
312#define LL_SYSCFG_EXTI_PORTH (uint32_t)7U
313#endif /* GPIOH */
321#define LL_SYSCFG_EXTI_LINE0 (uint32_t)(0x000FU << 16U | 0U) /* EXTI_POSITION_0 | EXTICR[0] */
322#define LL_SYSCFG_EXTI_LINE1 (uint32_t)(0x00F0U << 16U | 0U) /* EXTI_POSITION_4 | EXTICR[0] */
323#define LL_SYSCFG_EXTI_LINE2 (uint32_t)(0x0F00U << 16U | 0U) /* EXTI_POSITION_8 | EXTICR[0] */
324#define LL_SYSCFG_EXTI_LINE3 (uint32_t)(0xF000U << 16U | 0U) /* EXTI_POSITION_12 | EXTICR[0] */
325#define LL_SYSCFG_EXTI_LINE4 (uint32_t)(0x000FU << 16U | 1U) /* EXTI_POSITION_0 | EXTICR[1] */
326#define LL_SYSCFG_EXTI_LINE5 (uint32_t)(0x00F0U << 16U | 1U) /* EXTI_POSITION_4 | EXTICR[1] */
327#define LL_SYSCFG_EXTI_LINE6 (uint32_t)(0x0F00U << 16U | 1U) /* EXTI_POSITION_8 | EXTICR[1] */
328#define LL_SYSCFG_EXTI_LINE7 (uint32_t)(0xF000U << 16U | 1U) /* EXTI_POSITION_12 | EXTICR[1] */
329#define LL_SYSCFG_EXTI_LINE8 (uint32_t)(0x000FU << 16U | 2U) /* EXTI_POSITION_0 | EXTICR[2] */
330#define LL_SYSCFG_EXTI_LINE9 (uint32_t)(0x00F0U << 16U | 2U) /* EXTI_POSITION_4 | EXTICR[2] */
331#define LL_SYSCFG_EXTI_LINE10 (uint32_t)(0x0F00U << 16U | 2U) /* EXTI_POSITION_8 | EXTICR[2] */
332#define LL_SYSCFG_EXTI_LINE11 (uint32_t)(0xF000U << 16U | 2U) /* EXTI_POSITION_12 | EXTICR[2] */
333#define LL_SYSCFG_EXTI_LINE12 (uint32_t)(0x000FU << 16U | 3U) /* EXTI_POSITION_0 | EXTICR[3] */
334#define LL_SYSCFG_EXTI_LINE13 (uint32_t)(0x00F0U << 16U | 3U) /* EXTI_POSITION_4 | EXTICR[3] */
335#define LL_SYSCFG_EXTI_LINE14 (uint32_t)(0x0F00U << 16U | 3U) /* EXTI_POSITION_8 | EXTICR[3] */
336#define LL_SYSCFG_EXTI_LINE15 (uint32_t)(0xF000U << 16U | 3U) /* EXTI_POSITION_12 | EXTICR[3] */
344#if defined(SYSCFG_CFGR2_PVD_LOCK)
345#define LL_SYSCFG_TIMBREAK_PVD SYSCFG_CFGR2_PVD_LOCK
346#endif /*SYSCFG_CFGR2_PVD_LOCK*/
347#if defined(SYSCFG_CFGR2_SRAM_PARITY_LOCK)
348#define LL_SYSCFG_TIMBREAK_SRAM_PARITY SYSCFG_CFGR2_SRAM_PARITY_LOCK
349#endif /* SYSCFG_CFGR2_SRAM_PARITY_LOCK */
350#define LL_SYSCFG_TIMBREAK_LOCKUP SYSCFG_CFGR2_LOCKUP_LOCK
355#if defined(SYSCFG_RCR_PAGE0)
359#define LL_SYSCFG_CCMSRAMWRP_PAGE0 SYSCFG_RCR_PAGE0
360#define LL_SYSCFG_CCMSRAMWRP_PAGE1 SYSCFG_RCR_PAGE1
361#define LL_SYSCFG_CCMSRAMWRP_PAGE2 SYSCFG_RCR_PAGE2
362#define LL_SYSCFG_CCMSRAMWRP_PAGE3 SYSCFG_RCR_PAGE3
363#if defined(SYSCFG_RCR_PAGE4)
364#define LL_SYSCFG_CCMSRAMWRP_PAGE4 SYSCFG_RCR_PAGE4
365#define LL_SYSCFG_CCMSRAMWRP_PAGE5 SYSCFG_RCR_PAGE5
366#define LL_SYSCFG_CCMSRAMWRP_PAGE6 SYSCFG_RCR_PAGE6
367#define LL_SYSCFG_CCMSRAMWRP_PAGE7 SYSCFG_RCR_PAGE7
368#endif
369#if defined(SYSCFG_RCR_PAGE8)
370#define LL_SYSCFG_CCMSRAMWRP_PAGE8 SYSCFG_RCR_PAGE8
371#define LL_SYSCFG_CCMSRAMWRP_PAGE9 SYSCFG_RCR_PAGE9
372#define LL_SYSCFG_CCMSRAMWRP_PAGE10 SYSCFG_RCR_PAGE10
373#define LL_SYSCFG_CCMSRAMWRP_PAGE11 SYSCFG_RCR_PAGE11
374#define LL_SYSCFG_CCMSRAMWRP_PAGE12 SYSCFG_RCR_PAGE12
375#define LL_SYSCFG_CCMSRAMWRP_PAGE13 SYSCFG_RCR_PAGE13
376#define LL_SYSCFG_CCMSRAMWRP_PAGE14 SYSCFG_RCR_PAGE14
377#define LL_SYSCFG_CCMSRAMWRP_PAGE15 SYSCFG_RCR_PAGE15
378#endif
383#endif /* SYSCFG_RCR_PAGE0 */
384
388#define LL_DBGMCU_TRACE_NONE 0x00000000U
389#define LL_DBGMCU_TRACE_ASYNCH DBGMCU_CR_TRACE_IOEN
390#define LL_DBGMCU_TRACE_SYNCH_SIZE1 (DBGMCU_CR_TRACE_IOEN | DBGMCU_CR_TRACE_MODE_0)
391#define LL_DBGMCU_TRACE_SYNCH_SIZE2 (DBGMCU_CR_TRACE_IOEN | DBGMCU_CR_TRACE_MODE_1)
392#define LL_DBGMCU_TRACE_SYNCH_SIZE4 (DBGMCU_CR_TRACE_IOEN | DBGMCU_CR_TRACE_MODE)
400#define LL_DBGMCU_APB1_GRP1_TIM2_STOP DBGMCU_APB1_FZ_DBG_TIM2_STOP
401#if defined(DBGMCU_APB1_FZ_DBG_TIM3_STOP)
402#define LL_DBGMCU_APB1_GRP1_TIM3_STOP DBGMCU_APB1_FZ_DBG_TIM3_STOP
403#endif /*DBGMCU_APB1_FZ_DBG_TIM3_STOP*/
404#if defined(DBGMCU_APB1_FZ_DBG_TIM4_STOP)
405#define LL_DBGMCU_APB1_GRP1_TIM4_STOP DBGMCU_APB1_FZ_DBG_TIM4_STOP
406#endif /*DBGMCU_APB1_FZ_DBG_TIM4_STOP*/
407#if defined(DBGMCU_APB1_FZ_DBG_TIM5_STOP)
408#define LL_DBGMCU_APB1_GRP1_TIM5_STOP DBGMCU_APB1_FZ_DBG_TIM5_STOP
409#endif /*DBGMCU_APB1_FZ_DBG_TIM5_STOP*/
410#define LL_DBGMCU_APB1_GRP1_TIM6_STOP DBGMCU_APB1_FZ_DBG_TIM6_STOP
411#if defined(DBGMCU_APB1_FZ_DBG_TIM7_STOP)
412#define LL_DBGMCU_APB1_GRP1_TIM7_STOP DBGMCU_APB1_FZ_DBG_TIM7_STOP
413#endif /*DBGMCU_APB1_FZ_DBG_TIM7_STOP*/
414#if defined(DBGMCU_APB1_FZ_DBG_TIM12_STOP)
415#define LL_DBGMCU_APB1_GRP1_TIM12_STOP DBGMCU_APB1_FZ_DBG_TIM12_STOP
416#endif /*DBGMCU_APB1_FZ_DBG_TIM12_STOP*/
417#if defined(DBGMCU_APB1_FZ_DBG_TIM13_STOP)
418#define LL_DBGMCU_APB1_GRP1_TIM13_STOP DBGMCU_APB1_FZ_DBG_TIM13_STOP
419#endif /*DBGMCU_APB1_FZ_DBG_TIM13_STOP*/
420#if defined(DBGMCU_APB1_FZ_DBG_TIM14_STOP)
421#define LL_DBGMCU_APB1_GRP1_TIM14_STOP DBGMCU_APB1_FZ_DBG_TIM14_STOP
422#endif /*DBGMCU_APB1_FZ_DBG_TIM14_STOP*/
423#if defined(DBGMCU_APB1_FZ_DBG_TIM18_STOP)
424#define LL_DBGMCU_APB1_GRP1_TIM18_STOP DBGMCU_APB1_FZ_DBG_TIM18_STOP
425#endif /*DBGMCU_APB1_FZ_DBG_TIM18_STOP*/
426#define LL_DBGMCU_APB1_GRP1_RTC_STOP DBGMCU_APB1_FZ_DBG_RTC_STOP
427#define LL_DBGMCU_APB1_GRP1_WWDG_STOP DBGMCU_APB1_FZ_DBG_WWDG_STOP
428#define LL_DBGMCU_APB1_GRP1_IWDG_STOP DBGMCU_APB1_FZ_DBG_IWDG_STOP
429#define LL_DBGMCU_APB1_GRP1_I2C1_STOP DBGMCU_APB1_FZ_DBG_I2C1_SMBUS_TIMEOUT
430#if defined(DBGMCU_APB1_FZ_DBG_I2C2_SMBUS_TIMEOUT)
431#define LL_DBGMCU_APB1_GRP1_I2C2_STOP DBGMCU_APB1_FZ_DBG_I2C2_SMBUS_TIMEOUT
432#endif /*DBGMCU_APB1_FZ_DBG_I2C2_SMBUS_TIMEOUT*/
433#if defined(DBGMCU_APB1_FZ_DBG_I2C3_SMBUS_TIMEOUT)
434#define LL_DBGMCU_APB1_GRP1_I2C3_STOP DBGMCU_APB1_FZ_DBG_I2C3_SMBUS_TIMEOUT
435#endif /*DBGMCU_APB1_FZ_DBG_I2C3_SMBUS_TIMEOUT*/
436#if defined(DBGMCU_APB1_FZ_DBG_CAN_STOP)
437#define LL_DBGMCU_APB1_GRP1_CAN_STOP DBGMCU_APB1_FZ_DBG_CAN_STOP
438#endif /*DBGMCU_APB1_FZ_DBG_CAN_STOP*/
446#if defined(DBGMCU_APB2_FZ_DBG_TIM1_STOP)
447#define LL_DBGMCU_APB2_GRP1_TIM1_STOP DBGMCU_APB2_FZ_DBG_TIM1_STOP
448#endif /*DBGMCU_APB2_FZ_DBG_TIM1_STOP*/
449#if defined(DBGMCU_APB2_FZ_DBG_TIM8_STOP)
450#define LL_DBGMCU_APB2_GRP1_TIM8_STOP DBGMCU_APB2_FZ_DBG_TIM8_STOP
451#endif /*DBGMCU_APB2_FZ_DBG_TIM8_STOP*/
452#define LL_DBGMCU_APB2_GRP1_TIM15_STOP DBGMCU_APB2_FZ_DBG_TIM15_STOP
453#define LL_DBGMCU_APB2_GRP1_TIM16_STOP DBGMCU_APB2_FZ_DBG_TIM16_STOP
454#define LL_DBGMCU_APB2_GRP1_TIM17_STOP DBGMCU_APB2_FZ_DBG_TIM17_STOP
455#if defined(DBGMCU_APB2_FZ_DBG_TIM19_STOP)
456#define LL_DBGMCU_APB2_GRP1_TIM19_STOP DBGMCU_APB2_FZ_DBG_TIM19_STOP
457#endif /*DBGMCU_APB2_FZ_DBG_TIM19_STOP*/
458#if defined(DBGMCU_APB2_FZ_DBG_TIM20_STOP)
459#define LL_DBGMCU_APB2_GRP1_TIM20_STOP DBGMCU_APB2_FZ_DBG_TIM20_STOP
460#endif /*DBGMCU_APB2_FZ_DBG_TIM20_STOP*/
461#if defined(DBGMCU_APB2_FZ_DBG_HRTIM1_STOP)
462#define LL_DBGMCU_APB2_GRP1_HRTIM1_STOP DBGMCU_APB2_FZ_DBG_HRTIM1_STOP
463#endif /*DBGMCU_APB2_FZ_DBG_HRTIM1_STOP*/
471#define LL_FLASH_LATENCY_0 0x00000000U
472#define LL_FLASH_LATENCY_1 FLASH_ACR_LATENCY_0
473#define LL_FLASH_LATENCY_2 FLASH_ACR_LATENCY_1
482/* Exported macro ------------------------------------------------------------*/
483
484/* Exported functions --------------------------------------------------------*/
505__STATIC_INLINE void LL_SYSCFG_SetRemapMemory(uint32_t Memory)
506{
507 MODIFY_REG(SYSCFG->CFGR1, SYSCFG_CFGR1_MEM_MODE, Memory);
508}
509
521__STATIC_INLINE uint32_t LL_SYSCFG_GetRemapMemory(void)
522{
523 return (uint32_t)(READ_BIT(SYSCFG->CFGR1, SYSCFG_CFGR1_MEM_MODE));
524}
525
526#if defined(SYSCFG_CFGR3_SPI1_RX_DMA_RMP)
540__STATIC_INLINE void LL_SYSCFG_SetRemapDMA_SPI(uint32_t Remap)
541{
542 MODIFY_REG(SYSCFG->CFGR3, (Remap >> 16U), (Remap & 0x0000FFFF));
543}
544#endif /* SYSCFG_CFGR3_SPI1_RX_DMA_RMP */
545
546#if defined(SYSCFG_CFGR3_I2C1_RX_DMA_RMP)
560__STATIC_INLINE void LL_SYSCFG_SetRemapDMA_I2C(uint32_t Remap)
561{
562 MODIFY_REG(SYSCFG->CFGR3, (Remap >> 16U), (Remap & 0x0000FFFF));
563}
564#endif /* SYSCFG_CFGR3_I2C1_RX_DMA_RMP */
565
566#if defined(SYSCFG_CFGR1_ADC24_DMA_RMP) || defined(SYSCFG_CFGR3_ADC2_DMA_RMP)
582__STATIC_INLINE void LL_SYSCFG_SetRemapDMA_ADC(uint32_t Remap)
583{
584 __IO uint32_t *reg = (__IO uint32_t *)(uint32_t)(SYSCFG_BASE + (Remap >> 24U));
585 MODIFY_REG(*reg, (Remap & 0x00FF0000U) >> 8U, (Remap & 0x0000FFFFU));
586}
587#endif /* SYSCFG_CFGR1_ADC24_DMA_RMP || SYSCFG_CFGR3_ADC2_DMA_RMP */
588
606__STATIC_INLINE void LL_SYSCFG_SetRemapDMA_DAC(uint32_t Remap)
607{
608 MODIFY_REG(SYSCFG->CFGR1, (Remap & 0x00FF0000U) >> 8U, (Remap & 0x0000FF00U));
609}
610
628__STATIC_INLINE void LL_SYSCFG_SetRemapDMA_TIM(uint32_t Remap)
629{
630 MODIFY_REG(SYSCFG->CFGR1, (Remap & 0x00FF0000U) >> 8U, (Remap & 0x0000FF00U));
631}
632
633#if defined(SYSCFG_CFGR1_TIM1_ITR3_RMP) || defined(SYSCFG_CFGR1_ENCODER_MODE)
649__STATIC_INLINE void LL_SYSCFG_SetRemapInput_TIM(uint32_t Remap)
650{
651 MODIFY_REG(SYSCFG->CFGR1, (Remap & 0xFF00FF00U) >> 8U, (Remap & 0x00FF00FFU));
652}
653#endif /* SYSCFG_CFGR1_TIM1_ITR3_RMP || SYSCFG_CFGR1_ENCODER_MODE */
654
655#if defined(SYSCFG_CFGR4_ADC12_EXT2_RMP)
703__STATIC_INLINE void LL_SYSCFG_SetRemapTrigger_ADC(uint32_t Remap)
704{
705 MODIFY_REG(SYSCFG->CFGR4, (Remap & 0xFFFF0000U) >> 16U, (Remap & 0x0000FFFFU));
706}
707#endif /* SYSCFG_CFGR4_ADC12_EXT2_RMP */
708
709#if defined(SYSCFG_CFGR1_DAC1_TRIG1_RMP) || defined(SYSCFG_CFGR3_TRIGGER_RMP)
725__STATIC_INLINE void LL_SYSCFG_SetRemapTrigger_DAC(uint32_t Remap)
726{
727 __IO uint32_t *reg = (__IO uint32_t *)(uint32_t)(SYSCFG_BASE + (Remap >> 24U));
728 MODIFY_REG(*reg, (Remap & 0x00F00F00U) >> 4U, (Remap & 0x000F00F0U));
729}
730#endif /* SYSCFG_CFGR1_DAC1_TRIG1_RMP || SYSCFG_CFGR3_TRIGGER_RMP */
731
732#if defined(SYSCFG_CFGR1_USB_IT_RMP)
740__STATIC_INLINE void LL_SYSCFG_EnableRemapIT_USB(void)
741{
742 SET_BIT(SYSCFG->CFGR1, SYSCFG_CFGR1_USB_IT_RMP);
743}
744
750__STATIC_INLINE void LL_SYSCFG_DisableRemapIT_USB(void)
751{
752 CLEAR_BIT(SYSCFG->CFGR1, SYSCFG_CFGR1_USB_IT_RMP);
753}
754#endif /* SYSCFG_CFGR1_USB_IT_RMP */
755
756#if defined(SYSCFG_CFGR1_VBAT)
762__STATIC_INLINE void LL_SYSCFG_EnableVBATMonitoring(void)
763{
764 SET_BIT(SYSCFG->CFGR1, SYSCFG_CFGR1_VBAT);
765}
766
772__STATIC_INLINE void LL_SYSCFG_DisableVBATMonitoring(void)
773{
774 CLEAR_BIT(SYSCFG->CFGR1, SYSCFG_CFGR1_VBAT);
775}
776#endif /* SYSCFG_CFGR1_VBAT */
777
799__STATIC_INLINE void LL_SYSCFG_EnableFastModePlus(uint32_t ConfigFastModePlus)
800{
801 SET_BIT(SYSCFG->CFGR1, ConfigFastModePlus);
802}
803
825__STATIC_INLINE void LL_SYSCFG_DisableFastModePlus(uint32_t ConfigFastModePlus)
826{
827 CLEAR_BIT(SYSCFG->CFGR1, ConfigFastModePlus);
828}
829
835__STATIC_INLINE void LL_SYSCFG_EnableIT_FPU_IOC(void)
836{
837 SET_BIT(SYSCFG->CFGR1, SYSCFG_CFGR1_FPU_IE_0);
838}
839
845__STATIC_INLINE void LL_SYSCFG_EnableIT_FPU_DZC(void)
846{
847 SET_BIT(SYSCFG->CFGR1, SYSCFG_CFGR1_FPU_IE_1);
848}
849
855__STATIC_INLINE void LL_SYSCFG_EnableIT_FPU_UFC(void)
856{
857 SET_BIT(SYSCFG->CFGR1, SYSCFG_CFGR1_FPU_IE_2);
858}
859
865__STATIC_INLINE void LL_SYSCFG_EnableIT_FPU_OFC(void)
866{
867 SET_BIT(SYSCFG->CFGR1, SYSCFG_CFGR1_FPU_IE_3);
868}
869
875__STATIC_INLINE void LL_SYSCFG_EnableIT_FPU_IDC(void)
876{
877 SET_BIT(SYSCFG->CFGR1, SYSCFG_CFGR1_FPU_IE_4);
878}
879
885__STATIC_INLINE void LL_SYSCFG_EnableIT_FPU_IXC(void)
886{
887 SET_BIT(SYSCFG->CFGR1, SYSCFG_CFGR1_FPU_IE_5);
888}
889
895__STATIC_INLINE void LL_SYSCFG_DisableIT_FPU_IOC(void)
896{
897 CLEAR_BIT(SYSCFG->CFGR1, SYSCFG_CFGR1_FPU_IE_0);
898}
899
905__STATIC_INLINE void LL_SYSCFG_DisableIT_FPU_DZC(void)
906{
907 CLEAR_BIT(SYSCFG->CFGR1, SYSCFG_CFGR1_FPU_IE_1);
908}
909
915__STATIC_INLINE void LL_SYSCFG_DisableIT_FPU_UFC(void)
916{
917 CLEAR_BIT(SYSCFG->CFGR1, SYSCFG_CFGR1_FPU_IE_2);
918}
919
925__STATIC_INLINE void LL_SYSCFG_DisableIT_FPU_OFC(void)
926{
927 CLEAR_BIT(SYSCFG->CFGR1, SYSCFG_CFGR1_FPU_IE_3);
928}
929
935__STATIC_INLINE void LL_SYSCFG_DisableIT_FPU_IDC(void)
936{
937 CLEAR_BIT(SYSCFG->CFGR1, SYSCFG_CFGR1_FPU_IE_4);
938}
939
945__STATIC_INLINE void LL_SYSCFG_DisableIT_FPU_IXC(void)
946{
947 CLEAR_BIT(SYSCFG->CFGR1, SYSCFG_CFGR1_FPU_IE_5);
948}
949
955__STATIC_INLINE uint32_t LL_SYSCFG_IsEnabledIT_FPU_IOC(void)
956{
957 return (READ_BIT(SYSCFG->CFGR1, SYSCFG_CFGR1_FPU_IE_0) == (SYSCFG_CFGR1_FPU_IE_0));
958}
959
965__STATIC_INLINE uint32_t LL_SYSCFG_IsEnabledIT_FPU_DZC(void)
966{
967 return (READ_BIT(SYSCFG->CFGR1, SYSCFG_CFGR1_FPU_IE_1) == (SYSCFG_CFGR1_FPU_IE_1));
968}
969
975__STATIC_INLINE uint32_t LL_SYSCFG_IsEnabledIT_FPU_UFC(void)
976{
977 return (READ_BIT(SYSCFG->CFGR1, SYSCFG_CFGR1_FPU_IE_2) == (SYSCFG_CFGR1_FPU_IE_2));
978}
979
985__STATIC_INLINE uint32_t LL_SYSCFG_IsEnabledIT_FPU_OFC(void)
986{
987 return (READ_BIT(SYSCFG->CFGR1, SYSCFG_CFGR1_FPU_IE_3) == (SYSCFG_CFGR1_FPU_IE_3));
988}
989
995__STATIC_INLINE uint32_t LL_SYSCFG_IsEnabledIT_FPU_IDC(void)
996{
997 return (READ_BIT(SYSCFG->CFGR1, SYSCFG_CFGR1_FPU_IE_4) == (SYSCFG_CFGR1_FPU_IE_4));
998}
999
1005__STATIC_INLINE uint32_t LL_SYSCFG_IsEnabledIT_FPU_IXC(void)
1006{
1007 return (READ_BIT(SYSCFG->CFGR1, SYSCFG_CFGR1_FPU_IE_5) == (SYSCFG_CFGR1_FPU_IE_5));
1008}
1009
1106__STATIC_INLINE void LL_SYSCFG_SetEXTISource(uint32_t Port, uint32_t Line)
1107{
1108 MODIFY_REG(SYSCFG->EXTICR[Line & 0x3U], (Line >> 16U), Port << POSITION_VAL((Line >> 16U)));
1109}
1110
1206__STATIC_INLINE uint32_t LL_SYSCFG_GetEXTISource(uint32_t Line)
1207{
1208 return (uint32_t)(READ_BIT(SYSCFG->EXTICR[Line & 0x3U], (Line >> 16U)) >> POSITION_VAL(Line >> 16U));
1209}
1210
1224__STATIC_INLINE void LL_SYSCFG_SetTIMBreakInputs(uint32_t Break)
1225{
1226 MODIFY_REG(SYSCFG->CFGR2, SYSCFG_MASK_TIM_BREAK, Break);
1227}
1228
1241__STATIC_INLINE uint32_t LL_SYSCFG_GetTIMBreakInputs(void)
1242{
1243 return (uint32_t)(READ_BIT(SYSCFG->CFGR2, SYSCFG_MASK_TIM_BREAK));
1244}
1245
1246#if defined(SYSCFG_CFGR2_BYP_ADDR_PAR)
1252__STATIC_INLINE void LL_SYSCFG_DisableSRAMParityCheck(void)
1253{
1254 SET_BIT(SYSCFG->CFGR2, SYSCFG_CFGR2_BYP_ADDR_PAR);
1255}
1256#endif /* SYSCFG_CFGR2_BYP_ADDR_PAR */
1257
1258#if defined(SYSCFG_CFGR2_SRAM_PE)
1264__STATIC_INLINE uint32_t LL_SYSCFG_IsActiveFlag_SP(void)
1265{
1266 return (READ_BIT(SYSCFG->CFGR2, SYSCFG_CFGR2_SRAM_PE) == (SYSCFG_CFGR2_SRAM_PE));
1267}
1268
1274__STATIC_INLINE void LL_SYSCFG_ClearFlag_SP(void)
1275{
1276 SET_BIT(SYSCFG->CFGR2, SYSCFG_CFGR2_SRAM_PE);
1277}
1278#endif /* SYSCFG_CFGR2_SRAM_PE */
1279
1280#if defined(SYSCFG_RCR_PAGE0)
1321__STATIC_INLINE void LL_SYSCFG_EnableCCM_SRAMPageWRP(uint32_t PageWRP)
1322{
1323 SET_BIT(SYSCFG->RCR, PageWRP);
1324}
1325#endif /* SYSCFG_RCR_PAGE0 */
1326
1345__STATIC_INLINE uint32_t LL_DBGMCU_GetDeviceID(void)
1346{
1347 return (uint32_t)(READ_BIT(DBGMCU->IDCODE, DBGMCU_IDCODE_DEV_ID));
1348}
1349
1356__STATIC_INLINE uint32_t LL_DBGMCU_GetRevisionID(void)
1357{
1358 return (uint32_t)(READ_BIT(DBGMCU->IDCODE, DBGMCU_IDCODE_REV_ID) >> DBGMCU_IDCODE_REV_ID_Pos);
1359}
1360
1366__STATIC_INLINE void LL_DBGMCU_EnableDBGSleepMode(void)
1367{
1368 SET_BIT(DBGMCU->CR, DBGMCU_CR_DBG_SLEEP);
1369}
1370
1376__STATIC_INLINE void LL_DBGMCU_DisableDBGSleepMode(void)
1377{
1378 CLEAR_BIT(DBGMCU->CR, DBGMCU_CR_DBG_SLEEP);
1379}
1380
1386__STATIC_INLINE void LL_DBGMCU_EnableDBGStopMode(void)
1387{
1388 SET_BIT(DBGMCU->CR, DBGMCU_CR_DBG_STOP);
1389}
1390
1396__STATIC_INLINE void LL_DBGMCU_DisableDBGStopMode(void)
1397{
1398 CLEAR_BIT(DBGMCU->CR, DBGMCU_CR_DBG_STOP);
1399}
1400
1406__STATIC_INLINE void LL_DBGMCU_EnableDBGStandbyMode(void)
1407{
1408 SET_BIT(DBGMCU->CR, DBGMCU_CR_DBG_STANDBY);
1409}
1410
1416__STATIC_INLINE void LL_DBGMCU_DisableDBGStandbyMode(void)
1417{
1418 CLEAR_BIT(DBGMCU->CR, DBGMCU_CR_DBG_STANDBY);
1419}
1420
1433__STATIC_INLINE void LL_DBGMCU_SetTracePinAssignment(uint32_t PinAssignment)
1434{
1435 MODIFY_REG(DBGMCU->CR, DBGMCU_CR_TRACE_IOEN | DBGMCU_CR_TRACE_MODE, PinAssignment);
1436}
1437
1449__STATIC_INLINE uint32_t LL_DBGMCU_GetTracePinAssignment(void)
1450{
1451 return (uint32_t)(READ_BIT(DBGMCU->CR, DBGMCU_CR_TRACE_IOEN | DBGMCU_CR_TRACE_MODE));
1452}
1453
1495__STATIC_INLINE void LL_DBGMCU_APB1_GRP1_FreezePeriph(uint32_t Periphs)
1496{
1497 SET_BIT(DBGMCU->APB1FZ, Periphs);
1498}
1499
1541__STATIC_INLINE void LL_DBGMCU_APB1_GRP1_UnFreezePeriph(uint32_t Periphs)
1542{
1543 CLEAR_BIT(DBGMCU->APB1FZ, Periphs);
1544}
1545
1569__STATIC_INLINE void LL_DBGMCU_APB2_GRP1_FreezePeriph(uint32_t Periphs)
1570{
1571 SET_BIT(DBGMCU->APB2FZ, Periphs);
1572}
1573
1597__STATIC_INLINE void LL_DBGMCU_APB2_GRP1_UnFreezePeriph(uint32_t Periphs)
1598{
1599 CLEAR_BIT(DBGMCU->APB2FZ, Periphs);
1600}
1601
1619__STATIC_INLINE void LL_FLASH_SetLatency(uint32_t Latency)
1620{
1621 MODIFY_REG(FLASH->ACR, FLASH_ACR_LATENCY, Latency);
1622}
1623
1632__STATIC_INLINE uint32_t LL_FLASH_GetLatency(void)
1633{
1634 return (uint32_t)(READ_BIT(FLASH->ACR, FLASH_ACR_LATENCY));
1635}
1636
1642__STATIC_INLINE void LL_FLASH_EnablePrefetch(void)
1643{
1644 SET_BIT(FLASH->ACR, FLASH_ACR_PRFTBE );
1645}
1646
1652__STATIC_INLINE void LL_FLASH_DisablePrefetch(void)
1653{
1654 CLEAR_BIT(FLASH->ACR, FLASH_ACR_PRFTBE );
1655}
1656
1662__STATIC_INLINE uint32_t LL_FLASH_IsPrefetchEnabled(void)
1663{
1664 return (READ_BIT(FLASH->ACR, FLASH_ACR_PRFTBS) == (FLASH_ACR_PRFTBS));
1665}
1666
1667#if defined(FLASH_ACR_HLFCYA)
1673__STATIC_INLINE void LL_FLASH_EnableHalfCycleAccess(void)
1674{
1675 SET_BIT(FLASH->ACR, FLASH_ACR_HLFCYA);
1676}
1677
1683__STATIC_INLINE void LL_FLASH_DisableHalfCycleAccess(void)
1684{
1685 CLEAR_BIT(FLASH->ACR, FLASH_ACR_HLFCYA);
1686}
1687
1693__STATIC_INLINE uint32_t LL_FLASH_IsHalfCycleAccessEnabled(void)
1694{
1695 return (READ_BIT(FLASH->ACR, FLASH_ACR_HLFCYA) == (FLASH_ACR_HLFCYA));
1696}
1697#endif /* FLASH_ACR_HLFCYA */
1698
1699
1700
1713#endif /* defined (FLASH) || defined (SYSCFG) || defined (DBGMCU) */
1714
1719#ifdef __cplusplus
1720}
1721#endif
1722
1723#endif /* __STM32F3xx_LL_SYSTEM_H */
1724
1725
__STATIC_INLINE
#define __STATIC_INLINE
Definition: cmsis_armcc.h:59
__IO
#define __IO
Definition: core_armv8mbl.h:196
CLEAR_BIT
#define CLEAR_BIT(REG, BIT)
Definition: stm32f3xx.h:192
SET_BIT
#define SET_BIT(REG, BIT)
Definition: stm32f3xx.h:190
POSITION_VAL
#define POSITION_VAL(VAL)
Definition: stm32f3xx.h:204
MODIFY_REG
#define MODIFY_REG(REG, CLEARMASK, SETMASK)
Definition: stm32f3xx.h:202
READ_BIT
#define READ_BIT(REG, BIT)
Definition: stm32f3xx.h:194
DBGMCU_CR_DBG_SLEEP
#define DBGMCU_CR_DBG_SLEEP
Definition: stm32f303xe.h:6771
SYSCFG_CFGR2_BYP_ADDR_PAR
#define SYSCFG_CFGR2_BYP_ADDR_PAR
Definition: stm32f303xe.h:12812
DBGMCU_CR_DBG_STANDBY
#define DBGMCU_CR_DBG_STANDBY
Definition: stm32f303xe.h:6777
FLASH_ACR_PRFTBS
#define FLASH_ACR_PRFTBS
Definition: stm32f303xe.h:8125
SYSCFG_CFGR1_USB_IT_RMP
#define SYSCFG_CFGR1_USB_IT_RMP
Definition: stm32f303xe.h:12448
SYSCFG_CFGR1_FPU_IE_1
#define SYSCFG_CFGR1_FPU_IE_1
Definition: stm32f303xe.h:12509
FLASH_ACR_PRFTBE
#define FLASH_ACR_PRFTBE
Definition: stm32f303xe.h:8122
FLASH_ACR_HLFCYA
#define FLASH_ACR_HLFCYA
Definition: stm32f303xe.h:8119
DBGMCU_IDCODE_REV_ID_Pos
#define DBGMCU_IDCODE_REV_ID_Pos
Definition: stm32f303xe.h:6764
SYSCFG_CFGR2_SRAM_PE
#define SYSCFG_CFGR2_SRAM_PE
Definition: stm32f303xe.h:12815
SYSCFG_CFGR1_FPU_IE_2
#define SYSCFG_CFGR1_FPU_IE_2
Definition: stm32f303xe.h:12510
SYSCFG_CFGR1_FPU_IE_4
#define SYSCFG_CFGR1_FPU_IE_4
Definition: stm32f303xe.h:12512
DBGMCU_IDCODE_REV_ID
#define DBGMCU_IDCODE_REV_ID
Definition: stm32f303xe.h:6766
SYSCFG_CFGR1_FPU_IE_5
#define SYSCFG_CFGR1_FPU_IE_5
Definition: stm32f303xe.h:12513
DBGMCU_CR_TRACE_IOEN
#define DBGMCU_CR_TRACE_IOEN
Definition: stm32f303xe.h:6780
DBGMCU_CR_TRACE_MODE
#define DBGMCU_CR_TRACE_MODE
Definition: stm32f303xe.h:6784
SYSCFG_CFGR1_FPU_IE_0
#define SYSCFG_CFGR1_FPU_IE_0
Definition: stm32f303xe.h:12508
SYSCFG_CFGR1_MEM_MODE
#define SYSCFG_CFGR1_MEM_MODE
Definition: stm32f303xe.h:12442
FLASH_ACR_LATENCY
#define FLASH_ACR_LATENCY
Definition: stm32f303xe.h:8112
SYSCFG_CFGR1_FPU_IE_3
#define SYSCFG_CFGR1_FPU_IE_3
Definition: stm32f303xe.h:12511
DBGMCU_CR_DBG_STOP
#define DBGMCU_CR_DBG_STOP
Definition: stm32f303xe.h:6774
DBGMCU_IDCODE_DEV_ID
#define DBGMCU_IDCODE_DEV_ID
Definition: stm32f303xe.h:6763
SYSCFG
#define SYSCFG
Definition: stm32f303xe.h:951
FLASH
#define FLASH
Definition: stm32f303xe.h:978
DBGMCU
#define DBGMCU
Definition: stm32f303xe.h:962
SYSCFG_BASE
#define SYSCFG_BASE
Definition: stm32f303xe.h:820
stm32f3xx.h
CMSIS STM32F3xx Device Peripheral Access Layer Header File.