25#if defined ( __ICCARM__ )
26 #pragma system_include
27#elif defined (__clang__)
28 #pragma clang system_header
31#ifndef __CORE_SC300_H_GENERIC
32#define __CORE_SC300_H_GENERIC
66#define __SC300_CMSIS_VERSION_MAIN (__CM_CMSIS_VERSION_MAIN)
67#define __SC300_CMSIS_VERSION_SUB (__CM_CMSIS_VERSION_SUB)
68#define __SC300_CMSIS_VERSION ((__SC300_CMSIS_VERSION_MAIN << 16U) | \
69 __SC300_CMSIS_VERSION_SUB )
71#define __CORTEX_SC (300U)
78#if defined ( __CC_ARM )
79 #if defined __TARGET_FPU_VFP
80 #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
83#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
84 #if defined __ARM_PCS_VFP
85 #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
88#elif defined ( __GNUC__ )
89 #if defined (__VFP_FP__) && !defined(__SOFTFP__)
90 #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
93#elif defined ( __ICCARM__ )
94 #if defined __ARMVFP__
95 #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
98#elif defined ( __TI_ARM__ )
99 #if defined __TI_VFP_SUPPORT__
100 #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
103#elif defined ( __TASKING__ )
104 #if defined __FPU_VFP__
105 #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
108#elif defined ( __CSMC__ )
109 #if ( __CSMC__ & 0x400U)
110 #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
124#ifndef __CMSIS_GENERIC
126#ifndef __CORE_SC300_H_DEPENDANT
127#define __CORE_SC300_H_DEPENDANT
134#if defined __CHECK_DEVICE_DEFINES
136 #define __SC300_REV 0x0000U
137 #warning "__SC300_REV not defined in device header file; using default!"
140 #ifndef __MPU_PRESENT
141 #define __MPU_PRESENT 0U
142 #warning "__MPU_PRESENT not defined in device header file; using default!"
145 #ifndef __NVIC_PRIO_BITS
146 #define __NVIC_PRIO_BITS 3U
147 #warning "__NVIC_PRIO_BITS not defined in device header file; using default!"
150 #ifndef __Vendor_SysTickConfig
151 #define __Vendor_SysTickConfig 0U
152 #warning "__Vendor_SysTickConfig not defined in device header file; using default!"
167 #define __I volatile const
173#define __IM volatile const
175#define __IOM volatile
221#define APSR_N_Pos 31U
222#define APSR_N_Msk (1UL << APSR_N_Pos)
224#define APSR_Z_Pos 30U
225#define APSR_Z_Msk (1UL << APSR_Z_Pos)
227#define APSR_C_Pos 29U
228#define APSR_C_Msk (1UL << APSR_C_Pos)
230#define APSR_V_Pos 28U
231#define APSR_V_Msk (1UL << APSR_V_Pos)
233#define APSR_Q_Pos 27U
234#define APSR_Q_Msk (1UL << APSR_Q_Pos)
251#define IPSR_ISR_Pos 0U
252#define IPSR_ISR_Msk (0x1FFUL )
278#define xPSR_N_Pos 31U
279#define xPSR_N_Msk (1UL << xPSR_N_Pos)
281#define xPSR_Z_Pos 30U
282#define xPSR_Z_Msk (1UL << xPSR_Z_Pos)
284#define xPSR_C_Pos 29U
285#define xPSR_C_Msk (1UL << xPSR_C_Pos)
287#define xPSR_V_Pos 28U
288#define xPSR_V_Msk (1UL << xPSR_V_Pos)
290#define xPSR_Q_Pos 27U
291#define xPSR_Q_Msk (1UL << xPSR_Q_Pos)
293#define xPSR_ICI_IT_2_Pos 25U
294#define xPSR_ICI_IT_2_Msk (3UL << xPSR_ICI_IT_2_Pos)
296#define xPSR_T_Pos 24U
297#define xPSR_T_Msk (1UL << xPSR_T_Pos)
299#define xPSR_ICI_IT_1_Pos 10U
300#define xPSR_ICI_IT_1_Msk (0x3FUL << xPSR_ICI_IT_1_Pos)
302#define xPSR_ISR_Pos 0U
303#define xPSR_ISR_Msk (0x1FFUL )
321#define CONTROL_SPSEL_Pos 1U
322#define CONTROL_SPSEL_Msk (1UL << CONTROL_SPSEL_Pos)
324#define CONTROL_nPRIV_Pos 0U
325#define CONTROL_nPRIV_Msk (1UL )
342 __IOM uint32_t ISER[8U];
343 uint32_t RESERVED0[24U];
344 __IOM uint32_t ICER[8U];
345 uint32_t RSERVED1[24U];
346 __IOM uint32_t ISPR[8U];
347 uint32_t RESERVED2[24U];
348 __IOM uint32_t ICPR[8U];
349 uint32_t RESERVED3[24U];
350 __IOM uint32_t IABR[8U];
351 uint32_t RESERVED4[56U];
352 __IOM uint8_t IP[240U];
353 uint32_t RESERVED5[644U];
358#define NVIC_STIR_INTID_Pos 0U
359#define NVIC_STIR_INTID_Msk (0x1FFUL )
379 __IOM uint32_t AIRCR;
382 __IOM uint8_t SHP[12U];
383 __IOM uint32_t SHCSR;
387 __IOM uint32_t MMFAR;
390 __IM uint32_t PFR[2U];
393 __IM uint32_t MMFR[4U];
394 __IM uint32_t ISAR[5U];
395 uint32_t RESERVED0[5U];
396 __IOM uint32_t CPACR;
397 uint32_t RESERVED1[129U];
402#define SCB_CPUID_IMPLEMENTER_Pos 24U
403#define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos)
405#define SCB_CPUID_VARIANT_Pos 20U
406#define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos)
408#define SCB_CPUID_ARCHITECTURE_Pos 16U
409#define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos)
411#define SCB_CPUID_PARTNO_Pos 4U
412#define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos)
414#define SCB_CPUID_REVISION_Pos 0U
415#define SCB_CPUID_REVISION_Msk (0xFUL )
418#define SCB_ICSR_NMIPENDSET_Pos 31U
419#define SCB_ICSR_NMIPENDSET_Msk (1UL << SCB_ICSR_NMIPENDSET_Pos)
421#define SCB_ICSR_PENDSVSET_Pos 28U
422#define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos)
424#define SCB_ICSR_PENDSVCLR_Pos 27U
425#define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos)
427#define SCB_ICSR_PENDSTSET_Pos 26U
428#define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos)
430#define SCB_ICSR_PENDSTCLR_Pos 25U
431#define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos)
433#define SCB_ICSR_ISRPREEMPT_Pos 23U
434#define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos)
436#define SCB_ICSR_ISRPENDING_Pos 22U
437#define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos)
439#define SCB_ICSR_VECTPENDING_Pos 12U
440#define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos)
442#define SCB_ICSR_RETTOBASE_Pos 11U
443#define SCB_ICSR_RETTOBASE_Msk (1UL << SCB_ICSR_RETTOBASE_Pos)
445#define SCB_ICSR_VECTACTIVE_Pos 0U
446#define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL )
449#define SCB_VTOR_TBLBASE_Pos 29U
450#define SCB_VTOR_TBLBASE_Msk (1UL << SCB_VTOR_TBLBASE_Pos)
452#define SCB_VTOR_TBLOFF_Pos 7U
453#define SCB_VTOR_TBLOFF_Msk (0x3FFFFFUL << SCB_VTOR_TBLOFF_Pos)
456#define SCB_AIRCR_VECTKEY_Pos 16U
457#define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos)
459#define SCB_AIRCR_VECTKEYSTAT_Pos 16U
460#define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos)
462#define SCB_AIRCR_ENDIANESS_Pos 15U
463#define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos)
465#define SCB_AIRCR_PRIGROUP_Pos 8U
466#define SCB_AIRCR_PRIGROUP_Msk (7UL << SCB_AIRCR_PRIGROUP_Pos)
468#define SCB_AIRCR_SYSRESETREQ_Pos 2U
469#define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos)
471#define SCB_AIRCR_VECTCLRACTIVE_Pos 1U
472#define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos)
474#define SCB_AIRCR_VECTRESET_Pos 0U
475#define SCB_AIRCR_VECTRESET_Msk (1UL )
478#define SCB_SCR_SEVONPEND_Pos 4U
479#define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos)
481#define SCB_SCR_SLEEPDEEP_Pos 2U
482#define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos)
484#define SCB_SCR_SLEEPONEXIT_Pos 1U
485#define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos)
488#define SCB_CCR_STKALIGN_Pos 9U
489#define SCB_CCR_STKALIGN_Msk (1UL << SCB_CCR_STKALIGN_Pos)
491#define SCB_CCR_BFHFNMIGN_Pos 8U
492#define SCB_CCR_BFHFNMIGN_Msk (1UL << SCB_CCR_BFHFNMIGN_Pos)
494#define SCB_CCR_DIV_0_TRP_Pos 4U
495#define SCB_CCR_DIV_0_TRP_Msk (1UL << SCB_CCR_DIV_0_TRP_Pos)
497#define SCB_CCR_UNALIGN_TRP_Pos 3U
498#define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos)
500#define SCB_CCR_USERSETMPEND_Pos 1U
501#define SCB_CCR_USERSETMPEND_Msk (1UL << SCB_CCR_USERSETMPEND_Pos)
503#define SCB_CCR_NONBASETHRDENA_Pos 0U
504#define SCB_CCR_NONBASETHRDENA_Msk (1UL )
507#define SCB_SHCSR_USGFAULTENA_Pos 18U
508#define SCB_SHCSR_USGFAULTENA_Msk (1UL << SCB_SHCSR_USGFAULTENA_Pos)
510#define SCB_SHCSR_BUSFAULTENA_Pos 17U
511#define SCB_SHCSR_BUSFAULTENA_Msk (1UL << SCB_SHCSR_BUSFAULTENA_Pos)
513#define SCB_SHCSR_MEMFAULTENA_Pos 16U
514#define SCB_SHCSR_MEMFAULTENA_Msk (1UL << SCB_SHCSR_MEMFAULTENA_Pos)
516#define SCB_SHCSR_SVCALLPENDED_Pos 15U
517#define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos)
519#define SCB_SHCSR_BUSFAULTPENDED_Pos 14U
520#define SCB_SHCSR_BUSFAULTPENDED_Msk (1UL << SCB_SHCSR_BUSFAULTPENDED_Pos)
522#define SCB_SHCSR_MEMFAULTPENDED_Pos 13U
523#define SCB_SHCSR_MEMFAULTPENDED_Msk (1UL << SCB_SHCSR_MEMFAULTPENDED_Pos)
525#define SCB_SHCSR_USGFAULTPENDED_Pos 12U
526#define SCB_SHCSR_USGFAULTPENDED_Msk (1UL << SCB_SHCSR_USGFAULTPENDED_Pos)
528#define SCB_SHCSR_SYSTICKACT_Pos 11U
529#define SCB_SHCSR_SYSTICKACT_Msk (1UL << SCB_SHCSR_SYSTICKACT_Pos)
531#define SCB_SHCSR_PENDSVACT_Pos 10U
532#define SCB_SHCSR_PENDSVACT_Msk (1UL << SCB_SHCSR_PENDSVACT_Pos)
534#define SCB_SHCSR_MONITORACT_Pos 8U
535#define SCB_SHCSR_MONITORACT_Msk (1UL << SCB_SHCSR_MONITORACT_Pos)
537#define SCB_SHCSR_SVCALLACT_Pos 7U
538#define SCB_SHCSR_SVCALLACT_Msk (1UL << SCB_SHCSR_SVCALLACT_Pos)
540#define SCB_SHCSR_USGFAULTACT_Pos 3U
541#define SCB_SHCSR_USGFAULTACT_Msk (1UL << SCB_SHCSR_USGFAULTACT_Pos)
543#define SCB_SHCSR_BUSFAULTACT_Pos 1U
544#define SCB_SHCSR_BUSFAULTACT_Msk (1UL << SCB_SHCSR_BUSFAULTACT_Pos)
546#define SCB_SHCSR_MEMFAULTACT_Pos 0U
547#define SCB_SHCSR_MEMFAULTACT_Msk (1UL )
550#define SCB_CFSR_USGFAULTSR_Pos 16U
551#define SCB_CFSR_USGFAULTSR_Msk (0xFFFFUL << SCB_CFSR_USGFAULTSR_Pos)
553#define SCB_CFSR_BUSFAULTSR_Pos 8U
554#define SCB_CFSR_BUSFAULTSR_Msk (0xFFUL << SCB_CFSR_BUSFAULTSR_Pos)
556#define SCB_CFSR_MEMFAULTSR_Pos 0U
557#define SCB_CFSR_MEMFAULTSR_Msk (0xFFUL )
560#define SCB_CFSR_MMARVALID_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 7U)
561#define SCB_CFSR_MMARVALID_Msk (1UL << SCB_CFSR_MMARVALID_Pos)
563#define SCB_CFSR_MSTKERR_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 4U)
564#define SCB_CFSR_MSTKERR_Msk (1UL << SCB_CFSR_MSTKERR_Pos)
566#define SCB_CFSR_MUNSTKERR_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 3U)
567#define SCB_CFSR_MUNSTKERR_Msk (1UL << SCB_CFSR_MUNSTKERR_Pos)
569#define SCB_CFSR_DACCVIOL_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 1U)
570#define SCB_CFSR_DACCVIOL_Msk (1UL << SCB_CFSR_DACCVIOL_Pos)
572#define SCB_CFSR_IACCVIOL_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 0U)
573#define SCB_CFSR_IACCVIOL_Msk (1UL )
576#define SCB_CFSR_BFARVALID_Pos (SCB_CFSR_BUSFAULTSR_Pos + 7U)
577#define SCB_CFSR_BFARVALID_Msk (1UL << SCB_CFSR_BFARVALID_Pos)
579#define SCB_CFSR_STKERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 4U)
580#define SCB_CFSR_STKERR_Msk (1UL << SCB_CFSR_STKERR_Pos)
582#define SCB_CFSR_UNSTKERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 3U)
583#define SCB_CFSR_UNSTKERR_Msk (1UL << SCB_CFSR_UNSTKERR_Pos)
585#define SCB_CFSR_IMPRECISERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 2U)
586#define SCB_CFSR_IMPRECISERR_Msk (1UL << SCB_CFSR_IMPRECISERR_Pos)
588#define SCB_CFSR_PRECISERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 1U)
589#define SCB_CFSR_PRECISERR_Msk (1UL << SCB_CFSR_PRECISERR_Pos)
591#define SCB_CFSR_IBUSERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 0U)
592#define SCB_CFSR_IBUSERR_Msk (1UL << SCB_CFSR_IBUSERR_Pos)
595#define SCB_CFSR_DIVBYZERO_Pos (SCB_CFSR_USGFAULTSR_Pos + 9U)
596#define SCB_CFSR_DIVBYZERO_Msk (1UL << SCB_CFSR_DIVBYZERO_Pos)
598#define SCB_CFSR_UNALIGNED_Pos (SCB_CFSR_USGFAULTSR_Pos + 8U)
599#define SCB_CFSR_UNALIGNED_Msk (1UL << SCB_CFSR_UNALIGNED_Pos)
601#define SCB_CFSR_NOCP_Pos (SCB_CFSR_USGFAULTSR_Pos + 3U)
602#define SCB_CFSR_NOCP_Msk (1UL << SCB_CFSR_NOCP_Pos)
604#define SCB_CFSR_INVPC_Pos (SCB_CFSR_USGFAULTSR_Pos + 2U)
605#define SCB_CFSR_INVPC_Msk (1UL << SCB_CFSR_INVPC_Pos)
607#define SCB_CFSR_INVSTATE_Pos (SCB_CFSR_USGFAULTSR_Pos + 1U)
608#define SCB_CFSR_INVSTATE_Msk (1UL << SCB_CFSR_INVSTATE_Pos)
610#define SCB_CFSR_UNDEFINSTR_Pos (SCB_CFSR_USGFAULTSR_Pos + 0U)
611#define SCB_CFSR_UNDEFINSTR_Msk (1UL << SCB_CFSR_UNDEFINSTR_Pos)
614#define SCB_HFSR_DEBUGEVT_Pos 31U
615#define SCB_HFSR_DEBUGEVT_Msk (1UL << SCB_HFSR_DEBUGEVT_Pos)
617#define SCB_HFSR_FORCED_Pos 30U
618#define SCB_HFSR_FORCED_Msk (1UL << SCB_HFSR_FORCED_Pos)
620#define SCB_HFSR_VECTTBL_Pos 1U
621#define SCB_HFSR_VECTTBL_Msk (1UL << SCB_HFSR_VECTTBL_Pos)
624#define SCB_DFSR_EXTERNAL_Pos 4U
625#define SCB_DFSR_EXTERNAL_Msk (1UL << SCB_DFSR_EXTERNAL_Pos)
627#define SCB_DFSR_VCATCH_Pos 3U
628#define SCB_DFSR_VCATCH_Msk (1UL << SCB_DFSR_VCATCH_Pos)
630#define SCB_DFSR_DWTTRAP_Pos 2U
631#define SCB_DFSR_DWTTRAP_Msk (1UL << SCB_DFSR_DWTTRAP_Pos)
633#define SCB_DFSR_BKPT_Pos 1U
634#define SCB_DFSR_BKPT_Msk (1UL << SCB_DFSR_BKPT_Pos)
636#define SCB_DFSR_HALTED_Pos 0U
637#define SCB_DFSR_HALTED_Msk (1UL )
654 uint32_t RESERVED0[1U];
656 uint32_t RESERVED1[1U];
660#define SCnSCB_ICTR_INTLINESNUM_Pos 0U
661#define SCnSCB_ICTR_INTLINESNUM_Msk (0xFUL )
685#define SysTick_CTRL_COUNTFLAG_Pos 16U
686#define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos)
688#define SysTick_CTRL_CLKSOURCE_Pos 2U
689#define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos)
691#define SysTick_CTRL_TICKINT_Pos 1U
692#define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos)
694#define SysTick_CTRL_ENABLE_Pos 0U
695#define SysTick_CTRL_ENABLE_Msk (1UL )
698#define SysTick_LOAD_RELOAD_Pos 0U
699#define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL )
702#define SysTick_VAL_CURRENT_Pos 0U
703#define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL )
706#define SysTick_CALIB_NOREF_Pos 31U
707#define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos)
709#define SysTick_CALIB_SKEW_Pos 30U
710#define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos)
712#define SysTick_CALIB_TENMS_Pos 0U
713#define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL )
736 uint32_t RESERVED0[864U];
738 uint32_t RESERVED1[15U];
740 uint32_t RESERVED2[15U];
742 uint32_t RESERVED3[29U];
746 uint32_t RESERVED4[43U];
749 uint32_t RESERVED5[6U];
765#define ITM_TPR_PRIVMASK_Pos 0U
766#define ITM_TPR_PRIVMASK_Msk (0xFUL )
769#define ITM_TCR_BUSY_Pos 23U
770#define ITM_TCR_BUSY_Msk (1UL << ITM_TCR_BUSY_Pos)
772#define ITM_TCR_TraceBusID_Pos 16U
773#define ITM_TCR_TraceBusID_Msk (0x7FUL << ITM_TCR_TraceBusID_Pos)
775#define ITM_TCR_GTSFREQ_Pos 10U
776#define ITM_TCR_GTSFREQ_Msk (3UL << ITM_TCR_GTSFREQ_Pos)
778#define ITM_TCR_TSPrescale_Pos 8U
779#define ITM_TCR_TSPrescale_Msk (3UL << ITM_TCR_TSPrescale_Pos)
781#define ITM_TCR_SWOENA_Pos 4U
782#define ITM_TCR_SWOENA_Msk (1UL << ITM_TCR_SWOENA_Pos)
784#define ITM_TCR_DWTENA_Pos 3U
785#define ITM_TCR_DWTENA_Msk (1UL << ITM_TCR_DWTENA_Pos)
787#define ITM_TCR_SYNCENA_Pos 2U
788#define ITM_TCR_SYNCENA_Msk (1UL << ITM_TCR_SYNCENA_Pos)
790#define ITM_TCR_TSENA_Pos 1U
791#define ITM_TCR_TSENA_Msk (1UL << ITM_TCR_TSENA_Pos)
793#define ITM_TCR_ITMENA_Pos 0U
794#define ITM_TCR_ITMENA_Msk (1UL )
797#define ITM_IWR_ATVALIDM_Pos 0U
798#define ITM_IWR_ATVALIDM_Msk (1UL )
801#define ITM_IRR_ATREADYM_Pos 0U
802#define ITM_IRR_ATREADYM_Msk (1UL )
805#define ITM_IMCR_INTEGRATION_Pos 0U
806#define ITM_IMCR_INTEGRATION_Msk (1UL )
809#define ITM_LSR_ByteAcc_Pos 2U
810#define ITM_LSR_ByteAcc_Msk (1UL << ITM_LSR_ByteAcc_Pos)
812#define ITM_LSR_Access_Pos 1U
813#define ITM_LSR_Access_Msk (1UL << ITM_LSR_Access_Pos)
815#define ITM_LSR_Present_Pos 0U
816#define ITM_LSR_Present_Msk (1UL )
834 __IOM uint32_t CYCCNT;
835 __IOM uint32_t CPICNT;
836 __IOM uint32_t EXCCNT;
837 __IOM uint32_t SLEEPCNT;
838 __IOM uint32_t LSUCNT;
839 __IOM uint32_t FOLDCNT;
841 __IOM uint32_t COMP0;
842 __IOM uint32_t MASK0;
843 __IOM uint32_t FUNCTION0;
844 uint32_t RESERVED0[1U];
846 __IOM uint32_t MASK1;
847 __IOM uint32_t FUNCTION1;
848 uint32_t RESERVED1[1U];
850 __IOM uint32_t MASK2;
851 __IOM uint32_t FUNCTION2;
852 uint32_t RESERVED2[1U];
854 __IOM uint32_t MASK3;
855 __IOM uint32_t FUNCTION3;
859#define DWT_CTRL_NUMCOMP_Pos 28U
860#define DWT_CTRL_NUMCOMP_Msk (0xFUL << DWT_CTRL_NUMCOMP_Pos)
862#define DWT_CTRL_NOTRCPKT_Pos 27U
863#define DWT_CTRL_NOTRCPKT_Msk (0x1UL << DWT_CTRL_NOTRCPKT_Pos)
865#define DWT_CTRL_NOEXTTRIG_Pos 26U
866#define DWT_CTRL_NOEXTTRIG_Msk (0x1UL << DWT_CTRL_NOEXTTRIG_Pos)
868#define DWT_CTRL_NOCYCCNT_Pos 25U
869#define DWT_CTRL_NOCYCCNT_Msk (0x1UL << DWT_CTRL_NOCYCCNT_Pos)
871#define DWT_CTRL_NOPRFCNT_Pos 24U
872#define DWT_CTRL_NOPRFCNT_Msk (0x1UL << DWT_CTRL_NOPRFCNT_Pos)
874#define DWT_CTRL_CYCEVTENA_Pos 22U
875#define DWT_CTRL_CYCEVTENA_Msk (0x1UL << DWT_CTRL_CYCEVTENA_Pos)
877#define DWT_CTRL_FOLDEVTENA_Pos 21U
878#define DWT_CTRL_FOLDEVTENA_Msk (0x1UL << DWT_CTRL_FOLDEVTENA_Pos)
880#define DWT_CTRL_LSUEVTENA_Pos 20U
881#define DWT_CTRL_LSUEVTENA_Msk (0x1UL << DWT_CTRL_LSUEVTENA_Pos)
883#define DWT_CTRL_SLEEPEVTENA_Pos 19U
884#define DWT_CTRL_SLEEPEVTENA_Msk (0x1UL << DWT_CTRL_SLEEPEVTENA_Pos)
886#define DWT_CTRL_EXCEVTENA_Pos 18U
887#define DWT_CTRL_EXCEVTENA_Msk (0x1UL << DWT_CTRL_EXCEVTENA_Pos)
889#define DWT_CTRL_CPIEVTENA_Pos 17U
890#define DWT_CTRL_CPIEVTENA_Msk (0x1UL << DWT_CTRL_CPIEVTENA_Pos)
892#define DWT_CTRL_EXCTRCENA_Pos 16U
893#define DWT_CTRL_EXCTRCENA_Msk (0x1UL << DWT_CTRL_EXCTRCENA_Pos)
895#define DWT_CTRL_PCSAMPLENA_Pos 12U
896#define DWT_CTRL_PCSAMPLENA_Msk (0x1UL << DWT_CTRL_PCSAMPLENA_Pos)
898#define DWT_CTRL_SYNCTAP_Pos 10U
899#define DWT_CTRL_SYNCTAP_Msk (0x3UL << DWT_CTRL_SYNCTAP_Pos)
901#define DWT_CTRL_CYCTAP_Pos 9U
902#define DWT_CTRL_CYCTAP_Msk (0x1UL << DWT_CTRL_CYCTAP_Pos)
904#define DWT_CTRL_POSTINIT_Pos 5U
905#define DWT_CTRL_POSTINIT_Msk (0xFUL << DWT_CTRL_POSTINIT_Pos)
907#define DWT_CTRL_POSTPRESET_Pos 1U
908#define DWT_CTRL_POSTPRESET_Msk (0xFUL << DWT_CTRL_POSTPRESET_Pos)
910#define DWT_CTRL_CYCCNTENA_Pos 0U
911#define DWT_CTRL_CYCCNTENA_Msk (0x1UL )
914#define DWT_CPICNT_CPICNT_Pos 0U
915#define DWT_CPICNT_CPICNT_Msk (0xFFUL )
918#define DWT_EXCCNT_EXCCNT_Pos 0U
919#define DWT_EXCCNT_EXCCNT_Msk (0xFFUL )
922#define DWT_SLEEPCNT_SLEEPCNT_Pos 0U
923#define DWT_SLEEPCNT_SLEEPCNT_Msk (0xFFUL )
926#define DWT_LSUCNT_LSUCNT_Pos 0U
927#define DWT_LSUCNT_LSUCNT_Msk (0xFFUL )
930#define DWT_FOLDCNT_FOLDCNT_Pos 0U
931#define DWT_FOLDCNT_FOLDCNT_Msk (0xFFUL )
934#define DWT_MASK_MASK_Pos 0U
935#define DWT_MASK_MASK_Msk (0x1FUL )
938#define DWT_FUNCTION_MATCHED_Pos 24U
939#define DWT_FUNCTION_MATCHED_Msk (0x1UL << DWT_FUNCTION_MATCHED_Pos)
941#define DWT_FUNCTION_DATAVADDR1_Pos 16U
942#define DWT_FUNCTION_DATAVADDR1_Msk (0xFUL << DWT_FUNCTION_DATAVADDR1_Pos)
944#define DWT_FUNCTION_DATAVADDR0_Pos 12U
945#define DWT_FUNCTION_DATAVADDR0_Msk (0xFUL << DWT_FUNCTION_DATAVADDR0_Pos)
947#define DWT_FUNCTION_DATAVSIZE_Pos 10U
948#define DWT_FUNCTION_DATAVSIZE_Msk (0x3UL << DWT_FUNCTION_DATAVSIZE_Pos)
950#define DWT_FUNCTION_LNK1ENA_Pos 9U
951#define DWT_FUNCTION_LNK1ENA_Msk (0x1UL << DWT_FUNCTION_LNK1ENA_Pos)
953#define DWT_FUNCTION_DATAVMATCH_Pos 8U
954#define DWT_FUNCTION_DATAVMATCH_Msk (0x1UL << DWT_FUNCTION_DATAVMATCH_Pos)
956#define DWT_FUNCTION_CYCMATCH_Pos 7U
957#define DWT_FUNCTION_CYCMATCH_Msk (0x1UL << DWT_FUNCTION_CYCMATCH_Pos)
959#define DWT_FUNCTION_EMITRANGE_Pos 5U
960#define DWT_FUNCTION_EMITRANGE_Msk (0x1UL << DWT_FUNCTION_EMITRANGE_Pos)
962#define DWT_FUNCTION_FUNCTION_Pos 0U
963#define DWT_FUNCTION_FUNCTION_Msk (0xFUL )
981 __IOM uint32_t CSPSR;
982 uint32_t RESERVED0[2U];
984 uint32_t RESERVED1[55U];
986 uint32_t RESERVED2[131U];
990 uint32_t RESERVED3[759U];
991 __IM uint32_t TRIGGER;
993 __IM uint32_t ITATBCTR2;
994 uint32_t RESERVED4[1U];
995 __IM uint32_t ITATBCTR0;
997 __IOM uint32_t ITCTRL;
998 uint32_t RESERVED5[39U];
999 __IOM uint32_t CLAIMSET;
1000 __IOM uint32_t CLAIMCLR;
1001 uint32_t RESERVED7[8U];
1002 __IM uint32_t DEVID;
1003 __IM uint32_t DEVTYPE;
1007#define TPI_ACPR_PRESCALER_Pos 0U
1008#define TPI_ACPR_PRESCALER_Msk (0x1FFFUL )
1011#define TPI_SPPR_TXMODE_Pos 0U
1012#define TPI_SPPR_TXMODE_Msk (0x3UL )
1015#define TPI_FFSR_FtNonStop_Pos 3U
1016#define TPI_FFSR_FtNonStop_Msk (0x1UL << TPI_FFSR_FtNonStop_Pos)
1018#define TPI_FFSR_TCPresent_Pos 2U
1019#define TPI_FFSR_TCPresent_Msk (0x1UL << TPI_FFSR_TCPresent_Pos)
1021#define TPI_FFSR_FtStopped_Pos 1U
1022#define TPI_FFSR_FtStopped_Msk (0x1UL << TPI_FFSR_FtStopped_Pos)
1024#define TPI_FFSR_FlInProg_Pos 0U
1025#define TPI_FFSR_FlInProg_Msk (0x1UL )
1028#define TPI_FFCR_TrigIn_Pos 8U
1029#define TPI_FFCR_TrigIn_Msk (0x1UL << TPI_FFCR_TrigIn_Pos)
1031#define TPI_FFCR_EnFCont_Pos 1U
1032#define TPI_FFCR_EnFCont_Msk (0x1UL << TPI_FFCR_EnFCont_Pos)
1035#define TPI_TRIGGER_TRIGGER_Pos 0U
1036#define TPI_TRIGGER_TRIGGER_Msk (0x1UL )
1039#define TPI_FIFO0_ITM_ATVALID_Pos 29U
1040#define TPI_FIFO0_ITM_ATVALID_Msk (0x3UL << TPI_FIFO0_ITM_ATVALID_Pos)
1042#define TPI_FIFO0_ITM_bytecount_Pos 27U
1043#define TPI_FIFO0_ITM_bytecount_Msk (0x3UL << TPI_FIFO0_ITM_bytecount_Pos)
1045#define TPI_FIFO0_ETM_ATVALID_Pos 26U
1046#define TPI_FIFO0_ETM_ATVALID_Msk (0x3UL << TPI_FIFO0_ETM_ATVALID_Pos)
1048#define TPI_FIFO0_ETM_bytecount_Pos 24U
1049#define TPI_FIFO0_ETM_bytecount_Msk (0x3UL << TPI_FIFO0_ETM_bytecount_Pos)
1051#define TPI_FIFO0_ETM2_Pos 16U
1052#define TPI_FIFO0_ETM2_Msk (0xFFUL << TPI_FIFO0_ETM2_Pos)
1054#define TPI_FIFO0_ETM1_Pos 8U
1055#define TPI_FIFO0_ETM1_Msk (0xFFUL << TPI_FIFO0_ETM1_Pos)
1057#define TPI_FIFO0_ETM0_Pos 0U
1058#define TPI_FIFO0_ETM0_Msk (0xFFUL )
1061#define TPI_ITATBCTR2_ATREADY2_Pos 0U
1062#define TPI_ITATBCTR2_ATREADY2_Msk (0x1UL )
1064#define TPI_ITATBCTR2_ATREADY1_Pos 0U
1065#define TPI_ITATBCTR2_ATREADY1_Msk (0x1UL )
1068#define TPI_FIFO1_ITM_ATVALID_Pos 29U
1069#define TPI_FIFO1_ITM_ATVALID_Msk (0x3UL << TPI_FIFO1_ITM_ATVALID_Pos)
1071#define TPI_FIFO1_ITM_bytecount_Pos 27U
1072#define TPI_FIFO1_ITM_bytecount_Msk (0x3UL << TPI_FIFO1_ITM_bytecount_Pos)
1074#define TPI_FIFO1_ETM_ATVALID_Pos 26U
1075#define TPI_FIFO1_ETM_ATVALID_Msk (0x3UL << TPI_FIFO1_ETM_ATVALID_Pos)
1077#define TPI_FIFO1_ETM_bytecount_Pos 24U
1078#define TPI_FIFO1_ETM_bytecount_Msk (0x3UL << TPI_FIFO1_ETM_bytecount_Pos)
1080#define TPI_FIFO1_ITM2_Pos 16U
1081#define TPI_FIFO1_ITM2_Msk (0xFFUL << TPI_FIFO1_ITM2_Pos)
1083#define TPI_FIFO1_ITM1_Pos 8U
1084#define TPI_FIFO1_ITM1_Msk (0xFFUL << TPI_FIFO1_ITM1_Pos)
1086#define TPI_FIFO1_ITM0_Pos 0U
1087#define TPI_FIFO1_ITM0_Msk (0xFFUL )
1090#define TPI_ITATBCTR0_ATREADY2_Pos 0U
1091#define TPI_ITATBCTR0_ATREADY2_Msk (0x1UL )
1093#define TPI_ITATBCTR0_ATREADY1_Pos 0U
1094#define TPI_ITATBCTR0_ATREADY1_Msk (0x1UL )
1097#define TPI_ITCTRL_Mode_Pos 0U
1098#define TPI_ITCTRL_Mode_Msk (0x3UL )
1101#define TPI_DEVID_NRZVALID_Pos 11U
1102#define TPI_DEVID_NRZVALID_Msk (0x1UL << TPI_DEVID_NRZVALID_Pos)
1104#define TPI_DEVID_MANCVALID_Pos 10U
1105#define TPI_DEVID_MANCVALID_Msk (0x1UL << TPI_DEVID_MANCVALID_Pos)
1107#define TPI_DEVID_PTINVALID_Pos 9U
1108#define TPI_DEVID_PTINVALID_Msk (0x1UL << TPI_DEVID_PTINVALID_Pos)
1110#define TPI_DEVID_MinBufSz_Pos 6U
1111#define TPI_DEVID_MinBufSz_Msk (0x7UL << TPI_DEVID_MinBufSz_Pos)
1113#define TPI_DEVID_AsynClkIn_Pos 5U
1114#define TPI_DEVID_AsynClkIn_Msk (0x1UL << TPI_DEVID_AsynClkIn_Pos)
1116#define TPI_DEVID_NrTraceInput_Pos 0U
1117#define TPI_DEVID_NrTraceInput_Msk (0x1FUL )
1120#define TPI_DEVTYPE_SubType_Pos 4U
1121#define TPI_DEVTYPE_SubType_Msk (0xFUL )
1123#define TPI_DEVTYPE_MajorType_Pos 0U
1124#define TPI_DEVTYPE_MajorType_Msk (0xFUL << TPI_DEVTYPE_MajorType_Pos)
1129#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U)
1143 __IOM uint32_t CTRL;
1145 __IOM uint32_t RBAR;
1146 __IOM uint32_t RASR;
1147 __IOM uint32_t RBAR_A1;
1148 __IOM uint32_t RASR_A1;
1149 __IOM uint32_t RBAR_A2;
1150 __IOM uint32_t RASR_A2;
1151 __IOM uint32_t RBAR_A3;
1152 __IOM uint32_t RASR_A3;
1156#define MPU_TYPE_IREGION_Pos 16U
1157#define MPU_TYPE_IREGION_Msk (0xFFUL << MPU_TYPE_IREGION_Pos)
1159#define MPU_TYPE_DREGION_Pos 8U
1160#define MPU_TYPE_DREGION_Msk (0xFFUL << MPU_TYPE_DREGION_Pos)
1162#define MPU_TYPE_SEPARATE_Pos 0U
1163#define MPU_TYPE_SEPARATE_Msk (1UL )
1166#define MPU_CTRL_PRIVDEFENA_Pos 2U
1167#define MPU_CTRL_PRIVDEFENA_Msk (1UL << MPU_CTRL_PRIVDEFENA_Pos)
1169#define MPU_CTRL_HFNMIENA_Pos 1U
1170#define MPU_CTRL_HFNMIENA_Msk (1UL << MPU_CTRL_HFNMIENA_Pos)
1172#define MPU_CTRL_ENABLE_Pos 0U
1173#define MPU_CTRL_ENABLE_Msk (1UL )
1176#define MPU_RNR_REGION_Pos 0U
1177#define MPU_RNR_REGION_Msk (0xFFUL )
1180#define MPU_RBAR_ADDR_Pos 5U
1181#define MPU_RBAR_ADDR_Msk (0x7FFFFFFUL << MPU_RBAR_ADDR_Pos)
1183#define MPU_RBAR_VALID_Pos 4U
1184#define MPU_RBAR_VALID_Msk (1UL << MPU_RBAR_VALID_Pos)
1186#define MPU_RBAR_REGION_Pos 0U
1187#define MPU_RBAR_REGION_Msk (0xFUL )
1190#define MPU_RASR_ATTRS_Pos 16U
1191#define MPU_RASR_ATTRS_Msk (0xFFFFUL << MPU_RASR_ATTRS_Pos)
1193#define MPU_RASR_XN_Pos 28U
1194#define MPU_RASR_XN_Msk (1UL << MPU_RASR_XN_Pos)
1196#define MPU_RASR_AP_Pos 24U
1197#define MPU_RASR_AP_Msk (0x7UL << MPU_RASR_AP_Pos)
1199#define MPU_RASR_TEX_Pos 19U
1200#define MPU_RASR_TEX_Msk (0x7UL << MPU_RASR_TEX_Pos)
1202#define MPU_RASR_S_Pos 18U
1203#define MPU_RASR_S_Msk (1UL << MPU_RASR_S_Pos)
1205#define MPU_RASR_C_Pos 17U
1206#define MPU_RASR_C_Msk (1UL << MPU_RASR_C_Pos)
1208#define MPU_RASR_B_Pos 16U
1209#define MPU_RASR_B_Msk (1UL << MPU_RASR_B_Pos)
1211#define MPU_RASR_SRD_Pos 8U
1212#define MPU_RASR_SRD_Msk (0xFFUL << MPU_RASR_SRD_Pos)
1214#define MPU_RASR_SIZE_Pos 1U
1215#define MPU_RASR_SIZE_Msk (0x1FUL << MPU_RASR_SIZE_Pos)
1217#define MPU_RASR_ENABLE_Pos 0U
1218#define MPU_RASR_ENABLE_Msk (1UL )
1236 __IOM uint32_t DHCSR;
1237 __OM uint32_t DCRSR;
1238 __IOM uint32_t DCRDR;
1239 __IOM uint32_t DEMCR;
1243#define CoreDebug_DHCSR_DBGKEY_Pos 16U
1244#define CoreDebug_DHCSR_DBGKEY_Msk (0xFFFFUL << CoreDebug_DHCSR_DBGKEY_Pos)
1246#define CoreDebug_DHCSR_S_RESET_ST_Pos 25U
1247#define CoreDebug_DHCSR_S_RESET_ST_Msk (1UL << CoreDebug_DHCSR_S_RESET_ST_Pos)
1249#define CoreDebug_DHCSR_S_RETIRE_ST_Pos 24U
1250#define CoreDebug_DHCSR_S_RETIRE_ST_Msk (1UL << CoreDebug_DHCSR_S_RETIRE_ST_Pos)
1252#define CoreDebug_DHCSR_S_LOCKUP_Pos 19U
1253#define CoreDebug_DHCSR_S_LOCKUP_Msk (1UL << CoreDebug_DHCSR_S_LOCKUP_Pos)
1255#define CoreDebug_DHCSR_S_SLEEP_Pos 18U
1256#define CoreDebug_DHCSR_S_SLEEP_Msk (1UL << CoreDebug_DHCSR_S_SLEEP_Pos)
1258#define CoreDebug_DHCSR_S_HALT_Pos 17U
1259#define CoreDebug_DHCSR_S_HALT_Msk (1UL << CoreDebug_DHCSR_S_HALT_Pos)
1261#define CoreDebug_DHCSR_S_REGRDY_Pos 16U
1262#define CoreDebug_DHCSR_S_REGRDY_Msk (1UL << CoreDebug_DHCSR_S_REGRDY_Pos)
1264#define CoreDebug_DHCSR_C_SNAPSTALL_Pos 5U
1265#define CoreDebug_DHCSR_C_SNAPSTALL_Msk (1UL << CoreDebug_DHCSR_C_SNAPSTALL_Pos)
1267#define CoreDebug_DHCSR_C_MASKINTS_Pos 3U
1268#define CoreDebug_DHCSR_C_MASKINTS_Msk (1UL << CoreDebug_DHCSR_C_MASKINTS_Pos)
1270#define CoreDebug_DHCSR_C_STEP_Pos 2U
1271#define CoreDebug_DHCSR_C_STEP_Msk (1UL << CoreDebug_DHCSR_C_STEP_Pos)
1273#define CoreDebug_DHCSR_C_HALT_Pos 1U
1274#define CoreDebug_DHCSR_C_HALT_Msk (1UL << CoreDebug_DHCSR_C_HALT_Pos)
1276#define CoreDebug_DHCSR_C_DEBUGEN_Pos 0U
1277#define CoreDebug_DHCSR_C_DEBUGEN_Msk (1UL )
1280#define CoreDebug_DCRSR_REGWnR_Pos 16U
1281#define CoreDebug_DCRSR_REGWnR_Msk (1UL << CoreDebug_DCRSR_REGWnR_Pos)
1283#define CoreDebug_DCRSR_REGSEL_Pos 0U
1284#define CoreDebug_DCRSR_REGSEL_Msk (0x1FUL )
1287#define CoreDebug_DEMCR_TRCENA_Pos 24U
1288#define CoreDebug_DEMCR_TRCENA_Msk (1UL << CoreDebug_DEMCR_TRCENA_Pos)
1290#define CoreDebug_DEMCR_MON_REQ_Pos 19U
1291#define CoreDebug_DEMCR_MON_REQ_Msk (1UL << CoreDebug_DEMCR_MON_REQ_Pos)
1293#define CoreDebug_DEMCR_MON_STEP_Pos 18U
1294#define CoreDebug_DEMCR_MON_STEP_Msk (1UL << CoreDebug_DEMCR_MON_STEP_Pos)
1296#define CoreDebug_DEMCR_MON_PEND_Pos 17U
1297#define CoreDebug_DEMCR_MON_PEND_Msk (1UL << CoreDebug_DEMCR_MON_PEND_Pos)
1299#define CoreDebug_DEMCR_MON_EN_Pos 16U
1300#define CoreDebug_DEMCR_MON_EN_Msk (1UL << CoreDebug_DEMCR_MON_EN_Pos)
1302#define CoreDebug_DEMCR_VC_HARDERR_Pos 10U
1303#define CoreDebug_DEMCR_VC_HARDERR_Msk (1UL << CoreDebug_DEMCR_VC_HARDERR_Pos)
1305#define CoreDebug_DEMCR_VC_INTERR_Pos 9U
1306#define CoreDebug_DEMCR_VC_INTERR_Msk (1UL << CoreDebug_DEMCR_VC_INTERR_Pos)
1308#define CoreDebug_DEMCR_VC_BUSERR_Pos 8U
1309#define CoreDebug_DEMCR_VC_BUSERR_Msk (1UL << CoreDebug_DEMCR_VC_BUSERR_Pos)
1311#define CoreDebug_DEMCR_VC_STATERR_Pos 7U
1312#define CoreDebug_DEMCR_VC_STATERR_Msk (1UL << CoreDebug_DEMCR_VC_STATERR_Pos)
1314#define CoreDebug_DEMCR_VC_CHKERR_Pos 6U
1315#define CoreDebug_DEMCR_VC_CHKERR_Msk (1UL << CoreDebug_DEMCR_VC_CHKERR_Pos)
1317#define CoreDebug_DEMCR_VC_NOCPERR_Pos 5U
1318#define CoreDebug_DEMCR_VC_NOCPERR_Msk (1UL << CoreDebug_DEMCR_VC_NOCPERR_Pos)
1320#define CoreDebug_DEMCR_VC_MMERR_Pos 4U
1321#define CoreDebug_DEMCR_VC_MMERR_Msk (1UL << CoreDebug_DEMCR_VC_MMERR_Pos)
1323#define CoreDebug_DEMCR_VC_CORERESET_Pos 0U
1324#define CoreDebug_DEMCR_VC_CORERESET_Msk (1UL )
1342#define _VAL2FLD(field, value) (((uint32_t)(value) << field ## _Pos) & field ## _Msk)
1350#define _FLD2VAL(field, value) (((uint32_t)(value) & field ## _Msk) >> field ## _Pos)
1363#define SCS_BASE (0xE000E000UL)
1364#define ITM_BASE (0xE0000000UL)
1365#define DWT_BASE (0xE0001000UL)
1366#define TPI_BASE (0xE0040000UL)
1367#define CoreDebug_BASE (0xE000EDF0UL)
1368#define SysTick_BASE (SCS_BASE + 0x0010UL)
1369#define NVIC_BASE (SCS_BASE + 0x0100UL)
1370#define SCB_BASE (SCS_BASE + 0x0D00UL)
1372#define SCnSCB ((SCnSCB_Type *) SCS_BASE )
1373#define SCB ((SCB_Type *) SCB_BASE )
1374#define SysTick ((SysTick_Type *) SysTick_BASE )
1375#define NVIC ((NVIC_Type *) NVIC_BASE )
1376#define ITM ((ITM_Type *) ITM_BASE )
1377#define DWT ((DWT_Type *) DWT_BASE )
1378#define TPI ((TPI_Type *) TPI_BASE )
1379#define CoreDebug ((CoreDebug_Type *) CoreDebug_BASE)
1381#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U)
1382 #define MPU_BASE (SCS_BASE + 0x0D90UL)
1383 #define MPU ((MPU_Type *) MPU_BASE )
1412#ifdef CMSIS_NVIC_VIRTUAL
1413 #ifndef CMSIS_NVIC_VIRTUAL_HEADER_FILE
1414 #define CMSIS_NVIC_VIRTUAL_HEADER_FILE "cmsis_nvic_virtual.h"
1416 #include CMSIS_NVIC_VIRTUAL_HEADER_FILE
1418 #define NVIC_SetPriorityGrouping __NVIC_SetPriorityGrouping
1419 #define NVIC_GetPriorityGrouping __NVIC_GetPriorityGrouping
1420 #define NVIC_EnableIRQ __NVIC_EnableIRQ
1421 #define NVIC_GetEnableIRQ __NVIC_GetEnableIRQ
1422 #define NVIC_DisableIRQ __NVIC_DisableIRQ
1423 #define NVIC_GetPendingIRQ __NVIC_GetPendingIRQ
1424 #define NVIC_SetPendingIRQ __NVIC_SetPendingIRQ
1425 #define NVIC_ClearPendingIRQ __NVIC_ClearPendingIRQ
1426 #define NVIC_GetActive __NVIC_GetActive
1427 #define NVIC_SetPriority __NVIC_SetPriority
1428 #define NVIC_GetPriority __NVIC_GetPriority
1429 #define NVIC_SystemReset __NVIC_SystemReset
1432#ifdef CMSIS_VECTAB_VIRTUAL
1433 #ifndef CMSIS_VECTAB_VIRTUAL_HEADER_FILE
1434 #define CMSIS_VECTAB_VIRTUAL_HEADER_FILE "cmsis_vectab_virtual.h"
1436 #include CMSIS_VECTAB_VIRTUAL_HEADER_FILE
1438 #define NVIC_SetVector __NVIC_SetVector
1439 #define NVIC_GetVector __NVIC_GetVector
1442#define NVIC_USER_IRQ_OFFSET 16
1446#define EXC_RETURN_HANDLER (0xFFFFFFF1UL)
1447#define EXC_RETURN_THREAD_MSP (0xFFFFFFF9UL)
1448#define EXC_RETURN_THREAD_PSP (0xFFFFFFFDUL)
1464 uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL);
1466 reg_value =
SCB->AIRCR;
1468 reg_value = (reg_value |
1470 (PriorityGroupTmp << 8U) );
1471 SCB->AIRCR = reg_value;
1494 if ((int32_t)(IRQn) >= 0)
1496 NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
1511 if ((int32_t)(IRQn) >= 0)
1513 return((uint32_t)(((
NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
1530 if ((int32_t)(IRQn) >= 0)
1532 NVIC->ICER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
1549 if ((int32_t)(IRQn) >= 0)
1551 return((uint32_t)(((
NVIC->ISPR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
1568 if ((int32_t)(IRQn) >= 0)
1570 NVIC->ISPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
1583 if ((int32_t)(IRQn) >= 0)
1585 NVIC->ICPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
1600 if ((int32_t)(IRQn) >= 0)
1602 return((uint32_t)(((
NVIC->IABR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
1622 if ((int32_t)(IRQn) >= 0)
1624 NVIC->IP[((uint32_t)IRQn)] = (uint8_t)((priority << (8U -
__NVIC_PRIO_BITS)) & (uint32_t)0xFFUL);
1628 SCB->SHP[(((uint32_t)IRQn) & 0xFUL)-4UL] = (uint8_t)((priority << (8U -
__NVIC_PRIO_BITS)) & (uint32_t)0xFFUL);
1645 if ((int32_t)(IRQn) >= 0)
1669 uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL);
1670 uint32_t PreemptPriorityBits;
1671 uint32_t SubPriorityBits;
1674 SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(
__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(
__NVIC_PRIO_BITS));
1677 ((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits) |
1678 ((SubPriority & (uint32_t)((1UL << (SubPriorityBits )) - 1UL)))
1696 uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL);
1697 uint32_t PreemptPriorityBits;
1698 uint32_t SubPriorityBits;
1701 SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(
__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(
__NVIC_PRIO_BITS));
1703 *pPreemptPriority = (Priority >> SubPriorityBits) & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL);
1704 *pSubPriority = (Priority ) & (uint32_t)((1UL << (SubPriorityBits )) - 1UL);
1719 uint32_t *vectors = (uint32_t *)
SCB->VTOR;
1734 uint32_t *vectors = (uint32_t *)
SCB->VTOR;
1795#if defined (__Vendor_SysTickConfig) && (__Vendor_SysTickConfig == 0U)
1815 SysTick->LOAD = (uint32_t)(ticks - 1UL);
1839#define ITM_RXBUFFER_EMPTY ((int32_t)0x5AA55AA5U)
1853 ((
ITM->TER & 1UL ) != 0UL) )
1855 while (
ITM->PORT[0U].u32 == 0UL)
1859 ITM->PORT[0U].u8 = (uint8_t)ch;
#define __NO_RETURN
Definition: cmsis_armcc.h:65
#define __STATIC_INLINE
Definition: cmsis_armcc.h:59
CMSIS compiler generic header file.
CMSIS Core(M) Version definitions.
#define __OM
Definition: core_sc300.h:174
#define __IM
Definition: core_sc300.h:173
#define __IOM
Definition: core_sc300.h:175
#define __DSB()
Data Synchronization Barrier.
Definition: cmsis_armcc.h:429
#define __ISB()
Instruction Synchronization Barrier.
Definition: cmsis_armcc.h:418
#define __NOP
No Operation.
Definition: cmsis_armcc.h:387
__NO_RETURN __STATIC_INLINE void __NVIC_SystemReset(void)
System Reset.
Definition: core_armv8mbl.h:1581
__STATIC_INLINE void __NVIC_SetVector(IRQn_Type IRQn, uint32_t vector)
Set Interrupt Vector.
Definition: core_armv8mbl.h:1547
__STATIC_INLINE void NVIC_DecodePriority(uint32_t Priority, uint32_t PriorityGroup, uint32_t *const pPreemptPriority, uint32_t *const pSubPriority)
Decode Priority.
Definition: core_armv8mbl.h:1523
__STATIC_INLINE uint32_t __NVIC_GetVector(IRQn_Type IRQn)
Get Interrupt Vector.
Definition: core_armv8mbl.h:1566
__STATIC_INLINE void __NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority)
Set Interrupt Priority.
Definition: core_armv8mbl.h:1447
__STATIC_INLINE void __NVIC_ClearPendingIRQ(IRQn_Type IRQn)
Clear Pending Interrupt.
Definition: core_armv8mbl.h:1341
__STATIC_INLINE uint32_t __NVIC_GetPendingIRQ(IRQn_Type IRQn)
Get Pending Interrupt.
Definition: core_armv8mbl.h:1307
#define __NVIC_SetPriorityGrouping(X)
Definition: core_armv8mbl.h:1243
__STATIC_INLINE uint32_t SCB_GetFPUType(void)
get FPU type
Definition: core_armv8mbl.h:1791
__STATIC_INLINE void __NVIC_EnableIRQ(IRQn_Type IRQn)
Enable Interrupt.
Definition: core_armv8mbl.h:1252
#define NVIC_USER_IRQ_OFFSET
Definition: core_sc300.h:1442
__STATIC_INLINE uint32_t __NVIC_GetActive(IRQn_Type IRQn)
Get Active Interrupt.
Definition: core_armv8mbl.h:1358
__STATIC_INLINE void __NVIC_SetPendingIRQ(IRQn_Type IRQn)
Set Pending Interrupt.
Definition: core_armv8mbl.h:1326
__STATIC_INLINE uint32_t __NVIC_GetEnableIRQ(IRQn_Type IRQn)
Get Interrupt Enable status.
Definition: core_armv8mbl.h:1269
__STATIC_INLINE uint32_t NVIC_EncodePriority(uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority)
Encode Priority.
Definition: core_armv8mbl.h:1496
__STATIC_INLINE void __NVIC_DisableIRQ(IRQn_Type IRQn)
Disable Interrupt.
Definition: core_armv8mbl.h:1288
#define NVIC_SetPriority
Definition: core_sc300.h:1427
#define __NVIC_GetPriorityGrouping()
Get Priority Grouping.
Definition: core_armv8mbl.h:1244
__STATIC_INLINE uint32_t __NVIC_GetPriority(IRQn_Type IRQn)
Get Interrupt Priority.
Definition: core_armv8mbl.h:1471
#define ITM_TCR_ITMENA_Msk
Definition: core_sc300.h:794
#define SCB_AIRCR_PRIGROUP_Msk
Definition: core_sc300.h:466
#define SCB_AIRCR_VECTKEY_Msk
Definition: core_sc300.h:457
#define SCB_AIRCR_VECTKEY_Pos
Definition: core_sc300.h:456
#define SCB_AIRCR_SYSRESETREQ_Msk
Definition: core_sc300.h:469
#define SCB_AIRCR_PRIGROUP_Pos
Definition: core_sc300.h:465
#define SysTick_CTRL_ENABLE_Msk
Definition: core_sc300.h:695
#define SysTick_LOAD_RELOAD_Msk
Definition: core_sc300.h:699
#define SysTick_CTRL_TICKINT_Msk
Definition: core_sc300.h:692
#define SysTick_CTRL_CLKSOURCE_Msk
Definition: core_sc300.h:689
uint32_t T
Definition: core_sc300.h:266
volatile int32_t ITM_RxBuffer
__OM uint16_t u16
Definition: core_sc300.h:733
uint32_t Z
Definition: core_sc300.h:214
__OM uint8_t u8
Definition: core_sc300.h:732
uint32_t _reserved0
Definition: core_sc300.h:263
__OM uint32_t u32
Definition: core_sc300.h:734
uint32_t C
Definition: core_sc300.h:270
uint32_t Q
Definition: core_sc300.h:268
uint32_t N
Definition: core_sc300.h:215
uint32_t ISR
Definition: core_sc300.h:262
uint32_t Q
Definition: core_sc300.h:211
uint32_t _reserved1
Definition: core_sc300.h:315
uint32_t Z
Definition: core_sc300.h:271
uint32_t V
Definition: core_sc300.h:269
uint32_t SPSEL
Definition: core_sc300.h:314
uint32_t _reserved0
Definition: core_sc300.h:245
uint32_t V
Definition: core_sc300.h:212
#define ITM_RXBUFFER_EMPTY
Definition: core_sc300.h:1839
uint32_t nPRIV
Definition: core_sc300.h:313
__STATIC_INLINE int32_t ITM_ReceiveChar(void)
ITM Receive Character.
Definition: core_armv8mml.h:2883
__STATIC_INLINE uint32_t ITM_SendChar(uint32_t ch)
ITM Send Character.
Definition: core_armv8mml.h:2862
uint32_t ICI_IT_1
Definition: core_sc300.h:264
uint32_t ICI_IT_2
Definition: core_sc300.h:267
uint32_t _reserved1
Definition: core_sc300.h:265
uint32_t _reserved0
Definition: core_sc300.h:210
__STATIC_INLINE int32_t ITM_CheckChar(void)
ITM Check Character.
Definition: core_armv8mml.h:2903
uint32_t N
Definition: core_sc300.h:272
uint32_t C
Definition: core_sc300.h:213
uint32_t ISR
Definition: core_sc300.h:244
#define SCB
Definition: core_sc300.h:1373
#define ITM
Definition: core_sc300.h:1376
#define NVIC
Definition: core_sc300.h:1375
#define SysTick
Definition: core_sc300.h:1374
#define __NVIC_PRIO_BITS
Definition: stm32f303xe.h:49
#define COMP2
Definition: stm32f303xe.h:935
#define COMP3
Definition: stm32f303xe.h:937
#define COMP1
Definition: stm32f303xe.h:934
IRQn_Type
STM32F303xE devices Interrupt Number Definition, according to the selected device in Library_configur...
Definition: stm32f303xe.h:66
@ SysTick_IRQn
Definition: stm32f303xe.h:76
Structure type to access the Core Debug Register (CoreDebug).
Definition: core_armv8mbl.h:989
Structure type to access the Data Watchpoint and Trace Register (DWT).
Definition: core_armv8mbl.h:611
Structure type to access the Instrumentation Trace Macrocell Register (ITM).
Definition: core_armv8mml.h:1087
Structure type to access the Nested Vectored Interrupt Controller (NVIC).
Definition: core_armv8mbl.h:352
Structure type to access the System Control Block (SCB).
Definition: core_armv8mbl.h:382
Structure type to access the System Control and ID Register not in the SCB.
Definition: core_armv8mml.h:1010
Structure type to access the System Timer (SysTick).
Definition: core_armv8mbl.h:559
Structure type to access the Trace Port Interface Register (TPI).
Definition: core_armv8mbl.h:726
Union type to access the Application Program Status Register (APSR).
Definition: core_armv8mbl.h:234
Union type to access the Control Registers (CONTROL).
Definition: core_armv8mbl.h:321
Union type to access the Interrupt Program Status Register (IPSR).
Definition: core_armv8mbl.h:264
Union type to access the Special-Purpose Program Status Registers (xPSR).
Definition: core_armv8mbl.h:282