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Functions that access the ITM debug interface. More...
Functions that access the ITM debug interface.
| #define ITM_RXBUFFER_EMPTY ((int32_t)0x5AA55AA5U) |
Value identifying ITM_RxBuffer is ready for next character.
| #define ITM_RXBUFFER_EMPTY ((int32_t)0x5AA55AA5U) |
Value identifying ITM_RxBuffer is ready for next character.
| #define ITM_RXBUFFER_EMPTY ((int32_t)0x5AA55AA5U) |
Value identifying ITM_RxBuffer is ready for next character.
| #define ITM_RXBUFFER_EMPTY ((int32_t)0x5AA55AA5U) |
Value identifying ITM_RxBuffer is ready for next character.
| #define ITM_RXBUFFER_EMPTY ((int32_t)0x5AA55AA5U) |
Value identifying ITM_RxBuffer is ready for next character.
| #define ITM_RXBUFFER_EMPTY ((int32_t)0x5AA55AA5U) |
Value identifying ITM_RxBuffer is ready for next character.
| __STATIC_INLINE int32_t ITM_CheckChar | ( | void | ) |
ITM Check Character.
Checks whether a character is pending for reading in the variable ITM_RxBuffer.
| __STATIC_INLINE int32_t ITM_ReceiveChar | ( | void | ) |
ITM Receive Character.
Inputs a character via the external variable ITM_RxBuffer.
| __STATIC_INLINE uint32_t ITM_SendChar | ( | uint32_t | ch | ) |
ITM Send Character.
Transmits a character via the ITM channel 0, and
| [in] | ch | Character to transmit. |
| uint32_t { ... } ::_reserved0 |
bit: 0..15 Reserved
| uint32_t { ... } ::_reserved0 |
bit: 9..31 Reserved
| uint32_t { ... } ::_reserved0 |
bit: 9..15 Reserved
| uint32_t { ... } ::_reserved0 |
bit: 0..26 Reserved
| uint32_t { ... } ::_reserved0 |
bit: 9..31 Reserved
| uint32_t { ... } ::_reserved0 |
bit: 9 Reserved
| uint32_t { ... } ::_reserved0 |
bit: 0..15 Reserved
| uint32_t { ... } ::_reserved0 |
bit: 9..31 Reserved
| uint32_t { ... } ::_reserved0 |
bit: 9..15 Reserved
| uint32_t { ... } ::_reserved0 |
bit: 0..15 Reserved
| uint32_t { ... } ::_reserved0 |
bit: 9..31 Reserved
| uint32_t { ... } ::_reserved0 |
bit: 9 Reserved
| uint32_t { ... } ::_reserved0 |
bit: 3..31 Reserved
| uint32_t { ... } ::_reserved0 |
bit: 0..15 Reserved
| uint32_t { ... } ::_reserved0 |
bit: 9..31 Reserved
| uint32_t { ... } ::_reserved0 |
bit: 9 Reserved
| uint32_t { ... } ::_reserved0 |
bit: 3..31 Reserved
| uint32_t { ... } ::_reserved0 |
bit: 0..26 Reserved
| uint32_t { ... } ::_reserved0 |
bit: 9..31 Reserved
| uint32_t { ... } ::_reserved0 |
bit: 9 Reserved
| uint32_t APSR_Type::_reserved1 |
bit: 20..26 Reserved
| uint32_t { ... } ::_reserved1 |
bit: 20..26 Reserved
| uint32_t { ... } ::_reserved1 |
bit: 20..23 Reserved
| uint32_t { ... } ::_reserved1 |
bit: 4..31 Reserved
| uint32_t { ... } ::_reserved1 |
bit: 16..23 Reserved
| uint32_t { ... } ::_reserved1 |
bit: 2..31 Reserved
| uint32_t { ... } ::_reserved1 |
bit: 20..26 Reserved
| uint32_t { ... } ::_reserved1 |
bit: 20..23 Reserved
| uint32_t { ... } ::_reserved1 |
bit: 4..31 Reserved
| uint32_t { ... } ::_reserved1 |
bit: 20..26 Reserved
| uint32_t { ... } ::_reserved1 |
bit: 20..23 Reserved
| uint32_t { ... } ::_reserved1 |
bit: 20..26 Reserved
| uint32_t { ... } ::_reserved1 |
bit: 20..23 Reserved
| uint32_t { ... } ::_reserved1 |
bit: 16..23 Reserved
| uint32_t { ... } ::_reserved1 |
bit: 2..31 Reserved
| __IOM uint32_t SCB_Type::ABFSR |
Offset: 0x2A8 (R/W) Auxiliary Bus Fault Status Register
| __IOM uint32_t SCnSCB_Type::ACTLR |
Offset: 0x008 (R/W) Auxiliary Control Register
| __IM uint32_t SCB_Type::ADR |
Offset: 0x04C (R/ ) Auxiliary Feature Register
| __IOM uint32_t SCB_Type::AFSR |
Offset: 0x03C (R/W) Auxiliary Fault Status Register
| __IOM uint32_t SCB_Type::AHBPCR |
Offset: 0x298 (R/W) AHBP Control Register
| __IOM uint32_t SCB_Type::AHBSCR |
Offset: 0x2A0 (R/W) AHB Slave Control Register
| struct { ... } APSR_Type::b |
Structure used for bit access
| struct { ... } IPSR_Type::b |
Structure used for bit access
| struct { ... } xPSR_Type::b |
Structure used for bit access
| struct { ... } CONTROL_Type::b |
Structure used for bit access
| struct { ... } APSR_Type::b |
Structure used for bit access
| struct { ... } IPSR_Type::b |
Structure used for bit access
| struct { ... } xPSR_Type::b |
Structure used for bit access
| struct { ... } CONTROL_Type::b |
Structure used for bit access
| struct { ... } APSR_Type::b |
Structure used for bit access
| struct { ... } IPSR_Type::b |
Structure used for bit access
| struct { ... } xPSR_Type::b |
Structure used for bit access
| struct { ... } CONTROL_Type::b |
Structure used for bit access
| struct { ... } APSR_Type::b |
Structure used for bit access
| struct { ... } IPSR_Type::b |
Structure used for bit access
| struct { ... } xPSR_Type::b |
Structure used for bit access
| struct { ... } CONTROL_Type::b |
Structure used for bit access
| struct { ... } APSR_Type::b |
Structure used for bit access
| struct { ... } IPSR_Type::b |
Structure used for bit access
| struct { ... } xPSR_Type::b |
Structure used for bit access
| struct { ... } CONTROL_Type::b |
Structure used for bit access
| struct { ... } APSR_Type::b |
Structure used for bit access
| struct { ... } IPSR_Type::b |
Structure used for bit access
| struct { ... } xPSR_Type::b |
Structure used for bit access
| struct { ... } CONTROL_Type::b |
Structure used for bit access
| __IOM uint32_t SCB_Type::BFAR |
Offset: 0x038 (R/W) BusFault Address Register
| uint32_t { ... } ::C |
bit: 29 Carry condition code flag
| uint32_t { ... } ::C |
bit: 29 Carry condition code flag
| uint32_t { ... } ::C |
bit: 29 Carry condition code flag
| uint32_t { ... } ::C |
bit: 29 Carry condition code flag
| uint32_t { ... } ::C |
bit: 29 Carry condition code flag
| uint32_t { ... } ::C |
bit: 29 Carry condition code flag
| uint32_t { ... } ::C |
bit: 29 Carry condition code flag
| uint32_t { ... } ::C |
bit: 29 Carry condition code flag
| uint32_t { ... } ::C |
bit: 29 Carry condition code flag
| uint32_t { ... } ::C |
bit: 29 Carry condition code flag
| uint32_t { ... } ::C |
bit: 29 Carry condition code flag
| uint32_t { ... } ::C |
bit: 29 Carry condition code flag
| __IOM uint32_t SCB_Type::CACR |
Offset: 0x29C (R/W) L1 Cache Control Register
| __IM uint32_t SCB_Type::CCSIDR |
Offset: 0x080 (R/ ) Cache Size ID Register
| __IOM uint32_t SCB_Type::CFSR |
Offset: 0x028 (R/W) Configurable Fault Status Register
| __IM uint32_t ITM_Type::CID0 |
Offset: 0xFF0 (R/ ) ITM Component Identification Register #0
| __IM uint32_t ITM_Type::CID1 |
Offset: 0xFF4 (R/ ) ITM Component Identification Register #1
| __IM uint32_t ITM_Type::CID2 |
Offset: 0xFF8 (R/ ) ITM Component Identification Register #2
| __IM uint32_t ITM_Type::CID3 |
Offset: 0xFFC (R/ ) ITM Component Identification Register #3
| __IM uint32_t SCB_Type::CLIDR |
Offset: 0x078 (R/ ) Cache Level ID register
| __IOM uint32_t SCB_Type::CPACR |
Offset: 0x088 (R/W) Coprocessor Access Control Register
| __IOM uint32_t DWT_Type::CPICNT |
Offset: 0x008 (R/W) CPI Count Register
| __IOM uint32_t SCnSCB_Type::CPPWR |
Offset: 0x00C (R/W) Coprocessor Power Control Register
| __IOM uint32_t SCB_Type::CSSELR |
Offset: 0x084 (R/W) Cache Size Selection Register
| __IM uint32_t SCB_Type::CTR |
Offset: 0x07C (R/ ) Cache Type register
| __IOM uint32_t DWT_Type::CYCCNT |
Offset: 0x004 (R/W) Cycle Count Register
| __OM uint32_t SCB_Type::DCCIMVAC |
Offset: 0x270 ( /W) D-Cache Clean and Invalidate by MVA to PoC
| __OM uint32_t SCB_Type::DCCISW |
Offset: 0x274 ( /W) D-Cache Clean and Invalidate by Set-way
| __OM uint32_t SCB_Type::DCCMVAC |
Offset: 0x268 ( /W) D-Cache Clean by MVA to PoC
| __OM uint32_t SCB_Type::DCCMVAU |
Offset: 0x264 ( /W) D-Cache Clean by MVA to PoU
| __OM uint32_t SCB_Type::DCCSW |
Offset: 0x26C ( /W) D-Cache Clean by Set-way
| __OM uint32_t SCB_Type::DCIMVAC |
Offset: 0x25C ( /W) D-Cache Invalidate by MVA to PoC
| __OM uint32_t SCB_Type::DCISW |
Offset: 0x260 ( /W) D-Cache Invalidate by Set-way
| __IM uint32_t ITM_Type::DEVARCH |
Offset: 0xFBC (R/ ) ITM Device Architecture Register
| __IM uint32_t DWT_Type::DEVARCH |
Offset: 0xFBC (R/ ) Device Architecture Register
| __IM uint32_t SCB_Type::DFR |
Offset: 0x048 (R/ ) Debug Feature Register
| __IOM uint32_t SCB_Type::DFSR |
Offset: 0x030 (R/W) Debug Fault Status Register
| __IOM uint32_t SCB_Type::DTCMCR |
Offset: 0x294 (R/W) Data Tightly-Coupled Memory Control Registers
| __IOM uint32_t DWT_Type::EXCCNT |
Offset: 0x00C (R/W) Exception Overhead Count Register
| __IM uint32_t TPI_Type::FIFO0 |
Offset: 0xEEC (R/ ) Integration ETM Data
| __IM uint32_t TPI_Type::FIFO1 |
Offset: 0xEFC (R/ ) Integration ITM Data
| __IOM uint32_t DWT_Type::FOLDCNT |
Offset: 0x018 (R/W) Folded-instruction Count Register
| uint32_t { ... } ::FPCA |
bit: 2 Floating-point context active
| uint32_t CONTROL_Type::FPCA |
bit: 2 Floating-point context active
bit: 2 FP extension active flag
| uint32_t { ... } ::FPCA |
bit: 2 Floating-point context active
| uint32_t { ... } ::FPCA |
bit: 2 FP extension active flag
| uint32_t { ... } ::FPCA |
bit: 2 FP extension active flag
| __IOM uint32_t FPU_Type::FPCAR |
Offset: 0x008 (R/W) Floating-Point Context Address Register
| __IOM uint32_t FPU_Type::FPCCR |
Offset: 0x004 (R/W) Floating-Point Context Control Register
| __IOM uint32_t FPU_Type::FPDSCR |
Offset: 0x00C (R/W) Floating-Point Default Status Control Register
| __IM uint32_t TPI_Type::FSCR |
Offset: 0x308 (R/ ) Formatter Synchronization Counter Register
| uint32_t APSR_Type::GE |
bit: 16..19 Greater than or Equal flags
| uint32_t { ... } ::GE |
bit: 16..19 Greater than or Equal flags
| uint32_t xPSR_Type::GE |
bit: 16..19 Greater than or Equal flags
| uint32_t { ... } ::GE |
bit: 16..19 Greater than or Equal flags
| uint32_t { ... } ::GE |
bit: 16..19 Greater than or Equal flags
| uint32_t { ... } ::GE |
bit: 16..19 Greater than or Equal flags
| uint32_t { ... } ::GE |
bit: 16..19 Greater than or Equal flags
| uint32_t { ... } ::GE |
bit: 16..19 Greater than or Equal flags
| uint32_t { ... } ::GE |
bit: 16..19 Greater than or Equal flags
| uint32_t { ... } ::GE |
bit: 16..19 Greater than or Equal flags
| __IOM uint32_t SCB_Type::HFSR |
Offset: 0x02C (R/W) HardFault Status Register
| uint32_t xPSR_Type::ICI_IT_1 |
bit: 10..15 ICI/IT part 1
| uint32_t { ... } ::ICI_IT_1 |
bit: 10..15 ICI/IT part 1
| uint32_t { ... } ::ICI_IT_1 |
bit: 10..15 ICI/IT part 1
| uint32_t { ... } ::ICI_IT_1 |
bit: 10..15 ICI/IT part 1
| uint32_t { ... } ::ICI_IT_1 |
bit: 10..15 ICI/IT part 1
| uint32_t xPSR_Type::ICI_IT_2 |
bit: 25..26 ICI/IT part 2
| uint32_t { ... } ::ICI_IT_2 |
bit: 25..26 ICI/IT part 2
| uint32_t { ... } ::ICI_IT_2 |
bit: 25..26 ICI/IT part 2
| uint32_t { ... } ::ICI_IT_2 |
bit: 25..26 ICI/IT part 2
| uint32_t { ... } ::ICI_IT_2 |
bit: 25..26 ICI/IT part 2
| __OM uint32_t SCB_Type::ICIALLU |
Offset: 0x250 ( /W) I-Cache Invalidate All to PoU
| __OM uint32_t SCB_Type::ICIMVAU |
Offset: 0x258 ( /W) I-Cache Invalidate by MVA to PoU
| __IM uint32_t SCnSCB_Type::ICTR |
Offset: 0x004 (R/ ) Interrupt Controller Type Register
| __IM uint32_t SCB_Type::ID_ADR |
Offset: 0x04C (R/ ) Auxiliary Feature Register
| __IM uint32_t SCB_Type::ID_AFR |
Offset: 0x04C (R/ ) Auxiliary Feature Register
| __IM uint32_t SCB_Type::ID_DFR |
Offset: 0x048 (R/ ) Debug Feature Register
| __IM uint32_t SCB_Type::ID_ISAR |
Offset: 0x060 (R/ ) Instruction Set Attributes Register
| __IM uint32_t SCB_Type::ID_MFR[4U] |
Offset: 0x050 (R/ ) Memory Model Feature Register
| __IM uint32_t SCB_Type::ID_MMFR |
Offset: 0x050 (R/ ) Memory Model Feature Register
| __IM uint32_t SCB_Type::ID_PFR |
Offset: 0x040 (R/ ) Processor Feature Register
| __IOM uint32_t ITM_Type::IMCR |
Offset: 0xF00 (R/W) ITM Integration Mode Control Register
| __IOM uint8_t NVIC_Type::IP[240U] |
Offset: 0x300 (R/W) Interrupt Priority Register (8Bit wide)
| __IOM uint8_t NVIC_Type::IPR[496U] |
Offset: 0x300 (R/W) Interrupt Priority Register (8Bit wide)
| __IM uint32_t ITM_Type::IRR |
Offset: 0xEFC (R/ ) ITM Integration Read Register
| __IM uint32_t SCB_Type::ISAR |
Offset: 0x060 (R/ ) Instruction Set Attributes Register
| uint32_t { ... } ::ISR |
bit: 0.. 8 Exception number
| uint32_t { ... } ::ISR |
bit: 0.. 8 Exception number
| uint32_t { ... } ::ISR |
bit: 0.. 8 Exception number
| uint32_t { ... } ::ISR |
bit: 0.. 8 Exception number
| uint32_t { ... } ::ISR |
bit: 0.. 8 Exception number
| uint32_t { ... } ::ISR |
bit: 0.. 8 Exception number
| uint32_t { ... } ::ISR |
bit: 0.. 8 Exception number
| uint32_t { ... } ::ISR |
bit: 0.. 8 Exception number
| uint32_t { ... } ::ISR |
bit: 0.. 8 Exception number
| uint32_t { ... } ::ISR |
bit: 0.. 8 Exception number
| uint32_t { ... } ::ISR |
bit: 0.. 8 Exception number
| uint32_t { ... } ::ISR |
bit: 0.. 8 Exception number
| uint32_t { ... } ::IT |
bit: 25..26 saved IT state (read 0)
| uint32_t xPSR_Type::IT |
bit: 25..26 saved IT state (read 0)
| uint32_t { ... } ::IT |
bit: 25..26 saved IT state (read 0)
| __IM uint32_t TPI_Type::ITATBCTR2 |
Offset: 0xEF0 (R/ ) ITATBCTR2
| __IOM uint32_t SCB_Type::ITCMCR |
Offset: 0x290 (R/W) Instruction Tightly-Coupled Memory Control Register
|
extern |
External variable to receive characters.
|
extern |
External variable to receive characters.
|
extern |
External variable to receive characters.
|
extern |
External variable to receive characters.
|
extern |
External variable to receive characters.
|
extern |
External variable to receive characters.
| __OM uint32_t ITM_Type::IWR |
Offset: 0xEF8 ( /W) ITM Integration Write Register
| __OM uint32_t ITM_Type::LAR |
Offset: 0xFB0 ( /W) ITM Lock Access Register
| __OM uint32_t DWT_Type::LAR |
Offset: 0xFB0 ( W) Lock Access Register
| __IM uint32_t ITM_Type::LSR |
Offset: 0xFB4 (R/ ) ITM Lock Status Register
| __IM uint32_t DWT_Type::LSR |
Offset: 0xFB4 (R ) Lock Status Register
| __IOM uint32_t DWT_Type::LSUCNT |
Offset: 0x014 (R/W) LSU Count Register
| __IOM uint32_t DWT_Type::MASK0 |
Offset: 0x024 (R/W) Mask Register 0
| __IOM uint32_t DWT_Type::MASK1 |
Offset: 0x034 (R/W) Mask Register 1
| __IOM uint32_t DWT_Type::MASK2 |
Offset: 0x044 (R/W) Mask Register 2
| __IOM uint32_t DWT_Type::MASK3 |
Offset: 0x054 (R/W) Mask Register 3
| __IOM uint32_t SCB_Type::MMFAR |
Offset: 0x034 (R/W) MemManage Fault Address Register
| __IM uint32_t SCB_Type::MMFR |
Offset: 0x050 (R/ ) Memory Model Feature Register
| __IM uint32_t SCB_Type::MVFR0 |
Offset: 0x240 (R/ ) Media and VFP Feature Register 0
| __IM uint32_t FPU_Type::MVFR0 |
Offset: 0x010 (R/ ) Media and FP Feature Register 0
| __IM uint32_t SCB_Type::MVFR1 |
Offset: 0x244 (R/ ) Media and VFP Feature Register 1
| __IM uint32_t FPU_Type::MVFR1 |
Offset: 0x014 (R/ ) Media and FP Feature Register 1
| __IM uint32_t SCB_Type::MVFR2 |
Offset: 0x248 (R/ ) Media and VFP Feature Register 2
| __IM uint32_t FPU_Type::MVFR2 |
Offset: 0x018 (R/ ) Media and FP Feature Register 2
| uint32_t { ... } ::N |
bit: 31 Negative condition code flag
| uint32_t { ... } ::N |
bit: 31 Negative condition code flag
| uint32_t { ... } ::N |
bit: 31 Negative condition code flag
| uint32_t { ... } ::N |
bit: 31 Negative condition code flag
| uint32_t { ... } ::N |
bit: 31 Negative condition code flag
| uint32_t { ... } ::N |
bit: 31 Negative condition code flag
| uint32_t { ... } ::N |
bit: 31 Negative condition code flag
| uint32_t { ... } ::N |
bit: 31 Negative condition code flag
| uint32_t { ... } ::N |
bit: 31 Negative condition code flag
| uint32_t { ... } ::N |
bit: 31 Negative condition code flag
| uint32_t { ... } ::N |
bit: 31 Negative condition code flag
| uint32_t { ... } ::N |
bit: 31 Negative condition code flag
| uint32_t { ... } ::nPRIV |
bit: 0 Execution privilege in Thread mode
| uint32_t { ... } ::nPRIV |
bit: 0 Execution privilege in Thread mode
| uint32_t { ... } ::nPRIV |
bit: 0 Execution privilege in Thread mode
| uint32_t { ... } ::nPRIV |
bit: 0 Execution privilege in Thread mode
| uint32_t { ... } ::nPRIV |
bit: 0 Execution privilege in Thread mode
| uint32_t { ... } ::nPRIV |
bit: 0 Execution privilege in Thread mode
| __IOM uint32_t SCB_Type::NSACR |
Offset: 0x08C (R/W) Non-Secure Access Control Register
| __IM uint32_t SCB_Type::PFR |
Offset: 0x040 (R/ ) Processor Feature Register
| __IM uint32_t ITM_Type::PID0 |
Offset: 0xFE0 (R/ ) ITM Peripheral Identification Register #0
| __IM uint32_t ITM_Type::PID1 |
Offset: 0xFE4 (R/ ) ITM Peripheral Identification Register #1
| __IM uint32_t ITM_Type::PID2 |
Offset: 0xFE8 (R/ ) ITM Peripheral Identification Register #2
| __IM uint32_t ITM_Type::PID3 |
Offset: 0xFEC (R/ ) ITM Peripheral Identification Register #3
| __IM uint32_t ITM_Type::PID4 |
Offset: 0xFD0 (R/ ) ITM Peripheral Identification Register #4
| __IM uint32_t ITM_Type::PID5 |
Offset: 0xFD4 (R/ ) ITM Peripheral Identification Register #5
| __IM uint32_t ITM_Type::PID6 |
Offset: 0xFD8 (R/ ) ITM Peripheral Identification Register #6
| __IM uint32_t ITM_Type::PID7 |
Offset: 0xFDC (R/ ) ITM Peripheral Identification Register #7
| __OM union { ... } ITM_Type::PORT[32U] |
Offset: 0x000 ( /W) ITM Stimulus Port Registers
| __OM union { ... } ITM_Type::PORT[32U] |
Offset: 0x000 ( /W) ITM Stimulus Port Registers
| __OM union { ... } ITM_Type::PORT[32U] |
Offset: 0x000 ( /W) ITM Stimulus Port Registers
| __OM union { ... } ITM_Type::PORT[32U] |
Offset: 0x000 ( /W) ITM Stimulus Port Registers
| __OM union { ... } ITM_Type::PORT[32U] |
Offset: 0x000 ( /W) ITM Stimulus Port Registers
| __OM union { ... } ITM_Type::PORT[32U] |
Offset: 0x000 ( /W) ITM Stimulus Port Registers
| uint32_t APSR_Type::Q |
bit: 27 Saturation condition flag
| uint32_t { ... } ::Q |
bit: 27 Saturation condition flag
| uint32_t { ... } ::Q |
bit: 27 Saturation condition flag
| uint32_t xPSR_Type::Q |
bit: 27 Saturation condition flag
| uint32_t { ... } ::Q |
bit: 27 Saturation condition flag
| uint32_t { ... } ::Q |
bit: 27 Saturation condition flag
| uint32_t { ... } ::Q |
bit: 27 Saturation condition flag
| uint32_t { ... } ::Q |
bit: 27 Saturation condition flag
| uint32_t { ... } ::Q |
bit: 27 Saturation condition flag
| uint32_t { ... } ::Q |
bit: 27 Saturation condition flag
| uint32_t { ... } ::Q |
bit: 27 Saturation condition flag
| uint32_t { ... } ::Q |
bit: 27 Saturation condition flag
| uint32_t { ... } ::Q |
bit: 27 Saturation condition flag
| uint32_t { ... } ::Q |
bit: 27 Saturation condition flag
| uint32_t SCnSCB_Type::RESERVED0 |
| uint32_t FPU_Type::RESERVED0 |
| uint32_t ITM_Type::RESERVED0 |
| uint32_t ITM_Type::RESERVED1 |
| uint32_t SCnSCB_Type::RESERVED1 |
| uint32_t ITM_Type::RESERVED2 |
| uint32_t ITM_Type::RESERVED3 |
| uint32_t SCB_Type::RESERVED3 |
| uint32_t DWT_Type::RESERVED32 |
| uint32_t DWT_Type::RESERVED33 |
| uint32_t SCB_Type::RESERVED4 |
| uint32_t ITM_Type::RESERVED4 |
| uint32_t SCB_Type::RESERVED5 |
| uint32_t ITM_Type::RESERVED5 |
| uint32_t SCB_Type::RESERVED6 |
| uint32_t ITM_Type::RESERVED6 |
| uint32_t NVIC_Type::RESERVED6 |
| uint32_t SCB_Type::RESERVED7 |
| uint32_t SCB_Type::RESERVED8 |
| uint32_t { ... } ::SFPA |
bit: 3 Secure floating-point active
| uint32_t CONTROL_Type::SFPA |
bit: 3 Secure floating-point active
| uint32_t { ... } ::SFPA |
bit: 3 Secure floating-point active
| __IOM uint8_t SCB_Type::SHP[12U] |
Offset: 0x018 (R/W) System Handlers Priority Registers (4-7, 8-11, 12-15)
| __IOM uint8_t SCB_Type::SHPR[12U] |
Offset: 0x018 (R/W) System Handlers Priority Registers (4-7, 8-11, 12-15)
| __IOM uint32_t DWT_Type::SLEEPCNT |
Offset: 0x010 (R/W) Sleep Count Register
| uint32_t { ... } ::SPSEL |
bit: 1 Stack-pointer select
| uint32_t { ... } ::SPSEL |
bit: 1 Stack to be used
| uint32_t { ... } ::SPSEL |
bit: 1 Stack-pointer select
| uint32_t { ... } ::SPSEL |
bit: 1 Stack to be used
| uint32_t { ... } ::SPSEL |
bit: 1 Stack to be used
| uint32_t { ... } ::SPSEL |
bit: 1 Stack to be used
| __OM uint32_t NVIC_Type::STIR |
Offset: 0xE00 ( /W) Software Trigger Interrupt Register
| __OM uint32_t SCB_Type::STIR |
Offset: 0x200 ( /W) Software Triggered Interrupt Register
| uint32_t { ... } ::T |
bit: 24 Thumb bit (read 0)
| uint32_t { ... } ::T |
bit: 24 Thumb bit
| uint32_t { ... } ::T |
bit: 24 Thumb bit (read 0)
| uint32_t { ... } ::T |
bit: 24 Thumb bit
| uint32_t { ... } ::T |
bit: 24 Thumb bit
| uint32_t { ... } ::T |
bit: 24 Thumb bit
| __IOM uint32_t ITM_Type::TCR |
Offset: 0xE80 (R/W) ITM Trace Control Register
| __IOM uint32_t ITM_Type::TER |
Offset: 0xE00 (R/W) ITM Trace Enable Register
| __IOM uint32_t ITM_Type::TPR |
Offset: 0xE40 (R/W) ITM Trace Privilege Register
| __OM uint16_t { ... } ::u16 |
Offset: 0x000 ( /W) ITM Stimulus Port 16-bit
| __OM uint16_t ITM_Type::u16 |
Offset: 0x000 ( /W) ITM Stimulus Port 16-bit
| __OM uint16_t { ... } ::u16 |
Offset: 0x000 ( /W) ITM Stimulus Port 16-bit
| __OM uint16_t { ... } ::u16 |
Offset: 0x000 ( /W) ITM Stimulus Port 16-bit
| __OM uint16_t { ... } ::u16 |
Offset: 0x000 ( /W) ITM Stimulus Port 16-bit
| __OM uint16_t { ... } ::u16 |
Offset: 0x000 ( /W) ITM Stimulus Port 16-bit
| __OM uint16_t { ... } ::u16 |
Offset: 0x000 ( /W) ITM Stimulus Port 16-bit
| __OM uint32_t ITM_Type::u32 |
Offset: 0x000 ( /W) ITM Stimulus Port 32-bit
| __OM uint32_t { ... } ::u32 |
Offset: 0x000 ( /W) ITM Stimulus Port 32-bit
| __OM uint32_t { ... } ::u32 |
Offset: 0x000 ( /W) ITM Stimulus Port 32-bit
| __OM uint32_t { ... } ::u32 |
Offset: 0x000 ( /W) ITM Stimulus Port 32-bit
| __OM uint32_t { ... } ::u32 |
Offset: 0x000 ( /W) ITM Stimulus Port 32-bit
| __OM uint32_t { ... } ::u32 |
Offset: 0x000 ( /W) ITM Stimulus Port 32-bit
| __OM uint32_t { ... } ::u32 |
Offset: 0x000 ( /W) ITM Stimulus Port 32-bit
| __OM uint8_t { ... } ::u8 |
Offset: 0x000 ( /W) ITM Stimulus Port 8-bit
| __OM uint8_t ITM_Type::u8 |
Offset: 0x000 ( /W) ITM Stimulus Port 8-bit
| __OM uint8_t { ... } ::u8 |
Offset: 0x000 ( /W) ITM Stimulus Port 8-bit
| __OM uint8_t { ... } ::u8 |
Offset: 0x000 ( /W) ITM Stimulus Port 8-bit
| __OM uint8_t { ... } ::u8 |
Offset: 0x000 ( /W) ITM Stimulus Port 8-bit
| __OM uint8_t { ... } ::u8 |
Offset: 0x000 ( /W) ITM Stimulus Port 8-bit
| __OM uint8_t { ... } ::u8 |
Offset: 0x000 ( /W) ITM Stimulus Port 8-bit
| uint32_t { ... } ::V |
bit: 28 Overflow condition code flag
| uint32_t { ... } ::V |
bit: 28 Overflow condition code flag
| uint32_t { ... } ::V |
bit: 28 Overflow condition code flag
| uint32_t { ... } ::V |
bit: 28 Overflow condition code flag
| uint32_t { ... } ::V |
bit: 28 Overflow condition code flag
| uint32_t { ... } ::V |
bit: 28 Overflow condition code flag
| uint32_t { ... } ::V |
bit: 28 Overflow condition code flag
| uint32_t { ... } ::V |
bit: 28 Overflow condition code flag
| uint32_t { ... } ::V |
bit: 28 Overflow condition code flag
| uint32_t { ... } ::V |
bit: 28 Overflow condition code flag
| uint32_t { ... } ::V |
bit: 28 Overflow condition code flag
| uint32_t { ... } ::V |
bit: 28 Overflow condition code flag
| __IOM uint32_t SCB_Type::VTOR |
Offset: 0x008 (R/W) Vector Table Offset Register
| uint32_t { ... } ::Z |
bit: 30 Zero condition code flag
| uint32_t { ... } ::Z |
bit: 30 Zero condition code flag
| uint32_t { ... } ::Z |
bit: 30 Zero condition code flag
| uint32_t { ... } ::Z |
bit: 30 Zero condition code flag
| uint32_t { ... } ::Z |
bit: 30 Zero condition code flag
| uint32_t { ... } ::Z |
bit: 30 Zero condition code flag
| uint32_t { ... } ::Z |
bit: 30 Zero condition code flag
| uint32_t { ... } ::Z |
bit: 30 Zero condition code flag
| uint32_t { ... } ::Z |
bit: 30 Zero condition code flag
| uint32_t { ... } ::Z |
bit: 30 Zero condition code flag
| uint32_t { ... } ::Z |
bit: 30 Zero condition code flag
| uint32_t { ... } ::Z |
bit: 30 Zero condition code flag
1.9.6