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stm32f3xx_hal_rcc.h
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1
18/* Define to prevent recursive inclusion -------------------------------------*/
19#ifndef __STM32F3xx_HAL_RCC_H
20#define __STM32F3xx_HAL_RCC_H
21
22#ifdef __cplusplus
23 extern "C" {
24#endif
25
26/* Includes ------------------------------------------------------------------*/
27#include "stm32f3xx_hal_def.h"
28
45/* Disable Backup domain write protection state change timeout */
46#define RCC_DBP_TIMEOUT_VALUE (100U) /* 100 ms */
47/* LSE state change timeout */
48#define RCC_LSE_TIMEOUT_VALUE LSE_STARTUP_TIMEOUT
49#define CLOCKSWITCH_TIMEOUT_VALUE (5000U) /* 5 s */
50#define HSE_TIMEOUT_VALUE HSE_STARTUP_TIMEOUT
51#define HSI_TIMEOUT_VALUE (2U) /* 2 ms (minimum Tick + 1U) */
52#define LSI_TIMEOUT_VALUE (2U) /* 2 ms (minimum Tick + 1U) */
53#define PLL_TIMEOUT_VALUE (2U) /* 2 ms (minimum Tick + 1U) */
61#define RCC_OFFSET (RCC_BASE - PERIPH_BASE)
62#define RCC_CR_OFFSET 0x00
63#define RCC_CFGR_OFFSET 0x04
64#define RCC_CIR_OFFSET 0x08
65#define RCC_BDCR_OFFSET 0x20
66#define RCC_CSR_OFFSET 0x24
67
76#define RCC_CR_OFFSET_BB (RCC_OFFSET + RCC_CR_OFFSET)
77#define RCC_CFGR_OFFSET_BB (RCC_OFFSET + RCC_CFGR_OFFSET)
78#define RCC_CIR_OFFSET_BB (RCC_OFFSET + RCC_CIR_OFFSET)
79#define RCC_BDCR_OFFSET_BB (RCC_OFFSET + RCC_BDCR_OFFSET)
80#define RCC_CSR_OFFSET_BB (RCC_OFFSET + RCC_CSR_OFFSET)
81
82/* --- CR Register ---*/
83/* Alias word address of HSION bit */
84#define RCC_HSION_BIT_NUMBER POSITION_VAL(RCC_CR_HSION)
85#define RCC_CR_HSION_BB ((uint32_t)(PERIPH_BB_BASE + (RCC_CR_OFFSET_BB * 32U) + (RCC_HSION_BIT_NUMBER * 4U)))
86/* Alias word address of HSEON bit */
87#define RCC_HSEON_BIT_NUMBER POSITION_VAL(RCC_CR_HSEON)
88#define RCC_CR_HSEON_BB ((uint32_t)(PERIPH_BB_BASE + (RCC_CR_OFFSET_BB * 32U) + (RCC_HSEON_BIT_NUMBER * 4U)))
89/* Alias word address of CSSON bit */
90#define RCC_CSSON_BIT_NUMBER POSITION_VAL(RCC_CR_CSSON)
91#define RCC_CR_CSSON_BB ((uint32_t)(PERIPH_BB_BASE + (RCC_CR_OFFSET_BB * 32U) + (RCC_CSSON_BIT_NUMBER * 4U)))
92/* Alias word address of PLLON bit */
93#define RCC_PLLON_BIT_NUMBER POSITION_VAL(RCC_CR_PLLON)
94#define RCC_CR_PLLON_BB ((uint32_t)(PERIPH_BB_BASE + (RCC_CR_OFFSET_BB * 32U) + (RCC_PLLON_BIT_NUMBER * 4U)))
95
96/* --- CSR Register ---*/
97/* Alias word address of LSION bit */
98#define RCC_LSION_BIT_NUMBER POSITION_VAL(RCC_CSR_LSION)
99#define RCC_CSR_LSION_BB ((uint32_t)(PERIPH_BB_BASE + (RCC_CSR_OFFSET_BB * 32U) + (RCC_LSION_BIT_NUMBER * 4U)))
100
101/* Alias word address of RMVF bit */
102#define RCC_RMVF_BIT_NUMBER POSITION_VAL(RCC_CSR_RMVF)
103#define RCC_CSR_RMVF_BB ((uint32_t)(PERIPH_BB_BASE + (RCC_CSR_OFFSET_BB * 32U) + (RCC_RMVF_BIT_NUMBER * 4U)))
104
105/* --- BDCR Registers ---*/
106/* Alias word address of LSEON bit */
107#define RCC_LSEON_BIT_NUMBER POSITION_VAL(RCC_BDCR_LSEON)
108#define RCC_BDCR_LSEON_BB ((uint32_t)(PERIPH_BB_BASE + (RCC_BDCR_OFFSET_BB * 32U) + (RCC_LSEON_BIT_NUMBER * 4U)))
109
110/* Alias word address of LSEON bit */
111#define RCC_LSEBYP_BIT_NUMBER POSITION_VAL(RCC_BDCR_LSEBYP)
112#define RCC_BDCR_LSEBYP_BB ((uint32_t)(PERIPH_BB_BASE + (RCC_BDCR_OFFSET_BB * 32U) + (RCC_LSEBYP_BIT_NUMBER * 4U)))
113
114/* Alias word address of RTCEN bit */
115#define RCC_RTCEN_BIT_NUMBER POSITION_VAL(RCC_BDCR_RTCEN)
116#define RCC_BDCR_RTCEN_BB ((uint32_t)(PERIPH_BB_BASE + (RCC_BDCR_OFFSET_BB * 32U) + (RCC_RTCEN_BIT_NUMBER * 4U)))
117
118/* Alias word address of BDRST bit */
119#define RCC_BDRST_BIT_NUMBER POSITION_VAL(RCC_BDCR_BDRST)
120#define RCC_BDCR_BDRST_BB ((uint32_t)(PERIPH_BB_BASE + (RCC_BDCR_OFFSET_BB * 32U) + (RCC_BDRST_BIT_NUMBER * 4U)))
121
126/* CR register byte 2 (Bits[23:16]) base address */
127#define RCC_CR_BYTE2_ADDRESS ((uint32_t)(RCC_BASE + RCC_CR_OFFSET + 0x02U))
128
129/* CIR register byte 1 (Bits[15:8]) base address */
130#define RCC_CIR_BYTE1_ADDRESS ((uint32_t)(RCC_BASE + RCC_CIR_OFFSET + 0x01U))
131
132/* CIR register byte 2 (Bits[23:16]) base address */
133#define RCC_CIR_BYTE2_ADDRESS ((uint32_t)(RCC_BASE + RCC_CIR_OFFSET + 0x02U))
134
135/* Defines used for Flags */
136#define CR_REG_INDEX ((uint8_t)1U)
137#define BDCR_REG_INDEX ((uint8_t)2U)
138#define CSR_REG_INDEX ((uint8_t)3U)
139#define CFGR_REG_INDEX ((uint8_t)4U)
140
141#define RCC_FLAG_MASK ((uint8_t)0x1FU)
142
150#define IS_RCC_PLLSOURCE(__SOURCE__) (((__SOURCE__) == RCC_PLLSOURCE_HSI) || \
151 ((__SOURCE__) == RCC_PLLSOURCE_HSE))
152#define IS_RCC_OSCILLATORTYPE(__OSCILLATOR__) (((__OSCILLATOR__) == RCC_OSCILLATORTYPE_NONE) || \
153 (((__OSCILLATOR__) & RCC_OSCILLATORTYPE_HSE) == RCC_OSCILLATORTYPE_HSE) || \
154 (((__OSCILLATOR__) & RCC_OSCILLATORTYPE_HSI) == RCC_OSCILLATORTYPE_HSI) || \
155 (((__OSCILLATOR__) & RCC_OSCILLATORTYPE_LSI) == RCC_OSCILLATORTYPE_LSI) || \
156 (((__OSCILLATOR__) & RCC_OSCILLATORTYPE_LSE) == RCC_OSCILLATORTYPE_LSE))
157#define IS_RCC_HSE(__HSE__) (((__HSE__) == RCC_HSE_OFF) || ((__HSE__) == RCC_HSE_ON) || \
158 ((__HSE__) == RCC_HSE_BYPASS))
159#define IS_RCC_LSE(__LSE__) (((__LSE__) == RCC_LSE_OFF) || ((__LSE__) == RCC_LSE_ON) || \
160 ((__LSE__) == RCC_LSE_BYPASS))
161#define IS_RCC_HSI(__HSI__) (((__HSI__) == RCC_HSI_OFF) || ((__HSI__) == RCC_HSI_ON))
162#define IS_RCC_CALIBRATION_VALUE(__VALUE__) ((__VALUE__) <= 0x1FU)
163#define IS_RCC_LSI(__LSI__) (((__LSI__) == RCC_LSI_OFF) || ((__LSI__) == RCC_LSI_ON))
164#define IS_RCC_PLL(__PLL__) (((__PLL__) == RCC_PLL_NONE) || ((__PLL__) == RCC_PLL_OFF) || \
165 ((__PLL__) == RCC_PLL_ON))
166#if defined(RCC_CFGR_PLLSRC_HSI_PREDIV)
167#define IS_RCC_PREDIV(__PREDIV__) (((__PREDIV__) == RCC_PREDIV_DIV1) || ((__PREDIV__) == RCC_PREDIV_DIV2) || \
168 ((__PREDIV__) == RCC_PREDIV_DIV3) || ((__PREDIV__) == RCC_PREDIV_DIV4) || \
169 ((__PREDIV__) == RCC_PREDIV_DIV5) || ((__PREDIV__) == RCC_PREDIV_DIV6) || \
170 ((__PREDIV__) == RCC_PREDIV_DIV7) || ((__PREDIV__) == RCC_PREDIV_DIV8) || \
171 ((__PREDIV__) == RCC_PREDIV_DIV9) || ((__PREDIV__) == RCC_PREDIV_DIV10) || \
172 ((__PREDIV__) == RCC_PREDIV_DIV11) || ((__PREDIV__) == RCC_PREDIV_DIV12) || \
173 ((__PREDIV__) == RCC_PREDIV_DIV13) || ((__PREDIV__) == RCC_PREDIV_DIV14) || \
174 ((__PREDIV__) == RCC_PREDIV_DIV15) || ((__PREDIV__) == RCC_PREDIV_DIV16))
175#else
176#define IS_RCC_PLL_DIV(__DIV__) (((__DIV__) == RCC_PLL_DIV2) || \
177 ((__DIV__) == RCC_PLL_DIV3) || ((__DIV__) == RCC_PLL_DIV4))
178#endif
179#if defined(RCC_CFGR_PLLSRC_HSI_DIV2)
180#define IS_RCC_HSE_PREDIV(DIV) (((DIV) == RCC_HSE_PREDIV_DIV1) || ((DIV) == RCC_HSE_PREDIV_DIV2) || \
181 ((DIV) == RCC_HSE_PREDIV_DIV3) || ((DIV) == RCC_HSE_PREDIV_DIV4) || \
182 ((DIV) == RCC_HSE_PREDIV_DIV5) || ((DIV) == RCC_HSE_PREDIV_DIV6) || \
183 ((DIV) == RCC_HSE_PREDIV_DIV7) || ((DIV) == RCC_HSE_PREDIV_DIV8) || \
184 ((DIV) == RCC_HSE_PREDIV_DIV9) || ((DIV) == RCC_HSE_PREDIV_DIV10) || \
185 ((DIV) == RCC_HSE_PREDIV_DIV11) || ((DIV) == RCC_HSE_PREDIV_DIV12) || \
186 ((DIV) == RCC_HSE_PREDIV_DIV13) || ((DIV) == RCC_HSE_PREDIV_DIV14) || \
187 ((DIV) == RCC_HSE_PREDIV_DIV15) || ((DIV) == RCC_HSE_PREDIV_DIV16))
188#endif /* RCC_CFGR_PLLSRC_HSI_DIV2 */
189
190#define IS_RCC_PLL_MUL(__MUL__) (((__MUL__) == RCC_PLL_MUL2) || ((__MUL__) == RCC_PLL_MUL3) || \
191 ((__MUL__) == RCC_PLL_MUL4) || ((__MUL__) == RCC_PLL_MUL5) || \
192 ((__MUL__) == RCC_PLL_MUL6) || ((__MUL__) == RCC_PLL_MUL7) || \
193 ((__MUL__) == RCC_PLL_MUL8) || ((__MUL__) == RCC_PLL_MUL9) || \
194 ((__MUL__) == RCC_PLL_MUL10) || ((__MUL__) == RCC_PLL_MUL11) || \
195 ((__MUL__) == RCC_PLL_MUL12) || ((__MUL__) == RCC_PLL_MUL13) || \
196 ((__MUL__) == RCC_PLL_MUL14) || ((__MUL__) == RCC_PLL_MUL15) || \
197 ((__MUL__) == RCC_PLL_MUL16))
198#define IS_RCC_CLOCKTYPE(CLK) ((((CLK) & RCC_CLOCKTYPE_SYSCLK) == RCC_CLOCKTYPE_SYSCLK) || \
199 (((CLK) & RCC_CLOCKTYPE_HCLK) == RCC_CLOCKTYPE_HCLK) || \
200 (((CLK) & RCC_CLOCKTYPE_PCLK1) == RCC_CLOCKTYPE_PCLK1) || \
201 (((CLK) & RCC_CLOCKTYPE_PCLK2) == RCC_CLOCKTYPE_PCLK2))
202#define IS_RCC_SYSCLKSOURCE(__SOURCE__) (((__SOURCE__) == RCC_SYSCLKSOURCE_HSI) || \
203 ((__SOURCE__) == RCC_SYSCLKSOURCE_HSE) || \
204 ((__SOURCE__) == RCC_SYSCLKSOURCE_PLLCLK))
205#define IS_RCC_SYSCLKSOURCE_STATUS(__SOURCE__) (((__SOURCE__) == RCC_SYSCLKSOURCE_STATUS_HSI) || \
206 ((__SOURCE__) == RCC_SYSCLKSOURCE_STATUS_HSE) || \
207 ((__SOURCE__) == RCC_SYSCLKSOURCE_STATUS_PLLCLK))
208#define IS_RCC_HCLK(__HCLK__) (((__HCLK__) == RCC_SYSCLK_DIV1) || ((__HCLK__) == RCC_SYSCLK_DIV2) || \
209 ((__HCLK__) == RCC_SYSCLK_DIV4) || ((__HCLK__) == RCC_SYSCLK_DIV8) || \
210 ((__HCLK__) == RCC_SYSCLK_DIV16) || ((__HCLK__) == RCC_SYSCLK_DIV64) || \
211 ((__HCLK__) == RCC_SYSCLK_DIV128) || ((__HCLK__) == RCC_SYSCLK_DIV256) || \
212 ((__HCLK__) == RCC_SYSCLK_DIV512))
213#define IS_RCC_PCLK(__PCLK__) (((__PCLK__) == RCC_HCLK_DIV1) || ((__PCLK__) == RCC_HCLK_DIV2) || \
214 ((__PCLK__) == RCC_HCLK_DIV4) || ((__PCLK__) == RCC_HCLK_DIV8) || \
215 ((__PCLK__) == RCC_HCLK_DIV16))
216#define IS_RCC_MCO(__MCO__) ((__MCO__) == RCC_MCO)
217#define IS_RCC_RTCCLKSOURCE(__SOURCE__) (((__SOURCE__) == RCC_RTCCLKSOURCE_NO_CLK) || \
218 ((__SOURCE__) == RCC_RTCCLKSOURCE_LSE) || \
219 ((__SOURCE__) == RCC_RTCCLKSOURCE_LSI) || \
220 ((__SOURCE__) == RCC_RTCCLKSOURCE_HSE_DIV32))
221#if defined(RCC_CFGR3_USART2SW)
222#define IS_RCC_USART2CLKSOURCE(__SOURCE__) (((__SOURCE__) == RCC_USART2CLKSOURCE_PCLK1) || \
223 ((__SOURCE__) == RCC_USART2CLKSOURCE_SYSCLK) || \
224 ((__SOURCE__) == RCC_USART2CLKSOURCE_LSE) || \
225 ((__SOURCE__) == RCC_USART2CLKSOURCE_HSI))
226#endif /* RCC_CFGR3_USART2SW */
227#if defined(RCC_CFGR3_USART3SW)
228#define IS_RCC_USART3CLKSOURCE(__SOURCE__) (((__SOURCE__) == RCC_USART3CLKSOURCE_PCLK1) || \
229 ((__SOURCE__) == RCC_USART3CLKSOURCE_SYSCLK) || \
230 ((__SOURCE__) == RCC_USART3CLKSOURCE_LSE) || \
231 ((__SOURCE__) == RCC_USART3CLKSOURCE_HSI))
232#endif /* RCC_CFGR3_USART3SW */
233#define IS_RCC_I2C1CLKSOURCE(__SOURCE__) (((__SOURCE__) == RCC_I2C1CLKSOURCE_HSI) || \
234 ((__SOURCE__) == RCC_I2C1CLKSOURCE_SYSCLK))
235
240/* Exported types ------------------------------------------------------------*/
241
249typedef struct
250{
251 uint32_t PLLState;
254 uint32_t PLLSource;
257 uint32_t PLLMUL;
260#if defined(RCC_CFGR_PLLSRC_HSI_PREDIV)
261 uint32_t PREDIV;
264#endif
265} RCC_PLLInitTypeDef;
266
270typedef struct
271{
272 uint32_t OscillatorType;
275 uint32_t HSEState;
278#if defined(RCC_CFGR_PLLSRC_HSI_DIV2)
279 uint32_t HSEPredivValue;
282#endif /* RCC_CFGR_PLLSRC_HSI_DIV2 */
283 uint32_t LSEState;
286 uint32_t HSIState;
289 uint32_t HSICalibrationValue;
292 uint32_t LSIState;
295 RCC_PLLInitTypeDef PLL;
297} RCC_OscInitTypeDef;
298
302typedef struct
303{
304 uint32_t ClockType;
307 uint32_t SYSCLKSource;
310 uint32_t AHBCLKDivider;
313 uint32_t APB1CLKDivider;
316 uint32_t APB2CLKDivider;
318} RCC_ClkInitTypeDef;
319
324/* Exported constants --------------------------------------------------------*/
333#if defined(RCC_CFGR_PLLSRC_HSI_PREDIV)
334#define RCC_PLLSOURCE_HSI RCC_CFGR_PLLSRC_HSI_PREDIV
335#endif /* RCC_CFGR_PLLSRC_HSI_PREDIV */
336#if defined(RCC_CFGR_PLLSRC_HSI_DIV2)
337#define RCC_PLLSOURCE_HSI RCC_CFGR_PLLSRC_HSI_DIV2
338#endif /* RCC_CFGR_PLLSRC_HSI_DIV2 */
339#define RCC_PLLSOURCE_HSE RCC_CFGR_PLLSRC_HSE_PREDIV
348#define RCC_OSCILLATORTYPE_NONE (0x00000000U)
349#define RCC_OSCILLATORTYPE_HSE (0x00000001U)
350#define RCC_OSCILLATORTYPE_HSI (0x00000002U)
351#define RCC_OSCILLATORTYPE_LSE (0x00000004U)
352#define RCC_OSCILLATORTYPE_LSI (0x00000008U)
360#define RCC_HSE_OFF (0x00000000U)
361#define RCC_HSE_ON RCC_CR_HSEON
362#define RCC_HSE_BYPASS ((uint32_t)(RCC_CR_HSEBYP | RCC_CR_HSEON))
370#define RCC_LSE_OFF (0x00000000U)
371#define RCC_LSE_ON RCC_BDCR_LSEON
372#define RCC_LSE_BYPASS ((uint32_t)(RCC_BDCR_LSEBYP | RCC_BDCR_LSEON))
381#define RCC_HSI_OFF (0x00000000U)
382#define RCC_HSI_ON RCC_CR_HSION
384#define RCC_HSICALIBRATION_DEFAULT (0x10U) /* Default HSI calibration trimming value */
385
393#define RCC_LSI_OFF (0x00000000U)
394#define RCC_LSI_ON RCC_CSR_LSION
403#define RCC_PLL_NONE (0x00000000U)
404#define RCC_PLL_OFF (0x00000001U)
405#define RCC_PLL_ON (0x00000002U)
414#define RCC_CLOCKTYPE_SYSCLK (0x00000001U)
415#define RCC_CLOCKTYPE_HCLK (0x00000002U)
416#define RCC_CLOCKTYPE_PCLK1 (0x00000004U)
417#define RCC_CLOCKTYPE_PCLK2 (0x00000008U)
426#define RCC_SYSCLKSOURCE_HSI RCC_CFGR_SW_HSI
427#define RCC_SYSCLKSOURCE_HSE RCC_CFGR_SW_HSE
428#define RCC_SYSCLKSOURCE_PLLCLK RCC_CFGR_SW_PLL
437#define RCC_SYSCLKSOURCE_STATUS_HSI RCC_CFGR_SWS_HSI
438#define RCC_SYSCLKSOURCE_STATUS_HSE RCC_CFGR_SWS_HSE
439#define RCC_SYSCLKSOURCE_STATUS_PLLCLK RCC_CFGR_SWS_PLL
448#define RCC_SYSCLK_DIV1 RCC_CFGR_HPRE_DIV1
449#define RCC_SYSCLK_DIV2 RCC_CFGR_HPRE_DIV2
450#define RCC_SYSCLK_DIV4 RCC_CFGR_HPRE_DIV4
451#define RCC_SYSCLK_DIV8 RCC_CFGR_HPRE_DIV8
452#define RCC_SYSCLK_DIV16 RCC_CFGR_HPRE_DIV16
453#define RCC_SYSCLK_DIV64 RCC_CFGR_HPRE_DIV64
454#define RCC_SYSCLK_DIV128 RCC_CFGR_HPRE_DIV128
455#define RCC_SYSCLK_DIV256 RCC_CFGR_HPRE_DIV256
456#define RCC_SYSCLK_DIV512 RCC_CFGR_HPRE_DIV512
465#define RCC_HCLK_DIV1 RCC_CFGR_PPRE1_DIV1
466#define RCC_HCLK_DIV2 RCC_CFGR_PPRE1_DIV2
467#define RCC_HCLK_DIV4 RCC_CFGR_PPRE1_DIV4
468#define RCC_HCLK_DIV8 RCC_CFGR_PPRE1_DIV8
469#define RCC_HCLK_DIV16 RCC_CFGR_PPRE1_DIV16
478#define RCC_RTCCLKSOURCE_NO_CLK RCC_BDCR_RTCSEL_NOCLOCK
479#define RCC_RTCCLKSOURCE_LSE RCC_BDCR_RTCSEL_LSE
480#define RCC_RTCCLKSOURCE_LSI RCC_BDCR_RTCSEL_LSI
481#define RCC_RTCCLKSOURCE_HSE_DIV32 RCC_BDCR_RTCSEL_HSE
489#define RCC_PLL_MUL2 RCC_CFGR_PLLMUL2
490#define RCC_PLL_MUL3 RCC_CFGR_PLLMUL3
491#define RCC_PLL_MUL4 RCC_CFGR_PLLMUL4
492#define RCC_PLL_MUL5 RCC_CFGR_PLLMUL5
493#define RCC_PLL_MUL6 RCC_CFGR_PLLMUL6
494#define RCC_PLL_MUL7 RCC_CFGR_PLLMUL7
495#define RCC_PLL_MUL8 RCC_CFGR_PLLMUL8
496#define RCC_PLL_MUL9 RCC_CFGR_PLLMUL9
497#define RCC_PLL_MUL10 RCC_CFGR_PLLMUL10
498#define RCC_PLL_MUL11 RCC_CFGR_PLLMUL11
499#define RCC_PLL_MUL12 RCC_CFGR_PLLMUL12
500#define RCC_PLL_MUL13 RCC_CFGR_PLLMUL13
501#define RCC_PLL_MUL14 RCC_CFGR_PLLMUL14
502#define RCC_PLL_MUL15 RCC_CFGR_PLLMUL15
503#define RCC_PLL_MUL16 RCC_CFGR_PLLMUL16
504
509#if defined(RCC_CFGR_PLLSRC_HSI_PREDIV)
514#define RCC_PREDIV_DIV1 RCC_CFGR2_PREDIV_DIV1
515#define RCC_PREDIV_DIV2 RCC_CFGR2_PREDIV_DIV2
516#define RCC_PREDIV_DIV3 RCC_CFGR2_PREDIV_DIV3
517#define RCC_PREDIV_DIV4 RCC_CFGR2_PREDIV_DIV4
518#define RCC_PREDIV_DIV5 RCC_CFGR2_PREDIV_DIV5
519#define RCC_PREDIV_DIV6 RCC_CFGR2_PREDIV_DIV6
520#define RCC_PREDIV_DIV7 RCC_CFGR2_PREDIV_DIV7
521#define RCC_PREDIV_DIV8 RCC_CFGR2_PREDIV_DIV8
522#define RCC_PREDIV_DIV9 RCC_CFGR2_PREDIV_DIV9
523#define RCC_PREDIV_DIV10 RCC_CFGR2_PREDIV_DIV10
524#define RCC_PREDIV_DIV11 RCC_CFGR2_PREDIV_DIV11
525#define RCC_PREDIV_DIV12 RCC_CFGR2_PREDIV_DIV12
526#define RCC_PREDIV_DIV13 RCC_CFGR2_PREDIV_DIV13
527#define RCC_PREDIV_DIV14 RCC_CFGR2_PREDIV_DIV14
528#define RCC_PREDIV_DIV15 RCC_CFGR2_PREDIV_DIV15
529#define RCC_PREDIV_DIV16 RCC_CFGR2_PREDIV_DIV16
530
535#endif
536#if defined(RCC_CFGR_PLLSRC_HSI_DIV2)
541#define RCC_HSE_PREDIV_DIV1 RCC_CFGR2_PREDIV_DIV1
542#define RCC_HSE_PREDIV_DIV2 RCC_CFGR2_PREDIV_DIV2
543#define RCC_HSE_PREDIV_DIV3 RCC_CFGR2_PREDIV_DIV3
544#define RCC_HSE_PREDIV_DIV4 RCC_CFGR2_PREDIV_DIV4
545#define RCC_HSE_PREDIV_DIV5 RCC_CFGR2_PREDIV_DIV5
546#define RCC_HSE_PREDIV_DIV6 RCC_CFGR2_PREDIV_DIV6
547#define RCC_HSE_PREDIV_DIV7 RCC_CFGR2_PREDIV_DIV7
548#define RCC_HSE_PREDIV_DIV8 RCC_CFGR2_PREDIV_DIV8
549#define RCC_HSE_PREDIV_DIV9 RCC_CFGR2_PREDIV_DIV9
550#define RCC_HSE_PREDIV_DIV10 RCC_CFGR2_PREDIV_DIV10
551#define RCC_HSE_PREDIV_DIV11 RCC_CFGR2_PREDIV_DIV11
552#define RCC_HSE_PREDIV_DIV12 RCC_CFGR2_PREDIV_DIV12
553#define RCC_HSE_PREDIV_DIV13 RCC_CFGR2_PREDIV_DIV13
554#define RCC_HSE_PREDIV_DIV14 RCC_CFGR2_PREDIV_DIV14
555#define RCC_HSE_PREDIV_DIV15 RCC_CFGR2_PREDIV_DIV15
556#define RCC_HSE_PREDIV_DIV16 RCC_CFGR2_PREDIV_DIV16
557
561#endif /* RCC_CFGR_PLLSRC_HSI_DIV2 */
562
563#if defined(RCC_CFGR3_USART2SW)
567#define RCC_USART2CLKSOURCE_PCLK1 RCC_CFGR3_USART2SW_PCLK
568#define RCC_USART2CLKSOURCE_SYSCLK RCC_CFGR3_USART2SW_SYSCLK
569#define RCC_USART2CLKSOURCE_LSE RCC_CFGR3_USART2SW_LSE
570#define RCC_USART2CLKSOURCE_HSI RCC_CFGR3_USART2SW_HSI
571
575#endif /* RCC_CFGR3_USART2SW */
576
577#if defined(RCC_CFGR3_USART3SW)
581#define RCC_USART3CLKSOURCE_PCLK1 RCC_CFGR3_USART3SW_PCLK
582#define RCC_USART3CLKSOURCE_SYSCLK RCC_CFGR3_USART3SW_SYSCLK
583#define RCC_USART3CLKSOURCE_LSE RCC_CFGR3_USART3SW_LSE
584#define RCC_USART3CLKSOURCE_HSI RCC_CFGR3_USART3SW_HSI
585
589#endif /* RCC_CFGR3_USART3SW */
590
594#define RCC_I2C1CLKSOURCE_HSI RCC_CFGR3_I2C1SW_HSI
595#define RCC_I2C1CLKSOURCE_SYSCLK RCC_CFGR3_I2C1SW_SYSCLK
596
603#define RCC_MCO1 (0x00000000U)
604#define RCC_MCO RCC_MCO1
613#define RCC_IT_LSIRDY ((uint8_t)RCC_CIR_LSIRDYF)
614#define RCC_IT_LSERDY ((uint8_t)RCC_CIR_LSERDYF)
615#define RCC_IT_HSIRDY ((uint8_t)RCC_CIR_HSIRDYF)
616#define RCC_IT_HSERDY ((uint8_t)RCC_CIR_HSERDYF)
617#define RCC_IT_PLLRDY ((uint8_t)RCC_CIR_PLLRDYF)
618#define RCC_IT_CSS ((uint8_t)RCC_CIR_CSSF)
633/* Flags in the CR register */
634#define RCC_FLAG_HSIRDY ((uint8_t)((CR_REG_INDEX << 5U) | POSITION_VAL(RCC_CR_HSIRDY)))
635#define RCC_FLAG_HSERDY ((uint8_t)((CR_REG_INDEX << 5U) | POSITION_VAL(RCC_CR_HSERDY)))
636#define RCC_FLAG_PLLRDY ((uint8_t)((CR_REG_INDEX << 5U) | POSITION_VAL(RCC_CR_PLLRDY)))
638/* Flags in the CSR register */
639#define RCC_FLAG_LSIRDY ((uint8_t)((CSR_REG_INDEX << 5U) | POSITION_VAL(RCC_CSR_LSIRDY)))
640#if defined(RCC_CSR_V18PWRRSTF)
641#define RCC_FLAG_V18PWRRST ((uint8_t)((CSR_REG_INDEX << 5U) | POSITION_VAL(RCC_CSR_V18PWRRSTF)))
642#endif
643#define RCC_FLAG_OBLRST ((uint8_t)((CSR_REG_INDEX << 5U) | POSITION_VAL(RCC_CSR_OBLRSTF)))
644#define RCC_FLAG_PINRST ((uint8_t)((CSR_REG_INDEX << 5U) | POSITION_VAL(RCC_CSR_PINRSTF)))
645#define RCC_FLAG_PORRST ((uint8_t)((CSR_REG_INDEX << 5U) | POSITION_VAL(RCC_CSR_PORRSTF)))
646#define RCC_FLAG_SFTRST ((uint8_t)((CSR_REG_INDEX << 5U) | POSITION_VAL(RCC_CSR_SFTRSTF)))
647#define RCC_FLAG_IWDGRST ((uint8_t)((CSR_REG_INDEX << 5U) | POSITION_VAL(RCC_CSR_IWDGRSTF)))
648#define RCC_FLAG_WWDGRST ((uint8_t)((CSR_REG_INDEX << 5U) | POSITION_VAL(RCC_CSR_WWDGRSTF)))
649#define RCC_FLAG_LPWRRST ((uint8_t)((CSR_REG_INDEX << 5U) | POSITION_VAL(RCC_CSR_LPWRRSTF)))
651/* Flags in the BDCR register */
652#define RCC_FLAG_LSERDY ((uint8_t)((BDCR_REG_INDEX << 5U) | POSITION_VAL(RCC_BDCR_LSERDY)))
654/* Flags in the CFGR register */
655#if defined(RCC_CFGR_MCOF)
656#define RCC_FLAG_MCO ((uint8_t)((CFGR_REG_INDEX << 5U) | POSITION_VAL(RCC_CFGR_MCOF)))
657#endif /* RCC_CFGR_MCOF */
658
667/* Exported macro ------------------------------------------------------------*/
668
680#define __HAL_RCC_GPIOA_CLK_ENABLE() do { \
681 __IO uint32_t tmpreg; \
682 SET_BIT(RCC->AHBENR, RCC_AHBENR_GPIOAEN);\
683 /* Delay after an RCC peripheral clock enabling */ \
684 tmpreg = READ_BIT(RCC->AHBENR, RCC_AHBENR_GPIOAEN);\
685 UNUSED(tmpreg); \
686 } while(0U)
687#define __HAL_RCC_GPIOB_CLK_ENABLE() do { \
688 __IO uint32_t tmpreg; \
689 SET_BIT(RCC->AHBENR, RCC_AHBENR_GPIOBEN);\
690 /* Delay after an RCC peripheral clock enabling */ \
691 tmpreg = READ_BIT(RCC->AHBENR, RCC_AHBENR_GPIOBEN);\
692 UNUSED(tmpreg); \
693 } while(0U)
694#define __HAL_RCC_GPIOC_CLK_ENABLE() do { \
695 __IO uint32_t tmpreg; \
696 SET_BIT(RCC->AHBENR, RCC_AHBENR_GPIOCEN);\
697 /* Delay after an RCC peripheral clock enabling */ \
698 tmpreg = READ_BIT(RCC->AHBENR, RCC_AHBENR_GPIOCEN);\
699 UNUSED(tmpreg); \
700 } while(0U)
701#define __HAL_RCC_GPIOD_CLK_ENABLE() do { \
702 __IO uint32_t tmpreg; \
703 SET_BIT(RCC->AHBENR, RCC_AHBENR_GPIODEN);\
704 /* Delay after an RCC peripheral clock enabling */ \
705 tmpreg = READ_BIT(RCC->AHBENR, RCC_AHBENR_GPIODEN);\
706 UNUSED(tmpreg); \
707 } while(0U)
708#define __HAL_RCC_GPIOF_CLK_ENABLE() do { \
709 __IO uint32_t tmpreg; \
710 SET_BIT(RCC->AHBENR, RCC_AHBENR_GPIOFEN);\
711 /* Delay after an RCC peripheral clock enabling */ \
712 tmpreg = READ_BIT(RCC->AHBENR, RCC_AHBENR_GPIOFEN);\
713 UNUSED(tmpreg); \
714 } while(0U)
715#define __HAL_RCC_CRC_CLK_ENABLE() do { \
716 __IO uint32_t tmpreg; \
717 SET_BIT(RCC->AHBENR, RCC_AHBENR_CRCEN);\
718 /* Delay after an RCC peripheral clock enabling */ \
719 tmpreg = READ_BIT(RCC->AHBENR, RCC_AHBENR_CRCEN);\
720 UNUSED(tmpreg); \
721 } while(0U)
722#define __HAL_RCC_DMA1_CLK_ENABLE() do { \
723 __IO uint32_t tmpreg; \
724 SET_BIT(RCC->AHBENR, RCC_AHBENR_DMA1EN);\
725 /* Delay after an RCC peripheral clock enabling */ \
726 tmpreg = READ_BIT(RCC->AHBENR, RCC_AHBENR_DMA1EN);\
727 UNUSED(tmpreg); \
728 } while(0U)
729#define __HAL_RCC_SRAM_CLK_ENABLE() do { \
730 __IO uint32_t tmpreg; \
731 SET_BIT(RCC->AHBENR, RCC_AHBENR_SRAMEN);\
732 /* Delay after an RCC peripheral clock enabling */ \
733 tmpreg = READ_BIT(RCC->AHBENR, RCC_AHBENR_SRAMEN);\
734 UNUSED(tmpreg); \
735 } while(0U)
736#define __HAL_RCC_FLITF_CLK_ENABLE() do { \
737 __IO uint32_t tmpreg; \
738 SET_BIT(RCC->AHBENR, RCC_AHBENR_FLITFEN);\
739 /* Delay after an RCC peripheral clock enabling */ \
740 tmpreg = READ_BIT(RCC->AHBENR, RCC_AHBENR_FLITFEN);\
741 UNUSED(tmpreg); \
742 } while(0U)
743#define __HAL_RCC_TSC_CLK_ENABLE() do { \
744 __IO uint32_t tmpreg; \
745 SET_BIT(RCC->AHBENR, RCC_AHBENR_TSCEN);\
746 /* Delay after an RCC peripheral clock enabling */ \
747 tmpreg = READ_BIT(RCC->AHBENR, RCC_AHBENR_TSCEN);\
748 UNUSED(tmpreg); \
749 } while(0U)
750
751#define __HAL_RCC_GPIOA_CLK_DISABLE() (RCC->AHBENR &= ~(RCC_AHBENR_GPIOAEN))
752#define __HAL_RCC_GPIOB_CLK_DISABLE() (RCC->AHBENR &= ~(RCC_AHBENR_GPIOBEN))
753#define __HAL_RCC_GPIOC_CLK_DISABLE() (RCC->AHBENR &= ~(RCC_AHBENR_GPIOCEN))
754#define __HAL_RCC_GPIOD_CLK_DISABLE() (RCC->AHBENR &= ~(RCC_AHBENR_GPIODEN))
755#define __HAL_RCC_GPIOF_CLK_DISABLE() (RCC->AHBENR &= ~(RCC_AHBENR_GPIOFEN))
756#define __HAL_RCC_CRC_CLK_DISABLE() (RCC->AHBENR &= ~(RCC_AHBENR_CRCEN))
757#define __HAL_RCC_DMA1_CLK_DISABLE() (RCC->AHBENR &= ~(RCC_AHBENR_DMA1EN))
758#define __HAL_RCC_SRAM_CLK_DISABLE() (RCC->AHBENR &= ~(RCC_AHBENR_SRAMEN))
759#define __HAL_RCC_FLITF_CLK_DISABLE() (RCC->AHBENR &= ~(RCC_AHBENR_FLITFEN))
760#define __HAL_RCC_TSC_CLK_DISABLE() (RCC->AHBENR &= ~(RCC_AHBENR_TSCEN))
772#define __HAL_RCC_TIM2_CLK_ENABLE() do { \
773 __IO uint32_t tmpreg; \
774 SET_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM2EN);\
775 /* Delay after an RCC peripheral clock enabling */ \
776 tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM2EN);\
777 UNUSED(tmpreg); \
778 } while(0U)
779#define __HAL_RCC_TIM6_CLK_ENABLE() do { \
780 __IO uint32_t tmpreg; \
781 SET_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM6EN);\
782 /* Delay after an RCC peripheral clock enabling */ \
783 tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM6EN);\
784 UNUSED(tmpreg); \
785 } while(0U)
786#define __HAL_RCC_WWDG_CLK_ENABLE() do { \
787 __IO uint32_t tmpreg; \
788 SET_BIT(RCC->APB1ENR, RCC_APB1ENR_WWDGEN);\
789 /* Delay after an RCC peripheral clock enabling */ \
790 tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_WWDGEN);\
791 UNUSED(tmpreg); \
792 } while(0U)
793#define __HAL_RCC_USART2_CLK_ENABLE() do { \
794 __IO uint32_t tmpreg; \
795 SET_BIT(RCC->APB1ENR, RCC_APB1ENR_USART2EN);\
796 /* Delay after an RCC peripheral clock enabling */ \
797 tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_USART2EN);\
798 UNUSED(tmpreg); \
799 } while(0U)
800#define __HAL_RCC_USART3_CLK_ENABLE() do { \
801 __IO uint32_t tmpreg; \
802 SET_BIT(RCC->APB1ENR, RCC_APB1ENR_USART3EN);\
803 /* Delay after an RCC peripheral clock enabling */ \
804 tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_USART3EN);\
805 UNUSED(tmpreg); \
806 } while(0U)
807#define __HAL_RCC_I2C1_CLK_ENABLE() do { \
808 __IO uint32_t tmpreg; \
809 SET_BIT(RCC->APB1ENR, RCC_APB1ENR_I2C1EN);\
810 /* Delay after an RCC peripheral clock enabling */ \
811 tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_I2C1EN);\
812 UNUSED(tmpreg); \
813 } while(0U)
814#define __HAL_RCC_PWR_CLK_ENABLE() do { \
815 __IO uint32_t tmpreg; \
816 SET_BIT(RCC->APB1ENR, RCC_APB1ENR_PWREN);\
817 /* Delay after an RCC peripheral clock enabling */ \
818 tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_PWREN);\
819 UNUSED(tmpreg); \
820 } while(0U)
821#define __HAL_RCC_DAC1_CLK_ENABLE() do { \
822 __IO uint32_t tmpreg; \
823 SET_BIT(RCC->APB1ENR, RCC_APB1ENR_DAC1EN);\
824 /* Delay after an RCC peripheral clock enabling */ \
825 tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_DAC1EN);\
826 UNUSED(tmpreg); \
827 } while(0U)
828
829#define __HAL_RCC_TIM2_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM2EN))
830#define __HAL_RCC_TIM6_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM6EN))
831#define __HAL_RCC_WWDG_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_WWDGEN))
832#define __HAL_RCC_USART2_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_USART2EN))
833#define __HAL_RCC_USART3_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_USART3EN))
834#define __HAL_RCC_I2C1_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_I2C1EN))
835#define __HAL_RCC_PWR_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_PWREN))
836#define __HAL_RCC_DAC1_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_DAC1EN))
848#define __HAL_RCC_SYSCFG_CLK_ENABLE() do { \
849 __IO uint32_t tmpreg; \
850 SET_BIT(RCC->APB2ENR, RCC_APB2ENR_SYSCFGEN);\
851 /* Delay after an RCC peripheral clock enabling */ \
852 tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_SYSCFGEN);\
853 UNUSED(tmpreg); \
854 } while(0U)
855#define __HAL_RCC_TIM15_CLK_ENABLE() do { \
856 __IO uint32_t tmpreg; \
857 SET_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM15EN);\
858 /* Delay after an RCC peripheral clock enabling */ \
859 tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM15EN);\
860 UNUSED(tmpreg); \
861 } while(0U)
862#define __HAL_RCC_TIM16_CLK_ENABLE() do { \
863 __IO uint32_t tmpreg; \
864 SET_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM16EN);\
865 /* Delay after an RCC peripheral clock enabling */ \
866 tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM16EN);\
867 UNUSED(tmpreg); \
868 } while(0U)
869#define __HAL_RCC_TIM17_CLK_ENABLE() do { \
870 __IO uint32_t tmpreg; \
871 SET_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM17EN);\
872 /* Delay after an RCC peripheral clock enabling */ \
873 tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM17EN);\
874 UNUSED(tmpreg); \
875 } while(0U)
876#define __HAL_RCC_USART1_CLK_ENABLE() do { \
877 __IO uint32_t tmpreg; \
878 SET_BIT(RCC->APB2ENR, RCC_APB2ENR_USART1EN);\
879 /* Delay after an RCC peripheral clock enabling */ \
880 tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_USART1EN);\
881 UNUSED(tmpreg); \
882 } while(0U)
883
884#define __HAL_RCC_SYSCFG_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_SYSCFGEN))
885#define __HAL_RCC_TIM15_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_TIM15EN))
886#define __HAL_RCC_TIM16_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_TIM16EN))
887#define __HAL_RCC_TIM17_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_TIM17EN))
888#define __HAL_RCC_USART1_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_USART1EN))
900#define __HAL_RCC_GPIOA_IS_CLK_ENABLED() ((RCC->AHBENR & (RCC_AHBENR_GPIOAEN)) != RESET)
901#define __HAL_RCC_GPIOB_IS_CLK_ENABLED() ((RCC->AHBENR & (RCC_AHBENR_GPIOBEN)) != RESET)
902#define __HAL_RCC_GPIOC_IS_CLK_ENABLED() ((RCC->AHBENR & (RCC_AHBENR_GPIOCEN)) != RESET)
903#define __HAL_RCC_GPIOD_IS_CLK_ENABLED() ((RCC->AHBENR & (RCC_AHBENR_GPIODEN)) != RESET)
904#define __HAL_RCC_GPIOF_IS_CLK_ENABLED() ((RCC->AHBENR & (RCC_AHBENR_GPIOFEN)) != RESET)
905#define __HAL_RCC_CRC_IS_CLK_ENABLED() ((RCC->AHBENR & (RCC_AHBENR_CRCEN)) != RESET)
906#define __HAL_RCC_DMA1_IS_CLK_ENABLED() ((RCC->AHBENR & (RCC_AHBENR_DMA1EN)) != RESET)
907#define __HAL_RCC_SRAM_IS_CLK_ENABLED() ((RCC->AHBENR & (RCC_AHBENR_SRAMEN)) != RESET)
908#define __HAL_RCC_FLITF_IS_CLK_ENABLED() ((RCC->AHBENR & (RCC_AHBENR_FLITFEN)) != RESET)
909#define __HAL_RCC_TSC_IS_CLK_ENABLED() ((RCC->AHBENR & (RCC_AHBENR_TSCEN)) != RESET)
910
911#define __HAL_RCC_GPIOA_IS_CLK_DISABLED() ((RCC->AHBENR & (RCC_AHBENR_GPIOAEN)) == RESET)
912#define __HAL_RCC_GPIOB_IS_CLK_DISABLED() ((RCC->AHBENR & (RCC_AHBENR_GPIOBEN)) == RESET)
913#define __HAL_RCC_GPIOC_IS_CLK_DISABLED() ((RCC->AHBENR & (RCC_AHBENR_GPIOCEN)) == RESET)
914#define __HAL_RCC_GPIOD_IS_CLK_DISABLED() ((RCC->AHBENR & (RCC_AHBENR_GPIODEN)) == RESET)
915#define __HAL_RCC_GPIOF_IS_CLK_DISABLED() ((RCC->AHBENR & (RCC_AHBENR_GPIOFEN)) == RESET)
916#define __HAL_RCC_CRC_IS_CLK_DISABLED() ((RCC->AHBENR & (RCC_AHBENR_CRCEN)) == RESET)
917#define __HAL_RCC_DMA1_IS_CLK_DISABLED() ((RCC->AHBENR & (RCC_AHBENR_DMA1EN)) == RESET)
918#define __HAL_RCC_SRAM_IS_CLK_DISABLED() ((RCC->AHBENR & (RCC_AHBENR_SRAMEN)) == RESET)
919#define __HAL_RCC_FLITF_IS_CLK_DISABLED() ((RCC->AHBENR & (RCC_AHBENR_FLITFEN)) == RESET)
920#define __HAL_RCC_TSC_IS_CLK_DISABLED() ((RCC->AHBENR & (RCC_AHBENR_TSCEN)) == RESET)
932#define __HAL_RCC_TIM2_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM2EN)) != RESET)
933#define __HAL_RCC_TIM6_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM6EN)) != RESET)
934#define __HAL_RCC_WWDG_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_WWDGEN)) != RESET)
935#define __HAL_RCC_USART2_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_USART2EN)) != RESET)
936#define __HAL_RCC_USART3_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_USART3EN)) != RESET)
937#define __HAL_RCC_I2C1_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_I2C1EN)) != RESET)
938#define __HAL_RCC_PWR_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_PWREN)) != RESET)
939#define __HAL_RCC_DAC1_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_DAC1EN)) != RESET)
940
941#define __HAL_RCC_TIM2_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM2EN)) == RESET)
942#define __HAL_RCC_TIM6_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM6EN)) == RESET)
943#define __HAL_RCC_WWDG_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_WWDGEN)) == RESET)
944#define __HAL_RCC_USART2_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_USART2EN)) == RESET)
945#define __HAL_RCC_USART3_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_USART3EN)) == RESET)
946#define __HAL_RCC_I2C1_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_I2C1EN)) == RESET)
947#define __HAL_RCC_PWR_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_PWREN)) == RESET)
948#define __HAL_RCC_DAC1_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_DAC1EN)) == RESET)
960#define __HAL_RCC_SYSCFG_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_SYSCFGEN)) != RESET)
961#define __HAL_RCC_TIM15_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_TIM15EN)) != RESET)
962#define __HAL_RCC_TIM16_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_TIM16EN)) != RESET)
963#define __HAL_RCC_TIM17_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_TIM17EN)) != RESET)
964#define __HAL_RCC_USART1_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_USART1EN)) != RESET)
965
966#define __HAL_RCC_SYSCFG_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_SYSCFGEN)) == RESET)
967#define __HAL_RCC_TIM15_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_TIM15EN)) == RESET)
968#define __HAL_RCC_TIM16_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_TIM16EN)) == RESET)
969#define __HAL_RCC_TIM17_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_TIM17EN)) == RESET)
970#define __HAL_RCC_USART1_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_USART1EN)) == RESET)
979#define __HAL_RCC_AHB_FORCE_RESET() (RCC->AHBRSTR = 0xFFFFFFFFU)
980#define __HAL_RCC_GPIOA_FORCE_RESET() (RCC->AHBRSTR |= (RCC_AHBRSTR_GPIOARST))
981#define __HAL_RCC_GPIOB_FORCE_RESET() (RCC->AHBRSTR |= (RCC_AHBRSTR_GPIOBRST))
982#define __HAL_RCC_GPIOC_FORCE_RESET() (RCC->AHBRSTR |= (RCC_AHBRSTR_GPIOCRST))
983#define __HAL_RCC_GPIOD_FORCE_RESET() (RCC->AHBRSTR |= (RCC_AHBRSTR_GPIODRST))
984#define __HAL_RCC_GPIOF_FORCE_RESET() (RCC->AHBRSTR |= (RCC_AHBRSTR_GPIOFRST))
985#define __HAL_RCC_TSC_FORCE_RESET() (RCC->AHBRSTR |= (RCC_AHBRSTR_TSCRST))
986
987#define __HAL_RCC_AHB_RELEASE_RESET() (RCC->AHBRSTR = 0x00000000U)
988#define __HAL_RCC_GPIOA_RELEASE_RESET() (RCC->AHBRSTR &= ~(RCC_AHBRSTR_GPIOARST))
989#define __HAL_RCC_GPIOB_RELEASE_RESET() (RCC->AHBRSTR &= ~(RCC_AHBRSTR_GPIOBRST))
990#define __HAL_RCC_GPIOC_RELEASE_RESET() (RCC->AHBRSTR &= ~(RCC_AHBRSTR_GPIOCRST))
991#define __HAL_RCC_GPIOD_RELEASE_RESET() (RCC->AHBRSTR &= ~(RCC_AHBRSTR_GPIODRST))
992#define __HAL_RCC_GPIOF_RELEASE_RESET() (RCC->AHBRSTR &= ~(RCC_AHBRSTR_GPIOFRST))
993#define __HAL_RCC_TSC_RELEASE_RESET() (RCC->AHBRSTR &= ~(RCC_AHBRSTR_TSCRST))
1002#define __HAL_RCC_APB1_FORCE_RESET() (RCC->APB1RSTR = 0xFFFFFFFFU)
1003#define __HAL_RCC_TIM2_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_TIM2RST))
1004#define __HAL_RCC_TIM6_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_TIM6RST))
1005#define __HAL_RCC_WWDG_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_WWDGRST))
1006#define __HAL_RCC_USART2_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_USART2RST))
1007#define __HAL_RCC_USART3_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_USART3RST))
1008#define __HAL_RCC_I2C1_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_I2C1RST))
1009#define __HAL_RCC_PWR_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_PWRRST))
1010#define __HAL_RCC_DAC1_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_DAC1RST))
1011
1012#define __HAL_RCC_APB1_RELEASE_RESET() (RCC->APB1RSTR = 0x00000000U)
1013#define __HAL_RCC_TIM2_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM2RST))
1014#define __HAL_RCC_TIM6_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM6RST))
1015#define __HAL_RCC_WWDG_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_WWDGRST))
1016#define __HAL_RCC_USART2_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_USART2RST))
1017#define __HAL_RCC_USART3_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_USART3RST))
1018#define __HAL_RCC_I2C1_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_I2C1RST))
1019#define __HAL_RCC_PWR_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_PWRRST))
1020#define __HAL_RCC_DAC1_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_DAC1RST))
1029#define __HAL_RCC_APB2_FORCE_RESET() (RCC->APB2RSTR = 0xFFFFFFFFU)
1030#define __HAL_RCC_SYSCFG_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_SYSCFGRST))
1031#define __HAL_RCC_TIM15_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_TIM15RST))
1032#define __HAL_RCC_TIM16_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_TIM16RST))
1033#define __HAL_RCC_TIM17_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_TIM17RST))
1034#define __HAL_RCC_USART1_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_USART1RST))
1035
1036#define __HAL_RCC_APB2_RELEASE_RESET() (RCC->APB2RSTR = 0x00000000U)
1037#define __HAL_RCC_SYSCFG_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_SYSCFGRST))
1038#define __HAL_RCC_TIM15_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_TIM15RST))
1039#define __HAL_RCC_TIM16_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_TIM16RST))
1040#define __HAL_RCC_TIM17_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_TIM17RST))
1041#define __HAL_RCC_USART1_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_USART1RST))
1064#define __HAL_RCC_HSI_ENABLE() (*(__IO uint32_t *) RCC_CR_HSION_BB = ENABLE)
1065#define __HAL_RCC_HSI_DISABLE() (*(__IO uint32_t *) RCC_CR_HSION_BB = DISABLE)
1066
1074#define __HAL_RCC_HSI_CALIBRATIONVALUE_ADJUST(_HSICALIBRATIONVALUE_) \
1075 (MODIFY_REG(RCC->CR, RCC_CR_HSITRIM, (uint32_t)(_HSICALIBRATIONVALUE_) << POSITION_VAL(RCC_CR_HSITRIM)))
1076
1090#define __HAL_RCC_LSI_ENABLE() (*(__IO uint32_t *) RCC_CSR_LSION_BB = ENABLE)
1091
1097#define __HAL_RCC_LSI_DISABLE() (*(__IO uint32_t *) RCC_CSR_LSION_BB = DISABLE)
1098
1129#define __HAL_RCC_HSE_CONFIG(__STATE__) \
1130 do{ \
1131 if ((__STATE__) == RCC_HSE_ON) \
1132 { \
1133 SET_BIT(RCC->CR, RCC_CR_HSEON); \
1134 } \
1135 else if ((__STATE__) == RCC_HSE_OFF) \
1136 { \
1137 CLEAR_BIT(RCC->CR, RCC_CR_HSEON); \
1138 CLEAR_BIT(RCC->CR, RCC_CR_HSEBYP); \
1139 } \
1140 else if ((__STATE__) == RCC_HSE_BYPASS) \
1141 { \
1142 SET_BIT(RCC->CR, RCC_CR_HSEBYP); \
1143 SET_BIT(RCC->CR, RCC_CR_HSEON); \
1144 } \
1145 else \
1146 { \
1147 CLEAR_BIT(RCC->CR, RCC_CR_HSEON); \
1148 CLEAR_BIT(RCC->CR, RCC_CR_HSEBYP); \
1149 } \
1150 }while(0U)
1151
1177#define __HAL_RCC_LSE_CONFIG(__STATE__) \
1178 do{ \
1179 if ((__STATE__) == RCC_LSE_ON) \
1180 { \
1181 SET_BIT(RCC->BDCR, RCC_BDCR_LSEON); \
1182 } \
1183 else if ((__STATE__) == RCC_LSE_OFF) \
1184 { \
1185 CLEAR_BIT(RCC->BDCR, RCC_BDCR_LSEON); \
1186 CLEAR_BIT(RCC->BDCR, RCC_BDCR_LSEBYP); \
1187 } \
1188 else if ((__STATE__) == RCC_LSE_BYPASS) \
1189 { \
1190 SET_BIT(RCC->BDCR, RCC_BDCR_LSEBYP); \
1191 SET_BIT(RCC->BDCR, RCC_BDCR_LSEON); \
1192 } \
1193 else \
1194 { \
1195 CLEAR_BIT(RCC->BDCR, RCC_BDCR_LSEON); \
1196 CLEAR_BIT(RCC->BDCR, RCC_BDCR_LSEBYP); \
1197 } \
1198 }while(0U)
1199
1257#define __HAL_RCC_USART1_CONFIG(__USART1CLKSOURCE__) \
1258 MODIFY_REG(RCC->CFGR3, RCC_CFGR3_USART1SW, (uint32_t)(__USART1CLKSOURCE__))
1259
1308#define __HAL_RCC_GET_USART1_SOURCE() ((uint32_t)(READ_BIT(RCC->CFGR3, RCC_CFGR3_USART1SW)))
1309
1310#if defined(RCC_CFGR3_USART2SW)
1319#define __HAL_RCC_USART2_CONFIG(__USART2CLKSOURCE__) \
1320 MODIFY_REG(RCC->CFGR3, RCC_CFGR3_USART2SW, (uint32_t)(__USART2CLKSOURCE__))
1321
1329#define __HAL_RCC_GET_USART2_SOURCE() ((uint32_t)(READ_BIT(RCC->CFGR3, RCC_CFGR3_USART2SW)))
1330#endif /* RCC_CFGR3_USART2SW */
1331
1332#if defined(RCC_CFGR3_USART3SW)
1341#define __HAL_RCC_USART3_CONFIG(__USART3CLKSOURCE__) \
1342 MODIFY_REG(RCC->CFGR3, RCC_CFGR3_USART3SW, (uint32_t)(__USART3CLKSOURCE__))
1343
1351#define __HAL_RCC_GET_USART3_SOURCE() ((uint32_t)(READ_BIT(RCC->CFGR3, RCC_CFGR3_USART3SW)))
1352#endif /* RCC_CFGR3_USART2SW */
1367#define __HAL_RCC_I2C1_CONFIG(__I2C1CLKSOURCE__) \
1368 MODIFY_REG(RCC->CFGR3, RCC_CFGR3_I2C1SW, (uint32_t)(__I2C1CLKSOURCE__))
1369
1375#define __HAL_RCC_GET_I2C1_SOURCE() ((uint32_t)(READ_BIT(RCC->CFGR3, RCC_CFGR3_I2C1SW)))
1390#define __HAL_RCC_PLL_ENABLE() (*(__IO uint32_t *) RCC_CR_PLLON_BB = ENABLE)
1391
1395#define __HAL_RCC_PLL_DISABLE() (*(__IO uint32_t *) RCC_CR_PLLON_BB = DISABLE)
1396
1397
1404#define __HAL_RCC_GET_PLL_OSCSOURCE() ((uint32_t)(READ_BIT(RCC->CFGR, RCC_CFGR_PLLSRC)))
1405
1422#define __HAL_RCC_SYSCLK_CONFIG(__SYSCLKSOURCE__) \
1423 MODIFY_REG(RCC->CFGR, RCC_CFGR_SW, (__SYSCLKSOURCE__))
1424
1432#define __HAL_RCC_GET_SYSCLK_SOURCE() ((uint32_t)(READ_BIT(RCC->CFGR,RCC_CFGR_SWS)))
1433
1442#if defined(RCC_CFGR_MCOPRE)
1464#else
1479#endif
1480#if defined(RCC_CFGR_MCOPRE)
1481#define __HAL_RCC_MCO1_CONFIG(__MCOCLKSOURCE__, __MCODIV__) \
1482 MODIFY_REG(RCC->CFGR, (RCC_CFGR_MCO | RCC_CFGR_MCOPRE), ((__MCOCLKSOURCE__) | (__MCODIV__)))
1483#else
1484
1485#define __HAL_RCC_MCO1_CONFIG(__MCOCLKSOURCE__, __MCODIV__) \
1486 MODIFY_REG(RCC->CFGR, RCC_CFGR_MCO, (__MCOCLKSOURCE__))
1487
1488#endif
1489
1520#define __HAL_RCC_RTC_CONFIG(__RTC_CLKSOURCE__) MODIFY_REG(RCC->BDCR, RCC_BDCR_RTCSEL, (__RTC_CLKSOURCE__))
1521
1529#define __HAL_RCC_GET_RTC_SOURCE() (READ_BIT(RCC->BDCR, RCC_BDCR_RTCSEL))
1530
1534#define __HAL_RCC_RTC_ENABLE() (*(__IO uint32_t *) RCC_BDCR_RTCEN_BB = ENABLE)
1535
1539#define __HAL_RCC_RTC_DISABLE() (*(__IO uint32_t *) RCC_BDCR_RTCEN_BB = DISABLE)
1540
1545#define __HAL_RCC_BACKUPRESET_FORCE() (*(__IO uint32_t *) RCC_BDCR_BDRST_BB = ENABLE)
1546
1549#define __HAL_RCC_BACKUPRESET_RELEASE() (*(__IO uint32_t *) RCC_BDCR_BDRST_BB = DISABLE)
1550
1569#define __HAL_RCC_ENABLE_IT(__INTERRUPT__) (*(__IO uint8_t *) RCC_CIR_BYTE1_ADDRESS |= (__INTERRUPT__))
1570
1580#define __HAL_RCC_DISABLE_IT(__INTERRUPT__) (*(__IO uint8_t *) RCC_CIR_BYTE1_ADDRESS &= (uint8_t)(~(__INTERRUPT__)))
1581
1592#define __HAL_RCC_CLEAR_IT(__INTERRUPT__) (*(__IO uint8_t *) RCC_CIR_BYTE2_ADDRESS = (__INTERRUPT__))
1593
1605#define __HAL_RCC_GET_IT(__INTERRUPT__) ((RCC->CIR & (__INTERRUPT__)) == (__INTERRUPT__))
1606
1611#define __HAL_RCC_CLEAR_RESET_FLAGS() (*(__IO uint32_t *)RCC_CSR_RMVF_BB = ENABLE)
1612
1662#define __HAL_RCC_GET_FLAG(__FLAG__) (((((__FLAG__) >> 5U) == CR_REG_INDEX) ? RCC->CR : \
1663 (((__FLAG__) >> 5U) == BDCR_REG_INDEX)? RCC->BDCR : \
1664 (((__FLAG__) >> 5U) == CFGR_REG_INDEX)? RCC->CFGR : \
1665 RCC->CSR) & (1U << ((__FLAG__) & RCC_FLAG_MASK)))
1666
1675/* Include RCC HAL Extension module */
1676#include "stm32f3xx_hal_rcc_ex.h"
1677
1678/* Exported functions --------------------------------------------------------*/
1687/* Initialization and de-initialization functions ******************************/
1688HAL_StatusTypeDef HAL_RCC_DeInit(void);
1689HAL_StatusTypeDef HAL_RCC_OscConfig(RCC_OscInitTypeDef *RCC_OscInitStruct);
1690HAL_StatusTypeDef HAL_RCC_ClockConfig(RCC_ClkInitTypeDef *RCC_ClkInitStruct, uint32_t FLatency);
1691
1700/* Peripheral Control functions ************************************************/
1701void HAL_RCC_MCOConfig(uint32_t RCC_MCOx, uint32_t RCC_MCOSource, uint32_t RCC_MCODiv);
1702void HAL_RCC_EnableCSS(void);
1703/* CSS NMI IRQ handler */
1704void HAL_RCC_NMI_IRQHandler(void);
1705/* User Callbacks in non blocking mode (IT mode) */
1706void HAL_RCC_CSSCallback(void);
1707void HAL_RCC_DisableCSS(void);
1708uint32_t HAL_RCC_GetSysClockFreq(void);
1709uint32_t HAL_RCC_GetHCLKFreq(void);
1710uint32_t HAL_RCC_GetPCLK1Freq(void);
1711uint32_t HAL_RCC_GetPCLK2Freq(void);
1712void HAL_RCC_GetOscConfig(RCC_OscInitTypeDef *RCC_OscInitStruct);
1713void HAL_RCC_GetClockConfig(RCC_ClkInitTypeDef *RCC_ClkInitStruct, uint32_t *pFLatency);
1714
1731#ifdef __cplusplus
1732}
1733#endif
1734
1735#endif /* __STM32F3xx_HAL_RCC_H */
1736
1737
HAL_RCC_DeInit
HAL_StatusTypeDef HAL_RCC_DeInit(void)
HAL_RCC_OscConfig
HAL_StatusTypeDef HAL_RCC_OscConfig(RCC_OscInitTypeDef *RCC_OscInitStruct)
HAL_RCC_ClockConfig
HAL_StatusTypeDef HAL_RCC_ClockConfig(RCC_ClkInitTypeDef *RCC_ClkInitStruct, uint32_t FLatency)
HAL_RCC_NMI_IRQHandler
void HAL_RCC_NMI_IRQHandler(void)
HAL_RCC_GetHCLKFreq
uint32_t HAL_RCC_GetHCLKFreq(void)
HAL_RCC_GetSysClockFreq
uint32_t HAL_RCC_GetSysClockFreq(void)
HAL_RCC_MCOConfig
void HAL_RCC_MCOConfig(uint32_t RCC_MCOx, uint32_t RCC_MCOSource, uint32_t RCC_MCODiv)
HAL_RCC_CSSCallback
void HAL_RCC_CSSCallback(void)
HAL_RCC_EnableCSS
void HAL_RCC_EnableCSS(void)
HAL_RCC_GetPCLK1Freq
uint32_t HAL_RCC_GetPCLK1Freq(void)
HAL_RCC_GetPCLK2Freq
uint32_t HAL_RCC_GetPCLK2Freq(void)
HAL_RCC_GetClockConfig
void HAL_RCC_GetClockConfig(RCC_ClkInitTypeDef *RCC_ClkInitStruct, uint32_t *pFLatency)
HAL_RCC_DisableCSS
void HAL_RCC_DisableCSS(void)
HAL_RCC_GetOscConfig
void HAL_RCC_GetOscConfig(RCC_OscInitTypeDef *RCC_OscInitStruct)
stm32f3xx_hal_def.h
This file contains HAL common defines, enumeration, macros and structures definitions.
HAL_StatusTypeDef
HAL_StatusTypeDef
HAL Status structures definition
Definition: stm32f3xx_hal_def.h:39
stm32f3xx_hal_rcc_ex.h
Header file of RCC HAL Extension module.
RCC_ClkInitTypeDef
RCC System, AHB and APB busses clock configuration structure definition
Definition: stm32f3xx_hal_rcc.h:303
RCC_ClkInitTypeDef::APB1CLKDivider
uint32_t APB1CLKDivider
Definition: stm32f3xx_hal_rcc.h:313
RCC_ClkInitTypeDef::SYSCLKSource
uint32_t SYSCLKSource
Definition: stm32f3xx_hal_rcc.h:307
RCC_ClkInitTypeDef::ClockType
uint32_t ClockType
Definition: stm32f3xx_hal_rcc.h:304
RCC_ClkInitTypeDef::APB2CLKDivider
uint32_t APB2CLKDivider
Definition: stm32f3xx_hal_rcc.h:316
RCC_ClkInitTypeDef::AHBCLKDivider
uint32_t AHBCLKDivider
Definition: stm32f3xx_hal_rcc.h:310
RCC_OscInitTypeDef
RCC Internal/External Oscillator (HSE, HSI, LSE and LSI) configuration structure definition
Definition: stm32f3xx_hal_rcc.h:271
RCC_OscInitTypeDef::HSIState
uint32_t HSIState
Definition: stm32f3xx_hal_rcc.h:286
RCC_OscInitTypeDef::LSEState
uint32_t LSEState
Definition: stm32f3xx_hal_rcc.h:283
RCC_OscInitTypeDef::HSEState
uint32_t HSEState
Definition: stm32f3xx_hal_rcc.h:275
RCC_OscInitTypeDef::LSIState
uint32_t LSIState
Definition: stm32f3xx_hal_rcc.h:292
RCC_OscInitTypeDef::HSICalibrationValue
uint32_t HSICalibrationValue
Definition: stm32f3xx_hal_rcc.h:289
RCC_OscInitTypeDef::PLL
RCC_PLLInitTypeDef PLL
Definition: stm32f3xx_hal_rcc.h:295
RCC_OscInitTypeDef::OscillatorType
uint32_t OscillatorType
Definition: stm32f3xx_hal_rcc.h:272
RCC_PLLInitTypeDef
RCC PLL configuration structure definition
Definition: stm32f3xx_hal_rcc.h:250
RCC_PLLInitTypeDef::PLLMUL
uint32_t PLLMUL
Definition: stm32f3xx_hal_rcc.h:257
RCC_PLLInitTypeDef::PLLState
uint32_t PLLState
Definition: stm32f3xx_hal_rcc.h:251
RCC_PLLInitTypeDef::PLLSource
uint32_t PLLSource
Definition: stm32f3xx_hal_rcc.h:254