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#define | RCC_DBP_TIMEOUT_VALUE (100U) /* 100 ms */ |
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#define | RCC_LSE_TIMEOUT_VALUE LSE_STARTUP_TIMEOUT |
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#define | CLOCKSWITCH_TIMEOUT_VALUE (5000U) /* 5 s */ |
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#define | HSE_TIMEOUT_VALUE HSE_STARTUP_TIMEOUT |
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#define | HSI_TIMEOUT_VALUE (2U) /* 2 ms (minimum Tick + 1U) */ |
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#define | LSI_TIMEOUT_VALUE (2U) /* 2 ms (minimum Tick + 1U) */ |
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#define | PLL_TIMEOUT_VALUE (2U) /* 2 ms (minimum Tick + 1U) */ |
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#define | RCC_OFFSET (RCC_BASE - PERIPH_BASE) |
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#define | RCC_CR_OFFSET 0x00 |
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#define | RCC_CFGR_OFFSET 0x04 |
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#define | RCC_CIR_OFFSET 0x08 |
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#define | RCC_BDCR_OFFSET 0x20 |
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#define | RCC_CSR_OFFSET 0x24 |
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#define | RCC_CR_OFFSET_BB (RCC_OFFSET + RCC_CR_OFFSET) |
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#define | RCC_CFGR_OFFSET_BB (RCC_OFFSET + RCC_CFGR_OFFSET) |
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#define | RCC_CIR_OFFSET_BB (RCC_OFFSET + RCC_CIR_OFFSET) |
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#define | RCC_BDCR_OFFSET_BB (RCC_OFFSET + RCC_BDCR_OFFSET) |
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#define | RCC_CSR_OFFSET_BB (RCC_OFFSET + RCC_CSR_OFFSET) |
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#define | RCC_HSION_BIT_NUMBER POSITION_VAL(RCC_CR_HSION) |
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#define | RCC_CR_HSION_BB ((uint32_t)(PERIPH_BB_BASE + (RCC_CR_OFFSET_BB * 32U) + (RCC_HSION_BIT_NUMBER * 4U))) |
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#define | RCC_HSEON_BIT_NUMBER POSITION_VAL(RCC_CR_HSEON) |
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#define | RCC_CR_HSEON_BB ((uint32_t)(PERIPH_BB_BASE + (RCC_CR_OFFSET_BB * 32U) + (RCC_HSEON_BIT_NUMBER * 4U))) |
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#define | RCC_CSSON_BIT_NUMBER POSITION_VAL(RCC_CR_CSSON) |
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#define | RCC_CR_CSSON_BB ((uint32_t)(PERIPH_BB_BASE + (RCC_CR_OFFSET_BB * 32U) + (RCC_CSSON_BIT_NUMBER * 4U))) |
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#define | RCC_PLLON_BIT_NUMBER POSITION_VAL(RCC_CR_PLLON) |
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#define | RCC_CR_PLLON_BB ((uint32_t)(PERIPH_BB_BASE + (RCC_CR_OFFSET_BB * 32U) + (RCC_PLLON_BIT_NUMBER * 4U))) |
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#define | RCC_LSION_BIT_NUMBER POSITION_VAL(RCC_CSR_LSION) |
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#define | RCC_CSR_LSION_BB ((uint32_t)(PERIPH_BB_BASE + (RCC_CSR_OFFSET_BB * 32U) + (RCC_LSION_BIT_NUMBER * 4U))) |
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#define | RCC_RMVF_BIT_NUMBER POSITION_VAL(RCC_CSR_RMVF) |
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#define | RCC_CSR_RMVF_BB ((uint32_t)(PERIPH_BB_BASE + (RCC_CSR_OFFSET_BB * 32U) + (RCC_RMVF_BIT_NUMBER * 4U))) |
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#define | RCC_LSEON_BIT_NUMBER POSITION_VAL(RCC_BDCR_LSEON) |
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#define | RCC_BDCR_LSEON_BB ((uint32_t)(PERIPH_BB_BASE + (RCC_BDCR_OFFSET_BB * 32U) + (RCC_LSEON_BIT_NUMBER * 4U))) |
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#define | RCC_LSEBYP_BIT_NUMBER POSITION_VAL(RCC_BDCR_LSEBYP) |
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#define | RCC_BDCR_LSEBYP_BB ((uint32_t)(PERIPH_BB_BASE + (RCC_BDCR_OFFSET_BB * 32U) + (RCC_LSEBYP_BIT_NUMBER * 4U))) |
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#define | RCC_RTCEN_BIT_NUMBER POSITION_VAL(RCC_BDCR_RTCEN) |
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#define | RCC_BDCR_RTCEN_BB ((uint32_t)(PERIPH_BB_BASE + (RCC_BDCR_OFFSET_BB * 32U) + (RCC_RTCEN_BIT_NUMBER * 4U))) |
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#define | RCC_BDRST_BIT_NUMBER POSITION_VAL(RCC_BDCR_BDRST) |
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#define | RCC_BDCR_BDRST_BB ((uint32_t)(PERIPH_BB_BASE + (RCC_BDCR_OFFSET_BB * 32U) + (RCC_BDRST_BIT_NUMBER * 4U))) |
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#define | RCC_CR_BYTE2_ADDRESS ((uint32_t)(RCC_BASE + RCC_CR_OFFSET + 0x02U)) |
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#define | RCC_CIR_BYTE1_ADDRESS ((uint32_t)(RCC_BASE + RCC_CIR_OFFSET + 0x01U)) |
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#define | RCC_CIR_BYTE2_ADDRESS ((uint32_t)(RCC_BASE + RCC_CIR_OFFSET + 0x02U)) |
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#define | CR_REG_INDEX ((uint8_t)1U) |
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#define | BDCR_REG_INDEX ((uint8_t)2U) |
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#define | CSR_REG_INDEX ((uint8_t)3U) |
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#define | CFGR_REG_INDEX ((uint8_t)4U) |
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#define | RCC_FLAG_MASK ((uint8_t)0x1FU) |
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#define | IS_RCC_PLLSOURCE(__SOURCE__) |
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#define | IS_RCC_OSCILLATORTYPE(__OSCILLATOR__) |
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#define | IS_RCC_HSE(__HSE__) |
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#define | IS_RCC_LSE(__LSE__) |
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#define | IS_RCC_HSI(__HSI__) (((__HSI__) == RCC_HSI_OFF) || ((__HSI__) == RCC_HSI_ON)) |
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#define | IS_RCC_CALIBRATION_VALUE(__VALUE__) ((__VALUE__) <= 0x1FU) |
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#define | IS_RCC_LSI(__LSI__) (((__LSI__) == RCC_LSI_OFF) || ((__LSI__) == RCC_LSI_ON)) |
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#define | IS_RCC_PLL(__PLL__) |
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#define | IS_RCC_PLL_DIV(__DIV__) |
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#define | IS_RCC_PLL_MUL(__MUL__) |
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#define | IS_RCC_CLOCKTYPE(CLK) |
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#define | IS_RCC_SYSCLKSOURCE(__SOURCE__) |
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#define | IS_RCC_SYSCLKSOURCE_STATUS(__SOURCE__) |
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#define | IS_RCC_HCLK(__HCLK__) |
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#define | IS_RCC_PCLK(__PCLK__) |
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#define | IS_RCC_MCO(__MCO__) ((__MCO__) == RCC_MCO) |
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#define | IS_RCC_RTCCLKSOURCE(__SOURCE__) |
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#define | IS_RCC_I2C1CLKSOURCE(__SOURCE__) |
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#define | RCC_PLLSOURCE_HSE RCC_CFGR_PLLSRC_HSE_PREDIV |
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#define | RCC_OSCILLATORTYPE_NONE (0x00000000U) |
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#define | RCC_OSCILLATORTYPE_HSE (0x00000001U) |
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#define | RCC_OSCILLATORTYPE_HSI (0x00000002U) |
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#define | RCC_OSCILLATORTYPE_LSE (0x00000004U) |
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#define | RCC_OSCILLATORTYPE_LSI (0x00000008U) |
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#define | RCC_HSE_OFF (0x00000000U) |
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#define | RCC_HSE_ON RCC_CR_HSEON |
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#define | RCC_HSE_BYPASS ((uint32_t)(RCC_CR_HSEBYP | RCC_CR_HSEON)) |
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#define | RCC_LSE_OFF (0x00000000U) |
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#define | RCC_LSE_ON RCC_BDCR_LSEON |
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#define | RCC_LSE_BYPASS ((uint32_t)(RCC_BDCR_LSEBYP | RCC_BDCR_LSEON)) |
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#define | RCC_HSI_OFF (0x00000000U) |
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#define | RCC_HSI_ON RCC_CR_HSION |
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#define | RCC_HSICALIBRATION_DEFAULT (0x10U) /* Default HSI calibration trimming value */ |
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#define | RCC_LSI_OFF (0x00000000U) |
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#define | RCC_LSI_ON RCC_CSR_LSION |
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#define | RCC_PLL_NONE (0x00000000U) |
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#define | RCC_PLL_OFF (0x00000001U) |
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#define | RCC_PLL_ON (0x00000002U) |
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#define | RCC_CLOCKTYPE_SYSCLK (0x00000001U) |
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#define | RCC_CLOCKTYPE_HCLK (0x00000002U) |
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#define | RCC_CLOCKTYPE_PCLK1 (0x00000004U) |
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#define | RCC_CLOCKTYPE_PCLK2 (0x00000008U) |
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#define | RCC_SYSCLKSOURCE_HSI RCC_CFGR_SW_HSI |
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#define | RCC_SYSCLKSOURCE_HSE RCC_CFGR_SW_HSE |
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#define | RCC_SYSCLKSOURCE_PLLCLK RCC_CFGR_SW_PLL |
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#define | RCC_SYSCLKSOURCE_STATUS_HSI RCC_CFGR_SWS_HSI |
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#define | RCC_SYSCLKSOURCE_STATUS_HSE RCC_CFGR_SWS_HSE |
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#define | RCC_SYSCLKSOURCE_STATUS_PLLCLK RCC_CFGR_SWS_PLL |
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#define | RCC_SYSCLK_DIV1 RCC_CFGR_HPRE_DIV1 |
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#define | RCC_SYSCLK_DIV2 RCC_CFGR_HPRE_DIV2 |
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#define | RCC_SYSCLK_DIV4 RCC_CFGR_HPRE_DIV4 |
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#define | RCC_SYSCLK_DIV8 RCC_CFGR_HPRE_DIV8 |
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#define | RCC_SYSCLK_DIV16 RCC_CFGR_HPRE_DIV16 |
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#define | RCC_SYSCLK_DIV64 RCC_CFGR_HPRE_DIV64 |
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#define | RCC_SYSCLK_DIV128 RCC_CFGR_HPRE_DIV128 |
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#define | RCC_SYSCLK_DIV256 RCC_CFGR_HPRE_DIV256 |
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#define | RCC_SYSCLK_DIV512 RCC_CFGR_HPRE_DIV512 |
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#define | RCC_HCLK_DIV1 RCC_CFGR_PPRE1_DIV1 |
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#define | RCC_HCLK_DIV2 RCC_CFGR_PPRE1_DIV2 |
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#define | RCC_HCLK_DIV4 RCC_CFGR_PPRE1_DIV4 |
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#define | RCC_HCLK_DIV8 RCC_CFGR_PPRE1_DIV8 |
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#define | RCC_HCLK_DIV16 RCC_CFGR_PPRE1_DIV16 |
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#define | RCC_RTCCLKSOURCE_NO_CLK RCC_BDCR_RTCSEL_NOCLOCK |
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#define | RCC_RTCCLKSOURCE_LSE RCC_BDCR_RTCSEL_LSE |
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#define | RCC_RTCCLKSOURCE_LSI RCC_BDCR_RTCSEL_LSI |
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#define | RCC_RTCCLKSOURCE_HSE_DIV32 RCC_BDCR_RTCSEL_HSE |
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#define | RCC_PLL_MUL2 RCC_CFGR_PLLMUL2 |
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#define | RCC_PLL_MUL3 RCC_CFGR_PLLMUL3 |
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#define | RCC_PLL_MUL4 RCC_CFGR_PLLMUL4 |
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#define | RCC_PLL_MUL5 RCC_CFGR_PLLMUL5 |
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#define | RCC_PLL_MUL6 RCC_CFGR_PLLMUL6 |
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#define | RCC_PLL_MUL7 RCC_CFGR_PLLMUL7 |
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#define | RCC_PLL_MUL8 RCC_CFGR_PLLMUL8 |
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#define | RCC_PLL_MUL9 RCC_CFGR_PLLMUL9 |
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#define | RCC_PLL_MUL10 RCC_CFGR_PLLMUL10 |
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#define | RCC_PLL_MUL11 RCC_CFGR_PLLMUL11 |
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#define | RCC_PLL_MUL12 RCC_CFGR_PLLMUL12 |
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#define | RCC_PLL_MUL13 RCC_CFGR_PLLMUL13 |
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#define | RCC_PLL_MUL14 RCC_CFGR_PLLMUL14 |
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#define | RCC_PLL_MUL15 RCC_CFGR_PLLMUL15 |
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#define | RCC_PLL_MUL16 RCC_CFGR_PLLMUL16 |
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#define | RCC_I2C1CLKSOURCE_HSI RCC_CFGR3_I2C1SW_HSI |
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#define | RCC_I2C1CLKSOURCE_SYSCLK RCC_CFGR3_I2C1SW_SYSCLK |
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#define | RCC_MCO1 (0x00000000U) |
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#define | RCC_MCO RCC_MCO1 |
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#define | RCC_IT_LSIRDY ((uint8_t)RCC_CIR_LSIRDYF) |
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#define | RCC_IT_LSERDY ((uint8_t)RCC_CIR_LSERDYF) |
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#define | RCC_IT_HSIRDY ((uint8_t)RCC_CIR_HSIRDYF) |
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#define | RCC_IT_HSERDY ((uint8_t)RCC_CIR_HSERDYF) |
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#define | RCC_IT_PLLRDY ((uint8_t)RCC_CIR_PLLRDYF) |
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#define | RCC_IT_CSS ((uint8_t)RCC_CIR_CSSF) |
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#define | RCC_FLAG_HSIRDY ((uint8_t)((CR_REG_INDEX << 5U) | POSITION_VAL(RCC_CR_HSIRDY))) |
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#define | RCC_FLAG_HSERDY ((uint8_t)((CR_REG_INDEX << 5U) | POSITION_VAL(RCC_CR_HSERDY))) |
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#define | RCC_FLAG_PLLRDY ((uint8_t)((CR_REG_INDEX << 5U) | POSITION_VAL(RCC_CR_PLLRDY))) |
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#define | RCC_FLAG_LSIRDY ((uint8_t)((CSR_REG_INDEX << 5U) | POSITION_VAL(RCC_CSR_LSIRDY))) |
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#define | RCC_FLAG_OBLRST ((uint8_t)((CSR_REG_INDEX << 5U) | POSITION_VAL(RCC_CSR_OBLRSTF))) |
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#define | RCC_FLAG_PINRST ((uint8_t)((CSR_REG_INDEX << 5U) | POSITION_VAL(RCC_CSR_PINRSTF))) |
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#define | RCC_FLAG_PORRST ((uint8_t)((CSR_REG_INDEX << 5U) | POSITION_VAL(RCC_CSR_PORRSTF))) |
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#define | RCC_FLAG_SFTRST ((uint8_t)((CSR_REG_INDEX << 5U) | POSITION_VAL(RCC_CSR_SFTRSTF))) |
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#define | RCC_FLAG_IWDGRST ((uint8_t)((CSR_REG_INDEX << 5U) | POSITION_VAL(RCC_CSR_IWDGRSTF))) |
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#define | RCC_FLAG_WWDGRST ((uint8_t)((CSR_REG_INDEX << 5U) | POSITION_VAL(RCC_CSR_WWDGRSTF))) |
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#define | RCC_FLAG_LPWRRST ((uint8_t)((CSR_REG_INDEX << 5U) | POSITION_VAL(RCC_CSR_LPWRRSTF))) |
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#define | RCC_FLAG_LSERDY ((uint8_t)((BDCR_REG_INDEX << 5U) | POSITION_VAL(RCC_BDCR_LSERDY))) |
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#define | __HAL_RCC_GPIOA_CLK_ENABLE() |
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#define | __HAL_RCC_GPIOB_CLK_ENABLE() |
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#define | __HAL_RCC_GPIOC_CLK_ENABLE() |
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#define | __HAL_RCC_GPIOD_CLK_ENABLE() |
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#define | __HAL_RCC_GPIOF_CLK_ENABLE() |
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#define | __HAL_RCC_CRC_CLK_ENABLE() |
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#define | __HAL_RCC_DMA1_CLK_ENABLE() |
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#define | __HAL_RCC_SRAM_CLK_ENABLE() |
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#define | __HAL_RCC_FLITF_CLK_ENABLE() |
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#define | __HAL_RCC_TSC_CLK_ENABLE() |
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#define | __HAL_RCC_GPIOA_CLK_DISABLE() (RCC->AHBENR &= ~(RCC_AHBENR_GPIOAEN)) |
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#define | __HAL_RCC_GPIOB_CLK_DISABLE() (RCC->AHBENR &= ~(RCC_AHBENR_GPIOBEN)) |
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#define | __HAL_RCC_GPIOC_CLK_DISABLE() (RCC->AHBENR &= ~(RCC_AHBENR_GPIOCEN)) |
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#define | __HAL_RCC_GPIOD_CLK_DISABLE() (RCC->AHBENR &= ~(RCC_AHBENR_GPIODEN)) |
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#define | __HAL_RCC_GPIOF_CLK_DISABLE() (RCC->AHBENR &= ~(RCC_AHBENR_GPIOFEN)) |
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#define | __HAL_RCC_CRC_CLK_DISABLE() (RCC->AHBENR &= ~(RCC_AHBENR_CRCEN)) |
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#define | __HAL_RCC_DMA1_CLK_DISABLE() (RCC->AHBENR &= ~(RCC_AHBENR_DMA1EN)) |
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#define | __HAL_RCC_SRAM_CLK_DISABLE() (RCC->AHBENR &= ~(RCC_AHBENR_SRAMEN)) |
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#define | __HAL_RCC_FLITF_CLK_DISABLE() (RCC->AHBENR &= ~(RCC_AHBENR_FLITFEN)) |
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#define | __HAL_RCC_TSC_CLK_DISABLE() (RCC->AHBENR &= ~(RCC_AHBENR_TSCEN)) |
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#define | __HAL_RCC_TIM2_CLK_ENABLE() |
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#define | __HAL_RCC_TIM6_CLK_ENABLE() |
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#define | __HAL_RCC_WWDG_CLK_ENABLE() |
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#define | __HAL_RCC_USART2_CLK_ENABLE() |
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#define | __HAL_RCC_USART3_CLK_ENABLE() |
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#define | __HAL_RCC_I2C1_CLK_ENABLE() |
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#define | __HAL_RCC_PWR_CLK_ENABLE() |
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#define | __HAL_RCC_DAC1_CLK_ENABLE() |
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#define | __HAL_RCC_TIM2_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM2EN)) |
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#define | __HAL_RCC_TIM6_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM6EN)) |
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#define | __HAL_RCC_WWDG_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_WWDGEN)) |
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#define | __HAL_RCC_USART2_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_USART2EN)) |
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#define | __HAL_RCC_USART3_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_USART3EN)) |
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#define | __HAL_RCC_I2C1_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_I2C1EN)) |
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#define | __HAL_RCC_PWR_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_PWREN)) |
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#define | __HAL_RCC_DAC1_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_DAC1EN)) |
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#define | __HAL_RCC_SYSCFG_CLK_ENABLE() |
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#define | __HAL_RCC_TIM15_CLK_ENABLE() |
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#define | __HAL_RCC_TIM16_CLK_ENABLE() |
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#define | __HAL_RCC_TIM17_CLK_ENABLE() |
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#define | __HAL_RCC_USART1_CLK_ENABLE() |
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#define | __HAL_RCC_SYSCFG_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_SYSCFGEN)) |
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#define | __HAL_RCC_TIM15_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_TIM15EN)) |
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#define | __HAL_RCC_TIM16_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_TIM16EN)) |
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#define | __HAL_RCC_TIM17_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_TIM17EN)) |
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#define | __HAL_RCC_USART1_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_USART1EN)) |
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#define | __HAL_RCC_GPIOA_IS_CLK_ENABLED() ((RCC->AHBENR & (RCC_AHBENR_GPIOAEN)) != RESET) |
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#define | __HAL_RCC_GPIOB_IS_CLK_ENABLED() ((RCC->AHBENR & (RCC_AHBENR_GPIOBEN)) != RESET) |
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#define | __HAL_RCC_GPIOC_IS_CLK_ENABLED() ((RCC->AHBENR & (RCC_AHBENR_GPIOCEN)) != RESET) |
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#define | __HAL_RCC_GPIOD_IS_CLK_ENABLED() ((RCC->AHBENR & (RCC_AHBENR_GPIODEN)) != RESET) |
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#define | __HAL_RCC_GPIOF_IS_CLK_ENABLED() ((RCC->AHBENR & (RCC_AHBENR_GPIOFEN)) != RESET) |
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#define | __HAL_RCC_CRC_IS_CLK_ENABLED() ((RCC->AHBENR & (RCC_AHBENR_CRCEN)) != RESET) |
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#define | __HAL_RCC_DMA1_IS_CLK_ENABLED() ((RCC->AHBENR & (RCC_AHBENR_DMA1EN)) != RESET) |
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#define | __HAL_RCC_SRAM_IS_CLK_ENABLED() ((RCC->AHBENR & (RCC_AHBENR_SRAMEN)) != RESET) |
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#define | __HAL_RCC_FLITF_IS_CLK_ENABLED() ((RCC->AHBENR & (RCC_AHBENR_FLITFEN)) != RESET) |
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#define | __HAL_RCC_TSC_IS_CLK_ENABLED() ((RCC->AHBENR & (RCC_AHBENR_TSCEN)) != RESET) |
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#define | __HAL_RCC_GPIOA_IS_CLK_DISABLED() ((RCC->AHBENR & (RCC_AHBENR_GPIOAEN)) == RESET) |
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#define | __HAL_RCC_GPIOB_IS_CLK_DISABLED() ((RCC->AHBENR & (RCC_AHBENR_GPIOBEN)) == RESET) |
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#define | __HAL_RCC_GPIOC_IS_CLK_DISABLED() ((RCC->AHBENR & (RCC_AHBENR_GPIOCEN)) == RESET) |
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#define | __HAL_RCC_GPIOD_IS_CLK_DISABLED() ((RCC->AHBENR & (RCC_AHBENR_GPIODEN)) == RESET) |
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#define | __HAL_RCC_GPIOF_IS_CLK_DISABLED() ((RCC->AHBENR & (RCC_AHBENR_GPIOFEN)) == RESET) |
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#define | __HAL_RCC_CRC_IS_CLK_DISABLED() ((RCC->AHBENR & (RCC_AHBENR_CRCEN)) == RESET) |
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#define | __HAL_RCC_DMA1_IS_CLK_DISABLED() ((RCC->AHBENR & (RCC_AHBENR_DMA1EN)) == RESET) |
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#define | __HAL_RCC_SRAM_IS_CLK_DISABLED() ((RCC->AHBENR & (RCC_AHBENR_SRAMEN)) == RESET) |
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#define | __HAL_RCC_FLITF_IS_CLK_DISABLED() ((RCC->AHBENR & (RCC_AHBENR_FLITFEN)) == RESET) |
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#define | __HAL_RCC_TSC_IS_CLK_DISABLED() ((RCC->AHBENR & (RCC_AHBENR_TSCEN)) == RESET) |
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#define | __HAL_RCC_TIM2_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM2EN)) != RESET) |
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#define | __HAL_RCC_TIM6_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM6EN)) != RESET) |
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#define | __HAL_RCC_WWDG_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_WWDGEN)) != RESET) |
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#define | __HAL_RCC_USART2_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_USART2EN)) != RESET) |
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#define | __HAL_RCC_USART3_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_USART3EN)) != RESET) |
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#define | __HAL_RCC_I2C1_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_I2C1EN)) != RESET) |
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#define | __HAL_RCC_PWR_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_PWREN)) != RESET) |
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#define | __HAL_RCC_DAC1_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_DAC1EN)) != RESET) |
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#define | __HAL_RCC_TIM2_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM2EN)) == RESET) |
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#define | __HAL_RCC_TIM6_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM6EN)) == RESET) |
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#define | __HAL_RCC_WWDG_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_WWDGEN)) == RESET) |
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#define | __HAL_RCC_USART2_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_USART2EN)) == RESET) |
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#define | __HAL_RCC_USART3_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_USART3EN)) == RESET) |
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#define | __HAL_RCC_I2C1_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_I2C1EN)) == RESET) |
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#define | __HAL_RCC_PWR_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_PWREN)) == RESET) |
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#define | __HAL_RCC_DAC1_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_DAC1EN)) == RESET) |
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#define | __HAL_RCC_SYSCFG_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_SYSCFGEN)) != RESET) |
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#define | __HAL_RCC_TIM15_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_TIM15EN)) != RESET) |
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#define | __HAL_RCC_TIM16_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_TIM16EN)) != RESET) |
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#define | __HAL_RCC_TIM17_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_TIM17EN)) != RESET) |
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#define | __HAL_RCC_USART1_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_USART1EN)) != RESET) |
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#define | __HAL_RCC_SYSCFG_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_SYSCFGEN)) == RESET) |
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#define | __HAL_RCC_TIM15_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_TIM15EN)) == RESET) |
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#define | __HAL_RCC_TIM16_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_TIM16EN)) == RESET) |
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#define | __HAL_RCC_TIM17_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_TIM17EN)) == RESET) |
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#define | __HAL_RCC_USART1_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_USART1EN)) == RESET) |
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#define | __HAL_RCC_AHB_FORCE_RESET() (RCC->AHBRSTR = 0xFFFFFFFFU) |
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#define | __HAL_RCC_GPIOA_FORCE_RESET() (RCC->AHBRSTR |= (RCC_AHBRSTR_GPIOARST)) |
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#define | __HAL_RCC_GPIOB_FORCE_RESET() (RCC->AHBRSTR |= (RCC_AHBRSTR_GPIOBRST)) |
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#define | __HAL_RCC_GPIOC_FORCE_RESET() (RCC->AHBRSTR |= (RCC_AHBRSTR_GPIOCRST)) |
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#define | __HAL_RCC_GPIOD_FORCE_RESET() (RCC->AHBRSTR |= (RCC_AHBRSTR_GPIODRST)) |
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#define | __HAL_RCC_GPIOF_FORCE_RESET() (RCC->AHBRSTR |= (RCC_AHBRSTR_GPIOFRST)) |
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#define | __HAL_RCC_TSC_FORCE_RESET() (RCC->AHBRSTR |= (RCC_AHBRSTR_TSCRST)) |
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#define | __HAL_RCC_AHB_RELEASE_RESET() (RCC->AHBRSTR = 0x00000000U) |
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#define | __HAL_RCC_GPIOA_RELEASE_RESET() (RCC->AHBRSTR &= ~(RCC_AHBRSTR_GPIOARST)) |
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#define | __HAL_RCC_GPIOB_RELEASE_RESET() (RCC->AHBRSTR &= ~(RCC_AHBRSTR_GPIOBRST)) |
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#define | __HAL_RCC_GPIOC_RELEASE_RESET() (RCC->AHBRSTR &= ~(RCC_AHBRSTR_GPIOCRST)) |
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#define | __HAL_RCC_GPIOD_RELEASE_RESET() (RCC->AHBRSTR &= ~(RCC_AHBRSTR_GPIODRST)) |
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#define | __HAL_RCC_GPIOF_RELEASE_RESET() (RCC->AHBRSTR &= ~(RCC_AHBRSTR_GPIOFRST)) |
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#define | __HAL_RCC_TSC_RELEASE_RESET() (RCC->AHBRSTR &= ~(RCC_AHBRSTR_TSCRST)) |
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#define | __HAL_RCC_APB1_FORCE_RESET() (RCC->APB1RSTR = 0xFFFFFFFFU) |
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#define | __HAL_RCC_TIM2_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_TIM2RST)) |
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#define | __HAL_RCC_TIM6_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_TIM6RST)) |
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#define | __HAL_RCC_WWDG_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_WWDGRST)) |
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#define | __HAL_RCC_USART2_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_USART2RST)) |
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#define | __HAL_RCC_USART3_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_USART3RST)) |
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#define | __HAL_RCC_I2C1_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_I2C1RST)) |
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#define | __HAL_RCC_PWR_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_PWRRST)) |
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#define | __HAL_RCC_DAC1_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_DAC1RST)) |
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#define | __HAL_RCC_APB1_RELEASE_RESET() (RCC->APB1RSTR = 0x00000000U) |
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#define | __HAL_RCC_TIM2_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM2RST)) |
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#define | __HAL_RCC_TIM6_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM6RST)) |
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#define | __HAL_RCC_WWDG_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_WWDGRST)) |
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#define | __HAL_RCC_USART2_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_USART2RST)) |
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#define | __HAL_RCC_USART3_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_USART3RST)) |
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#define | __HAL_RCC_I2C1_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_I2C1RST)) |
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#define | __HAL_RCC_PWR_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_PWRRST)) |
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#define | __HAL_RCC_DAC1_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_DAC1RST)) |
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#define | __HAL_RCC_APB2_FORCE_RESET() (RCC->APB2RSTR = 0xFFFFFFFFU) |
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#define | __HAL_RCC_SYSCFG_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_SYSCFGRST)) |
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#define | __HAL_RCC_TIM15_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_TIM15RST)) |
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#define | __HAL_RCC_TIM16_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_TIM16RST)) |
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#define | __HAL_RCC_TIM17_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_TIM17RST)) |
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#define | __HAL_RCC_USART1_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_USART1RST)) |
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#define | __HAL_RCC_APB2_RELEASE_RESET() (RCC->APB2RSTR = 0x00000000U) |
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#define | __HAL_RCC_SYSCFG_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_SYSCFGRST)) |
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#define | __HAL_RCC_TIM15_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_TIM15RST)) |
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#define | __HAL_RCC_TIM16_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_TIM16RST)) |
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#define | __HAL_RCC_TIM17_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_TIM17RST)) |
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#define | __HAL_RCC_USART1_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_USART1RST)) |
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#define | __HAL_RCC_HSI_ENABLE() (*(__IO uint32_t *) RCC_CR_HSION_BB = ENABLE) |
| Macros to enable or disable the Internal High Speed oscillator (HSI).
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#define | __HAL_RCC_HSI_DISABLE() (*(__IO uint32_t *) RCC_CR_HSION_BB = DISABLE) |
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#define | __HAL_RCC_HSI_CALIBRATIONVALUE_ADJUST(_HSICALIBRATIONVALUE_) (MODIFY_REG(RCC->CR, RCC_CR_HSITRIM, (uint32_t)(_HSICALIBRATIONVALUE_) << POSITION_VAL(RCC_CR_HSITRIM))) |
| Macro to adjust the Internal High Speed oscillator (HSI) calibration value.
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#define | __HAL_RCC_LSI_ENABLE() (*(__IO uint32_t *) RCC_CSR_LSION_BB = ENABLE) |
| Macro to enable the Internal Low Speed oscillator (LSI).
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#define | __HAL_RCC_LSI_DISABLE() (*(__IO uint32_t *) RCC_CSR_LSION_BB = DISABLE) |
| Macro to disable the Internal Low Speed oscillator (LSI).
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#define | __HAL_RCC_HSE_CONFIG(__STATE__) |
| Macro to configure the External High Speed oscillator (HSE).
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#define | __HAL_RCC_LSE_CONFIG(__STATE__) |
| Macro to configure the External Low Speed oscillator (LSE).
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#define | __HAL_RCC_USART1_CONFIG(__USART1CLKSOURCE__) MODIFY_REG(RCC->CFGR3, RCC_CFGR3_USART1SW, (uint32_t)(__USART1CLKSOURCE__)) |
| Macro to configure the USART1 clock (USART1CLK).
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#define | __HAL_RCC_GET_USART1_SOURCE() ((uint32_t)(READ_BIT(RCC->CFGR3, RCC_CFGR3_USART1SW))) |
| Macro to get the USART1 clock source.
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#define | __HAL_RCC_I2C1_CONFIG(__I2C1CLKSOURCE__) MODIFY_REG(RCC->CFGR3, RCC_CFGR3_I2C1SW, (uint32_t)(__I2C1CLKSOURCE__)) |
| Macro to configure the I2C1 clock (I2C1CLK).
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#define | __HAL_RCC_GET_I2C1_SOURCE() ((uint32_t)(READ_BIT(RCC->CFGR3, RCC_CFGR3_I2C1SW))) |
| Macro to get the I2C1 clock source.
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#define | __HAL_RCC_PLL_ENABLE() (*(__IO uint32_t *) RCC_CR_PLLON_BB = ENABLE) |
| Macro to enable the main PLL.
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#define | __HAL_RCC_PLL_DISABLE() (*(__IO uint32_t *) RCC_CR_PLLON_BB = DISABLE) |
| Macro to disable the main PLL.
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#define | __HAL_RCC_GET_PLL_OSCSOURCE() ((uint32_t)(READ_BIT(RCC->CFGR, RCC_CFGR_PLLSRC))) |
| Get oscillator clock selected as PLL input clock.
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#define | __HAL_RCC_SYSCLK_CONFIG(__SYSCLKSOURCE__) MODIFY_REG(RCC->CFGR, RCC_CFGR_SW, (__SYSCLKSOURCE__)) |
| Macro to configure the system clock source.
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#define | __HAL_RCC_GET_SYSCLK_SOURCE() ((uint32_t)(READ_BIT(RCC->CFGR,RCC_CFGR_SWS))) |
| Macro to get the clock source used as system clock.
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#define | __HAL_RCC_MCO1_CONFIG(__MCOCLKSOURCE__, __MCODIV__) MODIFY_REG(RCC->CFGR, RCC_CFGR_MCO, (__MCOCLKSOURCE__)) |
| Macro to configure the MCO clock.
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#define | __HAL_RCC_RTC_CONFIG(__RTC_CLKSOURCE__) MODIFY_REG(RCC->BDCR, RCC_BDCR_RTCSEL, (__RTC_CLKSOURCE__)) |
| Macro to configure the RTC clock (RTCCLK).
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#define | __HAL_RCC_GET_RTC_SOURCE() (READ_BIT(RCC->BDCR, RCC_BDCR_RTCSEL)) |
| Macro to get the RTC clock source.
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#define | __HAL_RCC_RTC_ENABLE() (*(__IO uint32_t *) RCC_BDCR_RTCEN_BB = ENABLE) |
| Macro to enable the the RTC clock.
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#define | __HAL_RCC_RTC_DISABLE() (*(__IO uint32_t *) RCC_BDCR_RTCEN_BB = DISABLE) |
| Macro to disable the the RTC clock.
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#define | __HAL_RCC_BACKUPRESET_FORCE() (*(__IO uint32_t *) RCC_BDCR_BDRST_BB = ENABLE) |
| Macro to force the Backup domain reset.
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#define | __HAL_RCC_BACKUPRESET_RELEASE() (*(__IO uint32_t *) RCC_BDCR_BDRST_BB = DISABLE) |
| Macros to release the Backup domain reset.
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#define | __HAL_RCC_ENABLE_IT(__INTERRUPT__) (*(__IO uint8_t *) RCC_CIR_BYTE1_ADDRESS |= (__INTERRUPT__)) |
| Enable RCC interrupt.
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#define | __HAL_RCC_DISABLE_IT(__INTERRUPT__) (*(__IO uint8_t *) RCC_CIR_BYTE1_ADDRESS &= (uint8_t)(~(__INTERRUPT__))) |
| Disable RCC interrupt.
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#define | __HAL_RCC_CLEAR_IT(__INTERRUPT__) (*(__IO uint8_t *) RCC_CIR_BYTE2_ADDRESS = (__INTERRUPT__)) |
| Clear the RCC's interrupt pending bits.
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#define | __HAL_RCC_GET_IT(__INTERRUPT__) ((RCC->CIR & (__INTERRUPT__)) == (__INTERRUPT__)) |
| Check the RCC's interrupt has occurred or not.
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#define | __HAL_RCC_CLEAR_RESET_FLAGS() (*(__IO uint32_t *)RCC_CSR_RMVF_BB = ENABLE) |
| Set RMVF bit to clear the reset flags.
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#define | __HAL_RCC_GET_FLAG(__FLAG__) |
| Check RCC flag is set or not.
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Header file of RCC HAL module.
- Author
- MCD Application Team
- Attention
Copyright (c) 2016 STMicroelectronics. All rights reserved.
This software is licensed under terms that can be found in the LICENSE file in the root directory of this software component. If no LICENSE file comes with this software, it is provided AS-IS.